On Mon, 10 Feb 2025 18:28:16 -0500, Alex Deucher wrote:
> Does the attached patch fix it?
Yep, it prints a few more lines and shuts down now.
Thanks!
[ 53.525125] cstate: 1 pstate: 1 nbpstate: 1 sync: 0 dispclk: 0
[ 53.525125] sclk: 0 sclk_sleep: 12225 yclk: 2668000
blackout_recovery_time_u
Am 06.02.25 um 22:07 schrieb Harish Kasiviswanathan:
SDMA writes has to probe invalidate RW lines. Set snoop bit in mmhub for
this to happen.
v2: Missed a few mmhub_v9_4. Added now.
v3: Calculate hub offset once since it doesn't change inside the loop
Modified function names based on review
[AMD Official Use Only - AMD Internal Distribution Only]
Please feel free to add: Reviewed-by and Test-by: "jesse.zh...@amd.com" ,
-Original Message-
From: Ma, Le
Sent: Tuesday, February 11, 2025 2:40 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Lazar, Lijo ;
Zhang, Jesse(J
Add the trap irq processing for page queue of sdma442
Signed-off-by: Le Ma
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
index 5e0066cd6c51..14acc3b822ec 100
The seq64 VM cache policy should be set to UC (Uncached) to
match with userqueue fence address kernel mapped memory's
cache settings.
Signed-off-by: Arunpravin Paneer Selvam
---
drivers/gpu/drm/amd/amdgpu/amdgpu_seq64.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/dr
From: "jesse.zh...@amd.com"
This commit introduces several improvements to the SDMA reset logic:
1. Added `cached_rptr` to the `amdgpu_ring` structure to store the read pointer
before a reset, ensuring proper state restoration after reset.
2. Introduced `gfx_guilty` and `page_guilty` flags i
From: "jesse.zh...@amd.com"
This commit introduces a caller parameter to the amdgpu_sdma_reset_instance
function to differentiate
between reset requests originating from the KGD and KFD.
This change ensures proper synchronization between KGD and KFD during SDMA
resets.
If the caller is KFD, th
From: "jesse.zh...@amd.com"
This patch refactors the SDMA reset functionality in the `sdma_v4_4_2` driver
to improve modularity and support shared usage between AMDGPU and KFD. The
changes include:
1. **Refactored SDMA Reset Logic**:
- Split the `sdma_v4_4_2_reset_queue` function into two sep
From: "jesse.zh...@amd.com"
This patch introduces shared SDMA reset functionality between AMDGPU and KFD.
The implementation includes the following key changes:
1. Added `amdgpu_sdma_reset_queue`:
- Resets a specific SDMA queue by instance ID.
- Invokes registered pre-reset and post-reset
Hi Christian,
On 2/11/2025 12:54 AM, Christian König wrote:
Am 10.02.25 um 15:25 schrieb Sathishkumar S:
Add ring reset function callback for JPEG4_0_3 to
recover from job timeouts without a full gpu reset.
V2:
- sched->ready flag shouldn't be modified by back-ends (Christian)
- use drm_s
Hi Christian,
On 2/11/2025 12:52 AM, Christian König wrote:
Am 10.02.25 um 15:25 schrieb Sathishkumar S:
Add helper functions to handle per-instance and per-core
initialization and deinitialization in JPEG4_0_3.
Signed-off-by: Sathishkumar S
---
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 1
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Yang Wang
Best Regards,
Kevin
-Original Message-
From: amd-gfx On Behalf Of Asad Kamal
Sent: Monday, February 10, 2025 16:02
To: amd-gfx@lists.freedesktop.org; Lazar, Lijo
Cc: Ma, Le ; Zhang, Hawking ; Zhang,
Morri
The VCN and UVD helpers were split in
commit ff69bba05f08 ("drm/amd/pm: add inst to dpm_set_powergating_by_smu")
However, this happened in parallel to the vcn 5.0.1
development so it was missed there.
Fixes: 346492f30ce3 ("drm/amdgpu: Add VCN_5_0_1 support")
Signed-off-by: Alex Deucher
Cc: Sonny
[AMD Official Use Only - AMD Internal Distribution Only]
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Kamal, Asad
Sent: Monday, February 10, 2025 16:02
To: amd-gfx@lists.freedesktop.org; Lazar, Lijo
Cc: Ma, Le ; Zhang, Hawking ; Zhang,
Morris ; Kamal, Asad ; De
From: Alex Hung
[ Upstream commit 8adbb2a98b00926315fd513b5fe2596b5716b82d ]
[WHAT & HOW]
hpo_stream_to_link_encoder_mapping has size MAX_HPO_DP2_ENCODERS(=4),
but location can have size up to 6. As a result, it is necessary to
check location against MAX_HPO_DP2_ENCODERS.
Similiarly, disp_cfg_s
[AMD Official Use Only - AMD Internal Distribution Only]
Series is
Reviewed-by: Hawking Zhang
Regards,
Hawking
-Original Message-
From: Lazar, Lijo
Sent: Monday, February 10, 2025 15:01
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Deucher, Alexander
; Kim, Jonathan
Subject:
[AMD Official Use Only - AMD Internal Distribution Only]
Why only free the mem when unified mes is enabled , I remembered that
set_hw_resource_1 will also be called in none-unified mes mode .
Another thing is eventually we probably should allocate total 129 pages the
same as GFX11 (128 for h
From: Tom Chung
[ Upstream commit f245b400a223a71d6d5f4c72a2cb9b573a7fc2b6 ]
This reverts commit
a2b5a9956269 ("drm/amd/display: Use HW lock mgr for PSR1")
Because it may cause system hang while connect with two edp panel.
Acked-by: Wayne Lin
Signed-off-by: Tom Chung
Signed-off-by: Alex Deuc
From: Tom Chung
[ Upstream commit f245b400a223a71d6d5f4c72a2cb9b573a7fc2b6 ]
This reverts commit
a2b5a9956269 ("drm/amd/display: Use HW lock mgr for PSR1")
Because it may cause system hang while connect with two edp panel.
Acked-by: Wayne Lin
Signed-off-by: Tom Chung
Signed-off-by: Alex Deuc
From: Tom Chung
[ Upstream commit f245b400a223a71d6d5f4c72a2cb9b573a7fc2b6 ]
This reverts commit
a2b5a9956269 ("drm/amd/display: Use HW lock mgr for PSR1")
Because it may cause system hang while connect with two edp panel.
Acked-by: Wayne Lin
Signed-off-by: Tom Chung
Signed-off-by: Alex Deuc
From: Alex Hung
[ Upstream commit 8adbb2a98b00926315fd513b5fe2596b5716b82d ]
[WHAT & HOW]
hpo_stream_to_link_encoder_mapping has size MAX_HPO_DP2_ENCODERS(=4),
but location can have size up to 6. As a result, it is necessary to
check location against MAX_HPO_DP2_ENCODERS.
Similiarly, disp_cfg_s
From: Tom Chung
[ Upstream commit f245b400a223a71d6d5f4c72a2cb9b573a7fc2b6 ]
This reverts commit
a2b5a9956269 ("drm/amd/display: Use HW lock mgr for PSR1")
Because it may cause system hang while connect with two edp panel.
Acked-by: Wayne Lin
Signed-off-by: Tom Chung
Signed-off-by: Alex Deuc
[AMD Official Use Only - AMD Internal Distribution Only]
Looks good to me. You can can add
Reviewed by: Shaoyun.liu
-Original Message-
From: Deucher, Alexander
Sent: Monday, February 10, 2025 4:19 PM
To: amd-gfx@lists.freedesktop.org
Cc: SHANMUGAM, SRINIVASAN ; cao, lin
; Chen, JingW
Simplify the driver logic. We support multiple instances
now so reflect that in the driver state.
Fixes: ff69bba05f08 ("drm/amd/pm: add inst to dpm_set_powergating_by_smu")
Signed-off-by: Alex Deucher
Cc: Boyuan Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 9 ++---
drivers/gpu/d
UVD and VCN were split into separate dpm helpers in commit
ff69bba05f08 ("drm/amd/pm: add inst to dpm_set_powergating_by_smu")
but the check at the top was still included UVD from an earlier
version of the patch. Fix the check.
Fixes: ff69bba05f08 ("drm/amd/pm: add inst to dpm_set_powergating_by_
On Mon, Feb 10, 2025 at 6:03 PM Michał Pecio wrote:
>
> Hi,
>
> I have a machine with this APU:
> AMD PRO A10-8770 R7, 10 COMPUTE CORES 4C+6G
>
> 6.13 was OK, with 6.14-rc2 it hangs on shutdown after the display
> turns off.
>
> git-bisect says:
> # first bad commit: [ff69bba05f085cd6d4277c27ac760
Hi,
I have a machine with this APU:
AMD PRO A10-8770 R7, 10 COMPUTE CORES 4C+6G
6.13 was OK, with 6.14-rc2 it hangs on shutdown after the display
turns off.
git-bisect says:
# first bad commit: [ff69bba05f085cd6d4277c27ac7600160167b384] drm/amd/pm: add
inst to dpm_set_powergating_by_smu
The pr
Hi,
On 2024-12-16 12:34:46+0100, Thomas Weißschuh wrote:
> The sysfs core now allows instances of 'struct bin_attribute' to be
> moved into read-only memory. Make use of that to protect them against
> accidental or malicious modifications.
Can anybody pick up these patches?
Except for lima they a
On 2/10/25 15:18, Mario Limonciello wrote:
On 2/9/2025 16:50, Melissa Wen wrote:
When switching to drm_edid, we slightly changed how to get edid by
removing the possibility of getting them from dc_link when in aux
transaction mode. As MST doesn't initialize the connector with
`drm_connector_in
On 2025-02-10 02:51, Deng, Emily wrote:
[AMD Official Use Only - AMD Internal Distribution Only]
[AMD Official Use Only - AMD Internal Distribution Only]
On 2/9/2025 16:50, Melissa Wen wrote:
When switching to drm_edid, we slightly changed how to get edid by
removing the possibility of getting them from dc_link when in aux
transaction mode. As MST doesn't initialize the connector with
`drm_connector_init_with_ddc()`, restore the original behavior
On 2025-01-13 03:18, Simon Ser wrote:
> This patch should probably come after all patches introducing the
> properties referenced in the docs, e.g. NEXT and COLOR_PIPELINE.
> Probably after "[13/45] drm/colorop: Introduce
> DRM_CLIENT_CAP_PLANE_COLOR_PIPELINE"?
>
>> +/**
>> + * DOC: overview
>>
On Mon, Feb 10, 2025 at 02:07:43PM +0800, Tiezhu Yang wrote:
> On 01/15/2025 09:34 AM, Josh Poimboeuf wrote:
> > On Sat, Jan 11, 2025 at 02:57:42PM +0800, Tiezhu Yang wrote:
> > > Hi Josh and Peter,
> > >
> > > On 12/17/2024 09:08 AM, Tiezhu Yang wrote:
> > > > This version is based on tip/tip.git
This commit introduces enhancements to the handling of the cleaner
shader fence in the AMDGPU MES driver:
- The MES (Microcode Execution Scheduler) now sends a PM4 packet to the
KIQ (Kernel Interface Queue) to request the cleaner shader, ensuring
that requests are handled in a controlled manne
From: Srinivasan Shanmugam
This commit introduces enhancements to the handling of the cleaner
shader fence in the AMDGPU MES driver:
- The MES (Microcode Execution Scheduler) now sends a PM4 packet to the
KIQ (Kernel Interface Queue) to request the cleaner shader, ensuring
that requests are
On 2/7/2025 15:27, Ying Li wrote:
This initializes drm/amd/amdgpu version 11.5.2
Signed-off-by: YING LI
Reviewed-by: Mario Limonciello
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 3 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
On 2/7/2025 15:27, Ying Li wrote:
This initializes drm/amd/pm version 11.5.2
Signed-off-by: YING LI
Reviewed-by: Mario Limonciello
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 3 +++
drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 12
2 files changed, 11 insertions
On Tue, Dec 17, 2024 at 09:09:00AM +0800, Tiezhu Yang wrote:
> When compiling with Clang on LoongArch, there exists unreachable entry of
> rodata which points to a position after the function return instruction,
> this is generated by compiler to fill the non-existent switch case, just
> skip the e
On Wed, Feb 5, 2025 at 1:52 PM Shaoyun Liu wrote:
>
> MES fence_value will be updated in fence_addr if API success,
> otherwise upper 32 bit will be used to indicate error code.
> In any case, MES will trigger an EOP interrupt with 0xb1 as
> context id in the interrupt cookie
>
> Signed-off-by: Sh
On Mon, Feb 10, 2025 at 2:07 PM Liu, Shaoyun wrote:
>
> [AMD Official Use Only - AMD Internal Distribution Only]
>
> Might need to update the commit message since this change don't use the
> write-back memory and the package is set_hw_res_1.
Fixed locally. Thanks.
Alex
>
> Other than that
Am 10.02.25 um 17:27 schrieb Alex Deucher:
From: Srinivasan Shanmugam
This commit introduces enhancements to the handling of the cleaner
shader fence in the AMDGPU MES driver:
- The MES (Microcode Execution Scheduler) now sends a PM4 packet to the
KIQ (Kernel Interface Queue) to request
Am 10.02.25 um 17:27 schrieb Alex Deucher:
It's GPU page size not CPU page size. In most cases they
are the same, but not always. This can lead to overallocation
on systems with larger pages.
Cc: Srinivasan Shanmugam
Cc: Christian König
Signed-off-by: Alex Deucher
Reviewed-by: Christian K
[Public]
> -Original Message-
> From: Lazar, Lijo
> Sent: Monday, February 10, 2025 2:01 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhang, Hawking ; Deucher, Alexander
> ; Kim, Jonathan
> Subject: [PATCH v2 4/4] drm/amdgpu: Use xgmi APIs for init and bandwidth
>
> Initialize xgmi relat
Am 10.02.25 um 15:25 schrieb Sathishkumar S:
Add ring reset function callback for JPEG4_0_3 to
recover from job timeouts without a full gpu reset.
V2:
- sched->ready flag shouldn't be modified by back-ends (Christian)
- use drm_sched_wqueue_stop()/drm_sched_wqueue_start() instead (Alex)
Sig
Am 10.02.25 um 15:25 schrieb Sathishkumar S:
Add helper functions to handle per-instance and per-core
initialization and deinitialization in JPEG4_0_3.
Signed-off-by: Sathishkumar S
---
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 190 ---
1 file changed, 98 insertions(+),
[AMD Official Use Only - AMD Internal Distribution Only]
Might need to update the commit message since this change don't use the
write-back memory and the package is set_hw_res_1.
Other than that , it looks good to me . And I think we need a similar change
for gfx12
Regards
Shaoyun.liu
---
Hi Thomas,
On Mon, Dec 16, 2024 at 12:34:49PM +0100, Thomas Weißschuh wrote:
> The sysfs core now allows instances of 'struct bin_attribute' to be
> moved into read-only memory. Make use of that to protect them against
> accidental or malicious modifications.
>
> Signed-off-by: Thomas Weißschuh
Hi Thomas,
On Mon, Dec 16, 2024 at 12:34:48PM +0100, Thomas Weißschuh wrote:
> The sysfs core now allows instances of 'struct bin_attribute' to be
> moved into read-only memory. Make use of that to protect them against
> accidental or malicious modifications.
>
> Signed-off-by: Thomas Weißschuh
Hi Thomas,
On Mon, Dec 16, 2024 at 12:34:47PM +0100, Thomas Weißschuh wrote:
> The sysfs core now allows instances of 'struct bin_attribute' to be
> moved into read-only memory. Make use of that to protect them against
> accidental or malicious modifications.
>
> Signed-off-by: Thomas Weißschuh
[Public]
> -Original Message-
> From: jesse.zh...@amd.com
> Sent: Monday, February 10, 2025 2:32 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Kuehling, Felix
> ; Kim, Jonathan ; Zhu,
> Jiadong ; Zhang, Jesse(Jie) ;
> Deucher, Alexander ; Zhang, Jesse(Jie)
>
> Subject
From: Srinivasan Shanmugam
This commit introduces enhancements to the handling of the cleaner
shader fence in the AMDGPU MES driver:
- The MES (Microcode Execution Scheduler) now sends a PM4 packet to the
KIQ (Kernel Interface Queue) to request the cleaner shader, ensuring
that requests are
It's GPU page size not CPU page size. In most cases they
are the same, but not always. This can lead to overallocation
on systems with larger pages.
Cc: Srinivasan Shanmugam
Cc: Christian König
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 2 +-
1 file changed, 1 i
TMZ support is enabled for vcn on GC IP 11_5_0
Signed-off-by: Saleemkhan Jamadar
Reviewed-by: Leo Liu
---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v4_
On 05/02/2025 15:39, Aurabindo Pillai wrote:
From: Zaeem Mohamed
MAX_SURFACES and MAX_PLANES now have docstrings that better show the difference
between the two.
Reviewed-by: Sun peng Li
Signed-off-by: Zaeem Mohamed
Signed-off-by: Aurabindo Pillai
---
drivers/gpu/drm/amd/display/dc/dc.
On 2/10/2025 3:26 PM, jesse.zh...@amd.com wrote:
> From: "jesse.zh...@amd.com"
>
> This commit introduces several improvements to the SDMA reset logic:
>
> 1. Added `cached_rptr` to the `amdgpu_ring` structure to store the read
> pointer
>before a reset, ensuring proper state restoration
On 2/10/2025 1:01 PM, jesse.zh...@amd.com wrote:
> From: "jesse.zh...@amd.com"
>
> This commit introduces a caller parameter to the amdgpu_sdma_reset_instance
> function to differentiate
> between reset requests originating from the KGD and KFD.
> This change ensures proper synchronization be
On 2/10/2025 1:01 PM, jesse.zh...@amd.com wrote:
> From: "jesse.zh...@amd.com"
>
> This patch refactors the SDMA reset functionality in the `sdma_v4_4_2` driver
> to improve modularity and support shared usage between AMDGPU and KFD. The
> changes include:
>
> 1. **Refactored SDMA Reset Logic
[Public]
Hi all,
This week this patchset was tested on 4 systems, two dGPU and two APU based,
and tested across multiple display and connection types.
APU
* Single Display eDP -> 1080p 60hz, 2560x1600 120hz, 1920x1200 165hz
* Single Display DP (SST DSC) -> 4k144hz, 4k240hz
Add ring reset function callback for JPEG2_0_0 to
recover from job timeouts without a full gpu reset.
Signed-off-by: Sathishkumar S
---
drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2
Add ring reset function callback for JPEG2_5_0 to
recover from job timeouts without a full gpu reset.
Signed-off-by: Sathishkumar S
---
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v
Add helper functions to handle per-instance initialization
and deinitialization in JPEG2_5_0.
Signed-off-by: Sathishkumar S
---
drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 102 +
1 file changed, 55 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_
Add ring reset function callback for JPEG3_0_0 to
recover from job timeouts without a full gpu reset.
Signed-off-by: Sathishkumar S
---
drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3
Add ring reset function callback for JPEG4_0_0 to
recover from job timeouts without a full gpu reset.
Signed-off-by: Sathishkumar S
---
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c | 23 +--
1 file changed, 17 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/j
Add ring reset function callback for JPEG4_0_3 to
recover from job timeouts without a full gpu reset.
V2:
- sched->ready flag shouldn't be modified by back-ends (Christian)
- use drm_sched_wqueue_stop()/drm_sched_wqueue_start() instead (Alex)
Signed-off-by: Sathishkumar S
---
drivers/gpu/drm/
Add helper functions to handle per-instance and per-core
initialization and deinitialization in JPEG4_0_3.
Signed-off-by: Sathishkumar S
---
drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 190 ---
1 file changed, 98 insertions(+), 92 deletions(-)
diff --git a/drivers/gpu/drm/amd
This patch series enables jpeg ring reset callback to recover
from job timeouts without having to do a full gpu reset.
V2:
- sched->ready flag shouldn't be modified by backends (Christian)
- use drm_sched_wqueue_stop()/drm_sched_wqueue_start() instead (Alex)
Sathishkumar S (7):
drm/amdgpu: Pe
On 2/10/2025 1:01 PM, jesse.zh...@amd.com wrote:
> From: "jesse.zh...@amd.com"
>
> This patch introduces shared SDMA reset functionality between AMDGPU and KFD.
> The implementation includes the following key changes:
>
> 1. Added `amdgpu_sdma_reset_queue`:
>- Resets a specific SDMA queue
On 2/7/2025 9:40 PM, Eric Huang wrote:
> In some ASICs L2 cache info may miss in kfd topology,
> because the first bitmap may be empty, that means
> the first cu may be inactive, so to find the first
> active cu will solve the issue.
>
> v2: Only find the first active cu in the first xcc
>
> S
Hi Philipp,
On 07/02/25 08:02, Philipp Stanner wrote:
drm_sched_init() has a great many parameters and upcoming new
functionality for the scheduler might add even more. Generally, the
great number of parameters reduces readability and has already caused
one missnaming in:
commit 6f1cacf4eba7 ("
From: "jesse.zh...@amd.com"
This commit introduces several improvements to the SDMA reset logic:
1. Added `cached_rptr` to the `amdgpu_ring` structure to store the read pointer
before a reset, ensuring proper state restoration after reset.
2. Introduced `gfx_guilty` and `page_guilty` flags i
On 01/15/2025 09:34 AM, Josh Poimboeuf wrote:
On Sat, Jan 11, 2025 at 02:57:42PM +0800, Tiezhu Yang wrote:
Hi Josh and Peter,
On 12/17/2024 09:08 AM, Tiezhu Yang wrote:
This version is based on tip/tip.git objtool/core branch [1], add some weak
and arch-specific functions to make the generic c
Rename pmfw message SelectPstatePolicy to SetThrottlingPolicy as per
pmfw interface header for smu_v_13_0_6
Signed-off-by: Asad Kamal
Reviewed-by: Lijo Lazar
---
drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h | 2 +-
drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 2
72 matches
Mail list logo
