[PATCH] drm/amdgou/vcn: enable TMZ support for vcn 4_0_5

[Saleemkhan Jamadar]

TMZ support is enabled for vcn on GC IP 11_5_0

Signed-off-by: Saleemkhan Jamadar <saleemkhan.jama...@amd.com>
Reviewed-by: Leo Liu <leo....@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
index 8c9a9017320e..eb29b67ec807 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
@@ -1405,7 +1405,7 @@ static void vcn_v4_0_5_unified_ring_set_wptr(struct 
amdgpu_ring *ring)
        }
 }
 
-static const struct amdgpu_ring_funcs vcn_v4_0_5_unified_ring_vm_funcs = {
+static struct amdgpu_ring_funcs vcn_v4_0_5_unified_ring_vm_funcs = {
        .type = AMDGPU_RING_TYPE_VCN_ENC,
        .align_mask = 0x3f,
        .nop = VCN_ENC_CMD_NO_OP,
@@ -1449,6 +1449,9 @@ static void vcn_v4_0_5_set_unified_ring_funcs(struct 
amdgpu_device *adev)
                if (adev->vcn.harvest_config & (1 << i))
                        continue;
 
+               if (amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 5))
+                       
vcn_v4_0_5_unified_ring_vm_funcs.secure_submission_supported = true;
+
                adev->vcn.inst[i].ring_enc[0].funcs = 
&vcn_v4_0_5_unified_ring_vm_funcs;
                adev->vcn.inst[i].ring_enc[0].me = i;
        }
-- 
2.34.1