[PATCH] drm/amdkfd: Fix missing error code in kfd_queue_acquire_buffers

2024-07-25 Thread Srinivasan Shanmugam
The fix involves setting 'err' to '-EINVAL' before each 'goto out_err_unreserve'. Fixes the below: drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_queue.c:265 kfd_queue_acquire_buffers() warn: missing error code 'err' drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_queue.c 226 int kfd_queue_acquire_buffers

RE: [PATCH] drm/amdgpu: Fix APU handling in amdgpu_pm_load_smu_firmware()

2024-07-25 Thread Huang, Tim
[Public] This patch is, Reviewed-by: Tim Huang > -Original Message- > From: Deucher, Alexander > Sent: Friday, July 26, 2024 5:36 AM > To: amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander ; Huang, Tim > > Subject: [PATCH] drm/amdgpu: Fix APU handling in > amdgpu_pm_load_smu_fi

RE: [PATCH] drm/amdgpu/pm: update documentation on memory clock

2024-07-25 Thread Feng, Kenneth
[AMD Official Use Only - AMD Internal Distribution Only] Hi Alex, I know that G6 MCLK = 2*UCLK. May I know how did you get the data that effective_memory_clock = memory_controller_clock * 1? Thanks. -Original Message- From: amd-gfx On Behalf Of Alex Deucher Sent: Friday, July 26, 2024

Re: [PATCH v3] drm/amdkfd: Change kfd/svm page fault drain handling

2024-07-25 Thread Philip Yang
On 2024-07-25 14:19, Xiaogang.Chen wrote: From: Xiaogang Chen When app unmap vm ranges(munmap) kfd/svm starts drain pending page fault and not handle any incoming pages fault of this process until a deferred work item got executed by default system wq. The

[PATCH] drm/amdgpu: do not call mux_start_ib on high priority rings

2024-07-25 Thread jiadong.zhu
From: Jiadong Zhu The function amdgpu_ring_mux_start_ib shall not be called on high priority rings even if mcbp is disabled. Otherwise there maybe leak from the chunks of the ring mux. Signed-off-by: Jiadong Zhu --- drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c | 4 ++-- 1 file changed, 2 inser

[PATCH] drm/amdkfd: Fix compile error if HMM support not enabled

2024-07-25 Thread Philip Yang
Fixes the below if kernel config not enable HMM support >> drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_queue.c:107:26: error: implicit declaration of function 'svm_range_from_addr' >> drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_queue.c:107:24: error: assignment to 'struct svm_range *' from 'int' makes

Re: [PATCH] drm/amdgpu/pm: update documentation on memory clock

2024-07-25 Thread Alex Deucher
Ping? On Thu, May 2, 2024 at 5:07 PM Alex Deucher wrote: > > Update documentation for RDNA3 dGPUs. > > Signed-off-by: Alex Deucher > --- > drivers/gpu/drm/amd/pm/amdgpu_pm.c | 6 ++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c > b/drivers/gpu/drm/am

[PATCH] drm/amdgpu: Fix APU handling in amdgpu_pm_load_smu_firmware()

2024-07-25 Thread Alex Deucher
We only need to skip this on modern APUs. It's required on older APUs as it's where start_smu gets called from. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3502 Fixes: 064d92436b69 ("drm/amd/pm: avoid to load smu firmware for APUs") Signed-off-by: Alex Deucher Cc: Tim Huang --- dri

Re: [PATCH] drm/radeon/evergreen_cs: fix int overflow errors in cs track offsets

2024-07-25 Thread Alex Deucher
Applied. Thanks! Alex On Thu, Jul 25, 2024 at 2:20 PM Nikita Zhandarovich wrote: > > Several cs track offsets (such as 'track->db_s_read_offset') > either are initialized with or plainly take big enough values that, > once shifted 8 bits left, may be hit with integer overflow if the > resulting

Re: [PATCH] drm/amdgpu: fix contiguous handling for IB parsing v2

2024-07-25 Thread Dave Airlie
On Thu, 25 Jul 2024 at 23:35, Alex Deucher wrote: > > On Thu, Jul 25, 2024 at 4:07 AM Christian König > wrote: > > > > Otherwise we won't get correct access to the IB. > > > > v2: keep setting AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS to avoid problems in > > the VRAM backend. > > > > Signed-off-by:

[pull] amdgpu drm-fixes-6.11

2024-07-25 Thread Alex Deucher
Hi Dave, Sima, Fixes for 6.11. The following changes since commit 627a24f5f25d689682f395f3df1411273be4436b: Merge tag 'amd-drm-fixes-6.11-2024-07-18' of https://gitlab.freedesktop.org/agd5f/linux into drm-next (2024-07-22 13:03:50 +1000) are available in the Git repository at: https://gi

Re: [PATCH] drm/amd/display: Fix documentation warning for mpc.h

2024-07-25 Thread Alex Deucher
This is already fixed in: https://gitlab.freedesktop.org/agd5f/linux/-/commit/6e169c7e0f842c48c7bf683fb789dbf5a8b1dfd8 Alex On Wed, Jul 24, 2024 at 3:55 PM Ricardo B. Marliere wrote: > > On 24 Jul 24 23:24, Abhishek Tamboli wrote: > > Fix documentation compile warning by adding description > > f

Re: [PATCH] drm/amdgpu: increase mes log buffer size for gfx12

2024-07-25 Thread Alex Deucher
On Wed, Jul 24, 2024 at 2:47 PM Michael Chen wrote: > > MES firmware requires larger log buffer for gfx12. Allocate > proper buffer respectively for gfx11 and gfx12. > > Signed-off-by: Michael Chen Acked-by: Alex Deucher > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 6 +++--- > driv

Re: [PATCH -next] drm/amd/display: remove unneeded semicolon

2024-07-25 Thread Alex Deucher
Applied. Thanks! Alex On Wed, Jul 24, 2024 at 10:35 PM Jiapeng Chong wrote: > > No functional modification involved. > > ./drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c:481:2-3: > Unneeded semicolon. > ./drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/d

Re: [PATCH v3 4/4] drm/amdgpu: add print support for vcn_v3_0 ip dump

2024-07-25 Thread Alex Deucher
Series is: Reviewed-by: Alex Deucher On Thu, Jul 25, 2024 at 2:41 AM Sunil Khatri wrote: > > Add support for logging the registers in devcoredump > buffer for vcn_v3_0. > > Signed-off-by: Sunil Khatri > --- > drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 28 ++- > 1 file chan

[PATCH v3] drm/amdkfd: Change kfd/svm page fault drain handling

2024-07-25 Thread Xiaogang . Chen
From: Xiaogang Chen When app unmap vm ranges(munmap) kfd/svm starts drain pending page fault and not handle any incoming pages fault of this process until a deferred work item got executed by default system wq. The time period of "not handle page fault" can be long and is unpredicable. That is ad

[PATCH 33/39] drm/amd/display: Add missing DET segments programming

2024-07-25 Thread Rodrigo Siqueira
The commit 54bd97eedd39 ("drm/amd/display: Modify DHCUB waterwark structures and functions") introduced a code refactor for DCHUB, but during the merge process into amd-staging-drm-next, the program det segments were removed. This commit adds the DET segment programming for DCN35. Fixes: 54bd97eed

[PATCH 38/39] drm/amd/display: Remove unused code

2024-07-25 Thread Rodrigo Siqueira
Remove function pointers that were never used. Reviewed-by: Aurabindo Pillai Signed-off-by: Rodrigo Siqueira --- drivers/gpu/drm/amd/display/dc/inc/hw/transform.h | 10 -- 1 file changed, 10 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h b/drivers/gpu/drm/

[PATCH 37/39] drm/amd/display: Add missing registers for dcn32

2024-07-25 Thread Rodrigo Siqueira
Add missing debug registers for DCN32. Reviewed-by: Aurabindo Pillai Signed-off-by: Rodrigo Siqueira --- .../gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h b/driver

[PATCH 34/39] drm/amd/display: Remove duplicated code

2024-07-25 Thread Rodrigo Siqueira
DCN_MINIMUM_DISPCLK_Khz and DCN_MINIMUM_DPPCLK_Khz is declared twice. This commit removes that duplication. Reviewed-by: Aurabindo Pillai Signed-off-by: Rodrigo Siqueira --- drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/amd

[PATCH 39/39] drm/amd/display: 3.2.294

2024-07-25 Thread Rodrigo Siqueira
From: Aric Cyr This version brings along the following: - SPL improvements. - Address coverity issues. - DML2 fixes. - Code cleanup. - DIO and DCCG refactor. - Improve the PSR state. Signed-off-by: Aric Cyr Reviewed-by: Rodrigo Siqueira Signed-off-by: Rodrigo Siqueira --- drivers/gpu/drm/am

[PATCH 35/39] drm/amd/display: Add missing mcache registers

2024-07-25 Thread Rodrigo Siqueira
Add missing register programming for mcache in DCN401. Reviewed-by: Aurabindo Pillai Signed-off-by: Rodrigo Siqueira --- .../gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/resource/d

[PATCH 32/39] drm/amd/display: For FAMS2 don't program P-State force from driver

2024-07-25 Thread Rodrigo Siqueira
From: Alvin Lee P-State force programming is handled entirely by FW in FAMS2. Remove any programming from driver side to prevent incorrect programming from driver side (which may override FW programming) Signed-off-by: Alvin Lee Reviewed-by: Rodrigo Siqueira Signed-off-by: Rodrigo Siqueira -

[PATCH 36/39] drm/amd/display: Add dcc propagation value

2024-07-25 Thread Rodrigo Siqueira
Initialize the field dcc_meta_propagation_delay_us with 10 ms. Reviewed-by: Aurabindo Pillai Signed-off-by: Rodrigo Siqueira --- drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dc

[PATCH 31/39] drm/amd/display: Fix Cursor Offset in Scaled Scenarios

2024-07-25 Thread Rodrigo Siqueira
From: Sung Lee [WHY] Cursor position code had improper offsets in scaled modes. [HOW] Adjust cursor scaling to account for cursor offsets properly. Reviewed-by: Rodrigo Siqueira Signed-off-by: Sung Lee Signed-off-by: Rodrigo Siqueira --- drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hub

[PATCH 26/39] drm/amd/display: Check UnboundedRequestEnabled's value

2024-07-25 Thread Rodrigo Siqueira
From: Alex Hung CalculateSwathAndDETConfiguration_params_st's UnboundedRequestEnabled is a pointer (i.e. dml_bool_t *UnboundedRequestEnabled), and thus p->UnboundedRequestEnabled checks its address, not bool value. To check value, *p->UnboundedRequestEnabled is used instead. This fixes 1 REVERS

[PATCH 30/39] drm/amd/display: Replace dm_execute_dmub_cmd with dc_wake_and_execute_dmub_cmd

2024-07-25 Thread Rodrigo Siqueira
In the commit c2cec7a872b6 ("drm/amd/display: Wake DMCUB before sending a command for replay feature"), replaced dm_execute_dmub_cmd with dc_wake_and_execute_dmub_cmd in multiple areas, but due to merge issues the replacement of this function in the dmub_replay_copy_settings was missed. This commit

[PATCH 21/39] drm/amd/display: Initialize get_bytes_per_element's default to 1

2024-07-25 Thread Rodrigo Siqueira
From: Alex Hung Variables, used as denominators and maybe not assigned to other values, should not be 0. bytes_per_element_y & bytes_per_element_c are initialized by get_bytes_per_element() which should never return 0. This fixes 10 DIVIDE_BY_ZERO issues reported by Coverity. Signed-off-by: Ale

[PATCH 28/39] drm/amd/display: Re-order enum in a header file

2024-07-25 Thread Rodrigo Siqueira
Move the lb_memory_config close to the pixel format enums to improve the code readability. Reviewed-by: Aurabindo Pillai Signed-off-by: Rodrigo Siqueira --- .../gpu/drm/amd/display/dc/spl/dc_spl_types.h | 32 +-- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/dr

[PATCH 23/39] drm/amd/display: Add new enable and disable functions for DCN35

2024-07-25 Thread Rodrigo Siqueira
From: Hansen Dsouza Add new enable and disable functions based on DCCG spec. Signed-off-by: Hansen Dsouza Reviewed-by: Muhammad Ahmed Signed-off-by: Rodrigo Siqueira --- .../amd/display/dc/dccg/dcn35/dcn35_dccg.c| 54 ++- 1 file changed, 53 insertions(+), 1 deletion(-) d

[PATCH 29/39] drm/amd/display: Setup two pixel per container

2024-07-25 Thread Rodrigo Siqueira
SPL has a control field for controlling the two pixels per container that is not in use yet. This commit adds a proper initialization for this feature. Reviewed-by: Aurabindo Pillai Signed-off-by: Rodrigo Siqueira --- drivers/gpu/drm/amd/display/dc/dc_spl_translate.c | 1 + 1 file changed, 1 in

[PATCH 27/39] drm/amd/display: Get link index for AUX reply notification

2024-07-25 Thread Rodrigo Siqueira
From: Cruise The link index wasn't updated for the AUX reply notification. Get link index based on DPIA instance for AUX reply notification. Signed-off-by: Cruise Reviewed-by: Meenakshikumar Somasundaram Signed-off-by: Rodrigo Siqueira --- drivers/gpu/drm/amd/display/dc/core/dc_stat.c | 1 +

[PATCH 24/39] drm/amd/display: Enable aux transfer path via dmub for dp tunneling

2024-07-25 Thread Rodrigo Siqueira
From: Meenakshikumar Somasundaram [Why] Aux transfer retries path does not support dp tunneling. [How] Based on ddc pin check, aux will be issued in legacy path or dmub. Signed-off-by: Meenakshikumar Somasundaram Reviewed-by: Eric Yang Signed-off-by: Rodrigo Siqueira --- drivers/gpu/drm/amd

[PATCH 22/39] drm/amd/display: Use gpuvm_min_page_size_kbytes for DML2 surfaces

2024-07-25 Thread Rodrigo Siqueira
From: Nicholas Kazlauskas [Why] It's currently hard coded to 256 when it should be using the SOC provided values. This can result in corruption with linear surfaces where we prefetch more PTE than the buffer can hold. [How] Update the min page size correctly for the plane. Signed-off-by: Nichol

[PATCH 20/39] drm/amd/display: Check null values from functions

2024-07-25 Thread Rodrigo Siqueira
From: Alex Hung Functions get_per_method_common_meta and get_expanded_strategy_list can return null and thus it is necessary to check their returned values before dereferencing. This fixes 3 NULL_RETURNS issues reported by Coverity. Signed-off-by: Alex Hung Reviewed-by: Rodrigo Siqueira Signe

[PATCH 25/39] drm/amd/display: Underflow Seen on DCN401 eGPU

2024-07-25 Thread Rodrigo Siqueira
From: Daniel Sa [WHY] In dcn401 we read clock values before FW is loaded. These incorrect values cause the driver to believe that we are running higher clocks than what we actually have. This then causes corruption/underflow for the eGPU. [HOW] When new values are read from HW, update internal s

[PATCH 18/39] drm/amd/display: Add new enable and disable functions

2024-07-25 Thread Rodrigo Siqueira
From: Hansen Dsouza Add new enable and disable functions based on DCCG spec. Signed-off-by: Hansen Dsouza Reviewed-by: Muhammad Ahmed Signed-off-by: Rodrigo Siqueira --- .../amd/display/dc/dccg/dcn35/dcn35_dccg.c| 212 ++ 1 file changed, 212 insertions(+) diff --git a/dr

[PATCH 19/39] drm/amd/display: Add logs for debugging outbox

2024-07-25 Thread Rodrigo Siqueira
From: Cruise The DP tunnel AUX reply is received through Outbox1. Print the Outbox1 status if an issue occurs. Signed-off-by: Cruise Reviewed-by: Nicholas Kazlauskas Reviewed-by: Wayne Lin Signed-off-by: Rodrigo Siqueira --- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 3 +++ driver

[PATCH 17/39] drm/amd/display: Avoid overflow assignment in link_dp_cts

2024-07-25 Thread Rodrigo Siqueira
From: Alex Hung sampling_rate is an uint8_t but is assigned an unsigned int, and thus it can overflow. As a result, sampling_rate is changed to uint32_t. Similarly, LINK_QUAL_PATTERN_SET has a size of 2 bits, and it should only be assigned to a value less or equal than 4. This fixes 2 INTEGER_O

[PATCH 15/39] drm/amd/display: Add seamless boot support for more DIG operation modes

2024-07-25 Thread Rodrigo Siqueira
From: Nicholas Kazlauskas [Why] When pre-OS firmware enables display support for displays that operate the DIG in 2 pixels per cycle processing modes the inferred pixel rate from get_pixel_clk_frequency_100hz does not account for the true pixel rate since we're outputting 2 per cycle past the str

[PATCH 16/39] drm/amd/display: Use correct cm_helper function

2024-07-25 Thread Rodrigo Siqueira
From: Ilya Bakoulin Need to use cm3_helper function with DCN401 to avoid cases where high RGB component values can get set to zero if using the TF curve generated by cm_helper. Signed-off-by: Ilya Bakoulin Reviewed-by: Alvin Lee Signed-off-by: Rodrigo Siqueira --- .../amd/display/dc/hwss/dcn

[PATCH 14/39] drm/amd/display: Reset VRR config during resume

2024-07-25 Thread Rodrigo Siqueira
From: Tom Chung [Why] After resume the system, the new_crtc_state->vrr_infopacket does not synchronize with the current state. It will affect the update_freesync_state_on_stream() does not update the state correctly. The previous patch causes a PSR SU regression that cannot let panel go into se

[PATCH 12/39] drm/amd/display: sync dmub output event type.

2024-07-25 Thread Rodrigo Siqueira
From: Charlene Liu [why] dmubfw added a new event type, update amdgpu to avoid "notify type 6 invalid" Signed-off-by: Charlene Liu Reviewed-by: Chris Park Signed-off-by: Rodrigo Siqueira --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 + 1 file changed, 1 insertion(+) diff --git a

[PATCH 13/39] drm/amd/display: Add a missing PSR state

2024-07-25 Thread Rodrigo Siqueira
From: Tom Chung [Why & How] Add a missing PSR state to make the dmub_psr_get_state() return a correct PSR state. Signed-off-by: Tom Chung Reviewed-by: Sun peng Li Signed-off-by: Rodrigo Siqueira --- drivers/gpu/drm/amd/display/dc/dc_types.h | 1 + drivers/gpu/drm/amd/display/dc/dce/dmub_

[PATCH 10/39] drm/amd/display: Check stream_status before it is used

2024-07-25 Thread Rodrigo Siqueira
From: Alex Hung [WHAT & HOW] dc_state_get_stream_status can return null, and therefore null must be checked before stream_status is used. This fixes 1 NULL_RETURNS issue reported by Coverity. Signed-off-by: Alex Hung Reviewed-by: Rodrigo Siqueira Signed-off-by: Rodrigo Siqueira --- drivers/

[PATCH 11/39] drm/amd/display: restore immediate_disable_crtc for w/a

2024-07-25 Thread Rodrigo Siqueira
From: Charlene Liu [why] immediate_disable_crtc does not reset ODM. if switching to disable_crtc which will disable ODM as well. i.e. need to restore ODM mem cfg at reenable it at end of w/a. Signed-off-by: Charlene Liu Reviewed-by: Xi (Alex) Liu Signed-off-by: Rodrigo Siqueira --- .../gpu

[PATCH 09/39] drm/amd/display: Check null pointers before using them

2024-07-25 Thread Rodrigo Siqueira
From: Alex Hung [WHAT & HOW] dc_link is null checked previously in the same function, indicating it might be null as reported by Coverity. This fixes 1 FORWARD_NULL issue reported by Coverity. Signed-off-by: Alex Hung Reviewed-by: Rodrigo Siqueira Signed-off-by: Rodrigo Siqueira --- drivers

[PATCH 08/39] drm/amd/display: Fix possible overflow in integer multiplication

2024-07-25 Thread Rodrigo Siqueira
From: Alex Hung [WHAT & HOW] Integer multiplies integer may overflow in context that expects an expression of unsigned long long (64 bits). This can be fixed by casting integer to unsigned long long to force 64 bits results. This fixes 2 OVERFLOW_BEFORE_WIDEN issues reported by Coverity. Signed

[PATCH 07/39] drm/amd/display: Add option to disable unbounded req in DML21

2024-07-25 Thread Rodrigo Siqueira
From: Alvin Lee Use debug option for disabling unbounded req in DML21 Signed-off-by: Alvin Lee Reviewed-by: Austin Zheng Signed-off-by: Rodrigo Siqueira --- .../drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/

[PATCH 06/39] drm/amd/display: Refactor for dio

2024-07-25 Thread Rodrigo Siqueira
From: Bhuvanachandra Pinninti Moved files to respective folders to improve DIO code. Signed-off-by: Bhuvanachandra Pinninti Reviewed-by: Martin Leung Signed-off-by: Rodrigo Siqueira --- drivers/gpu/drm/amd/display/dc/Makefile| 1 - drivers/gpu/drm/amd/display/dc/dcn301/Makefile | 2

[PATCH 04/39] drm/amd/display: Add two dmmuy I2C entry for GPIO port mapping issue

2024-07-25 Thread Rodrigo Siqueira
From: Chris Park [Why] When only 4 I2C is declared, two dummies are required to correctly map GPIO port. [How] Add one more I2C dummy entry to match GPIO port. Signed-off-by: Chris Park Reviewed-by: Alvin Lee Signed-off-by: Rodrigo Siqueira --- .../display/dc/gpio/dcn401/hw_factory_dcn401.c

[PATCH 05/39] drm/amd/display: Request 0MHz dispclk for zero display case

2024-07-25 Thread Rodrigo Siqueira
From: Nicholas Kazlauskas [Why] If we aren't entering RCG/IPS2 or CLKSTOP is not supported by PMFW then we should be requesting a dispclk value of 0MHz to PMFW. Currenly we run at max clock since there's an assumption in APU clock table formulation where we can run at any DISPCLK at any state so

[PATCH 03/39] drm/amd/display: Run idle optimizations at end of vblank handler

2024-07-25 Thread Rodrigo Siqueira
From: Leo Li [Why & How] 1. After allowing idle optimizations, hw programming is disallowed. 2. Before hw programming, we need to disallow idle optimizations. Otherwise, in scenario 1, we will immediately kick hw out of idle optimizations with register access. Scenario 2 is less of a concern, s

[PATCH 02/39] drm/amd/display: Let drm_crtc_vblank_on/off manage interrupts

2024-07-25 Thread Rodrigo Siqueira
From: Leo Li [Why] We manage interrupts for CRTCs in two places: 1. In manage_dm_interrupts(), when CRTC get enabled or disabled 2. When drm_vblank_get/put() starts or kills the vblank counter, calling into amdgpu_dm_crtc_set_vblank() The interrupts managed by these twp places should be ident

[PATCH 00/39] DC Patches July 25, 2024

2024-07-25 Thread Rodrigo Siqueira
This DC patchset brings improvements in multiple areas. In summary, we have: - SPL improvements. - Address coverity issues. - DML2 fixes. - Code cleanup. - DIO and DCCG refactor. - Improve the PSR state. Cc: Daniel Wheeler Thanks Siqueira Alex Hung (7): drm/amd/display: Fix possible overflow

[PATCH] drm/sched: Add error code parameter to drm_sched_start

2024-07-25 Thread vitaly.prosyak
From: Vitaly Prosyak The current implementation of drm_sched_start uses a hardcoded -ECANCELED to dispose of a job when the parent/hw fence is NULL. This results in drm_sched_job_done being called with -ECANCELED for each job with a NULL parent in the pending list, making it difficult to disti

Re: [PATCH v4 10/11] drm/amd/display: get SADB from drm_eld when parsing EDID caps

2024-07-25 Thread Alex Hung
On 2024-07-05 21:35, Melissa Wen wrote: instead of parsing struct edid. A more informative commit message will be helpful. Signed-off-by: Melissa Wen --- .../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 15 +++ 1 file changed, 3 insertions(+), 12 deletions(-) diff --gi

Re: [PATCH v4 09/11] drm/amd/display: get SAD from drm_eld when parsing EDID caps

2024-07-25 Thread Alex Hung
On 2024-07-05 21:35, Melissa Wen wrote: instead of parsing struct edid. A more informative commit message will be helpful. Signed-off-by: Melissa Wen --- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 17 + 1 file changed, 9 insertions(+), 8 deletions(-) diff --git

Re: [PATCH v4 07/11] drm/amd/display: don't give initial values for sad/b_count

2024-07-25 Thread Alex Hung
Can this be merged with [PATCH 10/11] drm/amd/display: get SADB from drm_eld when parsing EDID caps On 2024-07-05 21:35, Melissa Wen wrote: Signed-off-by: Melissa Wen --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff

Re: [PATCH v4 03/11] drm/amd/display: switch to setting physical address directly

2024-07-25 Thread Alex Hung
On 2024-07-05 21:35, Melissa Wen wrote: Connectors have source physical address available in display info. Use drm_dp_cec_attach() to use it instead of parsing the EDID again. Signed-off-by: Melissa Wen --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 ++--- 1 file changed, 2 ins

Re: [PATCH v4 02/11] drm/amd/display: switch amdgpu_dm_connector to use struct drm_edid

2024-07-25 Thread Alex Hung
Please see inline comments. On 2024-07-05 21:35, Melissa Wen wrote: Replace raw edid handling (struct edid) with the opaque EDID type (struct drm_edid) on amdgpu_dm_connector for consistency. It may also prevent mismatch of approaches in different parts of the driver code. Working in progress. I

Re: [PATCH 1/2] drm/sched: Add error code parameter to drm_sched_start

2024-07-25 Thread Alex Deucher
On Wed, Jul 24, 2024 at 11:30 PM wrote: > > From: Vitaly Prosyak > > The current implementation of drm_sched_start uses a hardcoded -ECANCELED to > dispose of a job when > the parent/hw fence is NULL. This results in drm_sched_job_done being called > with -ECANCELED for > each job with a NULL p

Re: [PATCH v4 01/11] drm/amd/display: clean unused variables for hdmi freesync parser

2024-07-25 Thread Alex Hung
Hi Melissa, There are no commit messages in this patch. Also, do you think this can be merged with Patch 5 "drm/amd/display: remove redundant freesync parser for DP"? On 2024-07-05 21:35, Melissa Wen wrote: Signed-off-by: Melissa Wen --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

Re: [PATCH V2 00/53] GC per queue reset

2024-07-25 Thread Alex Deucher
On Thu, Jul 25, 2024 at 11:20 AM Alex Deucher wrote: > > This adds preliminary support for GC per queue reset. In this > case, only the jobs currently in the queue are lost. If this > fails, we fall back to a full adapter reset. > > V2: Fix fallbacks to full adapter reset > RLC safemode clea

[PATCH 44/53] drm/amdgpu/gfx9: use proper rlc safe mode helpers

2024-07-25 Thread Alex Deucher
Rather than open coding it for the queue reset. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 82b38432071e..77e

[PATCH 31/53] drm/amdgpu/mes: modify mes api for mmio queue reset

2024-07-25 Thread Alex Deucher
From: Jiadong Zhu Add me/pipe/queue parameters for queue reset input. v2: fix build (Alex) Signed-off-by: Jiadong Zhu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 3 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 14 +- driv

[PATCH 39/53] drm/amdgpu/gfx11: per queue reset only on bare metal

2024-07-25 Thread Alex Deucher
It's not supported under SR-IOV at the moment. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 37dd5002e92f..c1f799651b25 100644

[PATCH 49/53] drm/amdgpu/gfx12: use rlc safe mode for soft recovery

2024-07-25 Thread Alex Deucher
Protect the MMIO access with safe mode. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index 4984df3a0b75..89262bb2258d 100644 --- a/driv

[PATCH 36/53] drm/amdgpu/mes11: implement mmio queue reset for gfx11

2024-07-25 Thread Alex Deucher
From: Jiadong Zhu Implement queue reset for graphic and compute queue. v2: use amdgpu_gfx_rlc funcs to enter/exit safe mode. v3: use gfx_v11_0_request_gfx_index_mutex() Signed-off-by: Jiadong Zhu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mes_v11_0.

[PATCH 52/53] drm/amdgpu/gfx9.4.3: use rlc safe mode for soft recovery

2024-07-25 Thread Alex Deucher
Protect the MMIO access with safe mode. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 797de64cde74..c1a17bdee6cc 100644 --- a/d

[PATCH 23/53] drm/amdgpu/gfx9.4.3: add ring reset callback

2024-07-25 Thread Alex Deucher
Add ring reset callback for compute. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 38 + 1 file changed, 38 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 98fe6c40da64..6cf90

[PATCH 47/53] drm/amdgpu/gfx11: use proper rlc safe mode helpers

2024-07-25 Thread Alex Deucher
Rather than open coding it for the queue reset. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index c1f799651b25..

[PATCH 51/53] drm/amdgpu/gfx10: use rlc safe mode for soft recovery

2024-07-25 Thread Alex Deucher
Protect the MMIO access with safe mode. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index da0d3c8e00b8..2bf595f88970 100644 --- a/driv

[PATCH 38/53] drm/amdgpu/gfx10: per queue reset only on bare metal

2024-07-25 Thread Alex Deucher
It's not supported under SR-IOV at the moment. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 0c12ea47c79a..dc4bd17b4789 100644

[PATCH 48/53] drm/amdgpu/gfx12: use proper rlc safe mode helpers

2024-07-25 Thread Alex Deucher
Rather than open coding it for the queue reset. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index 7812c9256566..4984

[PATCH 42/53] drm/amdgpu/gfx8: add ring reset callback for gfx

2024-07-25 Thread Alex Deucher
Add ring reset callback for gfx. Untested. v2: fix operator precendence (kernel test robot) Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 75 ++- drivers/gpu/drm/amd/amdgpu/vid.h | 1 + 2 files changed, 75 insertions(+), 1 deletion(-) di

[PATCH 45/53] drm/amdgpu/gfx9.4.3: use proper rlc safe mode helpers

2024-07-25 Thread Alex Deucher
Rather than open coding it for the queue reset. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 7ac727f6b9b

[PATCH 34/53] drm/amdgpu/gfx11: add a mutex for the gfx semaphore

2024-07-25 Thread Alex Deucher
This will be used in more places in the future so add a mutex. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h| 2 ++ drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 10 +++--- 3 files changed, 10 insertions(+), 3 d

[PATCH 24/53] drm/amdgpu/gfx9.4.3: remap queue after reset successfully

2024-07-25 Thread Alex Deucher
From: Jiadong Zhu Kiq command unmap_queues only does the dequeueing action. We have to map the queue back with clean mqd. Signed-off-by: Jiadong Zhu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 36 ++--- 1 file change

[PATCH 35/53] drm/amdgpu/gfx11: export gfx_v11_0_request_gfx_index_mutex()

2024-07-25 Thread Alex Deucher
It will be used by the queue reset code. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.h | 3 +++ 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/a

[PATCH 53/53] drm/amdgpu/gfx9: use rlc safe mode for soft recovery

2024-07-25 Thread Alex Deucher
Protect the MMIO access with safe mode. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 77e64987bb03..11a565d7b5d1 100644 --- a/drivers

[PATCH 46/53] drm/amdgpu/gfx10: use proper rlc safe mode helpers

2024-07-25 Thread Alex Deucher
Rather than open coding it for the queue reset. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index dc4bd17b4789..da0d

[PATCH 50/53] drm/amdgpu/gfx11: use rlc safe mode for soft recovery

2024-07-25 Thread Alex Deucher
Protect the MMIO access with safe mode. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 4198656f9a0d..0b36c4039b2b 100644 --- a/driv

[PATCH 37/53] drm/amdgpu/gfx9: per queue reset only on bare metal

2024-07-25 Thread Alex Deucher
It's not supported under SR-IOV at the moment. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 +++ drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_

[PATCH 40/53] drm/amdgpu/gfx12: per queue reset only on bare metal

2024-07-25 Thread Alex Deucher
It's not supported under SR-IOV at the moment. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index 02efb0a2e625..7812c9256566 100644

[PATCH 43/53] drm/amdgpu/gfx7: add ring reset callback for gfx

2024-07-25 Thread Alex Deucher
Add ring reset callback for gfx. Untested. v2: fix operator precendence (kernel test robot) Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/cikd.h | 1 + drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 76 ++- 2 files changed, 76 insertions(+), 1 deletion(-) di

[PATCH 30/53] drm/amdgpu/gfx9.4.3: implement reset_hw_queue for gfx9.4.3

2024-07-25 Thread Alex Deucher
From: Jiadong Zhu Using mmio to do queue reset. Enter safe mode before writing mmio registers. v2: set register instance offset according to xcc id. Signed-off-by: Jiadong Zhu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 36

[PATCH 15/53] drm/amdgpu/gfx11: wait for reset done before remap

2024-07-25 Thread Alex Deucher
From: Jiadong Zhu There is a racing condition that cp firmware modifies MQD in reset sequence after driver updates it for remapping. We have to wait till CP_HQD_ACTIVE becoming false then remap the queue. Signed-off-by: Jiadong Zhu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- dr

[PATCH 18/53] drm/amdgpu/gfx10: wait for reset done before remap

2024-07-25 Thread Alex Deucher
From: Jiadong Zhu There is a racing condition that cp firmware modifies MQD in reset sequence after driver updates it for remapping. We have to wait till CP_HQD_ACTIVE becoming false then remap the queue. v2: fix KIQ locking (Alex) v3: fix KIQ locking harder (Jessie) Signed-off-by: Jiadong Zhu

[PATCH 19/53] drm/amdgpu/gfx10: rework reset sequence

2024-07-25 Thread Alex Deucher
To match other GFX IPs. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 26 +++--- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 7b534966a297..0c12

[PATCH 41/53] drm/amdgpu/gfx9: add ring reset callback for gfx

2024-07-25 Thread Alex Deucher
Add ring reset callback for gfx. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 47 +++ 1 file changed, 47 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index df5018b4e708..82b38432071e

[PATCH 25/53] drm/amdgpu/gfx_9.4.3: wait for reset done before remap

2024-07-25 Thread Alex Deucher
From: Jiadong Zhu There is a racing condition that cp firmware modifies MQD in reset sequence after driver updates it for remapping. We have to wait till CP_HQD_ACTIVE becoming false then remap the queue. v2: fix KIQ locking (Alex) v3: fix KIQ locking harder Signed-off-by: Jiadong Zhu Reviewed

[PATCH 26/53] drm/amdgpu/gfx12: add ring reset callbacks

2024-07-25 Thread Alex Deucher
Add ring reset callbacks for gfx and compute. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 18 ++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index f932c7ff85e3..790b8d

[PATCH 14/53] drm/amdgpu/gfx11: rename gfx_v11_0_gfx_init_queue()

2024-07-25 Thread Alex Deucher
Rename to gfx_v11_0_kgq_init_queue() to better align with the other naming in the file. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/a

[PATCH 06/53] drm/amdgpu/mes: add API for user queue reset

2024-07-25 Thread Alex Deucher
Add API for resetting user queues. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 43 + drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 9 ++ 2 files changed, 52 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/d

[PATCH 33/53] drm/amdgpu/gfx11: enter safe mode before touching CP_INT_CNTL

2024-07-25 Thread Alex Deucher
Need to enter safe mode before touching GC MMIO. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index c047e92471af..fc9

[PATCH 29/53] drm/amdgpu/gfx9: implement reset_hw_queue for gfx9

2024-07-25 Thread Alex Deucher
From: Jiadong Zhu Using mmio to do queue reset. Enter safe mode when writing registers. Signed-off-by: Jiadong Zhu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 37 +++ 1 file changed, 37 insertions(+) diff --git a/

[PATCH 10/53] drm/amdgpu: add per ring reset support (v5)

2024-07-25 Thread Alex Deucher
If a specific job is hung, try and reset just the ring associated with the job. v2: move to amdgpu_job.c v3: fix drm_sched_stop() handling when ring reset fails v4: drop unnecessary amdgpu_fence_driver_clear_job_fences() and drm_sched_increase_karma() v5: rework sched_stop handling Signed-off

[PATCH 20/53] drm/amdgpu/gfx9: add ring reset callback

2024-07-25 Thread Alex Deucher
Add ring reset callback for compute. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 38 +++ 1 file changed, 38 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 675a1a8e2515..78495df29

[PATCH 09/53] drm/amdgpu: add new ring reset callback

2024-07-25 Thread Alex Deucher
Use this to reset just a single ring. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h index 582053f1cd56..c7f15edeb367 100644 --- a/

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