Ensure there is no address overlapping.
Reported-by: Vlad Stolyarov
Signed-off-by: xinhui pan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 8af3f0fd3073.
From: Xiaogang Chen
When kfd/amdgpu driver is tearing down cannot handle callback from
ih_wq. If there is still work items left cancle them instead of flush
that would wait until they got served.
Signed-off-by: Xiaogang Chen
---
drivers/gpu/drm/amd/amdkfd/kfd_interrupt.c | 7 ---
1 file cha
Hi Dave, Sima,
Fixes for 6.9. Two weeks worth. There is a fairly big update for SMU 14.0.1,
but that is a new IP for 6.9 so it should be isolated to that.
The following changes since commit 718c4fb221dbeff9072810841b949413c5ffc345:
nouveau: fix devinit paths to only handle display on GSP. (2
The comment here states "no OGAM in DPP since DCN1", yet that is not
true.
Testing on an RX 7900XTX (dcn32), it actually does exist in hardware and
works fine.
My best guess is the comment is confused with OGAM ROM for DPP, rather
than OGAM RAM.
I did not test dcn35/351 as I do not have that hard
Fill ring buffer before offload.
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.
From: Aric Cyr
This version brings along following fixes:
* Expand dmub_cmd operations.
* Update DVI configuration.
* Modify power sequence.
* Enable Z10 flag for IPS.
* Multiple code cleanups.
Acked-by: Rodrigo Siqueira
Signed-off-by: Aric Cyr
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
Add some missing registers expansion in the dcn201_link_encoder file.
Signed-off-by: Rodrigo Siqueira
---
.../amd/display/dc/dcn201/dcn201_link_encoder.h| 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encode
From: Sung Joon Kim
Rework part of the modifications made to the power sequence and resource
allocation logic.
Reviewed-by: Xi (Alex) Liu
Acked-by: Rodrigo Siqueira
Signed-off-by: Sung Joon Kim
---
.../amd/display/dc/hwss/dcn351/dcn351_init.c | 8 ++---
.../dc/resource/dcn351/dcn351_resour
From: Eric Bernstein
[Why] Update FMT_CONTROL settings based on HW spec
[How] Update FMT settings for 4:2:0
Signed-off-by: Eric Bernstein
Reviewed-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 9 -
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h | 2 ++
This commit remove some unused code and also rename one of the define.
Signed-off-by: Rodrigo Siqueira
---
.../drm/amd/display/dc/dcn10/dcn10_stream_encoder.h| 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encod
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dc_types.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h
b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 614d7c27c759..0f66d00ef80f 100644
--- a/drivers/gpu/drm/amd/display/dc/d
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index ee6493a9a79c..5c7e4884cac2 100644
--- a/
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.c
b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_hubbub.c
index a046664e2031..c1959672df50 100644
---
This commit groups many parts of the code that are redundant or not used
and drops all of them.
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dc.h| 1 -
.../gpu/drm/amd/display/dc/dce/dce_i2c_hw.c| 3 ---
.../amd/display/dc/dcn10/dcn10_link_encoder.h | 6
From: Anthony Koo
Update dmub_cmd to manipulate SDP control in replay FSM, add command
for panel_cntl, expand link rate enum, and increase the reserve byte.
Acked-by: Rodrigo Siqueira
Signed-off-by: Anthony Koo
---
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 53 ++-
1 file
This commit updates some comments to be more precise and adds another
small comment to some other parts to improve the code readability.
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/dc.h | 10 +-
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h |
From: Mikita Lipski
[why]
Driver was passing a wrong command version which to DMCUB which caused
the DMCUB to treat it as 0, so it wouldn't support dual eDP and would
override the panel index to 0 instead of choosing between 0/1.
[how]
Use DMUB_CMD_PSR_CONTROL_VERSION_1 instead of PSR_VERSION_1.
From: "Bitnun, Ethan"
The previous assumption that there will be an optimize_bandwidth call
following every prepare_bandwidth call was incorrect and caused small
inaccuracies in logging, as some info was only updated in later prepare
calls.
Signed-off-by: Ethan Bitnun
Reviewed-by: Rodrigo Sique
The chip ID DEVICE_ID_NV_13FE is not meaningful and represents a legacy
way of dealing with chip ID. This commit uses dc_version instead of
chip_id and also DCN_VERSION_2_01 instead of DEVICE_ID_NV_13FE.
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 2 +-
Move the scl_data.format to be close to other similar parts.
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
b/drivers/gpu/drm/amd/dis
From: Sung Joon Kim
[why]
IPS FSM requires Z10 flag to be enabled to do save and restore the
registers properly.
[how]
Enable Z10 and use the correct function to determine Z10 capability
Reviewed-by: Nicholas Kazlauskas
Acked-by: Rodrigo Siqueira
Signed-off-by: Sung Joon Kim
---
.../gpu/drm
Update headers by removing two unecessary headers and include a new one.
Signed-off-by: Rodrigo Siqueira
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c | 1 +
drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c| 3 ---
.../gpu/drm/amd/display/dc/dcn30/dcn30_dio_st
From: Chaitanya Dhere
[Why]
Pointer initialization and assignment for dml2_options is not done
correctly. While this works for some compilers, others give an error.
[How]
Modify dc_state_create code to correctly initialize the dml2_opt pointer
and pass it to dml2_create. Also update the code wit
From: Nicholas Kazlauskas
[Why]
IPS ono sequence ordering differs based on the ASIC.
[How]
Detect the ASIC ID revision and set the boot option accordingly. Feed
it through the DCN35 DMUB functions.
Reviewed-by: Sung joon Kim
Acked-by: Rodrigo Siqueira
Signed-off-by: Nicholas Kazlauskas
---
From: Charlene Liu
Limit the code change for ips enable to reduce the impact for now. Also
exit_ips first before dc_power_down to avoid 0x9f.
Reviewed-by: Chris Park
Acked-by: Rodrigo Siqueira
Signed-off-by: Charlene Liu
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 7 ++-
1 file change
From: Samson Tam
[Why]
Adding support for chroma subsampling offset (cositing) in scaler
calculations to adjust reference point where we determine post-scaling
chroma value in YUV420 surfaces.
[How]
Add support for cositing options: NONE, LEFT and TOPLEFT Add debug
option force_cositing and set
From: Chris Park
[Why]
DVI is TMDS signal like HDMI but without audio. Current signal check
does not correctly reflect DVI clock programming.
[How]
Define a new signal check for TMDS that includes DVI to HDMI TMDS
programming.
Reviewed-by: Dillon Varone
Acked-by: Rodrigo Siqueira
Signed-off-
From: Sung Joon Kim
To reduce the complexity of pipe resource allocation for different
use-cases, now we search for any free pipe sequentially rather than from
bottom up.
Reviewed-by: Wenjing Liu
Acked-by: Rodrigo Siqueira
Signed-off-by: Sung Joon Kim
---
.../dc/resource/dcn32/dcn32_resource
From: Sung Joon Kim
Need to update the power sequence to help prevent potential issues like
multi-display or multi-plane.
Reviewed-by: Duncan Ma
Acked-by: Rodrigo Siqueira
Signed-off-by: Sung Joon Kim
---
drivers/gpu/drm/amd/display/dc/hwss/Makefile | 2 +-
.../drm/amd/display/dc/hwss/dcn
This DC patchset brings improvements in multiple areas. In summary, we
have:
* Expand dmub_cmd operations.
* Update DVI configuration.
* Modify power sequence.
* Enable Z10 flag for IPS.
* Multiple code cleanups.
Cc: Daniel Wheeler
Thanks
Siqueira
Anthony Koo (1):
drm/amd/display: Expand dm
[AMD Official Use Only - General]
> -Original Message-
> From: amd-gfx On Behalf Of Felix
> Kuehling
> Sent: Wednesday, April 10, 2024 4:05 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Chen, Xiaogang
> Subject: [PATCH] drm/amdkfd: Fix memory leak in create_process failure
>
> Caution: Th
[AMD Official Use Only - General]
Tested-by: Harish Kasiviswanthan
-Original Message-
From: amd-gfx On Behalf Of Felix
Kuehling
Sent: Wednesday, April 10, 2024 4:05 PM
To: amd-gfx@lists.freedesktop.org
Cc: Chen, Xiaogang
Subject: [PATCH] drm/amdkfd: Fix memory leak in create_process f
Fix memory leak due to a leaked mmget reference on an error handling
code path that is triggered when attempting to create KFD processes
while a GPU reset is in progress.
Fixes: 0ab2d7532b05 ("drm/amdkfd: prepare per-process debug enable and disable")
CC: Xiaogang Chen
Signed-off-by: Felix Kuehli
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 6ebf211bb11dfc004a2ff73a9de5386fa309c430 Add linux-next specific
files for 20240410
Error/Warning reports:
https://lore.kernel.org/oe-kbuild-all/202404102353.cv1gujk3-...@intel.com
Error
Adding initial set of registers for ipdump during
devcoredump starting with gfx10 gc registers.
ip dump is triggered when gpu reset happens via
devcoredump and the memory is allocated by each
ip and is freed once the dump is complete by
devcoredump.
Signed-off-by: Sunil Khatri
---
drivers/gpu/d
Add the prototype for all the ips of different
asics and set them to NULL for now and based on
the need will keep adding the function for each
ip eventually.
Signed-off-by: Sunil Khatri
---
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
Adding infrastructure needed for ipdump along
with dumping gfx10 registers.
Sunil Khatri (2):
drm/amdgpu: add prototype to dump ip state
drm/amdgpu: Add support of gfx10 register dump
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 16 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 1
On 08/04/2024 16:16, Arunpravin Paneer Selvam wrote:
- Add tracking clear page feature.
- Driver should enable the DRM_BUDDY_CLEARED flag if it
successfully clears the blocks in the free path. On the otherhand,
DRM buddy marks each block as cleared.
- Track the available cleared pages siz
When slice_height is 0, the division by slice_height in the calculation
of the number of slices will cause a division by zero driver crash. This
leaves the kernel in a state that requires a reboot. This patch adds a
check to avoid the division by zero.
The stack trace below is for the 6.8.4 Kernel
On 4/8/2024 9:23 PM, Alex Deucher wrote:
> On Mon, Apr 8, 2024 at 9:45 PM Kees Cook wrote:
>>
>>
>>
>> On April 8, 2024 5:45:29 PM PDT, Jeff Johnson
>> wrote:
>>> On 10/1/23 17:12, Justin Piszcz wrote:
>>
>>
On Mon, Apr 08, 2024 at 01:37:48PM -0400, Alex Deucher wrote:
> Convert a variable sized array from [1] to [].
>
> v2: fix up a few more.
>
> Acked-by: Christian König (v1)
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/radeon/pptable.h | 6 +++---
> 1 file changed, 3 insertions(+), 3 d
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