[Public]
> -Original Message-
> From: Wentland, Harry
> Sent: Monday, October 4, 2021 10:48 PM
> To: Lin, Wayne ; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Kazlauskas, Nicholas
> ; Siqueira, Rodrigo
> ; Wang, Chao-kai (Stylon) ;
> Shih, Jude ; Kizito, Jimmy
> ; Somasundar
On 10/5/2021 10:34 AM, Powell, Darren wrote:
[AMD Official Use Only]
I'm just looking to clarify this code. The macro eventually expands to
look like this
if ((smu)->ppt_funcs)
{
if ((smu)->ppt_funcs->get_power_limit)
(smu)->ppt_funcs->get_power_limit(smu,
[AMD Official Use Only]
I'm just looking to clarify this code. The macro eventually expands to look
like this
if ((smu)->ppt_funcs)
{
if ((smu)->ppt_funcs->get_power_limit)
(smu)->ppt_funcs->get_power_limit(smu,
&smu->current_powe
On 10/04, Alex Deucher wrote:
> Was missing the IP version check for green sardine.
>
> Fixes: db95b2bd598d1a ("drm/amdgpu/amdgpu_smu: convert to IP version
> checking")
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 1 +
> 1 file changed, 1 insertion(+)
>
>
On 10/04, Alex Deucher wrote:
> MP1 IP version is different on newer silicon revisions. Check
> for both revisions.
>
> Fixes: db95b2bd598d1a ("drm/amdgpu/amdgpu_smu: convert to IP version
> checking")
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 3 ++-
> 1
Was missing the IP version check for green sardine.
Fixes: db95b2bd598d1a ("drm/amdgpu/amdgpu_smu: convert to IP version checking")
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_sm
MP1 IP version is different on newer silicon revisions. Check
for both revisions.
Fixes: db95b2bd598d1a ("drm/amdgpu/amdgpu_smu: convert to IP version checking")
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
di
[AMD Official Use Only]
Hi Flelix,
I have tested YiFan's patch and pco s3 test can pass.
The original s3 issue always occurred on resume, And YiFan's patches
are only related to initialization.
Hi YiFan,
Reviewed-by: James Zhu for the series
Tested-by: James Zhu for the series
Thanks & B
On 2021-10-02 11:18 a.m., Guchun Chen wrote:
In current code, when a PCI error state pci_channel_io_normal is detectd,
it will report PCI_ERS_RESULT_CAN_RECOVER status to PCI driver, and PCI
driver will continue the execution of PCI resume callback report_resume by
pci_walk_bridge, and the call
I see my confusion, we hang all unsubmitted jobs on the last submitted
to HW job.
Yea, in this case indeed rescheduling to a different thread context will
avoid the splat but
the schedule work cannot be done for each dependency signalling but
rather they way we do
for ttm_bo_delayed_delete with
I'm trying to understand what the end result is after James' and your
patches. If I'm reading it correctly, we now initialize IOMMUv2 after
kfd_device_init during initialization, but before kfd_device_init during
resume from S3. Is that the correct understanding?
My concern is, that we may run in
On 2021-10-04 10:40, Wayne Lin wrote:
> These series patches are for supporting USB4 DP tunneling feature.
>
Can you provide a description (with or without diagrams) of what
DP4 tunneling is and some of the key parts of how it works?
Does this patchset have dependencies on patches in the USB
From: Jude Shih
[Why]
YELLOW_CARP_B0 address was not correct
[How]
Set YELLOW_CARP_B0 to 0x1A.
Reviewed-by: Nicholas Kazlauskas
Acked-by: Wayne Lin
Signed-off-by: Jude Shih
---
drivers/gpu/drm/amd/display/include/dal_asic_id.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --gi
From: Jude Shih
[Why]
Condition variable sometimes terminated unexpectedly
[How]
Use wait_for_completion_timeout to avoid unexpected termination of CV
Reviewed-by: Nicholas Kazlauskas
Acked-by: Wayne Lin
Signed-off-by: Jude Shih
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++-
From: Jude Shih
[why]
1. HPD callback function has deadlock problem
2. HPD status is not assigned
3. There is crash due to null pointer
4. link_enc is NULL in DPIA case
[How]
1. Fix deadlock problem by moving it out of the
drm_modeset_lock
2. Assign HPD status from the notify of outbox
fro
From: Meenakshikumar Somasundaram
[Why & How]
Add codes for commit "b693dfe24d61 drm/amd/display: Fix for null
pointer access for ddc pin and aux engine" to take USB4 feature
into account.
Reviewed-by: Jimmy Kizito
Acked-by: Wayne Lin
Acked-by: Nicholas Kazlauskas
Signed-off-by: Meenakshikuma
From: Jimmy Kizito
[Why & How]
Additional debug flags that can be useful for testing USB4 DP
link training.
Add flags:
- 0x2 : Forces USB4 DP link to non-LTTPR mode
- 0x4 : Extends status read intervals to about 60s.
Reviewed-by: Meenakshikumar Somasundaram
Reviewed-by: Jun Lei
Acked-by: Wayn
From: Jimmy Kizito
[Why]
DIB_BE_CNTL.DIG_HPD_SELECT selects the HPD block being used
by the display endpoint assigned to DIG. In the case of USB4
display endpoints, no physical HPD block is assigned.
[How]
Setting DIB_BE_CNTL.DIG_HPD_SELECT to 5 indicates that no HPD
is assigned to a display end
From: Jude Shih
[Why]
To process SET_CONFIG transactions with DMUB using inbox1 and
outbox1 mail boxes.
[How]
1) DMUB posts SET_CONFIG reply as an Outbox1 message of type
DMUB_OUT_CMD__SET_CONFIG_REPLY.
2) The dmub async to sync mechanism for AUX is modified to accommodate
SET_CONFIG comma
From: Meenakshikumar Somasundaram
[Why & How]
To add support for dpia debug options.
Reviewed-by: Jimmy Kizito
Acked-by: Wayne Lin
Acked-by: Nicholas Kazlauskas
Signed-off-by: Meenakshikumar Somasundaram
---
drivers/gpu/drm/amd/display/dc/dc.h | 9 +
drivers/gpu/dr
From: Jimmy Kizito
[Why]
We requires information from DPCD in order to identify USB4 DP
tunneling targets.
[How]
Add USB4 DP tunneling fields to DPCD struct and populate these fields
during sink detection.
Reviewed-by: Jun Lei
Acked-by: Wayne Lin
Acked-by: Nicholas Kazlauskas
Signed-off-by:
From: Meenakshikumar Somasundaram
[Why]
To process SET_CONFIG transactions with DMUB using inbox1 and
outbox1 mail boxes.
[How]
1) Added inbox1 DPIA command subtype DMUB_CMD__DPIA_SET_CONFIG_ACCESS to
issue SET_CONFIG command to DMUB in dc_process_dmub_set_config_async().
DMUB processes th
From: Jimmy Kizito
[Why & How]
Clear training pattern sequence for hop in display path once clock
recovery and equalization phases of DP tunnel link training completed.
Reviewed-by: Jun Lei
Acked-by: Wayne Lin
Acked-by: Nicholas Kazlauskas
Signed-off-by: Jimmy Kizito
---
.../gpu/drm/amd/dis
From: Jimmy Kizito
[Why]
Equalisation is the mandatory second phase of DisplayPort link training
over a USB4 DP tunnel.
[How]
Implement equalisation phase for DP tunneled over USB4 in DPIA
training module.
Reviewed-by: Jun Lei
Acked-by: Wayne Lin
Acked-by: Nicholas Kazlauskas
Signed-off-by:
From: Jimmy Kizito
[Why]
Clock recovery is the mandatory first phase of DP link training.
[How]
- Implement clock recovery phase in DPIA training module.
- Add helper functions for building SET_CONFIG messages.
Reviewed-by: Jun Lei
Acked-by: Wayne Lin
Acked-by: Nicholas Kazlauskas
Signed-off
From: Jimmy Kizito
[Why]
Training settings need to be applied to DPIA link at start of each
training loop. Note: FEC readiness should be configured before link
training while FEC enablement should be configured once training is
complete.
[How]
- Implement DPIA link configuration function.
- Acco
From: Jimmy Kizito
[Why]
Training of DPIA link differs enough from that of conventional
DP link to warrant a separate implementation.
[How]
- Implement top-level of DPIA training loop.
- Make functions shared between DP and DPIA link training "public".
Reviewed-by: Jun Lei
Acked-by: Wayne Lin
From: Jimmy Kizito
[Why & How]
Add codes for commit "822536713066 drm/amd/display: Add fallback
and abort paths for DP link training" to support USB4 DP tunneling
feature
Reviewed-by: Jun Lei
Acked-by: Wayne Lin
Acked-by: Nicholas Kazlauskas
Signed-off-by: Jimmy Kizito
---
drivers/gpu/drm/a
From: Jimmy Kizito
[why & how]
Add codes for commit "ede4f6dac99e drm/amd/display: Update
setting of DP training parameters." to support USB4 DP tunneling
feature
Reviewed-by: Jun Lei
Acked-by: Wayne Lin
Acked-by: Nicholas Kazlauskas
Signed-off-by: Jimmy Kizito
---
drivers/gpu/drm/amd/displ
From: Jimmy Kizito
[why & how]
Add codes for commit "99732e52e7f8 drm/amd/display: Update DPRX detection"
to support USB4 DP tunneling feature
Reviewed-by: Jun Lei
Acked-by: Wayne Lin
Acked-by: Nicholas Kazlauskas
Signed-off-by: Jimmy Kizito
---
drivers/gpu/drm/amd/display/dc/Makefile
From: Jimmy Kizito
[why & how]
Add codes for commit "79ed7354d70f drm/amd/display: Update
display endpoint control path" to support USB4 DP tunneling
feature.
Reviewed-by: Jun Lei
Acked-by: Wayne Lin
Acked-by: Nicholas Kazlauskas
Signed-off-by: Jimmy Kizito
---
.../gpu/drm/amd/display/dc/co
From: Jimmy Kizito
[why & how]
Add codes for commit "f42ef862fb1f drm/amd/display: Add dynamic
link encoder selection" to support USB4 DP tunneling feature.
Reviewed-by: Jun Lei
Acked-by: Wayne Lin
Acked-by: Nicholas Kazlauskas
Signed-off-by: Jimmy Kizito
---
drivers/gpu/drm/amd/display/dc/
From: Meenakshikumar Somasundaram
[WHY]
To add support for HPD & HPD RX interrupt handling for USB4 DPIA in
YELLOW_CARP_B0. USB4 DPIA HPD & HPD RX interrupts are issued from DMUB to
driver as a outbox1 message.
[HOW]
1) Created get_link_index_from_dpia_port_index() to retrieve link index
from
From: Meenakshikumar Somasundaram
[WHY]
To enable dc links for USB4 DPIA ports and AUX command tunneling
for YELLOW_CARP_B0.
[HOW]
1) Created dc links for all USB4 DPIA ports in create_links().
dc_link_construct() implementation is split for legacy DDC and DPIAs.
As usb4 has no ddc, ddc->d
From: Jimmy Kizito
[Why & How]
Add codes for commit "e1f4328f22c0 drm/amd/display: Update link
encoder object creation" to support USB4 DP tunneling feature
Reviewed-by: Jun Lei
Acked-by: Wayne Lin
Acked-by: Nicholas Kazlauskas
Signed-off-by: Jimmy Kizito
---
drivers/gpu/drm/amd/display/dc/
These series patches are for supporting USB4 DP tunneling feature.
---
Jimmy Kizito (14):
drm/amd/display: Update link encoder object creation.
drm/amd/display: Support USB4 dynamic link encoder selection.
drm/amd/display: Support USB4 for display endpoint control path.
drm/amd/display: S
On 2021-10-01 15:56, Sean Paul wrote:
> On Wed, Sep 29, 2021 at 03:39:26PM -0400, Mark Yacoub wrote:
>> From: Mark Yacoub
>>
>> [Why]
>> drm_atomic_helper_check_crtc now verifies both legacy and non-legacy LUT
>> sizes. There is no need to check it within amdgpu_dm_atomic_check.
>>
>> [How]
>>
Acked-by: Alex Deucher
On Mon, Oct 4, 2021 at 4:31 AM Christian König
wrote:
>
> Ping? Alex any objections to this?
>
> Otherwise I'm going to push it with Nirmoy's acked-by.
>
> Christian.
>
> Am 30.09.21 um 11:26 schrieb Christian König:
> > This reverts commit 728e7e0cd61899208e924472b9e641db
[Public]
Hi all,
This week this patchset was tested on the following systems:
HP Envy 360, with Ryzen 5 4500U, with the following display types: eDP 1080p
60hz, 4k 60hz (via USB-C to DP/HDMI), 1440p 144hz (via USB-C to DP/HDMI),
1680*1050 60hz (via USB-C to DP and then DP to DVI/VGA)
AMD
On 10/3/2021 10:16 AM, Darren Powell wrote:
Code appears to initialize values but macro will exit without error
or initializing value if function is not implmented
Signed-off-by: Darren Powell
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 4
1 file changed, 4 insertions(+)
diff --
On 10/3/2021 10:16 AM, Darren Powell wrote:
modify (pptable_funcs)->set_power_limit signature
modify smu11 set_power_limit signature (arcturus, navi10, sienna_cichlid)
modify smu13 set_power_limit signature (aldabaran)
modify vangogh_set_power_limit signature (vangogh)
=== Test ===
su
[AMD Official Use Only]
Hi Felix,
After sync w/ James, we agree that this patch series could fix both our
problems, and he verified this patch series will not cause regression of his
previous issue. Do you have more comments regarding this patch series ? Thanks.
BRs,
Yifan
From: Zhu, James
S
On Mon, 04 Oct 2021, Ville Syrjälä wrote:
> On Sun, Oct 03, 2021 at 12:32:14AM +0200, Fernando Ramos wrote:
>> On 21/10/02 09:13AM, Fernando Ramos wrote:
>> >
>> > Sean, could you revert the whole patch series? I'll have a deeper look
>> > into the
>> > patch set and come up with a v3 where all
Ping? Alex any objections to this?
Otherwise I'm going to push it with Nirmoy's acked-by.
Christian.
Am 30.09.21 um 11:26 schrieb Christian König:
This reverts commit 728e7e0cd61899208e924472b9e641dbeb0775c4.
Further discussion reveals that this feature is severely broken
and needs to be reve
Am 01.10.21 um 21:48 schrieb Alex Deucher:
Depends on DRM_AMDGPU_SI and DRM_AMD_DC
Signed-off-by: Alex Deucher
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/display/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/Kconfig
b/drivers/gpu/dr
Am 01.10.21 um 21:48 schrieb Alex Deucher:
Use IP versions rather than asic_type to differentiate
IP version specific features.
Signed-off-by: Alex Deucher
Acked-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 136 ++
1 file changed, 71 insertions
On Sun, Oct 03, 2021 at 12:32:14AM +0200, Fernando Ramos wrote:
> On 21/10/02 09:13AM, Fernando Ramos wrote:
> >
> > Sean, could you revert the whole patch series? I'll have a deeper look into
> > the
> > patch set and come up with a v3 where all these issues will be addressed.
> >
>
> Hi Sean,
The problem is a bit different.
The callback is on the dependent fence, while we need to signal the
scheduler fence.
Daniel is right that this needs an irq_work struct to handle this properly.
Christian.
Am 01.10.21 um 17:10 schrieb Andrey Grodzovsky:
From what I see here you supposed to hav
On Sat, Oct 02, 2021 at 07:28:02PM +0200, Fernando Ramos wrote:
> On 21/10/02 09:13AM, Fernando Ramos wrote:
> > On 21/10/02 05:30AM, Ville Syrjälä wrote:
> > > On Sat, Oct 02, 2021 at 01:05:47AM +0300, Ville Syrjälä wrote:
> > > > On Fri, Oct 01, 2021 at 04:48:15PM -0400, Sean Paul wrote:
> > > >
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