Thanks for explaining this, one thing I still don't understand is why
you schedule the reset work explicilty in the begining of
amdgpu_drv_delayed_reset_work_handler and then also call
amdgpu_do_asic_reset which will do the same thing too. It looks like the
physical reset will execute twice for
[AMD Official Use Only - Internal Distribution Only]
Instead of mixing to recover workflow, can this be separated out to something
like early_reset().
Thanks,
Lijo
From: amd-gfx on behalf of shaoyunl
Sent: Friday, March 5, 2021 11:21:49 PM
To: amd-gfx@lists.fr
[AMD Public Use]
Thanks Lyude for testing the patch.
Are you referring to this issue [1] ?
Is it reproducible after applying this patch as well ?
[1] https://gitlab.freedesktop.org/drm/amd/-/issues/1473
-- Anson
From: Lyude Paul
Sent: Friday, March 5, 2021 6:0
[AMD Official Use Only - Internal Distribution Only]
Hi, Andrey
The existing reset function (amdgpu_device_gpu_recover or amd do_asic _reset)
assumed driver already have the correct hive info . But in my case, it's not
true . The gpus are in a bad state and the XGMI TA might not functional
On 2/11/2021 7:34 AM, Daniel Vetter wrote:
> On Wed, Feb 10, 2021 at 02:00:57PM -0800, Brian Welty wrote:
>>
>> On 2/9/2021 2:54 AM, Daniel Vetter wrote:
>>> On Tue, Jan 26, 2021 at 01:46:25PM -0800, Brian Welty wrote:
This patch adds tracking of which cgroup to make charges against for a
>>
Tested-by: Lyude Paul
That just leaves the KASAN error from read_indirect_azalia_reg, thanks for the
fix!
On Thu, 2021-03-04 at 15:08 -0500, Anson Jacob wrote:
> If get_num_sdma_queues or get_num_xgmi_sdma_queues is 0, we end up
> doing a shift operation where the number of bits shifted equals
>
[AMD Official Use Only - Internal Distribution Only]
> -Original Message-
> From: Christian König
> Sent: Friday, March 5, 2021 3:18 PM
> To: Kim, Jonathan ; amd-
> g...@lists.freedesktop.org
> Cc: Yang, Philip ; Kuehling, Felix
> ; Koenig, Christian
> Subject: Re: [PATCH] drm/amdgpu: ad
[AMD Public Use]
Hi all,
This week this patchset was tested on a HP Envy 360, with Ryzen 5 4500U, on the
following display types (via usb-c to dp/dvi/hdmi/vga):
4k 60z, 1440p 144hz, 1680*1050 60hz, internal eDP 1080p 60hz
Tested on a Sapphire Pulse RX5700XT on the following display types (via D
Am 05.03.21 um 21:11 schrieb Jonathan Kim:
Add IH function to allow caller to wait until ring entries are processed
until the checkpoint write pointer.
This will be primarily used by HMM to drain pending page fault interrupts
before memory unmap to prevent HMM from handling stale interrupts.
v2
Add IH function to allow caller to wait until ring entries are processed
until the checkpoint write pointer.
This will be primarily used by HMM to drain pending page fault interrupts
before memory unmap to prevent HMM from handling stale interrupts.
v2: Update title and description to clarify use
From: Joshua Aberback
[Why]
The registers for the address of the cursor are aligned to 2KB, so all
cursor surfaces also need to be aligned to 2KB. Currently, the
provided cursor cache surface is not aligned, so we need a workaround
until alignment is enforced by the surface provider.
[How]
- ro
From: Sung Lee
[WHY & HOW]
Using values provided by DF for latency may cause hangs in
multi display configurations. Revert change to previous value.
Signed-off-by: Sung Lee
Reviewed-by: Haonan Wang
Acked-by: Eryk Brol
---
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 2 +-
1 file c
From: Aric Cyr
DC version 3.2.126 brings improvements in multiple areas.
In summary, we highlight:
- DMUB fixes
- Firmware relase 0.0.55
- Expanded dmub_cmd documentation
- Enhancements in DCN30
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Eryk Brol
---
drivers/gpu/drm/amd/displa
From: Jake Wang
[Why]
Panel control always programs instance 0. With multi eDP we need to
support multiple instances.
[How]
Use link index to set different instances for panel control.
Refactored LVTMA control to support multiple instances.
Signed-off-by: Jake Wang
Reviewed-by: Aric Cyr
Acked
From: Anthony Koo
Add comments to better describe the function of different cmds
and parameters in the dmub interface
Signed-off-by: Anthony Koo
Reviewed-by: Anthony Koo
Acked-by: Eryk Brol
---
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 834 +-
1 file changed, 795 insert
From: Yongqiang Sun
[Why]
Driver get wrap around dmub trace data due to read pointer being
increased incorrectly when there are multiple interrupt
queues with very short interval
[How]
Check read/write pointer before copying data from ring buffer
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony
From: Qingqing Zhuo
[Why]
- Wrong scope for ifdef
- Missing struct description
[How]
Move ifdef and add comment
Signed-off-by: Qingqing Zhuo
Reviewed-by: Nicholas Kazlauskas
Acked-by: Eryk Brol
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +++--
drivers/gpu/drm/amd/display/amd
From: Qingqing Zhuo
[Why]
pflip interrupt would not be enabled promptly if a pipe is disabled
and re-enabled, causing flip_done timeout error during DP
compliance tests
[How]
Enable pflip interrupt upon pipe enablement
Signed-off-by: Qingqing Zhuo
Reviewed-by: Nicholas Kazlauskas
Acked-by: Er
From: Yongqiang Sun
[Why]
If interval of two interrupt from dmub outbox0 is too short,
some event might be skipped
[How]
Compare read pointer and write pointer until all the event
entry is processed
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Eryk Brol
---
.../gpu/drm/amd
From: Martin Leung
[why]
In some boot configurations we need to retrieve the currently
UEFI-set dppclk, but there was a typo in the calculation
[how]
Fix typo to make dpp_clk calculate off dpp_clk divider instead of
disp_clk
Signed-off-by: Martin Leung
Reviewed-by: Sung Lee
Acked-by: Eryk Bro
From: Yongqiang Sun
[Why & How]
Reference to read pointer which is incorrect.
Change to reference to write pointer.
Signed-off-by: Yongqiang Sun
Reviewed-by: Tony Cheng
Acked-by: Eryk Brol
---
drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(
From: Yongqiang Sun
[Why & How]
Fix linux compile error
Signed-off-by: Yongqiang Sun
Reviewed-by: Nicholas Kazlauskas
Acked-by: Eryk Brol
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 12
drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 5 ++---
2 files changed, 14 ins
From: Martin Leung
[Why]
On baco-enabled systems running virtual dal, can get set power
state when hw is not initialized
[How]
Skip DC hw part of setPowerState when hw not available
Signed-off-by: Martin Leung
Reviewed-by: Aric Cyr
Acked-by: Eryk Brol
---
drivers/gpu/drm/amd/display/dc/core
From: Dillon Varone
[Why & How]
Ported logic from dcn21 for reading in pipe fusing to dcn30.
Supported configurations are 1 and 6 pipes. Invalid fusing
will revert to 1 pipe being enabled.
Signed-off-by: Dillon Varone
Reviewed-by: Jun Lei
Acked-by: Eryk Brol
---
.../drm/amd/display/dc/dcn30/
This DC patchset brings improvements in multiple areas.
In summary we highlight:
* DMUB fixes
* Firmware relase 0.0.55
* Expanded dmub_cmd documentation
* Enhancements in DCN30
Anthony Koo (1):
drm/amd/display: [FW Promotion] Release 0.0.55
Aric Cyr (1):
drm/amd/display: 3.2.126
Dillon Var
On 2021-03-05 12:52 p.m., shaoyunl wrote:
In passthrough configuration, hypervisior will trigger the SBR(Secondary bus
reset) to the devices
without sync to each other. This could cause device hang since for XGMI
configuration, all the devices
within the hive need to be reset at a limit time
On Fri, Mar 05, 2021 at 02:10:44PM -0500, Alex Deucher wrote:
> Applied. Thanks!
Awesome. :)
Thanks, Alex.
--
Gustavo
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
On Fri, Mar 5, 2021 at 9:23 AM Holger Hoffstätte
wrote:
>
> After fixing nested FPU contexts caused by 41401ac67791 we're still seeing
> complaints about spurious kernel_fpu_end(). As it turns out this was
> already fixed for dcn20 in commit f41ed88cbd ("drm/amdgpu/display:
> use GFP_ATOMIC in dcn
On Fri, Mar 5, 2021 at 6:39 AM Holger Hoffstätte
wrote:
>
>
> Commit 41401ac67791 added FPU wrappers to dcn21_validate_bandwidth(),
> which was correct. Unfortunately a nested function alredy contained
> DC_FP_START()/DC_FP_END() calls, which results in nested FPU context
> enter/exit and complain
The same patch was already applied a while ago.
Thanks,
Alex
On Fri, Mar 5, 2021 at 1:41 AM Jiapeng Chong
wrote:
>
> Fix the following coccicheck warnings:
>
> ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:8257:16-21: WARNING:
> conversion to bool not needed here.
>
> Reported-by: Abaci R
Applied. Thanks!
Alex
On Wed, Mar 3, 2021 at 2:05 PM Gustavo A. R. Silva
wrote:
>
> There is a regular need in the kernel to provide a way to declare having
> a dynamically sized set of trailing elements in a structure. Kernel code
> should always use “flexible array members”[1] for these cases
Applied. thanks.
Alex
On Wed, Mar 3, 2021 at 8:25 AM Colin King wrote:
>
> From: Colin Ian King
>
> The continue statement in a for-loop is redudant and can be removed.
> Clean up the code to address this.
>
> Addresses-Coverity: ("Continue as no effect")
> Fixes: b6f91fc183f7 ("drm/amdgpu/dis
Applied. Thanks!
Alex
On Wed, Mar 3, 2021 at 9:07 AM Colin King wrote:
>
> From: Colin Ian King
>
> The variable status is being initialized with a value that is never read
> and it is being updated later with a new value. The initialization is
> redundant and can be removed.
>
> Addresses-Co
Applied. Thanks!
Alex
On Thu, Mar 4, 2021 at 3:02 AM Jiapeng Chong
wrote:
>
> Fix the following coccicheck warnings:
>
> ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:956:52-57: WARNING:
> conversion to bool not needed here.
>
> ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:8311:16-
It fixed an intermittent failure to allocate page tables in the page
fault handler (turning retry faults into no-retry faults). I'm not sure
if this caused real problems. I think it could potentially result in
fault storms and a failure to report page faults properly. I'm not sure
if it's a regress
In passthrough configuration, hypervisior will trigger the SBR(Secondary bus
reset) to the devices
without sync to each other. This could cause device hang since for XGMI
configuration, all the devices
within the hive need to be reset at a limit time slot. This serial of patches
try to solve thi
The gmc.xgmi.head list originally is designed for device list in the XGMI hive.
Mix use it
for reset purpose will prevent the reset function to adjust XGMI device list
which is required
in next change
Signed-off-by: shaoyunl
Change-Id: Ibbdf75c02836151adf5bb44186e6ced97dbf8c1d
---
drivers/gpu/
The MQD might not be initialized duirng first init period if the device need to
be reset
druing probe. Driver need to proper init them in gpu recovery period
Signed-off-by: shaoyunl
Acked-by: Alex Deucher
Change-Id: Iad58a050939af2afa46d1c74a90866c47ba9efd2
---
drivers/gpu/drm/amd/amdgpu/gfx_v
amdgpu driver may be in reset state during init which will not initialize the
kfd,
driver need to initialize the KFD after reset by check the flag
Signed-off-by: shaoyunl
Acked-by: Alex Deucher
Change-Id: Ic1684b55b27e0afd42bee8b9b431c4fb0afcec15
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
Driver need to get XGMI info function earlier before ip_init since driver need
to check
the XGMI setting to determine how to perform reset during init
Signed-off-by: shaoyunl
Acked-by: Alex Deucher
Change-Id: Ic37276bbb6640bb4e9360220fed99494cedd3ef5
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c |
The vmwgfx ones look all good to me, so for
23-53: Reviewed-by: Roland Scheidegger
That said, they were already signed off by Zack, so not sure what
happened here.
Roland
On 03.03.21 14:42, Lee Jones wrote:
> This is a resend. All of these patches have been sent before.
>
> The vmwgfx ones wer
Le 02/03/2021 à 21:01, Geert Uytterhoeven a écrit :
Hi Alex,
On Tue, Mar 2, 2021 at 8:30 PM Alex Deucher wrote:
On Mon, Mar 1, 2021 at 9:21 AM Geert Uytterhoeven wrote:
On Mon, 1 Mar 2021, Geert Uytterhoeven wrote:
Below is the list of build error/warning regressions/improvements in
v5.12
On 3/5/21 4:18 PM, Christian König wrote:
Am 05.03.21 um 15:48 schrieb Nirmoy:
On 3/5/21 3:37 PM, Christian König wrote:
Am 05.03.21 um 15:35 schrieb Nirmoy Das:
Allow allocating BO structures with different structure size
than struct amdgpu_bo.
Signed-off-by: Nirmoy Das
---
drivers/
Am 05.03.21 um 15:48 schrieb Nirmoy:
On 3/5/21 3:37 PM, Christian König wrote:
Am 05.03.21 um 15:35 schrieb Nirmoy Das:
Allow allocating BO structures with different structure size
than struct amdgpu_bo.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 ++
Am 05.03.21 um 15:35 schrieb Nirmoy Das:
Implement a new struct amdgpu_bo_user as subclass of
struct amdgpu_bo and a function to created amdgpu_bo_user
bo with a flag to identify the owner.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 28 ++
Am 05.03.21 um 16:06 schrieb Nirmoy Das:
Allow allocating BO structures with different structure size
than struct amdgpu_bo.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 10 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 1 +
2 files changed, 10 in
Am 05.03.21 um 15:35 schrieb Nirmoy Das:
These memebers are only needed for BOs created by amdgpu_gem_object_create(),
so we can remove these from the base class.
This patch must be squashed together with the previous one or we would
have a broken driver in between.
Christian.
CC:felix.ku
Am 05.03.21 um 15:35 schrieb Nirmoy Das:
This flag is only needed for BOs created by amdgpu_gem_object_create(),
so we can remove tiling_flags from the base class.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 19 +--
drivers/gpu/drm/amd/amdgpu
We might need to use this for the KFD as well.
Christian.
Am 05.03.21 um 15:35 schrieb Nirmoy Das:
GEM objects encapsulate amdgpu_bo for userspace applications.
Now that we have a new amdgpu_bo_user subclass for that purpose,
let's use that instead.
Signed-off-by: Nirmoy Das
---
drivers/gpu
[AMD Public Use]
Hi Anson,
Please ignore the earlier comment.
Thanks,
Lijo
-Original Message-
From: Lazar, Lijo
Sent: Friday, March 5, 2021 11:05 AM
To: Anson Jacob ; amd-gfx@lists.freedesktop.org
Cc: Jacob, Anson ; Deucher, Alexander
; Kuehling, Felix
Subject: RE: [PATCH] drm/amdkf
These members are only needed for BOs created by
amdgpu_gem_object_create(), so we can remove these from the
base class.
CC: felix.kuehl...@amd.com
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 2 -
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 48 +++
This flag is only needed for BOs created by amdgpu_gem_object_create(),
so we can remove tiling_flags from the base class.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 19 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 1 -
2 files changed, 17 ins
Implement a new struct amdgpu_bo_user as subclass of
struct amdgpu_bo and a function to created amdgpu_bo_user
bo with a flag to identify the owner.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 28 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h |
GEM objects encapsulate amdgpu_bo for userspace applications.
Now that we have a new amdgpu_bo_user subclass for that purpose,
let's use that instead.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/driv
Allow allocating BO structures with different structure size
than struct amdgpu_bo.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 10 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 1 +
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/
On 3/5/21 3:37 PM, Christian König wrote:
Am 05.03.21 um 15:35 schrieb Nirmoy Das:
Allow allocating BO structures with different structure size
than struct amdgpu_bo.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_object
Am 05.03.21 um 15:35 schrieb Nirmoy Das:
Allow allocating BO structures with different structure size
than struct amdgpu_bo.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 1 +
2 files changed, 3 insertions(+)
These memebers are only needed for BOs created by amdgpu_gem_object_create(),
so we can remove these from the base class.
CC:felix.kuehl...@amd.com
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 2 -
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 48 +++
GEM objects encapsulate amdgpu_bo for userspace applications.
Now that we have a new amdgpu_bo_user subclass for that purpose,
let's use that instead.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/driv
Implement a new struct amdgpu_bo_user as subclass of
struct amdgpu_bo and a function to created amdgpu_bo_user
bo with a flag to identify the owner.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 28 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h |
Allow allocating BO structures with different structure size
than struct amdgpu_bo.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_
This flag is only needed for BOs created by amdgpu_gem_object_create(),
so we can remove tiling_flags from the base class.
Signed-off-by: Nirmoy Das
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 19 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 1 -
2 files changed, 17 ins
After fixing nested FPU contexts caused by 41401ac67791 we're still seeing
complaints about spurious kernel_fpu_end(). As it turns out this was
already fixed for dcn20 in commit f41ed88cbd ("drm/amdgpu/display:
use GFP_ATOMIC in dcn20_validate_bandwidth_internal") but never moved
forward to dcn21.
On 2021-03-05 13:23, Holger Hoffstätte wrote:
On 2021-03-05 12:39, Holger Hoffstätte wrote:
Commit 41401ac67791 added FPU wrappers to dcn21_validate_bandwidth(),
which was correct. Unfortunately a nested function alredy contained
DC_FP_START()/DC_FP_END() calls, which results in nested FPU cont
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Sonny Jiang
From: Christian König
Sent: Friday, March 5, 2021 7:51 AM
To: dri-de...@lists.freedesktop.org ;
amd-gfx@lists.freedesktop.org
Cc: Liu, Leo ; Jiang, Sonny
Subject: [PATCH 2/2] drm/amd
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Sonny Jiang
From: Christian König
Sent: Friday, March 5, 2021 7:51 AM
To: dri-de...@lists.freedesktop.org ;
amd-gfx@lists.freedesktop.org
Cc: Liu, Leo ; Jiang, Sonny
Subject: [PATCH 1/2] drm/sch
Add VCN3 IB parsing to figure out to which instance we can send the
stream for decode.
v2: remove VCN instance limit as well, fix amdgpu_cs_find_mapping,
check supported formats instead of unsupported.
v3: fix typo and error handling
v4: make sure the message BO is CPU accessible
v5: fix addr
This is necessary when changing priorities of an entity.
v2: test the sched_list instead of num_sched.
v3: set the sched_list to NULL when there is only one entry
Signed-off-by: Christian König
---
drivers/gpu/drm/scheduler/sched_entity.c | 6 --
1 file changed, 4 insertions(+), 2 deletions
[AMD Public Use]
Reviewed-by: Hawking Zhang
Per discussion, please work with Anna to identify the potential risk in SRIOV
guest driver (VEGA10) before pushing the patch. Thanks.
Regards,
Hawking
-Original Message-
From: Feifei Xu
Sent: Friday, March 5, 2021 17:10
To: amd-gfx@lists.fr
On 2021-03-05 12:39, Holger Hoffstätte wrote:
Commit 41401ac67791 added FPU wrappers to dcn21_validate_bandwidth(),
which was correct. Unfortunately a nested function alredy contained
DC_FP_START()/DC_FP_END() calls, which results in nested FPU context
enter/exit and complaints by kernel_fpu_beg
Fix the following coccicheck warnings:
./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:8257:16-21: WARNING:
conversion to bool not needed here.
Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +--
1 file changed, 1 insertion(+
Commit 41401ac67791 added FPU wrappers to dcn21_validate_bandwidth(),
which was correct. Unfortunately a nested function alredy contained
DC_FP_START()/DC_FP_END() calls, which results in nested FPU context
enter/exit and complaints by kernel_fpu_begin_mask().
This can be observed e.g. with 5.10.
Commit 41401ac67791 added FPU wrappers to dcn21_validate_bandwidth(),
which was correct. Unfortunately a nested function alredy contained
DC_FP_START()/DC_FP_END() calls, which results in nested FPU context
enter/exit and complaints by kernel_fpu_begin_mask().
This can be observed e.g. with 5.10.
Hello Yongqiang Sun,
This is a semi-automatic email about new static checker warnings.
The patch 70732504c53b: "drm/amd/display: Implement dmub trace event"
from Feb 19, 2021, leads to the following Smatch complaint:
drivers/gpu/drm/amd/amdgpu/../display/dmub/src/dmub_srv.c:520
dmub_srv_hw
Am 05.03.21 um 10:04 schrieb Emily Deng:
If have memory leak, maybe it will have issue in
ttm_bo_force_list_clean-> ttm_mem_evict_first.
Set adev->gart.ptr to null to avoid to call
amdgpu_gmc_set_pte_pde to cause ptr issue pointer when
calling amdgpu_gart_unbind in amdgpu_bo_fini which is after
On 2021-03-04 7:26 p.m., Kazlauskas, Nicholas wrote:
> On 2021-03-04 10:35 a.m., Michel Dänzer wrote:
>> On 2021-03-04 4:09 p.m., Kazlauskas, Nicholas wrote:
>>> On 2021-03-04 4:05 a.m., Michel Dänzer wrote:
On 2021-03-03 8:17 p.m., Daniel Vetter wrote:
> On Wed, Mar 3, 2021 at 5:53 PM Mic
On 3/5/21 1:37 AM, Felix Kuehling wrote:
Am 2021-03-03 um 7:04 a.m. schrieb Christian König:
Am 03.03.21 um 10:25 schrieb Nirmoy Das:
Implement a new struct based on amdgpu_bo base class
for BOs created by kfd device so that kfd related memeber
of amdgpu_bo can be moved there.
You should prob
Remove the ECO_BITS programing in driver on gfxhub1.0,
mmhub1_x and mmhub_9.4.
Signed-off-by: Feifei Xu
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 1 -
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 1 -
drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c | 1 -
drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c | 2
If have memory leak, maybe it will have issue in
ttm_bo_force_list_clean-> ttm_mem_evict_first.
Set adev->gart.ptr to null to avoid to call
amdgpu_gmc_set_pte_pde to cause ptr issue pointer when
calling amdgpu_gart_unbind in amdgpu_bo_fini which is after gart_fini.
Signed-off-by: Emily Deng
---
[AMD Official Use Only - Internal Distribution Only]
>-Original Message-
>From: Christian König
>Sent: Friday, March 5, 2021 4:52 PM
>To: Deng, Emily ; amd-gfx@lists.freedesktop.org
>Subject: Re: [PATCH] drm/amdgpu: Fix some unload driver issues
>
>
>
>Am 05.03.21 um 09:43 schrieb Deng, E
Am 05.03.21 um 09:43 schrieb Deng, Emily:
[AMD Official Use Only - Internal Distribution Only]
-Original Message-
From: Christian König
Sent: Friday, March 5, 2021 3:55 PM
To: Deng, Emily ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: Fix some unload driver issues
[AMD Official Use Only - Internal Distribution Only]
>-Original Message-
>From: Christian König
>Sent: Friday, March 5, 2021 3:55 PM
>To: Deng, Emily ; amd-gfx@lists.freedesktop.org
>Subject: Re: [PATCH] drm/amdgpu: Fix some unload driver issues
>
>Am 05.03.21 um 02:20 schrieb Emily Deng:
Am 05.03.21 um 04:59 schrieb Felix Kuehling:
Am 2021-03-04 um 3:03 a.m. schrieb Smith John:
Hi! I noticed that kernels with different VMIDs have different GPU
address spaces. I was wondering if it is possible for these kernels to
run concurrently on the same GPU, or they need to be serialized
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