From: Joshua Aberback <joshua.aberb...@amd.com>
[Why]
The registers for the address of the cursor are aligned to 2KB, so all
cursor surfaces also need to be aligned to 2KB. Currently, the
provided cursor cache surface is not aligned, so we need a workaround
until alignment is enforced by the surface provider.
[How]
- round up surface address to nearest multiple of 2048
- current policy is to provide a much bigger cache size than
necessary,so this operation is safe
Signed-off-by: Joshua Aberback <joshua.aberb...@amd.com>
Reviewed-by: Jun Lei <jun....@amd.com>
Acked-by: Eryk Brol <eryk.b...@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index c626334e9346..d53f8b39699b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -855,7 +855,7 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc,
bool enable)
cmd.mall.cursor_copy_src.quad_part =
cursor_attr.address.quad_part;
cmd.mall.cursor_copy_dst.quad_part =
-
plane->address.grph.cursor_cache_addr.quad_part;
+
(plane->address.grph.cursor_cache_addr.quad_part + 2047) & ~2047;
cmd.mall.cursor_width =
cursor_attr.width;
cmd.mall.cursor_height =
cursor_attr.height;
cmd.mall.cursor_pitch =
cursor_attr.pitch;
@@ -865,8 +865,7 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc,
bool enable)
dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
/* Use copied cursor, and it's okay to
not switch back */
- cursor_attr.address.quad_part =
-
plane->address.grph.cursor_cache_addr.quad_part;
+ cursor_attr.address.quad_part =
cmd.mall.cursor_copy_dst.quad_part;
dc_stream_set_cursor_attributes(stream,
&cursor_attr);
}
--
2.25.1
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