From: Rodrigo Siqueira
[Why]
Sometimes CRTCs can be disabled due to display unplugging or temporarily
transition in the userspace; in these circumstances, DCE tries to set
the minimum clock threshold. When we have this situation, the function
bw_calcs is invoked with number_of_displays set to zer
From: Anthony Koo
Signed-off-by: Anthony Koo
Reviewed-by: Aric Cyr
Acked-by: Eryk Brol
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
b/drivers/gpu/drm/amd/display/dmu
From: Alvin Lee
[Why]
DAL resume from BACO time is longer if we always flush inst_fb
[How]
Check if backdoor loading to flush inst_fb
Signed-off-by: Alvin Lee
Reviewed-by: Nicholas Kazlauskas
Acked-by: Eryk Brol
---
drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 17 +
1 f
From: Alvin Lee
[Why]
When forcing 3D mode in DAL, we set the right address to be the same as the
left address. We need to do the same for the meta addresses.
[How]
Program right meta to be same as left meta.
Signed-off-by: Alvin Lee
Reviewed-by: Aric Cyr
Acked-by: Eryk Brol
---
drivers/gpu
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Eryk Brol
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index d2d2032a40e1..203dab40a
From: Charlene Liu
[why]
HDCP 1.4 failed on SL8800 SW w/a test driver use.
[how]
Slow down the HW i2c speed when used by HW i2c.
This request: each acquired_i2c_engine setup the i2c speed needed
and sets the I2c engine for HDCP use at release_engine.
This covers SW using HW i2c engine and HDCP
From: Chris Park
[Why]
Formula uses kHz in their formula while our driver operates with Hz.
[How]
Divide audio rate by 1000 on the initial variable that is entered into formula.
Signed-off-by: Chris Park
Reviewed-by: Charlene Liu
Acked-by: Eryk Brol
Acked-by: Nicholas Kazlauskas
---
driver
From: Sung Lee
[WHY]
Currently construction of clock limits gets skipped for diags.
This logic would be useful to get tested in diags.
[HOW]
Copy existing states to clk_table such that update_bw_bounding_box
logic gets used to fill the table.
Signed-off-by: Sung Lee
Reviewed-by: Tony Cheng
Ac
From: Dmytro Laktyushkin
This should be programmed with timing rather than with odm.
Signed-off-by: Dmytro Laktyushkin
Reviewed-by: Dmytro Laktyushkin
Acked-by: Eryk Brol
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 11 +++
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
From: Aric Cyr
[Why]
On narrow range monitors without LFC, a margin prevents good utilization
of the available range.
[How]
Decrease the margin for exiting fixed mode and fix the frame counter to
reset if a non-consecutive render is found.
Signed-off-by: Aric Cyr
Reviewed-by: Anthony Koo
Acke
From: Felipe
[WHY]
This change was implemented because the comment style was not uniform
across the file. In some lines comments were initiated with // and in
others they were in between /* ... */.
Additionally, the style for multi-line comments was also not uniform and
some comment lines were mi
From: Joshua Aberback
[Why]
When we transfer the WM range table to SMU, they can perform a watermark
switch right away. This can be a problem if we're in not in accelerated mode
during hw_init as SMU may initiate a dummy p-state change before the rest
of the watermarks are programmed. Watermark s
From: Fangzhi Zuo
[Why]
Currently mode validation is bypassed if remote sink exists. That
leads to mode set issue when a BW bottle neck exists in the link path,
e.g., a DP-to-HDMI converter that only supports HDMI 1.4.
Any invalid mode passed to Linux user space will cause the modeset
failure du
From: Yongqiang Sun
[Why]
enable ODM on eDP panel with ABM will result in color difference
on the panel due to only one ABM module to set one pipe.
[How]
Block ABM in case of ODM enabled on eDP.
Signed-off-by: Yongqiang Sun
Reviewed-by: Eric Yang
Acked-by: Eryk Brol
---
drivers/gpu/drm/amd/
From: Joshua Aberback
[Why]
During driver unload, it is expected that p-state switching is supported.
If it's not supported, PMFW will hang due to a forced p-state switch. Even
if the current timing does not support p-state normally, we still want to
force allow because the worst that can happen
From: Alvin Lee
[Why]
We will hang if we report switch in VACTIVE but not in VBLANK and DPG_EN = 1
[How]
Block switch in ACTIVE if not supported in BLANK
Signed-off-by: Alvin Lee
Reviewed-by: Jun Lei
Acked-by: Eryk Brol
---
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c | 2
From: Aric Cyr
[Why]
When running games or benchmarking with v-sync disabled, disabling
a plane (which is v-sync) can cause underflow. This is caused by
flips pending before pipe locking being applied after locks are
released and pipes could have been re-arranged or disconnected. This
could poten
From: Aric Cyr
Signed-off-by: Aric Cyr
Reviewed-by: Aric Cyr
Acked-by: Eryk Brol
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
b/drivers/gpu/drm/amd/display/dc/dc.h
index 82fe0ab56e3a..3ea4be400
This DC patchset brings improvements in multiple areas. In summary, we have:
* Fixes in Freesync, audio, ABM
* Improvements in i2c, p-state
* Added HDMI remote sink validation
--
Alvin Lee (3):
drm/amd/display: Don't allow pstate if no support in blank
drm/amd/display: Progra
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