Hi all,
Please ignore this patch, will send another patch.
Best wishes
Emily Deng
-Original Message-
From: amd-gfx On Behalf Of Emily Deng
Sent: Tuesday, August 14, 2018 2:32 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deng, Emily
Subject: [PATCH] drm/amdgpu/sriov: For sriov runtime,
That is fixed by "drm/scheduler: bind job earlier to scheduler".
Christian.
Am 13.08.2018 um 16:33 schrieb Andres Rodriguez:
Any updates on this issue?
Regards,
Andres
On 2018-08-08 03:10 AM, Christian König wrote:
Yeah that is a known issue, but this solution is not correct either.
See the
Am 14.08.2018 um 05:05 schrieb Huang Rui:
On Tue, Aug 14, 2018 at 10:26:43AM +0800, Zhang, Jerry wrote:
On 08/13/2018 05:58 PM, Huang Rui wrote:
I continue to work for bulk moving that based on the proposal by Christian.
Background:
amdgpu driver will move all PD/PT and PerVM BOs into idle lis
To avoid the tlb flush not interrupted by world switch, use kiq and one
command to do tlb invalidate.
SWDEV-161497
Signed-off-by: Emily Deng
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gm
On Tue, Aug 14, 2018 at 10:26:43AM +0800, Zhang, Jerry wrote:
> On 08/13/2018 05:58 PM, Huang Rui wrote:
> > I continue to work for bulk moving that based on the proposal by Christian.
> >
> > Background:
> > amdgpu driver will move all PD/PT and PerVM BOs into idle list. Then move
> > all of
> >
a helper function to create and initialize amdgpu bo
v2: update error handling: add label and free bo
v3: update error handling: separate each error label
v4: update error handling and rebase
Signed-off-by: Junwei Zhang
Reviewed-by: Christian König
---
amdgpu/amdgpu_bo.c | 211
Fix potential memory leak when handle flink bo in bo import.
Free the flink bo after bo import and in error handling.
Signed-off-by: Junwei Zhang
---
amdgpu/amdgpu_bo.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c
index b790e9b..d9556ec 100644
On 08/13/2018 06:14 PM, Christian König wrote:
Am 13.08.2018 um 12:06 schrieb Junwei Zhang:
a helper function to create and initialize amdgpu bo
v2: update error handling: add label and free bo
v3: update error handling: separate each error label
v4: update error handling and free flink bo in b
On Tue, Aug 14, 2018 at 10:22:34AM +0800, Zhang, Jerry (Junwei) wrote:
> On 08/13/2018 06:16 PM, Christian König wrote:
> >Am 13.08.2018 um 11:58 schrieb Huang Rui:
> >>From: Christian König
> >>
> >>Add bulk move pos to store the pointer of first and last buffer object.
> >>The list in between wi
On 08/13/2018 05:58 PM, Huang Rui wrote:
I continue to work for bulk moving that based on the proposal by Christian.
Background:
amdgpu driver will move all PD/PT and PerVM BOs into idle list. Then move all of
them on the end of LRU list one by one. Thus, that cause so many BOs moved to
the end
On Tue, Aug 14, 2018 at 10:02:00AM +0800, Zhou, David(ChunMing) wrote:
>
>
> On 2018年08月13日 18:16, Christian König wrote:
> > Am 13.08.2018 um 11:58 schrieb Huang Rui:
> >> From: Christian König
> >>
> >> Add bulk move pos to store the pointer of first and last buffer object.
> >> The list in be
On 08/13/2018 06:16 PM, Christian König wrote:
Am 13.08.2018 um 11:58 schrieb Huang Rui:
From: Christian König
Add bulk move pos to store the pointer of first and last buffer object.
The list in between will be bulk moved on lru list.
Signed-off-by: Christian König
Signed-off-by: Huang Rui
On 2018年08月13日 18:16, Christian König wrote:
Am 13.08.2018 um 11:58 schrieb Huang Rui:
From: Christian König
Add bulk move pos to store the pointer of first and last buffer object.
The list in between will be bulk moved on lru list.
Signed-off-by: Christian König
Signed-off-by: Huang Rui
On Sun, Aug 12, 2018 at 3:46 PM Mauro Rossi wrote:
>
> Sending PATCH v3 series for support of {A,X}RGB pixel formats
> in DCE1/R5xx and later, with separated patches for amd dc,
> amdgpu and radeon, based on Alexander Deucher comments
>
> Tested and working on R5xx (X1300), R6xx (HD2400), R7xx (HD
On Mon, Aug 13, 2018 at 7:16 AM Rex Zhu wrote:
>
> Also ajust the gfx donamin voltage on Tonga when user overdriver
> the voltage.
Typo "domain"
>
> For Tonga, Driver do not update user's setting to voltage table
> in smu, we only pick up a minimum value from voltage table that
> not less than t
On Mon, Aug 13, 2018 at 4:49 PM Alex Deucher wrote:
>
> On Sun, Aug 12, 2018 at 3:55 AM Christian König
> wrote:
> > Adding Harry as well.
> > Am 11.08.2018 um 17:54 schrieb Arnd Bergmann:
> > >
> > > Fixes: bf2e2e2e0ea9 ("drm/amd/display: Limit DCN to x86 arch")
> > > Fixes: 4841203102a3 ("drm/a
On Sun, Aug 12, 2018 at 3:55 AM Christian König
wrote:
>
> Adding Harry as well.
>
> Am 11.08.2018 um 17:54 schrieb Arnd Bergmann:
> > Building the DCN 1.0 Raven display driver with CONFIG_KCOV_INSTRUMENT_ALL=y
> > and CONFIG_KCOV_ENABLE_COMPARISONS=y results in warnings about many
> > functions
Any updates on this issue?
Regards,
Andres
On 2018-08-08 03:10 AM, Christian König wrote:
Yeah that is a known issue, but this solution is not correct either.
See the scheduler where the job is execute on is simply not determined
yet when we want to trace it.
So using the scheduler name fro
Building the DCN 1.0 Raven display driver with CONFIG_KCOV_INSTRUMENT_ALL=y
and CONFIG_KCOV_ENABLE_COMPARISONS=y results in warnings about many functions
that do a comparison of floating-point variables:
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.o: In function
`dcn_bw_calc_rq_dlg_ttu':
dcn_c
On 08/13/2018 02:28 PM, Thomas Zimmermann wrote:
Hi
Am 13.08.2018 um 12:33 schrieb Christian König:
Yes, please! I had it on my TODO list to clean that up for an eternity.
On top of these patches, I have a patch set that provides a single
init/release interface for TTM global data. I'll post i
PSP engine only allocate space for firmware.
mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW/HIGH is for firmware TMR address.
The other two address are for HEAP/Session.
Regards!
James Zhu
On 2018-08-13 12:16 AM, Quan, Evan wrote:
Why only the mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW/HIGH use the new
tmr_
Hi
Am 13.08.2018 um 12:33 schrieb Christian König:
> Yes, please! I had it on my TODO list to clean that up for an eternity.
On top of these patches, I have a patch set that provides a single
init/release interface for TTM global data. I'll post it when the
current patches got some feed back.
I'
Also ajust the gfx donamin voltage on Tonga when user overdriver
the voltage.
For Tonga, Driver do not update user's setting to voltage table
in smu, we only pick up a minimum value from voltage table that
not less than the user's setting.
Signed-off-by: Rex Zhu
---
drivers/gpu/drm/amd/powerpla
Yes, please! I had it on my TODO list to clean that up for an eternity.
Actually I never understood why that should be driver work to setup TTM?
I mean can't we just have a module_init/module_exit for TTM?
Thanks,
Christian.
Am 13.08.2018 um 12:24 schrieb Thomas Zimmermann:
TTM uses global me
The functions ttm_bo_global_init() and ttm_bo_global_release() do not
receive an argument of type struct ttm_bo_global. Both take a struct
drm_global_reference that contains points to a struct ttm_bo_global_ref.
Renaming them reflects this.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/am
TTM uses global memory and BO for backing graphics buffers. These are
represented by struct ttm_mem_global and struct ttm_bo_global.
Currently, struct ttm_bo_global can only be initialized and released through
struct ttm_bo_global_ref. This is a workaround for passing an instance of
ttm_mem_global
So far, struct ttm_bo_global_ref was the only way of initializing a struct
ttm_bo_global. Providing separate initializer and release functions for
struct ttm_bo_global gives drivers the option of implementing their own
init and release callbacks for drm_global_references of type
DRM_GLOBAL_TTM_BO.
Am 13.08.2018 um 11:58 schrieb Huang Rui:
From: Christian König
Add bulk move pos to store the pointer of first and last buffer object.
The list in between will be bulk moved on lru list.
Signed-off-by: Christian König
Signed-off-by: Huang Rui
Tested-by: Mike Lothian
If you ask me that lo
Am 13.08.2018 um 12:06 schrieb Junwei Zhang:
a helper function to create and initialize amdgpu bo
v2: update error handling: add label and free bo
v3: update error handling: separate each error label
v4: update error handling and free flink bo in bo import
Signed-off-by: Junwei Zhang
A separ
Am 13.08.2018 um 12:08 schrieb Zhang, Jerry (Junwei):
On 08/13/2018 04:29 PM, Christian König wrote:
Am 13.08.2018 um 08:43 schrieb Zhang, Jerry (Junwei):
On 08/13/2018 11:03 AM, Zhang, Jerry (Junwei) wrote:
On 08/10/2018 10:20 PM, Christian König wrote:
Am 10.08.2018 um 07:05 schrieb Junwei
On 08/13/2018 04:29 PM, Christian König wrote:
Am 13.08.2018 um 08:43 schrieb Zhang, Jerry (Junwei):
On 08/13/2018 11:03 AM, Zhang, Jerry (Junwei) wrote:
On 08/10/2018 10:20 PM, Christian König wrote:
Am 10.08.2018 um 07:05 schrieb Junwei Zhang:
the flink bo is used to export
Why should we
a helper function to create and initialize amdgpu bo
v2: update error handling: add label and free bo
v3: update error handling: separate each error label
v4: update error handling and free flink bo in bo import
Signed-off-by: Junwei Zhang
---
amdgpu/amdgpu_bo.c | 208 ++
The new bulk moving functionality is ready, the overhead of moving PD/PT bos to
LRU is fixed. So move them on LRU again.
Signed-off-by: Huang Rui
Tested-by: Mike Lothian
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/dr
This function allow us to bulk move a group of BOs to the tail of their LRU.
The positions of group of BOs are stored on the (first, last) bulk_move_pos
structure.
Signed-off-by: Christian König
Signed-off-by: Huang Rui
Tested-by: Mike Lothian
---
drivers/gpu/drm/ttm/ttm_bo.c | 52
I continue to work for bulk moving that based on the proposal by Christian.
Background:
amdgpu driver will move all PD/PT and PerVM BOs into idle list. Then move all of
them on the end of LRU list one by one. Thus, that cause so many BOs moved to
the end of the LRU, and impact performance seriousl
From: Christian König
Add bulk move pos to store the pointer of first and last buffer object.
The list in between will be bulk moved on lru list.
Signed-off-by: Christian König
Signed-off-by: Huang Rui
Tested-by: Mike Lothian
---
include/drm/ttm/ttm_bo_driver.h | 28 +
The idea and proposal is originally from Christian, and I continue to work to
deliver it.
Background:
amdgpu driver will move all PD/PT and PerVM BOs into idle list. Then move all of
them on the end of LRU list one by one. Thus, that cause so many BOs moved to
the end of the LRU, and impact perfor
From: Christian König
When move a BO to the end of LRU, it need remember the BO positions.
Make sure all moved bo in between "first" and "last". And they will be bulk
moving together.
Signed-off-by: Christian König
Signed-off-by: Huang Rui
Tested-by: Mike Lothian
---
drivers/gpu/drm/amd/amdg
Am 13.08.2018 um 08:43 schrieb Zhang, Jerry (Junwei):
On 08/13/2018 11:03 AM, Zhang, Jerry (Junwei) wrote:
On 08/10/2018 10:20 PM, Christian König wrote:
Am 10.08.2018 um 07:05 schrieb Junwei Zhang:
the flink bo is used to export
Why should we do this? That makes no sense, this way we would
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