RE: [PATCH 11/22] drm/amdgpu: Remove the memory leak after unload amdgpu driver

Hi Alex This patch works on another branch, and staging looks not need it, my bad -Original Message- From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of Liu, Monk Sent: 2018年2月27日 13:27 To: Alex Deucher Cc: Deng, Emily ; amd-gfx list Subject: RE: [PATCH 11/22] drm

RE: [PATCH 11/22] drm/amdgpu: Remove the memory leak after unload amdgpu driver

Oh, Alex This patch is verified on an elder branch, I checked the latest staging and PSP already include the ucode_bo_fini, so I'll drop it right now and verify this memleak later /Monk -Original Message- From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of Monk L

RE: [PATCH 18/22] drm/amdgpu: Correct sdma_v4 get_wptr

Yeah, agreed -Original Message- From: Christian König [mailto:ckoenig.leichtzumer...@gmail.com] Sent: 2018年2月26日 18:22 To: Liu, Monk ; amd-gfx@lists.freedesktop.org Cc: Deng, Emily Subject: Re: [PATCH 18/22] drm/amdgpu: Correct sdma_v4 get_wptr Am 26.02.2018 um 06:18 schrieb Monk Liu:

RE: [PATCH 17/22] drm/amdgpu: disable GFX ring and disable PQ wptr in hw_fini

This is only for virtualization, for bare-metal it go another path -Original Message- From: Alex Deucher [mailto:alexdeuc...@gmail.com] Sent: 2018年2月27日 1:40 To: Liu, Monk Cc: amd-gfx list Subject: Re: [PATCH 17/22] drm/amdgpu: disable GFX ring and disable PQ wptr in hw_fini On Mon, F

RE: [PATCH 11/22] drm/amdgpu: Remove the memory leak after unload amdgpu driver

I'm sure it is right, the kmemleak is fixed by this patch -Original Message- From: Alex Deucher [mailto:alexdeuc...@gmail.com] Sent: 2018年2月27日 1:28 To: Liu, Monk Cc: amd-gfx list ; Deng, Emily Subject: Re: [PATCH 11/22] drm/amdgpu: Remove the memory leak after unload amdgpu driver O

RE: [PATCH 10/22] drm/amdgpu: no need to count emitted for SRIOV

> I would rather avoid calling the function in the first place. I already did it in patch 08, and you also rejected this patch So I'll consider patch 08 is still valid, and drop this one -Original Message- From: Christian König [mailto:ckoenig.leichtzumer...@gmail.com] Sent: 2018年2月26日

RE: [PATCH 09/22] drm/amdgpu: fix kmd reload bug on bare-metal

> In this case I think it would be much better to wait for the idle work before > trying to unload the driver. I already did it: > + if (!amdgpu_sriov_vf(adev)) > + while (cancel_delayed_work_sync(&adev->late_init_work)) > + schedule(); /* to make sure late_ini

RE: [PATCH 22/22] drm/amdgpu: fix reservation obj shared count bug

> Well then there is something else broken and I actually think that this is > the root cause here. What if this VM submits four different jobs on four different rings, e.g. gfx/compute1/compute2/vce So the fences for those jobs are from different context, and now you get a mapping on this VM S

FW: [PATCH] drm/amd/display: check for ipp before calling cursor operations

From: Shirish S Currently all cursor related functions are made to all pipes that are attached to a particular stream. This is not applicable to pipes that do not have cursor plane initialised like underlay. Hence this patch allows cursor related operations on a pipe only if ipp in available

[PATCH] drm/amd/display: make dm_dp_aux_transfer return payload bytes instead of size

From: Shirish S The drm layer expects aux->transfer() to return the payload bytes read. Currently dm_dp_aux_transfer() returns the payload size which does not gets updated during the read, hence not giving the right data for the drm layer to pars edid. This leads to the drm layer to conclude a

Re: [PATCH 13/33] drm/amd/display: allocate fbc buffer in AMDGPU_GEM_DOMAIN_GTT

On 2018-02-26 04:26 PM, Alex Deucher wrote: > On Mon, Feb 26, 2018 at 3:15 PM, Harry Wentland > wrote: >> From: Shirish S >> >> Currently the FBC buffer is allocated in VRAM, since VRAM usage is >> dedicatedly for scanouts, by allocating FBC back buffer in GTT >> shall help in conserving VRAM fo

Re: [PATCH] drm/amdgpu/powerplay/smu7: use proper dep table for mclk

Reviewed-by: Rex Zhu Best Regards Rex From: amd-gfx on behalf of Alex Deucher Sent: Tuesday, February 27, 2018 2:37:05 AM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander Subject: [PATCH] drm/amdgpu/powerplay/smu7: use proper dep table for mclk

Re: [PATCH 15/33] drm/amd/display: add per pipe dppclk for

On Mon, Feb 26, 2018 at 3:15 PM, Harry Wentland wrote: > From: Dmytro Laktyushkin > > Signed-off-by: Dmytro Laktyushkin > Reviewed-by: Tony Cheng > Acked-by: Harry Wentland Did the patch title get cut off? add per pipe dppclk for...what? Alex > --- > drivers/gpu/drm/amd/display/dc/calcs/

Re: [PATCH 13/33] drm/amd/display: allocate fbc buffer in AMDGPU_GEM_DOMAIN_GTT

On Mon, Feb 26, 2018 at 3:15 PM, Harry Wentland wrote: > From: Shirish S > > Currently the FBC buffer is allocated in VRAM, since VRAM usage is > dedicatedly for scanouts, by allocating FBC back buffer in GTT > shall help in conserving VRAM for other purposes. Are there any dGPUs that support FB

[PATCH 20/33] drm/amd/display: Use MACROS instead of dm_logger

From: Bhawanpreet Lakha Created MACROS for all log levels. Also Replaced usage of dm_logger_write to the defined MACROS Signed-off-by: Bhawanpreet Lakha Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/bios/bios_parser.c | 2 +- .../gpu/drm/amd/display/dc

[PATCH 23/33] drm/amd/display: update infoframe after dig fe is turned on

From: Eric Yang Before dig fe is enabled, infoframe can't be programmed. So in suspend resume case our infoframe programmming was not going through. This change changes the sequence so that infoframe is programmed after. Signed-off-by: Eric Yang Reviewed-by: Tony Cheng Acked-by: Harry Wentlan

[PATCH 33/33] drm/amd/display: Default HDMI6G support to true. Log VBIOS table error.

There have been many reports of Ellesmere and Baffin systems not being able to drive HDMI 4k60 due to the fact that we check the HDMI_6GB_EN bit from VBIOS table. Windows seems to not have this issue. On some systems we fail to the encoder cap info from VBIOS. In that case we should default to ena

[PATCH 09/33] drm/amd/display: Clear dmps off for eDP when resume.

From: Yongqiang Sun This patch fixed secondary screen only S4 resume, eDP is unintentionally light up due to incorrect dpms off flag. When entering S4, dpms off flags are set to true via set power state. During resume, eDP is light up by vbios, so the flags should be changed to false to match th

[PATCH 28/33] drm/amd/display: Clean up formatting in irq_service_dce110.c

Signed-off-by: Harry Wentland Reviewed-by: Roman Li Acked-by: Harry Wentland --- .../amd/display/dc/irq/dce110/irq_service_dce110.c | 62 +- 1 file changed, 26 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c b/driv

[PATCH 21/33] drm/amd/display: define DC_LOGGER for logger

From: Bhawanpreet Lakha Created a DC_LOGGER define. This is used to pass the logger into the macros. Anywhere we need to use the logger we need to define DC_LOGGER Signed-off-by: Bhawanpreet Lakha Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/bios/bios_

[PATCH 15/33] drm/amd/display: add per pipe dppclk for

From: Dmytro Laktyushkin Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_debug.c| 13 +++-- drivers/gpu/drm/amd/display/dc/dcn10

[PATCH 19/33] drm/amd/display: Handle HDR use cases.

From: Vitaly Prosyak Implementation of de-gamma, blnd-gamma, shaper and 3d lut's. Removed memory allocations in transfer functions. Refactor color module. Signed-off-by: Vitaly Prosyak Reviewed-by: Krunoslav Kovac Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- .../gpu/drm/amd/display/

[PATCH 24/33] drm/amd/display: Remove duplicate dm_pp_power_level enum

This is really just a copy of dm_pp_clocks_state, so just use that one. Thanks to Matthias Kaehlke for spotting this. Signed-off-by: Harry Wentland Reviewed-by: Roman Li Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/dm_services_types.h | 19 +-- 1 file changed, 1

[PATCH 27/33] drm/amd/display: Return success when enabling interrupt

Signed-off-by: Harry Wentland Reviewed-by: Roman Li Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +-- drivers/gpu/drm/amd/display/dc/core/dc.c | 6 +++--- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 3 files changed, 5 insertions(+), 6

[PATCH 29/33] drm/amd/display: defer modeset check in dm_update_planes_state

From: Shirish S amdgpu_dm_atomic_check() is used to validate the entire configuration of planes and crtc's that the user space wants to commit. However amdgpu_dm_atomic_check() depends upon DRM_MODE_ATOMIC_ALLOW_MODESET flag else its mostly dummy. Its not mandatory for the user space to set DRM_

[PATCH 17/33] drm/amd/display: dal 3.1.36

From: Tony Cheng Signed-off-by: Tony Cheng Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 14cc4beb12c1

[PATCH 22/33] drm/amd/display: fix dcn1 dppclk when min dispclk patch applies

From: Dmytro Laktyushkin Applying min dispclk patch would result in incorrect dppclk divider without this change Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 2 +- 1 file changed, 1 insertion(+), 1 d

[PATCH 25/33] drm/amd/display: dal 3.1.37

From: Tony Cheng Signed-off-by: Tony Cheng Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index e954705f7f0f

[PATCH 11/33] drm/amd/display: Update Link Training Fallback logic

From: Wenjing Liu [Description] When CR fails to minimum link rate, we should reduce lane count to the number lowest cr_done lanes. [Code Review] Jun Lei Signed-off-by: Wenjing Liu Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 98 +

[PATCH 18/33] drm/amd/display: Fix DAL surface change test

From: Eric Bernstein Signed-off-by: Eric Bernstein Reviewed-by: Yongqiang Sun Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b

[PATCH 30/33] drm/amd/display: validate plane in dce110 for scaling

From: Shirish S CZ & ST support uptil a limit 2:1 downscaling, this patch adds validate_plane hook, that shall be used to validate the plane attributes sent by the user space based on dce110 capabilities. Signed-off-by: Shirish S Reviewed-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/

[PATCH 07/33] drm/amd/display: dal 3.1.35

From: Tony Cheng Signed-off-by: Tony Cheng Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 5bb0e5defaf4

[PATCH 13/33] drm/amd/display: allocate fbc buffer in AMDGPU_GEM_DOMAIN_GTT

From: Shirish S Currently the FBC buffer is allocated in VRAM, since VRAM usage is dedicatedly for scanouts, by allocating FBC back buffer in GTT shall help in conserving VRAM for other purposes. Signed-off-by: Shirish S Reviewed-by: Charlene Liu Acked-by: Harry Wentland --- drivers/gpu/drm/

[PATCH 26/33] drm/amd/display: Use crtc enable/disable_vblank hooks

Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 24 +++ 1 file changed, 24 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdg

[PATCH 32/33] drm/amd/display: update plane params before validation

From: Shirish S This patch updates the dc's plane state with the parameters set by the user side. This is needed to validate the plane capabilities with the parameters user space wants to set. Signed-off-by: Shirish S Reviewed-by: Harry Wentland --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgp

[PATCH 31/33] drm/amd/display: Don't blow up if TG is NULL in dce110_vblank_set

Signed-off-by: Harry Wentland Reviewed-by: Roman Li Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c b/drivers/gpu/drm/a

[PATCH 14/33] drm/amd/display: Update DCN OPTC registers

From: Dmytro Laktyushkin Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 +++- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h | 6 -- 2 files changed, 7 insertions(+), 3 deletio

[PATCH 05/33] drm/amd/display: update cur_clock correctly within set bandwidth

From: Yue Hin Lau Signed-off-by: Yue Hin Lau Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 12 +--- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.

[PATCH 03/33] drm/amd/display: Add passive dongle support for HPD Rearch

From: John Barberiz Add HPD delay timer support to 1. Single/dual link DVI. 2. DP to HDMI passive dongle 3. DP to DVI passive dongle. Signed-off-by: John Barberiz Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 7 +-- drivers/gpu/drm/a

[PATCH 16/33] drm/amd/display: add diags clock programming

From: Dmytro Laktyushkin Signed-off-by: Dmytro Laktyushkin Reviewed-by: Dmytro Laktyushkin Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 5 + drivers/gpu/drm/amd/display/dc/dc.h | 11 +++ drivers/gpu/drm/amd/display

[PATCH 10/33] drm/amd/display: add psr_version to stream

From: Xingyue Tao Brightness could not be changed for some panels whose DPCD_version is below 1.2 Now psr_version is added into stream, and it copies from the displayTarget's psr_version. It checks if the stream's psr_versio is non-zero and sets the vsc info packet revision now. Signed-off-by:

[PATCH 01/33] drm/amd/display: move MST branch initialize to before link training

From: Hersen Wu some MST capable scaler doesn't like recieving CLEAR_PAYLOAD_ID_TABLE after link training. move branch initialize to before link training Signed-off-by: Hersen Wu Signed-off-by: Tony Cheng Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/amdg

[PATCH 12/33] drm/amd/display: Add regamma lut write mask to SOC base

From: "Leo (Sunpeng) Li" Mask and shift values for DCP0_REGAMMA_LUT_WRITE_EN_MASK were missing from XFM_COMMON_MASK_SH_LIST_SOC_BASE. Add it. Signed-off-by: Leo (Sunpeng) Li Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/dce/dce_transform.h | 1 + 1 file

[PATCH 04/33] drm/amd/display: Use 4096 lut entries

From: "Leo (Sunpeng) Li" Non-legacy LUT size should reflect hw capability. Change size from 256 to 4096. However, X doesn't seem to play with legacy LUTs of such size. Therefore, check for legacy lut when updating DC states, and update accordingly. v2: Use a macro for the maximum drm LUT value.

[PATCH 06/33] drm/amd/display: Check DCN PState ASSERT failure

From: Hersen Wu [Description] ASIC change debug register definition Signed-off-by: Hersen Wu Reviewed-by: Tony Cheng Acked-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c | 9 ++--- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h | 1 + 2 files changed, 7 i

[PATCH 02/33] drm/amd/display: Fix active dongle hotplug

From: Roman Li Clean fake sink flag after detecting link on downstream port. Fixing display light-up after "hot-unplug&plug again" downstream of an active dongle. Signed-off-by: Roman Li Reviewed-by: Harry Wentland --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 1 file change

[PATCH 08/33] drm/amd/display: fix missing az disable in reset backend

From: Eric Yang Optimization in reset backend skips disable stream if it is already done in dc_stream_set_dpms. However that path does not disable az in order to prevent audio from toggling between internal and external displays. This still need to be done. Signed-off-by: Eric Yang Reviewed-by:

[PATCH 00/33] DC Patches Feb 26, 2018

* Fix HDMI 4k60 problems on some ASICs * Fix NULL pointer when trying to wake up screen * Fix HDMI infoframe problem (wrong colors) * Increase LUT size to 4096 * Bunch of multi-plane fixes for Chrome * Bunch of other DCN patches Bhawanpreet Lakha (2): drm/amd/display: Use MACROS instead of

[PATCH] drm/amdgpu/powerplay/smu7: use proper dep table for mclk

For mclk od, use the vdd dependency on mclk table. Looks like a cut and paste typo. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 2 +- drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c | 2 +- drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c

Re: [PATCH] drm/amd/pp: Print more info when smu message failed on Vega10

On Sat, Feb 24, 2018 at 7:01 AM, Rex Zhu wrote: > Change-Id: Ifaa7058a4682bafeeef68e78bfcff26012ba71c1 > Signed-off-by: Rex Zhu Reviewed-by: Alex Deucher > --- > drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drive

Re: [PATCH 20/22] drm/amdgpu: increase gart size to 512MB

On Mon, Feb 26, 2018 at 12:18 AM, Monk Liu wrote: > 256MB is too small consider PTE/PDE shadow and TTM > eviction activity > > Change-Id: Ifaa30dc730eec36af47fbdeb3cce30de9067b17f > Signed-off-by: Monk Liu Acked-by: Alex Deucher > --- > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +- > 1 file c

Re: [PATCH 17/22] drm/amdgpu: disable GFX ring and disable PQ wptr in hw_fini

On Mon, Feb 26, 2018 at 12:18 AM, Monk Liu wrote: > otherwise there will be DMAR reading error comes out from CP since > GFX is still alive and CPC's WPTR_POLL is still enabled, which would > lead to DMAR read error. > > fix: > we can hault CPG after hw_fini, but cannot halt CPC becaues KIQ > stil

Re: [PATCH 15/22] drm/amdgpu: move WB_FREE to correct place

On Mon, Feb 26, 2018 at 12:18 AM, Monk Liu wrote: > WB_FREE should be put after all engines's hw_fini > done, otherwise the invalid wptr/rptr_addr would still > be used by engines which trigger abnormal bugs. > > This fixes couple DMAR reading error in host side for SRIOV > after guest kmd is unlo

Re: [PATCH 14/22] drm/amdgpu: change gfx9 ib test to use WB

On Mon, Feb 26, 2018 at 12:18 AM, Monk Liu wrote: > two reasons to switch SCRATCH reg method to WB method: > > 1)Because when doing IB test we don't want to involve KIQ health > status affect, and since SCRATCH register access is go through > KIQ that way GFX IB test would failed due to KIQ fail.

Re: [PATCH 11/22] drm/amdgpu: Remove the memory leak after unload amdgpu driver

On Mon, Feb 26, 2018 at 12:18 AM, Monk Liu wrote: > From: Emily Deng > > Need to call function amdgpu_ucode_fini_bo to release ucode bo for > psp firmware load type. Are you sure this is right? I think is this is handled in amdgpu_psp.c already. Alex > > Change-Id: I1c7be8135993e11076c9d46b3c

Re: [PATCH 12/22] drm/amdgpu: send rel event first after init failed

On Mon, Feb 26, 2018 at 12:18 AM, Monk Liu wrote: > and later send req_fini and rel_fini to host for the > finish routine This looks like it should be two patches: 1. Properly release the gpu in sr-iov in device_ip_init() when it fails 2. Make sure to request gpu in sr-iov in device_init() before

Re: [PATCH 04/22] drm/amdgpu: only flush hotplug work without DC

On Mon, Feb 26, 2018 at 12:18 AM, Monk Liu wrote: > since hotplug_work is initialized under the case of > no dc support > > Change-Id: I0d417a5b9f8dfb1863eafc95b6802be9e5c74720 > Signed-off-by: Monk Liu Reviewed-by: Alex Deucher > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 6 -- > 1

Re: [PATCH 01/22] drm/amdgpu: fix&cleanups for wb_clear

On Mon, Feb 26, 2018 at 12:17 AM, Monk Liu wrote: > fix: > should do right shift on wb before clearing > > cleanups: > 1,should memset all wb buffer > 2,set max wb number to 128 (total 4KB) is big enough > > Change-Id: I43832245c875ce039e7709dc049828e21c50c81f > Signed-off-by: Monk Liu Acked-by:

Re: [PATCH 03/22] drm/amdgpu: skip ECC for SRIOV in gmc late_init

On Mon, Feb 26, 2018 at 12:18 AM, Monk Liu wrote: > Change-Id: I2865a11d1dded214de289787d334ec4a22b5db19 > Signed-off-by: Monk Liu Acked-by: Alex Deucher > --- > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/

Re: [PATCH libdrm 2/2] amdgpu: add AMDGPU_VA_RANGE_HIGH

For the series: Reviewed-by: Marek Olšák Marek On Mon, Feb 26, 2018 at 2:16 PM, Christian König wrote: > Return high addresses if requested and available. > > Signed-off-by: Christian König > --- > amdgpu/amdgpu.h | 1 + > amdgpu/amdgpu_device.c | 6 -- > amdgpu/amdgpu_inter

Re: [PATCH] drm/amd/amdgpu: Correct VRAM width for APUs with GMC9

Reviewed-by: Alex Deucher From: amd-gfx on behalf of Tom St Denis Sent: Monday, February 26, 2018 9:18 AM To: amd-gfx@lists.freedesktop.org Cc: StDenis, Tom Subject: [PATCH] drm/amd/amdgpu: Correct VRAM width for APUs with GMC9 DDR4 has a 64-bit width not 128-

Re: [Mesa-dev] [PATCH] winsys/amdgpu: request high addresses

Reviewed-by: Marek Olšák Marek On Mon, Feb 26, 2018 at 2:17 PM, Christian König wrote: > We now have hopefully fixed all bugs regarding high addresses on Vega10 and > Raven. Start to use the high range to make room for SVM in the low > range. > > Signed-off-by: Christian König > --- > src/gal

Re: [PATCH 19/22] drm/amdgpu: adjust timeout for ib_ring_tests

On Mon, Feb 26, 2018 at 12:18 AM, Monk Liu wrote: > issue: > sometime GFX/MM ib test hit timeout under SRIOV env, root cause > is that engine doesn't come back soon enough so the current > IB test considered as timed out. > > fix: > for SRIOV GFX IB test wait time need to be expanded a lot during

[PATCH] drm/amd/amdgpu: Correct VRAM width for APUs with GMC9

DDR4 has a 64-bit width not 128-bits. It was reporting twice the width. Tested with my Ryzen 2400G. Signed-off-by: Tom St Denis --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu

gmc9 vram width

In the init sequence we have static int gmc_v9_0_mc_init(struct amdgpu_device *adev) { u32 tmp; int chansize, numchan; int r; if (amdgpu_emu_mode != 1) adev->gmc.vram_width = amdgpu_atomfirmware_get_vram_width(adev); if (!adev->gmc.vram_wid

[PATCH] winsys/amdgpu: request high addresses

We now have hopefully fixed all bugs regarding high addresses on Vega10 and Raven. Start to use the high range to make room for SVM in the low range. Signed-off-by: Christian König --- src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 16 1 file changed, 12 insertions(+), 4 deletions(

[PATCH libdrm 1/2] amdgpu: mostly revert "use the high VA range if possible v2"

This reverts commit 07ea20d5beb24315b721adf83bbfa72ce016e146. Unfortunately it turned out that this change broke some corner cases in Mesa. Revert it for now, but keep the high range in separate VA managers. Signed-off-by: Christian König --- amdgpu/amdgpu_device.c | 28 +++--

[PATCH libdrm 2/2] amdgpu: add AMDGPU_VA_RANGE_HIGH

Return high addresses if requested and available. Signed-off-by: Christian König --- amdgpu/amdgpu.h | 1 + amdgpu/amdgpu_device.c | 6 -- amdgpu/amdgpu_internal.h | 1 - amdgpu/amdgpu_vamgr.c| 24 +++- 4 files changed, 24 insertions(+), 8 deletions(-)

DCN memory width errors

Hi Harry/all, With my 2400G and dual-channel 2x4GB DDR4 memory the following assert fails dc->dcn_soc->number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width; ASSERT(dc->dcn_soc->number_of_channels < 3); from dcn10_resource.c (around line 1362). The assert succeeds if I

Re: [PATCH 16/22] drm/amdgpu: cleanup SA inti and fini

I cannot remind the details right now ... Ok, well it is still a rather nice to have cleanup. Just one comment, please keep the amdgpu_sa_bo_manager_fini function instead of the amdgpu_sa_bo_manager_suspend function. We can just return void and we still want the error message in case somebo

Re: [PATCH 22/22] drm/amdgpu: fix reservation obj shared count bug

What if all those context are not equal ? and accumulated finally to 4 ? Well then there is something else broken and I actually think that this is the root cause here. You can try VK_EXAMPLE test yourself, see if you can hit that BUG() in reservation.c file, Could you generate a simpler uni

RE: [PATCH 22/22] drm/amdgpu: fix reservation obj shared count bug

> So we call reserve_shared only once and then call > reservation_object_add_shared_fence() multiple times, always with the same > context. >should replace the fence when it has the same context as a previously added >fence. What if all those context are not equal ? and accumulated finally to 4

Re: [PATCH 22/22] drm/amdgpu: fix reservation obj shared count bug

Quoting Christian König (2018-02-26 10:44:40) > > We must call reserve_shared before amdgpu_bo_fence > Actually that's not correct. See reservation_object_add_shared_fence() > should replace the fence when it has the same context as a previously > added fence. > > So we call reserve_shared o

RE: [PATCH 16/22] drm/amdgpu: cleanup SA inti and fini

> Root cause is simple: many engine always accessing some wptr polling address > before They are disabled, so SA must always be valid since it is created, so > must use bo_create_kernel to make sure it is pinned already before someone > use it, Ortherwise during kmd reloading test there will be

Re: [PATCH 22/22] drm/amdgpu: fix reservation obj shared count bug

We must call reserve_shared before amdgpu_bo_fence Actually that's not correct. See reservation_object_add_shared_fence() should replace the fence when it has the same context as a previously added fence. So we call reserve_shared only once and then call reservation_object_add_shared_fenc

RE: [PATCH 16/22] drm/amdgpu: cleanup SA inti and fini

In SRIOV, I found hypervisor continues report DMAR read error, and finally one of that error Related with SA, (I judge by comparing the DMAR error page address with SA MC address, and they shared the same PAGE!!) With this patch applied, one of the DMAR reading error gone, Root cause is simpl

RE: [PATCH 22/22] drm/amdgpu: fix reservation obj shared count bug

amdgpu_vm_get_pd_bo() should already reserves a shared slot for the fence: > entry->tv.shared = true; That's not related with the bug I fixed! The root cause is there is some sequence that When code path comes to amdgpu_bo_fence of vm_update_directories, no one The shared_cnt is by coin

RE: [PATCH 22/22] drm/amdgpu: fix reservation obj shared count bug

Please check again Every time you call amdgpu_bo_fence should first call " reservation_object_reserve_shared", and this patch Fixed a bug by following this rule The thing is when shared comes to 4 (assume max is 4) before you call amdgpu_bo_fence, you will hit BUG() at reservation.c's reservat

RE: [PATCH 21/22] dma-buf/reservation: shouldn't kfree staged when slot available

Sorry, this bug is hit after I fixed another bug () And the only thing I observe is we hit vmc page fault or sometime kernel oops, very random, so I finally ends up with Thinking to wild pointer issue and found this place looks incorrect I don't have trace or something right now, but those weird

Re: [PATCH 18/22] drm/amdgpu: Correct sdma_v4 get_wptr

Am 26.02.2018 um 06:18 schrieb Monk Liu: From: Emily Deng the original method will change the wptr value in wb. Change-Id: I984fabca35d9dcf1f5fa8ef7779b2afb7f7d7370 Signed-off-by: Emily Deng --- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 10 +- 1 file changed, 5 insertions(+), 5 dele

Re: [PATCH 21/22] dma-buf/reservation: shouldn't kfree staged when slot available

Quoting Christian König (2018-02-26 09:42:15) > Well first of all you need to send that to dri-devel and even lkml, so > that Chris and others can take a look as well. > > Second that patch doesn't looks correct to me, obj->staged should never > be related to obj->fence. Concurred. I would susp

RE: [PATCH 21/22] dma-buf/reservation: shouldn't kfree staged when slot available

Hi Christian we call reservation_object_reserve_shared() at very first time, and later we call reservation_object_add_shared_fence(), which will call reservation_object_add_shared_replace() since fobj is not NULL by this time. in reservation_object_get_list(), @old is NULL, @fobj is not NULL, s

Re: [PATCH 16/22] drm/amdgpu: cleanup SA inti and fini

Am 26.02.2018 um 06:18 schrieb Monk Liu: should use bo_create_kernel instead of split to two function that create and pin the SA bo issue: before this patch, there are DMAR read error in host side when running SRIOV test, the DMAR address dropped in the range of SA bo. fix: after this cleanups

Re: [PATCH 13/22] drm/amdgpu: fix vce_ring test memleak

Yeah, well that is the leak you introduced in patch #8. So please instead fix the original patch which messed things up. Christian. Am 26.02.2018 um 06:18 schrieb Monk Liu: Change-Id: I35a343b21a007716fc7811781650264339c94273 Signed-off-by: Monk Liu --- drivers/gpu/drm/amd/amdgpu/amdgpu_vce

Re: [PATCH 10/22] drm/amdgpu: no need to count emitted for SRIOV

I would rather avoid calling the function in the first place. Christian. Am 26.02.2018 um 06:18 schrieb Monk Liu: Change-Id: I370966acd0f1925a99dfde888678e6e0fd093b15 Signed-off-by: Monk Liu --- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)

Re: [PATCH 09/22] drm/amdgpu: fix kmd reload bug on bare-metal

Am 26.02.2018 um 06:18 schrieb Monk Liu: issue: on bare-metal when doing kmd reload test, there are chance that kernel hit fatal error afer driver unloaded/reloaded fix: the cause is that those "idle work" not really stopped and if kmd was is unloaded too quick that were chance that "idle work"

Re: [PATCH 08/22] drm/amdgpu: cleanups VCE/UVD ib test part

Am 26.02.2018 um 06:18 schrieb Monk Liu: 1)amdgpu_vce_get_create_msg is only used in ib test so no reason no to use a static routine for it, and add a timeout parameter for it. 2)fence handling of MM's ib test part is a little messy clean it make it easier to read Change-Id: Ic9bfd9971457600266

Re: [PATCH 07/22] drm/amdgpu: fix fence_emit NULL pointer ref risk

Am 26.02.2018 um 06:18 schrieb Monk Liu: Change-Id: Ic39de73338d515d4e33a828f445d8a3c3ba544bb Signed-off-by: Monk Liu --- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/dr

Re: [PATCH 06/22] drm/amdgpu: don't use MM idle_work for SRIOV

Am 26.02.2018 um 06:18 schrieb Monk Liu: two reason for this patch: 1) SRIOV doesn't give VF cg/pg feature so the idle_work is useless That is a good reason. 2) VCE's idle work would cause "KMD reload" test failed and trigger KERNEL PANIC, this is because the idle work is triggered after VCE

Re: [PATCH 05/22] drm/amdgpu: cond_exec only for schedule with a job

Am 26.02.2018 um 06:18 schrieb Monk Liu: issue: under SR-IOV sometimes the iB test will fail on gfx ring fix: with cond_exec inserted in RB the gfx engine would skip part packets if RLCV issue PREEMPT on gfx engine if gfx engine is prior to COND_EXEC packet, this is okay for regular command from

Re: [PATCH 02/22] drm/amdgpu: remove duplicated job_free_resources

NAK, the job->fence is assigned a reference just the line before: job->fence = dma_fence_get(fence); When the fence ends up as a wild pointer in the SA we have a problem with fence reference counting somewhere, not a problem with freeing resources. Regards, Christian. Am 26.02.2018 um 06:1

Re: [PATCH 22/22] drm/amdgpu: fix reservation obj shared count bug

That fix is incorrect. amdgpu_vm_get_pd_bo() should already reserves a shared slot for the fence:     entry->tv.shared = true; So you must run into this issue because of something else. Regards, Christian. Am 26.02.2018 um 06:35 schrieb Monk Liu: should call reservation_object_reserve_s

Re: [PATCH 21/22] dma-buf/reservation: shouldn't kfree staged when slot available

Well first of all you need to send that to dri-devel and even lkml, so that Chris and others can take a look as well. Second that patch doesn't looks correct to me, obj->staged should never be related to obj->fence. Regards, Christian. Am 26.02.2018 um 06:34 schrieb Monk Liu: issue: kernel