From: Dmytro Laktyushkin <dmytro.laktyush...@amd.com>
Applying min dispclk patch would result in incorrect dppclk divider
without this change
Signed-off-by: Dmytro Laktyushkin <dmytro.laktyush...@amd.com>
Reviewed-by: Tony Cheng <tony.ch...@amd.com>
Acked-by: Harry Wentland <harry.wentl...@amd.com>
---
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index f1d8db56f406..8020bc7742c1 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -998,7 +998,7 @@ bool dcn_validate_bandwidth(
dc->debug.min_disp_clk_khz;
}
- context->bw.dcn.calc_clk.max_dppclk_khz = (int)(v->dppclk *
1000);
+ context->bw.dcn.calc_clk.max_dppclk_khz =
context->bw.dcn.calc_clk.dispclk_khz / v->dispclk_dppclk_ratio;
for (i = 0, input_idx = 0; i < pool->pipe_count; i++) {
struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
--
2.14.1
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