[Bug tree-optimization/118154] [15 Regression] RISC-V: Miscompile with -march=rv64gcv -O3 since r15-5117-g0b27a7dd050

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118154 --- Comment #4 from Patrick O'Neill --- (In reply to Robin Dapp from comment #3) > Uh, what a nice small test case ;) I'll have a look when I'm back mid next > week. With a bit more handholding of creduce/cvise: long a; char b; char c[22][484]

[Bug tree-optimization/118154] New: [15 Regression] RISC-V: Miscompile with -march=rv64gcv -O3 since 15-5117-g0b27a7dd050

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118154 Bug ID: 118154 Summary: [15 Regression] RISC-V: Miscompile with -march=rv64gcv -O3 since 15-5117-g0b27a7dd050 Product: gcc Version: 15.0 Status: UNCONFIRMED Se

[Bug target/118140] [14/15 Regression] RISC-V: Miscompile with -march=rv64gcv_zvl256b -O3 since r14-5076-g01c18f58d37

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118140 Patrick O'Neill changed: What|Removed |Added Summary|[15 Regression] RISC-V: |[14/15 Regression] RISC-V:

[Bug target/118140] [15 Regression] RISC-V: Miscompile with -march=rv64gcv_zvl256b -O3 since r15-3992-g698e0ec89bc

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118140 --- Comment #5 from Patrick O'Neill --- That worked, re-bisecting now.

[Bug target/118140] [15 Regression] RISC-V: Miscompile with -march=rv64gcv_zvl256b -O3 since r15-3992-g698e0ec89bc

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118140 --- Comment #3 from Patrick O'Neill --- (In reply to Andrew Pinski from comment #2) > I suspect if you rewrite it to be: > int h = f[g - 1] ? 2 : 0; > int i = f[g - 1] ? f_3 : 0; > > d = d || h > i; > You run into the same

[Bug middle-end/118140] New: [15 Regression] RISC-V: Miscompile with -march=rv64gcv_zvl256b -O3 since r15-3992-g698e0ec89bc

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118140 Bug ID: 118140 Summary: [15 Regression] RISC-V: Miscompile with -march=rv64gcv_zvl256b -O3 since r15-3992-g698e0ec89bc Product: gcc Version: 15.0 Status: UNCONFIRMED

[Bug target/117990] [15 regression] RISC-V: Miscompile at -O3 zvl 256 since r15-4746-g30435cc2610

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117990 --- Comment #12 from Patrick O'Neill --- (In reply to Vineet Gupta from comment #11) > FWIW cam4 is still failing with similar symptoms. So perhaps it is something > else. PR 118075 also bisected to this same commit - might be that.

[Bug middle-end/118084] New: [15 Regression] RISC-V: ICE in emit_move_insn, at expr.cc:4635

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118084 Bug ID: 118084 Summary: [15 Regression] RISC-V: ICE in emit_move_insn, at expr.cc:4635 Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal

[Bug target/118075] [15 Regression] RISC-V: Miscompile at -O3 zvl 256 since r15-4746-g30435cc2610

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118075 Patrick O'Neill changed: What|Removed |Added Target||riscv*-*-* CC|

[Bug target/118075] New: [15 Regression] RISC-V: Miscompile at -O3 zvl 256 since r15-4746-g30435cc2610

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118075 Bug ID: 118075 Summary: [15 Regression] RISC-V: Miscompile at -O3 zvl 256 since r15-4746-g30435cc2610 Product: gcc Version: 15.0 Status: UNCONFIRMED Severity:

[Bug target/117990] [15] RISC-V: Miscompile at -O3 zvl 256 since r15-4746-g30435cc2610

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117990 --- Comment #1 from Patrick O'Neill --- -flto can be replaced with -fwhole-program: -march=rv64gcv_zvl256b -fwhole-program -O3 -mrvv-vector-bits=zvl test.c -o user-config.out

[Bug target/117990] New: [15] RISC-V: Miscompile at -O3 zvl 256 since r15-4746-g30435cc2610

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117990 Bug ID: 117990 Summary: [15] RISC-V: Miscompile at -O3 zvl 256 since r15-4746-g30435cc2610 Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal

[Bug target/117682] [15 Regression] rv64gcv_zvl256b miscompile since r15-3228-g771256bcb9d

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117682 --- Comment #2 from Patrick O'Neill --- (In reply to Richard Biener from comment #1) > Possibly -fno-vect-cost-model allows bisecting to something else. No dice - the change is emitting an insn count for more patterns rather than immediately fa

[Bug target/117682] New: [15 Regression] rv64gcv_zvl256b miscompile since r15-3228-g771256bcb9d

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117682 Bug ID: 117682 Summary: [15 Regression] rv64gcv_zvl256b miscompile since r15-3228-g771256bcb9d Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal

[Bug target/117594] [15] RISC-V: Miscompile at -O3 since r15-4012-gba7632674a2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117594 Patrick O'Neill changed: What|Removed |Added Summary|[15] RISC-V: Miscompile at |[15] RISC-V: Miscompile at

[Bug target/117594] [15] RISC-V: Miscompile at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117594 --- Comment #3 from Patrick O'Neill --- Yep 36 looks correct but I get a zero for -O3: > /scratch/tc-testing/tc-compiler-fuzz-trunk/build-gcv/bin/riscv64-unknown-linux-gnu-gcc > -march=rv64gcv -O3 red.c -o user-config.out -fno-strict-aliasing >

[Bug target/117594] [15] RISC-V: Miscompile at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117594 --- Comment #1 from Patrick O'Neill --- Testcase that doesn't underflow: unsigned a; short b, d, e; long long c; int main() { short h = d; short *z = &h; for (_Bool i = 0; i < 1; i = 1) for (unsigned j = 0; j < (z[i] ?: 10); j += 3) {

[Bug target/117594] New: [15] RISC-V: Miscompile at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117594 Bug ID: 117594 Summary: [15] RISC-V: Miscompile at -O3 Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target

[Bug tree-optimization/117567] New: [15 Regression] ICE: segfault during GIMPLE pass: vect

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117567 Bug ID: 117567 Summary: [15 Regression] ICE: segfault during GIMPLE pass: vect Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal Priority: P3 Comp

[Bug rtl-optimization/117506] [15 Regression] ICE: in decompose, at wide-int.h:1049 with -O3 -funroll-loops

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117506 --- Comment #1 from Patrick O'Neill --- Godbolt: https://godbolt.org/z/PxqzhbnKa

[Bug rtl-optimization/117506] New: [15 Regression] ICE: in decompose, at wide-int.h:1049 with -O3 -funroll-loops

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117506 Bug ID: 117506 Summary: [15 Regression] ICE: in decompose, at wide-int.h:1049 with -O3 -funroll-loops Product: gcc Version: 15.0 Status: UNCONFIRMED Severity:

[Bug tree-optimization/117486] [15 Regression] ICE: in vect_build_slp_tree_2, at tree-vect-slp.cc:2027

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117486 --- Comment #3 from Patrick O'Neill --- (In reply to Andrew Pinski from comment #2) > I think you reduced the testcase case a little too much. Anyways confirmed, > see the attached testcase for one that fails on aarch64 with -march=armv9-a. Tha

[Bug tree-optimization/117486] New: [15 Regression] ICE: in vect_build_slp_tree_2, at tree-vect-slp.cc:2027

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117486 Bug ID: 117486 Summary: [15 Regression] ICE: in vect_build_slp_tree_2, at tree-vect-slp.cc:2027 Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal

[Bug tree-optimization/117484] New: [15 Regression] ICE: segfault during GIMPLE pass: vect

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117484 Bug ID: 117484 Summary: [15 Regression] ICE: segfault during GIMPLE pass: vect Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal Priority: P3 Comp

[Bug target/117483] New: [15 Regression] ICE: in merge, at config/riscv/riscv-vsetvl.cc:2106

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117483 Bug ID: 117483 Summary: [15 Regression] ICE: in merge, at config/riscv/riscv-vsetvl.cc:2106 Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal

[Bug target/115372] [15 Regression] RISCV pr97428.c scan-tree-dump-times after r15-812-gc71886f2ca2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115372 --- Comment #3 from Patrick O'Neill --- (In reply to Richard Biener from comment #2) > I don't remember seeing FAIL: gcc.dg/vect/pr97428.c in the precommit CI, this > one should get one SLP instance and seeing zero means it now fails to SLP on >

[Bug c++/116740] New: [15 Regression] ICE: in set_identifier_type_value_with_scope, at cp/name-lookup.cc:5098

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116740 Bug ID: 116740 Summary: [15 Regression] ICE: in set_identifier_type_value_with_scope, at cp/name-lookup.cc:5098 Product: gcc Version: 15.0 Status: UN

[Bug ipa/116721] New: [15 Regression] ICE: in merge, at ipa-modref-tree.cc:176

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116721 Bug ID: 116721 Summary: [15 Regression] ICE: in merge, at ipa-modref-tree.cc:176 Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal Prio

[Bug target/116720] New: [13/14/15 Regression] RISC-V: Unrecognizable insn with xtheadmemidx on rv32

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116720 Bug ID: 116720 Summary: [13/14/15 Regression] RISC-V: Unrecognizable insn with xtheadmemidx on rv32 Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: no

[Bug target/116715] RISC-V: Miscompile at -O2 with -march=rv64id_zbs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116715 --- Comment #1 from Patrick O'Neill --- Slightly improved testcase: int a, b; int d; long f = 695372830942; int main() { d = 0; for (; d < 1; d = 1) --f; d |= b = f; long h = d; a = h >> 40; __builtin_printf("%lX\n", a); } > /sc

[Bug target/116715] New: RISC-V: Miscompile at -O2 with -march=rv64id_zbs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116715 Bug ID: 116715 Summary: RISC-V: Miscompile at -O2 with -march=rv64id_zbs Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component:

[Bug target/116655] New: RISC-V: ICE with -mrvv-max-lmul=dynamic in compute_nregs_for_mode

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116655 Bug ID: 116655 Summary: RISC-V: ICE with -mrvv-max-lmul=dynamic in compute_nregs_for_mode Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal

[Bug target/116544] [15] RISC-V: Miscompile at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116544 --- Comment #1 from Patrick O'Neill --- Forgot to add - found via fuzzer.

[Bug target/116544] New: [15] RISC-V: Miscompile at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116544 Bug ID: 116544 Summary: [15] RISC-V: Miscompile at -O3 Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target

[Bug middle-end/115495] [15 Regression] ICE in smallest_mode_for_size, at stor-layout.cc:356 during combine on RISC-V rv64gcv_zvl256b at -O3 since r15-1042-g68b0742a49d

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115495 --- Comment #8 from Patrick O'Neill --- I'm not able to replicate it either (and the fuzzer hasn't found a duplicate that is still valid)

[Bug target/116242] [meta-bug] Tracker for zvl issues in RISC-V

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116242 Bug 116242 depends on bug 116202, which changed state. Bug 116202 Summary: RISC-V: Miscompile at -O3 with zvl256b https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116202 What|Removed |Added

[Bug target/116202] RISC-V: Miscompile at -O3 with zvl256b

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116202 Patrick O'Neill changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug tree-optimization/116351] New: [15 only] RISC-V ICE: in get_len_load_store_mode, at optabs-tree.cc:664

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116351 Bug ID: 116351 Summary: [15 only] RISC-V ICE: in get_len_load_store_mode, at optabs-tree.cc:664 Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal

[Bug target/116347] New: [13/14/15 only] RISC-V: Duplicate entries for -mtune in --target-help

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116347 Bug ID: 116347 Summary: [13/14/15 only] RISC-V: Duplicate entries for -mtune in --target-help Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal

[Bug target/116318] RISC-V: Miscompile at -O1 with -fwhole-program

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116318 Patrick O'Neill changed: What|Removed |Added Resolution|--- |INVALID Status|UNCONFIRME

[Bug target/116318] New: RISC-V: Miscompile at -O1 with -fwhole-program

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116318 Bug ID: 116318 Summary: RISC-V: Miscompile at -O1 with -fwhole-program Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: t

[Bug ipa/116296] New: [15 Regression] internal compiler error: in merge, at ipa-modref-tree.cc:176 at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116296 Bug ID: 116296 Summary: [15 Regression] internal compiler error: in merge, at ipa-modref-tree.cc:176 at -O3 Product: gcc Version: 15.0 Status: UNCONFIRMED Seve

[Bug target/116283] New: [15 Regression] RISC-V rv64id_zbs ICE: unrecognizable insn

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116283 Bug ID: 116283 Summary: [15 Regression] RISC-V rv64id_zbs ICE: unrecognizable insn Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal Pr

[Bug target/116282] New: [15 Regression] RISC-V rv64id_zba_zbkb ICE: could not split insn

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116282 Bug ID: 116282 Summary: [15 Regression] RISC-V rv64id_zba_zbkb ICE: could not split insn Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal

[Bug target/116280] New: [15 Regression] RISC-V: expected mode RVVMF8QI for operand 2 of insn pred_vwsllrvvmf4hi but got mode RVVMF2SI

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116280 Bug ID: 116280 Summary: [15 Regression] RISC-V: expected mode RVVMF8QI for operand 2 of insn pred_vwsllrvvmf4hi but got mode RVVMF2SI Product: gcc Version: 15.0

[Bug target/116278] New: [15] RISC-V: Miscompile at -O2 -fwrapv -fno-strict-aliasing

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116278 Bug ID: 116278 Summary: [15] RISC-V: Miscompile at -O2 -fwrapv -fno-strict-aliasing Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal P

[Bug target/116256] New: [15 Regression] RISC-V: testsuite failures since late-combine-pass

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116256 Bug ID: 116256 Summary: [15 Regression] RISC-V: testsuite failures since late-combine-pass Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal

[Bug target/116033] [14 only] RISC-V: -march=rv64gv_xtheadmemidx generates illegal vse8.v insn

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116033 --- Comment #5 from Patrick O'Neill --- Thanks for the quick fix!

[Bug target/116240] New: RISC-V: ICE during RTL pass: combine with -fwrapv -march=rv64imv_xtheadcondmov_xventanacondops at -O2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116240 Bug ID: 116240 Summary: RISC-V: ICE during RTL pass: combine with -fwrapv -march=rv64imv_xtheadcondmov_xventanacondops at -O2 Product: gcc Version: 15.0 Status: UNCONFIR

[Bug target/116204] RISC-V: rv32 miscompile at -O0

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116204 --- Comment #3 from Patrick O'Neill --- Ah - thanks for the quick correction. I had forgotten about that difference.

[Bug target/116204] New: RISC-V: rv32 miscompile at -O0

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116204 Bug ID: 116204 Summary: RISC-V: rv32 miscompile at -O0 Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target

[Bug target/116202] New: RISC-V: Miscompile at -O3 with zvl256b

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116202 Bug ID: 116202 Summary: RISC-V: Miscompile at -O3 with zvl256b Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target

[Bug target/116197] [14/15 only] RISC-V: zvkn does not imply "v" extension

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116197 Patrick O'Neill changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|---

[Bug target/116197] New: [14/15 only] RISC-V: zvkn does not imply "v" extension

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116197 Bug ID: 116197 Summary: [14/15 only] RISC-V: zvkn does not imply "v" extension Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal Priority: P3 Comp

[Bug target/116033] [14 only] RISC-V: -march=rv64gv_xtheadmemidx generates illegal vse8.v insn

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116033 Patrick O'Neill changed: What|Removed |Added Summary|[14/15 only] RISC-V:|[14 only] RISC-V: |

[Bug target/116152] New: RISC-V: Proposed deprecation of LP64E abi

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116152 Bug ID: 116152 Summary: RISC-V: Proposed deprecation of LP64E abi Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target

[Bug target/116150] New: RISC-V: Differences between GCC/LLVM

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116150 Bug ID: 116150 Summary: RISC-V: Differences between GCC/LLVM Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target

[Bug target/116149] New: RISC-V: Miscompile at -O3 with zvl256b -mrvv-vector-bits=zvl

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116149 Bug ID: 116149 Summary: RISC-V: Miscompile at -O3 with zvl256b -mrvv-vector-bits=zvl Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal

[Bug ipa/106783] [12/13/14/15 Regression] ICE in ipa-modref.cc:analyze_function since r12-5247-ga34edf9a3e907de2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106783 Patrick O'Neill changed: What|Removed |Added CC||patrick at rivosinc dot com --- Comme

[Bug middle-end/116134] New: [15 Regression] ICE: 'verify_gimple' failed

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116134 Bug ID: 116134 Summary: [15 Regression] ICE: 'verify_gimple' failed Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: midd

[Bug target/116131] New: [14/15 Regression] RISC-V: Unrecognizable insn with xtheadmemidx

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116131 Bug ID: 116131 Summary: [14/15 Regression] RISC-V: Unrecognizable insn with xtheadmemidx Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal

[Bug target/116086] RISC-V: Hash mismatch with vectorized 557.xz_r at zvl128b and LMUL=m2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116086 --- Comment #8 from Patrick O'Neill --- (In reply to Robin Dapp from comment #6) > Ah, thanks for reducing. I didn't get much further with cvise yesterday. > What were your settings for it? I used the normal settings (just --timeout to fail h

[Bug target/116111] New: RISC-V: 'd' extension allowed with -mabi=ilp32e

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116111 Bug ID: 116111 Summary: RISC-V: 'd' extension allowed with -mabi=ilp32e Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component:

[Bug target/116086] RISC-V: Hash mismatch with vectorized 557.xz_r at zvl128b and LMUL=m2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116086 --- Comment #5 from Patrick O'Neill --- Ah yep that was it :) Reduced testcase: long a; long b; long c[80]; int main() { for (int d = 0; d < 16; d++) c[d] = a; for (int d = 16; d < 80; d++) c[d] = c[d - 2]; for (int d = 0; d < 80;

[Bug target/116086] RISC-V: Hash mismatch with vectorized 557.xz_r at zvl128b and LMUL=m2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116086 --- Comment #3 from Patrick O'Neill --- I'm having trouble reproducing the failure. Here's my commands: > /scratch/tc-testing/tc-compiler-fuzz-trunk/build-gcv/bin/riscv64-unknown-linux-gnu-gcc > -O3 -march=rv64gcv -mrvv-max-lmul=m2 red.c -o use

[Bug target/116085] RISC-V: Miscompile at -O2 with zbb

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116085 --- Comment #3 from Patrick O'Neill --- (In reply to Xi Ruoyao from comment #2) > Maybe add __attribute__((noipa)) for test() and merge the files. That worked, thanks! Testcase: int a = 2; unsigned b = 0x8000; int arr_5[2][23]; void test(i

[Bug target/116085] RISC-V: Miscompile at -O2 with zbb

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116085 --- Comment #1 from Patrick O'Neill --- Tested using r15-2276-gd2fc64c8578

[Bug target/116085] New: RISC-V: Miscompile at -O2 with zbb

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116085 Bug ID: 116085 Summary: RISC-V: Miscompile at -O2 with zbb Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target

[Bug target/114665] [14/15 only] RISC-V rv64gcv: miscompile at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114665 --- Comment #11 from Patrick O'Neill --- (In reply to Robin Dapp from comment #10) > Arg, no, disregard. I was just looking for FFB5 as a failure but I'm > actually still seeing FFB5 for -O2, -O3, rv64gc etc. Ah bummer. Hopefully someo

[Bug target/116035] [14/15] RISC-V: -march=rv64g_xtheadmemidx_zba generates illegal lwu insn

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116035 --- Comment #8 from Patrick O'Neill --- (In reply to Sam James from comment #7) > (In reply to Patrick O'Neill from comment #5) ... > > Typically I use [14/15 Regression] if I'm sure it's a regression (ex. the > > feature exists in prior version

[Bug target/116035] [14/15] RISC-V: -march=rv64g_xtheadmemidx_zba generates illegal lwu insn

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116035 --- Comment #5 from Patrick O'Neill --- (In reply to Sam James from comment #3) > I assume this is a '[14/15 regression]', or does < 14 not support these > instructions and you're using it just to say what's affected? If the latter, > it's count

[Bug target/116059] [14/15 Regression] Miscompile at -O2 since r14-6420-g85c5efcffed

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116059 --- Comment #2 from Patrick O'Neill --- Thanks, I'll take a look at the riscv side and see what I can find out.

[Bug target/114665] [14] RISC-V rv64gcv: miscompile at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114665 --- Comment #8 from Patrick O'Neill --- Bisected to r14-3840-g88a0a883960 but that isn't the offending patch. Can't find a baseline with --param=riscv-autovec-preference=scalable so I guess this isn't bisectable.

[Bug tree-optimization/116059] New: [14/15 Regression] Miscompile at -O2 since r14-6420-g85c5efcffed

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116059 Bug ID: 116059 Summary: [14/15 Regression] Miscompile at -O2 since r14-6420-g85c5efcffed Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal

[Bug middle-end/114196] [13 Regression] Fixed length vector ICE: in vect_peel_nonlinear_iv_init, at tree-vect-loop.cc:9454

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114196 Patrick O'Neill changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED

[Bug target/114916] [14/15] RISC-V rv64gcv_zvl256b: miscompile at -O3 with -mrvv-vector-bits=zvl -fwhole-program

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114916 Patrick O'Neill changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED

[Bug target/114665] [14] RISC-V rv64gcv: miscompile at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114665 --- Comment #7 from Patrick O'Neill --- Retested using r15-2217-ga3f03891065. It's changed slightly but is still reproducible on my machine :-/ > /scratch/tc-testing/tc-compiler-fuzz-trunk/build-gcv/bin/riscv64-unknown-linux-gnu-gcc > -march=r

[Bug target/116039] New: [15] rv64gc miscompile at -O3 with -fno-strict-aliasing since r15-1901-g98914f9eba5

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116039 Bug ID: 116039 Summary: [15] rv64gc miscompile at -O3 with -fno-strict-aliasing since r15-1901-g98914f9eba5 Product: gcc Version: 15.0 Status: UNCONFIRMED Seve

[Bug target/116036] [14/15] RISCV: internal compiler error: in riscv_expand_mult_with_const_int with -march=rv64idv

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116036 --- Comment #1 from Patrick O'Neill --- Here's the assert that gets triggered: /* We use multiplication for remaining cases. */ gcc_assert ( TARGET_MUL && "M-extension must be enabled to calculate the poly_int " "size/offset.");

[Bug target/116036] New: [14/15] RISCV: internal compiler error: in riscv_expand_mult_with_const_int with -march=rv64idv

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116036 Bug ID: 116036 Summary: [14/15] RISCV: internal compiler error: in riscv_expand_mult_with_const_int with -march=rv64idv Product: gcc Version: 15.0 Status: UNCONFIRMED

[Bug target/116035] New: [14/15] RISC-V: -march=rv64g_xtheadmemidx_zba generates illegal lwu insn

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116035 Bug ID: 116035 Summary: [14/15] RISC-V: -march=rv64g_xtheadmemidx_zba generates illegal lwu insn Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: norma

[Bug target/116033] New: [14/15] RISC-V: -march=rv64gv_xtheadmemidx generates illegal vse8.v insn

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116033 Bug ID: 116033 Summary: [14/15] RISC-V: -march=rv64gv_xtheadmemidx generates illegal vse8.v insn Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: norma

[Bug tree-optimization/115959] New: [15 Regression] rv64gcv ICE: segfault during GIMPLE pass: vect

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115959 Bug ID: 115959 Summary: [15 Regression] rv64gcv ICE: segfault during GIMPLE pass: vect Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal

[Bug middle-end/115703] New: [15 Regression] rv64gcv_zvl256b miscompile since r15-1579-g792f97b44ff

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115703 Bug ID: 115703 Summary: [15 Regression] rv64gcv_zvl256b miscompile since r15-1579-g792f97b44ff Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal

[Bug tree-optimization/115669] New: [15 Regression] rv64gcv -fwrapv miscompile since r15-1006-gd93353e6423

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115669 Bug ID: 115669 Summary: [15 Regression] rv64gcv -fwrapv miscompile since r15-1006-gd93353e6423 Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal

[Bug rtl-optimization/115495] [15 Regression] ICE in smallest_mode_for_size, at stor-layout.cc:356 during combine on RISC-V rv64gcv_zvl256b at -O3 since r15-1042-g68b0742a49d

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115495 Patrick O'Neill changed: What|Removed |Added Summary|[15 Regression] ICE in |[15 Regression] ICE in

[Bug rtl-optimization/115495] [15 Regression] ICE in smallest_mode_for_size, at stor-layout.cc:356 during combine on RISC-V rv64gcv_zvl256b at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115495 --- Comment #4 from Patrick O'Neill --- This failure also appears when compiling glibc 2.39 with rv64gcv_zvl512b and rv64gcv_zvl1024b.

[Bug middle-end/115495] New: [15 Regression] ICE in smallest_mode_for_size, at stor-layout.cc:356 during combine on RISC-V rv64gcv_zvl256b at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115495 Bug ID: 115495 Summary: [15 Regression] ICE in smallest_mode_for_size, at stor-layout.cc:356 during combine on RISC-V rv64gcv_zvl256b at -O3 Product: gcc Version

[Bug c/115441] New: Pointer/integer mismatch in __atomic_fetch-* not covered by -Wint-conversion

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115441 Bug ID: 115441 Summary: Pointer/integer mismatch in __atomic_fetch-* not covered by -Wint-conversion Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: n

[Bug target/115375] New: [15 Regression] RISCV scan failures since 2024-05-04

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115375 Bug ID: 115375 Summary: [15 Regression] RISCV scan failures since 2024-05-04 Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal Priority: P3 Compon

[Bug target/115373] [15 Regression] RISCV slp-cond-2-big-array.c slp-cond-2.c scan-tree-dump fails since r15-859-geaaa4b88038

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115373 --- Comment #1 from Patrick O'Neill --- Relevant postcommit issue: https://github.com/patrick-rivos/gcc-postcommit-ci/issues/999

[Bug target/115373] New: [15 Regression] RISCV slp-cond-2-big-array.c slp-cond-2.c scan-tree-dump fails since r15-859-geaaa4b88038

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115373 Bug ID: 115373 Summary: [15 Regression] RISCV slp-cond-2-big-array.c slp-cond-2.c scan-tree-dump fails since r15-859-geaaa4b88038 Product: gcc Version: 15.0

[Bug target/115372] [15 Regression] RISCV pr97428.c scan-tree-dump-times after r15-812-gc71886f2ca2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115372 --- Comment #1 from Patrick O'Neill --- debug output: gcc.target/riscv/rvv/autovec/struct/struct_vect-4.c: vsseg3e64\\.v found 0 times FAIL: gcc.target/riscv/rvv/autovec/struct/struct_vect-4.c scan-assembler-times vsseg3e64\\.v 8 gcc.target/risc

[Bug target/115372] New: [15 Regression] RISCV pr97428.c scan-tree-dump-times after r15-812-gc71886f2ca2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115372 Bug ID: 115372 Summary: [15 Regression] RISCV pr97428.c scan-tree-dump-times after r15-812-gc71886f2ca2 Product: gcc Version: 15.0 Status: UNCONFIRMED Severity

[Bug middle-end/115346] New: [15] Volatile load elimination with packed struct bitfields at -O2

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115346 Bug ID: 115346 Summary: [15] Volatile load elimination with packed struct bitfields at -O2 Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal

[Bug target/115336] [15] rv64gcv_zvl256b miscompile at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115336 Patrick O'Neill changed: What|Removed |Added Keywords||wrong-code Target|

[Bug target/115336] New: [15] rv64gcv_zvl256b miscompile at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115336 Bug ID: 115336 Summary: [15] rv64gcv_zvl256b miscompile at -O3 Product: gcc Version: 15.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target

[Bug c++/115195] [12 Regression] Segfault when instantiating template

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115195 --- Comment #4 from Patrick O'Neill --- Thanks Andrew

[Bug c++/115195] New: [12 Regression] Segfault when instantiating template

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115195 Bug ID: 115195 Summary: [12 Regression] Segfault when instantiating template Product: gcc Version: 12.3.0 Status: UNCONFIRMED Severity: normal Priority: P3 Comp

[Bug tree-optimization/115143] New: [14/15 Regression] tree check: expected class 'type', have 'exceptional' (error_mark) in useless_type_conversion_p, at gimple-expr.cc:85

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115143 Bug ID: 115143 Summary: [14/15 Regression] tree check: expected class 'type', have 'exceptional' (error_mark) in useless_type_conversion_p, at gimple-expr.cc:85 Product: gc

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