https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116280
Bug ID: 116280
Summary: [15 Regression] RISC-V: expected mode RVVMF8QI for
operand 2 of insn pred_vwsllrvvmf4hi but got mode
RVVMF2SI
Product: gcc
Version: 15.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: patrick at rivosinc dot com
Target Milestone: ---
Created attachment 58865
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=58865&action=edit
Unreduced testcase
Testcase:
short a;
char b;
void c(int e[][1][1], char f[][1][1][1][1]) {
for (int g; b;)
for (;;)
for (int h; h < 4073709551572ULL; h += 18446744073709551612U)
a = f[2][2][1][4073709551612][1] << e[1][1][g];
}
Command/backtrace:
> /scratch/tc-testing/tc-compiler-fuzz-trunk/build-gcv/bin/riscv64-unknown-linux-gnu-gcc
> -O3 -march=rv64imdzvbb func.c -c -o /dev/null
during RTL pass: split1
func.c: In function 'c':
func.c:8:1: internal compiler error: expected mode RVVMF4QI for operand 2 of
insn pred_vwsllrvvmf2hi but got mode RVVM1SI.
8 | }
| ^
0x2de6365 internal_error(char const*, ...)
../../../gcc/gcc/diagnostic-global-context.cc:491
0x1878b7e riscv_vector::insn_expander<11>::emit_insn(insn_code, rtx_def**)
../../../gcc/gcc/config/riscv/riscv-v.cc:299
0x186fd1c riscv_vector::emit_vlmax_insn(unsigned int, unsigned int, rtx_def**)
../../../gcc/gcc/config/riscv/riscv-v.cc:398
0x20b9a9f gen_split_10234(rtx_insn*, rtx_def**)
../../../gcc/gcc/config/riscv/autovec-opt.md:1550
0xf04134 try_split(rtx_def*, rtx_insn*, int)
../../../gcc/gcc/emit-rtl.cc:3941
0x12df0c5 split_insn
../../../gcc/gcc/recog.cc:3462
0x12e4127 split_all_insns()
../../../gcc/gcc/recog.cc:3566
0x12e41ec execute
../../../gcc/gcc/recog.cc:4490
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.
Godbolt: https://godbolt.org/z/WcKErGs9M
Found via fuzzer
