On Thu, Dec 5, 2024 at 3:24 PM Philippe Mathieu-Daudé wrote:
>
> In preparation of heterogeneous emulation where cores with
> different endianness can run concurrently, we need to remove
> the tswap() calls -- which use a fixed per-binary endianness.
>
> Get the endianness of the CPU accessed usin
sa_isa_is_big_endian(xtensa_isa isa);
This file doesn't include stdbool.h and other boolean functions in it
(e.g. xtensa_opcode_is_branch()) return int. I'd suggest sticking with
that. With that change:
Acked-by: Max Filippov
> #ifdef __cplusplus
> }
> diff --git a/target/xtensa
On Sat, Nov 9, 2024 at 10:39 PM Takayuki 'January June' Suwa
wrote:
>
> The second source register of insn "*extzvsi-1bit_addsubx" cannot be the
> same as the destination register, because that register will be overwritten
> with an intermediate value after insn splitting.
>
> /* example #1 *
https://gcc.gnu.org/g:b433140a6cb40acedb2e6cb43c4e5a388e33f805
commit r15-5074-gb433140a6cb40acedb2e6cb43c4e5a388e33f805
Author: Takayuki 'January June' Suwa
Date: Sun Nov 10 15:39:22 2024 +0900
xtensa: Fix the issue in "*extzvsi-1bit_addsubx"
The second source register of insn "*
On Tue, Oct 22, 2024 at 7:31 PM Takayuki 'January June' Suwa
wrote:
>
> In commit bc5a9dab55d13f888a3cdd150c8cf5c2244f35e0 ("gcc: xtensa: reorder
> movsi_internal patterns for better code generation during LRA"), the
> instruction order in "movsi_internal" MD definition was changed to make LRA
>
https://gcc.gnu.org/g:211459e12147e9ed42c0a0947b1b95b551e03ef3
commit r15-4706-g211459e12147e9ed42c0a0947b1b95b551e03ef3
Author: Takayuki 'January June' Suwa
Date: Wed Oct 23 11:31:15 2024 +0900
xtensa: Define TARGET_DIFFERENT_ADDR_DISPLACEMENT_P target hook
In commit bc5a9dab55d1
et/xtensa/cpu.h| 6 ++
> target/xtensa/cpu.c| 2 +-
> target/xtensa/fpu_helper.c | 33 +++--
> 3 files changed, 26 insertions(+), 15 deletions(-)
Reviewed-by: Max Filippov
--
Thanks.
-- Max
n flag because the propagation rules
> will handle everything.)
>
> Signed-off-by: Peter Maydell
> ---
> target/xtensa/fpu_helper.c | 2 ++
> fpu/softfloat-specialize.c.inc | 12 +---
> 2 files changed, 3 insertions(+), 11 deletions(-)
Reviewed-by: Max Filippov
--
Thanks.
-- Max
On Sun, Sep 8, 2024 at 9:57 PM Dmitry Chestnykh wrote:
>
> clang rejects the code where function body is placed
> inside body of another function
>
> Signed-off-by: Dmitry Chestnykh
> ---
> libc/sysdeps/linux/common/rename.c | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff
; Spotted because Coverity (correctly) thought the issue was still
> outstanding.
> ---
> target/xtensa/exc_helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Acked-by: Max Filippov
--
Thanks.
-- Max
On Tue, Jul 23, 2024 at 5:52 PM Takayuki 'January June' Suwa
wrote:
>
> According to the implemented pipeline model, this cost can be assumed to be
> 1 clock cycle.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.cc (xtensa_insn_cost):
> Add a case statement for TYPE_FARITH.
Regtest
On Tue, Jul 23, 2024 at 5:52 PM Takayuki 'January June' Suwa
wrote:
>
> We would like to implement the following to store a single-precision FP
> constant in a hardware FP register:
>
> - Load the bit-exact integer image of the pooled single-precision FP
>constant into an address (integer) reg
On Fri, Jul 19, 2024 at 1:35 PM Takayuki 'January June' Suwa
wrote:
>
> It is not wrong but also not optimal to specify that sibcalls require
> register A0 in RTX generation pass, by misleading DFA into thinking it
> is being used in function body.
> It would be better to specify it in pro_and_epi
https://gcc.gnu.org/g:c1d35de0d94d43b9976aff44001dadd4dd42b7ae
commit r15-2398-gc1d35de0d94d43b9976aff44001dadd4dd42b7ae
Author: Takayuki 'January June' Suwa
Date: Wed Jul 24 06:07:06 2024 +0900
xtensa: Add missing speed cost for TYPE_FARITH in TARGET_INSN_COST
According to the im
https://gcc.gnu.org/g:fb7b82964f54192d0723a45c0657d2eb7c5ac97c
commit r15-2397-gfb7b82964f54192d0723a45c0657d2eb7c5ac97c
Author: Takayuki 'January June' Suwa
Date: Tue Jul 23 16:03:12 2024 +0900
xtensa: Fix suboptimal loading of pooled constant value into hardware
single-precision FP regi
https://gcc.gnu.org/g:8ebb1d79ea16f37214c33d853061d3c9cf5e7f46
commit r15-2396-g8ebb1d79ea16f37214c33d853061d3c9cf5e7f46
Author: Takayuki 'January June' Suwa
Date: Sat Jul 20 05:35:33 2024 +0900
xtensa: Fix the regression introduce by r15-959-gbe9b3f4375e7
It is not wrong but also
On Sun, Jul 14, 2024 at 4:05 AM Takayuki 'January June' Suwa
wrote:
>
> They were once mistakenly removed with
> "xtensa: Remove old broken tweak for leaf function", but caused unwanted
> register spills.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.h (LEAF_REGISTERS, LEAF_REG_REMAP):
>
On Sun, Jul 14, 2024 at 4:05 AM Takayuki 'January June' Suwa
wrote:
>
> [U]FLOAT.S machine instruction in Xtensa ISA, which converts an integer to
> a hardware single-precision FP register, has the ability to divide the
> result by power of two (0 to 15th).
>
> Similarly, [U]TRUNC.S instruction, w
On Sun, Jul 14, 2024 at 4:05 AM Takayuki 'January June' Suwa
wrote:
>
> No functional changes.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.cc
> (gen_int_relational, gen_float_relational): Replace tempvar-based
> value-swapping codes with std::swap.
> * config/xten
https://gcc.gnu.org/g:f9c7775f58798a051b57356ad321b758a2ee837d
commit r15-2392-gf9c7775f58798a051b57356ad321b758a2ee837d
Author: Takayuki 'January June' Suwa
Date: Sun Jul 14 20:04:15 2024 +0900
xtensa: Make use of scaled [U]FLOAT/TRUNC.S instructions
[U]FLOAT.S machine instructio
https://gcc.gnu.org/g:56c4979dd8be40681f2724861fc41ae6135e1e78
commit r15-2391-g56c4979dd8be40681f2724861fc41ae6135e1e78
Author: Takayuki 'January June' Suwa
Date: Sun Jul 14 20:03:13 2024 +0900
xtensa: Make use of std::swap where appropriate
No functional changes.
gcc/Ch
gcc/
* config/xtensa/xtensa.cc (xtensa_option_override_after_change):
New function.
(TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE): Define as
xtensa_option_override_after_change.
(xtensa_option_override): Call
xtensa_option_override_after_change.
---
gcc/con
https://gcc.gnu.org/g:9d5d6e61500411ea9043258e300d5b0f57e5c391
commit r15-2385-g9d5d6e61500411ea9043258e300d5b0f57e5c391
Author: Max Filippov
Date: Fri Jul 19 17:27:03 2024 -0700
gcc: xtensa: disable late-combine by default
gcc/
* config/xtensa/xtensa.cc
per.c
> @@ -991,7 +991,7 @@ uint32_t HELPER(rptlb1)(CPUXtensaState *env, uint32_t s)
> uint32_t HELPER(pptlb)(CPUXtensaState *env, uint32_t v)
> {
> unsigned nhits;
> -unsigned segment = XTENSA_MPU_PROBE_B;
> +unsigned segment;
The change suggests that coverity is ok
On Mon, Jul 15, 2024 at 10:21:18AM -0700, Ian Lance Taylor wrote:
> Can you see whether this patch works for FDPIC support? This is based
> on your patch but has various changes. Thanks.
Yes, it is working.
--
Thanks.
-- Max
On Wed, Jul 10, 2024 at 12:49 PM Ian Lance Taylor wrote:
> On Sun, May 26, 2024 at 11:51 PM Max Filippov wrote:
> > diff --git a/libbacktrace/internal.h b/libbacktrace/internal.h
> > index 4fa0af8cb6c9..456911166026 100644
> > --- a/libbacktrace/internal.h
> > ++
On Tue, Jun 18, 2024 at 10:00 PM Takayuki 'January June' Suwa
wrote:
>
> This patch makes avoid inserting a MEMW instruction before a load/store
> nstruction with volatile memory reference if there is already a MEMW
> immediately before it.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.cc
https://gcc.gnu.org/g:0982552bc4eeffb5520deba10dedecfb2390a8de
commit r15-1453-g0982552bc4eeffb5520deba10dedecfb2390a8de
Author: Takayuki 'January June' Suwa
Date: Wed Jun 19 13:59:54 2024 +0900
xtensa: Eliminate double MEMW insertions for volatile memory
This patch makes avoid in
On Tue, Jun 18, 2024 at 7:56 PM Takayuki 'January June' Suwa
wrote:
>
> The previous constant synthesis logic had some issues that were non-fatal
> but worth considering:
>
> - It didn't work with DFmode literals, because those were cast to SImode
>rather SFmode when splitting into two natural
https://gcc.gnu.org/g:23141088e8fb50bf916ac0b2e364b1eef9f3569d
commit r15-1433-g23141088e8fb50bf916ac0b2e364b1eef9f3569d
Author: Takayuki 'January June' Suwa
Date: Wed Jun 19 11:55:57 2024 +0900
xtensa: constantsynth: Reforge to fix some non-fatal issues
The previous constant synt
Hi Suwa-san,
On Mon, Jun 17, 2024 at 04:17:15PM +0900, Takayuki 'January June' Suwa wrote:
> The previous constant synthesis logic had some issues that were non-fatal
> but worth considering:
>
> - It didn't work with DFmode literals, because those were cast to SImode
> rather SFmode when split
On Sun, May 26, 2024 at 11:50 PM Max Filippov wrote:
>
> Instead of a single base address FDPIC ELF files use load map: a
> structure with an array of mappings for individual segments. Change
> libbacktrace functions and structures to support that.
Ping?
> libbacktrace/
ch is more correct (if we were to support a different accel).
>
> Reported-by: Anton Johansson
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/xtensa/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Acked-by: Max Filippov
--
Thanks.
-- Max
On Mon, Jun 3, 2024 at 11:43 PM wrote:
> On 3 June 2024 18:23:33 CEST, Max Filippov wrote:
> >On Mon, Jun 3, 2024 at 6:03 AM wrote:
> >> On 24 April 2024 13:36:55 CEST, Max Filippov wrote:
> >> >Make rule that announces and makes static libc archive can generate
On Mon, Jun 3, 2024 at 6:03 AM wrote:
> On 24 April 2024 13:36:55 CEST, Max Filippov wrote:
> >Make rule that announces and makes static libc archive can generate
> >command line that is too long when a full path O= option is used. That
> >breaks the build with
On Tue, May 21, 2024 at 12:01 AM Max Filippov wrote:
> On Mon, May 20, 2024 at 9:12 PM Waldemar Brodkorb wrote:
> > Is the uClibc-ng port ready to commit or do you have any changes
> > open?
>
> There's one fix for the xtensa port, I will resend the fixed version
> i
This change implements Xtensa FDPIC ABI as specified in the first
version of the following document:
https://github.com/jcmvbkbc/xtensa-abi/blob/master/fdpic-xtensa.txt
Signed-off-by: Max Filippov
---
The toolchain components matching the libc are available in
the following repositories with
On Fri, May 31, 2024 at 07:24:48PM +0900, Takayuki 'January June' Suwa wrote:
> No functional changes.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa-protos.h (xtensa_expand_call):
> Add the third argument as boolean.
> (xtensa_expand_epilogue): Remove the first argument.
>
On Fri, May 31, 2024 at 07:23:13PM +0900, Takayuki 'January June' Suwa wrote:
> No functional changes.
>
> gcc/ChangeLog:
>
> * config/xtensa/predicates.md
> (subreg_HQI_lowpart_operator, xtensa_sminmax_operator):
> New operator predicates.
> * config/xtensa/xtensa-protos.
https://gcc.gnu.org/g:be9b3f4375e74b6f10dd15fc563c93f803e91db5
commit r15-959-gbe9b3f4375e74b6f10dd15fc563c93f803e91db5
Author: Takayuki 'January June' Suwa
Date: Fri May 31 19:24:48 2024 +0900
xtensa: Prepend "(use A0_REG)" to sibling call CALL_INSN_FUNCTION_USAGE
instead of emitting it
https://gcc.gnu.org/g:68cda24d3ac12292a599ff8f9b58fdbc95baba4e
commit r15-958-g68cda24d3ac12292a599ff8f9b58fdbc95baba4e
Author: Takayuki 'January June' Suwa
Date: Fri May 31 19:23:13 2024 +0900
xtensa: Simplify several MD templates
No functional changes.
gcc/ChangeLog:
On Thu, May 30, 2024 at 6:33 AM Takayuki 'January June' Suwa
wrote:
>
> In commit ad89d820bf, an "epilogue_done" member was added to the
> machine_function structure, but it is sufficient to use the existing
> "epilogue_completed" global variable.
>
> gcc/ChangeLog:
>
> * config/xtensa/xte
On Thu, May 30, 2024 at 6:33 AM Takayuki 'January June' Suwa
wrote:
>
> Instead of comparing directly, this patch replaces as much as possible with
> macros that determine RTX code such as REG_P(), SUBREG_P() or MEM_P(), etc.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.cc (xtensa_valid_m
https://gcc.gnu.org/g:1b58f46ba2079b327580ffa1720c0b40ab3db74d
commit r15-936-g1b58f46ba2079b327580ffa1720c0b40ab3db74d
Author: Takayuki 'January June' Suwa
Date: Thu May 30 22:32:24 2024 +0900
xtensa: Use epilogue_completed rather than cfun->machine->epilogue_done
In commit ad89d
https://gcc.gnu.org/g:1e091097b1b42fed562a6d80a6e08603d1c648a2
commit r15-935-g1e091097b1b42fed562a6d80a6e08603d1c648a2
Author: Takayuki 'January June' Suwa
Date: Thu May 30 22:32:24 2024 +0900
xtensa: Use REG_P(), MEM_P(), etc. instead of comparing GET_CODE()
Instead of comparing
On Mon, May 27, 2024 at 12:01 AM Rainer Orth
wrote:
> > This is an RFC series that adds FDPIC ELF target support to
> > libbacktrace.
> >
> > While debugging this I've noticed that there's no unwinding info for the
> > libstdc++ version of libbacktrace, which made backtraces empty for me,
> > both
bc.
Adding -funwind-tables to the libstdc++ version of libbacktrace fixed
that. Which makes me wonder how it works for other architectures?
Max Filippov (2):
libbacktrace: add FDPIC support
libstdc++-v3/src/libbacktrace: add -funwind-tables
libbacktrace/dwarf.c
Instead of a single base address FDPIC ELF files use load map: a
structure with an array of mappings for individual segments. Change
libbacktrace functions and structures to support that.
libbacktrace/
PR libbacktrace/114941
* dwarf.c: Include or if available.
(struct d
libstdc++-v3/
* src/libbacktrace/Makefile.am (AM_CFLAGS, AM_CXXFLAGS): Add
-funwind-tables
* src/libbacktrace/Makefile.in: Regenerate.
---
libstdc++-v3/src/libbacktrace/Makefile.am | 4 ++--
libstdc++-v3/src/libbacktrace/Makefile.in | 4 ++--
2 files changed, 4 insertions(
a/toolchain/releases/download/2020.07/x86_64-2020.07-xtensa-dc232b-elf.tar.gz
>
> Signed-off-by: Jiaxun Yang
> ---
> Changes in v2:
> - Fix noMMU memory mappings
> - Addressing Max's comments in other patches
> - Link to v1:
> https://lore.kernel.org/r/20240519-qemu-xte
On Tue, May 21, 2024 at 1:20 AM Jiaxun Yang wrote:
> 在2024年5月21日五月 上午8:35，Max Filippov写道：
> >> +++ b/board/emulation/qemu-xtensa/MAINTAINERS
> >> @@ -0,0 +1,7 @@
> >> +QEMU XTENSA 'VIRT' BOARD
> >> +M: Jiaxun Yang
> >> +S: Ma
On Tue, May 21, 2024 at 12:12 AM Max Filippov wrote:
> On Mon, May 20, 2024 at 9:00 AM Jiaxun Yang wrote:
> > >> diff --git a/arch/xtensa/config.mk b/arch/xtensa/config.mk
> > >> index b080e403..3ec936272f25 100644
> > >> --- a/arch/xtensa/confi
On Sun, May 19, 2024 at 1:54 PM Jiaxun Yang wrote:
>
> Introduce the new board, define every bits.
>
> Signed-off-by: Jiaxun Yang
> ---
> arch/xtensa/Kconfig | 5 +++
> board/emulation/qemu-xtensa/Kconfig | 41 +
> board/emulation/qemu-xtensa/MAIN
On Mon, May 20, 2024 at 9:00 AM Jiaxun Yang wrote:
> >> diff --git a/arch/xtensa/config.mk b/arch/xtensa/config.mk
> >> index b080e403..3ec936272f25 100644
> >> --- a/arch/xtensa/config.mk
> >> +++ b/arch/xtensa/config.mk
> >> @@ -7,3 +7,6 @@ PLATFORM_CPPFLAGS += -D__XTENSA__ -mlongcalls
> >>
Hi Waldemar,
On Mon, May 20, 2024 at 9:12 PM Waldemar Brodkorb wrote:
> Is the uClibc-ng port ready to commit or do you have any changes
> open?
There's one fix for the xtensa port, I will resend the fixed version
in a couple days,
along with the new tags for the binutils and gcc.
And then there
On Sun, May 19, 2024 at 1:53 PM Jiaxun Yang wrote:
>
> Add xtensa semihosting driver.
>
> It can't use regular semihosting driver as Xtensa's has it's own
> semihosting ABI.
>
> Note that semihosting supports puts in serial but I never managed to
> get it work, so it's putc only for now.
I wonder
gt; arch/xtensa/include/asm/platform/simcall-iss.h | 73 +++
> arch/xtensa/include/asm/platform/simcall.h | 110
> +++
> 4 files changed, 244 insertions(+)
Reviewed-by: Max Filippov
--
Thanks.
-- Max
On Sun, May 19, 2024 at 1:53 PM Jiaxun Yang wrote:
>
> u-boot.elf target requiures it to work.
Typo.
> Signed-off-by: Jiaxun Yang
> ---
> arch/xtensa/config.mk | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/xtensa/config.mk b/arch/xtensa/config.mk
> index b080e403..3ec936
t that was so until the commit
74ca8d6f5d2e ("remove UCLIBC_HAS_LFS")
removed that definition. It seems to me that that commit removed the wrong
leg of the condition, and that the attached change (completely untested)
should fix it.
--
Thanks.
-- Max
>From c73701dae0ca5a679e67945a6da4d1c395c2e2aa Mon Sep 1
Hello.
This is a draft FDPIC ABI specification for the Xtensa architecture.
Please send comments. I will be implementing the final ABI version in
gcc and binutils.
The Xtensa FDPIC ABI
April 8, 2024
Version 1
Bas
Check that the size passed to memalign() is not greater than PTRDIFF_MAX
before adjusting it, otherwise it may wrap around in the adjustment.
This fixes gcc testsuite test gcc.dg/torture/pr60092.c
Signed-off-by: Max Filippov
---
libc/stdlib/malloc/memalign.c | 5 +
1 file changed, 5
U and noMMU
targets.
Signed-off-by: Max Filippov
---
test/test-skeleton.c | 65 ++--
1 file changed, 50 insertions(+), 15 deletions(-)
diff --git a/test/test-skeleton.c b/test/test-skeleton.c
index 557996d714cd..323a9c645df3 100644
--- a/test/test-skeleton.c
Hi Waldemar,
On Mon, May 6, 2024 at 11:17 AM Max Filippov wrote:
> On Sun, May 5, 2024 at 2:51 AM Waldemar Brodkorb wrote:
> > > On Sat, May 4, 2024 at 12:14 AM Max Filippov wrote:
> > > also the following tests either hang or cause problems,
> > > so I disabled
Hi Waldemar,
On Sun, May 5, 2024 at 2:51 AM Waldemar Brodkorb wrote:
> > On Sat, May 4, 2024 at 12:14 AM Max Filippov wrote:
> > > On Fri, May 3, 2024 at 8:15 PM Waldemar Brodkorb wrote:
> > > > How did you test NPTL/TLS?
> > >
> > > I grepped for t
On Sat, May 4, 2024 at 12:14 AM Max Filippov wrote:
> On Fri, May 3, 2024 at 8:15 PM Waldemar Brodkorb wrote:
> > How did you test NPTL/TLS?
>
> I grepped for the tests explicitly using fork and added them to the
> TESTS_DISABLED in the test/nptl/Makefile.in, and also added
On Sat, May 4, 2024 at 12:14 AM Max Filippov wrote:
> On Fri, May 3, 2024 at 8:15 PM Waldemar Brodkorb wrote:
> > How did you test NPTL/TLS?
...and for TLS I've posted a patch for the testsuite that adds
FDPIC-specific implementations of the test TLS macros.
The whole tls s
On Fri, May 3, 2024 at 8:15 PM Waldemar Brodkorb wrote:
>
> Hi Max,
> Max Filippov wrote,
>
> > On Fri, May 3, 2024 at 5:55 AM Waldemar Brodkorb wrote:
> > > Now I am booting up the system in Qemu with
> > > following command:
> > > qemu-system-
On Fri, May 3, 2024 at 5:55 AM Waldemar Brodkorb wrote:
> Now I am booting up the system in Qemu with
> following command:
> qemu-system-xtensa -nographic -M lx60 -cpu dc233c -kernel
> qemu-xtensa-initramfspiggyback-kernel
>
> Now every command f.e. ls or ps works but gives a Illegal
> Instructi
Hi Waldemar,
On Thu, May 2, 2024 at 7:13 AM Waldemar Brodkorb wrote:
> I am trying your patch series in OpenADK, but it fails with following
> error:
[...]
> ldso/ldso/dl-tls.c: Assembler messages:
> ldso/ldso/dl-tls.c:197: Error: invalid register 'threadptr' for 'rur'
> instruction
> ldso/ldso/
Signed-off-by: Max Filippov
---
test/tls/tls-macros-xtensa.h | 78 +++-
1 file changed, 76 insertions(+), 2 deletions(-)
diff --git a/test/tls/tls-macros-xtensa.h b/test/tls/tls-macros-xtensa.h
index 90fc726f6f6b..6b2621c221cb 100644
--- a/test/tls/tls-macros
Signed-off-by: Max Filippov
---
test/iconv/tst-iconv5.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/test/iconv/tst-iconv5.c b/test/iconv/tst-iconv5.c
index ff3fde5eb180..f8f4fb57c86b 100644
--- a/test/iconv/tst-iconv5.c
+++ b/test/iconv/tst-iconv5.c
@@ -59,7 +59,7
This change generates function descriptors for .preinit_array,
.init_array and .fini_array that are not generated by the gcc after
commit 11189793b6ef60645d5d1126d0bd9d0dd83e6583. This doesn't make
sense, the change in gcc is reverted, so this change is reverted as
well.
This reverts commit 99dfb1
This change implements Xtensa FDPIC ABI as specified in the first
version of the following document:
https://github.com/jcmvbkbc/xtensa-abi/blob/master/fdpic-xtensa.txt
Signed-off-by: Max Filippov
---
The toolchain components matching the libc are available in
the following repositories with
required to keep the ARM FDPIC port functional.
Max Filippov (2):
xtensa: add FDPIC support
Revert "Allow to generate PIE 'static' binary"
Rules.mak | 4 +
extra/Configs/Config.in | 2 +-
extra/Co
Make _init and _fini hidden so that references to these symbols bind
locally in the shared objects. glibc does the same.
Signed-off-by: Max Filippov
---
libc/sysdeps/linux/xtensa/crti.S | 2 ++
1 file changed, 2 insertions(+)
diff --git a/libc/sysdeps/linux/xtensa/crti.S b/libc/sysdeps/linux
Starting with gcc-13 the compiler provides configuration-specific macro
definitions for the target xtensa core. Use them when available instead
of the configuration overlay file xtensa-config.h
Signed-off-by: Max Filippov
---
.../sysdeps/linux/xtensa/bits/xtensa-config.h | 20
linuxthreads use a helper function to invoke signal handlers, this
function needs stack unwinding information to enable stack unwinding
from signal handlers over signal frames.
Signed-off-by: Max Filippov
---
libpthread/linuxthreads/Makefile.in | 2 ++
1 file changed, 2 insertions(+)
diff
: Max Filippov
---
ldso/ldso/arm/elfinterp.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/ldso/ldso/arm/elfinterp.c b/ldso/ldso/arm/elfinterp.c
index 4c268356fb37..9c9a3e8ca7f7 100644
--- a/ldso/ldso/arm/elfinterp.c
+++ b/ldso/ldso/arm/elfinterp.c
@@ -92,7 +92,7
With gcc-14 warnings caused by type mismatches turn to errors:
- (void **) needs explicit conversion operator to become
struct funcdesc_value **entry
- both subexpressions of the ternary operator must be pointers
- %p should be used instead of %x to print a pointer
Signed-off-by: Max Filippov
With gcc-14 warnings caused by type mismatches turn to errors:
- iconv_t is not a pointer type, convert the result directly to iconv_t
in combine_to_from()
- unsigned int is not the same as wchar_t, use temporary wchar_t wc as
an argument for utf8dec_wchar()
Signed-off-by: Max Filippov
Hello,
this series fixes a few type mismatches that have become errors when
building with gcc-14.
Max Filippov (3):
iconv: fix type mismatches
ldso: FDPIC: fix type mismatches
ldso: arm: fix build with gcc-14
ldso/ldso/arm/elfinterp.c| 6 +++---
ldso/ldso/fdpic/dl-inlines.h | 4
as $(AR) argument instead.
Signed-off-by: Max Filippov
---
Makerules | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Makerules b/Makerules
index fe8a7916e657..96f2a71ec49a 100644
--- a/Makerules
+++ b/Makerules
@@ -276,7 +276,7 @@ cmd_compile.mi= $(cmd_compile.m:-c=-E -dD
.
Signed-off-by: Max Filippov
---
Rules.mak | 1 +
1 file changed, 1 insertion(+)
diff --git a/Rules.mak b/Rules.mak
index f2e5791e3d89..27c80f924505 100644
--- a/Rules.mak
+++ b/Rules.mak
@@ -606,6 +606,7 @@ CFLAGS := $(XWARNINGS) $(CPU_CFLAGS) $(SSP_CFLAGS) \
-nostdinc -I$(top_builddir
as $(AR) argument instead.
Signed-off-by: Max Filippov
---
Makerules | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Makerules b/Makerules
index fe8a7916e657..96f2a71ec49a 100644
--- a/Makerules
+++ b/Makerules
@@ -276,7 +276,7 @@ cmd_compile.mi= $(cmd_compile.m:-c=-E -dD
.
Signed-off-by: Max Filippov
---
Rules.mak | 1 +
1 file changed, 1 insertion(+)
diff --git a/Rules.mak b/Rules.mak
index f2e5791e3d89..27c80f924505 100644
--- a/Rules.mak
+++ b/Rules.mak
@@ -606,6 +606,7 @@ CFLAGS := $(XWARNINGS) $(CPU_CFLAGS) $(SSP_CFLAGS) \
-nostdinc -I$(top_builddir
On Thu, Apr 11, 2024 at 5:06 PM Zack Buhman wrote:
>
> I noticed the recent SH4 patches are included in the 9.0.0-rc3 release.
>
> Is it appropriate that I request a wiki.qemu.org account so that I may
> document these changes in https://wiki.qemu.org/ChangeLog/9.0 in a manner
> that is consiste
-sta...@nongnu.org
Signed-off-by: Max Filippov
---
Changes v1->v2:
- split into a separate patch
- add PPC, SPARC and big-endian MIPS
linux-user/syscall.c | 20 +++-
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
in
sysv IPC structures")
Signed-off-by: Max Filippov
---
Changes v1->v2:
- split into a separate patch
linux-user/syscall.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index e384e1424890..d9bfd31c1cad 100644
---
On Fri, Mar 29, 2024 at 5:48 AM Philippe Mathieu-Daudé
wrote:
>
> Hi Max,
>
> On 29/3/24 07:31, Max Filippov wrote:
> > - target_ipc_perm::mode and target_ipc_perm::__seq fields are 32-bit wide
> >on xtensa and thus need to use tswap32
> > - target_msqid_ds::msg_
http://nsz.repo.hu/git/?p=libc-test
Cc: qemu-sta...@nongnu.org
Fixes: a3da8be5126b ("target/xtensa: linux-user: fix sysv IPC structures")
Signed-off-by: Max Filippov
---
linux-user/syscall.c | 19 +++
1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/
Hi Suwa-san,
I've noticed that in xtensa configurations with hardware FPU
function arguments of type float are spilled on the stack although
there's no need for that. E.g. the following function:
int f(float a, float b)
{
return a < b;
}
translates to the following with -O2:
f:
entry
On Fri, Mar 22, 2024 at 1:15 PM Max Filippov wrote:
>
> libgcc/
> * unwind-arm-common.inc (__gnu_personality_sigframe_fdpic): Cast
> last argument of _Unwind_VRS_Set to void *.
> ---
> libgcc/unwind-arm-common.inc | 2 +-
> 1 file changed, 1 insertion(+),
https://gcc.gnu.org/g:c2e68ff9edd5da7a55ba6574b4ce49ce6495b18d
commit r14-9655-gc2e68ff9edd5da7a55ba6574b4ce49ce6495b18d
Author: Max Filippov
Date: Fri Mar 22 13:03:46 2024 -0700
libgcc: arm: fix build for FDPIC target
libgcc/
* unwind-arm-common.inc
On Thu, Mar 21, 2024 at 8:50 AM Philippe Mathieu-Daudé
wrote:
>
> Extract the MMU API and expose it via "mmu.h" so we can
> reuse the methods in target/xtensa/ files.
The MMU/MPU are replaceable configuration blocks in the xtensa
architecture, their internals don't have architecture-wide signific
On Thu, Mar 21, 2024 at 4:36 PM Takayuki 'January June' Suwa
wrote:
>
> int test(int a) {
>return a * 4 + 3;
> }
>
> In the example above, since Xtensa has instructions to add register value
> scaled by 2, 4 or 8 (and corresponding define_insns), we would expect them
> to be used but not,
https://gcc.gnu.org/g:7a01cc711f33530436712a5bfd18f8457a68ea1f
commit r14-9638-g7a01cc711f33530436712a5bfd18f8457a68ea1f
Author: Takayuki 'January June' Suwa
Date: Fri Mar 22 08:36:30 2024 +0900
xtensa: Add supplementary split pattern for "*addsubx"
int test(int a) {
return
libgcc/
* unwind-arm-common.inc (__gnu_personality_sigframe_fdpic): Cast
last argument of _Unwind_VRS_Set to void *.
---
libgcc/unwind-arm-common.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/libgcc/unwind-arm-common.inc b/libgcc/unwind-arm-common.inc
inde
After switching to LRA xtensa backend generates the following code for
saving/loading registers:
movi a9, 0x190
add a9, a9, sp
s32i.n a3, a9, 0
instead of the shorter and more efficient
s32i a3, a9, 0x190
E.g. the following code can be used to reproduce it:
i
https://gcc.gnu.org/g:bc5a9dab55d13f888a3cdd150c8cf5c2244f35e0
commit r14-9480-gbc5a9dab55d13f888a3cdd150c8cf5c2244f35e0
Author: Max Filippov
Date: Thu Mar 14 04:20:36 2024 -0700
gcc: xtensa: reorder movsi_internal patterns for better code generation
during LRA
After switching
| 9 --
> librt/timer_settime.c | 11 +--
> 24 files changed, 193 insertions(+), 36 deletions(-)
> create mode 100644 include/internal/time64_helpers.h
This version looks good to me.
Reviewed-by: Max Filippov
--
Thanks.
-- Max
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