On Sat, Nov 9, 2024 at 10:39 PM Takayuki 'January June' Suwa
<jjsuwa_sys3...@yahoo.co.jp> wrote:
>
> The second source register of insn "*extzvsi-1bit_addsubx" cannot be the
> same as the destination register, because that register will be overwritten
> with an intermediate value after insn splitting.
>
> /* example #1 */
> int test1(int b, int a) {
> return ((a & 1024) ? 4 : 0) + b;
> }
>
> ;; result #1 (incorrect)
> test1:
> extui a2, a3, 10, 1 ;; overwrites A2 before used
> addx4 a2, a2, a2
> ret.n
Interestingly I couldn't reproduce it with the current gcc mainline.
For me it produces the following for the above source:
test1:
mov.n a9, a2
extui a2, a3, 10, 1
addx4 a2, a2, a9
ret.n
With this change the generated code is one instruction shorter,
so applying it still makes sense.
> This patch fixes that.
>
> ;; result #1 (correct)
> test1:
> extui a3, a3, 10, 1 ;; uses A3 and then overwrites
> addx4 a2, a3, a2
> ret.n
>
> However, it should be noted that the first source register can be the same
> as the destination without any problems.
>
> /* example #2 */
> int test2(int a, int b) {
> return ((a & 1024) ? 4 : 0) + b;
> }
>
> ;; result (correct)
> test2:
> extui a2, a2, 10, 1 ;; uses A2 and then overwrites
> addx4 a2, a2, a3
> ret.n
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.md (*extzvsi-1bit_addsubx):
> Add '&' to the destination register constraint to indicate that
> it is 'earlyclobber', append '0' to the first source register
> constraint to indicate that it can be the same as the destination
> register, and change the split condition from 1 to reload_completed
> so that the insn will be split only after RA in order to obtain
> allocated registers that satisfy the above constraints.
> ---
> gcc/config/xtensa/xtensa.md | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
Regtested for target=xtensa-linux-uclibc, no new regressions.
Committed to master
--
Thanks.
-- Max
