在 2025/1/16 下午8:59, Xi Ruoyao 写道:
On Thu, 2025-01-16 at 20:52 +0800, Xi Ruoyao wrote:
On Thu, 2025-01-16 at 20:30 +0800, Lulu Cheng wrote:
在 2025/1/15 下午6:10, Xi Ruoyao 写道:
diff --git a/gcc/config/loongarch/loongarch.cc
b/gcc/config/loongarch/loongarch.cc
index 9d97f0216f0..3a8e1297bd3
在 2025/1/15 下午6:10, Xi Ruoyao 写道:
diff --git a/gcc/config/loongarch/loongarch.cc
b/gcc/config/loongarch/loongarch.cc
index 9d97f0216f0..3a8e1297bd3 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -3929,14 +3929,31 @@ loongarch_rtx_costs (rtx x, machine
LGTM!
Thanks!
在 2025/1/15 下午6:09, Xi Ruoyao 写道:
On 64-bit capable LoongArch hardware, alsl.wu is similar to alsl.w but
zero-extending the 32-bit result.
gcc/ChangeLog:
* config/loongarch/loongarch.md (alslsi3_extend): Add alsl.wu.
gcc/testsuite/ChangeLog:
* gcc.target/loonga
Pushed to r15-6817.
在 2025/1/10 上午10:27, mengqinggang 写道:
Generate 0x1010 instead of 0x101>>12 for lu12i.w. lu32i.d and lu52i.d use
the same processing.
gcc/ChangeLog:
* config/loongarch/lasx.md: Use new loongarch_output_move.
* config/loongarch/loongarch-protos.h (loongarc
Pushed to r15-6755.
在 2025/1/7 下午9:04, chenxiaolong 写道:
When analyzing 525 on LoongArch architecture, it was found that the
for loop of hotspot function x264_pixel_satd_8x4 could not be quantized
256-bit due to the cost of vec_construct setting. After re-adjusting
vec_construct, the performan
在 2025/1/10 上午10:03, Lulu Cheng 写道:
Pushed to r15-6755.
Sorry, I replied to the wrong email.
在 2025/1/6 下午4:16, mengqinggang 写道:
Generate 0x1010 instead of 0x101>>12 for lu12i.w. lu32i.d and
lu52i.d use
the same processing.
gcc/ChangeLog:
* config/loongarch/lasx.md: U
Pushed to r15-6755.
在 2025/1/6 下午4:16, mengqinggang 写道:
Generate 0x1010 instead of 0x101>>12 for lu12i.w. lu32i.d and lu52i.d use
the same processing.
gcc/ChangeLog:
* config/loongarch/lasx.md: Use new loongarch_output_move.
* config/loongarch/loongarch-protos.h (loongarch_
在 2025/1/8 下午11:16, Xi Ruoyao 写道:
On Tue, 2025-01-07 at 10:44 +0800, Lulu Cheng wrote:
After changing this cost from 1 to 3, the performance of spec2006
401 473 416 465 482 can be improved by about 2% on LA664.
Would this fix https://gcc.gnu.org/PR114978 (or at least make it
latent)?
The
在 2025/1/7 下午12:47, chenxiaolong 写道:
When analyzing 525 on LoongArch architecture, it was found that the
for loop of hotspot function x264_pixel_satd_8x4 could not be quantized
256-bit due to the cost of vec_construct setting. After re-adjusting
vec_construct, the performance of 525 program
The target pragmas defined correspond to the target function attributes.
This implementation is derived from AArch64.
gcc/ChangeLog:
* config/loongarch/loongarch-protos.h
(loongarch_reset_previous_fndecl): Add function declaration.
(loongarch_save_restore_target_globals)
在 2025/1/2 下午5:46, Zhou Zhao 写道:
If SImode reg is continuous left shifted twice, combine related
instruction to one.
gcc/ChangeLog:
* config/loongarch/loongarch.md (extsv_ashlsi3):
New template
Hi, zhaozhou:
The indentation here is wrong, it needs to be aligned with *.
Pushed to r15-6617.
在 2024/12/31 下午7:33, Deng Jianbo 写道:
In LoongArch, currently uses instruction movgr2fr.{d|w} to move zero
from fixed-point register to floating-pointer regsiter for initializing
fp register to zero. When LSX or LASX is enabled, we can use instruction
vxor.v which has lower la
Add function attributes support for LoongArch.
Currently, the following items are supported:
__attribute__ ((target ("{no-}strict-align")))
__attribute__ ((target ("cmodel=")))
__attribute__ ((target ("arch=")))
__attribute__ ((target ("tune=")))
__attribut
__attribute__ ((target ("{no-}lsx")))
__attribute__ ((target ("{no-}lasx")))
Lulu Cheng (2):
LoongArch: Implement target attribute.
LoongArch: Implement target pragma.
gcc/attr-urls.def | 6 +
gcc/config.gcc| 2 +-
After changing this cost from 1 to 3, the performance of spec2006
401 473 416 465 482 can be improved by about 2% on LA664.
Add option '-maddr-reg-reg-cost='.
gcc/ChangeLog:
* config/loongarch/genopts/loongarch.opt.in: Add
option '-maddr-reg-reg-cost='.
* config/loongarch
Pushed to r15-6493.
在 2024/12/30 上午10:39, Guo Jie 写道:
The optimization example is as follows.
From:
if (condition)
dest += 1 << 16;
To:
dest += (condition ? 1 : 0) << 16;
It does not use maskeqz and masknez, thus reducing the number of
instructions.
gcc/ChangeLog:
* config
Pushed to r15-6491.
在 2024/12/30 上午10:38, Guo Jie 写道:
gcc/ChangeLog:
* config/loongarch/lasx.md (vec_unpacks_lo_): Redefine.
(vec_unpacku_lo_): Ditto.
(lasx_vext2xv_h_b): Replaced by vec_unpack_lo_v32qi.
(vec_unpack_lo_v32qi): New insn.
(lasx_vext2xv_w_h)
Pushed to r15-6492.
在 2024/12/30 下午3:12, Guo Jie 写道:
gcc/ChangeLog:
* config/loongarch/lasx.md (lasx_xvabsd_s_): Remove.
(abd3): New insn pattern.
(lasx_xvabsd_u_): Remove.
* config/loongarch/loongarch-builtins.cc (CODE_FOR_lsx_vabsd_b):
Rename.
(
Pushed to r15-6490.
在 2024/12/30 上午10:38, Guo Jie 写道:
For some instruction patterns with commutative operands,
the order of operands needs to be adjusted to match the rules.
gcc/ChangeLog:
* config/loongarch/loongarch.md
(bytepick_d__rev): New combiner.
(bstrpick_alsl_p
Pushed to r15-6489.
在 2024/12/30 上午10:37, Guo Jie 写道:
There are two aspects that affect the matching of instruction templates:
1. vec_duplicate is redundant in the following operations.
set (match_operand:V4DI ...)
(vec_duplicate:V4DI (vec_select:V4DI ...))
2. The range of values
Pushed to r15-6488.
在 2024/12/30 上午10:37, Guo Jie 写道:
The xvexth related instructions operate SEPARATELY according to
the high and low 128 bits, and sign/zero extend the upper half
of every 128 bits in src to the corresponding 128 bits in dest.
For xvexth.d.w, the rule for the first element of
Pushed to r15-6487.
在 2024/12/30 上午10:34, Guo Jie 写道:
gcc/ChangeLog:
* config/loongarch/lasx.md: Remove useless code.
* config/loongarch/lsx.md: Ditto.
---
gcc/config/loongarch/lasx.md | 66
gcc/config/loongarch/lsx.md | 35 -
Pushed to r15-6477.
在 2024/12/25 下午5:59, Jiahao Xu 写道:
In order to support vectorization of loops with multiple exits, this
patch adds the implementation of the conditional branch optab for
LoongArch LSX/LASX instructions.
This patch causes the gen-vect-{2,25}.c tests to fail. This is because
Pushed to r15-6445.
在 2024/12/18 下午3:45, Jiahao Xu 写道:
We can't vectorize the code into instructions like vslti.w that compare
with immediate_operand, because we miss immediate_operand support for
integer comparisons.
gcc/ChangeLog:
* config/loongarch/lasx.md (vec_cmp): Remove.
Pushed to r15-6432.
在 2024/12/17 上午10:41, Jiahao Xu 写道:
The hook changes the allocno class to either FP_REGS or GR_REGS depending on
the mode of the register. This results in better register allocation overall,
fewer spills and reduced codesize - particularly in SPEC2017 lbm.
gcc/ChangeLog:
在 2024/12/16 下午9:19, Xi Ruoyao 写道:
A generic CRC optimization pass has been implemented in r15-5850. But
without target-specific code, it'll only optimize the CRC loop to a
table lookup. With LoongArch-specific code we can do it better: for
64-bit LoongArch and the IEEE 802.3 polynomial or th
在 2024/12/17 下午12:30, Xi Ruoyao 写道:
On Tue, 2024-12-17 at 11:27 +0800, Lulu Cheng wrote:
在 2024/12/16 下午9:20, Xi Ruoyao 写道:
/* snip */
+;; For HImode it's a little complicated...
+(define_expand "rbithi"
I didn't find rtithi's template description. Are there any tes
在 2024/12/16 下午9:20, Xi Ruoyao 写道:
/* snip */
+;; For HImode it's a little complicated...
+(define_expand "rbithi"
I didn't find rtithi's template description. Are there any test cases ?
+ [(match_operand:HI 0 "register_operand")
+ (match_operand:HI 1 "register_operand")]
+ ""
+ {
+r
Pushed to r15-5819..
在 2024/11/28 上午9:26, Jinyang He 写道:
For {xv,v}{srl,sll,sra}, the constraint `vector_same_uimm6` cause overflow
in when emit {w,h,b}. Since the number of bits shifted is the remainder of
the register value, it is actually unnecessary to constrain the range.
Simply mask the sh
Pushed to r15-5818.
在 2024/11/26 下午4:06, Lulu Cheng 写道:
Add '-fdump-tree-optimized' to this testcases.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/lasx-andn-iorn.c:
Add '-fdump-tree-optimized'.
* gcc.target/loongarch/lsx-andn-iorn.c:
Pushed to r15-5817.
在 2024/11/26 下午4:06, Lulu Cheng 写道:
In r15-5327, change the default language version for C compilation from
-std=gnu17 to -std=gnu23.
ISO C99 and C11 allow ceil, floor, round and trunc, and their float and
long double variants, to raise the “inexact” exception,
but ISO/IEC
在 2024/11/28 上午9:26, Jinyang He 写道:
For {xv,v}{srl,sll,sra}, the constraint `vector_same_uimm6` cause overflow
in when emit {w,h,b}. Since the number of bits shifted is the remainder of
the register value, it is actually unnecessary to constrain the range.
Simply mask the shift number with the
在 2024/11/27 下午3:10, Xi Ruoyao 写道:
On Wed, 2024-11-27 at 14:24 +0800, Lulu Cheng wrote:
在 2024/11/27 下午12:06, Xi Ruoyao 写道:
On Wed, 2024-11-27 at 11:58 +0800, Lulu Cheng wrote:
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-shift-sameimm-vec.c
@@ -0,0 +1,72
在 2024/11/27 下午12:06, Xi Ruoyao 写道:
On Wed, 2024-11-27 at 11:58 +0800, Lulu Cheng wrote:
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-shift-sameimm-vec.c
@@ -0,0 +1,72 @@
+/* Test shift bits overflow in vector */
+/* { dg-do compile } */
+/* { dg-options "-mlas
在 2024/11/27 上午10:14, Xi Ruoyao 写道:
On Tue, 2024-11-26 at 18:37 +0800, Jinyang He wrote:
For {xv,v}{srl,sll,sra}, the constraint `vector_same_uimm6` cause overflow
in when emit {w,h,b}. Since the number of bits shifted is the remainder of
the register value, it is actually unnecessary to const
In r15-5327, change the default language version for C compilation from
-std=gnu17 to -std=gnu23.
ISO C99 and C11 allow ceil, floor, round and trunc, and their float and
long double variants, to raise the “inexact” exception,
but ISO/IEC TS 18661-1:2014, the C bindings to IEEE 754-2008, as
integra
Add '-fdump-tree-optimized' to this testcases.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/lasx-andn-iorn.c:
Add '-fdump-tree-optimized'.
* gcc.target/loongarch/lsx-andn-iorn.c:
Likewise.
---
gcc/testsuite/gcc.target/loongarch/lasx-andn-iorn.c | 2 +-
gcc/test
gcc/ChangeLog:
* config/g.opt.urls: Regenerate.
* config/i386/nto.opt.urls: Regenerate.
* config/riscv/riscv.opt.urls: Regenerate.
* config/rx/rx.opt.urls: Regenerate.
* config/sol2.opt.urls: Regenerate.
---
gcc/config/g.opt.urls | 2 +-
gcc/confi
Pushed to r15-5583 and r15-5584.
在 2024/11/2 上午10:48, Lulu Cheng 写道:
Lulu Cheng (2):
LoongArch: Remove redundant code.
LoongArch: Modify the document to remove options that don't exist.
gcc/config/loongarch/loongarch-builtins.cc | 102 -
gcc/config/loon
Pushed to r15-5581 and r14-10961.
在 2024/11/2 下午3:37, Lulu Cheng 写道:
[x]vldi.{b/h/w/d} is not implemented in LoongArch.
Use the macro [x]vrepli.{b/h/w/d} to replace.
gcc/ChangeLog:
* config/loongarch/lasx.md: Fixed.
* config/loongarch/lsx.md: Fixed.
---
gcc/config/loongarch
Pushed to r14-10960.
在 2024/11/22 上午9:52, Lulu Cheng 写道:
Pushed to r15-5580.
We searched in the multimedia package and found no cases of using
__builtin_lsx_vorn_v or __builtin_lasx_xvorn_v,
so the interface type has been modified in the form of a bugfix.
Thanks!
在 2024/10/31 下午11:58
Pushed to r15-5580.
We searched in the multimedia package and found no cases of using
__builtin_lsx_vorn_v or __builtin_lasx_xvorn_v,
so the interface type has been modified in the form of a bugfix.
Thanks!
在 2024/10/31 下午11:58, Xi Ruoyao 写道:
Align them with other vector bitwise builtins.
[x]vldi.{b/h/w/d} is not implemented in LoongArch.
Use the macro [x]vrepli.{b/h/w/d} to replace.
gcc/ChangeLog:
* config/loongarch/lasx.md: Fixed.
* config/loongarch/lsx.md: Fixed.
---
gcc/config/loongarch/lasx.md | 2 +-
gcc/config/loongarch/lsx.md | 2 +-
2 files changed, 2 in
在 2024/11/2 上午1:10, Xi Ruoyao 写道:
On Thu, 2024-10-31 at 23:58 +0800, Xi Ruoyao wrote:
/* snip */
---
Now running bootstrap & regtest. Posted early as a context for some
LLVM patch. I'll post the regtest result once it finishes.
Done, no regressions.
The LLVM patch is https://github.com/
gcc/ChangeLog:
* doc/invoke.texi: Remove the non-existent option
'-msmall-data-limit' and add a description of '-G'.
---
gcc/doc/invoke.texi | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index fd6c0c44709..
TARGET_ASM_ALIGNED_{HI,SI,QI}_OP are defined repeatedly and deleted.
gcc/ChangeLog:
* config/loongarch/loongarch-builtins.cc
(loongarch_builtin_vectorized_function): Delete.
(LARCH_GET_BUILTIN): Delete.
* config/loongarch/loongarch-protos.h
(loongarch_built
Lulu Cheng (2):
LoongArch: Remove redundant code.
LoongArch: Modify the document to remove options that don't exist.
gcc/config/loongarch/loongarch-builtins.cc | 102 -
gcc/config/loongarch/loongarch-protos.h| 1 -
gcc/config/loongarch/loongarch.cc
在 2024/11/2 上午1:36, Xi Ruoyao 写道:
Without optimization, GCC does not emit a jump table for the test case.
I'm not sure if the test case has been wrong in the first place or
something has changed in these months...
It was in the r15-4756 that turned -fjump-tables off at O0 optimization.
I wa
Pushed to r15-4588
在 2024/1/27 下午3:09, Yang Yujie 写道:
This patch correspond to the upstream PR:
https://github.com/libffi/libffi/pull/817
libffi/ChangeLog:
* src/loongarch64/ffi.c: Avoid defining floats
in struct call_context if the ABI is soft-float.
---
libffi/src/loongarch
Pushed to r15-4130.
在 2024/7/11 下午7:43, Xi Ruoyao 写道:
This is per the request from the kernel developers. For generating the
ORC unwind info, the objtool program needs to analysis the control flow
of a .o file. If a jump table is used, objtool has to correlate the
jump instruction with the tab
Pushed to r15-2879.
在 2024/8/8 下午2:47, Lulu Cheng 写道:
We support vashr vlshr and vashl. However, in r15-1638 support optimize
x < 0 ? -1 : 0 into (signed) x >> 31 and x < 0 ? 1 : 0 into (unsigned) x >> 31.
To support this optimization, vector ashr lshr and ashl need to be
Pushed to r15-2878.
在 2024/8/8 下午2:47, Lulu Cheng 写道:
Optabs vcond{,u} will be removed for GCC 15. Since regtest shows no
fallout, dropping the expanders, now.
gcc/ChangeLog:
PR target/114189
* config/loongarch/lasx.md (vcondu): Delete.
(vcond): Likewise
Pushed to r15-2877.
在 2024/8/2 上午9:19, Lulu Cheng 写道:
R15-1890 introduced new optabs iorc and andc, and its corresponding
internal functions BIT_{ANDC,IORC}, and if targets defines such optabs
for vector modes. And in r15-2258 the iorc and andc were renamed to
iorn and andn.
So we changed the
We support vashr vlshr and vashl. However, in r15-1638 support optimize
x < 0 ? -1 : 0 into (signed) x >> 31 and x < 0 ? 1 : 0 into (unsigned) x >> 31.
To support this optimization, vector ashr lshr and ashl need to be implemented.
gcc/ChangeLog:
* config/loongarch/loongarch.md (insn): Ad
Optabs vcond{,u} will be removed for GCC 15. Since regtest shows no
fallout, dropping the expanders, now.
gcc/ChangeLog:
PR target/114189
* config/loongarch/lasx.md (vcondu): Delete.
(vcond): Likewise.
* config/loongarch/lsx.md (vcondu): Likewise.
(vcond):
Pushed to r15-2660.
在 2024/7/23 上午10:04, Yang Yujie 写道:
Builds for the LoongArch target fail if the system "awk" is not "gawk".
This patch removes this unnecessary requirement.
Thanks to Jan-Benedict Glaw for finding and reporting
this issue.
Yang Yujie (1):
LoongArch: Remove gawk extensio
R15-1890 introduced new optabs iorc and andc, and its corresponding
internal functions BIT_{ANDC,IORC}, and if targets defines such optabs
for vector modes. And in r15-2258 the iorc and andc were renamed to
iorn and andn.
So we changed the andn and iorn implementation templates to the standard
tem
R15-1890 introduced new optabs iorc and andc, and its corresponding
internal functions BIT_{ANDC,IORC}, and if targets defines such optabs
for vector modes. And in r15-2258 the iorc and andc were renamed to
iorn and andn.
So we changed the andn and iorn implementation templates to the standard
tem
在 2024/7/31 下午6:25, Xi Ruoyao 写道:
On Wed, 2024-07-31 at 16:57 +0800, Lulu Cheng wrote:
在 2024/7/29 下午3:58, Xi Ruoyao 写道:
Per a gcc-help thread we are generating sub-optimal code for
__builtin_bswap{32,64}. To fix it:
- Use a single revb.d instruction for bswapdi2.
- Use a single revb.2w
在 2024/7/29 下午3:58, Xi Ruoyao 写道:
Per a gcc-help thread we are generating sub-optimal code for
__builtin_bswap{32,64}. To fix it:
- Use a single revb.d instruction for bswapdi2.
- Use a single revb.2w instruction for bswapsi2 for TARGET_64BIT,
revb.2h + rotri.w for !TARGET_64BIT.
- Use a s
在 2024/7/29 下午3:59, Xi Ruoyao 写道:
In r15-1207 I was too stupid to realize we just need to relax
ins_zero_bitmask_operand to allow using bstrins for aligning, instead of
adding a new split. And, "> 12" in ins_zero_bitmask_operand also makes
no sense: it rejects bstrins for things like "x & ~4l"
在 2024/7/26 下午8:43, Xi Ruoyao 写道:
We already had "si3_extend" insns and we hoped the fwprop or combine
passes can use them to remove unnecessary sign extensions. But this
does not always work: for cases like x << 1 | y, the compiler
tends to do
(sign_extend:DI
(ior:SI (ashift:SI (
在 2024/7/28 上午3:30, Andrew Pinski 写道:
On Sat, Jul 27, 2024 at 1:55 AM Lulu Cheng wrote:
gcc/ChangeLog:
* config/loongarch/lasx.md (xvandn3): Rename to ...
(andn3): This.
(xvorn3): Rename to ...
(iorn3): This.
* config/loongarch/loongarch
gcc/ChangeLog:
* config/loongarch/lasx.md (xvandn3): Rename to ...
(andn3): This.
(xvorn3): Rename to ...
(iorn3): This.
* config/loongarch/loongarch-builtins.cc (CODE_FOR_lsx_vandn_v):
Defined as the modified name.
(CODE_FOR_lsx_vorn_v): Lik
gcc/ChangeLog:
* config/loongarch/loongarch.md (n): Rename to ...
(n3): This.
---
gcc/config/loongarch/loongarch.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/loongarch/loongarch.md
b/gcc/config/loongarch/loongarch.md
index 459ad30b9bb..4e4ddd5
在 2024/7/27 下午4:41, Xi Ruoyao 写道:
On Sat, 2024-07-27 at 16:36 +0800, Lulu Cheng wrote:
gcc/ChangeLog:
* config/loongarch/loongarch.md (n): Rename to ...
(n3): This.
Ok.
Note that [x]vorn3 and [x]vandn3 should be renamed as well.
Uh, I just forgot about them, I'm modi
gcc/ChangeLog:
* config/loongarch/loongarch.md (n): Rename to ...
(n3): This.
---
gcc/config/loongarch/loongarch.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/loongarch/loongarch.md
b/gcc/config/loongarch/loongarch.md
index 459ad30b9bb..4e4ddd5
Pushed to r15-2167.
在 2024/7/13 下午5:04, Lulu Cheng 写道:
gcc/ChangeLog:
* config/loongarch/loongarch-protos.h
(loongarch_split_128bit_move): Delete.
(loongarch_split_128bit_move_p): Delete.
(loongarch_split_256bit_move): Delete
在 2024/7/11 下午7:45, Xi Ruoyao 写道:
Doing so can avoid loading FP constants from the memory. It also
partially fixes PR 66462 as fclass does not signal on sNaN.
gcc/ChangeLog:
* config/loongarch/loongarch.md (extendsidi2): Add ("=r", "f")
alternative and use movfr2gr.s for it.
gcc/ChangeLog:
* config/loongarch/loongarch-protos.h
(loongarch_split_128bit_move): Delete.
(loongarch_split_128bit_move_p): Delete.
(loongarch_split_256bit_move): Delete.
(loongarch_split_256bit_move_p): Delete.
(loongarch_split_vector_move): Add a
Pushed to r15-1987.
在 2024/7/4 下午5:56, Lulu Cheng 写道:
gcc/ChangeLog:
* config/loongarch/loongarch.cc
(loongarch_split_move): Delete.
(loongarch_hard_regno_mode_ok_uncached): Likewise.
* config/loongarch/loongarch.md
(move_doubleword_fpr): Likewise
Pushed to r15-1986.
在 2024/7/4 下午5:56, Lulu Cheng 写道:
PR target/115752
gcc/ChangeLog:
* config/loongarch/loongarch.cc
(loongarch_hard_regno_mode_ok_uncached): Replace
UNITS_PER_FPVALUE with UNITS_PER_HWFPVALUE.
* config/loongarch/loongarch.h
gcc/ChangeLog:
* config/loongarch/loongarch.cc
(loongarch_split_move): Delete.
(loongarch_hard_regno_mode_ok_uncached): Likewise.
* config/loongarch/loongarch.md
(move_doubleword_fpr): Likewise.
(load_low): Likewise.
(load_high): Likewise.
PR target/115752
gcc/ChangeLog:
* config/loongarch/loongarch.cc
(loongarch_hard_regno_mode_ok_uncached): Replace
UNITS_PER_FPVALUE with UNITS_PER_HWFPVALUE.
* config/loongarch/loongarch.h (UNITS_PER_FPVALUE): Delete.
gcc/testsuite/ChangeLog:
* gcc
Modified and pushed to r15-1765.
在 2024/7/2 上午11:50, Xi Ruoyao 写道:
On Tue, 2024-07-02 at 11:22 +0800, Lulu Cheng wrote:
+static int
+loongarch_insn_cost (rtx_insn *insn, bool speed)
+{
+ rtx x = PATTERN (insn);
+ int cost = pattern_cost (x, speed);
+
+ /* On LA464, prevent movcf2fr and
Pushed to r15-1764.
在 2024/7/2 上午11:21, Lulu Cheng 写道:
After r15-1579, ADD and LD/ST pairs will be merged into LDX/STX.
Cause these two tests to fail. To guarantee that these two tests pass,
add the compilation option '-fno-late-combine-instructions'.
gcc/testsuite
在 2024/7/2 上午11:50, Xi Ruoyao 写道:
On Tue, 2024-07-02 at 11:22 +0800, Lulu Cheng wrote:
+static int
+loongarch_insn_cost (rtx_insn *insn, bool speed)
+{
+ rtx x = PATTERN (insn);
+ int cost = pattern_cost (x, speed);
+
+ /* On LA464, prevent movcf2fr and movfr2gr from merging into movcf2gr
The following two FAIL items have been fixed:
FAIL: gcc.target/loongarch/movcf2gr-via-fr.c scan-assembler
movcf2fr\\t\$f[0-9]+,\$fcc
FAIL: gcc.target/loongarch/movcf2gr-via-fr.c scan-assembler
movfr2gr.s\\t\$r4
gcc/ChangeLog:
* config/loongarch/loongarch.cc (loongarch_i
After r15-1579, ADD and LD/ST pairs will be merged into LDX/STX.
Cause these two tests to fail. To guarantee that these two tests pass,
add the compilation option '-fno-late-combine-instructions'.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/explicit-relocs-extreme-tls-desc.c:
LGTM!
Thanks very much!
在 2024/6/26 下午3:53, Xi Ruoyao 写道:
Ping.
On Sun, 2024-06-16 at 01:50 +0800, Xi Ruoyao wrote:
Consider
c &= 0xfff;
a &= ~0xfff;
b &= ~0xfff;
a |= c;
b |= c;
This can be done with 2 bstrins instructions. But we need to
recognize
it in loongarc
;; We always avoid the shift operation in bstrins__for_ior_mask
-;; if possible, but the result may be sub-optimal when one of the
masks
+;; if possible, but the result may be larger when one of the masks
;; is (1 << N) - 1 and one of the src register is the dest register.
;; For example
I think that's fine.
Thanks!
在 2024/6/16 下午5:11, Xi Ruoyao 写道:
gcc/ChangeLog:
* config/loongarch/loongarch.cc (loongarch_print_operand_reloc):
Dedup and sort the comment describing modifiers.
---
It's a non-functional change thus I've not tested it. Ok for trunk?
gcc/confi
LGTM!
Thanks!
在 2024/6/9 下午9:48, Xi Ruoyao 写道:
A move/bstrins pair is as fast as a (addi.w|lu12i.w|lu32i.d|lu52i.d)/and
pair, and twice fast as a srli/slli pair. When the src reg and the dst
reg happens to be the same, the move instruction can be optimized away.
gcc/ChangeLog:
* conf
在 2024/6/12 上午11:06, Xi Ruoyao 写道:
We were comparing a mode size with word_mode, but word_mode is an enum
value thus this does not really make any sense. (Un)luckily E_DImode
happens to be 8 so this seemed to work, but let's make it correct so it
won't blow up when we add LA32 support or add a
Ok! Thanks!
Lulu Cheng
在 2024/6/3 上午11:01, Kewen Lin 写道:
This is to add new port specific hook implementation
loongarch_c_mode_for_floating_type, remove macro
defines for FLOAT_TYPE_SIZE and DOUBLE_TYPE_SIZE, and
rename LONG_DOUBLE_TYPE_SIZE to LA_LONG_DOUBLE_TYPE_SIZE
as we poison
LGTM!
Thanks!
在 2024/5/22 下午7:24, Xi Ruoyao 写道:
gcc/ChangeLog:
PR target/115169
* config/loongarch/loongarch.cc
(loongarch_expand_conditional_move): Guard REGNO with REG_P.
---
Bootstrapped with --enable-checking=all. Ok for trunk and 14?
gcc/config/loongarch/loong
dme-ov-file#target-presets
has a detailed description of -march.
-march=la64v1.0 will open lsx by default.
On Tue, 2024-04-23 at 11:31 +0800, Lulu Cheng wrote:
Pushed to r14-10083.
在 2024/4/23 上午10:42, Yang Yujie 写道:
These ISA versions are defined as -march= parameters and
are recommended
Pushed to r13-8661.
在 2024/4/29 下午4:09, Lulu Cheng 写道:
From: Yang Yujie
On LoongArch, the regitsters $r4 - $r7 (EH_RETURN_DATA_REGNO) will be saved
and restored in the function prologue and epilogue if the given function calls
__builtin_eh_return. This causes the return value to be
Pushed to r12-10403.
在 2024/4/29 下午4:09, Lulu Cheng 写道:
From: Yang Yujie
On LoongArch, the regitsters $r4 - $r7 (EH_RETURN_DATA_REGNO) will be saved
and restored in the function prologue and epilogue if the given function calls
__builtin_eh_return. This causes the return value to be
From: Yang Yujie
On LoongArch, the regitsters $r4 - $r7 (EH_RETURN_DATA_REGNO) will be saved
and restored in the function prologue and epilogue if the given function calls
__builtin_eh_return. This causes the return value to be overwritten on normal
return paths and breaks a rare case of libgcc'
From: Yang Yujie
On LoongArch, the regitsters $r4 - $r7 (EH_RETURN_DATA_REGNO) will be saved
and restored in the function prologue and epilogue if the given function calls
__builtin_eh_return. This causes the return value to be overwritten on normal
return paths and breaks a rare case of libgcc'
LGTM!
Thanks.
在 2024/4/26 下午9:52, Xi Ruoyao 写道:
Without the constrants, the compiler attempts to use a stack slot as the
target, causing an ICE building the kernel with -Os:
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c:3144:1:
error: could not split insn
(insn:TI 1764 67 1745
(s
在 2024/4/23 上午11:43, Lulu Cheng 写道:
---
htdocs/gcc-14/changes.html | 156 +
1 file changed, 156 insertions(+)
diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html
index 9509487c..f0f0efe0 100644
--- a/htdocs/gcc-14/changes.html
+++ b
---
htdocs/gcc-14/changes.html | 156 +
1 file changed, 156 insertions(+)
diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html
index 9509487c..f0f0efe0 100644
--- a/htdocs/gcc-14/changes.html
+++ b/htdocs/gcc-14/changes.html
@@ -877,6 +877,162 @
Pushed to r14-10083.
在 2024/4/23 上午10:42, Yang Yujie 写道:
These ISA versions are defined as -march= parameters and
are recommended for building binaries for distribution.
Detailed description of these definitions can be found at
https://github.com/loongson/la-toolchain-conventions, which
the Loo
Pushed to r14-10084.
在 2024/4/23 上午10:42, Yang Yujie 写道:
Detailed description of these definitions can be found at
https://github.com/loongson/la-toolchain-conventions, which
the LoongArch GCC port aims to conform to.
gcc/ChangeLog:
* config.gcc: Add loongarch-evolution.o.
* co
在 2024/4/19 下午10:27, Xi Ruoyao 写道:
On Fri, 2024-04-19 at 19:04 +0800, Yang Yujie wrote:
@table @samp
@item native
-This selects the CPU to generate code for at compilation time by determining
-the processor type of the compiling machine. Using @option{-march=native}
-enables all instructio
---
htdocs/gcc-13/changes.html | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html
index 4384c329..15a309d6 100644
--- a/htdocs/gcc-13/changes.html
+++ b/htdocs/gcc-13/changes.html
@@ -625,7 +625,7 @@ You may also want to chec
Pushed to r14-9984.
在 2024/4/9 下午4:19, Lulu Cheng 写道:
gcc/ChangeLog:
* config/loongarch/loongarch.opt.urls: Regenerate.
* config/mn10300/mn10300.opt.urls: Likewise.
* config/msp430/msp430.opt.urls: Likewise.
* config/nds32/nds32-elf.opt.urls: Likewise
Pushed to r14-9866.
在 2024/4/8 下午4:45, Yang Yujie 写道:
This patch fixes the back-end context switching in cases where functions
should be built with their own target contexts instead of the
global one, such as LTO linking and functions with target attributes (TBD).
PR target/113233
gcc/
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