Generate 0x1010 instead of 0x1010000>>12 for lu12i.w. lu32i.d and lu52i.d use
the same processing.
gcc/ChangeLog:
* config/loongarch/lasx.md: Use new loongarch_output_move.
* config/loongarch/loongarch-protos.h (loongarch_output_move):
Change parameters from (rtx, rtx) to (rtx *).
* config/loongarch/loongarch.cc (loongarch_output_move):
Generate final immediate for lu12i.w and lu52i.d.
* config/loongarch/loongarch.md:
Generate final immediate for lu32i.d and lu52i.d.
* config/loongarch/lsx.md: Use new loongarch_output_move.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/imm-load.c: Not generate ">>".
---
Changes in v2:
- Change imm-load test to scan-assembler-not >>.
gcc/config/loongarch/lasx.md | 2 +-
gcc/config/loongarch/loongarch-protos.h | 2 +-
gcc/config/loongarch/loongarch.cc | 14 ++++++--
gcc/config/loongarch/loongarch.md | 34 ++++++++++++-------
gcc/config/loongarch/lsx.md | 2 +-
gcc/testsuite/gcc.target/loongarch/imm-load.c | 1 +
6 files changed, 36 insertions(+), 19 deletions(-)
diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md
index edaf64eeb95..a37c85a25a4 100644
--- a/gcc/config/loongarch/lasx.md
+++ b/gcc/config/loongarch/lasx.md
@@ -723,7 +723,7 @@ (define_insn "mov<mode>_lasx"
[(set (match_operand:LASX 0 "nonimmediate_operand" "=f,f,R,*r,*f")
(match_operand:LASX 1 "move_operand" "fYGYI,R,f,*f,*r"))]
"ISA_HAS_LASX"
- { return loongarch_output_move (operands[0], operands[1]); }
+ { return loongarch_output_move (operands); }
[(set_attr "type" "simd_move,simd_load,simd_store,simd_copy,simd_insert")
(set_attr "mode" "<MODE>")
(set_attr "length" "8,4,4,4,4")])
diff --git a/gcc/config/loongarch/loongarch-protos.h
b/gcc/config/loongarch/loongarch-protos.h
index fb544ad75ca..6601f767dab 100644
--- a/gcc/config/loongarch/loongarch-protos.h
+++ b/gcc/config/loongarch/loongarch-protos.h
@@ -86,7 +86,7 @@ extern void loongarch_split_move (rtx, rtx);
extern bool loongarch_addu16i_imm12_operand_p (HOST_WIDE_INT, machine_mode);
extern void loongarch_split_plus_constant (rtx *, machine_mode);
extern void loongarch_split_vector_move (rtx, rtx);
-extern const char *loongarch_output_move (rtx, rtx);
+extern const char *loongarch_output_move (rtx *);
#ifdef RTX_CODE
extern void loongarch_expand_scc (rtx *);
extern void loongarch_expand_vec_cmp (rtx *);
diff --git a/gcc/config/loongarch/loongarch.cc
b/gcc/config/loongarch/loongarch.cc
index 89237c377e7..f26c1346acc 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -4721,8 +4721,10 @@ loongarch_split_vector_move (rtx dest, rtx src)
that SRC is operand 1 and DEST is operand 0. */
const char *
-loongarch_output_move (rtx dest, rtx src)
+loongarch_output_move (rtx *operands)
{
+ rtx src = operands[1];
+ rtx dest = operands[0];
enum rtx_code dest_code = GET_CODE (dest);
enum rtx_code src_code = GET_CODE (src);
machine_mode mode = GET_MODE (dest);
@@ -4875,13 +4877,19 @@ loongarch_output_move (rtx dest, rtx src)
if (src_code == CONST_INT)
{
if (LU12I_INT (src))
- return "lu12i.w\t%0,%1>>12\t\t\t# %X1";
+ {
+ operands[1] = GEN_INT (INTVAL (operands[1]) >> 12);
+ return "lu12i.w\t%0,%1\t\t\t# %X1";
+ }
else if (IMM12_INT (src))
return "addi.w\t%0,$r0,%1\t\t\t# %X1";
else if (IMM12_INT_UNSIGNED (src))
return "ori\t%0,$r0,%1\t\t\t# %X1";
else if (LU52I_INT (src))
- return "lu52i.d\t%0,$r0,%X1>>52\t\t\t# %1";
+ {
+ operands[1] = GEN_INT (INTVAL (operands[1]) >> 52);
+ return "lu52i.d\t%0,$r0,%X1\t\t\t# %1";
+ }
else
gcc_unreachable ();
}
diff --git a/gcc/config/loongarch/loongarch.md
b/gcc/config/loongarch/loongarch.md
index 3eff4077160..59f45770311 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -2209,7 +2209,7 @@ (define_insn_and_split "*movdi_32bit"
"!TARGET_64BIT
&& (register_operand (operands[0], DImode)
|| reg_or_0_operand (operands[1], DImode))"
- { return loongarch_output_move (operands[0], operands[1]); }
+ { return loongarch_output_move (operands); }
"CONST_INT_P (operands[1]) && REG_P (operands[0]) && GP_REG_P (REGNO
(operands[0]))"
[(const_int 0)]
@@ -2228,7 +2228,9 @@ (define_insn_and_split "*movdi_64bit"
"TARGET_64BIT
&& (register_operand (operands[0], DImode)
|| reg_or_0_operand (operands[1], DImode))"
- { return loongarch_output_move (operands[0], operands[1]); }
+ {
+ return loongarch_output_move (operands);
+ }
"CONST_INT_P (operands[1]) && REG_P (operands[0]) && GP_REG_P (REGNO
(operands[0]))"
[(const_int 0)]
@@ -2315,7 +2317,7 @@ (define_insn_and_split "*movsi_internal"
(match_operand:SI 1 "move_operand" "r,Yd,w,rJ,*r*J,m,*f,*f"))]
"(register_operand (operands[0], SImode)
|| reg_or_0_operand (operands[1], SImode))"
- { return loongarch_output_move (operands[0], operands[1]); }
+ { return loongarch_output_move (operands); }
"CONST_INT_P (operands[1]) && REG_P (operands[0]) && GP_REG_P (REGNO
(operands[0]))"
[(const_int 0)]
@@ -2349,7 +2351,7 @@ (define_insn_and_split "*movhi_internal"
(match_operand:HI 1 "move_operand" "r,Yd,I,m,rJ,k,rJ"))]
"(register_operand (operands[0], HImode)
|| reg_or_0_operand (operands[1], HImode))"
- { return loongarch_output_move (operands[0], operands[1]); }
+ { return loongarch_output_move (operands); }
"CONST_INT_P (operands[1]) && REG_P (operands[0]) && GP_REG_P (REGNO
(operands[0]))"
[(const_int 0)]
@@ -2383,7 +2385,7 @@ (define_insn "*movqi_internal"
(match_operand:QI 1 "move_operand" "r,I,m,rJ,k,rJ"))]
"(register_operand (operands[0], QImode)
|| reg_or_0_operand (operands[1], QImode))"
- { return loongarch_output_move (operands[0], operands[1]); }
+ { return loongarch_output_move (operands); }
[(set_attr "move_type" "move,const,load,store,load,store")
(set_attr "mode" "QI")])
@@ -2404,7 +2406,7 @@ (define_insn "*movsf_hardfloat"
"TARGET_HARD_FLOAT
&& (register_operand (operands[0], SFmode)
|| reg_or_0_operand (operands[1], SFmode))"
- { return loongarch_output_move (operands[0], operands[1]); }
+ { return loongarch_output_move (operands); }
[(set_attr "move_type"
"fmove,mgtf,fpload,fpstore,fpload,fpstore,store,store,mgtf,mftg,move,load,store")
(set_attr "mode" "SF")])
@@ -2414,7 +2416,7 @@ (define_insn "*movsf_softfloat"
"TARGET_SOFT_FLOAT
&& (register_operand (operands[0], SFmode)
|| reg_or_0_operand (operands[1], SFmode))"
- { return loongarch_output_move (operands[0], operands[1]); }
+ { return loongarch_output_move (operands); }
[(set_attr "move_type" "move,load,store")
(set_attr "mode" "SF")])
@@ -2435,7 +2437,7 @@ (define_insn "*movdf_hardfloat"
"TARGET_DOUBLE_FLOAT
&& (register_operand (operands[0], DFmode)
|| reg_or_0_operand (operands[1], DFmode))"
- { return loongarch_output_move (operands[0], operands[1]); }
+ { return loongarch_output_move (operands); }
[(set_attr "move_type"
"fmove,mgtf,fpload,fpstore,fpload,fpstore,store,store,mgtf,mftg,move,load,store")
(set_attr "mode" "DF")])
@@ -2446,7 +2448,7 @@ (define_insn "*movdf_softfloat"
&& TARGET_64BIT
&& (register_operand (operands[0], DFmode)
|| reg_or_0_operand (operands[1], DFmode))"
- { return loongarch_output_move (operands[0], operands[1]); }
+ { return loongarch_output_move (operands); }
[(set_attr "move_type" "move,load,store")
(set_attr "mode" "DF")])
@@ -2589,7 +2591,10 @@ (define_insn "lu32i_d"
(subreg:SI (match_operand:DI 1 "register_operand" "0") 0))
(match_operand:DI 2 "const_lu32i_operand" "u")))]
"TARGET_64BIT"
- "lu32i.d\t%0,%X2>>32"
+ {
+ operands[2] = GEN_INT (INTVAL (operands[2]) >> 32);
+ return "lu32i.d\t%0,%X2";
+ }
[(set_attr "type" "arith")
(set_attr "mode" "DI")])
@@ -2600,7 +2605,10 @@ (define_insn "lu52i_d"
(match_operand 2 "lu52i_mask_operand"))
(match_operand 3 "const_lu52i_operand" "v")))]
"TARGET_64BIT"
- "lu52i.d\t%0,%1,%X3>>52"
+ {
+ operands[3] = GEN_INT (INTVAL (operands[3]) >> 52);
+ return "lu52i.d\t%0,%1,%X3";
+ }
[(set_attr "type" "arith")
(set_attr "mode" "DI")])
@@ -4339,9 +4347,9 @@ (define_insn "*join2_load_store<JOIN_MODE:mode>"
{
/* The load destination does not overlap the source. */
gcc_assert (!reg_overlap_mentioned_p (operands[0], operands[1]));
- output_asm_insn (loongarch_output_move (operands[0], operands[1]),
+ output_asm_insn (loongarch_output_move (operands),
operands);
- output_asm_insn (loongarch_output_move (operands[2], operands[3]),
+ output_asm_insn (loongarch_output_move (&operands[2]),
&operands[2]);
return "";
}
diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md
index 516702efcf2..ca0066a21ed 100644
--- a/gcc/config/loongarch/lsx.md
+++ b/gcc/config/loongarch/lsx.md
@@ -597,7 +597,7 @@ (define_insn "mov<mode>_lsx"
[(set (match_operand:LSX 0 "nonimmediate_operand" "=f,f,R,*r,*f,*r")
(match_operand:LSX 1 "move_operand" "fYGYI,R,f,*f,*r,*r"))]
"ISA_HAS_LSX"
-{ return loongarch_output_move (operands[0], operands[1]); }
+{ return loongarch_output_move (operands); }
[(set_attr "type"
"simd_move,simd_load,simd_store,simd_copy,simd_insert,simd_copy")
(set_attr "mode" "<MODE>")])
diff --git a/gcc/testsuite/gcc.target/loongarch/imm-load.c b/gcc/testsuite/gcc.target/loongarch/imm-load.c
index c04ca33996f..33291fe89bd 100644
--- a/gcc/testsuite/gcc.target/loongarch/imm-load.c
+++ b/gcc/testsuite/gcc.target/loongarch/imm-load.c
@@ -1,5 +1,6 @@
/* { dg-do compile } */
/* { dg-options "-mabi=lp64d -O2 -fdump-rtl-split1" } */
+/* { dg-final { scan-assembler-not "test:.*>>.*test" } } */
long int
test (void)
