>
> Move the synchronization of the RTC with the system clock to the instance
> realization.
>
> Reported-by: Frederik Du Toit Lotter
> Signed-off-by: Heinrich Schuchardt
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> hw/rtc/goldfish_rtc.c | 14 +++---
> 1 fil
On Tue, Mar 4, 2025 at 4:23 AM Atish Patra wrote:
>
> This series adds a fix for KVM PMU code and improves the pmu selftest
> by allowing generating precise number of interrupts. It also provided
> another additional option to the overflow test that allows user to
> generate custom number of LCOFI
On Tue, Jan 14, 2025 at 9:41 PM Milan Djokic wrote:
>
> From: Slavisa Petrovic
>
> This patch introduces initial support for running RISC-V as a Xen guest.
> It provides the necessary infrastructure and stubs for Xen-specific
> operations. Key changes include:
>
> - Modifications to the RISC-V ke
Hi Palmer,
On Wed, Jun 19, 2024 at 9:11 PM Clément Léger wrote:
>
> Since commit e87412e621f1 ("integrate Zaamo and Zalrsc text (#1304)"),
> the A extension has been described as a set of instructions provided by
> Zaamo and Zalrsc. Add these two extensions.
>
> This series is based on the Zc one
On Wed, Jun 19, 2024 at 9:11 PM Clément Léger wrote:
>
> The KVM RISC-V allows Zaamo/Zalrsc extensions for Guest/VM so add these
> extensions to get-reg-list test.
>
> Signed-off-by: Clément Léger
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> tools/testing/selfte
On Wed, Jun 19, 2024 at 9:11 PM Clément Léger wrote:
>
> Extend the KVM ISA extension ONE_REG interface to allow KVM user space
> to detect and enable Zaamo/Zalrsc extensions for Guest/VM.
>
> Signed-off-by: Clément Léger
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
>
ing the senvcfg CSR within the guest, so that extension
> cannot be hidden from the guest without intercepting writes to the CSR.
>
> Signed-off-by: Samuel Holland
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
>
> Changes in v5:
> - Do not allow Smnpm to be disabled, as
On Thu, Aug 8, 2024 at 1:51 PM Yong-Xuan Wang wrote:
>
> In the section "4.7 Precise effects on interrupt-pending bits"
> of the RISC-V AIA specification defines that:
>
> If the source mode is Level1 or Level0 and the interrupt domain
> is configured in MSI delivery mode (domaincfg.DM = 1):
> The
n
For KVM RISC-V:
Acked-by: Anup Patel
Regards,
Anup
> ---
> arch/riscv/kvm/mmu.c | 11 ---
> 1 file changed, 4 insertions(+), 7 deletions(-)
>
> diff --git a/arch/riscv/kvm/mmu.c b/arch/riscv/kvm/mmu.c
> index 806f68e70642..f73d6a79a78c 100644
> --- a/arch/riscv
ed
> outside of mmu_lock is ok (not great, but safe), but marking pages _dirty_
> outside of mmu_lock can make filesystems unhappy.
>
> Signed-off-by: Sean Christopherson
For KVM RISC-V:
Acked-by: Anup Patel
Regards,
Anup
> ---
> arch/riscv/kvm/mmu.c | 4 ++--
> 1 file chan
fix, this paves the way for converting
> RISC-V to use kvm_release_faultin_page().
>
> Signed-off-by: Sean Christopherson
For KVM RISC-V:
Acked-by: Anup Patel
Regards,
Anup
> ---
> arch/riscv/kvm/mmu.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> dif
On Fri, Jul 26, 2024 at 2:19 PM Yong-Xuan Wang wrote:
>
> Fix compile error introduced by commit d27c34a73514 ("KVM: riscv:
> selftests: Add some Zc* extensions to get-reg-list test"). These
> 4 lines should be end with ";".
>
> Fixes: d27c34a73514 ("KVM: riscv: selftests: Add some Zc* extensions
On Fri, May 17, 2024 at 8:23 PM Clément Léger wrote:
>
> The KVM RISC-V allows Zimop extension for Guest/VM so add this
> extension to get-reg-list test.
>
> Signed-off-by: Clément Léger
LGTM.
Reviewed-by: Anup Patel
Acked-by: Anup Patel
Regards,
Anup
> ---
> tools/
On Fri, May 17, 2024 at 8:23 PM Clément Léger wrote:
>
> Extend the KVM ISA extension ONE_REG interface to allow KVM user space
> to detect and enable Zimop extension for Guest/VM.
>
> Signed-off-by: Clément Léger
LGTM.
Reviewed-by: Anup Patel
Acked-by: Anup Patel
Hi Palmer,
On Mon, Apr 22, 2024 at 3:29 PM Anup Patel wrote:
>
> On Sat, Apr 20, 2024 at 5:17 AM Atish Patra wrote:
> >
> > This series implements SBI PMU improvements done in SBI v2.0[1] i.e. PMU
> > snapshot
> > and fw_read_hi() functions.
> >
> >
On Sat, Apr 20, 2024 at 5:17 AM Atish Patra wrote:
>
> This series implements SBI PMU improvements done in SBI v2.0[1] i.e. PMU
> snapshot
> and fw_read_hi() functions.
>
> SBI v2.0 introduced PMU snapshot feature which allows the SBI implementation
> to provide counter information (i.e. values/o
ents or all ISA extensions.
>
> The commandline option allows user to disable any set of tests if
> they want to.
>
> Suggested-by: Andrew Jones
> Signed-off-by: Atish Patra
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> .../selftests/kvm/riscv/sbi_pmu_test.c
e to worry about the conversions.
>
> Replace the current usages as well with new helpers.
>
> Reviewed-by: Andrew Jones
> Signed-off-by: Atish Patra
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> tools/testing/selftests/kvm/include/riscv/processor.h | 10 ++
On Sat, Apr 20, 2024 at 5:18 AM Atish Patra wrote:
>
> The SBI definitions will continue to grow. Move the sbi related
> definitions to its own header file from processor.h
>
> Suggested-by: Andrew Jones
> Reviewed-by: Andrew Jones
> Signed-off-by: Atish Patra
LGTM.
Re
On Sat, Apr 20, 2024 at 5:18 AM Atish Patra wrote:
>
> Rename the function to indicate that it is meant for firmware
> counter read. While at it, add a range sanity check for it as
> well.
>
> Reviewed-by: Andrew Jones
> Signed-off-by: Atish Patra
LGTM.
Reviewed-by: Anup
d-off-by: Atish Patra
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> arch/riscv/kvm/vcpu_pmu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c
> index 86391a5061dd..cee1b9ca4ec4 100644
&g
Hi Palmer,
On Thu, Apr 18, 2024 at 6:13 PM Clément Léger wrote:
>
> Add support for (yet again) more RVA23U64 missing extensions. Add
> support for Zcmop, Zca, Zcf, Zcd and Zcb extensions isa string parsing,
> hwprobe and kvm support. Zce, Zcmt and Zcmp extensions have been left
> out since they
On Thu, Apr 18, 2024 at 6:14 PM Clément Léger wrote:
>
> The KVM RISC-V allows Zcmop extension for Guest/VM so add this
> extension to get-reg-list test.
>
> Signed-off-by: Clément Léger
LGTM.
Reviewed-by: Anup Patel
Acked-by: Anup Patel
Thanks,
Anup
> ---
> tools/
On Thu, Apr 18, 2024 at 6:14 PM Clément Léger wrote:
>
> Extend the KVM ISA extension ONE_REG interface to allow KVM user space
> to detect and enable Zcmop extension for Guest/VM.
>
> Signed-off-by: Clément Léger
LGTM.
Reviewed-by: Anup Patel
Acked-by: Anup Patel
On Thu, Apr 18, 2024 at 6:14 PM Clément Léger wrote:
>
> The KVM RISC-V allows Zca, Zcf, Zcd and Zcb extensions for Guest/VM so
> add these extensions to get-reg-list test.
>
> Signed-off-by: Clément Léger
LGTM.
Reviewed-by: Anup Patel
Acked-by: Anup Patel
Thanks,
Anup
On Thu, Apr 18, 2024 at 6:14 PM Clément Léger wrote:
>
> Extend the KVM ISA extension ONE_REG interface to allow KVM user space
> to detect and enable Zca, Zcf, Zcd and Zcb extensions for Guest/VM.
>
> Signed-off-by: Clément Léger
LGTM.
Reviewed-by: Anup Patel
Acked-by: Anup
e generic KVM code that dispatches to kvm_set_spte_gfn(), as
> well as all the architecture specific implementations.
>
> Signed-off-by: Paolo Bonzini
For KVM RISC-V:
Acked-by: Anup Patel
Regards,
Anup
> ---
> arch/arm64/kvm/mmu.c | 34 -
e generic KVM code that dispatches to kvm_set_spte_gfn(), as
> well as all the architecture specific implementations.
>
> Signed-off-by: Paolo Bonzini
For KVM RISC-V:
Acked-by: Anup Patel
Regards,
Anup
> ---
> arch/arm64/kvm/mmu.c | 34 -
On Sun, Apr 7, 2024 at 8:11 AM Haibo Xu wrote:
>
> On Tue, Apr 2, 2024 at 10:12 PM Andrew Jones wrote:
> >
> > On Mon, Apr 01, 2024 at 04:20:18PM +0800, Haibo Xu wrote:
> > > This is the first patch to enable the base extension selftest
> > > for the SBI implementation in KVM. Test for other exte
On Thu, Mar 7, 2024 at 1:49 PM Colin Ian King wrote:
>
> There are spelling mistakes in __GUEST_ASSERT messages. Fix them.
>
> Signed-off-by: Colin Ian King
Queued this patch for Linux-6.9 fixes.
Thanks,
Anup
> ---
> tools/testing/selftests/kvm/aarch64/arch_timer.c | 2 +-
> tools/testing/sel
On Fri, Mar 8, 2024 at 3:47 AM Oliver Upton wrote:
>
> Thanks for the fix Colin. Paolo/Anup, up to you how you want to play it,
> I see the 6.9 PR is already out for riscv.
>
> Acked-by: Oliver Upton
I can take this as a Linux-6.9-rcX fix if everyone is okay with it.
Regards,
Anup
>
> On Thu,
Few fixes for RISC-V APLIC discovered during Linux AIA patch reviews.
These patches can also be found in the apatel_aplic_fixes_v1 branch at:
https://github.com/avpatel/qemu.git
Anup Patel (2):
hw/intc/riscv_aplic: Fix setipnum_le write emulation for APLIC
MSI-mode
hw/intc/riscv_aplic
lue = (incoming wire value) XOR (source is inverted)"
Update the riscv_aplic_read_input_word() implementation to match the above.
Fixes: e8f79343cfc8 ("hw/intc: Add RISC-V AIA APLIC device emulation")
Signed-off-by: Anup Patel
---
hw/intc/riscv_aplic.c | 17 +++--
1 fil
d RISC-V AIA APLIC device emulation")
Signed-off-by: Anup Patel
---
hw/intc/riscv_aplic.c | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index e98e258deb..775bb96164 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw
On Tue, Mar 5, 2024 at 1:54 AM Björn Töpel wrote:
>
> Conor Dooley writes:
>
> > On Thu, Feb 29, 2024 at 01:10:56PM +0100, Alexandre Ghiti wrote:
> >> For now, we use stop_machine() to patch the text and when we use IPIs for
> >> remote icache flushes (which is emitted in patch_text_nosync()), th
On Wed, Feb 14, 2024 at 6:08 PM Anup Patel wrote:
>
> This series extends the KVM RISC-V ONE_REG interface to report few more
> ISA extensions namely: Ztso and Zacas. These extensions are already
> supported by the HWPROBE interface in Linux-6.8 kernel.
>
> To test these patches
ISA extensions to detect if a platform supports that. Thus,
> this test will fail on platform with virtualization but doesn't
> support overflow on these two events.
>
> Signed-off-by: Atish Patra
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> tools/testi
On Thu, Feb 29, 2024 at 6:32 AM Atish Patra wrote:
>
> Verify PMU snapshot functionality by setting up the shared memory
> correctly and reading the counter values from the shared memory
> instead of the CSR.
>
> Signed-off-by: Atish Patra
LGTM.
Reviewed-by: Anup Pat
at the time of merging.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> tools/testing/selftests/kvm/Makefile| 1 +
> tools/testing/selftests/kvm/riscv/sbi_pmu.c | 340
> 2 files changed, 341 insertions(+)
> create mode 100644 tools/testing/selftest
On Thu, Feb 29, 2024 at 6:32 AM Atish Patra wrote:
>
> The SBI PMU extension definition is required for upcoming SBI PMU
> selftests.
>
> Signed-off-by: Atish Patra
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> .../selftests/kvm/include/ris
On Thu, Feb 29, 2024 at 6:32 AM Atish Patra wrote:
>
> The KVM RISC-V allows Sscofpmf extension for Guest/VM so let us
> add this extension to get-reg-list test.
>
> Signed-off-by: Atish Patra
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> tools/testing/selfte
On Thu, Feb 29, 2024 at 8:42 PM Andrew Jones wrote:
>
> On Thu, Feb 29, 2024 at 07:07:43PM +0530, Himanshu Chauhan wrote:
> > All the CPUs may or may not implement the debug triggers (sdtrig)
> > extension. The presence of it should be dynamically detectable.
> > This patch exports the debug trigg
On Wed, Feb 21, 2024 at 2:07 PM Atish Patra wrote:
>
> On 2/20/24 18:13, Haibo Xu wrote:
> > On Wed, Feb 21, 2024 at 7:03 AM Atish Patra wrote:
> >>
> >> On Mon, Jan 22, 2024 at 1:48 AM Haibo Xu wrote:
> >>>
> >>> Move vcpu_has_ext to the processor.c and rename it to __vcpu_has_ext
> >>> so that
gt; Signed-off-by: Palmer Dabbelt
LTGM.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> drivers/tty/hvc/Kconfig | 8 +---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/tty/hvc/Kconfig b/drivers/tty/hvc/Kconfig
> index 6e05c5c7bca1..c2a4e88b328
The KVM RISC-V allows Zacas extension for Guest/VM so let us
add this extension to get-reg-list test.
Signed-off-by: Anup Patel
---
tools/testing/selftests/kvm/riscv/get-reg-list.c | 4
1 file changed, 4 insertions(+)
diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c
b/tools
We extend the KVM ISA extension ONE_REG interface to allow KVM
user space to detect and enable Zacas extension for Guest/VM.
Signed-off-by: Anup Patel
---
arch/riscv/include/uapi/asm/kvm.h | 1 +
arch/riscv/kvm/vcpu_onereg.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/arch/riscv
The KVM RISC-V allows Ztso extension for Guest/VM so let us
add this extension to get-reg-list test.
Signed-off-by: Anup Patel
---
tools/testing/selftests/kvm/riscv/get-reg-list.c | 4
1 file changed, 4 insertions(+)
diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c
b/tools
We extend the KVM ISA extension ONE_REG interface to allow KVM
user space to detect and enable Ztso extension for Guest/VM.
Signed-off-by: Anup Patel
---
arch/riscv/include/uapi/asm/kvm.h | 1 +
arch/riscv/kvm/vcpu_onereg.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/arch/riscv
rypto extensions for Guest/VM")
Signed-off-by: Anup Patel
---
arch/riscv/kvm/vcpu_insn.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/riscv/kvm/vcpu_insn.c b/arch/riscv/kvm/vcpu_insn.c
index 7a6abed41bc1..ee7215f4071f 100644
--- a/arch/riscv/kvm/vcpu_insn.c
+++ b/arch
/avpatel/kvmtool.git
These patches can also be found in the riscv_kvm_more_exts_round2_v1
branch at: https://github.com/avpatel/linux.git
Anup Patel (5):
RISC-V: KVM: Forward SEED CSR access to user space
RISC-V: KVM: Allow Ztso extension for Guest/VM
KVM: riscv: selftests: Add Ztso extension
On Mon, Jan 22, 2024 at 3:15 PM Haibo Xu wrote:
>
> The RISC-V arch_timer selftests is used to validate Sstc timer
> functionality in a guest, which sets up periodic timer interrupts
> and check the basic interrupt status upon its receipt.
>
> This KVM selftests was ported from aarch64 arch_timer
On Mon, Feb 5, 2024 at 9:36 AM Alistair Francis wrote:
>
> On Mon, Jan 22, 2024 at 7:16 PM Andrew Jones wrote:
> >
> > On Mon, Jan 22, 2024 at 03:42:10PM +1000, Alistair Francis wrote:
> > > > > From memory the "debug" property is for the original debug spec:
> > > > > https://github.com/riscv/ri
On Sat, Jan 20, 2024 at 3:29 AM Palmer Dabbelt wrote:
>
> On Fri, 19 Jan 2024 02:09:18 PST (-0800), apa...@ventanamicro.com wrote:
> > On Sat, Jan 13, 2024 at 12:00 AM Palmer Dabbelt wrote:
> >>
> >> On Thu, 11 Jan 2024 06:50:37 PST (-0800),
> >> patchwork-bot+linux-ri...@kernel.org wrote:
> >>
> +static ssize_t hvc_sbi_dbcn_tty_put(uint32_t vtermno, const u8 *buf, size_t
> count)
> {
> return sbi_debug_console_write(buf, count);
> }
>
> -static int hvc_sbi_dbcn_tty_get(uint32_t vtermno, char *buf, int count)
> +static ssize_t hvc_sbi_dbcn_tty_get(uint32_t vtermno, u8 *buf, size_t count)
> {
> return sbi_debug_console_read(buf, count);
> }
> --
> 2.43.0
>
>
Reviewed-by: Anup Patel
Thanks,
Anup
Let us enable SBI based earlycon support in defconfig for both RV32
and RV64 so that "earlycon=sbi" can be used again.
Signed-off-by: Anup Patel
Reviewed-by: Andrew Jones
---
arch/riscv/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/configs/defcon
From: Atish Patra
RISC-V SBI specification supports advanced debug console
support via SBI DBCN extension.
Extend the HVC SBI driver to support it.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Reviewed-by: Andrew Jones
Acked-by: Greg Kroah-Hartman
---
drivers/tty/hvc/Kconfig
We extend the existing RISC-V SBI earlycon support to use the new
RISC-V SBI debug console extension.
Signed-off-by: Anup Patel
Reviewed-by: Andrew Jones
Acked-by: Greg Kroah-Hartman
---
drivers/tty/serial/Kconfig | 2 +-
drivers/tty/serial/earlycon-riscv-sbi.c | 27
Let us provide SBI debug console helper routines which can be
shared by serial/earlycon-riscv-sbi.c and hvc/hvc_riscv_sbi.c.
Signed-off-by: Anup Patel
Reviewed-by: Andrew Jones
---
arch/riscv/include/asm/sbi.h | 5 +++
arch/riscv/kernel/sbi.c | 66
2
The functions sbi_console_putchar() and sbi_console_getchar() are
not defined when CONFIG_RISCV_SBI_V01 is disabled so let us add
stub of these functions to avoid "#ifdef" on user side.
Signed-off-by: Anup Patel
Reviewed-by: Andrew Jones
---
arch/riscv/include/asm/sbi.h | 5 +++
space have to explicitly opt-in for emulating
SBI DBCN.
- Introduced new PATCH5 in this series which adds inline version of
sbi_console_getchar() and sbi_console_putchar() for the case where
CONFIG_RISCV_SBI_V01 is disabled.
Anup Patel (4):
RISC-V: Add stubs for sbi_console_putchar/getcha
On Sat, Jan 13, 2024 at 12:00 AM Palmer Dabbelt wrote:
>
> On Thu, 11 Jan 2024 06:50:37 PST (-0800),
> patchwork-bot+linux-ri...@kernel.org wrote:
> > Hello:
> >
> > This series was applied to riscv/linux.git (for-next)
> > by Palmer Dabbelt :
> >
> > On Fri, 24 Nov 2023 12:39:00 +0530 you wrote:
On Wed, Jan 17, 2024 at 7:54 PM Himanshu Chauhan
wrote:
>
> The debug trigger (sdtrig) capability is controlled using the debug property.
> The sdtrig is an ISA extension and should be treated so. The sdtrig extension
> may or may not be implemented in a system. Therefore, it must raise an illegal
On Thu, Jan 18, 2024 at 11:10 PM Sean Christopherson wrote:
>
> On Thu, Jan 18, 2024, Anup Patel wrote:
> > On Thu, Jan 4, 2024 at 6:07 PM Andrew Jones wrote:
> > >
> > > KVM requires EVENTFD, which is selected by HAVE_KVM. Other KVM
> > > supporting archi
On Thu, Jan 4, 2024 at 6:07 PM Andrew Jones wrote:
>
> KVM requires EVENTFD, which is selected by HAVE_KVM. Other KVM
> supporting architectures select HAVE_KVM and then their KVM
> Kconfigs ensure its there with a depends on HAVE_KVM. Make RISCV
> consistent with that approach which fixes configs
On Tue, Nov 28, 2023 at 8:24 PM Anup Patel wrote:
>
> This extends the KVM RISC-V ONE_REG interface to report more ISA extensions
> namely: Zbz, scalar crypto, vector crypto, Zfh[min], Zihintntl, Zvfh[min],
> and Zfa.
>
> This series depends upon the "riscv: report more
On Thu, Jan 4, 2024 at 4:51 PM Andrew Jones wrote:
>
> On Thu, Jan 04, 2024 at 12:07:51PM +0100, Alexandre Ghiti wrote:
> > On 04/01/2024 11:52, Andrew Jones wrote:
> > > This applies to linux-next, but I forgot to append -next to the PATCH
> > > prefix.
> >
> >
> > Shoudn't this go to -fixes inst
On Wed, Dec 20, 2023 at 9:30 PM Andrew Jones wrote:
>
> One frequently touted benefit of virtualization is the ability to
> consolidate machines, increasing resource utilization. It may even be
> desirable to overcommit, at the risk of one or more VCPUs having to wait.
> Hypervisors which have in
Hi Palmer,
On Wed, Dec 20, 2023 at 9:30 PM Andrew Jones wrote:
>
> One frequently touted benefit of virtualization is the ability to
> consolidate machines, increasing resource utilization. It may even be
> desirable to overcommit, at the risk of one or more VCPUs having to wait.
> Hypervisors w
Signed-off-by: Andrew Jones
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> arch/riscv/Kconfig | 19 +++
> arch/riscv/kernel/paravirt.c | 63 ++--
> 2 files changed, 79 insertions(+), 3 deletions(-)
>
> diff --git a/
extension registers. Each SBI extension that uses this type
> > will have its own subtype. There are currently no subtypes defined.
> > The next patch introduces the first one.
> >
> > Reviewed-by: Anup Patel
> > Signed-off-by: Andrew Jones
> > ---
> > arch/r
On Thu, Dec 14, 2023 at 3:46 PM Andrew Jones wrote:
>
> Add SBI STA and its two registers to the get-reg-list test.
>
> Signed-off-by: Andrew Jones
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> .../selftests/kvm/riscv/get-reg-list.c| 43 +++
On Thu, Dec 14, 2023 at 3:46 PM Andrew Jones wrote:
>
> With the introduction of steal-time accounting support for
> RISC-V KVM we can add RISC-V support to the steal_time test.
>
> Signed-off-by: Andrew Jones
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> tools/
ll current extension IDs or base
> extension function IDs though, even though we need one of each,
> because we'd prefer to bring those in as necessary.
>
> Signed-off-by: Andrew Jones
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> .../sel
On Thu, Dec 14, 2023 at 3:46 PM Andrew Jones wrote:
>
> sbi_ecall() isn't ucall specific and its prototype is already in
> processor.h. Move its implementation to processor.c.
>
> Signed-off-by: Andrew Jones
LGTM.
Reviewed-by: Anup Patel ---
> .../selftests/kv
> Signed-off-by: Andrew Jones
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> arch/riscv/kvm/Kconfig| 1 +
> arch/riscv/kvm/vcpu_sbi_sta.c | 96 ++-
> 2 files changed, 95 insertions(+), 2 deletions(-)
>
> diff --git a/arc
userspace must not set the hi register to anything other
> than zero and is allowed to completely neglect saving/restoring it.
>
> Signed-off-by: Andrew Jones
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> arch/riscv/include/asm/kvm_vcpu_sbi.h | 5 +++
> arch/risc
type. There are currently no subtypes defined.
> The next patch introduces the first one.
>
> Signed-off-by: Andrew Jones
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> arch/riscv/include/asm/kvm_vcpu_sbi.h | 4 ++
> arch/riscv/include/uapi/asm/kvm.h | 3 +
(struct kvm_vcpu *vcpu)
> {
> + gpa_t shmem = vcpu->arch.sta.shmem;
> +
> + if (shmem == INVALID_GPA)
> + return;
> }
>
> static int kvm_sbi_sta_steal_time_set_shmem(struct kvm_vcpu *vcpu)
> --
> 2.43.0
>
Apart from the above, it looks good to me.
Reviewed-by: Anup Patel
Regards,
Anup
o by making the request from vcpu-load. The record
> function is just a stub for now and will be filled in with the rest
> of the steal-time support functions in following patches.
>
> Signed-off-by: Andrew Jones
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> arch
On Thu, Dec 14, 2023 at 3:46 PM Andrew Jones wrote:
>
> Add the files and functions needed to support the SBI STA
> (steal-time accounting) extension. In the next patches we'll
> complete the functions to fully enable SBI STA support.
>
> Signed-off-by: Andrew Jones
L
On Thu, Dec 14, 2023 at 3:45 PM Andrew Jones wrote:
>
> When the SBI STA extension exists we can use it to implement
> paravirt steal-time support. Fill in the empty pv-time functions
> with an SBI STA implementation and add the Kconfig knobs allowing
> it to be enabled.
>
> Signed-off-by: Andrew
On Thu, Dec 14, 2023 at 3:45 PM Andrew Jones wrote:
>
> The SBI STA extension enables steal-time accounting. Add the
> definitions it specifies.
>
> Signed-off-by: Andrew Jones
> Reviewed-by: Conor Dooley
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> arch
ions to fully enable steal-time
> support.
>
> Signed-off-by: Andrew Jones
LGTM.
Reviewed-by: Anup Patel
Regards,
Anup
> ---
> .../admin-guide/kernel-parameters.txt | 6 +-
> arch/riscv/include/asm/paravirt.h | 28 +++
> arch/riscv/include/asm/pa
Hi Marc, Hi Oliver,
On Tue, Dec 12, 2023 at 2:52 PM Haibo Xu wrote:
>
> There are intermittent failures occured when stressing the
> arch-timer test in a Qemu VM:
>
> Guest assert failed, vcpu 0; stage; 4; iter: 3
> Test Assertion Failure
>aarch64/arch_timer.c:196: config_iter +
Hi Marc, Hi Oliver,
On Tue, Dec 12, 2023 at 2:49 PM Haibo Xu wrote:
>
> Split the arch-neutral test code out of aarch64/arch_timer.c
> and put them into a common arch_timer.c. This is a preparation
> to share timer test codes in riscv.
>
> Suggested-by: Andrew Jones
> Signed-off-by: Haibo Xu
>
few PPC includes and an s390 declaration as needed, and
> opportunistically include kvm_host.h in trace/events.kvm.h instead of
> relying on the parent to provide the right includes.
>
> Cc: Anish Ghulati
> Cc: Venkatesh Srinivas
> Cc: Andrew Thornton
> Signed-off-by: Sean
not obviously better than having KVM
> react to -EINTR (though it's not obviously worse either).
>
> Signed-off-by: Sean Christopherson
For KVM RISC-V:
Anup Patel
Regards,
Anup
> ---
> arch/arm64/kvm/arm.c | 3 +--
> arch/riscv/kvm/vcpu.c | 2 +-
> arch/x86
ate, as both s390
> and PPC switched to the overwrite behavior without so much as a passing
> mention when EXTRA_CFLAGS was replaced with ccflags-y (commit c73028a02887
> ("s390: change to new flag variable") and commit 4108d9ba9091
> ("powerpc/Makefiles: Change to new f
On Sat, Sep 16, 2023 at 6:01 AM Sean Christopherson wrote:
>
> Move iodev.h, the last remaining holdout in include/kvm, to the standard
> include/linux directory as kvm_iodev.h and delete include/kvm.
>
> Signed-off-by: Sean Christopherson
For KVM RISC-V:
Acked-by: Anup Patel
On Wed, Dec 13, 2023 at 9:22 PM Andrew Jones wrote:
>
> On Tue, Nov 28, 2023 at 08:23:43PM +0530, Anup Patel wrote:
> > Various ISA extension reg_list have common pattern so let us generate
> > these using macros.
> >
> > We define two macro
The KVM RISC-V allows Zvfh[min] extensions for Guest/VM so let us
add these extensions to get-reg-list test.
Signed-off-by: Anup Patel
---
tools/testing/selftests/kvm/riscv/get-reg-list.c | 8
1 file changed, 8 insertions(+)
diff --git a/tools/testing/selftests/kvm/riscv/get-reg
We extend the KVM ISA extension ONE_REG interface to allow KVM
user space to detect and enable Zvfh[min] extensions for Guest/VM.
Signed-off-by: Anup Patel
---
arch/riscv/include/uapi/asm/kvm.h | 2 ++
arch/riscv/kvm/vcpu_onereg.c | 4
2 files changed, 6 insertions(+)
diff --git a
The KVM RISC-V allows Zihintntl extension for Guest/VM so let us
add this extension to get-reg-list test.
Signed-off-by: Anup Patel
---
tools/testing/selftests/kvm/riscv/get-reg-list.c | 4
1 file changed, 4 insertions(+)
diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c
b
We extend the KVM ISA extension ONE_REG interface to allow KVM
user space to detect and enable Zihintntl extension for Guest/VM.
Signed-off-by: Anup Patel
---
arch/riscv/include/uapi/asm/kvm.h | 1 +
arch/riscv/kvm/vcpu_onereg.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/arch
We extend the KVM ISA extension ONE_REG interface to allow KVM
user space to detect and enable Zfh[min] extensions for Guest/VM.
Signed-off-by: Anup Patel
---
arch/riscv/include/uapi/asm/kvm.h | 2 ++
arch/riscv/kvm/vcpu_onereg.c | 4
2 files changed, 6 insertions(+)
diff --git a
The KVM RISC-V allows Zfh[min] extensions for Guest/VM so let us
add these extensions to get-reg-list test.
Signed-off-by: Anup Patel
---
tools/testing/selftests/kvm/riscv/get-reg-list.c | 8
1 file changed, 8 insertions(+)
diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c
The KVM RISC-V allows vector crypto extensions for Guest/VM so let us
add these extensions to get-reg-list test. This includes extensions
Zvbb, Zvbc, Zvkb, Zvkg, Zvkned, Zvknha, Zvknhb, Zvksed, Zvksh, and Zvkt.
Signed-off-by: Anup Patel
---
.../selftests/kvm/riscv/get-reg-list.c| 40
We extend the KVM ISA extension ONE_REG interface to allow KVM
user space to detect and enable vector crypto extensions for
Guest/VM. This includes extensions Zvbb, Zvbc, Zvkb, Zvkg,
Zvkned, Zvknha, Zvknhb, Zvksed, Zvksh, and Zvkt.
Signed-off-by: Anup Patel
---
arch/riscv/include/uapi/asm/kvm.h
We extend the KVM ISA extension ONE_REG interface to allow KVM
user space to detect and enable scalar crypto extensions for
Guest/VM. This includes extensions Zbkb, Zbkc, Zbkx, Zknd, Zkne,
Zknh, Zkr, Zksed, Zksh, and Zkt.
Signed-off-by: Anup Patel
---
arch/riscv/include/uapi/asm/kvm.h | 10
The KVM RISC-V allows Zbc extension for Guest/VM so let us add
this extension to get-reg-list test.
Signed-off-by: Anup Patel
---
tools/testing/selftests/kvm/riscv/get-reg-list.c | 4
1 file changed, 4 insertions(+)
diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c
b/tools
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