Cool. I have a toshiba ac100 with a tegra2. But without graphics I'll
just go on and use drawterm some more time :(
sent from by d-bus
On Tue May 1 18:31:54 EDT 2012, ge...@plan9.bell-labs.com wrote:
> After you pull, you should see a new directory,
> /sys/src/9/teg2. From the _announce file:
>
> This is a preliminary Plan 9 port to the Compulab Trimslice,
> containing a Tegra 2 SoC: a dual-core, (truly) dual-issue 1GHz
> Corte
I've got one of the devices and was going to check some 5[acl] changes
Geoff had merged in, merge in any others from the Go 5[acl],
and (more originally) change the fp emulator to use VFP instead of 7500
instructions, so VFP can be made the default.
And 5i, I suppose.
On 1 May 2012 15:30, wrote:
Fantastic!
On Tuesday, May 1, 2012, wrote:
> After you pull, you should see a new directory,
> /sys/src/9/teg2. From the _announce file:
>
> This is a preliminary Plan 9 port to the Compulab Trimslice,
> containing a Tegra 2 SoC: a dual-core, (truly) dual-issue 1GHz
> Cortex-A9 v7a-architecture
> Great! Graphics support at this point, or is it still in the cpu server stage?
The version on sources, at least, doesn't seem to drive video. There are
pretty good notes on what works and what doesn't in that directory, in
particular words and notes/*.
signature.asc
Description: Message signe
Great! Graphics support at this point, or is it still in the cpu server stage?
john
On Tue, May 1, 2012 at 3:30 PM, wrote:
> After you pull, you should see a new directory,
> /sys/src/9/teg2. From the _announce file:
>
> This is a preliminary Plan 9 port to the Compulab Trimslice,
> containing
After you pull, you should see a new directory,
/sys/src/9/teg2. From the _announce file:
This is a preliminary Plan 9 port to the Compulab Trimslice,
containing a Tegra 2 SoC: a dual-core, (truly) dual-issue 1GHz
Cortex-A9 v7a-architecture ARM system, *and* it comes in a case. VFP
3 floating-po
