On Tue May 1 18:31:54 EDT 2012, ge...@plan9.bell-labs.com wrote: > After you pull, you should see a new directory, > /sys/src/9/teg2. From the _announce file: > > This is a preliminary Plan 9 port to the Compulab Trimslice, > containing a Tegra 2 SoC: a dual-core, (truly) dual-issue 1GHz > Cortex-A9 v7a-architecture ARM system, *and* it comes in a case. VFP > 3 floating-point hardware is present, but 5l doesn't yet generate > those instructions. This is the first multiprocessor ARM port we've > done, and much of the code should be reusable in future ports. There > are still things to be done but it can run both processors and is > believed to have adequate kernel support for VFP 3 floating-point.
excellent. i've just had time to look at the block diagram. is there a jtag connector somewhere? - erik
