IP generation issues tend to be caused by using the wrong Vivado version,
or having stale files laying around from previous versions. Make sure
you're using Vivado 2021.1 with the patch AR76780 installed. If you changed
Vivado versions at some point, you may need to clean the repo to remove any
stale files remaining from previous build attempts. Running "make cleanall"
in the FPGA's top directory is usually sufficient for this.
Also, if you changed anything in the code, that might be relevant as well.
Beyond that, you might need to share more of your logs since there may be
clues in the log further up before this failure.
Thanks,
Wade
On Fri, Jul 19, 2024 at 6:59 AM cyberphox wrote:
>
> Hi All,
>
> I have a clone of UHD 4.7 (Tags: v4.7.0.0) and am trying to build the
> default X310_XG FPGA to check if my setup is OK.
>
> I ran the following commands from /uhd/fpga/usrp3/top/x300
>
> source ./setupenv.sh
> rfnoc_image_builder -y x310_XG_rfnoc_image_core.yml -t X310_XG
>
> After some time I get this error:
>
> BUILDER: Adding IP:
> /home/gssltest/git/uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_fft/axi_fft.xci
> BUILDER: Adding IP:
> /home/gssltest/git/uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xci
> ERROR: [Common 17-107] Cannot change read-only property
> 'generate_synth_checkpoint'.
> Resolution: Please refer to Vivado Properties Reference Guide (UG912) for
> more information on setting properties.
> INFO: [Common 17-206] Exiting Vivado at Fri Jul 19 12:38:28 2024...
>
> Thanks for your help
>
> Marino
>
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