[USRP-users] N210 undetectable
Dear all, We need your help to solve an issue we having recently with one of N210. \ N210 - It works (the fan can be heard and some of the LEDs are on (please see attached pic). Unfortunately, it is 'timed out' when I ping it and it is undetectable (I tried both Windows and Ubuntu). Could you please help me to solve this issue. Thank you in advance. ___ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com
[USRP-users] Re: N210 undetectable
Probably, the device is programmed to use a different IP address than you think it's using. See https://files.ettus.com/manual/page_usrp2.html#usrp2_loadflash_brick on how to use the safe-mode button to temporarily set a fixed IP address. Do that, use the address to correct the programmed IP address to what you expect, and power-cycle the device after. Best regards, Marcus On 08.11.22 11:43, ali.mah...@brunel.ac.uk wrote: Dear all, We need your help to solve an issue we having recently with one of N210. N210 - It works (the fan can be heard and some of the LEDs are on (please see attached pic). Unfortunately, it is 'timed out' when I ping it and it is undetectable (I tried both Windows and Ubuntu). Could you please help me to solve this issue. Thank you in advance. ___ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com ___ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com
[USRP-users] Re: N210 undetectable
Dear Marcus, Thank you for your reply. I thought the NI-USRP Configuration Utility would detect it even though it has a different IP address. ___ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com
[USRP-users] Re: N210 undetectable
Dear Marcus, UPDATE I just did what you told me. it is detected when I use the safe mode. I changed the IP address by using NI-USRP Configuration Utility. Although it tells me that IP has been updated, I have the same issue when I dont use the safe mode. It is only detectable on the safe mode. by the way, it shows me ‘update needed’ on the image status - IN-USRP Configuration Utility. Thank you again ___ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com
[USRP-users] Re: N210 undetectable
On 08/11/2022 06:42, ali.mah...@brunel.ac.uk wrote: Dear Marcus, Thank you for your reply. I thought the NI-USRP Configuration Utility would detect it even though it has a different IP address. Only if it happens to be on the same subnet as the host that is doing the query. I'd take Mr. Mueller's advice ___ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com
[USRP-users] Re: N210 undetectable
To which address and subnet do you configure it in the utility? Best regards, Marcus On 08.11.22 14:39, ali.mah...@brunel.ac.uk wrote: Dear Marcus, UPDATE I just did what you told me. it is detected when I use the safe mode. I changed the IP address by using NI-USRP Configuration Utility. Although it tells me that IP has been updated, I have the same issue when I dont use the safe mode. It is only detectable on the safe mode. by the way, it shows me ‘update needed’ on the image status - IN-USRP Configuration Utility. Thank you again ___ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com ___ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com
[USRP-users] Re: N210 undetectable
it was changed to 192.168.10.3. The utility only allows to change the IP not the subnet. kind regards, Ali ___ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com
[USRP-users] Re: How can we develop two RFNOC block that there is a reg relation between them?
Gain and multiply are pretty simple operations. Perhaps you could put them both in the same block? Then you would not need to share this register between different blocks. Wade On Sun, Nov 6, 2022 at 1:06 PM sp wrote: > I am developing two RFNOC blocks, a gain block, and a multiplier block... > But I need there to be a reg relation between RFNOC blocks... > for example, a multiply_const is calculated in multiply rfnoc block and it > is used to block gain... > when I add the reg in rfnoc block and I define it as input and output > ... > I redefine rfnoc block in this filex300_rfnoc_image_core.v > when I build again, x300_rfnoc_image_core.v will be deleted to the > previous state. How can solve this problem? > > I ask this problem in this link but my problem is not solved yet... > > https://lists.ettus.com/empathy/thread/R7N27SR37EPZKMJLG7K6FR3FKBXOMBNO?hash=R7N27SR37EPZKMJLG7K6FR3FKBXOMBNO#R7N27SR37EPZKMJLG7K6FR3FKBXOMBNO > ___ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-le...@lists.ettus.com > ___ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com
[USRP-users] Re: N210 undetectable
As you might have guessed, I'm not aware at all of the NI-USRP utilities. If they just allow setting an IP address, but not a subnet, that would be pretty … incomplete. If that's the case, please try following the guide I linked you to about setting `ip-addr` and `subnet` fields in the N2xx. Best regards, Marcus On 08.11.22 15:43, ali.mah...@brunel.ac.uk wrote: it was changed to 192.168.10.3. The utility only allows to change the IP not the subnet. kind regards, Ali ___ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com ___ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com
[USRP-users] Custom FPGA image "version" register
I use a modified FPGA image on a few x310s. Is there a convenient mechanism for writing some kind of versioning to a register on the FPGA? The specific problem I’m trying to solve is I have a lot of USRPs, and I would like my application to report when one of the radios it connects to is still on the base image. My application is compatible with both images, but gets better performance with my custom image. I run into the issue where I don’t know when I get degraded performance because somebody else reflashed it, or if there was a regression in the application code itself. ___ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com
[USRP-users] Re: How can I define a global reg variable in Verilog between RFNOC blocks?
Thanks very much, Marcus. Can explain more? I had not any idea how develop your way? On Mon, Nov 7, 2022 at 11:29 PM Marcus Müller wrote: > Hi sp, > > That sounds like a bad idea. How are you planning to synchronize access to > that register? > > Generally, in almost *any* context, avoid global state. That makes things > complicated and > error prone; this is true for python as much as it is for C++, as much as > it is for > digital hardware design (in verilog or any other way); it's even true for > design of > mechanical machine factory floors (if you make each processing step as > independent from > the other as possible, you increase reliability). > > So, I'd recommend you find a different way to exchange information between > two blocks. > Exchanging information is the point of RFNoC, by the way. > > Best regards, > Marcus > > On 31.07.22 17:52, sp wrote: > > How can I define a global reg variable in Verilog between RFNOC blocks? > > I developed two RFNOC blocks: RFNOC block A, and RFNOC block B > > How can define a reg variable that shares between RFNOC blocks in USRP? > > Can anyone guide me? > > > > I study about global reg variable in the Verilog module, see below > link, but I can not > > do it for RFNOC blocks... > > How can implement this mechanism in RFNOC blocks > > > https://www.edaboard.com/threads/how-to-define-global-variable-in-verilog.174172/ > > > > Thanks in advance > > > > ___ > > USRP-users mailing list -- usrp-users@lists.ettus.com > > To unsubscribe send an email to usrp-users-le...@lists.ettus.com > ___ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-le...@lists.ettus.com > ___ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com
[USRP-users] Re: Custom FPGA image "version" register
On 08/11/2022 11:01, ri28...@mit.edu wrote: I use a modified FPGA image on a few x310s. Is there a convenient mechanism for writing some kind of versioning to a register on the FPGA? The specific problem I’m trying to solve is I have a lot of USRPs, and I would like my application to report when one of the radios it connects to is still on the base image. My application is compatible with both images, but gets better performance with my custom image. I run into the issue where I don’t know when I get degraded performance because somebody else reflashed it, or if there was a regression in the application code itself. ___ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com You could take a look at the "uhd_usrp_probe" code -- since it displays the FPGA rev number. ___ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com
[USRP-users] Re: Custom FPGA image "version" register
I found the following line in uhd_usrp_probe that looks like it does what I’m
looking for:
`if (tree->exists(path / "fw_version")) {`
` ss << "FW Version: " << tree->access(path / "fw_version").get()`
` << std::endl;`
` }`
The next question is where does the firmware version get set? I did some poking
around fpga/usrp3/top, but it’s not immediately obvious. Is this set somewhere
in the build scripts? I run the standard Makefile when I build my custom image.
I would like to write something so I can definitely distinguish this FPGA is
running my modified firmware.
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[USRP-users] Re: Custom FPGA image "version" register
On 08/11/2022 12:47, ri28...@mit.edu wrote:
I found the following line in uhd_usrp_probe that looks like it does
what I’m looking for:
|if (tree->exists(path / "fw_version")) {|
|ss << "FW Version: " << tree->access(path /
"fw_version").get()|
|<< std::endl;|
|}|
The next question is where does the firmware version get set? I did
some poking around fpga/usrp3/top, but it’s not immediately obvious.
Is this set somewhere in the build scripts? I run the standard
Makefile when I build my custom image. I would like to write something
so I can definitely distinguish this FPGA is running my modified
firmware.
Did:
find uhd -name "*.cpp" -exec grep -H fw_version '{}' ';'
Which yielded:
hd/host/utils/uhd_usrp_probe.cpp: if (tree->exists(path /
"fw_version")) {
uhd/host/utils/uhd_usrp_probe.cpp: ss << "FW Version: " <<
tree->access(path / "fw_version").get()
uhd/host/lib/usrp/b100/b100_impl.cpp:
_tree->create("/mboards/0/fw_version")
uhd/host/lib/usrp/usrp2/usrp2_impl.cpp:
_tree->create(mb_path / "fw_version")
uhd/host/lib/usrp/usrp2/usrp2_impl.cpp:
.set(_mbc[mb].iface->get_fw_version_string());
uhd/host/lib/usrp/usrp2/usrp2_iface.cpp: const std::string
get_fw_version_string(void) override
uhd/host/lib/usrp/x300/x300_impl.cpp: _tree->create(mb_path
/ "fw_version")
uhd/host/lib/usrp/b200/b200_impl.cpp:
_tree->create("/mboards/0/fw_version")
uhd/host/lib/usrp_clock/octoclock/octoclock_impl.cpp: _proto_ver =
_get_fw_version(oc);
uhd/host/lib/usrp_clock/octoclock/octoclock_impl.cpp:
_tree->create(oc_path / "fw_version")
uhd/host/lib/usrp_clock/octoclock/octoclock_impl.cpp:uint32_t
octoclock_impl::_get_fw_version(const std::string& oc)
So, a little bit further into the weeds
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[USRP-users] Re: Custom FPGA image "version" register
It's actually set in the firmware software code, firmware/usrp3/x300/x300_main.c towards
the end. What the host-side UHD does is ask the firmware running on the X3x0 to reply with
the content of that piece of memory.
How to figure out such things: you see how the code you found access a leaf "fw_version"
in the almighty property tree.
You either get very clever with your debugger, or you're like me and just grep for
fw_version in the uhd/host/ source code for '"fw_version"', find where that property is
created (host/lib/usrp/x300/x300_impl.cpp), then check that source code file for the
values/getters/setters that this property has, and see it is just in the end a value poked
(via `iface->peek32(SR_ADDR(X300_FW_SHMEM_BASE, X300_FW_SHMEM_COMPAT_NUM));`) from the
firmware.
From there, you go into uhd/firmware directory and find that place.
I'd honestly do roughly the same as for that firmware compatibility number, but outside
the firmware, directly in FPGA fabric: you instantiate a settings_reg module in your
verilog/VHDL, pick an address that isn't in use yet, and then query it from the iface with
peek just like the compat version getter does. I'd recommend copying an already
functioning settings_reg instance and modifying the address parameter accordingly :)
Best regards,
Marcus
On 08.11.22 18:47, ri28...@mit.edu wrote:
I found the following line in uhd_usrp_probe that looks like it does what I’m
looking for:
|if (tree->exists(path / "fw_version")) {|
|ss << "FW Version: " << tree->access(path / "fw_version").get()|
|<< std::endl;|
|}|
The next question is where does the firmware version get set? I did some poking around
fpga/usrp3/top, but it’s not immediately obvious. Is this set somewhere in the build
scripts? I run the standard Makefile when I build my custom image. I would like to write
something so I can definitely distinguish this FPGA is running my modified firmware.
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[USRP-users] Re: How can I define a global reg variable in Verilog between RFNOC blocks?
On Mon, Nov 7, 2022 at 6:29 PM Marcus Müller wrote: > Hi sp, > > That sounds like a bad idea. How are you planning to synchronize access to > that register? > > Generally, in almost *any* context, avoid global state. That makes things > complicated and > error prone; this is true for python as much as it is for C++, as much as > it is for > digital hardware design (in verilog or any other way); it's even true for > design of > mechanical machine factory floors (if you make each processing step as > independent from > the other as possible, you increase reliability). > As a point of order, though, reducing redundancy is also an admirable goal. I think the idea of sharing registers between multiple RFNoC blocks is not a bad idea. It's the idea of a single configuration space with fanouts to multiple consumers. In C++, imagine it as a singleton of configuration parameters to be referenced during execution. As a practical example, imagine you have a TDMA system which needs timings defined by which the TX and RX both adhere. Or a modulation/coding scheme which is shared between RX and TX. These are independent blocks with common configuration items. A suggestion to duplicate registers would not be seen as appropriate - there is a singular configuration space with fanout to multiple blocks. >From an FPGA perspective, it is not unheard of that a registerfile may be common amongst numerous individual blocks which make up a system. The suggestion earlier, I believe, was to have a custom input to the block which is the shared configuration space. Now, speaking in terms of RFNoC, I imagine this as an RFNoC block which is the configuration space, and has no flows in or out but only exists in the register space. It has outputs which fanout but no other inputs. Is there a document which describes how to build this type of system with RFNoC? Custom output/input port automatically instantiated with the system? Or does it need to be a custom instantiation after the rest of it has been templated? Thanks, Brian ___ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com
