[U-Boot] [PPC] Internet connection on qemu-ppce500

2018-10-08 Thread vnktux 
Hello guys,

I am running an image of U-boot 2018.09 in qemu 3.0, the goal would be to load 
an OS-9 rom file from tftp.
The problem is that I can't manage to have an Internet connection in U-boot. No 
matter how I run the image I always have Net: "No Ethernet found".

I run qemu 3.0 with the following command:

> qemu-system-ppc -cpu e500v2 -M ppce500 -nographic -kernel ~/u-boot -net nic 
> -net tap,ifname=tap0,script=no

I tried to use different -net options in qemu but the problem is always the 
same.

And from the u-boot source code I have edited the board file qemu-ppce500.c in 
order to have a few ENV variables (since I can't save any env variables from 
the running U-boot in qemu).

> ethact=eTSEC1
> ethprime=eTSEC1
> ethaddr=192.168.10.40
> netmask=255.255.254.0
> serverip=192.168.10.2
> gatewayip=192.168.10.254

The image is compiled using of course: qemu-ppce500_defconfig.

What am I doing wrong? Is it even possible to initialize the Ethernet port?

Thanks in advance,
Vincenzo

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[U-Boot] Include FSP in u-boot.rom

2017-11-07 Thread vnktux 
Hi guys,

I need to generate a u-boot.rom image of exactly 8Mb that include only fsp.bin 
and vga.bin. The reason is because in my company we will use an Intel tool that 
already contain descriptor and intel ME for our platform.
Has been already 1 week that I am struggling to do this, if I specify the build 
command  BUILD_ROM=y u-boot keep asking for descriptor, fsp and me.bin. And 
anyway if I give all the blobs in imput the building doesnt succed and it 
complain that the rom file is bigger than my flash (which is impossible since 
fsp=1.5Mb, vga=400Kb, me=8Mb, and the selected flash size is 16Mb).
Can someone please help me with this?

Best regards,
Vincenzo

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Re: [U-Boot] Include FSP in u-boot.rom

2017-11-08 Thread vnktux 
Hi,

Super it works, thanks!!

One more question, I am still trying to port Broadwell-DE in U-boot as bare 
metal boot-loader. Could you please tell me what are the files that I have to 
port from Coreboot/src/soc/intel/fsp_broadwell_de? And are there any files I 
can re-use from U-Boot/arch/x86/broadwell? (I think that Broadwell and 
Broadwell-DE should share some things).

If you would like to review what I have done so far, I can give you the link of 
my gitlab repo.
Thanks in advance!

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>  Original Message 
> Subject: Re: [U-Boot] Include FSP in u-boot.rom
> Local Time: November 8, 2017 12:16 AM
> UTC Time: November 7, 2017 11:16 PM
> From: bmeng...@gmail.com
> To: vnktux , Simon Glass 
> u-boot@lists.denx.de 
>
> Hi,
>
> On Wed, Nov 8, 2017 at 7:13 AM, Bin Meng bmeng...@gmail.com wrote:
>
>> Hi,
>> On Tue, Nov 7, 2017 at 10:13 PM, vnktux vnk...@protonmail.com wrote:
>>
>>> Hi guys,
>>> I need to generate a u-boot.rom image of exactly 8Mb that include only 
>>> fsp.bin and vga.bin. The reason is because in my company we will use an 
>>> Intel tool that already contain descriptor and intel ME for our platform.
>>> Has been already 1 week that I am struggling to do this, if I specify the 
>>> build command BUILD_ROM=y u-boot keep asking for descriptor, fsp and 
>>> me.bin. And anyway if I give all the blobs in imput the building doesnt 
>>> succed and it complain that the rom file is bigger than my flash (which is 
>>> impossible since fsp=1.5Mb, vga=400Kb, me=8Mb, and the selected flash size 
>>> is 16Mb).
>>> Can someone please help me with this?
>>
>> Don't set BUILD_ROM=y and you should be able to generate a u-boot.rom
>> with FSP and VGA images.
>>
>> Sorry, just woke up.. I wanted to say:
>>
>> Don't set CONFIG_HAVE_INTEL_ME and you should be able to generate a
>> u-boot.rom with FSP and VGA images.
>>
>> Regards,
>> Bin
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[U-Boot] Broadwell-DE porting code review

2017-11-09 Thread vnktux 
Hi guys,

For my graduation project I need to port Broadwell-DE in u-boot, and use it as 
bare-metal bootloader on our platform.
Our platform currently run Coreboot + U-Boot but of course they want to get rid 
of the first one. The final 16Mb rom file is created using a tool from Intel 
that basically combine descriptor + Intel ME, and on the address 0x0080 the 
8Mb BIOS region .
So my u-boot should contain the FSP firmware and vga blob. I started porting 
some files from the coreboot sourcode (src/soc/intel/fsp_broadwell_de), but my 
board doesn't boot.
I am quite stuck right now and I don't know what to do anymore, specially 
because there are some addressed that I don't know what to get, and also the 
fsp_conf.c specifications.
Can any of you guys please do the review of what I have done so far? Nobody in 
my company has knowledge with x86 platforms and if I don't get feedback I can't 
continue working on it. The repository is public and available on this 
link:https://git.drk.sc/WarOfDevil/u-boot.x86_64-broadwell-de
My custom code has been added in the following files/directory:
- config/poseidon_defconfig
- board/prodrive/poseidon
- arch/cpu/broadwell-de
- arch/include/asm/arch-broadwell-de
- arch/x86/dts/poseidon.dts
-arch/x86/dts/microcode/broadwell_de_microcode

Thanks a lot!

Best regards,
Vincenzo Bove

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[U-Boot] Broadwell-DE bare metal

2017-10-03 Thread vnktux 
Hi all,

For my graduation project my company asked to use U-Boot as bare metal 
boot-loader on one of their product. The product in an embedded board with a 
Xeon Broadwell-DE D-1527 Quad Core. The current boot-loader consist of Coreboot 
+ U-Boot, but of course they want to get rid of Coreboot. I have almost no 
experience with U-Boot (Just with ARM processor a little bit) and so far I 
don't even know if it's possible or not to achieve the final goal. What I have 
understood is that I need the following binary blobs to work: fsp.bin, vga.bin, 
descriptor.bin, me.bin, microcode.bin. Is it true? Can somebody point me in the 
right direction because I am a little bit lost?  Plus I don't see many x86 
boards implemented in the source code of U-Boot.

Best regards,
Vincenzo

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Re: [U-Boot] Broadwell-DE bare metal

2017-10-05 Thread vnktux 
Hi Bin,

Thanks a lot for the reply. Is there something I can do to help you? I mean 
that's my graduation project and I will have to work on it either I succed or 
not, and here I have available hardware aswell.

Best regards,
Vincenzo

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>  Original Message 
> Subject: Re: [U-Boot] Broadwell-DE bare metal
> Local Time: 5 October 2017 11:25 AM
> UTC Time: 5 October 2017 09:25
> From: bmeng...@gmail.com
> To: vnktux 
> u-boot@lists.denx.de 
>
> Hi,
>
> On Tue, Oct 3, 2017 at 10:58 PM, vnktux  wrote:
>> Hi all,
>>
>> For my graduation project my company asked to use U-Boot as bare metal 
>> boot-loader on one of their product. The product in an embedded board with a 
>> Xeon Broadwell-DE D-1527 Quad Core. The current boot-loader consist of 
>> Coreboot + U-Boot, but of course they want to get rid of Coreboot. I have 
>> almost no experience with U-Boot (Just with ARM processor a little bit) and 
>> so far I don"t even know if it"s possible or not to achieve the final goal. 
>> What I have understood is that I need the following binary blobs to work: 
>> fsp.bin, vga.bin, descriptor.bin, me.bin, microcode.bin. Is it true? Can 
>> somebody point me in the right direction because I am a little bit lost? 
>> Plus I don"t see many x86 boards implemented in the source code of U-Boot.
>>
>
> So far Broadwell-DE is not supported in U-Boot. However it is on my todo list.
>
> Regards,
> Bin
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Re: [U-Boot] Broadwell-DE bare metal

2017-10-10 Thread vnktux 
Hi Simon,

Thanks for the info. I already have all the necessary blobs from the current 
working implementation with Coreboot + U-Boot: FPS, ME, Microcode, Flash 
Descriptor, VGA Rom.

To start porting I was planning to copy all the files of the board minnowmax 
and rename it with the name of our product. I saw that minnowmax use FSP 1.0 
exactly like Broadwell-DE. I hope that helps.

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>  Original Message 
> Subject: Re: [U-Boot] Broadwell-DE bare metal
> Local Time: October 9, 2017 4:43 PM
> UTC Time: October 9, 2017 2:43 PM
> From: s...@chromium.org
> To: vnktux 
> u-boot@lists.denx.de 
>
> Hi,
>
> On 3 October 2017 at 08:58, vnktux  wrote:
>> Hi all,
>>
>> For my graduation project my company asked to use U-Boot as bare metal 
>> boot-loader on one of their product. The product in an embedded board with a 
>> Xeon Broadwell-DE D-1527 Quad Core. The current boot-loader consist of 
>> Coreboot + U-Boot, but of course they want to get rid of Coreboot. I have 
>> almost no experience with U-Boot (Just with ARM processor a little bit) and 
>> so far I don"t even know if it"s possible or not to achieve the final goal. 
>> What I have understood is that I need the following binary blobs to work: 
>> fsp.bin, vga.bin, descriptor.bin, me.bin, microcode.bin. Is it true? Can 
>> somebody point me in the right direction because I am a little bit lost? 
>> Plus I don"t see many x86 boards implemented in the source code of U-Boot.
>
> The original U-Boot payload support was done with Broadwell-DE (I"m
> not sure which one though). It allows U-Boot to boot from EFI.
>
> For what you want, yes you will need to obtain various binary blobs.
> Hopefully you can get the FSP from Intel, and with that the work
> required in U-Boot is probably not too large. Although I"m sure that
> the FSP API will have changed a little.
>
> Regards,
> Simon
>
>>
>> Best regards,
>> Vincenzo
>>
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[U-Boot] X86 Broadwell-DE override FSP configuration

2018-01-13 Thread vnktux 
Hi all,

I managed to fully boot a bare metal U-Boot on the Intel Camelback Mountain CRB 
(Broadwell-DE).
However I have a small problem, basically U-Boot does not override the FSP UPD 
data when the platform boot.
For prototyping I am using a patched FSP binary I got in the company where I 
work. Now that it boot on the camelback mountain I need it to run on another 
platform (also broadwell-de) that has memory down installed on the motherboard. 
That should be easy, all I have to do is to enable memory down in the 
fsp_config.c file and provide the address of the SPD binary file. I have done 
that, but for some reason it doesn't work. During the booting process the 
platform give an error about the Dimm module not being supported. That make 
sense since the pached FSP binary I am using has memory down disabled. The part 
I don't understand is why U-Boot doesnt override the UPD settings specified in 
my fsp_config.c file.

Below you will find my implementation, can somebody explain me what am I doing 
wrong?

/*
 * Copyright (C) 2017, Vincenzo Bove <
vincenzo.b...@prodrive-technologies.com
>
 *
 * SPDX-License-Identifier: GPL-2.0+
 */

#include 
#include 
#include 

#define CONFIG_FSP_MEMORY_DOWN 1

unsigned int px86a_c0_d0_spd[] = {
  0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x3a, 0x20, 0x32, 0x33, 0x20,
  0x30, 0x30, 0x20, 0x30, 0x63, 0x20, 0x30, 0x33, 0x20, 0x38, 0x35, 0x20,
  
};
unsigned int px86a_c0_d0_spd_len = 2400;

DECLARE_GLOBAL_DATA_PTR;

/**
 * Override the FSP's configuration data.
 * If the device tree does not specify an integer setting, use the default
 * provided by Prodrive BroadwellDE.rom
 */
void update_fsp_configs(struct fsp_config_data *config,
struct fspinit_rtbuf *rt_buf)
{
struct upd_region *fsp_upd = &config->fsp_upd;
const void *blob = gd->fdt_blob;
int node;

/* Initialize runtime buffer for fsp_init() */
rt_buf->common.stack_top = config->common.stack_top - 32;
rt_buf->common.boot_mode = config->common.boot_mode;
rt_buf->common.upd_data = &config->fsp_upd;

node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_BROADWELL_DE_FSP);
if (node < 0) {
debug("%s: Cannot find FSP node\n", __func__);
return;
}

  debug("%s: FSP node found!\n", __func__);

fsp_upd->memEccSupport = fdtdec_get_int(blob, node,
  "fsp,memEccSupport",
   MEM_ECC_SUPPORT_AUTO);

fsp_upd->memDdrMemoryType = fdtdec_get_int(blob, node,
  "fsp,memDdrMemoryType",
  MEM_DDR_MEMORY_TYPE_UDIMM_AND_RDIMM);

  fsp_upd->memRankMultiplication = fdtdec_get_int(blob, node,
  "fsp,memRankMultiplication",
  MEM_RANK_MULTIPLICATION_AUTO);

  fsp_upd->memRankMarginTool = fdtdec_get_int(blob, node,
  "fsp,memRankMarginTool",
  MEM_RANK_MARGIN_TOOL_AUTO);

  fsp_upd->memScrambling = fdtdec_get_int(blob, node,
  "fsp,memScrambling",
  MEM_SCRAMBLING_AUTO);

  fsp_upd->memRefreshMode = fdtdec_get_int(blob, node,
  "fsp,memRefreshMode",
  MEM_REFRESH_MODE_ACC_SELF_REFRESH);

  fsp_upd->memMcOdtOverride = fdtdec_get_int(blob, node,
  "fsp,memMcOdtOverride",
  MEM_MC0DT_OVERRIDE_AUTO);

  fsp_upd->memCAParity = fdtdec_get_int(blob, node,
  "fsp,memCAParity",
  MEM_CA_PARITY_AUTO);

  fsp_upd->memThermalThrottling = fdtdec_get_int(blob, node,
  "fsp,memThermalThrottling",
  MEM_THERMAL_THROTTLING_CLOSEDLOOP);

  fsp_upd->memPowerSavingsMode = fdtdec_get_int(blob, node,
  "fsp,memPowerSavingsMode",
  MEM_POWER_SAVINGS_MODE_AUTO);

  fsp_upd->memElectricalThrottling = fdtdec_get_int(blob, node,
  "fsp,memElectricalThrottling",
  MEM_ELECTRICAL_THROTTLING_DISABLED);

  fsp_upd->memPagePolicy = fdtdec_get_int(blob, node,
  "fsp,memPagePolicy",
  MEM_PAGE_POLICY_AUTO);

  fsp_upd->memSocketInterleaveBelow4G = fdtdec_get_int(blob, node,
  "fsp,memSocketInterleaveBelow4G",
  MEM_SOCKET_INTERLEAVE_BELOW_4G_DISABLED);

  fsp_upd->memChannelInterleave = fdtdec_get_int(blob, node,
  "fsp,memChannelInterleave",
  MEM_CHANNEL_INTERLEAVE_AUTO);

  fsp_upd->memRankInterleave = fdtdec_get_int(blob, node,
  "fsp,memRankInterleave",
  MEM_RANK_INTERLEAVE_AUTO);

if(CONFIG_FSP_MEMORY_DOWN){

//memcpy ((int *)0xfffd, px86a_c0_d0_spd, sizeof (px86a_c0_d0_spd));

fsp_upd->memDownEnable = fdtdec_get_bool(blob, node, 
"fsp,memDownEnable");

fsp_upd->memDownCh0Dimm0Sp

Re: [U-Boot] X86 Broadwell-DE override FSP configuration

2018-01-17 Thread vnktux 
Thank you Bin,

I managed to fully boot Broadwell-DE on platform with memory down enabled :)

Now before submitting the patch I have to solve a small problem.
In either case memory down is enable or not the booting process takes 1 hour 
and 20 minutes. On the output there are no error at all. I tried to 
enable/disable fastboot and  MRC but this didn't solve the problem.

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 Original Message 
On 16 January 2018 2:01 PM, Bin Meng  wrote:

> +ML
>
> Hi Vincenzo,
>
> On Tue, Jan 16, 2018 at 8:21 PM, vnktux vnk...@protonmail.com wrote:
>
>> Hi all,
>> I managed to fully boot a bare metal U-Boot on the Intel Camelback Mountain
>> CRB (Broadwell-DE).
>
> This is great!
>
>> However I have a small problem, basically U-Boot does not override the FSP
>> UPD data when the platform boot.
>
> U-Boot can override the FSP UPD data.
>
>> For prototyping I am using a patched FSP binary I got in the company where I
>> work. Now that it boot on the camelback mountain I need it to run on another
>> platform (also broadwell-de) that has memory down installed on the
>> motherboard. That should be easy, all I have to do is to enable memory down
>> in the fsp_config.c file and provide the address of the SPD binary file. I
>> have done that, but for some reason it doesn't work. During the booting
>> process the platform give an error about the Dimm module not being
>> supported. That make sense since the pached FSP binary I am using has memory
>> down disabled. The part I don't understand is why U-Boot doesnt override the
>> UPD settings specified in my fsp_config.c file.
>> Below you will find my implementation, can somebody explain me what am I
>> doing wrong?
>> https://raw.githubusercontent.com/WarOfDevil/u-boot.x86_64-broadwell-de/master/arch/x86/cpu/broadwell-de/fsp_configs.c
>> https://raw.githubusercontent.com/WarOfDevil/u-boot.x86_64-broadwell-de/master/arch/x86/dts/poseidon.dts
>
> It looks you have commented out the FSP node in the device tree, then
> your fsp_configs.c won't do the UPD override.
>
>> Once I manage to make this work, I can create a patch for U-Boot.
>
> Regards,
> Bin
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[U-Boot] Broadwell-DE booting time

2018-01-18 Thread vnktux 
Hi Bin,

To avoid top-posting I will send another email.
Basically my Broadwell-DE implementation work, on both Camelback mountain CRB 
(DIMM memory) and our custom design product (memory down). I can't submit the 
patch to U-Boot because in both cases the booting process takes 1 hour and 20 
minutes and there are no errors in the log. The platform takes lot of time to 
boot when it reach "DDRIO Initialization".
I have attached the boot log if it may help, and my source-code is available 
here: https://github.com/WarOfDevil/u-boot.x86_64-broadwell-de

Thanks in advance!

Vincenzo

Sent with [ProtonMail](https://protonmail.com) Secure Email.= PEIM FSP v1.0 (_BDX-DE_ v0.0.3.2) =
Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE
Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3
Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A
The 0th FV start address is 0x000FFEB1000, size is 0x0011F000, handle is 0x0
Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38
Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6
Install PPI: DBE23AA9-A345-4B97-85B6-B226F1617389
Loading PEIM at 0x000FFEB8638 EntryPoint=0x000FFEB8CF0
Install PPI: 06E81C58-4AD7-44BC-8390-F10265F72480
Install PPI: 01F34D25-4DE2-23AD-3FF3-36353FF323F1
Loading PEIM at 0x000FFEBB080 EntryPoint=0x000FFEBC6D4
Install PPI: 57B195D1-E14B-40AD-A68F-9806000C436A
Loading PEIM at 0x000FFEBCA2C EntryPoint=0x000FFEBD000
enable all DMI VCx
   :: CPU Type Socket ModelId# 56
   :: CPU stepping # 1
Install PPI: 1E2ACC41-E26A-483D-AFC7-A056C34E087B
Publish PlatformInfoPPI
Loading PEIM at 0x000FFEBE6BC EntryPoint=0x000FFEBEC24
Install PPI: 7AE3CEB7-2EE2-48FA-AA49-3510BC83CABF
ME PEI Platform Policy PPI Installed
Loading PEIM at 0x000FFEBFBEC EntryPoint=0x000FFEC04F8
Force an S5 exit path.
Install PPI: E5EE2066-FAA1-4DFA-924E-B1E3A8EE30E8
Install PPI: EE0EA811-FBD9-4777-B95A-BA4F71101F74
Loading PEIM at 0x000FFEC247C EntryPoint=0x000FFEC33E4
Install PPI: 8C376010-2400-4D7D-B47B-9D851DF3C9D1
ME UMA:  ME UMA PPI Installed
Loading PEIM at 0x000FFEC5064 EntryPoint=0x000FFEC5CD4
[SPS] Waiting for ME firmware init complete
[SPS] WARNING: ME is in recovery mode (cause: 3)
[HECI-0] VID-DID: 8086-8C3A
[HECI-0] MBAR not programmed, using default 0xFEDB
[SPS] Sending ME-BIOS Interface Version request
[HECI-0] Send msg: 80010020
[HECI-0]  Got msg: 80050020
[SPS] SPS ME-BIOS interface version is 1.0
  Feature set is 0x
[SPS] HOB: features 0x00, flow 1, boot mode 0, cores to disable 0
Loading PEIM at 0x000FFEC7B2C EntryPoint=0x000FFEF4044
OVERRIDING TOTAL SYSTEM CONFIGURATION WITH UPD
  upd->MemDdr4Platform = 0x0
  tsc->DDR4Platform = 0x2
Halting the TCO Timer (Watchdog)
FastBoot is not supported on this SKU.
Running on hardware
Revision: 0
BIOSSIM: InitHeap()
BIOSSIM: InitUSBDebug()

BDX (1HA) processor detected

 CPU Stepping  1
 Found
CCMRC Version: 0050

MRC Sync Number: 244071

RC Version: 0200
host = FE191770  (pointer to sysHost structure)
Legacy Serial Debug Enabled

QPI Init starting...


*** QPI Setup Structure ***
PPINrOptIn: 0
Bus   Ratio: 1 1 1 1
IORatio: 1 1 1 1
MMIOL Ratio: 1 1 1 1
LegacyVgaSoc: 0
MmioP2pDis: 0
IsocAzaliaVc1En: 0
DebugPrintLevel: 15
ClusterOnDieEn: 0
IBPECIEn: 1
E2EParityEn: 0
EarlySnoopEn: 1
HomeDirWOSBEn: 1
DegradePrecedence: 0
QpiLinkSpeedMode: 1 (FAST)
QpiLinkSpeed: 6
QpiLinkL0pEn: 1
QpiLinkL1En: 1
QpiLinkL0rEn: 1
QpiLbEn: 0
IioUniphyDisable (per socket):   0  0  0  0
QpiLinkCreditReduce: 2
QpiConfigTxWci: 11
QpiCrcMode: 0
QpiCpuSktHotPlugEn: 0
QpiCpuSktHotPlugTopology: 0
QpiSkuMismatchCheck: 1
QpiPortDisable (per port):  S0:0 0   S1:0 0   S2:0 0   S3:0 0
QpiLinkCreditReduce (per port):  S0:0 0   S1:0 0   S2:0 0   S3:0 0
QpiLinkSpeed (per port):  S0:6 6   S1:6 6   S2:6 6   S3:6 6
QpiProbeType (per port):  S0:0 0   S1:0 0   S2:0 0   S3:0 0
QpiConfigTxWci (per port):  S0:11 11   S1:11 11   S2:11 11   S3:11 11
Rsvd (per port):  S0:0 0   S1:0 0   S2:0 0   S3:0 0


*** Common Setup Structure ***
mmCfgBase: 0x8000
mmCfgSize: 0x1000
mmiolBase: 0x9000
mmiolSize: 0x6C00
mmiohBase: 0x3800-
mmiohSize: 256 GB
numaEn: 1
isocEn: 0
mesegEn: 0
dcaEn: 1


*** Common Var Structure ***
resetRequired: 0
state: 0
numCpus: 0
socketPresentBitMap: 0x01
busIio: 0x00 0x00 0x00 0x00
busUncore: 0x3F 0x00 0x00 0x00
mmCfgBase: 0x8000


;*** Collecting Early System Information - START ***
 CAPID0[5] is set. SKU Detected as DE.
SocketId: 0Physical Chop: 3
SocketId: 0CAPID5: 0x06000B6D
SocketId: 0CAPID4: 0x24080F02
SocketId: 0CAPID3: 0x009B0220
SocketId: 0CAPID2: 0x53B4
SocketId: 0CAPID1: 0x8C83
SocketId: 0CAPID0: 0x00108120
;  SBSP Socket: 0   SKU: 0x05   SubSKU: 0x00   Stepping: 0x01   CAPID4[sbsp]: 
0x24080F02
;  Total Cbos: 08   Cbo List: 0xB6D   Total HA: 01   Total R3Qpi: 00   Total 
QpiAgent: 00

;  TotCpus: 4  C

[U-Boot] [PATCH 1/6] Add Broadwell-DE architecture cpu files

2018-01-26 Thread vnktux 
This patch contain all the cpu files for Broadwell-DE architecture, including 
ACPI and FSP settings.

Signed-off-by: Vincenzo Bove 
---
arch/x86/cpu/broadwell-de/Kconfig|  66 +++
arch/x86/cpu/broadwell-de/Makefile   |  10 ++
arch/x86/cpu/broadwell-de/acpi.c | 234 +
arch/x86/cpu/broadwell-de/broadwell_de.c |  38 
arch/x86/cpu/broadwell-de/cpu.c  |  98 +++
arch/x86/cpu/broadwell-de/fsp_configs.c  | 292 +++
6 files changed, 738 insertions(+)
create mode 100644 arch/x86/cpu/broadwell-de/Kconfig
create mode 100644 arch/x86/cpu/broadwell-de/Makefile
create mode 100644 arch/x86/cpu/broadwell-de/acpi.c
create mode 100644 arch/x86/cpu/broadwell-de/broadwell_de.c
create mode 100644 arch/x86/cpu/broadwell-de/cpu.c
create mode 100644 arch/x86/cpu/broadwell-de/fsp_configs.c

diff --git a/arch/x86/cpu/broadwell-de/Kconfig 
b/arch/x86/cpu/broadwell-de/Kconfig
new file mode 100644
index 00..4e7b72c81c
--- /dev/null
+++ b/arch/x86/cpu/broadwell-de/Kconfig
@@ -0,0 +1,66 @@
+#
+# Copyright (C) 2017, Vincenzo Bove 
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+config INTEL_BROADWELL_DE
+ bool
+ select HAVE_FSP
+ select ARCH_MISC_INIT
+ select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
+ imply HAVE_INTEL_ME
+ imply ENABLE_MRC_CACHE
+ imply AHCI_PCI
+ imply ICH_SPI
+ imply INTEL_ICH6_GPIO
+ imply SCSI
+ imply SPI_FLASH
+ imply SYS_NS16550
+ imply USB
+ imply USB_EHCI_HCD
+ imply USB_XHCI_HCD
+ #imply VIDEO_VESA
+
+if INTEL_BROADWELL_DE
+
+config FSP_ADDR
+ hex
+ default 0xffeb
+
+#config DCACHE_RAM_BASE
+# default 0xfef0
+
+#config DCACHE_RAM_SIZE
+# default 0x4000
+
+config CPU_SPECIFIC_OPTIONS
+ def_bool y
+ select SMM_TSEG
+ #select X86_RAMTEST
+
+config SMM_TSEG_SIZE
+ hex
+ default 0x80
+
+config INTERNAL_UART
+ bool
+ default y
+
+config MAX_CPUS
+ int
+ default 16
+
+config MAX_PIRQ_LINKS
+ int
+ default 4
+
+config IRQ_SLOT_COUNT
+ int
+ default 18
+
+config XIP_ROM_SIZE
+ hex
+ default 0x1
+
+endif
diff --git a/arch/x86/cpu/broadwell-de/Makefile 
b/arch/x86/cpu/broadwell-de/Makefile
new file mode 100644
index 00..0fa427e1bf
--- /dev/null
+++ b/arch/x86/cpu/broadwell-de/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright (C) 2017, Vincenzo Bove 
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += cpu.o
+obj-y += fsp_configs.o
+obj-y += broadwell_de.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o
diff --git a/arch/x86/cpu/broadwell-de/acpi.c b/arch/x86/cpu/broadwell-de/acpi.c
new file mode 100644
index 00..2e005623de
--- /dev/null
+++ b/arch/x86/cpu/broadwell-de/acpi.c
@@ -0,0 +1,234 @@
+/*
+ * Copyright (C) 2017, Vincenzo Bove 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define PM1_STS 0x00
+#define PM1_CNT 0x04
+#define GEN_PMCON1 0xA0
+#define WAK_STS (1 << 15)
+#define PWR_FLR (1 << 1)
+#define  SUS_PWR_FLR (1 << 14)
+
+#define PMC_BASE_ADDRESS 0xfed03000
+#define PMC_BASE_SIZE 0x400
+
+void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
+   void *dsdt)
+{
+ struct acpi_table_header *header = &(fadt->header);
+ u16 pmbase = ACPI_BASE_ADDRESS;
+
+ memset((void *)fadt, 0, sizeof(struct acpi_fadt));
+
+ /*
+ * Reference section 5.2.9 Fixed ACPI Description Table (FADT)
+ * in the ACPI 3.0b specification.
+ */
+
+ /* FADT Header Structure */
+ acpi_fill_header(header, "FACP");
+ header->length = sizeof(struct acpi_fadt);
+ header->revision = 4;
+
+ /* ACPI Pointers */
+ fadt->firmware_ctrl = (u32)facs;
+ fadt->dsdt = (u32)dsdt;
+
+ fadt->preferred_pm_profile = ACPI_PM_MOBILE;
+ fadt->sci_int = 9;
+
+ /* System Management */
+ fadt->smi_cmd = 0;
+ fadt->acpi_enable = 0;
+ fadt->acpi_disable = 0;
+
+ /* Power Control */
+ fadt->s4bios_req = 0;
+ fadt->pstate_cnt = 0;
+
+ /* Control Registers - Base Address */
+ fadt->pm1a_evt_blk = pmbase + 0x00; //PM1_STS
+ fadt->pm1b_evt_blk = 0x0;
+ fadt->pm1a_cnt_blk = pmbase + 0x04; //PM1_CNT
+ fadt->pm1b_cnt_blk = 0x0;
+ fadt->pm2_cnt_blk = pmbase + 0x50; //PM2A_CNT_BLK
+ fadt->pm_tmr_blk = pmbase + 0x8; //PM1_TMR
+ fadt->gpe0_blk = pmbase + 0x20; //GPE0_STS
+ fadt->gpe1_blk = 0;
+
+ /* Control Registers - Length */
+ fadt->pm1_evt_len = 4;
+ fadt->pm1_cnt_len = 2;
+ fadt->pm2_cnt_len = 1;
+ fadt->pm_tmr_len = 4;
+ fadt->gpe0_blk_len = 8;
+ fadt->gpe1_blk_len = 0;
+ fadt->gpe1_base = 0;
+ fadt->cst_cnt = 0;
+ fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
+ fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
+ fadt->flush_size = 0;
+ fadt->flush_stride = 0;
+ fadt->duty_offset = 1;
+ fadt->duty_width = 0;
+
+ /* RTC Registers */
+ fadt->day_alrm = 0x0d;
+ fadt->mon_alrm = 0x00;
+ fadt->century = 0x00;
+ fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
+
+ fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+ ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
+ ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_RESET_REG

[U-Boot] [PATCH 3/6] Implemented support for SPD memory file required by BDE FSP

2018-01-26 Thread vnktux 
This patch include the support for SPD binary required by Broadwell-DE FSP in 
case the platform has memory down enabled.

Signed-off-by: Vincenzo Bove 
---
arch/x86/Kconfig | 24 
arch/x86/dts/u-boot.dtsi |  6 ++
2 files changed, 30 insertions(+)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 5c23b2cb57..9d78c80d9f 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -766,6 +766,30 @@ config HIGH_TABLE_SIZE
  Increse it if the default size does not fit the board's needs.
  This is most likely due to a large ACPI DSDT table is used.

+config FSP_MEMORY_DOWN
+ bool "Platform has memory down"
+ help
+   Select this option if your platform has memory soldered on the motherboard 
and FSP need SPD file.
+
+config HAVE_SPD
+ bool "Add SPD file"
+ help
+   Select this option if you have a SPD binary file for your memorydown.
+
+config SPD_FILE
+ string "SPD image filename"
+ depends on HAVE_SPD
+ default "spd_ch0_dimm0.bin"
+ help
+   The filename of the ram SPD binary.
+
+config SPD_ADDR
+ hex "SPD image location"
+ depends on HAVE_SPD
+ default 0xffcb
+ help
+   The location of the SPD binary file.
+
source "arch/x86/lib/efi/Kconfig"

endmenu
diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
index 7e37d4f394..486abe31bf 100644
--- a/arch/x86/dts/u-boot.dtsi
+++ b/arch/x86/dts/u-boot.dtsi
@@ -67,6 +67,12 @@
pos = ;
};
#endif
+#ifdef CONFIG_HAVE_SPD
+ intel-spd {
+ filename = CONFIG_SPD_FILE;
+ pos = ;
+ };
+#endif
#ifdef CONFIG_HAVE_VBT
intel-vbt {
filename = CONFIG_VBT_FILE;
--
2.11.0
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 4/6] Add DTS for Broadwell-DE platform board

2018-01-26 Thread vnktux 
This patch include a DTS file for a Broadwell-de platform used for developing 
called Poseidon. I did not include the 3 microcodes to keep the patch small, do 
I have to submit them as well?

Signed-off-by: Vincenzo Bove 

---
arch/x86/dts/Makefile |   1 +
arch/x86/dts/poseidon.dts | 177 ++
2 files changed, 178 insertions(+)
create mode 100644 arch/x86/dts/poseidon.dts

diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile
index 6d0c4b65ec..e59f192b6e 100644
--- a/arch/x86/dts/Makefile
+++ b/arch/x86/dts/Makefile
@@ -15,6 +15,7 @@ dtb-y += bayleybay.dtb \
efi.dtb \
galileo.dtb \
minnowmax.dtb \
+ poseidon.dtb \
qemu-x86_i440fx.dtb \
qemu-x86_q35.dtb \
theadorable-x86-dfi-bt700.dtb \
diff --git a/arch/x86/dts/poseidon.dts b/arch/x86/dts/poseidon.dts
new file mode 100644
index 00..3a08dc76df
--- /dev/null
+++ b/arch/x86/dts/poseidon.dts
@@ -0,0 +1,177 @@
+/*
+ * Copyright (C) 2014, Bin Meng 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include 
+#include 
+#include 
+
+/include/ "skeleton.dtsi"
+/include/ "serial.dtsi"
+/include/ "rtc.dtsi"
+/include/ "tsc_timer.dtsi"
+/include/ "coreboot_fb.dtsi"
+
+/ {
+ model = "Intel Broadwell-DE";
+ compatible = "x86", "intel,poseidon", "intel,broadwell-de";
+
+ chosen {
+ stdout-path = "/serial";
+ };
+
+ tsc-timer {
+ clock-frequency = <10>;
+ };
+
+ pci {
+ compatible = "pci-x86";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ ranges = <0x0200 0x0 0xc000 0xc000 0 0x1000
+ 0x4200 0x0 0xd000 0xd000 0 0x1000
+ 0x0100 0x0 0x2000 0x2000 0 0xe000>;
+
+ pch@1f,0 {
+ reg = <0xf800 0 0 0 0>;
+ compatible = "intel,pch9";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ irq-router {
+ compatible = "intel,irq-router";
+ intel,pirq-config = "ibase";
+ intel,ibase-offset = <0x50>;
+ intel,pirq-link = <8 8>;
+ intel,pirq-mask = <0xdee0>;
+ intel,pirq-routing = <
+ /*PCI_BDF(0, 31, 0) LPC Controller does not generate an interrupt */
+ PCI_BDF(0, 31, 2) INTB PIRQB /* SATA Controller #1 */
+ PCI_BDF(0, 31, 3) INTC PIRQC /* SMBus Controller */
+ PCI_BDF(0, 31, 5) INTB PIRQB/* SATA Controller #2 */
+ PCI_BDF(0, 31, 6) INTC PIRQC/* Thermal Subsystem */
+ PCI_BDF(0, 29, 0) INTA PIRQA/* USB EHCI Controller #1 */
+ PCI_BDF(0, 28, 0) INTA PIRQA/* PCI Express Port 1 */
+ PCI_BDF(0, 28, 1) INTB PIRQB/* PCI Express Port 2 */
+ PCI_BDF(0, 28, 2) INTC PIRQC/* PCI Express Port 3 */
+ PCI_BDF(0, 28, 3) INTD PIRQD/* PCI Express Port 4 */
+ PCI_BDF(0, 28, 4) INTA PIRQA/* PCI Express Port 5 */
+ PCI_BDF(0, 28, 5) INTB PIRQB/* PCI Express Port 6 */
+ PCI_BDF(0, 28, 6) INTC PIRQC/* PCI Express Port 7 */
+ PCI_BDF(0, 28, 7) INTD PIRQD/* PCI Express Port 8 */
+ PCI_BDF(0, 25, 0) INTA PIRQA/* Gigabit Ethernet Controller*/
+ PCI_BDF(0, 22, 0) INTA PIRQA/* Intel Management Engine Interface #1 */
+ PCI_BDF(0, 22, 1) INTB PIRQB/* Intel Management Engine Interface #2*/
+ PCI_BDF(0, 22, 2) INTC PIRQC/* IDE-R*/
+ PCI_BDF(0, 22, 3) INTD PIRQD/* KT*/
+ PCI_BDF(0, 20, 0) INTA PIRQA/* xHCI Controller */
+ >;
+ };
+
+ };
+ };
+
+ fsp {
+ compatible = "intel,broadwell-de-fsp";
+ fsp,memEccSupport = ;
+fsp,memDdrMemoryType = ;
+ fsp,memRankMultiplication = ;
+fsp,memRankMarginTool = ;
+fsp,memScrambling = ;
+ fsp,memRefreshMode = ;
+fsp,memMcOdtOverride = ;
+ fsp,memCAParity = ;
+fsp,memThermalThrottling = ;
+fsp,memPowerSavingsMode = ;
+ fsp,memElectricalThrottling = ;
+ fsp,memPagePolicy = ;
+ fsp,memSocketInterleaveBelow4G = ;
+ fsp,memChannelInterleave = ;
+ fsp,memRankInterleave = ;
+
+ #ifdef CONFIG_FSP_MEMORY_DOWN
+ fsp,memDownEnable;
+ fsp,memDownCh0Dimm0SpdPtr = ;
+ fsp,memDownCh0Dimm1SpdPtr = <0x0>;
+ fsp,memDownCh1Dimm0SpdPtr = <0x0>;
+ fsp,memDownCh1Dimm1SpdPtr = <0x0>;
+ #endif
+
+ /*#ifdef CONFIG_ENABLE_MRC_CACHE
+ fsp,mem-fast-boot = ;
+ #else
+ fsp,mem-fast-boot = ;
+ #endif*/
+ fsp,mem-fast-boot = ;
+
+fsp,pam0-hienable = ;
+ fsp,pam1-loenable = ;
+ fsp,pam1-hienable = ;
+ fsp,pam2-loenable = ;
+ fsp,pam2-hienable = ;
+ fsp,pam3-loenable = ;
+ fsp,pam3-hienable = ;
+ fsp,pam4-loenable = ;
+ fsp,pam4-hienable = ;
+ fsp,pam5-loenable = ;
+ fsp,pam5-hienable = ;
+fsp,pam6-loenable = ;
+ fsp,pam6-hienable = ;
+ fsp,memAdr = ;
+   fsp,serial-port-type = ;
+ fsp,serial-port-address = <0x3f8>;
+ fsp,serial-port-configure;
+ fsp,serial-port-baudrate = ;
+ fsp,serial-port-controller-init0;
+ fsp,serial-port-controller-init1;
+ fsp,config-iou1-pci-port3 = ;
+   fsp,config-iou2-pci-port1 = ;
+ fsp,pch-pci-port1;
+ fsp,pch-pci-port2;
+ fsp,pch-pci-port3;
+ fsp,pch-pci-port4;
+ fsp,pch-pci-port5;
+ fsp,pch-pci-port6;
+ fsp,pch-pci-port7;
+ fsp,pch-pci-port8;
+ fsp,ehci1-enable;
+ fsp,hyper-threading;
+ fsp,debug-output-level = ;
+ fsp,tco-timer-halt-lock;
+ fsp,turbo-mode;
+ fsp,boot-perf-mode;
+ fsp,pcie-port1a-aspm = ;
+ fsp,pci

[U-Boot] [PATCH 5/6] Add Poseidon platform, based on BDE with memory down

2018-01-26 Thread vnktux 
This patch include a board called Poseidon. That is a platform based on 
Broadwell-DE with memory down enabled on channel 0 dimm 0. This platform was 
used to implement the architecture in U-Boot.

Signed-off-by: Vincenzo Bove 
---
board/prodrive/Kconfig |  23 
board/prodrive/poseidon/.gitignore |   5 +
board/prodrive/poseidon/Kconfig|  45 +++
board/prodrive/poseidon/MAINTAINERS|   6 +
board/prodrive/poseidon/Makefile   |   8 ++
board/prodrive/poseidon/acpi/mainboard.asl |  11 ++
board/prodrive/poseidon/dsdt.asl   | 187 +
board/prodrive/poseidon/poseidon.c |  18 +++
board/prodrive/poseidon/start.S|   9 ++
configs/poseidon_defconfig |  70 +++
include/configs/poseidon.h |  29 +
11 files changed, 411 insertions(+)
create mode 100644 board/prodrive/Kconfig
create mode 100644 board/prodrive/poseidon/.gitignore
create mode 100644 board/prodrive/poseidon/Kconfig
create mode 100644 board/prodrive/poseidon/MAINTAINERS
create mode 100644 board/prodrive/poseidon/Makefile
create mode 100644 board/prodrive/poseidon/acpi/mainboard.asl
create mode 100644 board/prodrive/poseidon/dsdt.asl
create mode 100644 board/prodrive/poseidon/poseidon.c
create mode 100644 board/prodrive/poseidon/start.S
create mode 100644 configs/poseidon_defconfig
create mode 100644 include/configs/poseidon.h

diff --git a/board/prodrive/Kconfig b/board/prodrive/Kconfig
new file mode 100644
index 00..4828b65b2b
--- /dev/null
+++ b/board/prodrive/Kconfig
@@ -0,0 +1,23 @@
+#
+# Copyright (C) 2017, Vincenzo Bove 
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+if VENDOR_PRODRIVE
+
+choice
+ prompt "Mainboard model"
+ optional
+
+config TARGET_POSEIDON
+ bool "Poseidon"
+ help
+   This target is for Prodrive Poseidon.
+   Embedded board hosting x86 Broadwell-DE Xeon processor.
+
+endchoice
+
+source "board/prodrive/poseidon/Kconfig"
+
+endif
diff --git a/board/prodrive/poseidon/.gitignore 
b/board/prodrive/poseidon/.gitignore
new file mode 100644
index 00..c782010f5b
--- /dev/null
+++ b/board/prodrive/poseidon/.gitignore
@@ -0,0 +1,5 @@
+dsdt.aml
+dsdt.asl.tmp
+dsdt.c
+
+!*.bin
\ No newline at end of file
diff --git a/board/prodrive/poseidon/Kconfig b/board/prodrive/poseidon/Kconfig
new file mode 100644
index 00..4fa9feff6e
--- /dev/null
+++ b/board/prodrive/poseidon/Kconfig
@@ -0,0 +1,45 @@
+#
+# Copyright (C) 2017, Vincenzo Bove 
+#
+# SPDX-License-Identifier: GPL-2.0+
+
+if TARGET_POSEIDON
+
+config SYS_BOARD
+ default "poseidon"
+
+config SYS_VENDOR
+ default "prodrive"
+
+config SYS_SOC
+ default "broadwell-de"
+
+config SYS_CONFIG_NAME
+ default "poseidon"
+
+config SYS_TEXT_BASE
+ default 0xffdb
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select X86_RESET_VECTOR
+ select INTEL_BROADWELL_DE
+ select BOARD_ROMSIZE_KB_16384
+ select SPI_FLASH_MACRONIX
+
+config PCIE_ECAM_BASE
+ default 0x8000
+
+config SYS_CAR_ADDR
+ hex
+ default 0xfef0
+
+config SYS_CAR_SIZE
+ hex
+ default 0x4
+
+config SYS_PROMPT
+ string
+ default "Poseidon => "
+
+endif
diff --git a/board/prodrive/poseidon/MAINTAINERS 
b/board/prodrive/poseidon/MAINTAINERS
new file mode 100644
index 00..c21f2e6374
--- /dev/null
+++ b/board/prodrive/poseidon/MAINTAINERS
@@ -0,0 +1,6 @@
+Prodrive Poseidon x86 Broadwell-DE
+M: Vincenzo Bove 
+S: Maintained
+F: board/prodrive/poseidon
+F: include/configs/poseidon.h
+F: configs/poseidon_defconfig
diff --git a/board/prodrive/poseidon/Makefile b/board/prodrive/poseidon/Makefile
new file mode 100644
index 00..83fd499814
--- /dev/null
+++ b/board/prodrive/poseidon/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2017, Vincenzo Bove 
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += poseidon.o start.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
diff --git a/board/prodrive/poseidon/acpi/mainboard.asl 
b/board/prodrive/poseidon/acpi/mainboard.asl
new file mode 100644
index 00..4cc8ad376d
--- /dev/null
+++ b/board/prodrive/poseidon/acpi/mainboard.asl
@@ -0,0 +1,11 @@
+/*
+ * Copyright (C) 2017, Vincenzo Bove 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Power Button */
+Device (PWRB)
+{
+ Name(_HID, EISAID("PNP0C0C"))
+}
diff --git a/board/prodrive/poseidon/dsdt.asl b/board/prodrive/poseidon/dsdt.asl
new file mode 100644
index 00..951f320b74
--- /dev/null
+++ b/board/prodrive/poseidon/dsdt.asl
@@ -0,0 +1,187 @@
+/*
+ * Copyright (C) 2017, Vincenzo Bove 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x20110725)
+{
+ /* platform specific */
+ #include 
+
+ Name(_S0, Package() { 0x00, 0x00, 0x00, 0x00 })
+ Name(_S5, Package() { 0x07, 0x00, 0x00, 0x00 })
+
+ Scope (\_SB)
+ {
+ Device (PCI0)
+ {
+ #include 
+ #include 
+ }
+
+ Name (PRUN, Package() {
+ Package() { 0x0008, 0, \_SB.PCI0.LPC0.LNKA, 0 },
+ Package() { 0x0008, 1, \_SB.PCI0.LPC0

[U-Boot] [PATCH 6/6] Updated Makefile and Kconfig in order to build BDE

2018-01-26 Thread vnktux 
This patch modify Makefile and Kconfig file in order to build Broadwell-de 
platforms.

Signed-off-by: Vincenzo Bove 

---
arch/x86/Kconfig|  5 +
arch/x86/cpu/Makefile   |  1 +
include/fdtdec.h|  1 +
lib/fdtdec.c|  1 +
tools/binman/etype/intel_spd.py | 14 ++
5 files changed, 22 insertions(+)
create mode 100644 tools/binman/etype/intel_spd.py

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 9d78c80d9f..57fdcd780b 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -78,6 +78,9 @@ config VENDOR_GOOGLE
config VENDOR_INTEL
bool "Intel"

+config VENDOR_PRODRIVE
+ bool "Prodrive"
+
endchoice

# subarchitectures-specific options below
@@ -105,11 +108,13 @@ source "board/efi/Kconfig"
source "board/emulation/Kconfig"
source "board/google/Kconfig"
source "board/intel/Kconfig"
+source "board/prodrive/Kconfig"

# platform-specific options below
source "arch/x86/cpu/baytrail/Kconfig"
source "arch/x86/cpu/braswell/Kconfig"
source "arch/x86/cpu/broadwell/Kconfig"
+source "arch/x86/cpu/broadwell-de/Kconfig"
source "arch/x86/cpu/coreboot/Kconfig"
source "arch/x86/cpu/ivybridge/Kconfig"
source "arch/x86/cpu/qemu/Kconfig"
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 94cdff18cc..1fb1c40095 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -29,6 +29,7 @@ obj-y += intel_common/
obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/
obj-$(CONFIG_INTEL_BRASWELL) += braswell/
obj-$(CONFIG_INTEL_BROADWELL) += broadwell/
+obj-$(CONFIG_INTEL_BROADWELL_DE) += broadwell-de/
obj-$(CONFIG_SYS_COREBOOT) += coreboot/
obj-$(CONFIG_EFI_APP) += efi/
obj-$(CONFIG_QEMU) += qemu/
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 4afb9ac501..ea8bff43a1 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -150,6 +150,7 @@ enum fdt_compat_id {
COMPAT_INTEL_BAYTRAIL_FSP, /* Intel Bay Trail FSP */
COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP memory-down params */
COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge FSP */
+ COMPAT_INTEL_BROADWELL_DE_FSP,  /* Intel Broadwell-DE FSP */
COMPAT_SUNXI_NAND, /* SUNXI NAND controller */
COMPAT_ALTERA_SOCFPGA_CLK, /* SoCFPGA Clock initialization */
COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE, /* SoCFPGA pinctrl-single */
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index df9d9ae433..e1a2f176e3 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -62,6 +62,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
COMPAT(INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"),
COMPAT(INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
COMPAT(INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
+ COMPAT(INTEL_BROADWELL_DE_FSP, "intel,broadwell-de-fsp"),
COMPAT(COMPAT_SUNXI_NAND, "allwinner,sun4i-a10-nand"),
COMPAT(ALTERA_SOCFPGA_CLK, "altr,clk-mgr"),
COMPAT(ALTERA_SOCFPGA_PINCTRL_SINGLE, "pinctrl-single"),
diff --git a/tools/binman/etype/intel_spd.py b/tools/binman/etype/intel_spd.py
new file mode 100644
index 00..028c98f0c8
--- /dev/null
+++ b/tools/binman/etype/intel_spd.py
@@ -0,0 +1,14 @@
+# Copyright (c) 2016 Google, Inc
+# Written by Simon Glass 
+#
+# SPDX-License-Identifier:  GPL-2.0+
+#
+# Entry-type module for Intel Management Engine binary blob
+#
+
+from entry import Entry
+from blob import Entry_blob
+
+class Entry_intel_spd(Entry_blob):
+def __init__(self, image, etype, node):
+Entry_blob.__init__(self, image, etype, node)
\ No newline at end of file
--
2.11.0
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[U-Boot] [PATCH 2/6] Add Broadwell-DE include header files

2018-01-26 Thread vnktux 
This patch contain all the include headers for Broadwell-DE architecture.

Signed-off-by: Vincenzo Bove 
---
.../asm/arch-broadwell-de/acpi/global_nvs.asl  |  15 +
.../asm/arch-broadwell-de/acpi/irq_helper.h|  36 ++
.../asm/arch-broadwell-de/acpi/irqlinks.asl| 454 
.../asm/arch-broadwell-de/acpi/irqroute.asl|  29 ++
.../include/asm/arch-broadwell-de/acpi/irqroute.h  |  31 ++
.../x86/include/asm/arch-broadwell-de/acpi/lpc.asl |  81 
.../include/asm/arch-broadwell-de/acpi/pcie1.asl   | 455 +
.../asm/arch-broadwell-de/acpi/platform.asl|  61 +++
.../asm/arch-broadwell-de/acpi/southcluster.asl| 339 +++
arch/x86/include/asm/arch-broadwell-de/device.h| 116 ++
.../asm/arch-broadwell-de/fsp/fsp_configs.h| 134 ++
.../include/asm/arch-broadwell-de/fsp/fsp_vpd.h| 116 ++
.../x86/include/asm/arch-broadwell-de/global_nvs.h |  21 +
arch/x86/include/asm/arch-broadwell-de/iomap.h |  58 +++
arch/x86/include/asm/arch-broadwell-de/irq.h   |  88 
15 files changed, 2034 insertions(+)
create mode 100644 arch/x86/include/asm/arch-broadwell-de/acpi/global_nvs.asl
create mode 100644 arch/x86/include/asm/arch-broadwell-de/acpi/irq_helper.h
create mode 100644 arch/x86/include/asm/arch-broadwell-de/acpi/irqlinks.asl
create mode 100644 arch/x86/include/asm/arch-broadwell-de/acpi/irqroute.asl
create mode 100644 arch/x86/include/asm/arch-broadwell-de/acpi/irqroute.h
create mode 100644 arch/x86/include/asm/arch-broadwell-de/acpi/lpc.asl
create mode 100644 arch/x86/include/asm/arch-broadwell-de/acpi/pcie1.asl
create mode 100644 arch/x86/include/asm/arch-broadwell-de/acpi/platform.asl
create mode 100644 arch/x86/include/asm/arch-broadwell-de/acpi/southcluster.asl
create mode 100644 arch/x86/include/asm/arch-broadwell-de/device.h
create mode 100644 arch/x86/include/asm/arch-broadwell-de/fsp/fsp_configs.h
create mode 100644 arch/x86/include/asm/arch-broadwell-de/fsp/fsp_vpd.h
create mode 100644 arch/x86/include/asm/arch-broadwell-de/global_nvs.h
create mode 100644 arch/x86/include/asm/arch-broadwell-de/iomap.h
create mode 100644 arch/x86/include/asm/arch-broadwell-de/irq.h

diff --git a/arch/x86/include/asm/arch-broadwell-de/acpi/global_nvs.asl 
b/arch/x86/include/asm/arch-broadwell-de/acpi/global_nvs.asl
new file mode 100644
index 00..a28d4dfade
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell-de/acpi/global_nvs.asl
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2016 Bin Meng 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include 
+
+OperationRegion(GNVS, SystemMemory, ACPI_GNVS_ADDR, ACPI_GNVS_SIZE)
+Field(GNVS, ByteAcc, NoLock, Preserve)
+{
+ Offset (0x00),
+ PCNT, 8, /* processor count */
+ IURE, 8, /* internal UART enabled */
+}
diff --git a/arch/x86/include/asm/arch-broadwell-de/acpi/irq_helper.h 
b/arch/x86/include/asm/arch-broadwell-de/acpi/irq_helper.h
new file mode 100644
index 00..5b7d9c
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell-de/acpi/irq_helper.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2017, Vincenzo Bove 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#undef PCI_DEV_PIRQ_ROUTES
+#undef ACPI_DEV_IRQ
+#undef PCI_DEV_PIRQ_ROUTE
+#undef PIRQ_PIC_ROUTES
+#undef PIRQ_PIC
+#undef IRQROUTE_H
+
+#if defined(PIC_MODE)
+
+#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \
+ { Package() { ## dev_ ## , pin_, \_SB.PCI0.LPCB.LNK ## pin_name_, 0 } }
+
+#else /* defined(PIC_MODE) */
+
+#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \
+ { Package() { ## dev_ ## , pin_, 0, PIRQ ## pin_name_ ## _APIC_IRQ } }
+
+#endif
+
+#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \
+ { ACPI_DEV_IRQ(dev_, 0, a_), \
+   ACPI_DEV_IRQ(dev_, 1, b_), \
+   ACPI_DEV_IRQ(dev_, 2, c_), \
+   ACPI_DEV_IRQ(dev_, 3, d_)  }
+
+/* Empty PIRQ_PIC definition. */
+#define PIRQ_PIC(pirq_, pic_irq_)
+
+///* Include the mainboard irq route definition */
+#include "irqroute.h"
diff --git a/arch/x86/include/asm/arch-broadwell-de/acpi/irqlinks.asl 
b/arch/x86/include/asm/arch-broadwell-de/acpi/irqlinks.asl
new file mode 100644
index 00..36942982c8
--- /dev/null
+++ b/arch/x86/include/asm/arch-broadwell-de/acpi/irqlinks.asl
@@ -0,0 +1,454 @@
+/*
+ * Copyright (C) 2017, Vincenzo Bove 
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+OperationRegion (PRR0, PCI_Config, 0x00, 0x100)
+Field (PRR0, AnyAcc, NoLock, Preserve) {
+  Offset(0x60),
+  PIRA, 8,
+  PIRB, 8,
+  PIRC, 8,
+  PIRD, 8,
+  Offset(0x68),
+  PIRE, 8,
+  PIRF, 8,
+  PIRG, 8,
+  PIRH, 8
+}
+
+Device (LNKA) {  // PCI IRQ link A
+  Name (_HID,EISAID("PNP0C0F"))
+  //Name(_UID, 1)
+  Method (_STA,0,NotSerialized) {
+If(And(PIRA, 0x80)) {
+  Return (0x9)
+} Else {
+  Return (0xB)
+} // Don't display
+  }
+
+  Method (_DIS,0,NotSerialized) {
+Or (PIRA, 0x80, PIRA)
+  }
+
+  Method (_CRS,0,Serialized) {
+Name (BUF0, ResourceTemplate() {IRQ(Level,ActiveLow,Shared){0}})
+//
+// Define references to buffer elem

[U-Boot] Minnowmax Turbot not supported

2018-02-02 Thread vnktux 
Hi all,

I have just received from ADI Engineering a MinnowBoard Turbot Quad-core 
(Baytrail E3845).
I wanted to compile bare metal U-Boot according to the README.x86 in the doc 
folder. Unfortunately the board doesn't boot and doesn't print any informations 
on the serial port. I know that also someone else have the same problem, but I 
couldn't find any solutions on internet. It look like the board doesn't load 
the correct microcode.

I got the descriptor file from the original firmware.
Then for the FSP binary I tried the one from the official Intel Github repo, 
and also the one you can download from Intelfirmware.com called FSP Gold 2014 
Minnowmax.

From the official UEFI firmware I can see the following specs:
CPU Family: 6
Model: 7
Step: 9
Microcode: 906
Sig: 0x30679
PF: 0x1

Did anybody succeeded to boot U-Boot on the new Turbot board?

Best regards,
Vincenzo
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Re: [U-Boot] [PATCH 1/1] Broadwell-DE Implementation

2018-02-05 Thread vnktux 
Hi Peter,

Thanks a lot, your help was really precious! I just tested your fix on two 
platforms, one with memory down and one with DIMM. U-Boot works on both of them 
and the booting time is around 17 seconds. Now I will try to fix some minor 
errors that U-Boot report on the shell and then I will definetly submit a new 
patch. (If I manage to understand how to properly submit one). Thanks again!

Best regards,
Vincenzo

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