[PATCH 0/4] Add StarFive JH7110 PCIe drvier support

[Minda Chen]

This patchset needs to apply after patchset in [1]. These PCIe series patches
are based on the JH7110 RISC-V SoC and VisionFive V2 board.

The PCIe driver depends on gpio, pinctrl, clk and reset driver to do init.
The PCIe dts configuation includes all these setting.

The PCIe drivers codes has been tested on the VisionFive V2 boards.
The test devices includes M.2 NVMe SSD and Realtek 8169 Ethernet adapter.

Mason Huo (4):
  starfive: pci: Add StarFive JH7110 pcie driver
  clk: starfive: Add PCIe clocks for PCIe controller
  configs: starfive-jh7110: Add support for PCIe host driver
  riscv: dts: starfive: Enable PCIe host controller

The JH7110 minimal system patchset upstream is in progress.
PCIe driver patches is based on this patchset.

The JH7110 minimal system patchset details are listed in [1].

[1] 
https://patchwork.ozlabs.org/project/uboot/cover/20230118081132.31403-1-yanhong.w...@starfivetech.com/

For more JH7110 and visionFive v2 information and support,
you can visit RVspace wiki[2].

[2] https://wiki.rvspace.org/

 arch/riscv/dts/jh7110.dtsi  |  79 
 arch/riscv/dts/starfive_visionfive2.dts | 104 +
 configs/starfive_visionfive2_defconfig  |   9 +
 drivers/clk/starfive/clk-jh7110.c   |  27 ++
 drivers/pci/Kconfig |  11 +
 drivers/pci/Makefile|   1 +
 drivers/pci/pcie_starfive_jh7110.c  | 482 
 7 files changed, 713 insertions(+)
 create mode 100644 drivers/pci/pcie_starfive_jh7110.c

-- 
2.17.1

[PATCH 2/4] clk: starfive: Add PCIe clocks for PCIe controller

[Minda Chen]

From: Mason Huo 

Add the stg clocks for StarFive JH7110 PCIe controller.

Signed-off-by: Mason Huo  
Signed-off-by: Minda Chen 
---
 drivers/clk/starfive/clk-jh7110.c | 27 +++
 1 file changed, 27 insertions(+)

diff --git a/drivers/clk/starfive/clk-jh7110.c 
b/drivers/clk/starfive/clk-jh7110.c
index a904852cab..7cfed7b847 100644
--- a/drivers/clk/starfive/clk-jh7110.c
+++ b/drivers/clk/starfive/clk-jh7110.c
@@ -305,6 +305,10 @@ static int jh7110_syscrg_init(struct udevice *dev)
clk_dm(JH7110_SYSCLK_AON_APB,
   starfive_clk_fix_factor(priv->reg,
   "aon_apb", "apb_bus_func", 1, 1));
+   clk_dm(JH7110_SYSCLK_NOCSTG_BUS,
+  starfive_clk_divider(priv->reg,
+   "nocstg_bus", "bus_root",
+   OFFSET(JH7110_SYSCLK_NOCSTG_BUS), 3));
clk_dm(JH7110_SYSCLK_QSPI_AHB,
   starfive_clk_gate(priv->reg,
 "qspi_ahb", "ahb1",
@@ -342,6 +346,11 @@ static int jh7110_syscrg_init(struct udevice *dev)
   starfive_clk_divider(priv->reg,
"usb_125m", "gmacusb_root",
OFFSET(JH7110_SYSCLK_USB_125M), 4));
+   clk_dm(JH7110_SYSCLK_NOC_BUS_STG_AXI,
+  starfive_clk_gate(priv->reg,
+"noc_bus_stg_axi",
+"nocstg_bus",
+ OFFSET(JH7110_SYSCLK_NOC_BUS_STG_AXI)));
clk_dm(JH7110_SYSCLK_GMAC1_AHB,
   starfive_clk_gate(priv->reg,
 "gmac1_ahb", "ahb0",
@@ -512,6 +521,24 @@ static int jh7110_stgcrg_init(struct udevice *dev)
clk_dm(JH7110_STGCLK_USB_REFCLK,
   starfive_clk_divider(priv->reg, "usb_refclk", "osc",
STGOFFSET(JH7110_STGCLK_USB_REFCLK), 2));
+   clk_dm(JH7110_STGCLK_PCIE0_TL,
+  starfive_clk_gate(priv->reg, "pcie0_tl", "stg_axiahb",
+STGOFFSET(JH7110_STGCLK_PCIE0_TL)));
+   clk_dm(JH7110_STGCLK_PCIE0_AXI,
+  starfive_clk_gate(priv->reg, "pcie0_axi_mst0", "stg_axiahb",
+STGOFFSET(JH7110_STGCLK_PCIE0_AXI)));
+   clk_dm(JH7110_STGCLK_PCIE0_APB,
+  starfive_clk_gate(priv->reg, "pcie0_apb", "stg_apb",
+STGOFFSET(JH7110_STGCLK_PCIE0_APB)));
+   clk_dm(JH7110_STGCLK_PCIE1_TL,
+  starfive_clk_gate(priv->reg, "pcie1_tl", "stg_axiahb",
+STGOFFSET(JH7110_STGCLK_PCIE1_TL)));
+   clk_dm(JH7110_STGCLK_PCIE1_AXI,
+  starfive_clk_gate(priv->reg, "pcie1_axi_mst0", "stg_axiahb",
+STGOFFSET(JH7110_STGCLK_PCIE1_AXI)));
+   clk_dm(JH7110_STGCLK_PCIE1_APB,
+  starfive_clk_gate(priv->reg, "pcie1_apb", "stg_apb",
+STGOFFSET(JH7110_STGCLK_PCIE1_APB)));
return 0;
 }
 
-- 
2.17.1

[PATCH 1/4] starfive: pci: Add StarFive JH7110 pcie driver

[Minda Chen]

From: Mason Huo 

Add pcie driver for StarFive JH7110, the driver depends on
starfive gpio, pinctrl, clk and reset driver to do init.

Several devices are tested:
a) M.2 NVMe SSD
b) Realtek 8169 Ethernet adapter.

Signed-off-by: Mason Huo 
Signed-off-by: Minda Chen 
---
 drivers/pci/Kconfig|  11 +
 drivers/pci/Makefile   |   1 +
 drivers/pci/pcie_starfive_jh7110.c | 482 +
 3 files changed, 494 insertions(+)
 create mode 100644 drivers/pci/pcie_starfive_jh7110.c

diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index a3b662fb13..da9290204b 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -365,4 +365,15 @@ config PCIE_UNIPHIER
  Say Y here if you want to enable PCIe controller support on
  UniPhier SoCs.
 
+config PCIE_STARFIVE_JH7110
+   bool "Enable Starfive JH7110 PCIe driver"
+   depends on STARFIVE_JH7110
+   depends on PINCTRL_STARFIVE_JH7110
+   depends on CLK_JH7110
+   depends on RESET_JH7110
+   default y
+   help
+ Say Y here if you want to enable PCIe controller support on
+ StarFive JH7110 SoC.
+
 endif
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index dd1ad91ced..92a92409ab 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -49,3 +49,4 @@ obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o
 obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o
 obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o
 obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o
+obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o
diff --git a/drivers/pci/pcie_starfive_jh7110.c 
b/drivers/pci/pcie_starfive_jh7110.c
new file mode 100644
index 00..1f14352dfb
--- /dev/null
+++ b/drivers/pci/pcie_starfive_jh7110.c
@@ -0,0 +1,482 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * StarFive PLDA PCIe host controller driver
+ *
+ * Copyright (c) 2023 Starfive, Inc.
+ * Author: Mason Huo 
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define GEN_SETTINGS   0x80
+#define PCIE_PCI_IDS   0x9C
+#define PCIE_WINROM0xFC
+#define PMSG_SUPPORT_RX0x3F0
+#define PCI_MISC   0xB4
+
+#define PLDA_EP_ENABLE 0
+#define PLDA_RP_ENABLE 1
+
+#define IDS_REVISION_ID0x02
+#define IDS_PCI_TO_PCI_BRIDGE  0x060400
+#define IDS_CLASS_CODE_SHIFT   8
+
+#define PREF_MEM_WIN_64_SUPPORTBIT(3)
+#define PMSG_LTR_SUPPORT   BIT(2)
+#define PLDA_FUNCTION_DIS  BIT(15)
+#define PLDA_FUNC_NUM  4
+#define PLDA_PHY_FUNC_SHIFT9
+
+#define XR3PCI_ATR_AXI4_SLV0   0x800
+#define XR3PCI_ATR_SRC_ADDR_LOW0x0
+#define XR3PCI_ATR_SRC_ADDR_HIGH   0x4
+#define XR3PCI_ATR_TRSL_ADDR_LOW   0x8
+#define XR3PCI_ATR_TRSL_ADDR_HIGH  0xc
+#define XR3PCI_ATR_TRSL_PARAM  0x10
+#define XR3PCI_ATR_TABLE_OFFSET0x20
+#define XR3PCI_ATR_MAX_TABLE_NUM   8
+
+#define XR3PCI_ATR_SRC_WIN_SIZE_SHIFT  1
+#define XR3PCI_ATR_SRC_ADDR_MASK   0xf000
+#define XR3PCI_ATR_TRSL_ADDR_MASK  0xf000
+#define XR3_PCI_ECAM_SIZE  28
+#define XR3PCI_ATR_TRSL_DIRBIT(22)
+/* IDs used in the XR3PCI_ATR_TRSL_PARAM */
+#define XR3PCI_ATR_TRSLID_PCIE_MEMORY  0x0
+#define XR3PCI_ATR_TRSLID_PCIE_CONFIG  0x1
+
+#define ECAM_BUS_SHIFT 20
+#define ECAM_DEV_SHIFT 15
+#define ECAM_FUNC_SHIFT12
+/* Secondary bus number offset in config space */
+#define PCI_SECONDARY_BUS  0x19
+
+/* system control */
+#define STG_SYSCON_K_RP_NEP_SHIFT  8
+#define STG_SYSCON_K_RP_NEP_MASK   0x100
+#define STG_SYSCON_AXI4_SLVL_ARFUNC_MASK   0x7FFF00
+#define STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT  8
+#define STG_SYSCON_AXI4_SLVL_AWFUNC_MASK   0x7FFF
+#define STG_SYSCON_AXI4_SLVL_AWFUNC_SHIFT  0
+#define STG_SYSCON_CLKREQ_SHIFT22
+#define STG_SYSCON_CLKREQ_MASK 0x40
+#define STG_SYSCON_CKREF_SRC_SHIFT 18
+#define STG_SYSCON_CKREF_SRC_MASK  0xC
+
+struct starfive_pcie {
+   struct udevice *dev;
+
+   void __iomem *reg_base;
+   void __iomem *cfg_base;
+
+   struct regmap *regmap;
+   u32 stg_arfun;
+   u32 stg_awfun;
+   u32 stg_rp_nep;
+
+   struct clk_bulk clks;
+   struct reset_ctl_bulk   rsts;
+
+   int atr_table_num;
+   int first_busno;
+};
+
+static int starfive_pcie_addr_valid(pci_dev_t bdf, int first_busno)
+{
+   if ((PCI_BUS(bdf) == first_busno) && (PCI_DEV(bdf) > 0))
+   return 0;
+   if ((PCI_BUS(bdf) == first_busno + 1)

[PATCH 4/4] riscv: dts: starfive: Enable PCIe host controller

[Minda Chen]

From: Mason Huo 

Enable and add pinctrl configuration for PCIe host controller.
Also add JH7110 stg syscon configuration.

Signed-off-by: Mason Huo 
Signed-off-by: Minda Chen 
---
 arch/riscv/dts/jh7110.dtsi  |  79 ++
 arch/riscv/dts/starfive_visionfive2.dts | 104 
 2 files changed, 183 insertions(+)

diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index 49d34b85af..6f37d107e3 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -493,5 +493,84 @@
#address-cells = <1>;
#size-cells = <0>;
};
+
+   pcie0: pcie@2B00 {
+   compatible = "starfive,jh7110-pcie";
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   reg = <0x0 0x2B00 0x0 0x100>,
+ <0x9 0x4000 0x0 0x1000>;
+   reg-names = "reg", "config";
+   device_type = "pci";
+   starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130>;
+   bus-range = <0x0 0xff>;
+   ranges = <0x8200  0x0 0x3000  0x0 0x3000 
0x0 0x0800>,
+   <0xc300  0x9 0x  0x9 0x 0x0 
0x4000>;
+   msi-parent = <&plic>;
+   interrupts = <56>;
+   interrupt-controller;
+   interrupt-names = "msi";
+   interrupt-parent = <&plic>;
+   interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+   interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
+   <0x0 0x0 0x0 0x2 &plic 0x2>,
+   <0x0 0x0 0x0 0x3 &plic 0x3>,
+   <0x0 0x0 0x0 0x4 &plic 0x4>;
+   resets = <&stgcrg JH7110_STGRST_PCIE0_MST0>,
+<&stgcrg JH7110_STGRST_PCIE0_SLV0>,
+<&stgcrg JH7110_STGRST_PCIE0_SLV>,
+<&stgcrg JH7110_STGRST_PCIE0_BRG>,
+<&stgcrg JH7110_STGRST_PCIE0_CORE>,
+<&stgcrg JH7110_STGRST_PCIE0_APB>;
+   reset-names = "rst_mst0", "rst_slv0", "rst_slv",
+ "rst_brg", "rst_core", "rst_apb";
+   clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
+<&stgcrg JH7110_STGCLK_PCIE0_TL>,
+<&stgcrg JH7110_STGCLK_PCIE0_AXI>,
+<&stgcrg JH7110_STGCLK_PCIE0_APB>;
+   clock-names = "noc", "tl", "axi_mst0", "apb";
+   status = "disabled";
+   };
+
+   pcie1: pcie@2C00 {
+   compatible = "starfive,jh7110-pcie";
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   reg = <0x0 0x2C00 0x0 0x100>,
+ <0x9 0xc000 0x0 0x1000>;
+   reg-names = "reg", "config";
+   device_type = "pci";
+   starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0>;
+   bus-range = <0x0 0xff>;
+   ranges = <0x8200  0x0 0x3800  0x0 0x3800 
0x0 0x0800>,
+   <0xc300  0x9 0x8000  0x9 0x8000 0x0 
0x4000>;
+   msi-parent = <&plic>;
+   interrupts = <57>;
+   interrupt-controller;
+   interrupt-names = "msi";
+   interrupt-parent = <&plic>;
+   interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+   interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
+   <0x0 0x0 0x0 0x2 &plic 0x2>,
+   <0x0 0x0 0x0 0x3 &plic 0x3>,
+   <0x0 0x0 0x0 0x4 &plic 0x4>;
+   resets = <&stg

[PATCH 3/4] configs: starfive-jh7110: Add support for PCIe host driver

[Minda Chen]

From: Mason Huo 

also add the nvme driver and rtl8169 support.

Signed-off-by: Mason Huo 
Signed-off-by: Minda Chen 
---
 configs/starfive_visionfive2_defconfig | 9 +
 1 file changed, 9 insertions(+)

diff --git a/configs/starfive_visionfive2_defconfig 
b/configs/starfive_visionfive2_defconfig
index 54ae6b2a43..8e38201858 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -11,6 +11,7 @@ CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
 CONFIG_SYS_LOAD_ADDR=0x8200
+CONFIG_SYS_PCI_64BIT=y
 CONFIG_TARGET_STARFIVE_VISIONFIVE2=y
 CONFIG_SPL_OPENSBI_LOAD_ADDR=0x4000
 CONFIG_ARCH_RV64I=y
@@ -45,8 +46,11 @@ CONFIG_SYS_CBSIZE=256
 CONFIG_SYS_PBSIZE=276
 CONFIG_SYS_BOOTM_LEN=0x400
 CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_PCI=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_SPL_CLK_COMPOSITE_CCF=y
 CONFIG_CLK_CCF=y
 CONFIG_CLK_COMPOSITE_CCF=y
@@ -61,6 +65,11 @@ CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_ISSI=y
 CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_RTL8169=y
+CONFIG_NVME_PCI=y
+CONFIG_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCI_REGION_MULTI_ENTRY=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_PINCTRL_STARFIVE=y
-- 
2.17.1

[PATCH v2 3/3] riscv: dts: starfive: Enable PCIe host controller

[Minda Chen]

From: Mason Huo 

Enable and add pinctrl configuration for PCIe host controller.
Also add JH7110 stg syscon configuration.

Signed-off-by: Mason Huo 
Signed-off-by: Minda Chen 
---
 .../dts/jh7110-starfive-visionfive-2.dtsi | 99 +++
 arch/riscv/dts/jh7110.dtsi| 75 ++
 2 files changed, 174 insertions(+)

diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi 
b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index e669c2a26a..995f842a6b 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -178,6 +178,87 @@
slew-rate = <0>;
};
};
+
+   pcie0_perst_default: pcie0_perst_default {
+   perst-pins {
+   pinmux = ;
+   drive-strength = <2>;
+   input-disable;
+   input-schmitt-disable;
+   slew-rate = <0>;
+   };
+   };
+
+   pcie0_perst_active: pcie0_perst_active {
+   perst-pins {
+   pinmux = ;
+   drive-strength = <2>;
+   input-disable;
+   input-schmitt-disable;
+   slew-rate = <0>;
+   };
+   };
+
+   pcie0_wake_default: pcie0_wake_default {
+   wake-pins {
+   pinmux = ;
+   drive-strength = <2>;
+   input-enable;
+   input-schmitt-disable;
+   slew-rate = <0>;
+   };
+   };
+
+   pcie0_clkreq_default: pcie0_clkreq_default {
+   clkreq-pins {
+   pinmux = ;
+   drive-strength = <2>;
+   input-enable;
+   input-schmitt-disable;
+   slew-rate = <0>;
+   };
+   };
+
+   pcie1_perst_default: pcie1_perst_default {
+   perst-pins {
+   pinmux = ;
+   drive-strength = <2>;
+   input-disable;
+   input-schmitt-disable;
+   slew-rate = <0>;
+   };
+   };
+
+   pcie1_perst_active: pcie1_perst_active {
+   perst-pins {
+   pinmux = ;
+   drive-strength = <2>;
+   input-disable;
+   input-schmitt-disable;
+   slew-rate = <0>;
+   };
+   };
+
+   pcie1_wake_default: pcie1_wake_default {
+   wake-pins {
+   pinmux = ;
+   drive-strength = <2>;
+   input-enable;
+   input-schmitt-disable;
+   slew-rate = <0>;
+   };
+   };
+
+   pcie1_clkreq_default: pcie1_clkreq_default {
+   clkreq-pins {
+   pinmux = ;
+   drive-strength = <2>;
+   input-enable;
+   input-schmitt-disable;
+   slew-rate = <0>;
+   };
+   };
+
 };
 
 &mmc0 {
@@ -234,6 +315,24 @@
};
 };
 
+&pcie0 {
+   pinctrl-names = "perst-default", "perst-active", "wake-default", 
"clkreq-default";
+   pinctrl-0 = <&pcie0_perst_default>;
+   pinctrl-1 = <&pcie0_perst_active>;
+   pinctrl-2 = <&pcie0_wake_default>;
+   pinctrl-3 = <&pcie0_clkreq_default>;
+   status = "disabled";
+};
+
+&pcie1 {
+   pinctrl-names = "perst-default", "perst-active", "wake-default", 
"clkreq-default";
+   pinctrl-0 = <&pcie1_perst_default>;
+   pinctrl-1 = <&pcie1_perst_active>;
+   pinctrl-2 = <&pcie1_wake_default>;
+   pinctrl-3 = <&pcie1_clkreq_default>;
+   status = "okay";
+};
+
 &syscrg {
assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
  <&syscrg JH7110_SYSCLK_BUS_ROOT>,
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index d3e9f92987..e43296c9d5 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -578,5 +578,80 @@
gpio-controller;
#gpio-cells = <2>;
};
+
+   pcie0: pcie@2B00 {
+   compatible = "starfive,jh7110-pcie";
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   reg = <0x0 0x2B000

[PATCH v2 0/3] Add StarFive JH7110 PCIe drvier support

[Minda Chen]

This patchset needs to apply after patchset in [1]. These PCIe series patches
are based on the JH7110 RISC-V SoC and VisionFive V2 board.

[1] 
https://patchwork.ozlabs.org/project/uboot/cover/20230303032432.7837-1-yanhong.w...@starfivetech.com/

The PCIe driver depends on gpio, pinctrl, clk and reset driver to do init.
The PCIe dts configuation includes all these setting.

The PCIe drivers codes has been tested on the VisionFive V2 boards.
The test devices includes M.2 NVMe SSD and Realtek 8169 Ethernet adapter.

previous patch version

v1: 
https://patchwork.ozlabs.org/project/uboot/cover/20230223105240.15180-1-minda.c...@starfivetech.com/

changes
v1->v2
   1. remove clock commit. The pcie clocks change has been includeded in [1].
   2. Using GENMASK marco1 in patch1.
   3. remove the syscon dts node in patch3. The syscon dts dts node has been
  included in [1]. 

---

The JH7110 minimal system patchset upstream is in progress.
PCIe driver patches is based on this patchset.

The JH7110 minimal system patchset details are listed in [1].

For more JH7110 and visionFive v2 information and support,
you can visit RVspace wiki[2].

[2] https://wiki.rvspace.org/

Mason Huo (3):
  starfive: pci: Add StarFive JH7110 pcie driver
  configs: starfive-jh7110: Add support for PCIe host driver
  riscv: dts: starfive: Enable PCIe host controller

 .../dts/jh7110-starfive-visionfive-2.dtsi |  99 
 arch/riscv/dts/jh7110.dtsi|  75 +++
 configs/starfive_visionfive2_defconfig|   9 +
 drivers/pci/Kconfig   |  11 +
 drivers/pci/Makefile  |   1 +
 drivers/pci/pcie_starfive_jh7110.c| 478 ++
 6 files changed, 673 insertions(+)
 create mode 100644 drivers/pci/pcie_starfive_jh7110.c


base-commit: b0eda49bc9b00503366f2ec431be0178caf9e9b5
prerequisite-patch-id: a84452ba131408ff842b65ae19a3a05f64b3ff60
prerequisite-patch-id: bb320a2102f46d2b2d08b4467cbcdb92050767b8
prerequisite-patch-id: ef5e9d61f7392c7d2e5321aa8a10996ca8eae5fc
prerequisite-patch-id: 26dfdb401d680ecd9449acf09131cf4790e987b7
prerequisite-patch-id: a0cfa5d8cdb49bbe9d4739afa90991f882950881
prerequisite-patch-id: a0509f01172e24b3d163f4701496b0349435bdc0
prerequisite-patch-id: d834ece14ffb525b8c3e661e78736692f33fca9b
prerequisite-patch-id: aa95c1c047d0b7dae469586873a42932d613411d
prerequisite-patch-id: ebc26ed3f97f7babc0fc805152acb578f5eff922
prerequisite-patch-id: 81a83d6fc1e71ce190f9151577deb0c5cd382a20
prerequisite-patch-id: ff5bd799e4cb905fef6cf1cd0ce757980e1d34b7
prerequisite-patch-id: a341d4e8a8e25cb711309123939235fcb3c10c1a
prerequisite-patch-id: 749e4eafb431857ee2bec4ac8e78a682f6a57588
prerequisite-patch-id: 04cd7779c7464c7be683cd2718baee8c6554791d
prerequisite-patch-id: 25cb7c602018ec89abce43d8835926ac3356f5db
prerequisite-patch-id: cf1af96990b01e1025ec50d0b49c79f92f64f352
prerequisite-patch-id: cc5878da5f03e7e1d2c15e88537fd2a93bf47e53
-- 
2.17.1

[PATCH v2 2/3] configs: starfive-jh7110: Add support for PCIe host driver

[Minda Chen]

From: Mason Huo 

also add the nvme driver and rtl8169 support.

Signed-off-by: Mason Huo 
Signed-off-by: Minda Chen 
---
 configs/starfive_visionfive2_defconfig | 9 +
 1 file changed, 9 insertions(+)

diff --git a/configs/starfive_visionfive2_defconfig 
b/configs/starfive_visionfive2_defconfig
index 550d0ff3ab..98d23d9461 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -16,6 +16,7 @@ CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
 CONFIG_SYS_LOAD_ADDR=0x8200
+CONFIG_SYS_PCI_64BIT=y
 CONFIG_TARGET_STARFIVE_VISIONFIVE2=y
 CONFIG_SPL_OPENSBI_LOAD_ADDR=0x4000
 CONFIG_ARCH_RV64I=y
@@ -50,8 +51,11 @@ CONFIG_SYS_CBSIZE=256
 CONFIG_SYS_PBSIZE=276
 CONFIG_SYS_BOOTM_LEN=0x400
 CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_PCI=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_SPL_CLK_COMPOSITE_CCF=y
 CONFIG_CLK_COMPOSITE_CCF=y
 CONFIG_SPL_CLK_JH7110=y
@@ -65,6 +69,11 @@ CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_ISSI=y
 CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_RTL8169=y
+CONFIG_NVME_PCI=y
+CONFIG_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCI_REGION_MULTI_ENTRY=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_SPL_PINCTRL=y
-- 
2.17.1

[PATCH v2 1/3] starfive: pci: Add StarFive JH7110 pcie driver

[Minda Chen]

From: Mason Huo 

Add pcie driver for StarFive JH7110, the driver depends on
starfive gpio, pinctrl, clk and reset driver to do init.

Several devices are tested:
a) M.2 NVMe SSD
b) Realtek 8169 Ethernet adapter.

Signed-off-by: Mason Huo 
Signed-off-by: Minda Chen 
---
 drivers/pci/Kconfig|  11 +
 drivers/pci/Makefile   |   1 +
 drivers/pci/pcie_starfive_jh7110.c | 478 +
 3 files changed, 490 insertions(+)
 create mode 100644 drivers/pci/pcie_starfive_jh7110.c

diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index ef328d2652..e7b0ff5bc3 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -374,4 +374,15 @@ config PCIE_UNIPHIER
  Say Y here if you want to enable PCIe controller support on
  UniPhier SoCs.
 
+config PCIE_STARFIVE_JH7110
+   bool "Enable Starfive JH7110 PCIe driver"
+   depends on STARFIVE_JH7110
+   depends on PINCTRL_STARFIVE_JH7110
+   depends on CLK_JH7110
+   depends on RESET_JH7110
+   default y
+   help
+ Say Y here if you want to enable PCIe controller support on
+ StarFive JH7110 SoC.
+
 endif
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 49506e7ba5..bbe3323bb5 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -49,3 +49,4 @@ obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o
 obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o
 obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o
 obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o
+obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o
diff --git a/drivers/pci/pcie_starfive_jh7110.c 
b/drivers/pci/pcie_starfive_jh7110.c
new file mode 100644
index 00..5ccef1ef02
--- /dev/null
+++ b/drivers/pci/pcie_starfive_jh7110.c
@@ -0,0 +1,478 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * StarFive PLDA PCIe host controller driver
+ *
+ * Copyright (c) 2023 Starfive, Inc.
+ * Author: Mason Huo 
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define GEN_SETTINGS   0x80
+#define PCIE_PCI_IDS   0x9C
+#define PCIE_WINROM0xFC
+#define PMSG_SUPPORT_RX0x3F0
+#define PCI_MISC   0xB4
+
+#define PLDA_EP_ENABLE 0
+#define PLDA_RP_ENABLE 1
+
+#define IDS_REVISION_ID0x02
+#define IDS_PCI_TO_PCI_BRIDGE  0x060400
+#define IDS_CLASS_CODE_SHIFT   8
+
+#define PREF_MEM_WIN_64_SUPPORTBIT(3)
+#define PMSG_LTR_SUPPORT   BIT(2)
+#define PLDA_FUNCTION_DIS  BIT(15)
+#define PLDA_FUNC_NUM  4
+#define PLDA_PHY_FUNC_SHIFT9
+
+#define XR3PCI_ATR_AXI4_SLV0   0x800
+#define XR3PCI_ATR_SRC_ADDR_LOW0x0
+#define XR3PCI_ATR_SRC_ADDR_HIGH   0x4
+#define XR3PCI_ATR_TRSL_ADDR_LOW   0x8
+#define XR3PCI_ATR_TRSL_ADDR_HIGH  0xc
+#define XR3PCI_ATR_TRSL_PARAM  0x10
+#define XR3PCI_ATR_TABLE_OFFSET0x20
+#define XR3PCI_ATR_MAX_TABLE_NUM   8
+
+#define XR3PCI_ATR_SRC_WIN_SIZE_SHIFT  1
+#define XR3PCI_ATR_SRC_ADDR_MASK   GENMASK(31, 12)
+#define XR3PCI_ATR_TRSL_ADDR_MASK  GENMASK(31, 12)
+#define XR3_PCI_ECAM_SIZE  28
+#define XR3PCI_ATR_TRSL_DIRBIT(22)
+/* IDs used in the XR3PCI_ATR_TRSL_PARAM */
+#define XR3PCI_ATR_TRSLID_PCIE_MEMORY  0x0
+#define XR3PCI_ATR_TRSLID_PCIE_CONFIG  0x1
+
+#define ECAM_BUS_SHIFT 20
+#define ECAM_DEV_SHIFT 15
+#define ECAM_FUNC_SHIFT12
+/* Secondary bus number offset in config space */
+#define PCI_SECONDARY_BUS  0x19
+
+/* system control */
+#define STG_SYSCON_K_RP_NEP_MASK   BIT(8)
+#define STG_SYSCON_AXI4_SLVL_ARFUNC_MASK   GENMASK(22, 8)
+#define STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT  8
+#define STG_SYSCON_AXI4_SLVL_AWFUNC_MASK   GENMASK(14, 0)
+#define STG_SYSCON_CLKREQ_MASK BIT(22)
+#define STG_SYSCON_CKREF_SRC_SHIFT 18
+#define STG_SYSCON_CKREF_SRC_MASK  GENMASK(19, 18)
+
+struct starfive_pcie {
+   struct udevice *dev;
+
+   void __iomem *reg_base;
+   void __iomem *cfg_base;
+
+   struct regmap *regmap;
+   u32 stg_arfun;
+   u32 stg_awfun;
+   u32 stg_rp_nep;
+
+   struct clk_bulk clks;
+   struct reset_ctl_bulk   rsts;
+
+   int atr_table_num;
+   int first_busno;
+};
+
+static int starfive_pcie_addr_valid(pci_dev_t bdf, int first_busno)
+{
+   if ((PCI_BUS(bdf) == first_busno) && (PCI_DEV(bdf) > 0))
+   return 0;
+   if ((PCI_BUS(bdf) == first_busno + 1) && (PCI_DEV(bdf) > 0))
+   return 0;
+
+   return 1;
+}
+
+static int starfive_pcie_off

Re: [PATCH v2 1/3] starfive: pci: Add StarFive JH7110 pcie driver

[Minda Chen]

On 2023/3/8 15:31, Pali Rohár wrote:
> Hello! See few comments below.
> 
> On Wednesday 08 March 2023 13:48:31 Minda Chen wrote:
>> From: Mason Huo 
>> 
>> Add pcie driver for StarFive JH7110, the driver depends on
>> starfive gpio, pinctrl, clk and reset driver to do init.
>> 
>> Several devices are tested:
>> a) M.2 NVMe SSD
>> b) Realtek 8169 Ethernet adapter.
>> 
>> Signed-off-by: Mason Huo 
>> Signed-off-by: Minda Chen 
>> ---
>>  drivers/pci/Kconfig|  11 +
>>  drivers/pci/Makefile   |   1 +
>>  drivers/pci/pcie_starfive_jh7110.c | 478 +
>>  3 files changed, 490 insertions(+)
>>  create mode 100644 drivers/pci/pcie_starfive_jh7110.c
>> 
>> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
>> index ef328d2652..e7b0ff5bc3 100644
>> --- a/drivers/pci/Kconfig
>> +++ b/drivers/pci/Kconfig
>> @@ -374,4 +374,15 @@ config PCIE_UNIPHIER
>>Say Y here if you want to enable PCIe controller support on
>>UniPhier SoCs.
>>  
>> +config PCIE_STARFIVE_JH7110
>> +bool "Enable Starfive JH7110 PCIe driver"
>> +depends on STARFIVE_JH7110
>> +depends on PINCTRL_STARFIVE_JH7110
>> +depends on CLK_JH7110
>> +depends on RESET_JH7110
>> +default y
>> +help
>> +  Say Y here if you want to enable PCIe controller support on
>> +  StarFive JH7110 SoC.
>> +
>>  endif
>> diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
>> index 49506e7ba5..bbe3323bb5 100644
>> --- a/drivers/pci/Makefile
>> +++ b/drivers/pci/Makefile
>> @@ -49,3 +49,4 @@ obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o
>>  obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o
>>  obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o
>>  obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o
>> +obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o
>> diff --git a/drivers/pci/pcie_starfive_jh7110.c 
>> b/drivers/pci/pcie_starfive_jh7110.c
>> new file mode 100644
>> index 00..5ccef1ef02
>> --- /dev/null
>> +++ b/drivers/pci/pcie_starfive_jh7110.c
>> @@ -0,0 +1,478 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * StarFive PLDA PCIe host controller driver
>> + *
>> + * Copyright (c) 2023 Starfive, Inc.
>> + * Author: Mason Huo 
>> + *
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +#define GEN_SETTINGS0x80
>> +#define PCIE_PCI_IDS0x9C
>> +#define PCIE_WINROM 0xFC
>> +#define PMSG_SUPPORT_RX 0x3F0
>> +#define PCI_MISC0xB4
>> +
>> +#define PLDA_EP_ENABLE  0
>> +#define PLDA_RP_ENABLE  1
>> +
>> +#define IDS_REVISION_ID 0x02
>> +#define IDS_PCI_TO_PCI_BRIDGE   0x060400
>> +#define IDS_CLASS_CODE_SHIFT8
> 
> Please do not duplicate standard PCI macros and constants. In U-Boot
> they are already available in include/pci_ids.h header file.
> 
ok
>> +#define PREF_MEM_WIN_64_SUPPORT BIT(3)
>> +#define PMSG_LTR_SUPPORTBIT(2)
>> +#define PLDA_FUNCTION_DIS   BIT(15)
>> +#define PLDA_FUNC_NUM   4
>> +#define PLDA_PHY_FUNC_SHIFT 9
>> +
>> +#define XR3PCI_ATR_AXI4_SLV00x800
>> +#define XR3PCI_ATR_SRC_ADDR_LOW 0x0
>> +#define XR3PCI_ATR_SRC_ADDR_HIGH0x4
>> +#define XR3PCI_ATR_TRSL_ADDR_LOW0x8
>> +#define XR3PCI_ATR_TRSL_ADDR_HIGH   0xc
>> +#define XR3PCI_ATR_TRSL_PARAM   0x10
>> +#define XR3PCI_ATR_TABLE_OFFSET 0x20
>> +#define XR3PCI_ATR_MAX_TABLE_NUM8
>> +
>> +#define XR3PCI_ATR_SRC_WIN_SIZE_SHIFT   1
>> +#define XR3PCI_ATR_SRC_ADDR_MASKGENMASK(31, 12)
>> +#define XR3PCI_ATR_TRSL_ADDR_MASK   GENMASK(31, 12)
>> +#define XR3_PCI_ECAM_SIZE   28
>> +#define XR3PCI_ATR_TRSL_DIR BIT(22)
>> +/* IDs used in the XR3PCI_ATR_TRSL_PARAM */
>> +#define XR3PCI_ATR_TRSLID_PCIE_MEMORY   0x0
>> +#define XR3PCI_ATR_TRSLID_PCIE_CONFIG   0x1
>> +
>> +#define ECA

Re: [PATCH v2 1/3] starfive: pci: Add StarFive JH7110 pcie driver

[Minda Chen]

On 2023/3/11 1:42, Pali Rohár wrote:
> On Friday 10 March 2023 18:36:44 Minda Chen wrote:
>> On 2023/3/8 15:31, Pali Rohár wrote:
>> > Hello! See few comments below.
>> > 
>> > On Wednesday 08 March 2023 13:48:31 Minda Chen wrote:
>> >> From: Mason Huo 
>> >> 
>> >> Add pcie driver for StarFive JH7110, the driver depends on
>> >> starfive gpio, pinctrl, clk and reset driver to do init.
>> >> 
>> >> Several devices are tested:
>> >> a) M.2 NVMe SSD
>> >> b) Realtek 8169 Ethernet adapter.
>> >> 
>> >> Signed-off-by: Mason Huo 
>> >> Signed-off-by: Minda Chen 
>> >> ---
>> >>  drivers/pci/Kconfig|  11 +
>> >>  drivers/pci/Makefile   |   1 +
>> >>  drivers/pci/pcie_starfive_jh7110.c | 478 +
>> >>  3 files changed, 490 insertions(+)
>> >>  create mode 100644 drivers/pci/pcie_starfive_jh7110.c
>> >> 
>> >> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
>> >> index ef328d2652..e7b0ff5bc3 100644
>> >> --- a/drivers/pci/Kconfig
>> >> +++ b/drivers/pci/Kconfig
>> >> @@ -374,4 +374,15 @@ config PCIE_UNIPHIER
>> >> Say Y here if you want to enable PCIe controller support on
>> >> UniPhier SoCs.
>> >>  
>> >> +config PCIE_STARFIVE_JH7110
>> >> + bool "Enable Starfive JH7110 PCIe driver"
>> >> + depends on STARFIVE_JH7110
>> >> + depends on PINCTRL_STARFIVE_JH7110
>> >> + depends on CLK_JH7110
>> >> + depends on RESET_JH7110
>> >> + default y
>> >> + help
>> >> +   Say Y here if you want to enable PCIe controller support on
>> >> +   StarFive JH7110 SoC.
>> >> +
>> >>  endif
>> >> diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
>> >> index 49506e7ba5..bbe3323bb5 100644
>> >> --- a/drivers/pci/Makefile
>> >> +++ b/drivers/pci/Makefile
>> >> @@ -49,3 +49,4 @@ obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o
>> >>  obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o
>> >>  obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o
>> >>  obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o
>> >> +obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o
>> >> diff --git a/drivers/pci/pcie_starfive_jh7110.c 
>> >> b/drivers/pci/pcie_starfive_jh7110.c
>> >> new file mode 100644
>> >> index 00..5ccef1ef02
>> >> --- /dev/null
>> >> +++ b/drivers/pci/pcie_starfive_jh7110.c
>> >> @@ -0,0 +1,478 @@
>> >> +// SPDX-License-Identifier: GPL-2.0+
>> >> +/*
>> >> + * StarFive PLDA PCIe host controller driver
>> >> + *
>> >> + * Copyright (c) 2023 Starfive, Inc.
>> >> + * Author: Mason Huo 
>> >> + *
>> >> + */
>> >> +
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +
>> >> +DECLARE_GLOBAL_DATA_PTR;
>> >> +
>> >> +#define GEN_SETTINGS 0x80
>> >> +#define PCIE_PCI_IDS 0x9C
>> >> +#define PCIE_WINROM  0xFC
>> >> +#define PMSG_SUPPORT_RX  0x3F0
>> >> +#define PCI_MISC 0xB4
>> >> +
>> >> +#define PLDA_EP_ENABLE   0
>> >> +#define PLDA_RP_ENABLE   1
>> >> +
>> >> +#define IDS_REVISION_ID  0x02
>> >> +#define IDS_PCI_TO_PCI_BRIDGE0x060400
>> >> +#define IDS_CLASS_CODE_SHIFT 8
>> > 
>> > Please do not duplicate standard PCI macros and constants. In U-Boot
>> > they are already available in include/pci_ids.h header file.
>> > 
>> ok
>> >> +#define PREF_MEM_WIN_64_SUPPORT  BIT(3)
>> >> +#define PMSG_LTR_SUPPORT BIT(2)
>> >> +#define PLDA_FUNCTION_DISBIT(15)
>> >> +#define PLDA_FUNC

Re: [PATCH v1 0/4] Fix rtl8169 compile warning and add a new device ID

[Minda Chen]

Hi Joe and Ramon

 Sorry to disturb you. Could you please review this patchset. Thanks

On 2023/6/21 17:05, Minda Chen wrote:
> StarFive JH7110 uboot support PCIe and using rtl8169 network adapter
> PCIe device. But compile warning in rtl8169 driver cause CI test fail.
> So commit this patch set to fix it, Also a new device ID to adjust the
> PCI bar regions in rtl8169.
> 
> The StarFive JH7110 PCIe driver link:
> https://patchwork.ozlabs.org/project/uboot/cover/20230509082617.119018-1-minda.c...@starfivetech.com/
> 
> patch 1 is fix make pointer from integer warning.
>  eg: /home/minda/vf2/visionfive/u-boot/drivers/net/rtl8169.c:103:52: warning:
> passing argument 2 of ‘writew’ makes pointer from integer without a cast 
> [-Wint-conversion]
> patch 2 fix RISC-V 8169 descriptor less than DMA min aligned size warning
> patch 3 add new device ID
> patch 4 enable 8169 in JH7110 SoC configs file.
> 
> Minda Chen (4):
>   net: rtl8169: Fix compile warning in rtl8169 network adapter
>   net: rtl8169: Fix DMA min aligned compile warning in riscv
>   net: rtl8169: Add one more device ID
>   configs: starfive-jh7110: Add CONFIG_RTL8169
> 
>  configs/starfive_visionfive2_defconfig |  1 +
>  drivers/net/rtl8169.c  | 22 +-
>  2 files changed, 14 insertions(+), 9 deletions(-)
> 
> 
> base-commit: 50842b217fef505a0ec6662cc2acdc55d0bb23c5

[PATCH v7 0/4] Add StarFive JH7110 PCIe drvier support

[Minda Chen]

These PCIe series patches are based on the JH7110 RISC-V SoC and VisionFive V2 
board.

The PCIe driver depends on gpio, pinctrl, clk and reset driver to do init.
The PCIe dts configuation includes all these setting.

The PCIe drivers codes has been tested on the VisionFive V2 boards.
The test devices includes M.2 NVMe SSD and Realtek 8169 Ethernet adapter.

patch1 is for fixing the compile error in designware_i2c_pci.c
while enable designware i2c and PCI.

previous patch version

v1: 
https://patchwork.ozlabs.org/project/uboot/cover/20230223105240.15180-1-minda.c...@starfivetech.com/
v2: 
https://patchwork.ozlabs.org/project/uboot/cover/20230308054833.95730-1-minda.c...@starfivetech.com/
v3: 
https://patchwork.ozlabs.org/project/uboot/cover/20230329100143.10724-1-minda.c...@starfivetech.com/
v4: 
https://patchwork.ozlabs.org/project/uboot/cover/20230411010209.76561-1-minda.c...@starfivetech.com/
v5: 
https://patchwork.ozlabs.org/project/uboot/cover/20230423105859.125764-1-minda.c...@starfivetech.com/
v6: 
https://patchwork.ozlabs.org/project/uboot/cover/20230509082617.119018-1-minda.c...@starfivetech.com/

changes
  v7
   Add patch1 to fix compiling error while enable PCI.
   patch 2 and patch 3 rebase to latest mainline codes.

  v6
   patch 3
1. Change one VisionFive2 config file.
   patch 4
1. remove the pcie interrupt-controller. interrupts setting revert to 
origin.

setting.
  v5
   patch 2
1. split PLDA controller driver codes to pcie_plda_common.c
2. correct the codes of record secondary number. 
   patch 4
1. change the pcie dtsi config. make them the same with kernel.
 
  v4
   patch 2
1. Remove the IDS_REVISION_ID macros.
2. Replace sec_busno to first_busno in starfive_pcie
3. Remove starfive_pcie_off_conf function.
4. Replace "imply" to "depends on" in PCIe Kconfig.
5 .Check sec_busno in starfive_pcie_addr_valid.
 
  v3
   patch 2
1. remove the read vendor ID delay
2. remove starfive_pcie_hide_rc_bar function. do not hide host
bridge BAR write.
3. Using PCIE_ECAM_OFFSET and PCI_CLASS_BRIDGE_PCI_NORMAL macros.
4. Add comments for bus and address limitation reason in function
   starfive_pcie_addr_valid
5. Change the multiple line comments in Line 373
6. Using gpio_request_by_name to get PCIe reset gpio,and using
   dm_gpio_set_value set GPIO value.
  patch 3
1. support PCIeboth 12a and 13b vf2 board.  
  patch 4
1. reset dts change to reset-gpio.

  v2
   1. remove clock commit. The pcie clocks change has been includeded in [1].
   2. Using GENMASK marco1 in patch1.
   3. remove the syscon dts node in patch3. The syscon dts dts node has been
  included in [1]. 


Mason Huo (3):
  starfive: pci: Add StarFive JH7110 pcie driver
  configs: starfive-jh7110: Add support for PCIe host driver
  riscv: dts: starfive: Enable PCIe host controller

Minda Chen (1):
  i2c: designware: Add CONFIG_ACPIGEN limitation to designware_i2c_pci.c

 .../dts/jh7110-starfive-visionfive-2.dtsi |  11 +
 arch/riscv/dts/jh7110.dtsi|  74 
 configs/starfive_visionfive2_defconfig|   8 +
 drivers/i2c/Makefile  |   2 +
 drivers/pci/Kconfig   |  13 +
 drivers/pci/Makefile  |   2 +
 drivers/pci/pcie_plda_common.c| 116 +++
 drivers/pci/pcie_plda_common.h| 118 +++
 drivers/pci/pcie_starfive_jh7110.c| 317 ++
 9 files changed, 661 insertions(+)
 create mode 100644 drivers/pci/pcie_plda_common.c
 create mode 100644 drivers/pci/pcie_plda_common.h
 create mode 100644 drivers/pci/pcie_starfive_jh7110.c


base-commit: e6e67bb9e0a40f3eb3c87d16935192821987c3e0
-- 
2.17.1

[PATCH v7 3/4] configs: starfive-jh7110: Add support for PCIe host driver

[Minda Chen]

From: Mason Huo 

Add PCIe host driver and nvme driver in configure file.

Signed-off-by: Mason Huo 
Signed-off-by: Minda Chen 
---
 configs/starfive_visionfive2_defconfig | 8 
 1 file changed, 8 insertions(+)

diff --git a/configs/starfive_visionfive2_defconfig 
b/configs/starfive_visionfive2_defconfig
index 570a1f53a1..59e39c6f9b 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -19,6 +19,8 @@ CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
 CONFIG_SYS_LOAD_ADDR=0x8200
+CONFIG_SYS_PCI_64BIT=y
+CONFIG_PCI=y
 CONFIG_TARGET_STARFIVE_VISIONFIVE2=y
 CONFIG_SPL_OPENSBI_LOAD_ADDR=0x4000
 CONFIG_ARCH_RV64I=y
@@ -62,6 +64,7 @@ CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
 CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_I2C=y
+CONFIG_CMD_PCI=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_OF_BOARD=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
@@ -92,6 +95,11 @@ CONFIG_DWC_ETH_QOS=y
 CONFIG_DWC_ETH_QOS_STARFIVE=y
 CONFIG_RGMII=y
 CONFIG_RMII=y
+CONFIG_NVME_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+# CONFIG_PCI_PNP is not set
+CONFIG_PCI_REGION_MULTI_ENTRY=y
+CONFIG_PCIE_STARFIVE_JH7110=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_SPL_PINCTRL=y
-- 
2.17.1

[PATCH v7 4/4] riscv: dts: starfive: Enable PCIe host controller

[Minda Chen]

From: Mason Huo 

Enable and add pinctrl configuration for PCIe host controller.

Signed-off-by: Mason Huo 
Signed-off-by: Minda Chen 
---
 .../dts/jh7110-starfive-visionfive-2.dtsi | 11 +++
 arch/riscv/dts/jh7110.dtsi| 74 +++
 2 files changed, 85 insertions(+)

diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi 
b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index 710b082766..54a147c7d0 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -7,6 +7,7 @@
 
 #include "jh7110.dtsi"
 #include 
+#include 
 / {
aliases {
serial0 = &uart0;
@@ -308,6 +309,16 @@
};
 };
 
+&pcie0 {
+   reset-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
+   status = "disabled";
+};
+
+&pcie1 {
+   reset-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;
+   status = "okay";
+};
+
 &syscrg {
assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
  <&syscrg JH7110_SYSCLK_BUS_ROOT>,
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index 58e332e9d7..72d0251da6 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -638,5 +638,79 @@
gpio-controller;
#gpio-cells = <2>;
};
+
+   pcie0: pcie@2b00 {
+   compatible = "starfive,jh7110-pcie";
+   reg = <0x0 0x2b00 0x0 0x100
+  0x9 0x4000 0x0 0x1000>;
+   reg-names = "reg", "config";
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   ranges = <0x8200  0x0 0x3000  0x0 0x3000 
0x0 0x0800>,
+<0xc300  0x9 0x  0x9 0x 
0x0 0x4000>;
+   interrupts = <56>;
+   interrupt-parent = <&plic>;
+   interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+   interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
+   <0x0 0x0 0x0 0x2 &plic 0x2>,
+   <0x0 0x0 0x0 0x3 &plic 0x3>,
+   <0x0 0x0 0x0 0x4 &plic 0x4>;
+   msi-parent = <&plic>;
+   device_type = "pci";
+   starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 
0x1b8>;
+   bus-range = <0x0 0xff>;
+   clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
+<&stgcrg JH7110_STGCLK_PCIE0_TL>,
+<&stgcrg JH7110_STGCLK_PCIE0_AXI>,
+<&stgcrg JH7110_STGCLK_PCIE0_APB>;
+   clock-names = "noc", "tl", "axi", "apb";
+   resets = <&stgcrg JH7110_STGRST_PCIE0_MST0>,
+<&stgcrg JH7110_STGRST_PCIE0_SLV0>,
+<&stgcrg JH7110_STGRST_PCIE0_SLV>,
+<&stgcrg JH7110_STGRST_PCIE0_BRG>,
+<&stgcrg JH7110_STGRST_PCIE0_CORE>,
+<&stgcrg JH7110_STGRST_PCIE0_APB>;
+   reset-names = "mst0", "slv0", "slv", "brg",
+ "core", "apb";
+   status = "disabled";
+   };
+
+   pcie1: pcie@2c00 {
+   compatible = "starfive,jh7110-pcie";
+   reg = <0x0 0x2c00 0x0 0x100
+  0x9 0xc000 0x0 0x1000>;
+   reg-names = "reg", "config";
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   ranges = <0x8200  0x0 0x3800  0x0 0x3800 
0x0 0x0800>,
+<0xc300  0x9 0x8000  0x9 0x8000 
0x0 0x4000>;
+   interrupts = <57>;
+   interrupt-parent = <&plic>;
+   interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+   interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
+   <0x0 0x

[PATCH v7 1/4] i2c: designware: Add CONFIG_ACPIGEN limitation to designware_i2c_pci.c

[Minda Chen]

As the designware_i2c_pci.c uses ACPI APIs, If some SoCs (StarFive
JH7110) contain designware i2c and PCI but do not use ACPI,
This file will be can't be compiled. So add ACPIGEN to
designware_i2c_pci.c

Signed-off-by: Minda Chen 
---
 drivers/i2c/Makefile | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 99545df2e5..92b1ec6bc3 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -18,9 +18,11 @@ obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o
 obj-$(CONFIG_SYS_I2C_CA) += i2c-cortina.o
 obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
 obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o
+ifdef CONFIG_ACPIGEN
 ifdef CONFIG_PCI
 obj-$(CONFIG_SYS_I2C_DW) += designware_i2c_pci.o
 endif
+endif
 obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
 obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o
 obj-$(CONFIG_SYS_I2C_INTEL) += intel_i2c.o
-- 
2.17.1

[PATCH v7 2/4] starfive: pci: Add StarFive JH7110 pcie driver

[Minda Chen]

From: Mason Huo 

Add pcie driver for StarFive JH7110, Also add PLDA
PCIe controller common driver functions.

Several devices are tested:
a) M.2 NVMe SSD
b) Realtek 8169 Ethernet adapter.

Signed-off-by: Mason Huo 
Signed-off-by: Minda Chen 
Acked-by: Pali Rohár 
---
 drivers/pci/Kconfig|  13 ++
 drivers/pci/Makefile   |   2 +
 drivers/pci/pcie_plda_common.c | 116 +++
 drivers/pci/pcie_plda_common.h | 118 +++
 drivers/pci/pcie_starfive_jh7110.c | 317 +
 5 files changed, 566 insertions(+)
 create mode 100644 drivers/pci/pcie_plda_common.c
 create mode 100644 drivers/pci/pcie_plda_common.h
 create mode 100644 drivers/pci/pcie_starfive_jh7110.c

diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 84a2ae951f..fa21d60ce9 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -387,4 +387,17 @@ config PCIE_XILINX_NWL
 Say 'Y' here if you want support for Xilinx / AMD NWL PCIe
 controller as Root Port.
 
+config PCIE_PLDA_COMMON
+   bool
+
+config PCIE_STARFIVE_JH7110
+   bool "Enable Starfive JH7110 PCIe driver"
+   select PCIE_PLDA_COMMON
+   imply STARFIVE_JH7110
+   imply CLK_JH7110
+   imply RESET_JH7110
+   help
+ Say Y here if you want to enable PLDA XpressRich PCIe controller
+ support on StarFive JH7110 SoC.
+
 endif
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 11f60c6991..a712a317a3 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -50,3 +50,5 @@ obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o
 obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o
 obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o
 obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o
+obj-$(CONFIG_PCIE_PLDA_COMMON) += pcie_plda_common.o
+obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o
diff --git a/drivers/pci/pcie_plda_common.c b/drivers/pci/pcie_plda_common.c
new file mode 100644
index 00..005b92616a
--- /dev/null
+++ b/drivers/pci/pcie_plda_common.c
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * PLDA XpressRich PCIe host controller common functions.
+ *
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "pcie_plda_common.h"
+
+static bool plda_pcie_addr_valid(struct pcie_plda *plda, pci_dev_t bdf)
+{
+   /*
+* Single device limitation.
+* PCIe controller contain HW issue that secondary bus of
+* host bridge emumerate duplicate devices.
+* Only can access device 0 in secondary bus.
+*/
+   if (PCI_BUS(bdf) == plda->sec_busno && PCI_DEV(bdf) > 0)
+   return false;
+
+   return true;
+}
+
+static int plda_pcie_conf_address(const struct udevice *udev, pci_dev_t bdf,
+ uint offset, void **paddr)
+{
+   struct pcie_plda *priv = dev_get_priv(udev);
+   int where = PCIE_ECAM_OFFSET(PCI_BUS(bdf), PCI_DEV(bdf),
+PCI_FUNC(bdf), offset);
+
+   if (!plda_pcie_addr_valid(priv, bdf))
+   return -ENODEV;
+
+   *paddr = (void *)(priv->cfg_base + where);
+   return 0;
+}
+
+int plda_pcie_config_read(const struct udevice *udev, pci_dev_t bdf,
+ uint offset, ulong *valuep,
+ enum pci_size_t size)
+{
+   return pci_generic_mmap_read_config(udev, plda_pcie_conf_address,
+   bdf, offset, valuep, size);
+}
+
+int plda_pcie_config_write(struct udevice *udev, pci_dev_t bdf,
+  uint offset, ulong value,
+  enum pci_size_t size)
+{
+   struct pcie_plda *priv = dev_get_priv(udev);
+   int ret;
+
+   ret = pci_generic_mmap_write_config(udev, plda_pcie_conf_address,
+   bdf, offset, value, size);
+
+   /* record secondary bus number */
+   if (!ret && PCI_BUS(bdf) == dev_seq(udev) &&
+   PCI_DEV(bdf) == 0 && PCI_FUNC(bdf) == 0 &&
+   (offset == PCI_SECONDARY_BUS ||
+   (offset == PCI_PRIMARY_BUS && size != PCI_SIZE_8))) {
+   priv->sec_busno =
+   ((offset == PCI_PRIMARY_BUS) ? (value >> 8) : value) & 
0xff;
+   debug("Secondary bus number was changed to %d\n",
+ priv->sec_busno);
+   }
+   return ret;
+}
+
+int plda_pcie_set_atr_entry(struct pcie_plda *plda, phys_addr_t src_addr,
+   phys_addr_t trsl_addr, phys_size_t window_size,
+   int trsl_param)
+{
+   void __iomem *base =
+   plda->reg_base + XR3PCI_ATR_AXI4_SLV0;
+
+   /* Support AXI4 Slave 0 Address Translation Tables 0-7. */
+   if

[PATCH v2 2/4] net: rtl8169: Fix DMA minimal aligned compile warning in RISC-V

[Minda Chen]

For RISC-V architeture, hardware maintain the dcache coherency.
Software do not flush the cache. So even cache-line size larger
than descriptor size, driver can work.

Signed-off-by: Minda Chen 
---
 drivers/net/rtl8169.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c
index dcba51590d..34e4cff1e9 100644
--- a/drivers/net/rtl8169.c
+++ b/drivers/net/rtl8169.c
@@ -311,10 +311,12 @@ static unsigned char rxdata[RX_BUF_LEN];
  *
  * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause
  * the driver to allocate descriptors from a pool of non-cached memory.
+ *
+ * Hardware maintain D-cache coherency in RISC-V architecture.
  */
 #if RTL8169_DESC_SIZE < ARCH_DMA_MINALIGN
 #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
-   !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86)
+   !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86) && 
!defined(CONFIG_RISCV)
 #warning cache-line size is larger than descriptor size
 #endif
 #endif
-- 
2.17.1

[PATCH v2 1/4] net: rtl8169: Fix compile warning in rtl8169

[Minda Chen]

While compiling rtl8169.c, There are many "make pointer from
integer without a cast" compile warnings. fix them with
adding cast.

Signed-off-by: Minda Chen 
---
 drivers/net/rtl8169.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c
index 2276a465e7..dcba51590d 100644
--- a/drivers/net/rtl8169.c
+++ b/drivers/net/rtl8169.c
@@ -96,12 +96,12 @@ static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, 
-1 };
 #define TX_TIMEOUT  (6*HZ)
 
 /* write/read MMIO register. Notice: {read,write}[wl] do the necessary 
swapping */
-#define RTL_W8(reg, val8)  writeb((val8), ioaddr + (reg))
-#define RTL_W16(reg, val16)writew((val16), ioaddr + (reg))
-#define RTL_W32(reg, val32)writel((val32), ioaddr + (reg))
-#define RTL_R8(reg)readb(ioaddr + (reg))
-#define RTL_R16(reg)   readw(ioaddr + (reg))
-#define RTL_R32(reg)   readl(ioaddr + (reg))
+#define RTL_W8(reg, val8)  writeb((val8), (void *)(ioaddr + (reg)))
+#define RTL_W16(reg, val16)writew((val16), (void *)(ioaddr + (reg)))
+#define RTL_W32(reg, val32)writel((val32), (void *)(ioaddr + (reg)))
+#define RTL_R8(reg)readb((void *)(ioaddr + (reg)))
+#define RTL_R16(reg)   readw((void *)(ioaddr + (reg)))
+#define RTL_R32(reg)   readl((void *)(ioaddr + (reg)))
 
 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)(unsigned long)dev->priv, \
(pci_addr_t)(unsigned long)a)
-- 
2.17.1

[PATCH v2 4/4] configs: starfive-jh7110: Add CONFIG_RTL8169

[Minda Chen]

Add PCIe device rtl8169 net adapter driver support.

Signed-off-by: Minda Chen 
---
 configs/starfive_visionfive2_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/starfive_visionfive2_defconfig 
b/configs/starfive_visionfive2_defconfig
index 59e39c6f9b..7fc1569b59 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -95,6 +95,7 @@ CONFIG_DWC_ETH_QOS=y
 CONFIG_DWC_ETH_QOS_STARFIVE=y
 CONFIG_RGMII=y
 CONFIG_RMII=y
+CONFIG_RTL8169=y
 CONFIG_NVME_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 # CONFIG_PCI_PNP is not set
-- 
2.17.1

[PATCH v2 0/4] Fix rtl8169 compile warning and add a new device ID

[Minda Chen]

StarFive JH7110 uboot support PCIe and using rtl8169 network adapter
PCIe device. But compile warning in rtl8169 driver cause CI test fail.
So commit this patch set to fix it, Also a new device ID to adjust the
PCI bar regions in rtl8169.

The StarFive JH7110 PCIe driver link, patch 4 rely on this.
https://patchwork.ozlabs.org/project/uboot/cover/20230720112333.9255-1-minda.c...@starfivetech.com/

previous version:
[1] 
https://patchwork.ozlabs.org/project/uboot/cover/20230621090540.119313-1-minda.c...@starfivetech.com/

change:
v2: patch 1- 3 modify the commit messages.
rebase to latest mainline codes.

patch 1 is fix make pointer from integer warning.
 eg: /home/minda/vf2/visionfive/u-boot/drivers/net/rtl8169.c:103:52: warning:
passing argument 2 of ‘writew’ makes pointer from integer without a cast 
[-Wint-conversion]
patch 2 fix RISC-V 8169 descriptor less than DMA min aligned size warning
patch 3 add new device ID
patch 4 enable 8169 in JH7110 SoC configs file.

Minda Chen (4):
  net: rtl8169: Fix compile warning in rtl8169
  net: rtl8169: Fix DMA minimal aligned compile warning in RISC-V
  net: rtl8169: Add one device ID 0x8161
  configs: starfive-jh7110: Add CONFIG_RTL8169

 configs/starfive_visionfive2_defconfig |  1 +
 drivers/net/rtl8169.c  | 22 +-
 2 files changed, 14 insertions(+), 9 deletions(-)


base-commit: e6e67bb9e0a40f3eb3c87d16935192821987c3e0
-- 
2.17.1

[PATCH v2 3/4] net: rtl8169: Add one device ID 0x8161

[Minda Chen]

Add rtl8169 NIC device ID and reorder the device ID.

Signed-off-by: Minda Chen 
---
 drivers/net/rtl8169.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c
index 34e4cff1e9..963702777c 100644
--- a/drivers/net/rtl8169.c
+++ b/drivers/net/rtl8169.c
@@ -353,10 +353,11 @@ static const unsigned int rtl8169_rx_config =
 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
 
 static struct pci_device_id supported[] = {
+   { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8125) },
+   { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8161) },
{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167) },
{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168) },
{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169) },
-   { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8125) },
{}
 };
 
@@ -1051,8 +1052,9 @@ static int rtl8169_eth_probe(struct udevice *dev)
int ret;
 
switch (pplat->device) {
-   case 0x8168:
case 0x8125:
+   case 0x8161:
+   case 0x8168:
region = 2;
break;
default:
-- 
2.17.1

Re: [PATCH v7 1/4] i2c: designware: Add CONFIG_ACPIGEN limitation to designware_i2c_pci.c

[Minda Chen]

On 2023/7/21 3:42, Simon Glass wrote:
> Hi,
> 
> On Thu, 20 Jul 2023 at 05:24, Minda Chen  wrote:
>>
>> As the designware_i2c_pci.c uses ACPI APIs, If some SoCs (StarFive
>> JH7110) contain designware i2c and PCI but do not use ACPI,
>> This file will be can't be compiled. So add ACPIGEN to
>> designware_i2c_pci.c
>>
>> Signed-off-by: Minda Chen 
>> ---
>>  drivers/i2c/Makefile | 2 ++
>>  1 file changed, 2 insertions(+)
>>
>> diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
>> index 99545df2e5..92b1ec6bc3 100644
>> --- a/drivers/i2c/Makefile
>> +++ b/drivers/i2c/Makefile
>> @@ -18,9 +18,11 @@ obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o
>>  obj-$(CONFIG_SYS_I2C_CA) += i2c-cortina.o
>>  obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
>>  obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o
>> +ifdef CONFIG_ACPIGEN
> 
> You should use Kconfig to see SYS_I2C_DW depends on ACPIGEN. You might
> need a separate I2C_DW_PCI Kconfig.
> 
I think so.

I can add Kconfig like this.
config SYS_I2C_DW_PCI
bool "Designware PCI I2C Controller"
depends on SYS_I2C_DW && PCI && APIGEN
default y

> But that sounds bad to me. Why does it have to generate ACPI tables?
> It should work fine without that.
> 
designware_i2c_pci.c contain ACPI and lpss related codes.
>>  ifdef CONFIG_PCI
>>  obj-$(CONFIG_SYS_I2C_DW) += designware_i2c_pci.o
>>  endif
>> +endif
>>  obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
>>  obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o
>>  obj-$(CONFIG_SYS_I2C_INTEL) += intel_i2c.o
>> --
>> 2.17.1
>>
> 
> Regards,
> Simon

[PATCH v8 3/4] configs: starfive-jh7110: Add support for PCIe host driver

[Minda Chen]

From: Mason Huo 

Add PCIe host driver and nvme driver in configure file.

Signed-off-by: Mason Huo 
Signed-off-by: Minda Chen 
Reviewed-by: Leo Yu-Chi Liang 
---
 configs/starfive_visionfive2_defconfig | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/configs/starfive_visionfive2_defconfig 
b/configs/starfive_visionfive2_defconfig
index 570a1f53a1..ad701132fa 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -19,6 +19,8 @@ CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
 CONFIG_SYS_LOAD_ADDR=0x8200
+CONFIG_SYS_PCI_64BIT=y
+CONFIG_PCI=y
 CONFIG_TARGET_STARFIVE_VISIONFIVE2=y
 CONFIG_SPL_OPENSBI_LOAD_ADDR=0x4000
 CONFIG_ARCH_RV64I=y
@@ -62,6 +64,7 @@ CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
 CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_I2C=y
+CONFIG_CMD_PCI=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_OF_BOARD=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
@@ -92,6 +95,10 @@ CONFIG_DWC_ETH_QOS=y
 CONFIG_DWC_ETH_QOS_STARFIVE=y
 CONFIG_RGMII=y
 CONFIG_RMII=y
+CONFIG_NVME_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCI_REGION_MULTI_ENTRY=y
+CONFIG_PCIE_STARFIVE_JH7110=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_SPL_PINCTRL=y
-- 
2.17.1

[PATCH v8 2/4] starfive: pci: Add StarFive JH7110 pcie driver

[Minda Chen]

From: Mason Huo 

Add pcie driver for StarFive JH7110, Also add PLDA
PCIe controller common driver functions.

Several devices are tested:
a) M.2 NVMe SSD
b) Realtek 8169 Ethernet adapter.

Signed-off-by: Mason Huo 
Signed-off-by: Minda Chen 
Acked-by: Pali Rohár 
Reviewed-by: Leo Yu-Chi Liang 
---
 drivers/pci/Kconfig|  13 ++
 drivers/pci/Makefile   |   2 +
 drivers/pci/pcie_plda_common.c | 116 +++
 drivers/pci/pcie_plda_common.h | 118 +++
 drivers/pci/pcie_starfive_jh7110.c | 317 +
 5 files changed, 566 insertions(+)
 create mode 100644 drivers/pci/pcie_plda_common.c
 create mode 100644 drivers/pci/pcie_plda_common.h
 create mode 100644 drivers/pci/pcie_starfive_jh7110.c

diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 84a2ae951f..fa21d60ce9 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -387,4 +387,17 @@ config PCIE_XILINX_NWL
 Say 'Y' here if you want support for Xilinx / AMD NWL PCIe
 controller as Root Port.
 
+config PCIE_PLDA_COMMON
+   bool
+
+config PCIE_STARFIVE_JH7110
+   bool "Enable Starfive JH7110 PCIe driver"
+   select PCIE_PLDA_COMMON
+   imply STARFIVE_JH7110
+   imply CLK_JH7110
+   imply RESET_JH7110
+   help
+ Say Y here if you want to enable PLDA XpressRich PCIe controller
+ support on StarFive JH7110 SoC.
+
 endif
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 11f60c6991..a712a317a3 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -50,3 +50,5 @@ obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o
 obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o
 obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o
 obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o
+obj-$(CONFIG_PCIE_PLDA_COMMON) += pcie_plda_common.o
+obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o
diff --git a/drivers/pci/pcie_plda_common.c b/drivers/pci/pcie_plda_common.c
new file mode 100644
index 00..005b92616a
--- /dev/null
+++ b/drivers/pci/pcie_plda_common.c
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * PLDA XpressRich PCIe host controller common functions.
+ *
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "pcie_plda_common.h"
+
+static bool plda_pcie_addr_valid(struct pcie_plda *plda, pci_dev_t bdf)
+{
+   /*
+* Single device limitation.
+* PCIe controller contain HW issue that secondary bus of
+* host bridge emumerate duplicate devices.
+* Only can access device 0 in secondary bus.
+*/
+   if (PCI_BUS(bdf) == plda->sec_busno && PCI_DEV(bdf) > 0)
+   return false;
+
+   return true;
+}
+
+static int plda_pcie_conf_address(const struct udevice *udev, pci_dev_t bdf,
+ uint offset, void **paddr)
+{
+   struct pcie_plda *priv = dev_get_priv(udev);
+   int where = PCIE_ECAM_OFFSET(PCI_BUS(bdf), PCI_DEV(bdf),
+PCI_FUNC(bdf), offset);
+
+   if (!plda_pcie_addr_valid(priv, bdf))
+   return -ENODEV;
+
+   *paddr = (void *)(priv->cfg_base + where);
+   return 0;
+}
+
+int plda_pcie_config_read(const struct udevice *udev, pci_dev_t bdf,
+ uint offset, ulong *valuep,
+ enum pci_size_t size)
+{
+   return pci_generic_mmap_read_config(udev, plda_pcie_conf_address,
+   bdf, offset, valuep, size);
+}
+
+int plda_pcie_config_write(struct udevice *udev, pci_dev_t bdf,
+  uint offset, ulong value,
+  enum pci_size_t size)
+{
+   struct pcie_plda *priv = dev_get_priv(udev);
+   int ret;
+
+   ret = pci_generic_mmap_write_config(udev, plda_pcie_conf_address,
+   bdf, offset, value, size);
+
+   /* record secondary bus number */
+   if (!ret && PCI_BUS(bdf) == dev_seq(udev) &&
+   PCI_DEV(bdf) == 0 && PCI_FUNC(bdf) == 0 &&
+   (offset == PCI_SECONDARY_BUS ||
+   (offset == PCI_PRIMARY_BUS && size != PCI_SIZE_8))) {
+   priv->sec_busno =
+   ((offset == PCI_PRIMARY_BUS) ? (value >> 8) : value) & 
0xff;
+   debug("Secondary bus number was changed to %d\n",
+ priv->sec_busno);
+   }
+   return ret;
+}
+
+int plda_pcie_set_atr_entry(struct pcie_plda *plda, phys_addr_t src_addr,
+   phys_addr_t trsl_addr, phys_size_t window_size,
+   int trsl_param)
+{
+   void __iomem *base =
+   plda->reg_base + XR3PCI_ATR_AXI4_SLV0;
+
+   /* Support AXI4 Slave 0 Address Tr

[PATCH v8 4/4] riscv: dts: starfive: Enable PCIe host controller

[Minda Chen]

From: Mason Huo 

Enable and add pinctrl configuration for PCIe host controller.

Signed-off-by: Mason Huo 
Signed-off-by: Minda Chen 
Reviewed-by: Leo Yu-Chi Liang 
---
 .../dts/jh7110-starfive-visionfive-2.dtsi | 11 +++
 arch/riscv/dts/jh7110.dtsi| 74 +++
 2 files changed, 85 insertions(+)

diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi 
b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index 710b082766..54a147c7d0 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -7,6 +7,7 @@
 
 #include "jh7110.dtsi"
 #include 
+#include 
 / {
aliases {
serial0 = &uart0;
@@ -308,6 +309,16 @@
};
 };
 
+&pcie0 {
+   reset-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
+   status = "disabled";
+};
+
+&pcie1 {
+   reset-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;
+   status = "okay";
+};
+
 &syscrg {
assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
  <&syscrg JH7110_SYSCLK_BUS_ROOT>,
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index 58e332e9d7..72d0251da6 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -638,5 +638,79 @@
gpio-controller;
#gpio-cells = <2>;
};
+
+   pcie0: pcie@2b00 {
+   compatible = "starfive,jh7110-pcie";
+   reg = <0x0 0x2b00 0x0 0x100
+  0x9 0x4000 0x0 0x1000>;
+   reg-names = "reg", "config";
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   ranges = <0x8200  0x0 0x3000  0x0 0x3000 
0x0 0x0800>,
+<0xc300  0x9 0x  0x9 0x 
0x0 0x4000>;
+   interrupts = <56>;
+   interrupt-parent = <&plic>;
+   interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+   interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
+   <0x0 0x0 0x0 0x2 &plic 0x2>,
+   <0x0 0x0 0x0 0x3 &plic 0x3>,
+   <0x0 0x0 0x0 0x4 &plic 0x4>;
+   msi-parent = <&plic>;
+   device_type = "pci";
+   starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 
0x1b8>;
+   bus-range = <0x0 0xff>;
+   clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
+<&stgcrg JH7110_STGCLK_PCIE0_TL>,
+<&stgcrg JH7110_STGCLK_PCIE0_AXI>,
+<&stgcrg JH7110_STGCLK_PCIE0_APB>;
+   clock-names = "noc", "tl", "axi", "apb";
+   resets = <&stgcrg JH7110_STGRST_PCIE0_MST0>,
+<&stgcrg JH7110_STGRST_PCIE0_SLV0>,
+<&stgcrg JH7110_STGRST_PCIE0_SLV>,
+<&stgcrg JH7110_STGRST_PCIE0_BRG>,
+<&stgcrg JH7110_STGRST_PCIE0_CORE>,
+<&stgcrg JH7110_STGRST_PCIE0_APB>;
+   reset-names = "mst0", "slv0", "slv", "brg",
+ "core", "apb";
+   status = "disabled";
+   };
+
+   pcie1: pcie@2c00 {
+   compatible = "starfive,jh7110-pcie";
+   reg = <0x0 0x2c00 0x0 0x100
+  0x9 0xc000 0x0 0x1000>;
+   reg-names = "reg", "config";
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   ranges = <0x8200  0x0 0x3800  0x0 0x3800 
0x0 0x0800>,
+<0xc300  0x9 0x8000  0x9 0x8000 
0x0 0x4000>;
+   interrupts = <57>;
+   interrupt-parent = <&plic>;
+   interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+   interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
+ 

[PATCH v8 1/4] i2c: designware: Add Kconfig for designware_i2c_pci.c

[Minda Chen]

As the Designware_i2c_pci.c uses ACPI APIs, If some SoCs (StarFive
JH7110) contain Designware i2c and PCI but do not use ACPI,
This file will be can't be compiled. So add a new Kconfig for
designware_i2c_pci.c, which depends on ACPIGEN

Signed-off-by: Minda Chen 
---
 drivers/i2c/Kconfig  | 9 +
 drivers/i2c/Makefile | 4 +---
 2 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 5e81698143..4c76fd7e41 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -231,6 +231,15 @@ config SYS_I2C_DW
  controller is used in various SoCs, e.g. the ST SPEAr, Altera
  SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs.
 
+config SYS_I2C_DW_PCI
+   bool "Designware PCI I2C Controller"
+   depends on SYS_I2C_DW && PCI && ACPIGEN
+   default y
+   help
+ Say yes here to select the Designware PCI I2C Host Controller.
+ This PCI I2C controller is the base on Desigware I2C host
+ controller.
+
 config SYS_I2C_AST2600
 bool "AST2600 I2C Controller"
 depends on DM_I2C && ARCH_ASPEED
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 99545df2e5..d5b85f398d 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -18,9 +18,7 @@ obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o
 obj-$(CONFIG_SYS_I2C_CA) += i2c-cortina.o
 obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
 obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o
-ifdef CONFIG_PCI
-obj-$(CONFIG_SYS_I2C_DW) += designware_i2c_pci.o
-endif
+obj-$(CONFIG_SYS_I2C_DW_PCI) += designware_i2c_pci.o
 obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
 obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o
 obj-$(CONFIG_SYS_I2C_INTEL) += intel_i2c.o
-- 
2.17.1

[PATCH v7 0/4] Add StarFive JH7110 PCIe drvier support

[Minda Chen]

These PCIe series patches are based on the JH7110 RISC-V SoC and VisionFive V2 
board.

The PCIe driver depends on gpio, pinctrl, clk and reset driver to do init.
The PCIe dts configuation includes all these setting.

The PCIe drivers codes has been tested on the VisionFive V2 boards.
The test devices includes M.2 NVMe SSD and Realtek 8169 Ethernet adapter.

patch1 is for fixing the compile error in designware_i2c_pci.c
while enable designware i2c and PCI.

previous patch version

v1: 
https://patchwork.ozlabs.org/project/uboot/cover/20230223105240.15180-1-minda.c...@starfivetech.com/
v2: 
https://patchwork.ozlabs.org/project/uboot/cover/20230308054833.95730-1-minda.c...@starfivetech.com/
v3: 
https://patchwork.ozlabs.org/project/uboot/cover/20230329100143.10724-1-minda.c...@starfivetech.com/
v4: 
https://patchwork.ozlabs.org/project/uboot/cover/20230411010209.76561-1-minda.c...@starfivetech.com/
v5: 
https://patchwork.ozlabs.org/project/uboot/cover/20230423105859.125764-1-minda.c...@starfivetech.com/
v6: 
https://patchwork.ozlabs.org/project/uboot/cover/20230509082617.119018-1-minda.c...@starfivetech.com/
v7: 
https://patchwork.ozlabs.org/project/uboot/cover/20230720112333.9255-1-minda.c...@starfivetech.com/

changes
  v8
   patch1: Add Kconfig for designware_i2c_pci.c

  v7
   Add patch1 to fix compiling error while enable PCI.
   patch 2 and patch 3 rebase to latest mainline codes.

  v6
   patch 3
1. Change one VisionFive2 config file.
   patch 4
1. remove the pcie interrupt-controller. interrupts setting revert to 
origin.

setting.
  v5
   patch 2
1. split PLDA controller driver codes to pcie_plda_common.c
2. correct the codes of record secondary number. 
   patch 4
1. change the pcie dtsi config. make them the same with kernel.
 
  v4
   patch 2
1. Remove the IDS_REVISION_ID macros.
2. Replace sec_busno to first_busno in starfive_pcie
3. Remove starfive_pcie_off_conf function.
4. Replace "imply" to "depends on" in PCIe Kconfig.
5 .Check sec_busno in starfive_pcie_addr_valid.
 
  v3
   patch 2
1. remove the read vendor ID delay
2. remove starfive_pcie_hide_rc_bar function. do not hide host
bridge BAR write.
3. Using PCIE_ECAM_OFFSET and PCI_CLASS_BRIDGE_PCI_NORMAL macros.
4. Add comments for bus and address limitation reason in function
   starfive_pcie_addr_valid
5. Change the multiple line comments in Line 373
6. Using gpio_request_by_name to get PCIe reset gpio,and using
   dm_gpio_set_value set GPIO value.
  patch 3
1. support PCIeboth 12a and 13b vf2 board.  
  patch 4
1. reset dts change to reset-gpio.

  v2
   1. remove clock commit. The pcie clocks change has been includeded in [1].
   2. Using GENMASK marco1 in patch1.
   3. remove the syscon dts node in patch3. The syscon dts dts node has been
  included in [1]. 


Mason Huo (3):
  starfive: pci: Add StarFive JH7110 pcie driver
  configs: starfive-jh7110: Add support for PCIe host driver
  riscv: dts: starfive: Enable PCIe host controller

Minda Chen (1):
  i2c: designware: Add Kconfig for designware_i2c_pci.c

 .../dts/jh7110-starfive-visionfive-2.dtsi |  11 +
 arch/riscv/dts/jh7110.dtsi|  74 
 configs/starfive_visionfive2_defconfig|   7 +
 drivers/i2c/Kconfig   |   9 +
 drivers/i2c/Makefile  |   4 +-
 drivers/pci/Kconfig   |  13 +
 drivers/pci/Makefile  |   2 +
 drivers/pci/pcie_plda_common.c| 116 +++
 drivers/pci/pcie_plda_common.h| 118 +++
 drivers/pci/pcie_starfive_jh7110.c| 317 ++
 10 files changed, 668 insertions(+), 3 deletions(-)
 create mode 100644 drivers/pci/pcie_plda_common.c
 create mode 100644 drivers/pci/pcie_plda_common.h
 create mode 100644 drivers/pci/pcie_starfive_jh7110.c


base-commit: e6e67bb9e0a40f3eb3c87d16935192821987c3e0
-- 
2.17.1

[PATCH v1] usb: xhci: Check return value of wait for TRB_TRANSFER event

[Minda Chen]

xhci_wait_for_event() waiting TRB_TRANSFER event may return
NULL. Checking the return value to avoid crash.

Signed-off-by: Minda Chen 
---
 drivers/usb/host/xhci-ring.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
index c8260cbdf9..5f02ff0769 100644
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -544,6 +544,8 @@ static void abort_td(struct usb_device *udev, int ep_index)
xhci_queue_command(ctrl, 0, udev->slot_id, ep_index, TRB_STOP_RING);
 
event = xhci_wait_for_event(ctrl, TRB_TRANSFER);
+   if (!event)
+   return;
field = le32_to_cpu(event->trans_event.flags);
BUG_ON(TRB_TO_SLOT_ID(field) != udev->slot_id);
BUG_ON(TRB_TO_EP_INDEX(field) != ep_index);
-- 
2.17.1

Re: [PATCH v1] usb: xhci: Check return value of wait for TRB_TRANSFER event

[Minda Chen]

On 2023/10/17 19:20, Marek Vasut wrote:
> On 10/17/23 08:20, Minda Chen wrote:
>> xhci_wait_for_event() waiting TRB_TRANSFER event may return
>> NULL. Checking the return value to avoid crash.
>>
>> Signed-off-by: Minda Chen 
> 
> How did you trigger this error ? Is there a reproducer ? Details please ...

While Scanning a lenovo usb2.0 udisk， not 100 % reproduce

This is log.

StarFive # usb reset
resetting USB...
Bus xhci_pci: Register 5000420 NbrPorts 5
Starting the controller
USB XHCI 1.00
scanning bus xhci_pci for devices... WARN halted endpoint, queueing URB anyway.
Unexpected XHCI event TRB, skipping... (f77141f0  1300 02008401)
Unhandled exception: Load access fault
EPC: f7f563c6 RA: f7f563c6 TVAL: 000c
EPC: 4024a3c6 RA: 4024a3c6 reloc adjusted

SP:  f76f9a60 GP:  f76fbdd0 TP:  0001
T0:  f76fa168 T1:  00ff T2:  0016
S0:  f7712fc0 S1:  f76fb100 A0:  
A1:   A2:  f77145d0 A3:  f7714590
A4:   A5:  0020 A6:  000f
A7:  0100 S2:   S3:  
S4:  f7717050 S5:  f7717050 S6:  8383
S7:  f76f9dc0 S8:  00ff S9:  0001
S10: f76f9ba0 S11: 00010c04 T3:  0010
T4:  0006 T5:  0080 T6:  f76fa231

Code: 842a f0ef d75f 0593 0200 8522 f0ef ebdf (455c) 


This is USB info and storage info 

StarFive # 
1: Hub,  USB Revision 3.0
 - U-Boot XHCI Host Controller 
 - Class: Hub
 - PacketSize: 512  Configurations: 1
 - Vendor: 0x  Product 0x Version 1.0
   Configuration: 1
   - Interfaces: 1 Self Powered 0mA
 Interface: 0
 - Alternate Setting 0, Endpoints: 1
 - Class Hub
 - Endpoint 1 In Interrupt MaxPacket 8 Interval 255ms

2: Hub,  USB Revision 2.10
 -  USB2.0 Hub 
 - Class: Hub
 - PacketSize: 64  Configurations: 1
 - Vendor: 0x2109  Product 0x3431 Version 4.32
   Configuration: 1
   - Interfaces: 1 Self Powered Remote Wakeup 100mA
 Interface: 0
 - Alternate Setting 0, Endpoints: 1
 - Class Hub
 - Endpoint 1 In Interrupt MaxPacket 1 Interval 12ms

3: Mass Storage,  USB Revision 2.0
 - Generic Mass Storage 31097778XB15113405
 - Class: (from Interface) Mass Storage
 - PacketSize: 64  Configurations: 1
 - Vendor: 0x17ef  Product 0x38ac Version 1.0
   Configuration: 1
   - Interfaces: 1 Bus Powered 200mA
 Interface: 0
 - Alternate Setting 0, Endpoints: 2
 - Class Mass Storage, Transp. SCSI, Bulk only
 - Endpoint 1 Out Bulk MaxPacket 512
 - Endpoint 2 In Bulk MaxPacket 512

StarFive # usb storage
  Device 0: Vendor:  Rev: 8.07 Prod: Lenovo SX1 64G  
Type: Removable Hard Disk
Capacity: 6.0 MB = 58.5 GB (12288 x 512)
StarFive # 

Re: [PATCH v1] usb: xhci: Check return value of wait for TRB_TRANSFER event

[Minda Chen]

On 2023/10/18 10:35, Marek Vasut wrote:
> On 10/18/23 03:22, Minda Chen wrote:
>>
>>
>> On 2023/10/17 19:20, Marek Vasut wrote:
>>> On 10/17/23 08:20, Minda Chen wrote:
>>>> xhci_wait_for_event() waiting TRB_TRANSFER event may return
>>>> NULL. Checking the return value to avoid crash.
>>>>
>>>> Signed-off-by: Minda Chen 
>>>
>>> How did you trigger this error ? Is there a reproducer ? Details please ...
>>
>> While Scanning a lenovo usb2.0 udisk， not 100 % reproduce
> 
> Can you include Linux
> 
> lsusb -vvv
> 
> output for this device and include that information in the commit message ? 
> (or the U-Boot info below, that works too, just please add it into the commit 
> message, it is important for future reference).
> 
OK， I will add lsusb -vvv Linux udisk message and crash dump info to commit 
message
>> This is log.
>>
>> StarFive # usb reset
>> resetting USB...
>> Bus xhci_pci: Register 5000420 NbrPorts 5
>> Starting the controller
>> USB XHCI 1.00
>> scanning bus xhci_pci for devices... WARN halted endpoint, queueing URB 
>> anyway.
>> Unexpected XHCI event TRB, skipping... (f77141f0  1300 02008401)
>> Unhandled exception: Load access fault
>> EPC: f7f563c6 RA: f7f563c6 TVAL: 000c
>> EPC: 4024a3c6 RA: 4024a3c6 reloc adjusted
> 
> Where does the crash point to in code, can you disassemble the PC pointer ? 
> (or maybe you can use scripts/decodecode I think)
> 
OK， I will add EPC pointer disassemble  to commit message
>> SP:  f76f9a60 GP:  f76fbdd0 TP:  0001
>> T0:  f76fa168 T1:  00ff T2:  0016
>> S0:  f7712fc0 S1:  f76fb100 A0:  
>> A1:   A2:  f77145d0 A3:  f7714590
>> A4:   A5:  0020 A6:  000f
>> A7:  0100 S2:   S3:  
>> S4:  f7717050 S5:  f7717050 S6:  8383
>> S7:  f76f9dc0 S8:  00ff S9:  0001
>> S10: f76f9ba0 S11: 00010c04 T3:  0010
>> T4:  0006 T5:  0080 T6:  f76fa231
> 
> [...]
> 
>> 3: Mass Storage,  USB Revision 2.0
>>   - Generic Mass Storage 31097778XB15113405
>>   - Class: (from Interface) Mass Storage
>>   - PacketSize: 64  Configurations: 1
>>   - Vendor: 0x17ef  Product 0x38ac Version 1.0
>>     Configuration: 1
>>     - Interfaces: 1 Bus Powered 200mA
>>   Interface: 0
>>   - Alternate Setting 0, Endpoints: 2
>>   - Class Mass Storage, Transp. SCSI, Bulk only
>>   - Endpoint 1 Out Bulk MaxPacket 512
>>   - Endpoint 2 In Bulk MaxPacket 512
>>
>> StarFive # usb storage
>>    Device 0: Vendor:  Rev: 8.07 Prod: Lenovo SX1 64G
>>  Type: Removable Hard Disk
>>  Capacity: 6.0 MB = 58.5 GB (12288 x 512)
> 
> [...]

Re: [PATCH v1] usb: xhci: Check return value of wait for TRB_TRANSFER event

[Minda Chen]

On 2023/10/18 18:11, Marek Vasut wrote:
> On 10/18/23 05:46, Minda Chen wrote:
>>
>>
>> On 2023/10/18 10:35, Marek Vasut wrote:
>>> On 10/18/23 03:22, Minda Chen wrote:
>>>>
>>>>
>>>> On 2023/10/17 19:20, Marek Vasut wrote:
>>>>> On 10/17/23 08:20, Minda Chen wrote:
>>>>>> xhci_wait_for_event() waiting TRB_TRANSFER event may return
>>>>>> NULL. Checking the return value to avoid crash.
>>>>>>
>>>>>> Signed-off-by: Minda Chen 
>>>>>
>>>>> How did you trigger this error ? Is there a reproducer ? Details please 
>>>>> ...
>>>>
>>>> While Scanning a lenovo usb2.0 udisk， not 100 % reproduce
>>>
>>> Can you include Linux
>>>
>>> lsusb -vvv
>>>
>>> output for this device and include that information in the commit message ? 
>>> (or the U-Boot info below, that works too, just please add it into the 
>>> commit message, it is important for future reference).
>>>
>> OK， I will add lsusb -vvv Linux udisk message and crash dump info to commit 
>> message
> 
> Thank you
> 
>>>> This is log.
>>>>
>>>> StarFive # usb reset
>>>> resetting USB...
>>>> Bus xhci_pci: Register 5000420 NbrPorts 5
>>>> Starting the controller
>>>> USB XHCI 1.00
>>>> scanning bus xhci_pci for devices... WARN halted endpoint, queueing URB 
>>>> anyway.
>>>> Unexpected XHCI event TRB, skipping... (f77141f0  1300 
>>>> 02008401)
>>>> Unhandled exception: Load access fault
>>>> EPC: f7f563c6 RA: f7f563c6 TVAL: 000c
>>>> EPC: 4024a3c6 RA: 4024a3c6 reloc adjusted
>>>
>>> Where does the crash point to in code, can you disassemble the PC pointer ? 
>>> (or maybe you can use scripts/decodecode I think)
>>>
>> OK， I will add EPC pointer disassemble  to commit message
> 
> This part probably doesn't need to be in the commit message. I'd like to know 
> where the crash occurred in the code.


4024a376 :
{
4024a376:   7179addisp,sp,-48
4024a378:   f406sd  ra,40(sp)
4024a37a:   f022sd  s0,32(sp)
4024a37c:   ec26sd  s1,24(sp)
4024a37e:   e84asd  s2,16(sp)
4024a380:   e44esd  s3,8(sp)
4024a382:   e052sd  s4,0(sp)
4024a384:   89aemv  s3,a1
4024a386:   84aamv  s1,a0
struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
4024a388:   8c4fe0efjal ra,4024844c 
struct xhci_ring *ring =  ctrl->devs[udev->slot_id]->eps[ep_index].ring;
4024a38c:   6785lui a5,0x1
4024a38e:   94beadd s1,s1,a5
4024a390:   9444a603lw  a2,-1724(s1)
4024a394:   00198713addia4,s3,1
4024a398:   0712sllia4,a4,0x4
4024a39a:   02061793sllia5,a2,0x20
4024a39e:   9381srlia5,a5,0x20
4024a3a0:   07c9addia5,a5,18
4024a3a2:   078esllia5,a5,0x3
4024a3a4:   97aaadd a5,a5,a0
4024a3a6:   679cld  a5,8(a5)
xhci_queue_command(ctrl, NULL, udev->slot_id, ep_index, TRB_STOP_RING);
4024a3a8:   2981sext.w  s3,s3
4024a3aa:   86cemv  a3,s3
struct xhci_ring *ring =  ctrl->devs[udev->slot_id]->eps[ep_index].ring;
4024a3ac:   97baadd a5,a5,a4
xhci_queue_command(ctrl, NULL, udev->slot_id, ep_index, TRB_STOP_RING);
4024a3ae:   4581li  a1,0
4024a3b0:   473dli  a4,15
struct xhci_ring *ring =  ctrl->devs[udev->slot_id]->eps[ep_index].ring;
4024a3b2:   0087ba03ld  s4,8(a5) # 1008 
<_start-0x401feff8>
struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
4024a3b6:   842amv  s0,a0
xhci_queue_command(ctrl, NULL, udev->slot_id, ep_index, TRB_STOP_RING);
4024a3b8:   d75ff0efjal ra,4024a12c 
event = xhci_wait_for_event(ctrl, TRB_TRANSFER);
4024a3bc:   02000593li  a1,32
4024a3c0:   8522mv  a0,s0
4024a3c2:   ebdff0efjal ra,4024a27e 

field = le32_to_cpu(event->trans_event.flags);
epc-> 4024a3c6:   455clw  a5,12(a0) 
BUG_ON(TRB_TO_SLOT_ID(field) != udev->slot_id);
4024a3c8:   9444a703lw  a4,-1724(s1)
field = le32_to_cpu(event->trans_event.flags);
4024a3cc:   0007891bsext.w  s2,a5

Re: [PATCH v1] usb: xhci: Check return value of wait for TRB_TRANSFER event

[Minda Chen]

On 2023/10/18 18:55, Marek Vasut wrote:
> On 10/18/23 12:16, Minda Chen wrote:
>>
>>
>> On 2023/10/18 18:11, Marek Vasut wrote:
>>> On 10/18/23 05:46, Minda Chen wrote:
>>>>
>>>>
>>>> On 2023/10/18 10:35, Marek Vasut wrote:
>>>>> On 10/18/23 03:22, Minda Chen wrote:
>>>>>>
>>>>>>
>>>>>> On 2023/10/17 19:20, Marek Vasut wrote:
>>>>>>> On 10/17/23 08:20, Minda Chen wrote:
>>>>>>>> xhci_wait_for_event() waiting TRB_TRANSFER event may return
>>>>>>>> NULL. Checking the return value to avoid crash.
>>>>>>>>
>>>>>>>> Signed-off-by: Minda Chen 
>>>>>>>
>>>>>>> How did you trigger this error ? Is there a reproducer ? Details please 
>>>>>>> ...
>>>>>>
>>>>>> While Scanning a lenovo usb2.0 udisk， not 100 % reproduce
>>>>>
>>>>> Can you include Linux
>>>>>
>>>>> lsusb -vvv
>>>>>
>>>>> output for this device and include that information in the commit message 
>>>>> ? (or the U-Boot info below, that works too, just please add it into the 
>>>>> commit message, it is important for future reference).
>>>>>
>>>> OK， I will add lsusb -vvv Linux udisk message and crash dump info to 
>>>> commit message
>>>
>>> Thank you
>>>
>>>>>> This is log.
>>>>>>
>>>>>> StarFive # usb reset
>>>>>> resetting USB...
>>>>>> Bus xhci_pci: Register 5000420 NbrPorts 5
>>>>>> Starting the controller
>>>>>> USB XHCI 1.00
>>>>>> scanning bus xhci_pci for devices... WARN halted endpoint, queueing URB 
>>>>>> anyway.
>>>>>> Unexpected XHCI event TRB, skipping... (f77141f0  1300 
>>>>>> 02008401)
>>>>>> Unhandled exception: Load access fault
>>>>>> EPC: f7f563c6 RA: f7f563c6 TVAL: 000c
>>>>>> EPC: 4024a3c6 RA: 4024a3c6 reloc adjusted
>>>>>
>>>>> Where does the crash point to in code, can you disassemble the PC pointer 
>>>>> ? (or maybe you can use scripts/decodecode I think)
>>>>>
>>>> OK， I will add EPC pointer disassemble  to commit message
>>>
>>> This part probably doesn't need to be in the commit message. I'd like to 
>>> know where the crash occurred in the code.
>>
>>
>> 4024a376 :
>> {
>>  4024a376:   7179    addi    sp,sp,-48
>>  4024a378:   f406    sd  ra,40(sp)
>>  4024a37a:   f022    sd  s0,32(sp)
>>  4024a37c:   ec26    sd  s1,24(sp)
>>  4024a37e:   e84a    sd  s2,16(sp)
>>  4024a380:   e44e    sd  s3,8(sp)
>>  4024a382:   e052    sd  s4,0(sp)
>>  4024a384:   89ae    mv  s3,a1
>>  4024a386:   84aa    mv  s1,a0
>>  struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
>>  4024a388:   8c4fe0ef    jal ra,4024844c 
>>  struct xhci_ring *ring =  
>> ctrl->devs[udev->slot_id]->eps[ep_index].ring;
>>  4024a38c:   6785    lui a5,0x1
>>  4024a38e:   94be    add s1,s1,a5
>>  4024a390:   9444a603    lw  a2,-1724(s1)
>>  4024a394:   00198713    addi    a4,s3,1
>>  4024a398:   0712    slli    a4,a4,0x4
>>  4024a39a:   02061793    slli    a5,a2,0x20
>>  4024a39e:   9381    srli    a5,a5,0x20
>>  4024a3a0:   07c9    addi    a5,a5,18
>>  4024a3a2:   078e    slli    a5,a5,0x3
>>  4024a3a4:   97aa    add a5,a5,a0
>>  4024a3a6:   679c    ld  a5,8(a5)
>>  xhci_queue_command(ctrl, NULL, udev->slot_id, ep_index, 
>> TRB_STOP_RING);
>>  4024a3a8:   2981    sext.w  s3,s3
>>  4024a3aa:   86ce    mv  a3,s3
>>  struct xhci_ring *ring =  
>> ctrl->devs[udev->slot_id]->eps[ep_index].ring;
>>  4024a3ac:   97ba    add a5,a5,a4
>>  

Re: [PATCH v2 1/3] starfive: pci: Add StarFive JH7110 pcie driver

[Minda Chen]

On 2023/3/24 2:19, Pali Rohár wrote:
> On Thursday 23 March 2023 18:51:38 Minda Chen wrote:
>> On 2023/3/11 1:42, Pali Rohár wrote:
>> > On Friday 10 March 2023 18:36:44 Minda Chen wrote:
>> >> On 2023/3/8 15:31, Pali Rohár wrote:
>> >> > Hello! See few comments below.
>> >> > 
>> >> > On Wednesday 08 March 2023 13:48:31 Minda Chen wrote:
>> >> >> From: Mason Huo 
>> >> >> 
>> >> >> Add pcie driver for StarFive JH7110, the driver depends on
>> >> >> starfive gpio, pinctrl, clk and reset driver to do init.
>> >> >> 
>> >> >> Several devices are tested:
>> >> >> a) M.2 NVMe SSD
>> >> >> b) Realtek 8169 Ethernet adapter.
>> >> >> 
>> >> >> Signed-off-by: Mason Huo 
>> >> >> Signed-off-by: Minda Chen 
>> >> >> ---
>> >> >>  drivers/pci/Kconfig|  11 +
>> >> >>  drivers/pci/Makefile   |   1 +
>> >> >>  drivers/pci/pcie_starfive_jh7110.c | 478 +
>> >> >>  3 files changed, 490 insertions(+)
>> >> >>  create mode 100644 drivers/pci/pcie_starfive_jh7110.c
>> >> >> 
>> >> >> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
>> >> >> index ef328d2652..e7b0ff5bc3 100644
>> >> >> --- a/drivers/pci/Kconfig
>> >> >> +++ b/drivers/pci/Kconfig
>> >> >> @@ -374,4 +374,15 @@ config PCIE_UNIPHIER
>> >> >>  Say Y here if you want to enable PCIe controller support on
>> >> >>  UniPhier SoCs.
>> >> >>  
>> >> >> +config PCIE_STARFIVE_JH7110
>> >> >> +  bool "Enable Starfive JH7110 PCIe driver"
>> >> >> +  depends on STARFIVE_JH7110
>> >> >> +  depends on PINCTRL_STARFIVE_JH7110
>> >> >> +  depends on CLK_JH7110
>> >> >> +  depends on RESET_JH7110
>> >> >> +  default y
>> >> >> +  help
>> >> >> +Say Y here if you want to enable PCIe controller support on
>> >> >> +StarFive JH7110 SoC.
>> >> >> +
>> >> >>  endif
>> >> >> diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
>> >> >> index 49506e7ba5..bbe3323bb5 100644
>> >> >> --- a/drivers/pci/Makefile
>> >> >> +++ b/drivers/pci/Makefile
>> >> >> @@ -49,3 +49,4 @@ obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o
>> >> >>  obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o
>> >> >>  obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o
>> >> >>  obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o
>> >> >> +obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o
>> >> >> diff --git a/drivers/pci/pcie_starfive_jh7110.c 
>> >> >> b/drivers/pci/pcie_starfive_jh7110.c
>> >> >> new file mode 100644
>> >> >> index 00..5ccef1ef02
>> >> >> --- /dev/null
>> >> >> +++ b/drivers/pci/pcie_starfive_jh7110.c
>> >> >> @@ -0,0 +1,478 @@
>> >> >> +// SPDX-License-Identifier: GPL-2.0+
>> >> >> +/*
>> >> >> + * StarFive PLDA PCIe host controller driver
>> >> >> + *
>> >> >> + * Copyright (c) 2023 Starfive, Inc.
>> >> >> + * Author: Mason Huo 
>> >> >> + *
>> >> >> + */
>> >> >> +
>> >> >> +#include 
>> >> >> +#include 
>> >> >> +#include 
>> >> >> +#include 
>> >> >> +#include 
>> >> >> +#include 
>> >> >> +#include 
>> >> >> +#include 
>> >> >> +#include 
>> >> >> +#include 
>> >> >> +#include 
>> >> >> +#include 
>> >> >> +#include 
>> >> >> +#include 
>> >> >> +#include 
>> >> >> +#include 
>> >> >> +#include 
>> >> >> +
>> >> >> +DECLARE_GLOBAL_DATA_PTR;
>> >> >> +
>> >> >> +#define GEN_SETTINGS  0x80
>> >> >> +#define PCIE_PCI_IDS  0x9C
>> >> >> +

Re: [PATCH v2 1/3] starfive: pci: Add StarFive JH7110 pcie driver

[Minda Chen]

On 2023/3/25 20:31, Pali Rohár wrote:
> On Friday 24 March 2023 18:57:33 Minda Chen wrote:
>> On 2023/3/24 2:19, Pali Rohár wrote:
>> > On Thursday 23 March 2023 18:51:38 Minda Chen wrote:
>> >> On 2023/3/11 1:42, Pali Rohár wrote:
>> >> > On Friday 10 March 2023 18:36:44 Minda Chen wrote:
>> >> >> On 2023/3/8 15:31, Pali Rohár wrote:
>> >> >> > Hello! See few comments below.
>> >> >> > 
>> >> >> > On Wednesday 08 March 2023 13:48:31 Minda Chen wrote:
>> >> >> >> From: Mason Huo 
>> >> >> >> 
>> >> >> >> Add pcie driver for StarFive JH7110, the driver depends on
>> >> >> >> starfive gpio, pinctrl, clk and reset driver to do init.
>> >> >> >> 
>> >> >> >> Several devices are tested:
>> >> >> >> a) M.2 NVMe SSD
>> >> >> >> b) Realtek 8169 Ethernet adapter.
>> >> >> >> 
>> >> >> >> Signed-off-by: Mason Huo 
>> >> >> >> Signed-off-by: Minda Chen 
>> >> >> >> ---
>> >> >> >>  drivers/pci/Kconfig|  11 +
>> >> >> >>  drivers/pci/Makefile   |   1 +
>> >> >> >>  drivers/pci/pcie_starfive_jh7110.c | 478 
>> >> >> >> +
>> >> >> >>  3 files changed, 490 insertions(+)
>> >> >> >>  create mode 100644 drivers/pci/pcie_starfive_jh7110.c
>> >> >> >> 
>> >> >> >> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
>> >> >> >> index ef328d2652..e7b0ff5bc3 100644
>> >> >> >> --- a/drivers/pci/Kconfig
>> >> >> >> +++ b/drivers/pci/Kconfig
>> >> >> >> @@ -374,4 +374,15 @@ config PCIE_UNIPHIER
>> >> >> >>   Say Y here if you want to enable PCIe controller support on
>> >> >> >>   UniPhier SoCs.
>> >> >> >>  
>> >> >> >> +config PCIE_STARFIVE_JH7110
>> >> >> >> +   bool "Enable Starfive JH7110 PCIe driver"
>> >> >> >> +   depends on STARFIVE_JH7110
>> >> >> >> +   depends on PINCTRL_STARFIVE_JH7110
>> >> >> >> +   depends on CLK_JH7110
>> >> >> >> +   depends on RESET_JH7110
>> >> >> >> +   default y
>> >> >> >> +   help
>> >> >> >> + Say Y here if you want to enable PCIe controller support on
>> >> >> >> + StarFive JH7110 SoC.
>> >> >> >> +
>> >> >> >>  endif
>> >> >> >> diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
>> >> >> >> index 49506e7ba5..bbe3323bb5 100644
>> >> >> >> --- a/drivers/pci/Makefile
>> >> >> >> +++ b/drivers/pci/Makefile
>> >> >> >> @@ -49,3 +49,4 @@ obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o
>> >> >> >>  obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o
>> >> >> >>  obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o
>> >> >> >>  obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o
>> >> >> >> +obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o
>> >> >> >> diff --git a/drivers/pci/pcie_starfive_jh7110.c 
>> >> >> >> b/drivers/pci/pcie_starfive_jh7110.c
>> >> >> >> new file mode 100644
>> >> >> >> index 00..5ccef1ef02
>> >> >> >> --- /dev/null
>> >> >> >> +++ b/drivers/pci/pcie_starfive_jh7110.c
>> >> >> >> @@ -0,0 +1,478 @@
>> >> >> >> +// SPDX-License-Identifier: GPL-2.0+
>> >> >> >> +/*
>> >> >> >> + * StarFive PLDA PCIe host controller driver
>> >> >> >> + *
>> >> >> >> + * Copyright (c) 2023 Starfive, Inc.
>> >> >> >> + * Author: Mason Huo 
>> >> >> >> + *
>> >> >> >> + */
>> >> >> >> +
>> >> >> >> +#include 
>> >> >> >> +#include 
>> >> >> >> +#include 
>> >> >> >> +#i

Re: [PATCH v2 3/3] riscv: dts: starfive: Enable PCIe host controller

[Minda Chen]

On 2023/3/25 21:22, Pali Rohár wrote:
> On Wednesday 08 March 2023 13:48:33 Minda Chen wrote:
>> From: Mason Huo 
>> 
>> Enable and add pinctrl configuration for PCIe host controller.
>> Also add JH7110 stg syscon configuration.
>> 
>> Signed-off-by: Mason Huo 
>> Signed-off-by: Minda Chen 
>> ---
>>  .../dts/jh7110-starfive-visionfive-2.dtsi | 99 +++
>>  arch/riscv/dts/jh7110.dtsi| 75 ++
>>  2 files changed, 174 insertions(+)
>> 
>> diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi 
>> b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
>> index e669c2a26a..995f842a6b 100644
>> --- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
>> +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
>> @@ -178,6 +178,87 @@
>>  slew-rate = <0>;
>>  };
>>  };
>> +
>> +pcie0_perst_default: pcie0_perst_default {
>> +perst-pins {
>> +pinmux = > GPI_NONE)>;
>> +drive-strength = <2>;
>> +input-disable;
>> +input-schmitt-disable;
>> +slew-rate = <0>;
>> +};
>> +};
>> +
>> +pcie0_perst_active: pcie0_perst_active {
>> +perst-pins {
>> +pinmux = > GPI_NONE)>;
>> +drive-strength = <2>;
>> +input-disable;
>> +input-schmitt-disable;
>> +slew-rate = <0>;
>> +};
>> +};
> ...
>> +&pcie0 {
>> +pinctrl-names = "perst-default", "perst-active", "wake-default", 
>> "clkreq-default";
>> +pinctrl-0 = <&pcie0_perst_default>;
>> +pinctrl-1 = <&pcie0_perst_active>;
>> +pinctrl-2 = <&pcie0_wake_default>;
>> +pinctrl-3 = <&pcie0_clkreq_default>;
>> +status = "disabled";
>> +};
> 
> This is not correct declaration of PERST# signal. You should define in
> &pcie0 node "reset-gpios" property with plain gpio definition with
> active state.
> 
> "reset-gpios" is standard PCIe property for controlling PERST# signal
> over GPIO. Look for example into drivers/pci/pci-aardvark.c and
> arch/arm/dts/armada-3720-espressobin.dtsi files how it is used.

OK, I will change this, thanks

[PATCH v3 0/3] Add StarFive JH7110 PCIe drvier support

[Minda Chen]

This patchset needs to apply after patchset in [1]. These PCIe series patches
are based on the JH7110 RISC-V SoC and VisionFive V2 board.

[1] 
https://patchwork.ozlabs.org/project/uboot/cover/20230329034224.26545-1-yanhong.w...@starfivetech.com

The PCIe driver depends on gpio, pinctrl, clk and reset driver to do init.
The PCIe dts configuation includes all these setting.

The PCIe drivers codes has been tested on the VisionFive V2 boards.
The test devices includes M.2 NVMe SSD and Realtek 8169 Ethernet adapter.

previous patch version

v1: 
https://patchwork.ozlabs.org/project/uboot/cover/20230223105240.15180-1-minda.c...@starfivetech.com/
v2: 
https://patchwork.ozlabs.org/project/uboot/cover/20230308054833.95730-1-minda.c...@starfivetech.com/

changes
  v2
   1. remove clock commit. The pcie clocks change has been includeded in [1].
   2. Using GENMASK marco1 in patch1.
   3. remove the syscon dts node in patch3. The syscon dts dts node has been
  included in [1]. 

  v3
   patch 1
1. remove the read vendor ID delay
2. remove starfive_pcie_hide_rc_bar function. do not hide host
bridge BAR write.
3. Using PCIE_ECAM_OFFSET and PCI_CLASS_BRIDGE_PCI_NORMAL macros.
4. Add comments for bus and address limitation reason in function
   starfive_pcie_addr_valid
5. Change the multiple line comments in Line 373
6. Using gpio_request_by_name to get PCIe reset gpio,and using
   dm_gpio_set_value set GPIO value.
  patch 2
1. support PCIeboth 12a and 13b vf2 board.  
  patch 3
1. reset dts change to reset-gpio.

---

The JH7110 minimal system patchset upstream is in progress.
PCIe driver patches is based on this patchset.

The JH7110 minimal system patchset details are listed in [1].

For more JH7110 and visionFive v2 information and support,
you can visit RVspace wiki[2].

[2] https://wiki.rvspace.org/

Mason Huo (3):
  starfive: pci: Add StarFive JH7110 pcie driver
  configs: starfive-jh7110: Add support for PCIe host driver
  riscv: dts: starfive: Enable PCIe host controller

 .../dts/jh7110-starfive-visionfive-2.dtsi |  11 +
 arch/riscv/dts/jh7110.dtsi|  74 +++
 configs/starfive_visionfive2_12a_defconfig|   9 +
 configs/starfive_visionfive2_13b_defconfig|   9 +
 drivers/pci/Kconfig   |  11 +
 drivers/pci/Makefile  |   1 +
 drivers/pci/pcie_starfive_jh7110.c| 463 ++
 7 files changed, 578 insertions(+)
 create mode 100644 drivers/pci/pcie_starfive_jh7110.c


base-commit: 41a88ad529b3943b1e465846eb24fe2c29203e35
prerequisite-patch-id: a84452ba131408ff842b65ae19a3a05f64b3ff60
prerequisite-patch-id: 4abb46d56dbaf36017b2866688f31a73c2cacd0d
prerequisite-patch-id: ef5e9d61f7392c7d2e5321aa8a10996ca8eae5fc
prerequisite-patch-id: 26dfdb401d680ecd9449acf09131cf4790e987b7
prerequisite-patch-id: a0cfa5d8cdb49bbe9d4739afa90991f882950881
prerequisite-patch-id: 61ceecb41cfd9029bfb267f7b7c5330a2d7e5edc
prerequisite-patch-id: d834ece14ffb525b8c3e661e78736692f33fca9b
prerequisite-patch-id: 88c9f9637335fdc4107d42db67b9110c9b73ead3
prerequisite-patch-id: ebc26ed3f97f7babc0fc805152acb578f5eff922
prerequisite-patch-id: e85a9ca22facac4d5b5562a2708b7332478d6db4
prerequisite-patch-id: ff5bd799e4cb905fef6cf1cd0ce757980e1d34b7
prerequisite-patch-id: a341d4e8a8e25cb711309123939235fcb3c10c1a
prerequisite-patch-id: 749e4eafb431857ee2bec4ac8e78a682f6a57588
prerequisite-patch-id: d4a3666ce2e7135402537cea60e9e6f0435230bf
prerequisite-patch-id: fa8ad1bfce7d6ab74ad63ff8d31dff3c2ccb5e43
prerequisite-patch-id: cc352634b8dfaf2d4243819362326a579e010c94
prerequisite-patch-id: 8e0fa3d987020ca06e22401bc4c69f834c38c3dc
-- 
2.17.1

[PATCH v3 2/3] configs: starfive-jh7110: Add support for PCIe host driver

[Minda Chen]

From: Mason Huo 

also add the nvme driver and rtl8169 support.

Signed-off-by: Mason Huo 
Signed-off-by: Minda Chen 
---
 configs/starfive_visionfive2_12a_defconfig | 9 +
 configs/starfive_visionfive2_13b_defconfig | 9 +
 2 files changed, 18 insertions(+)

diff --git a/configs/starfive_visionfive2_12a_defconfig 
b/configs/starfive_visionfive2_12a_defconfig
index e0f98292ff..2a7563743b 100644
--- a/configs/starfive_visionfive2_12a_defconfig
+++ b/configs/starfive_visionfive2_12a_defconfig
@@ -16,6 +16,7 @@ CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
 CONFIG_SYS_LOAD_ADDR=0x8200
+CONFIG_SYS_PCI_64BIT=y
 CONFIG_TARGET_STARFIVE_VISIONFIVE2=y
 CONFIG_SPL_OPENSBI_LOAD_ADDR=0x4000
 CONFIG_ARCH_RV64I=y
@@ -49,9 +50,12 @@ CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_CBSIZE=256
 CONFIG_SYS_PBSIZE=276
 CONFIG_SYS_BOOTM_LEN=0x400
+CONFIG_CMD_PCI=y
 CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_SPL_CLK_COMPOSITE_CCF=y
 CONFIG_CLK_COMPOSITE_CCF=y
 CONFIG_SPL_CLK_JH7110=y
@@ -65,6 +69,11 @@ CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_ISSI=y
 CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_RTL8169=y
+CONFIG_NVME_PCI=y
+CONFIG_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCI_REGION_MULTI_ENTRY=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_SPL_PINCTRL=y
diff --git a/configs/starfive_visionfive2_13b_defconfig 
b/configs/starfive_visionfive2_13b_defconfig
index 550d0ff3ab..98d23d9461 100644
--- a/configs/starfive_visionfive2_13b_defconfig
+++ b/configs/starfive_visionfive2_13b_defconfig
@@ -16,6 +16,7 @@ CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
 CONFIG_SYS_LOAD_ADDR=0x8200
+CONFIG_SYS_PCI_64BIT=y
 CONFIG_TARGET_STARFIVE_VISIONFIVE2=y
 CONFIG_SPL_OPENSBI_LOAD_ADDR=0x4000
 CONFIG_ARCH_RV64I=y
@@ -50,8 +51,11 @@ CONFIG_SYS_CBSIZE=256
 CONFIG_SYS_PBSIZE=276
 CONFIG_SYS_BOOTM_LEN=0x400
 CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_PCI=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_SPL_CLK_COMPOSITE_CCF=y
 CONFIG_CLK_COMPOSITE_CCF=y
 CONFIG_SPL_CLK_JH7110=y
@@ -65,6 +69,11 @@ CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_ISSI=y
 CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_RTL8169=y
+CONFIG_NVME_PCI=y
+CONFIG_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCI_REGION_MULTI_ENTRY=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_SPL_PINCTRL=y
-- 
2.17.1

[PATCH v3 3/3] riscv: dts: starfive: Enable PCIe host controller

[Minda Chen]

From: Mason Huo 

Enable and add pinctrl configuration for PCIe host controller.
Also add JH7110 stg syscon configuration.

Signed-off-by: Mason Huo 
Signed-off-by: Minda Chen 
---
 .../dts/jh7110-starfive-visionfive-2.dtsi | 11 +++
 arch/riscv/dts/jh7110.dtsi| 74 +++
 2 files changed, 85 insertions(+)

diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi 
b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index c6b6dfa940..12245576ac 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -7,6 +7,7 @@
 
 #include "jh7110.dtsi"
 #include 
+#include 
 / {
aliases {
serial0 = &uart0;
@@ -300,6 +301,16 @@
};
 };
 
+&pcie0 {
+   reset-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
+   status = "disabled";
+};
+
+&pcie1 {
+   reset-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;
+   status = "okay";
+};
+
 &syscrg {
assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
  <&syscrg JH7110_SYSCLK_BUS_ROOT>,
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index bd60879615..eaf8035a61 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -569,5 +569,79 @@
gpio-controller;
#gpio-cells = <2>;
};
+
+   pcie0: pcie@2B00 {
+   compatible = "starfive,jh7110-pcie";
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   reg = <0x0 0x2B00 0x0 0x100>,
+ <0x9 0x4000 0x0 0x1000>;
+   reg-names = "reg", "config";
+   device_type = "pci";
+   starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130>;
+   bus-range = <0x0 0xff>;
+   ranges = <0x8200  0x0 0x3000  0x0 0x3000 
0x0 0x0800>,
+   <0xc300  0x9 0x  0x9 0x 0x0 
0x4000>;
+   msi-parent = <&plic>;
+   interrupts = <56>;
+   interrupt-controller;
+   interrupt-names = "msi";
+   interrupt-parent = <&plic>;
+   interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+   interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
+   <0x0 0x0 0x0 0x2 &plic 0x2>,
+   <0x0 0x0 0x0 0x3 &plic 0x3>,
+   <0x0 0x0 0x0 0x4 &plic 0x4>;
+   resets = <&stgcrg JH7110_STGRST_PCIE0_MST0>,
+<&stgcrg JH7110_STGRST_PCIE0_SLV0>,
+<&stgcrg JH7110_STGRST_PCIE0_SLV>,
+<&stgcrg JH7110_STGRST_PCIE0_BRG>,
+<&stgcrg JH7110_STGRST_PCIE0_CORE>,
+<&stgcrg JH7110_STGRST_PCIE0_APB>;
+   clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
+<&stgcrg JH7110_STGCLK_PCIE0_TL>,
+<&stgcrg JH7110_STGCLK_PCIE0_AXI>,
+<&stgcrg JH7110_STGCLK_PCIE0_APB>;
+   clock-names = "noc_bus_stg_axi", "pcie0_tl", 
"pcie0_axi", "pcie0_apb";
+   status = "disabled";
+   };
+
+   pcie1: pcie@2C00 {
+   compatible = "starfive,jh7110-pcie";
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   reg = <0x0 0x2C00 0x0 0x100>,
+ <0x9 0xc000 0x0 0x1000>;
+   reg-names = "reg", "config";
+   device_type = "pci";
+   starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0>;
+   bus-range = <0x0 0xff>;
+   ranges = <0x8200  0x0 0x3800  0x0 0x3800 
0x0 0x0800>,
+   <0xc300  0x9 0x8000  0x9 0x8000 0x0 
0x4000>;
+   msi-parent = <&plic>;
+   interrupts = <

[PATCH v3 1/3] starfive: pci: Add StarFive JH7110 pcie driver

[Minda Chen]

From: Mason Huo 

Add pcie driver for StarFive JH7110, the driver depends on
starfive gpio, pinctrl, clk and reset driver to do init.

Several devices are tested:
a) M.2 NVMe SSD
b) Realtek 8169 Ethernet adapter.

Signed-off-by: Mason Huo 
Signed-off-by: Minda Chen 
---
 drivers/pci/Kconfig|  11 +
 drivers/pci/Makefile   |   1 +
 drivers/pci/pcie_starfive_jh7110.c | 463 +
 3 files changed, 475 insertions(+)
 create mode 100644 drivers/pci/pcie_starfive_jh7110.c

diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index ef328d2652..e7b0ff5bc3 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -374,4 +374,15 @@ config PCIE_UNIPHIER
  Say Y here if you want to enable PCIe controller support on
  UniPhier SoCs.
 
+config PCIE_STARFIVE_JH7110
+   bool "Enable Starfive JH7110 PCIe driver"
+   depends on STARFIVE_JH7110
+   depends on PINCTRL_STARFIVE_JH7110
+   depends on CLK_JH7110
+   depends on RESET_JH7110
+   default y
+   help
+ Say Y here if you want to enable PCIe controller support on
+ StarFive JH7110 SoC.
+
 endif
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 49506e7ba5..bbe3323bb5 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -49,3 +49,4 @@ obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o
 obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o
 obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o
 obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o
+obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o
diff --git a/drivers/pci/pcie_starfive_jh7110.c 
b/drivers/pci/pcie_starfive_jh7110.c
new file mode 100644
index 00..1005ed9919
--- /dev/null
+++ b/drivers/pci/pcie_starfive_jh7110.c
@@ -0,0 +1,463 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * StarFive PLDA PCIe host controller driver
+ *
+ * Copyright (c) 2023 Starfive, Inc.
+ * Author: Mason Huo 
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define GEN_SETTINGS   0x80
+#define PCIE_PCI_IDS   0x9C
+#define PCIE_WINROM0xFC
+#define PMSG_SUPPORT_RX0x3F0
+#define PCI_MISC   0xB4
+
+#define PLDA_EP_ENABLE 0
+#define PLDA_RP_ENABLE 1
+
+#define IDS_REVISION_ID0x02
+#define IDS_CLASS_CODE_SHIFT   8
+
+#define PREF_MEM_WIN_64_SUPPORTBIT(3)
+#define PMSG_LTR_SUPPORT   BIT(2)
+#define PLDA_FUNCTION_DIS  BIT(15)
+#define PLDA_FUNC_NUM  4
+#define PLDA_PHY_FUNC_SHIFT9
+
+#define XR3PCI_ATR_AXI4_SLV0   0x800
+#define XR3PCI_ATR_SRC_ADDR_LOW0x0
+#define XR3PCI_ATR_SRC_ADDR_HIGH   0x4
+#define XR3PCI_ATR_TRSL_ADDR_LOW   0x8
+#define XR3PCI_ATR_TRSL_ADDR_HIGH  0xc
+#define XR3PCI_ATR_TRSL_PARAM  0x10
+#define XR3PCI_ATR_TABLE_OFFSET0x20
+#define XR3PCI_ATR_MAX_TABLE_NUM   8
+
+#define XR3PCI_ATR_SRC_WIN_SIZE_SHIFT  1
+#define XR3PCI_ATR_SRC_ADDR_MASK   GENMASK(31, 12)
+#define XR3PCI_ATR_TRSL_ADDR_MASK  GENMASK(31, 12)
+#define XR3_PCI_ECAM_SIZE  28
+#define XR3PCI_ATR_TRSL_DIRBIT(22)
+/* IDs used in the XR3PCI_ATR_TRSL_PARAM */
+#define XR3PCI_ATR_TRSLID_PCIE_MEMORY  0x0
+#define XR3PCI_ATR_TRSLID_PCIE_CONFIG  0x1
+
+/* system control */
+#define STG_SYSCON_K_RP_NEP_MASK   BIT(8)
+#define STG_SYSCON_AXI4_SLVL_ARFUNC_MASK   GENMASK(22, 8)
+#define STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT  8
+#define STG_SYSCON_AXI4_SLVL_AWFUNC_MASK   GENMASK(14, 0)
+#define STG_SYSCON_CLKREQ_MASK BIT(22)
+#define STG_SYSCON_CKREF_SRC_SHIFT 18
+#define STG_SYSCON_CKREF_SRC_MASK  GENMASK(19, 18)
+
+struct starfive_pcie {
+   struct udevice *dev;
+
+   void __iomem *reg_base;
+   void __iomem *cfg_base;
+
+   struct regmap *regmap;
+   u32 stg_arfun;
+   u32 stg_awfun;
+   u32 stg_rp_nep;
+
+   struct clk_bulk clks;
+   struct reset_ctl_bulk   rsts;
+   struct gpio_descreset_gpio;
+
+   int atr_table_num;
+   int first_busno;
+};
+
+static int starfive_pcie_off_conf(pci_dev_t bdf, uint offset)
+{
+   unsigned int bus = PCI_BUS(bdf);
+   unsigned int dev = PCI_DEV(bdf);
+   unsigned int func = PCI_FUNC(bdf);
+
+   return PCIE_ECAM_OFFSET(bus, dev, func, offset);
+}
+
+static int starfive_pcie_addr_valid(pci_dev_t bdf, int first_busno)
+{
+   /*
+* Single device limitation.
+* For JH7110 SoC limitation, one bus can only connnect one device.
+* And PCIe controller contain HW issue that non-root host bridge
+* bus emumerate duplicate devices.
+

Re: [PATCH v3 1/3] starfive: pci: Add StarFive JH7110 pcie driver

[Minda Chen]

On 2023/3/30 1:27, Pali Rohár wrote:
> Hello!
> 
> On Wednesday 29 March 2023 18:01:41 Minda Chen wrote:
>> From: Mason Huo 
>> 
>> Add pcie driver for StarFive JH7110, the driver depends on
>> starfive gpio, pinctrl, clk and reset driver to do init.
>> 
>> Several devices are tested:
>> a) M.2 NVMe SSD
>> b) Realtek 8169 Ethernet adapter.
>> 
>> Signed-off-by: Mason Huo 
>> Signed-off-by: Minda Chen 
>> ---
>>  drivers/pci/Kconfig|  11 +
>>  drivers/pci/Makefile   |   1 +
>>  drivers/pci/pcie_starfive_jh7110.c | 463 +
>>  3 files changed, 475 insertions(+)
>>  create mode 100644 drivers/pci/pcie_starfive_jh7110.c
>> 
>> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
>> index ef328d2652..e7b0ff5bc3 100644
>> --- a/drivers/pci/Kconfig
>> +++ b/drivers/pci/Kconfig
>> @@ -374,4 +374,15 @@ config PCIE_UNIPHIER
>>Say Y here if you want to enable PCIe controller support on
>>UniPhier SoCs.
>>  
>> +config PCIE_STARFIVE_JH7110
>> +bool "Enable Starfive JH7110 PCIe driver"
>> +depends on STARFIVE_JH7110
>> +depends on PINCTRL_STARFIVE_JH7110
>> +depends on CLK_JH7110
>> +depends on RESET_JH7110
> 
> There is no direct hard dependency on on these 4 symbols (or at least I
> do not see any in include header files). So to allow compile time
> checks, change it to just soft dependency by switching from "depends" to
> "imply" keyword.
> 
ok， I will change this.
>> +default y
>> +help
>> +  Say Y here if you want to enable PCIe controller support on
>> +  StarFive JH7110 SoC.
>> +
>>  endif
> ...
>> diff --git a/drivers/pci/pcie_starfive_jh7110.c 
>> b/drivers/pci/pcie_starfive_jh7110.c
>> new file mode 100644
>> index 00..1005ed9919
>> --- /dev/null
>> +++ b/drivers/pci/pcie_starfive_jh7110.c
> ...
>> +static int starfive_pcie_off_conf(pci_dev_t bdf, uint offset)
>> +{
>> +unsigned int bus = PCI_BUS(bdf);
>> +unsigned int dev = PCI_DEV(bdf);
>> +unsigned int func = PCI_FUNC(bdf);
>> +
>> +return PCIE_ECAM_OFFSET(bus, dev, func, offset);
> 
> This function is used just on one place, it is pretty straightforward
> and nothing starfive_pcie-specific. Just directly inline it into
> starfive_pcie_conf_address() function?
> 
>   int where = PCIE_ECAM_OFFSET(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), 
> offset);
> 
ok, thanks
>> +}
>> +
>> +static int starfive_pcie_addr_valid(pci_dev_t bdf, int first_busno)
>> +{
>> +/*
>> + * Single device limitation.
>> + * For JH7110 SoC limitation, one bus can only connnect one device.
>> + * And PCIe controller contain HW issue that non-root host bridge
>> + * bus emumerate duplicate devices.
>> + * Only can access device 0 in Bus 1 host bridge.
>> + */
>> +if ((PCI_BUS(bdf) != first_busno) && (PCI_DEV(bdf) > 0))
>> +return 0;
> 
> In v2 discussion you wrote that the issue with duplicate devices is on
> the bus 1, which is secondary bus - the bus behind the root port.
> 
> So check against root port bus (first_busno) is not correct, you need to
> check it against bus behind the root port (secondary bus).
> 
> Current check completely filters all devices with numbers higher than 0
> behind the secondary bus, which completely breaks support for PCIe
> switches. Moreover behind PCIe switch can be anything with more
> complicated topology.
> 
> That secondary bus number is dynamically allocated / assigned by U-Boot
> core code, so you need to check PCI_SECONDARY_BUS register of the root
> port.
> 
> In pci_mvebu.c is this value cached in "->sec_busno" member. You can
> reuse this pattern.
> 
> You probably want this kind of check:
> 
>   if (PCI_BUS(bdf) == priv->sec_busno && PCI_DEV(bdf) > 0)
> return false;
>   else
> return true;
> 
OK, thanks， I will record secondary busno according PCI_SECONDARY_BUS  register
> Also comment "non-root host bridge bus" is strange. Bus of the host
> bridge is always the root one. You probably want to write the bus
> immediately behind the root bus / host bridge OR the secondary bus of
> the host bridge.
> 
ok
>> +return 1;
>> +}
>> +
>> +static int starfive_pcie_conf_address(const struct udevice *udev, pci_dev_t 
>> bdf,
>> +  uint offset, void **paddr)
>> +{
>

Re: [PATCH v3 1/3] starfive: pci: Add StarFive JH7110 pcie driver

[Minda Chen]

On 2023/3/31 20:59, Pali Rohár wrote:
> On Friday 31 March 2023 18:35:00 Minda Chen wrote:
>> On 2023/3/30 1:27, Pali Rohár wrote:
>> > Hello!
>> > 
>> > On Wednesday 29 March 2023 18:01:41 Minda Chen wrote:
>> >> + /* PCIe PCI Standard Configuration Identification Settings. */
>> >> + value = (PCI_CLASS_BRIDGE_PCI_NORMAL << IDS_CLASS_CODE_SHIFT) | 
>> >> IDS_REVISION_ID;
>> >> + writel(value, priv->reg_base + PCIE_PCI_IDS);
>> > 
>> > This looks like configuration of the PCI_CLASS_REVISION read-only
>> > register. Is there any reason why you are removing the original
>> > "revision" information by hardcoded IDS_REVISION_ID constant?
>> > 
>> This register is not read-only register, consist  resion ID and class code.
>>  Bit [39:32]: Revision ID
>>  Bit [63:40]: Class code
> 
> I mean that this "priv->reg_base + PCIE_PCI_IDS" read-write register
> configures what is visible when reading read-only standard PCI register
> PCI_CLASS_REVISION.
> 
> PCIe Root Port is by definition of PCI-to-PCI Bridge class and therefore
> reading from PCI_CLASS_REVISION must return PCI_CLASS_BRIDGE_PCI_* value.
> This is required by PCIe spec.
> 
> With above driver init code it looks like that your PCIe controller does
> not set correct value into PCI_CLASS_REVISION register after power-on
> and manually setting correct value via "priv->reg_base + PCIE_PCI_IDS"
> is a workaround.
> 
> Hopefully it is a more clear what I mean in my previous email.
> 

> Also mvebu controller has this issue and has similar workaround in
> pci_mvebu.c driver.
> 
>> And the register reset value is zero, Our PCIe version is 2.0. So set value 
>> 2.
>> Maybe I will add comment to  this.
> 
> Well, Revision ID (low 8 bits of PCI_CLASS_REVISION) is the extension to
> the vendor / device id register. It is not version of PCIe standard.
> 
> I would expect that this Vendor ID, Device ID and Revision ID values are
> not being changed by the driver as they identify PCI and PCIe devices.
I am sorry. It is PCIe controller IP revision ID. I have make a mistake for it.
So zero value is correct. I will remove writing IDS_REVISION_ID value.

[PATCH v4 2/3] configs: starfive-jh7110: Add support for PCIe host driver

[Minda Chen]

From: Mason Huo 

also add the nvme driver and rtl8169 support.

Signed-off-by: Mason Huo 
Signed-off-by: Minda Chen 
---
 configs/starfive_visionfive2_12a_defconfig | 10 ++
 configs/starfive_visionfive2_13b_defconfig | 10 ++
 2 files changed, 20 insertions(+)

diff --git a/configs/starfive_visionfive2_12a_defconfig 
b/configs/starfive_visionfive2_12a_defconfig
index e0f98292ff..bd5b25f9d4 100644
--- a/configs/starfive_visionfive2_12a_defconfig
+++ b/configs/starfive_visionfive2_12a_defconfig
@@ -16,6 +16,7 @@ CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
 CONFIG_SYS_LOAD_ADDR=0x8200
+CONFIG_SYS_PCI_64BIT=y
 CONFIG_TARGET_STARFIVE_VISIONFIVE2=y
 CONFIG_SPL_OPENSBI_LOAD_ADDR=0x4000
 CONFIG_ARCH_RV64I=y
@@ -49,9 +50,12 @@ CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_CBSIZE=256
 CONFIG_SYS_PBSIZE=276
 CONFIG_SYS_BOOTM_LEN=0x400
+CONFIG_CMD_PCI=y
 CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_SPL_CLK_COMPOSITE_CCF=y
 CONFIG_CLK_COMPOSITE_CCF=y
 CONFIG_SPL_CLK_JH7110=y
@@ -65,6 +69,12 @@ CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_ISSI=y
 CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_RTL8169=y
+CONFIG_NVME_PCI=y
+CONFIG_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCI_REGION_MULTI_ENTRY=y
+CONFIG_PCIE_STARFIVE_JH7110=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_SPL_PINCTRL=y
diff --git a/configs/starfive_visionfive2_13b_defconfig 
b/configs/starfive_visionfive2_13b_defconfig
index 550d0ff3ab..7247992796 100644
--- a/configs/starfive_visionfive2_13b_defconfig
+++ b/configs/starfive_visionfive2_13b_defconfig
@@ -16,6 +16,7 @@ CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
 CONFIG_SYS_LOAD_ADDR=0x8200
+CONFIG_SYS_PCI_64BIT=y
 CONFIG_TARGET_STARFIVE_VISIONFIVE2=y
 CONFIG_SPL_OPENSBI_LOAD_ADDR=0x4000
 CONFIG_ARCH_RV64I=y
@@ -50,8 +51,11 @@ CONFIG_SYS_CBSIZE=256
 CONFIG_SYS_PBSIZE=276
 CONFIG_SYS_BOOTM_LEN=0x400
 CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_PCI=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_SPL_CLK_COMPOSITE_CCF=y
 CONFIG_CLK_COMPOSITE_CCF=y
 CONFIG_SPL_CLK_JH7110=y
@@ -65,6 +69,12 @@ CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_ISSI=y
 CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_RTL8169=y
+CONFIG_NVME_PCI=y
+CONFIG_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCI_REGION_MULTI_ENTRY=y
+CONFIG_PCIE_STARFIVE_JH7110=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_SPL_PINCTRL=y
-- 
2.17.1

[PATCH v4 0/3] Add StarFive JH7110 PCIe drvier support

[Minda Chen]

This patchset needs to apply after patchset in [1]. These PCIe series patches
are based on the JH7110 RISC-V SoC and VisionFive V2 board.

[1] 
https://patchwork.ozlabs.org/project/uboot/cover/20230329034224.26545-1-yanhong.w...@starfivetech.com

The PCIe driver depends on gpio, pinctrl, clk and reset driver to do init.
The PCIe dts configuation includes all these setting.

The PCIe drivers codes has been tested on the VisionFive V2 boards.
The test devices includes M.2 NVMe SSD and Realtek 8169 Ethernet adapter.

previous patch version

v1: 
https://patchwork.ozlabs.org/project/uboot/cover/20230223105240.15180-1-minda.c...@starfivetech.com/
v2: 
https://patchwork.ozlabs.org/project/uboot/cover/20230308054833.95730-1-minda.c...@starfivetech.com/
v3: 
https://patchwork.ozlabs.org/project/uboot/cover/20230329100143.10724-1-minda.c...@starfivetech.com/

changes
  v4
   patch 1
1. Remove the IDS_REVISION_ID macros.
2. Replace sec_busno to first_busno in starfive_pcie
3. Remove starfive_pcie_off_conf function.
4. Replace "imply" to "depends on" in PCIe Kconfig.
5 .Check sec_busno in starfive_pcie_addr_valid.
 
  v3
   patch 1
1. remove the read vendor ID delay
2. remove starfive_pcie_hide_rc_bar function. do not hide host
bridge BAR write.
3. Using PCIE_ECAM_OFFSET and PCI_CLASS_BRIDGE_PCI_NORMAL macros.
4. Add comments for bus and address limitation reason in function
   starfive_pcie_addr_valid
5. Change the multiple line comments in Line 373
6. Using gpio_request_by_name to get PCIe reset gpio,and using
   dm_gpio_set_value set GPIO value.
  patch 2
1. support PCIeboth 12a and 13b vf2 board.  
  patch 3
1. reset dts change to reset-gpio.

  v2
   1. remove clock commit. The pcie clocks change has been includeded in [1].
   2. Using GENMASK marco1 in patch1.
   3. remove the syscon dts node in patch3. The syscon dts dts node has been
  included in [1]. 

---
Mason Huo (3):
  starfive: pci: Add StarFive JH7110 pcie driver
  configs: starfive-jh7110: Add support for PCIe host driver
  riscv: dts: starfive: Enable PCIe host controller

 .../dts/jh7110-starfive-visionfive-2.dtsi |  11 +
 arch/riscv/dts/jh7110.dtsi|  74 +++
 configs/starfive_visionfive2_12a_defconfig|  10 +
 configs/starfive_visionfive2_13b_defconfig|  10 +
 drivers/pci/Kconfig   |   9 +
 drivers/pci/Makefile  |   1 +
 drivers/pci/pcie_starfive_jh7110.c| 465 ++
 7 files changed, 580 insertions(+)
 create mode 100644 drivers/pci/pcie_starfive_jh7110.c


base-commit: 41a88ad529b3943b1e465846eb24fe2c29203e35
prerequisite-patch-id: a84452ba131408ff842b65ae19a3a05f64b3ff60
prerequisite-patch-id: 4abb46d56dbaf36017b2866688f31a73c2cacd0d
prerequisite-patch-id: ef5e9d61f7392c7d2e5321aa8a10996ca8eae5fc
prerequisite-patch-id: 26dfdb401d680ecd9449acf09131cf4790e987b7
prerequisite-patch-id: a0cfa5d8cdb49bbe9d4739afa90991f882950881
prerequisite-patch-id: 61ceecb41cfd9029bfb267f7b7c5330a2d7e5edc
prerequisite-patch-id: d834ece14ffb525b8c3e661e78736692f33fca9b
prerequisite-patch-id: 88c9f9637335fdc4107d42db67b9110c9b73ead3
prerequisite-patch-id: ebc26ed3f97f7babc0fc805152acb578f5eff922
prerequisite-patch-id: e85a9ca22facac4d5b5562a2708b7332478d6db4
prerequisite-patch-id: ff5bd799e4cb905fef6cf1cd0ce757980e1d34b7
prerequisite-patch-id: a341d4e8a8e25cb711309123939235fcb3c10c1a
prerequisite-patch-id: 749e4eafb431857ee2bec4ac8e78a682f6a57588
prerequisite-patch-id: d4a3666ce2e7135402537cea60e9e6f0435230bf
prerequisite-patch-id: fa8ad1bfce7d6ab74ad63ff8d31dff3c2ccb5e43
prerequisite-patch-id: cc352634b8dfaf2d4243819362326a579e010c94
prerequisite-patch-id: 8e0fa3d987020ca06e22401bc4c69f834c38c3dc
-- 
2.17.1

[PATCH v4 3/3] riscv: dts: starfive: Enable PCIe host controller

[Minda Chen]

From: Mason Huo 

Enable and add pinctrl configuration for PCIe host controller.
Also add JH7110 stg syscon configuration.

Signed-off-by: Mason Huo 
Signed-off-by: Minda Chen 
---
 .../dts/jh7110-starfive-visionfive-2.dtsi | 11 +++
 arch/riscv/dts/jh7110.dtsi| 74 +++
 2 files changed, 85 insertions(+)

diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi 
b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index c6b6dfa940..12245576ac 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -7,6 +7,7 @@
 
 #include "jh7110.dtsi"
 #include 
+#include 
 / {
aliases {
serial0 = &uart0;
@@ -300,6 +301,16 @@
};
 };
 
+&pcie0 {
+   reset-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
+   status = "disabled";
+};
+
+&pcie1 {
+   reset-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;
+   status = "okay";
+};
+
 &syscrg {
assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
  <&syscrg JH7110_SYSCLK_BUS_ROOT>,
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index bd60879615..eaf8035a61 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -569,5 +569,79 @@
gpio-controller;
#gpio-cells = <2>;
};
+
+   pcie0: pcie@2B00 {
+   compatible = "starfive,jh7110-pcie";
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   reg = <0x0 0x2B00 0x0 0x100>,
+ <0x9 0x4000 0x0 0x1000>;
+   reg-names = "reg", "config";
+   device_type = "pci";
+   starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130>;
+   bus-range = <0x0 0xff>;
+   ranges = <0x8200  0x0 0x3000  0x0 0x3000 
0x0 0x0800>,
+   <0xc300  0x9 0x  0x9 0x 0x0 
0x4000>;
+   msi-parent = <&plic>;
+   interrupts = <56>;
+   interrupt-controller;
+   interrupt-names = "msi";
+   interrupt-parent = <&plic>;
+   interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+   interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
+   <0x0 0x0 0x0 0x2 &plic 0x2>,
+   <0x0 0x0 0x0 0x3 &plic 0x3>,
+   <0x0 0x0 0x0 0x4 &plic 0x4>;
+   resets = <&stgcrg JH7110_STGRST_PCIE0_MST0>,
+<&stgcrg JH7110_STGRST_PCIE0_SLV0>,
+<&stgcrg JH7110_STGRST_PCIE0_SLV>,
+<&stgcrg JH7110_STGRST_PCIE0_BRG>,
+<&stgcrg JH7110_STGRST_PCIE0_CORE>,
+<&stgcrg JH7110_STGRST_PCIE0_APB>;
+   clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
+<&stgcrg JH7110_STGCLK_PCIE0_TL>,
+<&stgcrg JH7110_STGCLK_PCIE0_AXI>,
+<&stgcrg JH7110_STGCLK_PCIE0_APB>;
+   clock-names = "noc_bus_stg_axi", "pcie0_tl", 
"pcie0_axi", "pcie0_apb";
+   status = "disabled";
+   };
+
+   pcie1: pcie@2C00 {
+   compatible = "starfive,jh7110-pcie";
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   reg = <0x0 0x2C00 0x0 0x100>,
+ <0x9 0xc000 0x0 0x1000>;
+   reg-names = "reg", "config";
+   device_type = "pci";
+   starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0>;
+   bus-range = <0x0 0xff>;
+   ranges = <0x8200  0x0 0x3800  0x0 0x3800 
0x0 0x0800>,
+   <0xc300  0x9 0x8000  0x9 0x8000 0x0 
0x4000>;
+   msi-parent = <&plic>;
+   interrupts = <

[PATCH v4 1/3] starfive: pci: Add StarFive JH7110 pcie driver

[Minda Chen]

From: Mason Huo 

Add pcie driver for StarFive JH7110, the driver depends on
starfive gpio, pinctrl, clk and reset driver to do init.

Several devices are tested:
a) M.2 NVMe SSD
b) Realtek 8169 Ethernet adapter.

Signed-off-by: Mason Huo 
Signed-off-by: Minda Chen 
---
 drivers/pci/Kconfig|   9 +
 drivers/pci/Makefile   |   1 +
 drivers/pci/pcie_starfive_jh7110.c | 465 +
 3 files changed, 475 insertions(+)
 create mode 100644 drivers/pci/pcie_starfive_jh7110.c

diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index ef328d2652..f37b6baa25 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -374,4 +374,13 @@ config PCIE_UNIPHIER
  Say Y here if you want to enable PCIe controller support on
  UniPhier SoCs.
 
+config PCIE_STARFIVE_JH7110
+   bool "Enable Starfive JH7110 PCIe driver"
+   imply STARFIVE_JH7110
+   imply CLK_JH7110
+   imply RESET_JH7110
+   help
+ Say Y here if you want to enable PCIe controller support on
+ StarFive JH7110 SoC.
+
 endif
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 49506e7ba5..bbe3323bb5 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -49,3 +49,4 @@ obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o
 obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o
 obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o
 obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o
+obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o
diff --git a/drivers/pci/pcie_starfive_jh7110.c 
b/drivers/pci/pcie_starfive_jh7110.c
new file mode 100644
index 00..130181013e
--- /dev/null
+++ b/drivers/pci/pcie_starfive_jh7110.c
@@ -0,0 +1,465 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * StarFive PLDA PCIe host controller driver
+ *
+ * Copyright (c) 2023 Starfive, Inc.
+ * Author: Mason Huo 
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define GEN_SETTINGS   0x80
+#define PCIE_PCI_IDS   0x9C
+#define PCIE_WINROM0xFC
+#define PMSG_SUPPORT_RX0x3F0
+#define PCI_MISC   0xB4
+
+#define PLDA_EP_ENABLE 0
+#define PLDA_RP_ENABLE 1
+
+#define IDS_CLASS_CODE_SHIFT   8
+
+#define PREF_MEM_WIN_64_SUPPORTBIT(3)
+#define PMSG_LTR_SUPPORT   BIT(2)
+#define PLDA_FUNCTION_DIS  BIT(15)
+#define PLDA_FUNC_NUM  4
+#define PLDA_PHY_FUNC_SHIFT9
+
+#define XR3PCI_ATR_AXI4_SLV0   0x800
+#define XR3PCI_ATR_SRC_ADDR_LOW0x0
+#define XR3PCI_ATR_SRC_ADDR_HIGH   0x4
+#define XR3PCI_ATR_TRSL_ADDR_LOW   0x8
+#define XR3PCI_ATR_TRSL_ADDR_HIGH  0xc
+#define XR3PCI_ATR_TRSL_PARAM  0x10
+#define XR3PCI_ATR_TABLE_OFFSET0x20
+#define XR3PCI_ATR_MAX_TABLE_NUM   8
+
+#define XR3PCI_ATR_SRC_WIN_SIZE_SHIFT  1
+#define XR3PCI_ATR_SRC_ADDR_MASK   GENMASK(31, 12)
+#define XR3PCI_ATR_TRSL_ADDR_MASK  GENMASK(31, 12)
+#define XR3_PCI_ECAM_SIZE  28
+#define XR3PCI_ATR_TRSL_DIRBIT(22)
+/* IDs used in the XR3PCI_ATR_TRSL_PARAM */
+#define XR3PCI_ATR_TRSLID_PCIE_MEMORY  0x0
+#define XR3PCI_ATR_TRSLID_PCIE_CONFIG  0x1
+
+/* system control */
+#define STG_SYSCON_K_RP_NEP_MASK   BIT(8)
+#define STG_SYSCON_AXI4_SLVL_ARFUNC_MASK   GENMASK(22, 8)
+#define STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT  8
+#define STG_SYSCON_AXI4_SLVL_AWFUNC_MASK   GENMASK(14, 0)
+#define STG_SYSCON_CLKREQ_MASK BIT(22)
+#define STG_SYSCON_CKREF_SRC_SHIFT 18
+#define STG_SYSCON_CKREF_SRC_MASK  GENMASK(19, 18)
+
+struct starfive_pcie {
+   struct udevice *dev;
+
+   void __iomem *reg_base;
+   void __iomem *cfg_base;
+
+   struct regmap *regmap;
+   u32 stg_arfun;
+   u32 stg_awfun;
+   u32 stg_rp_nep;
+
+   struct clk_bulk clks;
+   struct reset_ctl_bulk   rsts;
+   struct gpio_descreset_gpio;
+
+   int atr_table_num;
+   int sec_busno;
+};
+
+static bool starfive_pcie_addr_valid(pci_dev_t bdf, struct starfive_pcie *priv)
+{
+   /*
+* Single device limitation.
+* For JH7110 SoC limitation, one bus can only connnect one device.
+* And PCIe controller contain HW issue that secondary bus of
+* host bridge emumerate duplicate devices.
+* Only can access device 0 in secondary bus.
+*/
+   if (PCI_BUS(bdf) == priv->sec_busno && PCI_DEV(bdf) > 0)
+   return false;
+
+   return true;
+}
+
+static int starfive_pcie_conf_address(const struct udevice *udev, pci_dev_t 
bdf,
+ uint offset, void **paddr)
+{
+   struct starfive_p

Re: [PATCH v4 1/3] starfive: pci: Add StarFive JH7110 pcie driver

[Minda Chen]

On 2023/4/11 10:55, Bin Meng wrote:
> On Tue, Apr 11, 2023 at 9:03 AM Minda Chen  
> wrote:
>>
>> From: Mason Huo 
>>
>> Add pcie driver for StarFive JH7110, the driver depends on
>> starfive gpio, pinctrl, clk and reset driver to do init.
>>
>> Several devices are tested:
>> a) M.2 NVMe SSD
>> b) Realtek 8169 Ethernet adapter.
>>
>> Signed-off-by: Mason Huo 
>> Signed-off-by: Minda Chen 
>> ---
>>  drivers/pci/Kconfig|   9 +
>>  drivers/pci/Makefile   |   1 +
>>  drivers/pci/pcie_starfive_jh7110.c | 465 +
>>  3 files changed, 475 insertions(+)
>>  create mode 100644 drivers/pci/pcie_starfive_jh7110.c
>>
>> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
>> index ef328d2652..f37b6baa25 100644
>> --- a/drivers/pci/Kconfig
>> +++ b/drivers/pci/Kconfig
>> @@ -374,4 +374,13 @@ config PCIE_UNIPHIER
>>   Say Y here if you want to enable PCIe controller support on
>>   UniPhier SoCs.
>>
>> +config PCIE_STARFIVE_JH7110
>> +   bool "Enable Starfive JH7110 PCIe driver"
>> +   imply STARFIVE_JH7110
>> +   imply CLK_JH7110
>> +   imply RESET_JH7110
>> +   help
>> + Say Y here if you want to enable PCIe controller support on
>> + StarFive JH7110 SoC.
>> +
>>  endif
>> diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
>> index 49506e7ba5..bbe3323bb5 100644
>> --- a/drivers/pci/Makefile
>> +++ b/drivers/pci/Makefile
>> @@ -49,3 +49,4 @@ obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o
>>  obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o
>>  obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o
>>  obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o
>> +obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o
>> diff --git a/drivers/pci/pcie_starfive_jh7110.c 
>> b/drivers/pci/pcie_starfive_jh7110.c
>> new file mode 100644
>> index 00..130181013e
>> --- /dev/null
>> +++ b/drivers/pci/pcie_starfive_jh7110.c
>> @@ -0,0 +1,465 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * StarFive PLDA PCIe host controller driver
>> + *
>> + * Copyright (c) 2023 Starfive, Inc.
>> + * Author: Mason Huo 
>> + *
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +#define GEN_SETTINGS   0x80
>> +#define PCIE_PCI_IDS   0x9C
>> +#define PCIE_WINROM0xFC
>> +#define PMSG_SUPPORT_RX0x3F0
>> +#define PCI_MISC   0xB4
>> +
>> +#define PLDA_EP_ENABLE 0
>> +#define PLDA_RP_ENABLE 1
>> +
>> +#define IDS_CLASS_CODE_SHIFT   8
>> +
>> +#define PREF_MEM_WIN_64_SUPPORTBIT(3)
>> +#define PMSG_LTR_SUPPORT   BIT(2)
>> +#define PLDA_FUNCTION_DIS  BIT(15)
>> +#define PLDA_FUNC_NUM  4
>> +#define PLDA_PHY_FUNC_SHIFT9
>> +
>> +#define XR3PCI_ATR_AXI4_SLV0   0x800
>> +#define XR3PCI_ATR_SRC_ADDR_LOW0x0
>> +#define XR3PCI_ATR_SRC_ADDR_HIGH   0x4
>> +#define XR3PCI_ATR_TRSL_ADDR_LOW   0x8
>> +#define XR3PCI_ATR_TRSL_ADDR_HIGH  0xc
>> +#define XR3PCI_ATR_TRSL_PARAM  0x10
>> +#define XR3PCI_ATR_TABLE_OFFSET0x20
>> +#define XR3PCI_ATR_MAX_TABLE_NUM   8
>> +
>> +#define XR3PCI_ATR_SRC_WIN_SIZE_SHIFT  1
>> +#define XR3PCI_ATR_SRC_ADDR_MASK   GENMASK(31, 12)
>> +#define XR3PCI_ATR_TRSL_ADDR_MASK  GENMASK(31, 12)
>> +#define XR3_PCI_ECAM_SIZE  28
>> +#define XR3PCI_ATR_TRSL_DIRBIT(22)
>> +/* IDs used in the XR3PCI_ATR_TRSL_PARAM */
>> +#define XR3PCI_ATR_TRSLID_PCIE_MEMORY  0x0
>> +#define XR3PCI_ATR_TRSLID_PCIE_CONFIG  0x1
>> +
>> +/* system control */
>> +#define STG_SYSCON_K_RP_NEP_MASK   BIT(8)
>> +#define STG_SYSCON_AXI4_SLVL_ARFUNC_MASK   GENMASK(22, 8)
>> +#define STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT  8
>> +#define STG_SYSCON_AXI4_SLVL_AWFUNC_MASK   GENMASK(14, 0)
>> +#define STG_SYSCON_CLKREQ_MASK BIT(22)
>> 

Re: [PATCH v4 1/3] starfive: pci: Add StarFive JH7110 pcie driver

[Minda Chen]

On 2023/4/11 13:20, Bin Meng wrote:
> On Tue, Apr 11, 2023 at 11:53 AM Minda Chen  
> wrote:
>>
>>
>>
>> On 2023/4/11 10:55, Bin Meng wrote:
>> > On Tue, Apr 11, 2023 at 9:03 AM Minda Chen  
>> > wrote:
>> >>
>> >> From: Mason Huo 
>> >>
>> >> Add pcie driver for StarFive JH7110, the driver depends on
>> >> starfive gpio, pinctrl, clk and reset driver to do init.
>> >>
>> >> Several devices are tested:
>> >> a) M.2 NVMe SSD
>> >> b) Realtek 8169 Ethernet adapter.
>> >>
>> >> Signed-off-by: Mason Huo 
>> >> Signed-off-by: Minda Chen 
>> >> ---
>> >>  drivers/pci/Kconfig|   9 +
>> >>  drivers/pci/Makefile   |   1 +
>> >>  drivers/pci/pcie_starfive_jh7110.c | 465 +
>> >>  3 files changed, 475 insertions(+)
>> >>  create mode 100644 drivers/pci/pcie_starfive_jh7110.c
>> >>
>> >> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
>> >> index ef328d2652..f37b6baa25 100644
>> >> --- a/drivers/pci/Kconfig
>> >> +++ b/drivers/pci/Kconfig
>> >> @@ -374,4 +374,13 @@ config PCIE_UNIPHIER
>> >>   Say Y here if you want to enable PCIe controller support on
>> >>   UniPhier SoCs.
>> >>
>> >> +config PCIE_STARFIVE_JH7110
>> >> +   bool "Enable Starfive JH7110 PCIe driver"
>> >> +   imply STARFIVE_JH7110
>> >> +   imply CLK_JH7110
>> >> +   imply RESET_JH7110
>> >> +   help
>> >> + Say Y here if you want to enable PCIe controller support on
>> >> + StarFive JH7110 SoC.
>> >> +
>> >>  endif
>> >> diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
>> >> index 49506e7ba5..bbe3323bb5 100644
>> >> --- a/drivers/pci/Makefile
>> >> +++ b/drivers/pci/Makefile
>> >> @@ -49,3 +49,4 @@ obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o
>> >>  obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o
>> >>  obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o
>> >>  obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o
>> >> +obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o
>> >> diff --git a/drivers/pci/pcie_starfive_jh7110.c 
>> >> b/drivers/pci/pcie_starfive_jh7110.c
>> >> new file mode 100644
>> >> index 00..130181013e
>> >> --- /dev/null
>> >> +++ b/drivers/pci/pcie_starfive_jh7110.c
>> >> @@ -0,0 +1,465 @@
>> >> +// SPDX-License-Identifier: GPL-2.0+
>> >> +/*
>> >> + * StarFive PLDA PCIe host controller driver
>> >> + *
>> >> + * Copyright (c) 2023 Starfive, Inc.
>> >> + * Author: Mason Huo 
>> >> + *
>> >> + */
>> >> +
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +
>> >> +DECLARE_GLOBAL_DATA_PTR;
>> >> +
>> >> +#define GEN_SETTINGS   0x80
>> >> +#define PCIE_PCI_IDS   0x9C
>> >> +#define PCIE_WINROM0xFC
>> >> +#define PMSG_SUPPORT_RX0x3F0
>> >> +#define PCI_MISC   0xB4
>> >> +
>> >> +#define PLDA_EP_ENABLE 0
>> >> +#define PLDA_RP_ENABLE 1
>> >> +
>> >> +#define IDS_CLASS_CODE_SHIFT   8
>> >> +
>> >> +#define PREF_MEM_WIN_64_SUPPORTBIT(3)
>> >> +#define PMSG_LTR_SUPPORT   BIT(2)
>> >> +#define PLDA_FUNCTION_DIS  BIT(15)
>> >> +#define PLDA_FUNC_NUM  4
>> >> +#define PLDA_PHY_FUNC_SHIFT9
>> >> +
>> >> +#define XR3PCI_ATR_AXI4_SLV0   0x800
>> >> +#define XR3PCI_ATR_SRC_ADDR_LOW0x0
>> >> +#define XR3PCI_ATR_SRC_ADDR_HIGH   0x4
>> >> +#define XR3PCI

Re: [PATCH v4 1/3] starfive: pci: Add StarFive JH7110 pcie driver

[Minda Chen]

On 2023/4/12 5:29, Pali Rohár wrote:
> Hello!
> 
> On Tuesday 11 April 2023 09:02:07 Minda Chen wrote:
>> +int starfive_pcie_config_write(struct udevice *udev, pci_dev_t bdf,
>> +   uint offset, ulong value,
>> +   enum pci_size_t size)
>> +{
>> +struct starfive_pcie *priv = dev_get_priv(udev);
>> +int ret;
>> +
>> +ret = pci_generic_mmap_write_config(udev, starfive_pcie_conf_address,
>> +bdf, offset, value, size);
>> +
>> +if (!ret && offset == PCI_SECONDARY_BUS) {
>> +priv->sec_busno = value & 0xff;
>> +debug("Secondary bus number was changed to %d\n",
>> +  priv->sec_busno);
>> +}
> 
> This block of code contains two issues:
> 
> 1) If secondary bus is changed by the 16-bit or 32-bit write operation
>then this condition does not catch it.
> 
> 2) priv->sec_busno is used just for checking if driver is going to
>access device on secondary bus of the Root Port. But this code
>updates priv->sec_busno also for write to _any_ device on any bus,
>not just when updating Root Port device. So it breaks support for
>non-trivial PCIe hierarchy which contains e.g. PCIe switch (e.g. when
>changing configuration of the virtual PCI-to-PCI bridge device of
>PCIe switch, which is behind the secondary bus of the Root Port).
> 
> So you need something like this:
> 
> if (!ret &&
> PCI_BUS(bdf) == dev_seq(udev) && PCI_DEV(bdf) == 0 && PCI_FUNC(bdf) 
> == 0 &&
> (offset == PCI_SECONDARY_BUS || (offset == PCI_PRIMARY_BUS && size != 
> PCI_SIZE_8)) {
> priv->sec_busno = ((offset == PCI_PRIMARY_BUS) ? (value >> 8) : 
> value) & 0xff;
> debug("Secondary bus number was changed to %d\n", pcie->sec_busno);
> }
> 
> You have to update priv->sec_busno only when write request is for the
> Root Port. And you need to catch also 16-bit or 32-bit write operation
> to the PCI_PRIMARY_BUS register. It is because PCI_SECONDARY_BUS reg
> is (PCI_PRIMARY_BUS+2) and (PCI_SECONDARY_BUS & ~3) == PCI_PRIMARY_BUS
> 
I will change like this. Thank you very much.
>> +return ret;
>> +}

[PATCH v5 0/3] Add StarFive JH7110 PCIe drvier support

[Minda Chen]

This patchset needs to apply after patchset in [1]. These PCIe series patches
are based on the JH7110 RISC-V SoC and VisionFive V2 board.

[1] 
https://patchwork.ozlabs.org/project/uboot/cover/20230329034224.26545-1-yanhong.w...@starfivetech.com

The PCIe driver depends on gpio, pinctrl, clk and reset driver to do init.
The PCIe dts configuation includes all these setting.

The PCIe drivers codes has been tested on the VisionFive V2 boards.
The test devices includes M.2 NVMe SSD and Realtek 8169 Ethernet adapter.

previous patch version

v1: 
https://patchwork.ozlabs.org/project/uboot/cover/20230223105240.15180-1-minda.c...@starfivetech.com/
v2: 
https://patchwork.ozlabs.org/project/uboot/cover/20230308054833.95730-1-minda.c...@starfivetech.com/
v3: 
https://patchwork.ozlabs.org/project/uboot/cover/20230329100143.10724-1-minda.c...@starfivetech.com/
v4: 
https://patchwork.ozlabs.org/project/uboot/cover/20230411010209.76561-1-minda.c...@starfivetech.com/

changes
  v5
   patch 1
1. split PLDA controller driver codes to pcie_plda_common.c
2. correct the codes of record secondary number. 
   patch 3
1. change the pcie dtsi config. make them the same with kernel.
 
  v4
   patch 1
1. Remove the IDS_REVISION_ID macros.
2. Replace sec_busno to first_busno in starfive_pcie
3. Remove starfive_pcie_off_conf function.
4. Replace "imply" to "depends on" in PCIe Kconfig.
5 .Check sec_busno in starfive_pcie_addr_valid.
 
  v3
   patch 1
1. remove the read vendor ID delay
2. remove starfive_pcie_hide_rc_bar function. do not hide host
bridge BAR write.
3. Using PCIE_ECAM_OFFSET and PCI_CLASS_BRIDGE_PCI_NORMAL macros.
4. Add comments for bus and address limitation reason in function
   starfive_pcie_addr_valid
5. Change the multiple line comments in Line 373
6. Using gpio_request_by_name to get PCIe reset gpio,and using
   dm_gpio_set_value set GPIO value.
  patch 2
1. support PCIeboth 12a and 13b vf2 board.  
  patch 3
1. reset dts change to reset-gpio.

  v2
   1. remove clock commit. The pcie clocks change has been includeded in [1].
   2. Using GENMASK marco1 in patch1.
   3. remove the syscon dts node in patch3. The syscon dts dts node has been
  included in [1]. 


Mason Huo (3):
  starfive: pci: Add StarFive JH7110 pcie driver
  configs: starfive-jh7110: Add support for PCIe host driver
  riscv: dts: starfive: Enable PCIe host controller

 .../dts/jh7110-starfive-visionfive-2.dtsi |  11 +
 arch/riscv/dts/jh7110.dtsi|  88 +
 configs/starfive_visionfive2_12a_defconfig|  10 +
 configs/starfive_visionfive2_13b_defconfig|  10 +
 drivers/pci/Kconfig   |  13 +
 drivers/pci/Makefile  |   2 +
 drivers/pci/pcie_plda_common.c| 116 +++
 drivers/pci/pcie_plda_common.h| 118 +++
 drivers/pci/pcie_starfive_jh7110.c| 317 ++
 9 files changed, 685 insertions(+)
 create mode 100644 drivers/pci/pcie_plda_common.c
 create mode 100644 drivers/pci/pcie_plda_common.h
 create mode 100644 drivers/pci/pcie_starfive_jh7110.c


base-commit: 41a88ad529b3943b1e465846eb24fe2c29203e35
-- 
2.17.1

[PATCH v5 2/3] configs: starfive-jh7110: Add support for PCIe host driver

[Minda Chen]

From: Mason Huo 

also add the nvme driver and rtl8169 support.

Signed-off-by: Mason Huo 
Signed-off-by: Minda Chen 
---
 configs/starfive_visionfive2_12a_defconfig | 10 ++
 configs/starfive_visionfive2_13b_defconfig | 10 ++
 2 files changed, 20 insertions(+)

diff --git a/configs/starfive_visionfive2_12a_defconfig 
b/configs/starfive_visionfive2_12a_defconfig
index e0f98292ff..bd5b25f9d4 100644
--- a/configs/starfive_visionfive2_12a_defconfig
+++ b/configs/starfive_visionfive2_12a_defconfig
@@ -16,6 +16,7 @@ CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
 CONFIG_SYS_LOAD_ADDR=0x8200
+CONFIG_SYS_PCI_64BIT=y
 CONFIG_TARGET_STARFIVE_VISIONFIVE2=y
 CONFIG_SPL_OPENSBI_LOAD_ADDR=0x4000
 CONFIG_ARCH_RV64I=y
@@ -49,9 +50,12 @@ CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_CBSIZE=256
 CONFIG_SYS_PBSIZE=276
 CONFIG_SYS_BOOTM_LEN=0x400
+CONFIG_CMD_PCI=y
 CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_SPL_CLK_COMPOSITE_CCF=y
 CONFIG_CLK_COMPOSITE_CCF=y
 CONFIG_SPL_CLK_JH7110=y
@@ -65,6 +69,12 @@ CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_ISSI=y
 CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_RTL8169=y
+CONFIG_NVME_PCI=y
+CONFIG_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCI_REGION_MULTI_ENTRY=y
+CONFIG_PCIE_STARFIVE_JH7110=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_SPL_PINCTRL=y
diff --git a/configs/starfive_visionfive2_13b_defconfig 
b/configs/starfive_visionfive2_13b_defconfig
index 550d0ff3ab..7247992796 100644
--- a/configs/starfive_visionfive2_13b_defconfig
+++ b/configs/starfive_visionfive2_13b_defconfig
@@ -16,6 +16,7 @@ CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
 CONFIG_SYS_LOAD_ADDR=0x8200
+CONFIG_SYS_PCI_64BIT=y
 CONFIG_TARGET_STARFIVE_VISIONFIVE2=y
 CONFIG_SPL_OPENSBI_LOAD_ADDR=0x4000
 CONFIG_ARCH_RV64I=y
@@ -50,8 +51,11 @@ CONFIG_SYS_CBSIZE=256
 CONFIG_SYS_PBSIZE=276
 CONFIG_SYS_BOOTM_LEN=0x400
 CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_PCI=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_SPL_CLK_COMPOSITE_CCF=y
 CONFIG_CLK_COMPOSITE_CCF=y
 CONFIG_SPL_CLK_JH7110=y
@@ -65,6 +69,12 @@ CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_ISSI=y
 CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_RTL8169=y
+CONFIG_NVME_PCI=y
+CONFIG_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCI_REGION_MULTI_ENTRY=y
+CONFIG_PCIE_STARFIVE_JH7110=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_SPL_PINCTRL=y
-- 
2.17.1

[PATCH v5 3/3] riscv: dts: starfive: Enable PCIe host controller

[Minda Chen]

From: Mason Huo 

Enable and add pinctrl configuration for PCIe host controller.
Also add JH7110 stg syscon configuration.

Signed-off-by: Mason Huo 
Signed-off-by: Minda Chen 
---
 .../dts/jh7110-starfive-visionfive-2.dtsi | 11 +++
 arch/riscv/dts/jh7110.dtsi| 88 +++
 2 files changed, 99 insertions(+)

diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi 
b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index c6b6dfa940..12245576ac 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -7,6 +7,7 @@
 
 #include "jh7110.dtsi"
 #include 
+#include 
 / {
aliases {
serial0 = &uart0;
@@ -300,6 +301,16 @@
};
 };
 
+&pcie0 {
+   reset-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
+   status = "disabled";
+};
+
+&pcie1 {
+   reset-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;
+   status = "okay";
+};
+
 &syscrg {
assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
  <&syscrg JH7110_SYSCLK_BUS_ROOT>,
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index bd60879615..f210dfc99c 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -569,5 +569,93 @@
gpio-controller;
#gpio-cells = <2>;
};
+
+   pcie0: pcie@2b00 {
+   compatible = "starfive,jh7110-pcie";
+   reg = <0x0 0x2b00 0x0 0x100
+  0x9 0x4000 0x0 0x1000>;
+   reg-names = "reg", "config";
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   ranges = <0x8200  0x0 0x3000  0x0 0x3000 
0x0 0x0800>,
+<0xc300  0x9 0x  0x9 0x 
0x0 0x4000>;
+   interrupts = <56>;
+   interrupt-parent = <&plic>;
+   interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+   interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>,
+   <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>,
+   <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>,
+   <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>;
+   device_type = "pci";
+   starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 
0x1b8>;
+   bus-range = <0x0 0xff>;
+   msi-parent = <&pcie0>;
+   msi-controller;
+   clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
+<&stgcrg JH7110_STGCLK_PCIE0_TL>,
+<&stgcrg JH7110_STGCLK_PCIE0_AXI>,
+<&stgcrg JH7110_STGCLK_PCIE0_APB>;
+   clock-names = "noc", "tl", "axi", "apb";
+   resets = <&stgcrg JH7110_STGRST_PCIE0_MST0>,
+<&stgcrg JH7110_STGRST_PCIE0_SLV0>,
+<&stgcrg JH7110_STGRST_PCIE0_SLV>,
+<&stgcrg JH7110_STGRST_PCIE0_BRG>,
+<&stgcrg JH7110_STGRST_PCIE0_CORE>,
+<&stgcrg JH7110_STGRST_PCIE0_APB>;
+   reset-names = "mst0", "slv0", "slv", "brg",
+ "core", "apb";
+   status = "disabled";
+
+   pcie_intc0: interrupt-controller {
+   #address-cells = <0>;
+   #interrupt-cells = <1>;
+   interrupt-controller;
+   };
+   };
+
+   pcie1: pcie@2c00 {
+   compatible = "starfive,jh7110-pcie";
+   reg = <0x0 0x2c00 0x0 0x100
+  0x9 0xc000 0x0 0x1000>;
+   reg-names = "reg", "config";
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   ranges = <0x8200  0x0 0x3800  0x0 0x3800 
0x0 0x0800>,
+

[PATCH v5 1/3] starfive: pci: Add StarFive JH7110 pcie driver

[Minda Chen]

From: Mason Huo 

Add pcie driver for StarFive JH7110, Also add PLDA
PCIe controller common driver functions.

Several devices are tested:
a) M.2 NVMe SSD
b) Realtek 8169 Ethernet adapter.

Signed-off-by: Mason Huo 
Signed-off-by: Minda Chen 
---
 drivers/pci/Kconfig|  13 ++
 drivers/pci/Makefile   |   2 +
 drivers/pci/pcie_plda_common.c | 116 +++
 drivers/pci/pcie_plda_common.h | 118 +++
 drivers/pci/pcie_starfive_jh7110.c | 317 +
 5 files changed, 566 insertions(+)
 create mode 100644 drivers/pci/pcie_plda_common.c
 create mode 100644 drivers/pci/pcie_plda_common.h
 create mode 100644 drivers/pci/pcie_starfive_jh7110.c

diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index ef328d2652..f2c5f0be63 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -374,4 +374,17 @@ config PCIE_UNIPHIER
  Say Y here if you want to enable PCIe controller support on
  UniPhier SoCs.
 
+config PCIE_PLDA_COMMON
+   bool
+
+config PCIE_STARFIVE_JH7110
+   bool "Enable Starfive JH7110 PCIe driver"
+   select PCIE_PLDA_COMMON
+   imply STARFIVE_JH7110
+   imply CLK_JH7110
+   imply RESET_JH7110
+   help
+ Say Y here if you want to enable PLDA XpressRich PCIe controller
+ support on StarFive JH7110 SoC.
+
 endif
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 49506e7ba5..5a6974f013 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -49,3 +49,5 @@ obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o
 obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o
 obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o
 obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o
+obj-$(CONFIG_PCIE_PLDA_COMMON) += pcie_plda_common.o
+obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o
diff --git a/drivers/pci/pcie_plda_common.c b/drivers/pci/pcie_plda_common.c
new file mode 100644
index 00..005b92616a
--- /dev/null
+++ b/drivers/pci/pcie_plda_common.c
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * PLDA XpressRich PCIe host controller common functions.
+ *
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "pcie_plda_common.h"
+
+static bool plda_pcie_addr_valid(struct pcie_plda *plda, pci_dev_t bdf)
+{
+   /*
+* Single device limitation.
+* PCIe controller contain HW issue that secondary bus of
+* host bridge emumerate duplicate devices.
+* Only can access device 0 in secondary bus.
+*/
+   if (PCI_BUS(bdf) == plda->sec_busno && PCI_DEV(bdf) > 0)
+   return false;
+
+   return true;
+}
+
+static int plda_pcie_conf_address(const struct udevice *udev, pci_dev_t bdf,
+ uint offset, void **paddr)
+{
+   struct pcie_plda *priv = dev_get_priv(udev);
+   int where = PCIE_ECAM_OFFSET(PCI_BUS(bdf), PCI_DEV(bdf),
+PCI_FUNC(bdf), offset);
+
+   if (!plda_pcie_addr_valid(priv, bdf))
+   return -ENODEV;
+
+   *paddr = (void *)(priv->cfg_base + where);
+   return 0;
+}
+
+int plda_pcie_config_read(const struct udevice *udev, pci_dev_t bdf,
+ uint offset, ulong *valuep,
+ enum pci_size_t size)
+{
+   return pci_generic_mmap_read_config(udev, plda_pcie_conf_address,
+   bdf, offset, valuep, size);
+}
+
+int plda_pcie_config_write(struct udevice *udev, pci_dev_t bdf,
+  uint offset, ulong value,
+  enum pci_size_t size)
+{
+   struct pcie_plda *priv = dev_get_priv(udev);
+   int ret;
+
+   ret = pci_generic_mmap_write_config(udev, plda_pcie_conf_address,
+   bdf, offset, value, size);
+
+   /* record secondary bus number */
+   if (!ret && PCI_BUS(bdf) == dev_seq(udev) &&
+   PCI_DEV(bdf) == 0 && PCI_FUNC(bdf) == 0 &&
+   (offset == PCI_SECONDARY_BUS ||
+   (offset == PCI_PRIMARY_BUS && size != PCI_SIZE_8))) {
+   priv->sec_busno =
+   ((offset == PCI_PRIMARY_BUS) ? (value >> 8) : value) & 
0xff;
+   debug("Secondary bus number was changed to %d\n",
+ priv->sec_busno);
+   }
+   return ret;
+}
+
+int plda_pcie_set_atr_entry(struct pcie_plda *plda, phys_addr_t src_addr,
+   phys_addr_t trsl_addr, phys_size_t window_size,
+   int trsl_param)
+{
+   void __iomem *base =
+   plda->reg_base + XR3PCI_ATR_AXI4_SLV0;
+
+   /* Support AXI4 Slave 0 Address Translation Tables 0-7. */
+   if (plda->atr_table

[PATCH v6 2/3] configs: starfive-jh7110: Add support for PCIe host driver

[Minda Chen]

From: Mason Huo 

also add the nvme driver and rtl8169 support.

Signed-off-by: Mason Huo 
Signed-off-by: Minda Chen 
---
 configs/starfive_visionfive2_defconfig | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/configs/starfive_visionfive2_defconfig 
b/configs/starfive_visionfive2_defconfig
index 550d0ff3ab..ea798919be 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -16,6 +16,7 @@ CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
 CONFIG_SYS_LOAD_ADDR=0x8200
+CONFIG_SYS_PCI_64BIT=y
 CONFIG_TARGET_STARFIVE_VISIONFIVE2=y
 CONFIG_SPL_OPENSBI_LOAD_ADDR=0x4000
 CONFIG_ARCH_RV64I=y
@@ -49,9 +50,12 @@ CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_CBSIZE=256
 CONFIG_SYS_PBSIZE=276
 CONFIG_SYS_BOOTM_LEN=0x400
+CONFIG_CMD_PCI=y
 CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_SPL_CLK_COMPOSITE_CCF=y
 CONFIG_CLK_COMPOSITE_CCF=y
 CONFIG_SPL_CLK_JH7110=y
@@ -65,6 +69,12 @@ CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_ISSI=y
 CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_RTL8169=y
+CONFIG_NVME_PCI=y
+CONFIG_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCI_REGION_MULTI_ENTRY=y
+CONFIG_PCIE_STARFIVE_JH7110=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_SPL_PINCTRL=y
-- 
2.17.1

[PATCH v6 0/3] Add StarFive JH7110 PCIe drvier support

[Minda Chen]

These PCIe series patches are based on the JH7110 RISC-V SoC and VisionFive V2 
board.

The PCIe driver depends on gpio, pinctrl, clk and reset driver to do init.
The PCIe dts configuation includes all these setting.

The PCIe drivers codes has been tested on the VisionFive V2 boards.
The test devices includes M.2 NVMe SSD and Realtek 8169 Ethernet adapter.

previous patch version

v1: 
https://patchwork.ozlabs.org/project/uboot/cover/20230223105240.15180-1-minda.c...@starfivetech.com/
v2: 
https://patchwork.ozlabs.org/project/uboot/cover/20230308054833.95730-1-minda.c...@starfivetech.com/
v3: 
https://patchwork.ozlabs.org/project/uboot/cover/20230329100143.10724-1-minda.c...@starfivetech.com/
v4: 
https://patchwork.ozlabs.org/project/uboot/cover/20230411010209.76561-1-minda.c...@starfivetech.com/
v5: 
https://patchwork.ozlabs.org/project/uboot/cover/20230423105859.125764-1-minda.c...@starfivetech.com/

changes
  v6
   patch 2
1. Change one VisionFive2 config file.
   patch 3
1. remove the pcie interrupt-controller. interrupts setting revert to 
origin.

setting.
  v5
   patch 1
1. split PLDA controller driver codes to pcie_plda_common.c
2. correct the codes of record secondary number. 
   patch 3
1. change the pcie dtsi config. make them the same with kernel.
 
  v4
   patch 1
1. Remove the IDS_REVISION_ID macros.
2. Replace sec_busno to first_busno in starfive_pcie
3. Remove starfive_pcie_off_conf function.
4. Replace "imply" to "depends on" in PCIe Kconfig.
5 .Check sec_busno in starfive_pcie_addr_valid.
 
  v3
   patch 1
1. remove the read vendor ID delay
2. remove starfive_pcie_hide_rc_bar function. do not hide host
bridge BAR write.
3. Using PCIE_ECAM_OFFSET and PCI_CLASS_BRIDGE_PCI_NORMAL macros.
4. Add comments for bus and address limitation reason in function
   starfive_pcie_addr_valid
5. Change the multiple line comments in Line 373
6. Using gpio_request_by_name to get PCIe reset gpio,and using
   dm_gpio_set_value set GPIO value.
  patch 2
1. support PCIeboth 12a and 13b vf2 board.  
  patch 3
1. reset dts change to reset-gpio.

  v2
   1. remove clock commit. The pcie clocks change has been includeded in [1].
   2. Using GENMASK marco1 in patch1.
   3. remove the syscon dts node in patch3. The syscon dts dts node has been
  included in [1]. 


Mason Huo (3):
  starfive: pci: Add StarFive JH7110 pcie driver
  configs: starfive-jh7110: Add support for PCIe host driver
  riscv: dts: starfive: Enable PCIe host controller

 .../dts/jh7110-starfive-visionfive-2.dtsi |  11 +
 arch/riscv/dts/jh7110.dtsi|  74 
 configs/starfive_visionfive2_defconfig|  10 +
 drivers/pci/Kconfig   |  13 +
 drivers/pci/Makefile  |   2 +
 drivers/pci/pcie_plda_common.c| 116 +++
 drivers/pci/pcie_plda_common.h| 118 +++
 drivers/pci/pcie_starfive_jh7110.c| 317 ++
 8 files changed, 661 insertions(+)
 create mode 100644 drivers/pci/pcie_plda_common.c
 create mode 100644 drivers/pci/pcie_plda_common.h
 create mode 100644 drivers/pci/pcie_starfive_jh7110.c


base-commit: c9c2c95d4cd27fe0cd41fe13a863899d268f973c
-- 
2.17.1

[PATCH v6 1/3] starfive: pci: Add StarFive JH7110 pcie driver

[Minda Chen]

From: Mason Huo 

Add pcie driver for StarFive JH7110, Also add PLDA
PCIe controller common driver functions.

Several devices are tested:
a) M.2 NVMe SSD
b) Realtek 8169 Ethernet adapter.

Signed-off-by: Mason Huo 
Signed-off-by: Minda Chen 
Acked-by: Pali Rohár 
---
 drivers/pci/Kconfig|  13 ++
 drivers/pci/Makefile   |   2 +
 drivers/pci/pcie_plda_common.c | 116 +++
 drivers/pci/pcie_plda_common.h | 118 +++
 drivers/pci/pcie_starfive_jh7110.c | 317 +
 5 files changed, 566 insertions(+)
 create mode 100644 drivers/pci/pcie_plda_common.c
 create mode 100644 drivers/pci/pcie_plda_common.h
 create mode 100644 drivers/pci/pcie_starfive_jh7110.c

diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index ef328d2652..f2c5f0be63 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -374,4 +374,17 @@ config PCIE_UNIPHIER
  Say Y here if you want to enable PCIe controller support on
  UniPhier SoCs.
 
+config PCIE_PLDA_COMMON
+   bool
+
+config PCIE_STARFIVE_JH7110
+   bool "Enable Starfive JH7110 PCIe driver"
+   select PCIE_PLDA_COMMON
+   imply STARFIVE_JH7110
+   imply CLK_JH7110
+   imply RESET_JH7110
+   help
+ Say Y here if you want to enable PLDA XpressRich PCIe controller
+ support on StarFive JH7110 SoC.
+
 endif
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 49506e7ba5..5a6974f013 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -49,3 +49,5 @@ obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o
 obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o
 obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o
 obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o
+obj-$(CONFIG_PCIE_PLDA_COMMON) += pcie_plda_common.o
+obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o
diff --git a/drivers/pci/pcie_plda_common.c b/drivers/pci/pcie_plda_common.c
new file mode 100644
index 00..005b92616a
--- /dev/null
+++ b/drivers/pci/pcie_plda_common.c
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * PLDA XpressRich PCIe host controller common functions.
+ *
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "pcie_plda_common.h"
+
+static bool plda_pcie_addr_valid(struct pcie_plda *plda, pci_dev_t bdf)
+{
+   /*
+* Single device limitation.
+* PCIe controller contain HW issue that secondary bus of
+* host bridge emumerate duplicate devices.
+* Only can access device 0 in secondary bus.
+*/
+   if (PCI_BUS(bdf) == plda->sec_busno && PCI_DEV(bdf) > 0)
+   return false;
+
+   return true;
+}
+
+static int plda_pcie_conf_address(const struct udevice *udev, pci_dev_t bdf,
+ uint offset, void **paddr)
+{
+   struct pcie_plda *priv = dev_get_priv(udev);
+   int where = PCIE_ECAM_OFFSET(PCI_BUS(bdf), PCI_DEV(bdf),
+PCI_FUNC(bdf), offset);
+
+   if (!plda_pcie_addr_valid(priv, bdf))
+   return -ENODEV;
+
+   *paddr = (void *)(priv->cfg_base + where);
+   return 0;
+}
+
+int plda_pcie_config_read(const struct udevice *udev, pci_dev_t bdf,
+ uint offset, ulong *valuep,
+ enum pci_size_t size)
+{
+   return pci_generic_mmap_read_config(udev, plda_pcie_conf_address,
+   bdf, offset, valuep, size);
+}
+
+int plda_pcie_config_write(struct udevice *udev, pci_dev_t bdf,
+  uint offset, ulong value,
+  enum pci_size_t size)
+{
+   struct pcie_plda *priv = dev_get_priv(udev);
+   int ret;
+
+   ret = pci_generic_mmap_write_config(udev, plda_pcie_conf_address,
+   bdf, offset, value, size);
+
+   /* record secondary bus number */
+   if (!ret && PCI_BUS(bdf) == dev_seq(udev) &&
+   PCI_DEV(bdf) == 0 && PCI_FUNC(bdf) == 0 &&
+   (offset == PCI_SECONDARY_BUS ||
+   (offset == PCI_PRIMARY_BUS && size != PCI_SIZE_8))) {
+   priv->sec_busno =
+   ((offset == PCI_PRIMARY_BUS) ? (value >> 8) : value) & 
0xff;
+   debug("Secondary bus number was changed to %d\n",
+ priv->sec_busno);
+   }
+   return ret;
+}
+
+int plda_pcie_set_atr_entry(struct pcie_plda *plda, phys_addr_t src_addr,
+   phys_addr_t trsl_addr, phys_size_t window_size,
+   int trsl_param)
+{
+   void __iomem *base =
+   plda->reg_base + XR3PCI_ATR_AXI4_SLV0;
+
+   /* Support AXI4 Slave 0 Address Translation Tables 0-7. */
+   if (plda->atr_table

[PATCH v6 3/3] riscv: dts: starfive: Enable PCIe host controller

[Minda Chen]

From: Mason Huo 

Enable and add pinctrl configuration for PCIe host controller.
Also add JH7110 stg syscon configuration.

Signed-off-by: Mason Huo 
Signed-off-by: Minda Chen 
---
 .../dts/jh7110-starfive-visionfive-2.dtsi | 11 +++
 arch/riscv/dts/jh7110.dtsi| 74 +++
 2 files changed, 85 insertions(+)

diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi 
b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index c6b6dfa940..12245576ac 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -7,6 +7,7 @@
 
 #include "jh7110.dtsi"
 #include 
+#include 
 / {
aliases {
serial0 = &uart0;
@@ -300,6 +301,16 @@
};
 };
 
+&pcie0 {
+   reset-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
+   status = "disabled";
+};
+
+&pcie1 {
+   reset-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;
+   status = "okay";
+};
+
 &syscrg {
assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
  <&syscrg JH7110_SYSCLK_BUS_ROOT>,
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index bd60879615..c7b071e743 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -569,5 +569,79 @@
gpio-controller;
#gpio-cells = <2>;
};
+
+   pcie0: pcie@2b00 {
+   compatible = "starfive,jh7110-pcie";
+   reg = <0x0 0x2b00 0x0 0x100
+  0x9 0x4000 0x0 0x1000>;
+   reg-names = "reg", "config";
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   ranges = <0x8200  0x0 0x3000  0x0 0x3000 
0x0 0x0800>,
+<0xc300  0x9 0x  0x9 0x 
0x0 0x4000>;
+   interrupts = <56>;
+   interrupt-parent = <&plic>;
+   interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+   interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
+   <0x0 0x0 0x0 0x2 &plic 0x2>,
+   <0x0 0x0 0x0 0x3 &plic 0x3>,
+   <0x0 0x0 0x0 0x4 &plic 0x4>;
+   msi-parent = <&plic>;
+   device_type = "pci";
+   starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 
0x1b8>;
+   bus-range = <0x0 0xff>;
+   clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
+<&stgcrg JH7110_STGCLK_PCIE0_TL>,
+<&stgcrg JH7110_STGCLK_PCIE0_AXI>,
+<&stgcrg JH7110_STGCLK_PCIE0_APB>;
+   clock-names = "noc", "tl", "axi", "apb";
+   resets = <&stgcrg JH7110_STGRST_PCIE0_MST0>,
+<&stgcrg JH7110_STGRST_PCIE0_SLV0>,
+<&stgcrg JH7110_STGRST_PCIE0_SLV>,
+<&stgcrg JH7110_STGRST_PCIE0_BRG>,
+<&stgcrg JH7110_STGRST_PCIE0_CORE>,
+<&stgcrg JH7110_STGRST_PCIE0_APB>;
+   reset-names = "mst0", "slv0", "slv", "brg",
+ "core", "apb";
+   status = "disabled";
+   };
+
+   pcie1: pcie@2c00 {
+   compatible = "starfive,jh7110-pcie";
+   reg = <0x0 0x2c00 0x0 0x100
+  0x9 0xc000 0x0 0x1000>;
+   reg-names = "reg", "config";
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   ranges = <0x8200  0x0 0x3800  0x0 0x3800 
0x0 0x0800>,
+<0xc300  0x9 0x8000  0x9 0x8000 
0x0 0x4000>;
+   interrupts = <57>;
+   interrupt-parent = <&plic>;
+   interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+   interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
+ 

Re: [PATCH v8 1/4] i2c: designware: Add Kconfig for designware_i2c_pci.c

[Minda Chen]

On 2023/7/26 11:07, Leo Liang wrote:
> On Tue, Jul 25, 2023 at 05:46:47PM +0800, Minda Chen wrote:
>> As the Designware_i2c_pci.c uses ACPI APIs, If some SoCs (StarFive
>> JH7110) contain Designware i2c and PCI but do not use ACPI,
>> This file will be can't be compiled. So add a new Kconfig for
>> designware_i2c_pci.c, which depends on ACPIGEN
>> 
>> Signed-off-by: Minda Chen 
>> ---
>>  drivers/i2c/Kconfig  | 9 +
>>  drivers/i2c/Makefile | 4 +---
>>  2 files changed, 10 insertions(+), 3 deletions(-)
> 
> Reviewed-by: Leo Yu-Chi Liang 

Thanks. Does this patch require Heiko review? 

Re: [PULL] u-boot-riscv/master

[Minda Chen]

On 2023/8/2 17:31, Leo Liang wrote:
> Hi Bin,
> 
> On Wed, Aug 02, 2023 at 02:27:29PM +0800, Bin Meng wrote:
>> Hi Leo,
>> 
>> On Wed, Aug 2, 2023 at 1:49 PM Leo Liang  wrote:
>> >
>> > Hi Tom,
>> >
>> > The following changes since commit 
>> > 7755b2200777f72dca87dd169138e95f011bbcb9:
>> >
>> >   Merge tag 'x86-pull-20230801' of 
>> > https://source.denx.de/u-boot/custodians/u-boot-x86 (2023-08-01 11:57:55 
>> > -0400)
>> >
>> > are available in the Git repository at:
>> >
>> >   https://source.denx.de/u-boot/custodians/u-boot-riscv.git
>> >
>> > for you to fetch changes up to 093bd0354e5b947b0bd634bf5ed4041ba075b57d:
>> >
>> >   acpi: Add missing RISC-V acpi_table header (2023-08-02 11:02:33 +0800)
>> >
>> > CI result shows no issue: 
>> > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/17177
>> >
>> > 
>> >
>> > + Fix compilation error for CI when enabling RTL8169 driver
>> > + Fix compilation error for pci_mmc.c by adding acpi_table header file
>> > + Support StarFive JH7110 PCIe driver
>> > + Enable PCI on Unmatched board
>> >
>> > 
>> >
>> > Heinrich Schuchardt (2):
>> >   riscv: sifive: initialize PCI on Unmatched
>> >   acpi: Add missing RISC-V acpi_table header
>> >
>> > Mason Huo (3):
>> >   starfive: pci: Add StarFive JH7110 pcie driver
>> >   configs: starfive-jh7110: Add support for PCIe host driver
>> >   riscv: dts: starfive: Enable PCIe host controller
>> >
>> > Minda Chen (5):
>> >   i2c: designware: Add Kconfig for designware_i2c_pci.c
>> >   net: rtl8169: Fix compile warning in rtl8169
>> >   net: rtl8169: Fix DMA minimal aligned compile warning in RISC-V
>> >   net: rtl8169: Add one device ID 0x8161
>> >   configs: starfive-jh7110: Add CONFIG_RTL8169
>> >
>> 
>> Looks the second half of this series is missed?
>> https://patchwork.ozlabs.org/project/uboot/list/?series=365237
>> 
>> Regards,
>> Bin
> 
> Thanks for the reminder!
> I did omit this second half of the series by accident!
> I will re-send the PR again ASAP!
> 
> Best regards,
> Leo
Hi Leo and Bin
Thanks!

[PATCH v1 2/4] riscv: dts: starfive: Enable pcie0 dts node

[Minda Chen]

In StarFive VF2 board. pcie0 connect to VTI usb controller.
Enable it to support usb host.

Signed-off-by: Minda Chen 
---
 arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi 
b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index bf7fdb4dd6..e40f57a150 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -311,7 +311,7 @@
 
 &pcie0 {
reset-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
-   status = "disabled";
+   status = "okay";
 };
 
 &pcie1 {
-- 
2.17.1

[PATCH v1 1/4] pci: plda: Get correct ECAM offset in multiple PCIe RC case

[Minda Chen]

Get the correct ECAM offset and record the secondary bus
number in Multiple RC case.

Signed-off-by: Minda Chen 
---
 drivers/pci/pcie_plda_common.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/pcie_plda_common.c b/drivers/pci/pcie_plda_common.c
index 005b92616a..cd74bb4711 100644
--- a/drivers/pci/pcie_plda_common.c
+++ b/drivers/pci/pcie_plda_common.c
@@ -36,8 +36,8 @@ static int plda_pcie_conf_address(const struct udevice *udev, 
pci_dev_t bdf,
  uint offset, void **paddr)
 {
struct pcie_plda *priv = dev_get_priv(udev);
-   int where = PCIE_ECAM_OFFSET(PCI_BUS(bdf), PCI_DEV(bdf),
-PCI_FUNC(bdf), offset);
+   int where = PCIE_ECAM_OFFSET(PCI_BUS(bdf) - dev_seq(udev),
+PCI_DEV(bdf), PCI_FUNC(bdf), offset);
 
if (!plda_pcie_addr_valid(priv, bdf))
return -ENODEV;
@@ -71,6 +71,7 @@ int plda_pcie_config_write(struct udevice *udev, pci_dev_t 
bdf,
(offset == PCI_PRIMARY_BUS && size != PCI_SIZE_8))) {
priv->sec_busno =
((offset == PCI_PRIMARY_BUS) ? (value >> 8) : value) & 
0xff;
+   priv->sec_busno += dev_seq(udev);
debug("Secondary bus number was changed to %d\n",
  priv->sec_busno);
}
-- 
2.17.1

[PATCH v1 3/4] riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHE_LINE_SIZE

[Minda Chen]

Some devices need SYS_CACHE_LINE_SIZE macro. Add StarFive
SYS_CACHE_SHIFT_6 to enable it.

Signed-off-by: Minda Chen 
---
 arch/riscv/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 867cbcbe74..15da2a8559 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -26,6 +26,7 @@ config TARGET_SIFIVE_UNMATCHED
 
 config TARGET_STARFIVE_VISIONFIVE2
bool "Support StarFive VisionFive2 Board"
+   select SYS_CACHE_SHIFT_6
 
 config TARGET_TH1520_LPI4A
bool "Support Sipeed's TH1520 Lichee PI 4A Board"
-- 
2.17.1

[PATCH v1 4/4] configs: riscv: starfive: Add VF2 PCIe XHCI config support

[Minda Chen]

Add PCI_XHCI support to enable usb3-host functions.
Also add usb command and keyboard config.

Signed-off-by: Minda Chen 
---
 configs/starfive_visionfive2_defconfig | 5 +
 1 file changed, 5 insertions(+)

diff --git a/configs/starfive_visionfive2_defconfig 
b/configs/starfive_visionfive2_defconfig
index 5d8a8e28cb..a70ada394f 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -65,6 +65,7 @@ CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
 CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_OF_BOARD=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
@@ -111,3 +112,7 @@ CONFIG_PINCTRL_STARFIVE=y
 CONFIG_SYS_NS16550=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_TIMER_EARLY=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PCI=y
+CONFIG_USB_KEYBOARD=y
-- 
2.17.1

[PATCH v1 0/4] Add VF2 USB host support.

[Minda Chen]

StarFive VF2 VTI usb-host controller connect to pcie0 RC.
Enable pcie0 first the enable USB function.

patch1 is Get the correct ECAM offset in multiple PCIe RC.
patch2 is enable pcie0 dts node.
patch3 is enable SYS_CACHE_LINE_SIZE
patch4 is Add VF2 USB related configuration.

Minda Chen (4):
  pci: plda: Get correct ECAM offset in multiple PCIe RC case
  riscv: dts: starfive: Enable pcie0 dts node
  riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHE_LINE_SIZE
  configs: riscv: starfive: Add VF2 PCIe XHCI config support

 arch/riscv/Kconfig   | 1 +
 arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 2 +-
 configs/starfive_visionfive2_defconfig   | 5 +
 drivers/pci/pcie_plda_common.c   | 5 +++--
 4 files changed, 10 insertions(+), 3 deletions(-)

base-commit: 38dedebc547f795efc3daad17f7c013c515e1285
-- 
2.17.1

Re: [PATCH v1 3/4] riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHE_LINE_SIZE

[Minda Chen]

On 2023/8/3 12:49, Bin Meng wrote:
> On Thu, Aug 3, 2023 at 11:22 AM Minda Chen  
> wrote:
>>
>> Some devices need SYS_CACHE_LINE_SIZE macro. Add StarFive
>> SYS_CACHE_SHIFT_6 to enable it.
>>
>> Signed-off-by: Minda Chen 
>> ---
>>  arch/riscv/Kconfig | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
>> index 867cbcbe74..15da2a8559 100644
>> --- a/arch/riscv/Kconfig
>> +++ b/arch/riscv/Kconfig
>> @@ -26,6 +26,7 @@ config TARGET_SIFIVE_UNMATCHED
>>
>>  config TARGET_STARFIVE_VISIONFIVE2
>> bool "Support StarFive VisionFive2 Board"
>> +   select SYS_CACHE_SHIFT_6
>>
>>  config TARGET_TH1520_LPI4A
>> bool "Support Sipeed's TH1520 Lichee PI 4A Board"
> 
> This needs to go into arch/riscv/cpu/jh7110/Kconfig::STARFIVE_JH7110
> 
> Regards,
> Bin
ok, thanks

[RESEND, v1 1/4] pci: plda: Get correct ECAM offset in multiple PCIe RC case

[Minda Chen]

Get the correct ECAM offset and record the secondary bus
number in Multiple RC case.

Signed-off-by: Minda Chen 
---
 drivers/pci/pcie_plda_common.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/pcie_plda_common.c b/drivers/pci/pcie_plda_common.c
index 005b92616a..cd74bb4711 100644
--- a/drivers/pci/pcie_plda_common.c
+++ b/drivers/pci/pcie_plda_common.c
@@ -36,8 +36,8 @@ static int plda_pcie_conf_address(const struct udevice *udev, 
pci_dev_t bdf,
  uint offset, void **paddr)
 {
struct pcie_plda *priv = dev_get_priv(udev);
-   int where = PCIE_ECAM_OFFSET(PCI_BUS(bdf), PCI_DEV(bdf),
-PCI_FUNC(bdf), offset);
+   int where = PCIE_ECAM_OFFSET(PCI_BUS(bdf) - dev_seq(udev),
+PCI_DEV(bdf), PCI_FUNC(bdf), offset);
 
if (!plda_pcie_addr_valid(priv, bdf))
return -ENODEV;
@@ -71,6 +71,7 @@ int plda_pcie_config_write(struct udevice *udev, pci_dev_t 
bdf,
(offset == PCI_PRIMARY_BUS && size != PCI_SIZE_8))) {
priv->sec_busno =
((offset == PCI_PRIMARY_BUS) ? (value >> 8) : value) & 
0xff;
+   priv->sec_busno += dev_seq(udev);
debug("Secondary bus number was changed to %d\n",
  priv->sec_busno);
}
-- 
2.17.1

[RESEND,v1 0/4] Add StarFive VF2 USB host support.

[Minda Chen]

StarFive VF2 VLI usb-host controller connect to pcie0 RC.
Enable pcie0 first the enable USB function.

patch1 is Get the correct ECAM offset in multiple PCIe RC.
patch2 is enable pcie0 dts node.
patch3 is enable SYS_CACHELINE_SIZE
patch4 is Add VF2 USB related configuration.

Minda Chen (4):
  pci: plda: Get correct ECAM offset in multiple PCIe RC case
  riscv: dts: starfive: Enable pcie0 dts node
  riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHELINE_SIZE
  configs: riscv: starfive: Add VF2 PCIe USB3 XHCI support

 arch/riscv/cpu/jh7110/Kconfig| 1 +
 arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 2 +-
 configs/starfive_visionfive2_defconfig   | 5 +
 drivers/pci/pcie_plda_common.c   | 5 +++--
 4 files changed, 10 insertions(+), 3 deletions(-)

base-commit: 38dedebc547f795efc3daad17f7c013c515e1285
-- 
2.17.1

[RESEND, v1 4/4] configs: riscv: starfive: Add VF2 PCIe USB3 XHCI support

[Minda Chen]

Add XHCI_PCI to enable usb3-host functions.
Also add usb command and keyboard config.

Signed-off-by: Minda Chen 
---
 configs/starfive_visionfive2_defconfig | 5 +
 1 file changed, 5 insertions(+)

diff --git a/configs/starfive_visionfive2_defconfig 
b/configs/starfive_visionfive2_defconfig
index 5d8a8e28cb..a70ada394f 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -65,6 +65,7 @@ CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
 CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_OF_BOARD=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
@@ -111,3 +112,7 @@ CONFIG_PINCTRL_STARFIVE=y
 CONFIG_SYS_NS16550=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_TIMER_EARLY=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PCI=y
+CONFIG_USB_KEYBOARD=y
-- 
2.17.1

[RESEND, v1 3/4] riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHELINE_SIZE

[Minda Chen]

Some device driver need SYS_CACHELINE_SIZE macro. Add StarFive
SYS_CACHE_SHIFT_6 to enable it.

Signed-off-by: Minda Chen 
---
 arch/riscv/cpu/jh7110/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig
index 4d9581165b..c1d3e6ada2 100644
--- a/arch/riscv/cpu/jh7110/Kconfig
+++ b/arch/riscv/cpu/jh7110/Kconfig
@@ -13,6 +13,7 @@ config STARFIVE_JH7110
select SUPPORT_SPL
select SPL_RAM if SPL
select SPL_STARFIVE_DDR
+   select SYS_CACHE_SHIFT_6
select PINCTRL_STARFIVE_JH7110
imply MMC
imply MMC_BROKEN_CD
-- 
2.17.1

[RESEND,v1 2/4] riscv: dts: starfive: Enable pcie0 dts node

[Minda Chen]

In StarFive VF2 board. pcie0 connect to VTI usb controller.
Enable it to support usb host.

Signed-off-by: Minda Chen 
---
 arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi 
b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index bf7fdb4dd6..e40f57a150 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -311,7 +311,7 @@
 
 &pcie0 {
reset-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
-   status = "disabled";
+   status = "okay";
 };
 
 &pcie1 {
-- 
2.17.1

Re: v2024.07-rc4 issues on VisionFive v2

[Minda Chen]

> 
> Hey,
> 
> After going from Vendor SPL/OpenSBI/U-Boot to OpenSBI v1.4++ plus
> v2024.07-rc4 SPL/U-Boot I ran into a boot loop problem relating to
> PCI:
>   U-Boot 2024.07-rc4 (Jun 13 2024 - 15:09:34 +0100)
> 
>   CPU:   sifive,u74-mc
>   Model: StarFive VisionFive 2 v1.2A
>   DRAM:  4 GiB
>   Core:  136 devices, 26 uclasses, devicetree: board
>   WDT:   Not starting watchdog@1307
>   MMC:   mmc@1601: 0, mmc@1602: 1
>   Loading Environment from SPIFlash... SF: Detected gd25lq128 with page
> size 256 Bytes, erase size 4 KiB, total 16 MiB
>   OK
>   StarFive EEPROM format v2
> 
>   EEPROM INFO
>   Vendor : StarFive Technology Co., Ltd.
>   Product full SN: VF7110A1-2249-D004E000-0540
>   data version: 0x2
>   PCB revision: 0xa1
>   BOM revision: A
>   Ethernet MAC0 address: 6c:cf:39:00:17:95
>   Ethernet MAC1 address: 6c:cf:39:00:17:96
>   EEPROM INFO
> 
>   starfive_7110_pcie pcie@2b00: Starfive PCIe bus probed.
>   starfive_7110_pcie pcie@2c00: Starfive PCIe bus probed.
>   In:serial@1000
>   Out:   serial@1000
>   Err:   serial@1000
>   Net:   eth0: ethernet@1603, eth1: ethernet@1604
>   starting USB...
>   Bus xhci_pci: Register 5000420 NbrPorts 5
>   Starting the controller
>   USB XHCI 1.00
>   scanning bus xhci_pci for devices...
>   U-Boot SPL 2024.07-rc4 (Jun 13 2024 - 15:09:34 +0100)
>   DDR version: dc2e84f0.
>   Trying to boot from SPI
> 
> This only appeared after I refreshed the environment by running.
> `env default -a -f; env save`. Before that things worked "fine", I suppose 
> because
> nothing actually touched PCI. I've just disabled PCI for now and things are
> working once more. I've not attempted to bisect/debug this, cos that's not the
> fastest process while running U-Boot out of flash.
> 
> In case it is relevant, the board I have is one of the "super early bird" 
> ones.
> 
> Cheers,
> Conor.

CC  Hal

Re: [PATCH v1 0/7] Add Starfive JH7110 Cadence USB driver

[Minda Chen]

> 
> Minda, can you test USB Host function on VisionFive2? I guess that it is
> connected to the USB-C port. For the boards with JH7110 and not any
> VL805 USB controller this Cadence USB is the only way to have host USB. It is
> very much wanted to have host USB. Thanks! -E
> 

In VF2, PCIe0 connect with VL805 USB 3.0 host controller. Now PCIe driver have
commit to Uboot upstream code. USB 3.0 can be used in uboot upstream code.
Milk-v mars also connect VL805 and can use USB 3.0 host too.

You can use "pci e" command to active USB 3.0 host controller and then "usb 
reset" to 
scan usb devices.  If you have any issue about this. Also reply it in this. 
Thanks.

> On Sun, May 19, 2024 at 11:20 PM Minda Chen 
> wrote:
> >
> >
> >
> > >
> > > Hi, there is a compile warning. I don't know why.
> > >
> > > On Sat, May 4, 2024 at 8:04 AM Minda Chen
> > > 
> > > wrote:
> > > >
> > > > Add Starfive JH7110 Cadence USB driver and related PHY driver.
> > > > So the codes can be used in visionfive2 and milkv 7110 board.
> > > >
> > > > The driver is almost the same with kernel driver.
> > > >
> > > > patch1: Add set phy mode function in cdns3 core driver
> > > >     which is used by Starfive.
> > > >
> > > > patch2-3: USB and PCIe 2.0 (usb 3.0) PHY drivier
> > > > patch4: Cadence USB wrapper driver.
> > > > patch5-7 dts, config and maintainers update.
> > > >
> > > > Minda Chen (7):
> > > >   usb: cdns3: Set USB PHY mode in cdns3_probe()
> > > >   phy: starfive: Add Starfive JH7110 USB 2.0 PHY driver
> > > >   phy: starfive: Add Starfive JH7110 PCIe 2.0 PHY driver
> > > >   usb: cdns: starfive: Add cdns USB driver
> > > >   configs: starfive: Add visionfive2 cadence USB configuration
> > > >   dts: starfive: Add JH7110 Cadence USB dts node
> > > >   MAINTAINERS: Update Starfive visionfive2 maintain files.
> > > >
> > > >  .../dts/jh7110-starfive-visionfive-2.dtsi |   5 +
> > > >  arch/riscv/dts/jh7110.dtsi|  52 +
> > > >  board/starfive/visionfive2/MAINTAINERS|   2 +
> > > >  configs/starfive_visionfive2_defconfig|   9 +
> > > >  drivers/phy/Kconfig   |   1 +
> > > >  drivers/phy/Makefile  |   1 +
> > > >  drivers/phy/starfive/Kconfig  |  19 ++
> > > >  drivers/phy/starfive/Makefile |   7 +
> > > >  drivers/phy/starfive/phy-jh7110-pcie.c| 211
> > > ++
> > > >  drivers/phy/starfive/phy-jh7110-usb2.c| 135 +++
> > > >  drivers/usb/cdns3/Kconfig |   7 +
> > > >  drivers/usb/cdns3/Makefile|   2 +
> > > >  drivers/usb/cdns3/cdns3-starfive.c| 184
> +++
> > > >  drivers/usb/cdns3/core.c  |  17 ++
> > > >  14 files changed, 652 insertions(+)  create mode 100644
> > > > drivers/phy/starfive/Kconfig  create mode 100644
> > > > drivers/phy/starfive/Makefile  create mode 100644
> > > > drivers/phy/starfive/phy-jh7110-pcie.c
> > > >  create mode 100644 drivers/phy/starfive/phy-jh7110-usb2.c
> > > >  create mode 100644 drivers/usb/cdns3/cdns3-starfive.c
> > > >
> > > >
> > > > base-commit: 174ac987655c888017c82df1883c0c2ea0dc2495
> > > > --
> > > > 2.17.1
> > > >
> > >
> > > The compile warning as follows:
> > >
> > > In file included from
> > > /home/user/source/u-boot.git/drivers/usb/cdns3/gadget.c:70:
> > > /home/user/source/u-boot.git/include/linux/bitmap.h: In function
> > > ‘bitmap_find_next_zero_area’:
> > > /home/user/source/u-boot.git/include/linux/bitmap.h:170:17: warning:
> > > implicit declaration of function ‘find_next_zero_bit’; did you mean
> > > ‘find_next_bit’? [-Wimplicit-function-declaration]
> > >   170 | index = find_next_zero_bit(map, size, start);
> > >   | ^~
> > >   | find_next_bit
> > >   CC  drivers/usb/cdns3/ep0.o
> > > In file included from
> > > /home/user/source/u-boot.git/include/linux/usb/composite.h:26,
> > >  from
> > > /home/user/source/u-boot.git/drivers/usb/cdns3/ep0.c:19:
> > > /home/user/source/u-boot.git/include/linux/bitmap.h: In function
> > > ‘bitmap_find_next_zero_area’:
> > > /home/user/source/u-boot.git/include/linux/bitmap.h:170:17: warning:
> > > implicit declaration of function ‘find_next_zero_bit’; did you mean
> > > ‘find_next_bit’? [-Wimplicit-function-declaration]
> > >   170 | index = find_next_zero_bit(map, size, start);
> > >   | ^~
> > >   | find_next_bit
> > >
> > >
> > > Is this something missing in the patch series?
> > >
> > > -E
> >
> > I have not noticed this. I just check this it is risc-v code do not contain
> "find_next_zero_bit" macro define.

Re: [PATCH v1 0/7] Add Starfive JH7110 Cadence USB driver

[Minda Chen]

> 
> Hi,
> 
> On Sun, Jun 23, 2024 at 6:28 PM Minda Chen 
> wrote:
> >
> >
> >
> > >
> > > Minda, can you test USB Host function on VisionFive2? I guess that
> > > it is connected to the USB-C port. For the boards with JH7110 and
> > > not any
> > > VL805 USB controller this Cadence USB is the only way to have host
> > > USB. It is very much wanted to have host USB. Thanks! -E
> > >
> >
> > In VF2, PCIe0 connect with VL805 USB 3.0 host controller. Now PCIe
> > driver have commit to Uboot upstream code. USB 3.0 can be used in uboot
> upstream code.
> > Milk-v mars also connect VL805 and can use USB 3.0 host too.
> 
> No no I am asking about Cadence USB of JH7110 CPU. This VL805 is not the
> question, sorry that my question was not easy to understand before.
> 
> >
> > You can use "pci e" command to active USB 3.0 host controller and then
> > "usb reset" to scan usb devices.  If you have any issue about this. Also 
> > reply it
> in this. Thanks.
> 
> Can you show that Host USB is functioning on VF2 with the JH7110 CPU Cadence
> USB, not the VL805 controller?
> 
VF2 cadence USB is dr mode device.I cant test is with host.

> This is needed so Milk-V Mars CM and Pine64 Star64 can have USB Host.
> There is no use of VL805 and we need JH7110 Cadence USB then.
> 
> Thanks!
> 
> -E
> 
Okay. I will test cadence USB host in star64 board.

> >
> > > On Sun, May 19, 2024 at 11:20 PM Minda Chen
> > > 
> > > wrote:
> > > >
> > > >
> > > >
> > > > >
> > > > > Hi, there is a compile warning. I don't know why.
> > > > >
> > > > > On Sat, May 4, 2024 at 8:04 AM Minda Chen
> > > > > 
> > > > > wrote:
> > > > > >
> > > > > > Add Starfive JH7110 Cadence USB driver and related PHY driver.
> > > > > > So the codes can be used in visionfive2 and milkv 7110 board.
> > > > > >
> > > > > > The driver is almost the same with kernel driver.
> > > > > >
> > > > > > patch1: Add set phy mode function in cdns3 core driver
> > > > > > which is used by Starfive.
> > > > > >
> > > > > > patch2-3: USB and PCIe 2.0 (usb 3.0) PHY drivier
> > > > > > patch4: Cadence USB wrapper driver.
> > > > > > patch5-7 dts, config and maintainers update.
> > > > > >
> > > > > > Minda Chen (7):
> > > > > >   usb: cdns3: Set USB PHY mode in cdns3_probe()
> > > > > >   phy: starfive: Add Starfive JH7110 USB 2.0 PHY driver
> > > > > >   phy: starfive: Add Starfive JH7110 PCIe 2.0 PHY driver
> > > > > >   usb: cdns: starfive: Add cdns USB driver
> > > > > >   configs: starfive: Add visionfive2 cadence USB configuration
> > > > > >   dts: starfive: Add JH7110 Cadence USB dts node
> > > > > >   MAINTAINERS: Update Starfive visionfive2 maintain files.
> > > > > >
> > > > > >  .../dts/jh7110-starfive-visionfive-2.dtsi |   5 +
> > > > > >  arch/riscv/dts/jh7110.dtsi|  52 +
> > > > > >  board/starfive/visionfive2/MAINTAINERS|   2 +
> > > > > >  configs/starfive_visionfive2_defconfig|   9 +
> > > > > >  drivers/phy/Kconfig   |   1 +
> > > > > >  drivers/phy/Makefile  |   1 +
> > > > > >  drivers/phy/starfive/Kconfig  |  19 ++
> > > > > >  drivers/phy/starfive/Makefile |   7 +
> > > > > >  drivers/phy/starfive/phy-jh7110-pcie.c| 211
> > > > > ++
> > > > > >  drivers/phy/starfive/phy-jh7110-usb2.c| 135 +++
> > > > > >  drivers/usb/cdns3/Kconfig |   7 +
> > > > > >  drivers/usb/cdns3/Makefile|   2 +
> > > > > >  drivers/usb/cdns3/cdns3-starfive.c| 184
> > > +++
> > > > > >  drivers/usb/cdns3/core.c  |  17 ++
> > > > > >  14 files changed, 652 insertions(+)  create mode 100644
> > > > > > drivers/phy/starfive/Kconfig  create mode 100644
> > > > > > drivers/phy/starfive/Makefile  create mode 100644
> > > > > > drivers

[PATCH v2 0/7] Add Starfive JH7110 Cadence USB driver

[Minda Chen]

Add Starfive JH7110 Cadence USB driver and related PHY driver.
So the codes can be used in visionfive2 and star64 7110 board.

The driver is almost the same with kernel driver.

Test with Star64 JH7110 board USB 3.0 + USB 2.0 host.
The code can work.

- Star64 using USB 3.0 and USB 2.0 host must add below board dts setting.

1. usb pin setting
usb_pins: usb0-0 {
driver-vbus-pin {
pinmux = ;
bias-disable;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
};

2. related dts node setting.
&pcie0 {
status = "disabled";
};

&pciephy0 {
starfive,sys-syscon = <&sys_syscon 0x18>;
starfive,stg-syscon = <&stg_syscon 0x148 0x1f4>;
status = "okay";
};

&usb0 {
pinctrl-names = "default";
pinctrl-0 = <&usb_pins>;
status = "okay";
};

&usb_cdns3 {
phys = <&usbphy0>, <&pciephy0>;
phy-names = "cdns3,usb2-phy", "cdns3,usb3-phy";
dr_mode = "host";
status = "okay";
};

- previous version
  v1: 
https://patchwork.ozlabs.org/project/uboot/cover/20240504150358.19600-1-minda.c...@starfivetech.com/

- patch description.

patch1: Add set phy mode function in cdns3 core driver
which is used by Starfive JH7110.
patch2-3: USB and PCIe 2.0 (usb 3.0) PHY drivier
patch4: Cadence USB wrapper driver.
patch5: Add JH7110 USB default overcurrent pin.
patch6-8 dts, config and maintainers update.

- change:
v2:
- patch 1 Move the added code to cdns3_core_init_role(). Must
  set PHY mode before calling cdns3 role start function.
    - patch 1-4 correct the code format.(follow Marek's comments.)
- patch 2 Add set 125M clock in PHY init function.
- Add new patch5. 

Minda Chen (8):
  usb: cdns3: Set USB PHY mode in cdns3_core_init_role()
  phy: starfive: Add Starfive JH7110 USB 2.0 PHY driver
  phy: starfive: Add Starfive JH7110 PCIe 2.0 PHY driver
  usb: cdns: starfive: Add cdns USB driver
  pinctrl: starfive: Setup USB default disable overcurrent pin
  configs: starfive: Add visionfive2 cadence USB configuration
  dts: starfive: Add JH7110 Cadence USB dts node
  MAINTAINERS: Update Starfive visionfive2 maintain files.

 .../dts/jh7110-starfive-visionfive-2.dtsi |   5 +
 arch/riscv/dts/jh7110.dtsi|  52 +
 board/starfive/visionfive2/MAINTAINERS|   2 +
 configs/starfive_visionfive2_defconfig|   9 +
 drivers/phy/Kconfig   |   1 +
 drivers/phy/Makefile  |   1 +
 drivers/phy/starfive/Kconfig  |  21 ++
 drivers/phy/starfive/Makefile |   7 +
 drivers/phy/starfive/phy-jh7110-pcie.c| 202 ++
 drivers/phy/starfive/phy-jh7110-usb2.c| 135 
 drivers/pinctrl/starfive/pinctrl-jh7110-sys.c |  11 +-
 drivers/usb/cdns3/Kconfig |   7 +
 drivers/usb/cdns3/Makefile|   2 +
 drivers/usb/cdns3/cdns3-starfive.c| 183 
 drivers/usb/cdns3/core.c  |  25 +++
 15 files changed, 661 insertions(+), 2 deletions(-)
 create mode 100644 drivers/phy/starfive/Kconfig
 create mode 100644 drivers/phy/starfive/Makefile
 create mode 100644 drivers/phy/starfive/phy-jh7110-pcie.c
 create mode 100644 drivers/phy/starfive/phy-jh7110-usb2.c
 create mode 100644 drivers/usb/cdns3/cdns3-starfive.c


base-commit: 8937bb265a7f2251c1bd999784a4ef10e9c6080d
-- 
2.17.1

[PATCH v2 1/8] usb: cdns3: Set USB PHY mode in cdns3_core_init_role()

[Minda Chen]

USB PHY maybe need to set PHY mode in different USB
dr mode. So translate to generic PHY mode and call
generic_phy_set_mode().

Signed-off-by: Minda Chen 
---
 drivers/usb/cdns3/core.c | 25 +
 1 file changed, 25 insertions(+)

diff --git a/drivers/usb/cdns3/core.c b/drivers/usb/cdns3/core.c
index 12a741c6ea..1e863bed89 100644
--- a/drivers/usb/cdns3/core.c
+++ b/drivers/usb/cdns3/core.c
@@ -107,6 +107,7 @@ static int cdns3_core_init_role(struct cdns3 *cdns)
 {
struct udevice *dev = cdns->dev;
enum usb_dr_mode best_dr_mode;
+   int mode = PHY_MODE_INVALID;
enum usb_dr_mode dr_mode;
int ret = 0;
 
@@ -173,6 +174,30 @@ static int cdns3_core_init_role(struct cdns3 *cdns)
 
cdns->dr_mode = dr_mode;
 
+   if (cdns->dr_mode == USB_DR_MODE_HOST) {
+   mode = PHY_MODE_USB_HOST;
+   } else if (cdns->dr_mode == USB_DR_MODE_PERIPHERAL) {
+   mode = PHY_MODE_USB_DEVICE;
+   } else if (cdns->dr_mode == USB_DR_MODE_OTG) {
+   mode = PHY_MODE_USB_OTG;
+   } else {
+   dev_err(dev, "Unknown dr mode %d\n", cdns->dr_mode);
+   ret = -EINVAL;
+   goto err;
+   }
+
+   ret = generic_phy_set_mode(&cdns->usb2_phy, mode, 0);
+   if (ret) {
+   dev_err(dev, "Set usb 2.0 PHY mode failed %d\n", ret);
+   goto err;
+   }
+
+   ret = generic_phy_set_mode(&cdns->usb3_phy, mode, 0);
+   if (ret) {
+   dev_err(dev, "Set usb 3.0 PHY mode failed %d\n", ret);
+   goto err;
+   }
+
ret = cdns3_drd_update_mode(cdns);
if (ret)
goto err;
-- 
2.17.1

[PATCH v2 3/8] phy: starfive: Add Starfive JH7110 PCIe 2.0 PHY driver

[Minda Chen]

Add Starfive JH7110 PCIe 2.0 PHY driver, which is generic
PHY driver and can be used as USB 3.0 driver.

Signed-off-by: Minda Chen 
---
 drivers/phy/starfive/Kconfig   |   7 +
 drivers/phy/starfive/Makefile  |   1 +
 drivers/phy/starfive/phy-jh7110-pcie.c | 202 +
 3 files changed, 210 insertions(+)
 create mode 100644 drivers/phy/starfive/phy-jh7110-pcie.c

diff --git a/drivers/phy/starfive/Kconfig b/drivers/phy/starfive/Kconfig
index 11a819f8b2..5d49684bc7 100644
--- a/drivers/phy/starfive/Kconfig
+++ b/drivers/phy/starfive/Kconfig
@@ -4,6 +4,13 @@
 
 menu "Starfive PHY driver"
 
+config PHY_STARFIVE_JH7110_PCIE
+bool "Starfive JH7110 PCIe 2.0 PHY driver"
+select PHY
+help
+  Enable this to support the Starfive JH7110 PCIE 2.0/USB 3.0 PHY.
+ Generic PHY driver JH7110 USB 3.0/ PCIe 2.0.
+
 config PHY_STARFIVE_JH7110_USB2
bool "Starfive JH7110 USB 2.0 PHY driver"
select PHY
diff --git a/drivers/phy/starfive/Makefile b/drivers/phy/starfive/Makefile
index a405a75e34..82f25aa21b 100644
--- a/drivers/phy/starfive/Makefile
+++ b/drivers/phy/starfive/Makefile
@@ -3,4 +3,5 @@
 # Copyright (C) 2023 Starfive
 #
 
+obj-$(CONFIG_PHY_STARFIVE_JH7110_PCIE) += phy-jh7110-pcie.o
 obj-$(CONFIG_PHY_STARFIVE_JH7110_USB2) += phy-jh7110-usb2.o
diff --git a/drivers/phy/starfive/phy-jh7110-pcie.c 
b/drivers/phy/starfive/phy-jh7110-pcie.c
new file mode 100644
index 00..57d5d8bf53
--- /dev/null
+++ b/drivers/phy/starfive/phy-jh7110-pcie.c
@@ -0,0 +1,202 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * StarFive JH7110 PCIe 2.0 PHY driver
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ * Author: Minda Chen 
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define PCIE_KVCO_LEVEL_OFF0x28
+#define PCIE_USB3_PHY_PLL_CTL_OFF  0x7c
+#define PCIE_USB3_PHY_SS_MODE  BIT(4)
+#define PCIE_KVCO_TUNE_SIGNAL_OFF  0x80
+#define PHY_KVCO_FINE_TUNE_LEVEL   0x91
+#define PHY_KVCO_FINE_TUNE_SIGNALS 0xc
+
+#define USB_PDRSTN_SPLIT   BIT(17)
+
+#define PCIE_USB3_PHY_MODE BIT(20)
+#define PCIE_PHY_MODE_MASK GENMASK(21, 20)
+#define PCIE_USB3_BUS_WIDTH_MASK   GENMASK(3, 2)
+#define PCIE_BUS_WIDTH BIT(3)
+#define PCIE_USB3_RATE_MASKGENMASK(6, 5)
+#define PCIE_USB3_RX_STANDBY_MASK  BIT(7)
+#define PCIE_USB3_PHY_ENABLE   BIT(4)
+
+struct jh7110_pcie_phy {
+   struct phy *phy;
+   struct regmap *stg_syscon;
+   struct regmap *sys_syscon;
+   void __iomem *regs;
+   u32 sys_phy_connect;
+   u32 stg_pcie_mode;
+   u32 stg_pcie_usb;
+   enum phy_mode mode;
+};
+
+static int phy_pcie_mode_set(struct jh7110_pcie_phy *data, bool usb_mode)
+{
+   unsigned int phy_mode, width, usb3_phy, ss_mode;
+
+   /* default is PCIe mode */
+   if (!data->stg_syscon || !data->sys_syscon) {
+   if (usb_mode) {
+   dev_err(data->phy->dev, "doesn't support usb3 mode\n");
+   return -EINVAL;
+   }
+   return 0;
+   }
+
+   if (usb_mode) {
+   phy_mode = PCIE_USB3_PHY_MODE;
+   width = 0;
+   usb3_phy = PCIE_USB3_PHY_ENABLE;
+   ss_mode = PCIE_USB3_PHY_SS_MODE;
+   } else {
+   phy_mode = 0;
+   width = PCIE_BUS_WIDTH;
+   usb3_phy = 0;
+   ss_mode = 0;
+   }
+
+   regmap_update_bits(data->stg_syscon, data->stg_pcie_mode,
+  PCIE_PHY_MODE_MASK, phy_mode);
+   regmap_update_bits(data->stg_syscon, data->stg_pcie_usb,
+  PCIE_USB3_BUS_WIDTH_MASK, width);
+   regmap_update_bits(data->stg_syscon, data->stg_pcie_usb,
+  PCIE_USB3_PHY_ENABLE, usb3_phy);
+   clrsetbits_le32(data->regs + PCIE_USB3_PHY_PLL_CTL_OFF,
+   PCIE_USB3_PHY_SS_MODE, ss_mode);
+
+   regmap_update_bits(data->sys_syscon, data->sys_phy_connect,
+  USB_PDRSTN_SPLIT, 0);
+
+   return 0;
+}
+
+static void phy_kvco_gain_set(struct jh7110_pcie_phy *phy)
+{
+   /* PCIe Multi-PHY PLL KVCO Gain fine tune settings: */
+   writel(PHY_KVCO_FINE_TUNE_LEVEL, phy->regs + PCIE_KVCO_LEVEL_OFF);
+   writel(PHY_KVCO_FINE_TUNE_SIGNALS, phy->regs + 
PCIE_KVCO_TUNE_SIGNAL_OFF);
+}
+
+static int jh7110_pcie_phy_set_mode(struct phy *_phy,
+   enum phy_mode mode, int submode)
+{
+   struct udevice *dev = _phy->dev;
+   struct jh7110_pcie_phy *phy = dev_get_priv(dev);
+   int ret;
+
+   if (mode == phy->mode)
+   return 0;
+
+   switch (mode) {
+   case PHY_MODE_USB_HOST:
+   case PHY_MODE_USB_DEVICE:
+  

[PATCH v2 5/8] pinctrl: starfive: Setup USB default disable overcurrent pin

[Minda Chen]

For some JH7110 boards, USB host overcurent pin is not reserved,
To make USB host work, overcurrent pin must be disabled. So set the
pin default disabled.

Signed-off-by: Minda Chen 
---
 drivers/pinctrl/starfive/pinctrl-jh7110-sys.c | 11 +--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/starfive/pinctrl-jh7110-sys.c 
b/drivers/pinctrl/starfive/pinctrl-jh7110-sys.c
index dafba65eae..1102985ab9 100644
--- a/drivers/pinctrl/starfive/pinctrl-jh7110-sys.c
+++ b/drivers/pinctrl/starfive/pinctrl-jh7110-sys.c
@@ -378,8 +378,15 @@ static int jh7110_sys_pinctrl_probe(struct udevice *dev)
 {
struct starfive_pinctrl_soc_info *info =
(struct starfive_pinctrl_soc_info *)dev_get_driver_data(dev);
-
-   return starfive_pinctrl_probe(dev, info);
+   struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
+   int ret;
+
+   ret = starfive_pinctrl_probe(dev, info);
+   /* Set default the usb controller overcurrent signal. */
+   if (!ret)
+   clrsetbits_le32(priv->base + JH7110_SYS_GPI,
+   GENMASK(22, 16), BIT(16));
+   return ret;
 }
 
 static const struct udevice_id jh7110_sys_pinctrl_ids[] = {
-- 
2.17.1

[PATCH v2 4/8] usb: cdns: starfive: Add cdns USB driver

[Minda Chen]

Add cdns USB3 wrapper driver.

Signed-off-by: Minda Chen 
---
 drivers/usb/cdns3/Kconfig  |   7 ++
 drivers/usb/cdns3/Makefile |   2 +
 drivers/usb/cdns3/cdns3-starfive.c | 183 +
 3 files changed, 192 insertions(+)
 create mode 100644 drivers/usb/cdns3/cdns3-starfive.c

diff --git a/drivers/usb/cdns3/Kconfig b/drivers/usb/cdns3/Kconfig
index 35b61497d9..f8f363982b 100644
--- a/drivers/usb/cdns3/Kconfig
+++ b/drivers/usb/cdns3/Kconfig
@@ -55,4 +55,11 @@ config USB_CDNS3_TI
help
  Say 'Y' here if you are building for Texas Instruments
  platforms that contain Cadence USB3 controller core. E.g.: J721e.
+
+config USB_CDNS3_STARFIVE
+   tristate "Cadence USB3 support on Starfive platforms"
+   default USB_CDNS3
+   help
+ Say 'Y' here if you are building for Starfive platforms
+ that contain Cadence USB3 controller core. E.g.: JH7110.
 endif
diff --git a/drivers/usb/cdns3/Makefile b/drivers/usb/cdns3/Makefile
index 18d7190755..03d1eadb2f 100644
--- a/drivers/usb/cdns3/Makefile
+++ b/drivers/usb/cdns3/Makefile
@@ -9,3 +9,5 @@ cdns3-$(CONFIG_$(SPL_)USB_CDNS3_GADGET) += gadget.o ep0.o
 cdns3-$(CONFIG_$(SPL_)USB_CDNS3_HOST)  += host.o
 
 obj-$(CONFIG_USB_CDNS3_TI) += cdns3-ti.o
+
+obj-$(CONFIG_USB_CDNS3_STARFIVE)   += cdns3-starfive.o
diff --git a/drivers/usb/cdns3/cdns3-starfive.c 
b/drivers/usb/cdns3/cdns3-starfive.c
new file mode 100644
index 00..660833fb5b
--- /dev/null
+++ b/drivers/usb/cdns3/cdns3-starfive.c
@@ -0,0 +1,183 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * cdns3-starfive.c - StarFive specific Glue layer for Cadence USB Controller
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ *
+ * Author: Minda Chen 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "core.h"
+
+#define USB_STRAP_HOST BIT(17)
+#define USB_STRAP_DEVICE   BIT(18)
+#define USB_STRAP_MASK GENMASK(18, 16)
+
+#define USB_SUSPENDM_HOST  BIT(19)
+#define USB_SUSPENDM_MASK  BIT(19)
+
+#define USB_MISC_CFG_MASK  GENMASK(23, 20)
+#define USB_SUSPENDM_BYPS  BIT(20)
+#define USB_PLL_EN BIT(22)
+#define USB_REFCLK_MODEBIT(23)
+
+struct cdns_starfive {
+   struct udevice *dev;
+   struct regmap *stg_syscon;
+   struct reset_ctl_bulk resets;
+   struct clk_bulk clks;
+   u32 stg_usb_mode;
+   enum usb_dr_mode mode;
+};
+
+static void cdns_mode_init(struct cdns_starfive *data, enum usb_dr_mode mode)
+{
+   unsigned int strap, suspendm;
+
+   regmap_update_bits(data->stg_syscon, data->stg_usb_mode,
+  USB_MISC_CFG_MASK,
+  USB_SUSPENDM_BYPS | USB_PLL_EN | USB_REFCLK_MODE);
+
+   switch (mode) {
+   case USB_DR_MODE_HOST:
+   strap = USB_STRAP_HOST;
+   suspendm = USB_SUSPENDM_HOST;
+   break;
+
+   case USB_DR_MODE_PERIPHERAL:
+   strap = USB_STRAP_DEVICE;
+   suspendm = 0;
+   break;
+   default:
+   return;
+   }
+
+   regmap_update_bits(data->stg_syscon, data->stg_usb_mode,
+  USB_STRAP_MASK, strap);
+   regmap_update_bits(data->stg_syscon, data->stg_usb_mode,
+  USB_SUSPENDM_MASK, suspendm);
+}
+
+static void cdns_clk_rst_deinit(struct cdns_starfive *data)
+{
+   reset_assert_bulk(&data->resets);
+   clk_disable_bulk(&data->clks);
+}
+
+static int cdns_clk_rst_init(struct cdns_starfive *data)
+{
+   int ret;
+
+   ret = clk_get_bulk(data->dev, &data->clks);
+   if (ret)
+   return ret;
+
+   ret = reset_get_bulk(data->dev, &data->resets);
+   if (ret)
+   goto err_clk;
+
+   ret = clk_enable_bulk(&data->clks);
+   if (ret)
+   goto err_en_clk;
+
+   ret = reset_deassert_bulk(&data->resets);
+   if (ret)
+   goto err_reset;
+
+   return 0;
+
+err_reset:
+   clk_disable_bulk(&data->clks);
+err_en_clk:
+   reset_release_bulk(&data->resets);
+err_clk:
+   clk_release_bulk(&data->clks);
+
+   return ret;
+}
+
+static int cdns_starfive_get_syscon(struct cdns_starfive *data)
+{
+   struct ofnode_phandle_args phandle;
+   int ret;
+
+   ret = dev_read_phandle_with_args(data->dev, "starfive,stg-syscon", 
NULL, 1, 0,
+&phandle);
+
+   if (ret < 0) {
+   dev_err(data->dev, "Can't get stg cfg phandle: %d\n", ret);
+   return ret;
+   }
+
+   data->stg_syscon = syscon_node_to_regmap(phandle.node);
+   if (IS_E

[PATCH v2 6/8] configs: starfive: Add visionfive2 cadence USB configuration

[Minda Chen]

Add cadence USB confiuration.

Signed-off-by: Minda Chen 
---
 configs/starfive_visionfive2_defconfig | 9 +
 1 file changed, 9 insertions(+)

diff --git a/configs/starfive_visionfive2_defconfig 
b/configs/starfive_visionfive2_defconfig
index 174ac24dc7..35137eec59 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -69,6 +69,7 @@ CONFIG_SYS_EEPROM_SIZE=512
 CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
 CONFIG_CMD_MEMINFO=y
+# CONFIG_CMD_BIND is not set
 CONFIG_CMD_I2C=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_USB=y
@@ -112,6 +113,8 @@ CONFIG_NVME_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCI_REGION_MULTI_ENTRY=y
 CONFIG_PCIE_STARFIVE_JH7110=y
+CONFIG_PHY_STARFIVE_JH7110_PCIE=y
+CONFIG_PHY_STARFIVE_JH7110_USB2=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_SPL_PINCTRL=y
@@ -127,13 +130,19 @@ CONFIG_CADENCE_QSPI=y
 CONFIG_SYSRESET=y
 CONFIG_TIMER_EARLY=y
 CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_PCI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_PCI=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_OHCI_PCI=y
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_CDNS3_HOST=y
+# CONFIG_USB_CDNS3_TI is not set
 CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
 # CONFIG_WATCHDOG is not set
 # CONFIG_WATCHDOG_AUTOSTART is not set
 CONFIG_WDT=y
-- 
2.17.1

[PATCH v2 8/8] MAINTAINERS: Update Starfive visionfive2 maintain files.

[Minda Chen]

Add USB related files to Starfive visionfive2 MAINTAINERS.

Signed-off-by: Minda Chen 
Reviewed-by: Marek Vasut 
---
 board/starfive/visionfive2/MAINTAINERS | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/board/starfive/visionfive2/MAINTAINERS 
b/board/starfive/visionfive2/MAINTAINERS
index d7f638f9b4..1faf83f581 100644
--- a/board/starfive/visionfive2/MAINTAINERS
+++ b/board/starfive/visionfive2/MAINTAINERS
@@ -6,3 +6,5 @@ F:  board/starfive/visionfive2/
 F: include/configs/starfive-visionfive2.h
 F: configs/starfive_visionfive2_defconfig
 F: drivers/pci/pcie_starfive_jh7110.c
+F: drivers/phy/starfive/
+F: drivers/usb/cdns3/cdns3-starfive.c
-- 
2.17.1

[PATCH v2 2/8] phy: starfive: Add Starfive JH7110 USB 2.0 PHY driver

[Minda Chen]

Add Starfive JH7110 USB 2.0 PHY driver, which is generic
PHY driver.

Signed-off-by: Minda Chen 
---
 drivers/phy/Kconfig|   1 +
 drivers/phy/Makefile   |   1 +
 drivers/phy/starfive/Kconfig   |  14 +++
 drivers/phy/starfive/Makefile  |   6 ++
 drivers/phy/starfive/phy-jh7110-usb2.c | 135 +
 5 files changed, 157 insertions(+)
 create mode 100644 drivers/phy/starfive/Kconfig
 create mode 100644 drivers/phy/starfive/Makefile
 create mode 100644 drivers/phy/starfive/phy-jh7110-usb2.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 8f767877e7..0c4d63a01f 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -307,5 +307,6 @@ source "drivers/phy/cadence/Kconfig"
 source "drivers/phy/ti/Kconfig"
 source "drivers/phy/qcom/Kconfig"
 source "drivers/phy/renesas/Kconfig"
+source "drivers/phy/starfive/Kconfig"
 
 endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 7a2b764492..6ac867350c 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -44,3 +44,4 @@ obj-y += cadence/
 obj-y += ti/
 obj-y += qcom/
 obj-y += renesas/
+obj-y += starfive/
diff --git a/drivers/phy/starfive/Kconfig b/drivers/phy/starfive/Kconfig
new file mode 100644
index 00..11a819f8b2
--- /dev/null
+++ b/drivers/phy/starfive/Kconfig
@@ -0,0 +1,14 @@
+#
+# Phy drivers for Starfive platforms
+#
+
+menu "Starfive PHY driver"
+
+config PHY_STARFIVE_JH7110_USB2
+   bool "Starfive JH7110 USB 2.0 PHY driver"
+   select PHY
+   help
+ Enable this to support the Starfive JH7110 USB 2.0 PHY.
+ Generic PHY driver JH7110 USB 2.0.
+
+endmenu
diff --git a/drivers/phy/starfive/Makefile b/drivers/phy/starfive/Makefile
new file mode 100644
index 00..a405a75e34
--- /dev/null
+++ b/drivers/phy/starfive/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2023 Starfive
+#
+
+obj-$(CONFIG_PHY_STARFIVE_JH7110_USB2) += phy-jh7110-usb2.o
diff --git a/drivers/phy/starfive/phy-jh7110-usb2.c 
b/drivers/phy/starfive/phy-jh7110-usb2.c
new file mode 100644
index 00..d48c9f8a74
--- /dev/null
+++ b/drivers/phy/starfive/phy-jh7110-usb2.c
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * StarFive JH7110 USB 2.0 PHY driver
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ * Author: Minda Chen 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define USB_LS_KEEPALIVE_OFF   0x4
+#define USB_LS_KEEPALIVE_ENABLEBIT(4)
+#define USB_PHY_CLK_RATE   12500
+
+struct jh7110_usb2_phy {
+   struct phy *phy;
+   void __iomem *regs;
+   struct clk *usb_125m_clk;
+   struct clk *app_125m;
+   enum phy_mode mode;
+};
+
+static void usb2_set_ls_keepalive(struct jh7110_usb2_phy *phy, bool set)
+{
+   /* Host mode enable the LS speed keep-alive signal */
+   if (set)
+   clrsetbits_le32(phy->regs + USB_LS_KEEPALIVE_OFF,
+   USB_LS_KEEPALIVE_ENABLE,
+   USB_LS_KEEPALIVE_ENABLE);
+   else
+   clrsetbits_le32(phy->regs + USB_LS_KEEPALIVE_OFF,
+   USB_LS_KEEPALIVE_ENABLE, 0);
+}
+
+static int usb2_phy_set_mode(struct phy *_phy,
+enum phy_mode mode, int submode)
+{
+   struct udevice *dev = _phy->dev;
+   struct jh7110_usb2_phy *phy = dev_get_priv(dev);
+
+   if (mode == phy->mode)
+   return 0;
+
+   switch (mode) {
+   case PHY_MODE_USB_HOST:
+   case PHY_MODE_USB_DEVICE:
+   case PHY_MODE_USB_OTG:
+   dev_dbg(dev, "Changing phy to %d\n", mode);
+   phy->mode = mode;
+   usb2_set_ls_keepalive(phy, (mode != PHY_MODE_USB_DEVICE));
+   break;
+   default:
+   return -EINVAL;
+   }
+
+   return 0;
+}
+
+static int jh7110_usb2_phy_init(struct phy *_phy)
+{
+   struct udevice *dev = _phy->dev;
+   struct jh7110_usb2_phy *phy = dev_get_priv(dev);
+   int ret;
+
+   ret = clk_set_rate(phy->usb_125m_clk, USB_PHY_CLK_RATE);
+   if (ret < 0) {
+   dev_err(dev, "Failed to set 125m clock\n");
+   return ret;
+   }
+
+   return clk_prepare_enable(phy->app_125m);
+}
+
+static int jh7110_usb2_phy_exit(struct phy *_phy)
+{
+   struct udevice *dev = _phy->dev;
+   struct jh7110_usb2_phy *phy = dev_get_priv(dev);
+
+   clk_disable_unprepare(phy->app_125m);
+
+   return 0;
+}
+
+struct phy_ops jh7110_usb2_phy_ops = {
+   .init = jh7110_usb2_phy_init,
+   .exit = jh7110_usb2_phy_exit,
+   .set_mode = usb2_phy_set_mode,
+};
+
+int jh7110_usb2_phy_probe(struct udevice *dev)
+{
+ 

[PATCH v2 7/8] dts: starfive: Add JH7110 Cadence USB dts node

[Minda Chen]

Add Jh7110 Cadence USB dts node, Visionfive2 default setting
is USB 2.0 device.

Signed-off-by: Minda Chen 
---
 .../dts/jh7110-starfive-visionfive-2.dtsi |  5 ++
 arch/riscv/dts/jh7110.dtsi| 52 +++
 2 files changed, 57 insertions(+)

diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi 
b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index e11babc1cd..44785bbee3 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -378,3 +378,8 @@
};
};
 };
+
+&usb_cdns3 {
+   dr_mode = "peripheral";
+   status = "okay";
+};
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index 2cdc683d49..1eee924e1d 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -371,6 +371,58 @@
status = "disabled";
};
 
+   usb0: usb@1010 {
+   compatible = "starfive,jh7110-usb";
+   ranges = <0x0 0x0 0x1010 0x10>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   starfive,stg-syscon = <&stg_syscon 0x4>;
+   clocks = <&stgcrg JH7110_STGCLK_USB_LPM>,
+<&stgcrg JH7110_STGCLK_USB_STB>,
+<&stgcrg JH7110_STGCLK_USB_APB>,
+<&stgcrg JH7110_STGCLK_USB_AXI>,
+<&stgcrg JH7110_STGCLK_USB_UTMI_APB>;
+   clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
+   resets = <&stgcrg JH7110_STGRST_USB_PWRUP>,
+<&stgcrg JH7110_STGRST_USB_APB>,
+<&stgcrg JH7110_STGRST_USB_AXI>,
+<&stgcrg JH7110_STGRST_USB_UTMI_APB>;
+   reset-names = "pwrup", "apb", "axi", "utmi_apb";
+
+   usb_cdns3: usb@0 {
+   compatible = "cdns,usb3";
+   reg = <0x0 0x1>,
+ <0x1 0x1>,
+ <0x2 0x1>;
+   reg-names = "otg", "xhci", "dev";
+   interrupts = <100>, <108>, <110>;
+   interrupt-names = "host", "peripheral", "otg";
+   phys = <&usbphy0>;
+   phy-names = "cdns3,usb2-phy";
+   };
+   };
+
+   usbphy0: phy@1020 {
+   compatible = "starfive,jh7110-usb-phy";
+   reg = <0x0 0x1020 0x0 0x1>;
+   clocks = <&syscrg JH7110_SYSCLK_USB_125M>,
+<&stgcrg JH7110_STGCLK_USB_APP_125>;
+   clock-names = "125m", "app_125m";
+   #phy-cells = <0>;
+   };
+
+   pciephy0: phy@1021 {
+   compatible = "starfive,jh7110-pcie-phy";
+   reg = <0x0 0x1021 0x0 0x1>;
+   #phy-cells = <0>;
+   };
+
+   pciephy1: phy@1022 {
+   compatible = "starfive,jh7110-pcie-phy";
+   reg = <0x0 0x1022 0x0 0x1>;
+   #phy-cells = <0>;
+   };
+
stgcrg: clock-controller@1023 {
compatible = "starfive,jh7110-stgcrg";
reg = <0x0 0x1023 0x0 0x1>;
-- 
2.17.1

回复: [PATCH v2 0/7] Add Starfive JH7110 Cadence USB driver

[Minda Chen]

> 
> On Thu, Jul 4, 2024 at 6:25 AM Heinrich Schuchardt 
> wrote:
> >
> > On 7/4/24 07:50, Minda Chen wrote:
> > > Add Starfive JH7110 Cadence USB driver and related PHY driver.
> > > So the codes can be used in visionfive2 and star64 7110 board.
> > >
> > > The driver is almost the same with kernel driver.
> > >
> > > Test with Star64 JH7110 board USB 3.0 + USB 2.0 host.
> > > The code can work.
> > >
> > > - Star64 using USB 3.0 and USB 2.0 host must add below board dts setting.
> >
> > Does this mean a future patch for spl_fdt_fixup_star64() is needed?
> 
> As said by Hal they will be introducing a patchset to OF_UPSTREAM the
> JH7110 board support so we should pursue that first to get dts upstream 
> (Linux?)
> aligned with U-Boot.
> 
> >
> > Did you also have a look at the USB on the Milk V Mars CM?
> 
> With Minda's advice for Star64 applied to jh7110-starfive-visionfive-2.dtsi
> directly as a test on Milk-V Mars CM
> Lite:
> 
> StarFive # usb info
> 1: Hub,  USB Revision 3.0
>  - U-Boot XHCI Host Controller
>  - Class: Hub
>  - PacketSize: 512  Configurations: 1
>  - Vendor: 0x  Product 0x Version 1.0
>Configuration: 1
>- Interfaces: 1 Self Powered 0mA
>  Interface: 0
>  - Alternate Setting 0, Endpoints: 1
>  - Class Hub
>  - Endpoint 1 In Interrupt MaxPacket 8 Interval 255ms
> 
> >
> > Best regards
> >
> > Heinrich
> >
> > >
> > > 1. usb pin setting
> > >   usb_pins: usb0-0 {
> > >   driver-vbus-pin {
> > >   pinmux =  GPOUT_SYS_USB_DRIVE_VBUS,
> > > GPOEN_ENABLE,
> > > GPI_NONE)>;
> > >   bias-disable;
> > >   input-disable;
> > >   input-schmitt-disable;
> > >   slew-rate = <0>;
> > >   };
> > >   };
> > >
> > > 2. related dts node setting.
> > > &pcie0 {
> > >   status = "disabled";
> > > };
> > >
> > > &pciephy0 {
> > >   starfive,sys-syscon = <&sys_syscon 0x18>;
> > >   starfive,stg-syscon = <&stg_syscon 0x148 0x1f4>;
> > >   status = "okay";
> > > };
> 
> Question I have is:   Where is the documentation for these "magical"
> numbers 0x18 00x148 0x1f4 ?  Is this a defined constant, or else where is 
> this in
> the Technical Reference Manual?
> 
This is USB 3.0 configuration. 0x18 0x148 and 0x1f4 is register offset.
MilkV CM is USB 2.0 host.  It is not needed.
And I don't know whether Vbus pin is GPIO25 in CM board. If not, I think
Just set dr mode to host is OK in Milk-V CM board.
> > >
> > > &usb0 {
> > >   pinctrl-names = "default";
> > >   pinctrl-0 = <&usb_pins>;
> > >   status = "okay";
> > > };
> > >
> > > &usb_cdns3 {
> > >   phys = <&usbphy0>, <&pciephy0>;
> > >   phy-names = "cdns3,usb2-phy", "cdns3,usb3-phy";
> > >   dr_mode = "host";
> > >   status = "okay";
> > > };
> > >
> > > - previous version
> > >v1:
> > > https://patchwork.ozlabs.org/project/uboot/cover/20240504150358.1960
> > > 0-1-minda.c...@starfivetech.com/
> > >
> > > - patch description.
> > >
> > > patch1: Add set phy mode function in cdns3 core driver
> > >  which is used by Starfive JH7110.
> > > patch2-3: USB and PCIe 2.0 (usb 3.0) PHY drivier
> > > patch4: Cadence USB wrapper driver.
> > > patch5: Add JH7110 USB default overcurrent pin.
> > > patch6-8 dts, config and maintainers update.
> > >
> > > - change:
> > >   v2:
> > >   - patch 1 Move the added code to cdns3_core_init_role(). Must
> > > set PHY mode before calling cdns3 role start function.
> > >   - patch 1-4 correct the code format.(follow Marek's comments.)
> > >   - patch 2 Add set 125M clock in PHY init function.
> > >   - Add new patch5.
> > >
> > > Minda Chen (8):
> > >usb: cdns3: Set USB PHY mode in cdns3_core_init_role()
> > >phy: starfive: Add Starfive JH7110 USB 2.0 PHY driver
> > >phy: starfive: Add Starfive JH7110 PCIe 2

Re: [PATCH v2 1/8] usb: cdns3: Set USB PHY mode in cdns3_core_init_role()

[Minda Chen]

> 
> Hi,
> 
> On 04/07/2024 08:50, Minda Chen wrote:
> > USB PHY maybe need to set PHY mode in different USB dr mode. So
> > translate to generic PHY mode and call generic_phy_set_mode().
> >
> > Signed-off-by: Minda Chen 
> > ---
> >  drivers/usb/cdns3/core.c | 25 +
> >  1 file changed, 25 insertions(+)
> >
> > diff --git a/drivers/usb/cdns3/core.c b/drivers/usb/cdns3/core.c index
> > 12a741c6ea..1e863bed89 100644
> > --- a/drivers/usb/cdns3/core.c
> > +++ b/drivers/usb/cdns3/core.c
> > @@ -107,6 +107,7 @@ static int cdns3_core_init_role(struct cdns3
> > *cdns)  {
> > struct udevice *dev = cdns->dev;
> > enum usb_dr_mode best_dr_mode;
> > +   int mode = PHY_MODE_INVALID;
> > enum usb_dr_mode dr_mode;
> > int ret = 0;
> >
> > @@ -173,6 +174,30 @@ static int cdns3_core_init_role(struct cdns3
> > *cdns)
> >
> > cdns->dr_mode = dr_mode;
> >
> > +   if (cdns->dr_mode == USB_DR_MODE_HOST) {
> > +   mode = PHY_MODE_USB_HOST;
> > +   } else if (cdns->dr_mode == USB_DR_MODE_PERIPHERAL) {
> > +   mode = PHY_MODE_USB_DEVICE;
> > +   } else if (cdns->dr_mode == USB_DR_MODE_OTG) {
> > +   mode = PHY_MODE_USB_OTG;
> > +   } else {
> > +   dev_err(dev, "Unknown dr mode %d\n", cdns->dr_mode);
> > +   ret = -EINVAL;
> > +   goto err;
> > +   }
> > +
> > +   ret = generic_phy_set_mode(&cdns->usb2_phy, mode, 0);
> > +   if (ret) {
> > +   dev_err(dev, "Set usb 2.0 PHY mode failed %d\n", ret);
> > +   goto err;
> > +   }
> > +
> > +   ret = generic_phy_set_mode(&cdns->usb3_phy, mode, 0);
> > +   if (ret) {
> > +   dev_err(dev, "Set usb 3.0 PHY mode failed %d\n", ret);
> > +   goto err;
> > +   }
> > +
> 
> Should we be doing the above inside cdns3_drd_update_mode() so that the PHY
> can be put in the correct state even during role switches?
> 
OK， Thanks.  
> > ret = cdns3_drd_update_mode(cdns);
> > if (ret)
> > goto err;
> 
> --
> cheers,
> -roger

Re: [PATCH v2 3/8] phy: starfive: Add Starfive JH7110 PCIe 2.0 PHY driver

[Minda Chen]

> 
> 
> 
> On 04/07/2024 08:50, Minda Chen wrote:
> > Add Starfive JH7110 PCIe 2.0 PHY driver, which is generic PHY driver
> > and can be used as USB 3.0 driver.
> >
> > Signed-off-by: Minda Chen 
> > ---
> >  drivers/phy/starfive/Kconfig   |   7 +
> >  drivers/phy/starfive/Makefile  |   1 +
> >  drivers/phy/starfive/phy-jh7110-pcie.c | 202
> > +
> >  3 files changed, 210 insertions(+)
> >  create mode 100644 drivers/phy/starfive/phy-jh7110-pcie.c
> >
> > diff --git a/drivers/phy/starfive/Kconfig
> > b/drivers/phy/starfive/Kconfig index 11a819f8b2..5d49684bc7 100644
> > --- a/drivers/phy/starfive/Kconfig
> > +++ b/drivers/phy/starfive/Kconfig
> > @@ -4,6 +4,13 @@
> >
> >  menu "Starfive PHY driver"
> >
> > +config PHY_STARFIVE_JH7110_PCIE
> > +bool "Starfive JH7110 PCIe 2.0 PHY driver"
> > +select PHY
> > +help
> > +  Enable this to support the Starfive JH7110 PCIE 2.0/USB 3.0 PHY.
> > + Generic PHY driver JH7110 USB 3.0/ PCIe 2.0.
> 
> Should be aligned to previous line.
> 
> > +
> >  config PHY_STARFIVE_JH7110_USB2
> > bool "Starfive JH7110 USB 2.0 PHY driver"
> > select PHY
> > diff --git a/drivers/phy/starfive/Makefile
> > b/drivers/phy/starfive/Makefile index a405a75e34..82f25aa21b 100644
> > --- a/drivers/phy/starfive/Makefile
> > +++ b/drivers/phy/starfive/Makefile
> > @@ -3,4 +3,5 @@
> >  # Copyright (C) 2023 Starfive
> >  #
> >
> > +obj-$(CONFIG_PHY_STARFIVE_JH7110_PCIE) += phy-jh7110-pcie.o
> >  obj-$(CONFIG_PHY_STARFIVE_JH7110_USB2) += phy-jh7110-usb2.o
> > diff --git a/drivers/phy/starfive/phy-jh7110-pcie.c
> > b/drivers/phy/starfive/phy-jh7110-pcie.c
> > new file mode 100644
> > index 00..57d5d8bf53
> > --- /dev/null
> > +++ b/drivers/phy/starfive/phy-jh7110-pcie.c
> > @@ -0,0 +1,202 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * StarFive JH7110 PCIe 2.0 PHY driver
> > + *
> > + * Copyright (C) 2024 StarFive Technology Co., Ltd.
> > + * Author: Minda Chen   */ #include
> > + #include  #include  #include
> > + #include  #include  #include
> > + #include  #include  #include
> > +
> > +
> > +#define PCIE_KVCO_LEVEL_OFF0x28
> > +#define PCIE_USB3_PHY_PLL_CTL_OFF  0x7c
> > +#define PCIE_USB3_PHY_SS_MODE  BIT(4)
> 
> extra tab?
> 
> > +#define PCIE_KVCO_TUNE_SIGNAL_OFF  0x80
> > +#define PHY_KVCO_FINE_TUNE_LEVEL   0x91
> > +#define PHY_KVCO_FINE_TUNE_SIGNALS 0xc
> > +
> > +#define USB_PDRSTN_SPLIT   BIT(17)
> > +
> > +#define PCIE_USB3_PHY_MODE BIT(20)
> > +#define PCIE_PHY_MODE_MASK GENMASK(21, 20)
> > +#define PCIE_USB3_BUS_WIDTH_MASK   GENMASK(3, 2)
> > +#define PCIE_BUS_WIDTH BIT(3)
> > +#define PCIE_USB3_RATE_MASKGENMASK(6, 5)
> > +#define PCIE_USB3_RX_STANDBY_MASK  BIT(7)
> > +#define PCIE_USB3_PHY_ENABLE   BIT(4)
> 
> Why not use define and use regmap_fields? You are already using regmap.
> 
> > +
> > +struct jh7110_pcie_phy {
> > +   struct phy *phy;
> > +   struct regmap *stg_syscon;
> > +   struct regmap *sys_syscon;
> > +   void __iomem *regs;
> > +   u32 sys_phy_connect;
> > +   u32 stg_pcie_mode;
> > +   u32 stg_pcie_usb;
> > +   enum phy_mode mode;
> > +};
> > +
> > +static int phy_pcie_mode_set(struct jh7110_pcie_phy *data, bool
> > +usb_mode) {
> > +   unsigned int phy_mode, width, usb3_phy, ss_mode;
> > +
> > +   /* default is PCIe mode */
> > +   if (!data->stg_syscon || !data->sys_syscon) {
> > +   if (usb_mode) {
> > +   dev_err(data->phy->dev, "doesn't support usb3 mode\n");
> > +   return -EINVAL;
> > +   }
> > +   return 0;
> > +   }
> > +
> > +   if (usb_mode) {
> > +   phy_mode = PCIE_USB3_PHY_MODE;
> > +   width = 0;
> > +   usb3_phy = PCIE_USB3_PHY_ENABLE;
> > +   ss_mode = PCIE_USB3_PHY_SS_MODE;
> > +   } else {
> > +   phy_mode = 0;
> > +   width = PCIE_BUS_WIDTH;
> > +   usb3_phy = 0;
> > +   ss_mode = 0;
> > +   }
> > +
> > +   regmap_update_bits(data->stg_syscon, data->stg_pcie_mode,
> > +  PCIE_PHY_MODE_MASK, phy_mode);
> > 

回复: [PATCH v2 0/7] Add Starfive JH7110 Cadence USB driver

[Minda Chen]

> 
> On 7/4/24 07:50, Minda Chen wrote:
> > Add Starfive JH7110 Cadence USB driver and related PHY driver.
> > So the codes can be used in visionfive2 and star64 7110 board.
> >
> > The driver is almost the same with kernel driver.
> >
> > Test with Star64 JH7110 board USB 3.0 + USB 2.0 host.
> > The code can work.
> >
> > - Star64 using USB 3.0 and USB 2.0 host must add below board dts setting.
> 
> Does this mean a future patch for spl_fdt_fixup_star64() is needed?
> 
> Did you also have a look at the USB on the Milk V Mars CM?
> 
> Best regards
> 
> Heinrich
> 
Maybe the USB pin setting can be added to dts. But VF2 do not contain
USB vbus pin defaut setting.
> >
> > 1. usb pin setting
> > usb_pins: usb0-0 {
> > driver-vbus-pin {
> > pinmux =  >   GPOEN_ENABLE,
> >   GPI_NONE)>;
> > bias-disable;
> > input-disable;
> > input-schmitt-disable;
> > slew-rate = <0>;
> > };
> > };
> >
> > 2. related dts node setting.
> > &pcie0 {
> > status = "disabled";
> > };
> >
> > &pciephy0 {
> > starfive,sys-syscon = <&sys_syscon 0x18>;
> > starfive,stg-syscon = <&stg_syscon 0x148 0x1f4>;
> > status = "okay";
> > };
> >
> > &usb0 {
> > pinctrl-names = "default";
> > pinctrl-0 = <&usb_pins>;
> > status = "okay";
> > };
> >
> > &usb_cdns3 {
> > phys = <&usbphy0>, <&pciephy0>;
> > phy-names = "cdns3,usb2-phy", "cdns3,usb3-phy";
> > dr_mode = "host";
> > status = "okay";
> > };
> >
> > - previous version
> >v1:
> https://patchwork.ozlabs.org/project/uboot/cover/20240504150358.19600-1-
> minda.c...@starfivetech.com/
> >
> > - patch description.
> >
> > patch1: Add set phy mode function in cdns3 core driver
> >  which is used by Starfive JH7110.
> > patch2-3: USB and PCIe 2.0 (usb 3.0) PHY drivier
> > patch4: Cadence USB wrapper driver.
> > patch5: Add JH7110 USB default overcurrent pin.
> > patch6-8 dts, config and maintainers update.
> >
> > - change:
> > v2:
> > - patch 1 Move the added code to cdns3_core_init_role(). Must
> >   set PHY mode before calling cdns3 role start function.
> > - patch 1-4 correct the code format.(follow Marek's comments.)
> > - patch 2 Add set 125M clock in PHY init function.
> > - Add new patch5.
> >
> > Minda Chen (8):
> >usb: cdns3: Set USB PHY mode in cdns3_core_init_role()
> >phy: starfive: Add Starfive JH7110 USB 2.0 PHY driver
> >phy: starfive: Add Starfive JH7110 PCIe 2.0 PHY driver
> >usb: cdns: starfive: Add cdns USB driver
> >pinctrl: starfive: Setup USB default disable overcurrent pin
> >configs: starfive: Add visionfive2 cadence USB configuration
> >dts: starfive: Add JH7110 Cadence USB dts node
> >MAINTAINERS: Update Starfive visionfive2 maintain files.
> >
> >   .../dts/jh7110-starfive-visionfive-2.dtsi |   5 +
> >   arch/riscv/dts/jh7110.dtsi|  52 +
> >   board/starfive/visionfive2/MAINTAINERS|   2 +
> >   configs/starfive_visionfive2_defconfig|   9 +
> >   drivers/phy/Kconfig   |   1 +
> >   drivers/phy/Makefile  |   1 +
> >   drivers/phy/starfive/Kconfig  |  21 ++
> >   drivers/phy/starfive/Makefile |   7 +
> >   drivers/phy/starfive/phy-jh7110-pcie.c| 202
> ++
> >   drivers/phy/starfive/phy-jh7110-usb2.c| 135 
> >   drivers/pinctrl/starfive/pinctrl-jh7110-sys.c |  11 +-
> >   drivers/usb/cdns3/Kconfig |   7 +
> >   drivers/usb/cdns3/Makefile|   2 +
> >   drivers/usb/cdns3/cdns3-starfive.c| 183 
> >   drivers/usb/cdns3/core.c  |  25 +++
> >   15 files changed, 661 insertions(+), 2 deletions(-)
> >   create mode 100644 drivers/phy/starfive/Kconfig
> >   create mode 100644 drivers/phy/starfive/Makefile
> >   create mode 100644 drivers/phy/starfive/phy-jh7110-pcie.c
> >   create mode 100644 drivers/phy/starfive/phy-jh7110-usb2.c
> >   create mode 100644 drivers/usb/cdns3/cdns3-starfive.c
> >
> >
> > base-commit: 8937bb265a7f2251c1bd999784a4ef10e9c6080d

[PATCH v3 0/8] Add Starfive JH7110 Cadence USB driver

[Minda Chen]

Add Starfive JH7110 Cadence USB driver and related PHY driver.
So the codes can be used in visionfive2 and star64 7110 board.

The driver is almost the same with kernel driver.

Test with Star64 JH7110 board USB 3.0 + USB 2.0 host.
The code can work.

- Star64 using USB 3.0 and USB 2.0 host must add below board dts setting.
(Vbus bin setting. If usb host in Other JH7110 vbus pin is not GPIO, don't
require to set this)

1. usb pin setting
usb_pins: usb0-0 {
driver-vbus-pin {
pinmux = ;
bias-disable;
input-disable;
input-schmitt-disable;
slew-rate = <0>;
};
};

2. related dts node setting(USB 3.0 host)
&pcie0 {
status = "disabled";
};

&pciephy0 {
starfive,sys-syscon = <&sys_syscon 0x18>;
starfive,stg-syscon = <&stg_syscon 0x148 0x1f4>;
status = "okay";
};

&usb0 {
pinctrl-names = "default";
pinctrl-0 = <&usb_pins>;
status = "okay";
};

&usb_cdns3 {
phys = <&usbphy0>, <&pciephy0>;
phy-names = "cdns3,usb2-phy", "cdns3,usb3-phy";
dr_mode = "host";
status = "okay";
};

- If other board is USB 2.0 host, Just set dr mode is OKay.
&usb_cdns3 {
dr_mode = "host";
status = "okay";
};

- previous version
  v1: 
https://patchwork.ozlabs.org/project/uboot/cover/20240504150358.19600-1-minda.c...@starfivetech.com/
  v2: 
https://patchwork.ozlabs.org/project/uboot/cover/20240704055014.55117-1-minda.c...@starfivetech.com/

- patch description.

patch1: Add set phy mode function in cdns3 core driver
which is used by Starfive JH7110.
patch2-3: USB and PCIe 2.0 (usb 3.0) PHY drivier
patch4: Cadence USB wrapper driver.
patch5: Add JH7110 USB default overcurrent pin.
patch6-8 dts, config and maintainers update.

- change:
v3:
- patch 1 Move the added code to cdns3_drd_update_mode().
- patch 1-4 correct the code format.(follow Rogers's comments.)
- patch 3 using regmap_field.

v2:
- patch 1 Move the added code to cdns3_core_init_role(). Must
  set PHY mode before calling cdns3 role start function.
- patch 1-4 correct the code format.(follow Marek's comments.)
- patch 2 Add set 125M clock in PHY init function.
- Add new patch5.


Minda Chen (8):
  usb: cdns3: Set USB PHY mode in cdns3_drd_update_mode()
  phy: starfive: Add Starfive JH7110 USB 2.0 PHY driver
  phy: starfive: Add Starfive JH7110 PCIe 2.0 PHY driver
  usb: cdns: starfive: Add cdns USB driver
  pinctrl: starfive: Setup USB default disable overcurrent pin
  configs: starfive: Add visionfive2 cadence USB configuration
  dts: starfive: Add JH7110 Cadence USB dts node
  MAINTAINERS: Update Starfive visionfive2 maintain files.

 .../dts/jh7110-starfive-visionfive-2.dtsi |   5 +
 arch/riscv/dts/jh7110.dtsi|  52 
 board/starfive/visionfive2/MAINTAINERS|   2 +
 configs/starfive_visionfive2_defconfig|   9 +
 drivers/phy/Kconfig   |   1 +
 drivers/phy/Makefile  |   1 +
 drivers/phy/starfive/Kconfig  |  21 ++
 drivers/phy/starfive/Makefile |   7 +
 drivers/phy/starfive/phy-jh7110-pcie.c| 237 ++
 drivers/phy/starfive/phy-jh7110-usb2.c| 135 ++
 drivers/pinctrl/starfive/pinctrl-jh7110-sys.c |  11 +-
 drivers/usb/cdns3/Kconfig |   7 +
 drivers/usb/cdns3/Makefile|   2 +
 drivers/usb/cdns3/cdns3-starfive.c| 191 ++
 drivers/usb/cdns3/drd.c   |  14 ++
 15 files changed, 693 insertions(+), 2 deletions(-)
 create mode 100644 drivers/phy/starfive/Kconfig
 create mode 100644 drivers/phy/starfive/Makefile
 create mode 100644 drivers/phy/starfive/phy-jh7110-pcie.c
 create mode 100644 drivers/phy/starfive/phy-jh7110-usb2.c
 create mode 100644 drivers/usb/cdns3/cdns3-starfive.c


base-commit: fd46ea0e701920eb205c2bce9d527bf0dec10b59
-- 
2.17.1

[PATCH v3 1/8] usb: cdns3: Set USB PHY mode in cdns3_drd_update_mode()

[Minda Chen]

USB PHY maybe need to set PHY mode in different USB
dr mode. So translate USB PHY mode to generic PHY mode
and call generic_phy_set_mode().

Signed-off-by: Minda Chen 
---
 drivers/usb/cdns3/drd.c | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/drivers/usb/cdns3/drd.c b/drivers/usb/cdns3/drd.c
index 47874fec29..cbb1334234 100644
--- a/drivers/usb/cdns3/drd.c
+++ b/drivers/usb/cdns3/drd.c
@@ -217,15 +217,19 @@ static int cdns3_init_otg_mode(struct cdns3 *cdns)
 int cdns3_drd_update_mode(struct cdns3 *cdns)
 {
int ret = 0;
+   int mode;
 
switch (cdns->dr_mode) {
case USB_DR_MODE_PERIPHERAL:
+   mode = PHY_MODE_USB_DEVICE;
ret = cdns3_set_mode(cdns, USB_DR_MODE_PERIPHERAL);
break;
case USB_DR_MODE_HOST:
+   mode = PHY_MODE_USB_HOST;
ret = cdns3_set_mode(cdns, USB_DR_MODE_HOST);
break;
case USB_DR_MODE_OTG:
+   mode = PHY_MODE_USB_OTG;
ret = cdns3_init_otg_mode(cdns);
break;
default:
@@ -234,6 +238,16 @@ int cdns3_drd_update_mode(struct cdns3 *cdns)
return -EINVAL;
}
 
+   ret = generic_phy_set_mode(&cdns->usb2_phy, mode, 0);
+   if (ret) {
+   dev_err(cdns->dev, "Set usb 2.0 PHY mode failed %d\n", ret);
+   return ret;
+   }
+
+   ret = generic_phy_set_mode(&cdns->usb3_phy, mode, 0);
+   if (ret)
+   dev_err(cdns->dev, "Set usb 3.0 PHY mode failed %d\n", ret);
+
return ret;
 }
 
-- 
2.17.1

[PATCH v3 2/8] phy: starfive: Add Starfive JH7110 USB 2.0 PHY driver

[Minda Chen]

Add Starfive JH7110 USB 2.0 PHY driver, which is generic
PHY driver.

Signed-off-by: Minda Chen 
Reviewed-by: Roger Quadros 
---
 drivers/phy/Kconfig|   1 +
 drivers/phy/Makefile   |   1 +
 drivers/phy/starfive/Kconfig   |  14 +++
 drivers/phy/starfive/Makefile  |   6 ++
 drivers/phy/starfive/phy-jh7110-usb2.c | 135 +
 5 files changed, 157 insertions(+)
 create mode 100644 drivers/phy/starfive/Kconfig
 create mode 100644 drivers/phy/starfive/Makefile
 create mode 100644 drivers/phy/starfive/phy-jh7110-usb2.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 8f767877e7..0c4d63a01f 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -307,5 +307,6 @@ source "drivers/phy/cadence/Kconfig"
 source "drivers/phy/ti/Kconfig"
 source "drivers/phy/qcom/Kconfig"
 source "drivers/phy/renesas/Kconfig"
+source "drivers/phy/starfive/Kconfig"
 
 endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 7a2b764492..6ac867350c 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -44,3 +44,4 @@ obj-y += cadence/
 obj-y += ti/
 obj-y += qcom/
 obj-y += renesas/
+obj-y += starfive/
diff --git a/drivers/phy/starfive/Kconfig b/drivers/phy/starfive/Kconfig
new file mode 100644
index 00..f28529d1f9
--- /dev/null
+++ b/drivers/phy/starfive/Kconfig
@@ -0,0 +1,14 @@
+#
+# PHY drivers for Starfive platforms
+#
+
+menu "Starfive PHY driver"
+
+config PHY_STARFIVE_JH7110_USB2
+   bool "Starfive JH7110 USB 2.0 PHY driver"
+   select PHY
+   help
+ Enable this to support the Starfive JH7110 USB 2.0 PHY.
+ Generic PHY driver JH7110 USB 2.0.
+
+endmenu
diff --git a/drivers/phy/starfive/Makefile b/drivers/phy/starfive/Makefile
new file mode 100644
index 00..a405a75e34
--- /dev/null
+++ b/drivers/phy/starfive/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2023 Starfive
+#
+
+obj-$(CONFIG_PHY_STARFIVE_JH7110_USB2) += phy-jh7110-usb2.o
diff --git a/drivers/phy/starfive/phy-jh7110-usb2.c 
b/drivers/phy/starfive/phy-jh7110-usb2.c
new file mode 100644
index 00..d48c9f8a74
--- /dev/null
+++ b/drivers/phy/starfive/phy-jh7110-usb2.c
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * StarFive JH7110 USB 2.0 PHY driver
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ * Author: Minda Chen 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define USB_LS_KEEPALIVE_OFF   0x4
+#define USB_LS_KEEPALIVE_ENABLEBIT(4)
+#define USB_PHY_CLK_RATE   12500
+
+struct jh7110_usb2_phy {
+   struct phy *phy;
+   void __iomem *regs;
+   struct clk *usb_125m_clk;
+   struct clk *app_125m;
+   enum phy_mode mode;
+};
+
+static void usb2_set_ls_keepalive(struct jh7110_usb2_phy *phy, bool set)
+{
+   /* Host mode enable the LS speed keep-alive signal */
+   if (set)
+   clrsetbits_le32(phy->regs + USB_LS_KEEPALIVE_OFF,
+   USB_LS_KEEPALIVE_ENABLE,
+   USB_LS_KEEPALIVE_ENABLE);
+   else
+   clrsetbits_le32(phy->regs + USB_LS_KEEPALIVE_OFF,
+   USB_LS_KEEPALIVE_ENABLE, 0);
+}
+
+static int usb2_phy_set_mode(struct phy *_phy,
+enum phy_mode mode, int submode)
+{
+   struct udevice *dev = _phy->dev;
+   struct jh7110_usb2_phy *phy = dev_get_priv(dev);
+
+   if (mode == phy->mode)
+   return 0;
+
+   switch (mode) {
+   case PHY_MODE_USB_HOST:
+   case PHY_MODE_USB_DEVICE:
+   case PHY_MODE_USB_OTG:
+   dev_dbg(dev, "Changing phy to %d\n", mode);
+   phy->mode = mode;
+   usb2_set_ls_keepalive(phy, (mode != PHY_MODE_USB_DEVICE));
+   break;
+   default:
+   return -EINVAL;
+   }
+
+   return 0;
+}
+
+static int jh7110_usb2_phy_init(struct phy *_phy)
+{
+   struct udevice *dev = _phy->dev;
+   struct jh7110_usb2_phy *phy = dev_get_priv(dev);
+   int ret;
+
+   ret = clk_set_rate(phy->usb_125m_clk, USB_PHY_CLK_RATE);
+   if (ret < 0) {
+   dev_err(dev, "Failed to set 125m clock\n");
+   return ret;
+   }
+
+   return clk_prepare_enable(phy->app_125m);
+}
+
+static int jh7110_usb2_phy_exit(struct phy *_phy)
+{
+   struct udevice *dev = _phy->dev;
+   struct jh7110_usb2_phy *phy = dev_get_priv(dev);
+
+   clk_disable_unprepare(phy->app_125m);
+
+   return 0;
+}
+
+struct phy_ops jh7110_usb2_phy_ops = {
+   .init = jh7110_usb2_phy_init,
+   .exit = jh7110_usb2_phy_exit,
+   .set_mode = usb2_phy_set_mode,
+};
+
+int jh7110_usb2_phy_probe(struct udevice

[PATCH v3 3/8] phy: starfive: Add Starfive JH7110 PCIe 2.0 PHY driver

[Minda Chen]

Add Starfive JH7110 PCIe 2.0 PHY driver, which is generic
PHY driver and can be used as USB 3.0 driver.

Signed-off-by: Minda Chen 
---
 drivers/phy/starfive/Kconfig   |   7 +
 drivers/phy/starfive/Makefile  |   1 +
 drivers/phy/starfive/phy-jh7110-pcie.c | 237 +
 3 files changed, 245 insertions(+)
 create mode 100644 drivers/phy/starfive/phy-jh7110-pcie.c

diff --git a/drivers/phy/starfive/Kconfig b/drivers/phy/starfive/Kconfig
index f28529d1f9..0843070b74 100644
--- a/drivers/phy/starfive/Kconfig
+++ b/drivers/phy/starfive/Kconfig
@@ -4,6 +4,13 @@
 
 menu "Starfive PHY driver"
 
+config PHY_STARFIVE_JH7110_PCIE
+   bool "Starfive JH7110 PCIe 2.0 PHY driver"
+   select PHY
+   help
+ Enable this to support the Starfive JH7110 PCIE 2.0/USB 3.0 PHY.
+ Generic PHY driver JH7110 USB 3.0/ PCIe 2.0.
+
 config PHY_STARFIVE_JH7110_USB2
bool "Starfive JH7110 USB 2.0 PHY driver"
select PHY
diff --git a/drivers/phy/starfive/Makefile b/drivers/phy/starfive/Makefile
index a405a75e34..82f25aa21b 100644
--- a/drivers/phy/starfive/Makefile
+++ b/drivers/phy/starfive/Makefile
@@ -3,4 +3,5 @@
 # Copyright (C) 2023 Starfive
 #
 
+obj-$(CONFIG_PHY_STARFIVE_JH7110_PCIE) += phy-jh7110-pcie.o
 obj-$(CONFIG_PHY_STARFIVE_JH7110_USB2) += phy-jh7110-usb2.o
diff --git a/drivers/phy/starfive/phy-jh7110-pcie.c 
b/drivers/phy/starfive/phy-jh7110-pcie.c
new file mode 100644
index 00..53bfc4839e
--- /dev/null
+++ b/drivers/phy/starfive/phy-jh7110-pcie.c
@@ -0,0 +1,237 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * StarFive JH7110 PCIe 2.0 PHY driver
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ * Author: Minda Chen 
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define PCIE_KVCO_LEVEL_OFF0x28
+#define PCIE_USB3_PHY_PLL_CTL_OFF  0x7c
+#define PCIE_USB3_PHY_SS_MODE  BIT(4)
+#define PCIE_KVCO_TUNE_SIGNAL_OFF  0x80
+#define PHY_KVCO_FINE_TUNE_LEVEL   0x91
+#define PHY_KVCO_FINE_TUNE_SIGNALS 0xc
+
+#define PCIE_USB3_PHY_MODE 0x1
+#define PCIE_BUS_WIDTH 0x2
+#define PCIE_USB3_PHY_ENABLE   0x1
+#define PCIE_USB3_PHY_SPLIT0x1
+
+struct jh7110_pcie_phy {
+   struct phy *phy;
+   struct regmap *stg_syscon;
+   struct regmap *sys_syscon;
+   void __iomem *regs;
+   struct regmap_field *phy_mode;
+   struct regmap_field *bus_width;
+   struct regmap_field *usb3_phy_en;
+   struct regmap_field *usb_split;
+   enum phy_mode mode;
+};
+
+static int phy_pcie_mode_set(struct jh7110_pcie_phy *data, bool usb_mode)
+{
+   unsigned int phy_mode, width, usb3_phy, ss_mode, split;
+
+   /* default is PCIe mode */
+   if (!data->stg_syscon || !data->sys_syscon) {
+   if (usb_mode) {
+   dev_err(data->phy->dev, "doesn't support usb3 mode\n");
+   return -EINVAL;
+   }
+   return 0;
+   }
+
+   if (usb_mode) {
+   phy_mode = PCIE_USB3_PHY_MODE;
+   width = 0;
+   usb3_phy = PCIE_USB3_PHY_ENABLE;
+   ss_mode = PCIE_USB3_PHY_SS_MODE;
+   split = 0;
+   } else {
+   phy_mode = 0;
+   width = PCIE_BUS_WIDTH;
+   usb3_phy = 0;
+   ss_mode = 0;
+   split = PCIE_USB3_PHY_SPLIT;
+   }
+
+   regmap_field_write(data->phy_mode, phy_mode);
+   regmap_field_write(data->bus_width, width);
+   regmap_field_write(data->usb3_phy_en, usb3_phy);
+   clrsetbits_le32(data->regs + PCIE_USB3_PHY_PLL_CTL_OFF,
+   PCIE_USB3_PHY_SS_MODE, ss_mode);
+   regmap_field_write(data->usb_split, split);
+
+   return 0;
+}
+
+static void phy_kvco_gain_set(struct jh7110_pcie_phy *phy)
+{
+   /* PCIe Multi-PHY PLL KVCO Gain fine tune settings: */
+   writel(PHY_KVCO_FINE_TUNE_LEVEL, phy->regs + PCIE_KVCO_LEVEL_OFF);
+   writel(PHY_KVCO_FINE_TUNE_SIGNALS, phy->regs + 
PCIE_KVCO_TUNE_SIGNAL_OFF);
+}
+
+static int jh7110_pcie_phy_set_mode(struct phy *_phy,
+   enum phy_mode mode, int submode)
+{
+   struct udevice *dev = _phy->dev;
+   struct jh7110_pcie_phy *phy = dev_get_priv(dev);
+   int ret;
+
+   if (mode == phy->mode)
+   return 0;
+
+   switch (mode) {
+   case PHY_MODE_USB_HOST:
+   case PHY_MODE_USB_DEVICE:
+   case PHY_MODE_USB_OTG:
+   ret = phy_pcie_mode_set(phy, 1);
+   if (ret)
+   return ret;
+   break;
+   case PHY_MODE_PCIE:
+   phy_pcie_mode_set(phy, 0);
+   break;
+   default:
+

[PATCH v3 4/8] usb: cdns: starfive: Add cdns USB driver

[Minda Chen]

Add cdns USB3 wrapper driver.

Signed-off-by: Minda Chen 
---
 drivers/usb/cdns3/Kconfig  |   7 ++
 drivers/usb/cdns3/Makefile |   2 +
 drivers/usb/cdns3/cdns3-starfive.c | 191 +
 3 files changed, 200 insertions(+)
 create mode 100644 drivers/usb/cdns3/cdns3-starfive.c

diff --git a/drivers/usb/cdns3/Kconfig b/drivers/usb/cdns3/Kconfig
index 35b61497d9..f8f363982b 100644
--- a/drivers/usb/cdns3/Kconfig
+++ b/drivers/usb/cdns3/Kconfig
@@ -55,4 +55,11 @@ config USB_CDNS3_TI
help
  Say 'Y' here if you are building for Texas Instruments
  platforms that contain Cadence USB3 controller core. E.g.: J721e.
+
+config USB_CDNS3_STARFIVE
+   tristate "Cadence USB3 support on Starfive platforms"
+   default USB_CDNS3
+   help
+ Say 'Y' here if you are building for Starfive platforms
+ that contain Cadence USB3 controller core. E.g.: JH7110.
 endif
diff --git a/drivers/usb/cdns3/Makefile b/drivers/usb/cdns3/Makefile
index 18d7190755..03d1eadb2f 100644
--- a/drivers/usb/cdns3/Makefile
+++ b/drivers/usb/cdns3/Makefile
@@ -9,3 +9,5 @@ cdns3-$(CONFIG_$(SPL_)USB_CDNS3_GADGET) += gadget.o ep0.o
 cdns3-$(CONFIG_$(SPL_)USB_CDNS3_HOST)  += host.o
 
 obj-$(CONFIG_USB_CDNS3_TI) += cdns3-ti.o
+
+obj-$(CONFIG_USB_CDNS3_STARFIVE)   += cdns3-starfive.o
diff --git a/drivers/usb/cdns3/cdns3-starfive.c 
b/drivers/usb/cdns3/cdns3-starfive.c
new file mode 100644
index 00..839d72e4e1
--- /dev/null
+++ b/drivers/usb/cdns3/cdns3-starfive.c
@@ -0,0 +1,191 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * cdns3-starfive.c - StarFive specific Glue layer for Cadence USB Controller
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ *
+ * Author: Minda Chen 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "core.h"
+
+#define USB_STRAP_HOST BIT(17)
+#define USB_STRAP_DEVICE   BIT(18)
+#define USB_STRAP_MASK GENMASK(18, 16)
+
+#define USB_SUSPENDM_HOST  BIT(19)
+#define USB_SUSPENDM_MASK  BIT(19)
+
+#define USB_MISC_CFG_MASK  GENMASK(23, 20)
+#define USB_SUSPENDM_BYPS  BIT(20)
+#define USB_PLL_EN BIT(22)
+#define USB_REFCLK_MODEBIT(23)
+
+struct cdns_starfive {
+   struct udevice *dev;
+   struct regmap *stg_syscon;
+   struct reset_ctl_bulk resets;
+   struct clk_bulk clks;
+   u32 stg_usb_mode;
+   enum usb_dr_mode mode;
+};
+
+static void cdns_mode_init(struct cdns_starfive *data, enum usb_dr_mode mode)
+{
+   unsigned int strap, suspendm;
+
+   regmap_update_bits(data->stg_syscon, data->stg_usb_mode,
+  USB_MISC_CFG_MASK,
+  USB_SUSPENDM_BYPS | USB_PLL_EN | USB_REFCLK_MODE);
+
+   switch (mode) {
+   case USB_DR_MODE_HOST:
+   strap = USB_STRAP_HOST;
+   suspendm = USB_SUSPENDM_HOST;
+   break;
+
+   case USB_DR_MODE_PERIPHERAL:
+   strap = USB_STRAP_DEVICE;
+   suspendm = 0;
+   break;
+   default:
+   return;
+   }
+
+   regmap_update_bits(data->stg_syscon, data->stg_usb_mode,
+  USB_STRAP_MASK, strap);
+   regmap_update_bits(data->stg_syscon, data->stg_usb_mode,
+  USB_SUSPENDM_MASK, suspendm);
+}
+
+static void cdns_clk_rst_deinit(struct cdns_starfive *data)
+{
+   reset_assert_bulk(&data->resets);
+   clk_disable_bulk(&data->clks);
+}
+
+static int cdns_clk_rst_init(struct cdns_starfive *data)
+{
+   int ret;
+
+   ret = clk_get_bulk(data->dev, &data->clks);
+   if (ret)
+   return ret;
+
+   ret = reset_get_bulk(data->dev, &data->resets);
+   if (ret)
+   goto err_clk;
+
+   ret = clk_enable_bulk(&data->clks);
+   if (ret) {
+   dev_err(data->dev, "clk enable failed: %d\n", ret);
+   goto err_en_clk;
+   }
+
+   ret = reset_deassert_bulk(&data->resets);
+   if (ret) {
+   dev_err(data->dev, "reset deassert failed: %d\n", ret);
+   goto err_reset;
+   }
+
+   return 0;
+
+err_reset:
+   clk_disable_bulk(&data->clks);
+err_en_clk:
+   reset_release_bulk(&data->resets);
+err_clk:
+   clk_release_bulk(&data->clks);
+
+   return ret;
+}
+
+static int cdns_starfive_get_syscon(struct cdns_starfive *data)
+{
+   struct ofnode_phandle_args phandle;
+   int ret;
+
+   ret = dev_read_phandle_with_args(data->dev, "starfive,stg-syscon", 
NULL, 1, 0,
+&phandle);
+   if (ret < 0) {
+   dev_err(d

[PATCH v3 5/8] pinctrl: starfive: Setup USB default disable overcurrent pin

[Minda Chen]

For some JH7110 boards, USB host overcurent pin is not reserved,
To make USB host work, overcurrent pin must be disabled. So set the
pin default disabled.

Signed-off-by: Minda Chen 
---
 drivers/pinctrl/starfive/pinctrl-jh7110-sys.c | 11 +--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/starfive/pinctrl-jh7110-sys.c 
b/drivers/pinctrl/starfive/pinctrl-jh7110-sys.c
index dafba65eae..1102985ab9 100644
--- a/drivers/pinctrl/starfive/pinctrl-jh7110-sys.c
+++ b/drivers/pinctrl/starfive/pinctrl-jh7110-sys.c
@@ -378,8 +378,15 @@ static int jh7110_sys_pinctrl_probe(struct udevice *dev)
 {
struct starfive_pinctrl_soc_info *info =
(struct starfive_pinctrl_soc_info *)dev_get_driver_data(dev);
-
-   return starfive_pinctrl_probe(dev, info);
+   struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
+   int ret;
+
+   ret = starfive_pinctrl_probe(dev, info);
+   /* Set default the usb controller overcurrent signal. */
+   if (!ret)
+   clrsetbits_le32(priv->base + JH7110_SYS_GPI,
+   GENMASK(22, 16), BIT(16));
+   return ret;
 }
 
 static const struct udevice_id jh7110_sys_pinctrl_ids[] = {
-- 
2.17.1

[PATCH v3 7/8] dts: starfive: Add JH7110 Cadence USB dts node

[Minda Chen]

Add Jh7110 Cadence USB dts node, Visionfive2 default setting
is USB 2.0 device.

Signed-off-by: Minda Chen 
---
 .../dts/jh7110-starfive-visionfive-2.dtsi |  5 ++
 arch/riscv/dts/jh7110.dtsi| 52 +++
 2 files changed, 57 insertions(+)

diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi 
b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index e11babc1cd..44785bbee3 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -378,3 +378,8 @@
};
};
 };
+
+&usb_cdns3 {
+   dr_mode = "peripheral";
+   status = "okay";
+};
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index 2cdc683d49..1eee924e1d 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -371,6 +371,58 @@
status = "disabled";
};
 
+   usb0: usb@1010 {
+   compatible = "starfive,jh7110-usb";
+   ranges = <0x0 0x0 0x1010 0x10>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   starfive,stg-syscon = <&stg_syscon 0x4>;
+   clocks = <&stgcrg JH7110_STGCLK_USB_LPM>,
+<&stgcrg JH7110_STGCLK_USB_STB>,
+<&stgcrg JH7110_STGCLK_USB_APB>,
+<&stgcrg JH7110_STGCLK_USB_AXI>,
+<&stgcrg JH7110_STGCLK_USB_UTMI_APB>;
+   clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
+   resets = <&stgcrg JH7110_STGRST_USB_PWRUP>,
+<&stgcrg JH7110_STGRST_USB_APB>,
+<&stgcrg JH7110_STGRST_USB_AXI>,
+<&stgcrg JH7110_STGRST_USB_UTMI_APB>;
+   reset-names = "pwrup", "apb", "axi", "utmi_apb";
+
+   usb_cdns3: usb@0 {
+   compatible = "cdns,usb3";
+   reg = <0x0 0x1>,
+ <0x1 0x1>,
+ <0x2 0x1>;
+   reg-names = "otg", "xhci", "dev";
+   interrupts = <100>, <108>, <110>;
+   interrupt-names = "host", "peripheral", "otg";
+   phys = <&usbphy0>;
+   phy-names = "cdns3,usb2-phy";
+   };
+   };
+
+   usbphy0: phy@1020 {
+   compatible = "starfive,jh7110-usb-phy";
+   reg = <0x0 0x1020 0x0 0x1>;
+   clocks = <&syscrg JH7110_SYSCLK_USB_125M>,
+<&stgcrg JH7110_STGCLK_USB_APP_125>;
+   clock-names = "125m", "app_125m";
+   #phy-cells = <0>;
+   };
+
+   pciephy0: phy@1021 {
+   compatible = "starfive,jh7110-pcie-phy";
+   reg = <0x0 0x1021 0x0 0x1>;
+   #phy-cells = <0>;
+   };
+
+   pciephy1: phy@1022 {
+   compatible = "starfive,jh7110-pcie-phy";
+   reg = <0x0 0x1022 0x0 0x1>;
+   #phy-cells = <0>;
+   };
+
stgcrg: clock-controller@1023 {
compatible = "starfive,jh7110-stgcrg";
reg = <0x0 0x1023 0x0 0x1>;
-- 
2.17.1

[PATCH v3 6/8] configs: starfive: Add visionfive2 cadence USB configuration

[Minda Chen]

Add cadence USB confiuration.

Signed-off-by: Minda Chen 
---
 configs/starfive_visionfive2_defconfig | 9 +
 1 file changed, 9 insertions(+)

diff --git a/configs/starfive_visionfive2_defconfig 
b/configs/starfive_visionfive2_defconfig
index 174ac24dc7..35137eec59 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -69,6 +69,7 @@ CONFIG_SYS_EEPROM_SIZE=512
 CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
 CONFIG_CMD_MEMINFO=y
+# CONFIG_CMD_BIND is not set
 CONFIG_CMD_I2C=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_USB=y
@@ -112,6 +113,8 @@ CONFIG_NVME_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCI_REGION_MULTI_ENTRY=y
 CONFIG_PCIE_STARFIVE_JH7110=y
+CONFIG_PHY_STARFIVE_JH7110_PCIE=y
+CONFIG_PHY_STARFIVE_JH7110_USB2=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_SPL_PINCTRL=y
@@ -127,13 +130,19 @@ CONFIG_CADENCE_QSPI=y
 CONFIG_SYSRESET=y
 CONFIG_TIMER_EARLY=y
 CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_PCI=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_PCI=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_OHCI_PCI=y
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_CDNS3_HOST=y
+# CONFIG_USB_CDNS3_TI is not set
 CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
 # CONFIG_WATCHDOG is not set
 # CONFIG_WATCHDOG_AUTOSTART is not set
 CONFIG_WDT=y
-- 
2.17.1

[PATCH v3 8/8] MAINTAINERS: Update Starfive visionfive2 maintain files.

[Minda Chen]

Add USB related files to Starfive visionfive2 MAINTAINERS.

Signed-off-by: Minda Chen 
Reviewed-by: Marek Vasut 
---
 board/starfive/visionfive2/MAINTAINERS | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/board/starfive/visionfive2/MAINTAINERS 
b/board/starfive/visionfive2/MAINTAINERS
index d7f638f9b4..1faf83f581 100644
--- a/board/starfive/visionfive2/MAINTAINERS
+++ b/board/starfive/visionfive2/MAINTAINERS
@@ -6,3 +6,5 @@ F:  board/starfive/visionfive2/
 F: include/configs/starfive-visionfive2.h
 F: configs/starfive_visionfive2_defconfig
 F: drivers/pci/pcie_starfive_jh7110.c
+F: drivers/phy/starfive/
+F: drivers/usb/cdns3/cdns3-starfive.c
-- 
2.17.1

Re: [PATCH v3 7/8] dts: starfive: Add JH7110 Cadence USB dts node

[Minda Chen]

> 
> On Sat, Jul 20, 2024 at 6:47 PM E Shattow  wrote:
> >
> > Hi, I am testing on Milk-V Mars CM Lite, and I add to these devicetree
> > changes at runtime from board/starfive/visionfive2/spl.c
> >
> > On Thu, Jul 18, 2024 at 6:38 PM Minda Chen 
> wrote:
> > >
> > > Add Jh7110 Cadence USB dts node, Visionfive2 default setting is USB
> > > 2.0 device.
> > >
> > > Signed-off-by: Minda Chen 
> > > ---
> > >  .../dts/jh7110-starfive-visionfive-2.dtsi |  5 ++
> > >  arch/riscv/dts/jh7110.dtsi| 52
> +++
> > >  2 files changed, 57 insertions(+)
> > >
> > > diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > > b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > > index e11babc1cd..44785bbee3 100644
> > > --- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > > +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > > @@ -378,3 +378,8 @@
> > > };
> > > };
> > >  };
> > > +
> > > +&usb_cdns3 {
> > > +   dr_mode = "peripheral";
> > > +   status = "okay";
> > > +};
> > > diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
> > > index 2cdc683d49..1eee924e1d 100644
> > > --- a/arch/riscv/dts/jh7110.dtsi
> > > +++ b/arch/riscv/dts/jh7110.dtsi
> > > @@ -371,6 +371,58 @@
> > > status = "disabled";
> > > };
> > >
> > > +   usb0: usb@1010 {
> > > +   compatible = "starfive,jh7110-usb";
> > > +   ranges = <0x0 0x0 0x1010 0x10>;
> > > +   #address-cells = <1>;
> > > +   #size-cells = <1>;
> > > +   starfive,stg-syscon = <&stg_syscon 0x4>;
> > > +   clocks = <&stgcrg
> JH7110_STGCLK_USB_LPM>,
> > > +<&stgcrg
> JH7110_STGCLK_USB_STB>,
> > > +<&stgcrg
> JH7110_STGCLK_USB_APB>,
> > > +<&stgcrg
> JH7110_STGCLK_USB_AXI>,
> > > +<&stgcrg
> JH7110_STGCLK_USB_UTMI_APB>;
> > > +   clock-names = "lpm", "stb", "apb", "axi",
> "utmi_apb";
> > > +   resets = <&stgcrg
> JH7110_STGRST_USB_PWRUP>,
> > > +<&stgcrg
> JH7110_STGRST_USB_APB>,
> > > +<&stgcrg
> JH7110_STGRST_USB_AXI>,
> > > +<&stgcrg
> JH7110_STGRST_USB_UTMI_APB>;
> > > +   reset-names = "pwrup", "apb", "axi",
> > > + "utmi_apb";
> > > +
> > > +   usb_cdns3: usb@0 {
> > > +   compatible = "cdns,usb3";
> > > +   reg = <0x0 0x1>,
> > > + <0x1 0x1>,
> > > + <0x2 0x1>;
> > > +   reg-names = "otg", "xhci", "dev";
> > > +   interrupts = <100>, <108>, <110>;
> > > +   interrupt-names = "host",
> "peripheral", "otg";
> > > +   phys = <&usbphy0>;
> > > +   phy-names = "cdns3,usb2-phy";
> > > +   };
> > > +   };
> > > +
> > > +   usbphy0: phy@1020 {
> > > +   compatible = "starfive,jh7110-usb-phy";
> > > +   reg = <0x0 0x1020 0x0 0x1>;
> > > +   clocks = <&syscrg
> JH7110_SYSCLK_USB_125M>,
> > > +<&stgcrg
> JH7110_STGCLK_USB_APP_125>;
> > > +   clock-names = "125m", "app_125m";
> > > +   #phy-cells = <0>;
> > > +   };
> > > +
> > > +   pci

Re: [PATCH v3 7/8] dts: starfive: Add JH7110 Cadence USB dts node

[Minda Chen]

> 
> On Mon, Jul 22, 2024 at 6:29 PM Minda Chen 
> wrote:
> >
> >
> >
> > >
> > > On Sat, Jul 20, 2024 at 6:47 PM E Shattow  wrote:
> > > >
> > > > Hi, I am testing on Milk-V Mars CM Lite, and I add to these
> > > > devicetree changes at runtime from
> > > > board/starfive/visionfive2/spl.c
> > > >
> > > > On Thu, Jul 18, 2024 at 6:38 PM Minda Chen
> > > > 
> > > wrote:
> > > > >
> > > > > Add Jh7110 Cadence USB dts node, Visionfive2 default setting is
> > > > > USB
> > > > > 2.0 device.
> > > > >
> > > > > Signed-off-by: Minda Chen 
> > > > > ---
> > > > >  .../dts/jh7110-starfive-visionfive-2.dtsi |  5 ++
> > > > >  arch/riscv/dts/jh7110.dtsi| 52
> > > +++
> > > > >  2 files changed, 57 insertions(+)
> > > > >
> > > > > diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > > > > b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > > > > index e11babc1cd..44785bbee3 100644
> > > > > --- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > > > > +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > > > > @@ -378,3 +378,8 @@
> > > > > };
> > > > > };
> > > > >  };
> > > > > +
> > > > > +&usb_cdns3 {
> > > > > +   dr_mode = "peripheral";
> > > > > +   status = "okay";
> > > > > +};
> > > > > diff --git a/arch/riscv/dts/jh7110.dtsi
> > > > > b/arch/riscv/dts/jh7110.dtsi index 2cdc683d49..1eee924e1d 100644
> > > > > --- a/arch/riscv/dts/jh7110.dtsi
> > > > > +++ b/arch/riscv/dts/jh7110.dtsi
> > > > > @@ -371,6 +371,58 @@
> > > > > status = "disabled";
> > > > > };
> > > > >
> > > > > +   usb0: usb@1010 {
> > > > > +   compatible = "starfive,jh7110-usb";
> > > > > +   ranges = <0x0 0x0 0x1010 0x10>;
> > > > > +   #address-cells = <1>;
> > > > > +   #size-cells = <1>;
> > > > > +   starfive,stg-syscon = <&stg_syscon 0x4>;
> > > > > +   clocks = <&stgcrg
> > > JH7110_STGCLK_USB_LPM>,
> > > > > +<&stgcrg
> > > JH7110_STGCLK_USB_STB>,
> > > > > +<&stgcrg
> > > JH7110_STGCLK_USB_APB>,
> > > > > +<&stgcrg
> > > JH7110_STGCLK_USB_AXI>,
> > > > > +<&stgcrg
> > > JH7110_STGCLK_USB_UTMI_APB>;
> > > > > +   clock-names = "lpm", "stb", "apb",
> > > > > + "axi",
> > > "utmi_apb";
> > > > > +   resets = <&stgcrg
> > > JH7110_STGRST_USB_PWRUP>,
> > > > > +<&stgcrg
> > > JH7110_STGRST_USB_APB>,
> > > > > +<&stgcrg
> > > JH7110_STGRST_USB_AXI>,
> > > > > +<&stgcrg
> > > JH7110_STGRST_USB_UTMI_APB>;
> > > > > +   reset-names = "pwrup", "apb", "axi",
> > > > > + "utmi_apb";
> > > > > +
> > > > > +   usb_cdns3: usb@0 {
> > > > > +   compatible = "cdns,usb3";
> > > > > +   reg = <0x0 0x1>,
> > > > > + <0x1 0x1>,
> > > > > + <0x2 0x1>;
> > > > > +   reg-names = "otg", "xhci",
> "dev";
> > > > > +   interrupts = <100>, <108>,
> <110>;
> > > > > +   interrupt-na

Re: [PATCH v3 7/8] dts: starfive: Add JH7110 Cadence USB dts node

[Minda Chen]

> -邮件原件-
> 发件人: E Shattow 
> 发送时间: 2024年7月23日 21:06
> 收件人: Minda Chen 
> 抄送: Marek Vasut ; Tom Rini ; Roger
> Quadros ; Neil Armstrong ;
> Alexey Romanov ; Sumit Garg
> ; Mark Kettenis ; Nishanth
> Menon ; Rick Chen ; Leo Yu-Chi Liang
> ; u-boot@lists.denx.de; Heinrich Schuchardt
> ; Simon Glass 
> 主题: Re: [PATCH v3 7/8] dts: starfive: Add JH7110 Cadence USB dts node
> 
> On Tue, Jul 23, 2024 at 3:16 AM Minda Chen 
> wrote:
> >
> >
> >
> > >
> > > On Mon, Jul 22, 2024 at 6:29 PM Minda Chen
> > > 
> > > wrote:
> > > >
> > > >
> > > >
> > > > >
> > > > > On Sat, Jul 20, 2024 at 6:47 PM E Shattow  wrote:
> > > > > >
> > > > > > Hi, I am testing on Milk-V Mars CM Lite, and I add to these
> > > > > > devicetree changes at runtime from
> > > > > > board/starfive/visionfive2/spl.c
> > > > > >
> > > > > > On Thu, Jul 18, 2024 at 6:38 PM Minda Chen
> > > > > > 
> > > > > wrote:
> > > > > > >
> > > > > > > Add Jh7110 Cadence USB dts node, Visionfive2 default setting
> > > > > > > is USB
> > > > > > > 2.0 device.
> > > > > > >
> > > > > > > Signed-off-by: Minda Chen 
> > > > > > > ---
> > > > > > >  .../dts/jh7110-starfive-visionfive-2.dtsi |  5 ++
> > > > > > >  arch/riscv/dts/jh7110.dtsi| 52
> > > > > +++
> > > > > > >  2 files changed, 57 insertions(+)
> > > > > > >
> > > > > > > diff --git
> > > > > > > a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > > > > > > b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > > > > > > index e11babc1cd..44785bbee3 100644
> > > > > > > --- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > > > > > > +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> > > > > > > @@ -378,3 +378,8 @@
> > > > > > > };
> > > > > > > };
> > > > > > >  };
> > > > > > > +
> > > > > > > +&usb_cdns3 {
> > > > > > > +   dr_mode = "peripheral";
> > > > > > > +   status = "okay";
> > > > > > > +};
> > > > > > > diff --git a/arch/riscv/dts/jh7110.dtsi
> > > > > > > b/arch/riscv/dts/jh7110.dtsi index 2cdc683d49..1eee924e1d
> > > > > > > 100644
> > > > > > > --- a/arch/riscv/dts/jh7110.dtsi
> > > > > > > +++ b/arch/riscv/dts/jh7110.dtsi
> > > > > > > @@ -371,6 +371,58 @@
> > > > > > > status = "disabled";
> > > > > > > };
> > > > > > >
> > > > > > > +   usb0: usb@1010 {
> > > > > > > +   compatible = "starfive,jh7110-usb";
> > > > > > > +   ranges = <0x0 0x0 0x1010
> 0x10>;
> > > > > > > +   #address-cells = <1>;
> > > > > > > +   #size-cells = <1>;
> > > > > > > +   starfive,stg-syscon = <&stg_syscon
> 0x4>;
> > > > > > > +   clocks = <&stgcrg
> > > > > JH7110_STGCLK_USB_LPM>,
> > > > > > > +<&stgcrg
> > > > > JH7110_STGCLK_USB_STB>,
> > > > > > > +<&stgcrg
> > > > > JH7110_STGCLK_USB_APB>,
> > > > > > > +<&stgcrg
> > > > > JH7110_STGCLK_USB_AXI>,
> > > > > > > +<&stgcrg
> > > > > JH7110_STGCLK_USB_UTMI_APB>;
> > > > > > > +   clock-names = "lpm", "stb", "apb",
> > > > > > > + "axi",
> > > > > "utmi_apb";
> > > > > > > +   resets = <&stgcrg
> 

Re: [PATCH v3 5/8] pinctrl: starfive: Setup USB default disable overcurrent pin

[Minda Chen]

> 
> For some JH7110 boards, USB host overcurent pin is not reserved, To make USB
> host work, overcurrent pin must be disabled. So set the pin default disabled.
> 
> Signed-off-by: Minda Chen 
> ---
>  drivers/pinctrl/starfive/pinctrl-jh7110-sys.c | 11 +--
>  1 file changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pinctrl/starfive/pinctrl-jh7110-sys.c
> b/drivers/pinctrl/starfive/pinctrl-jh7110-sys.c
> index dafba65eae..1102985ab9 100644
> --- a/drivers/pinctrl/starfive/pinctrl-jh7110-sys.c
> +++ b/drivers/pinctrl/starfive/pinctrl-jh7110-sys.c
> @@ -378,8 +378,15 @@ static int jh7110_sys_pinctrl_probe(struct udevice
> *dev)  {
>   struct starfive_pinctrl_soc_info *info =
>   (struct starfive_pinctrl_soc_info *)dev_get_driver_data(dev);
> -
> - return starfive_pinctrl_probe(dev, info);
> + struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
> + int ret;
> +
> + ret = starfive_pinctrl_probe(dev, info);
> + /* Set default the usb controller overcurrent signal. */
> + if (!ret)
> + clrsetbits_le32(priv->base + JH7110_SYS_GPI,
> + GENMASK(22, 16), BIT(16));
> + return ret;
>  }
> 
>  static const struct udevice_id jh7110_sys_pinctrl_ids[] = {
> --
> 2.17.1

Hi Rick and Leo
  I think move this to spl is better. 

Re: [PATCH v3 1/8] usb: cdns3: Set USB PHY mode in cdns3_drd_update_mode()

[Minda Chen]

> 
> USB PHY maybe need to set PHY mode in different USB dr mode. So translate
> USB PHY mode to generic PHY mode and call generic_phy_set_mode().
> 
> Signed-off-by: Minda Chen 
> ---
>  drivers/usb/cdns3/drd.c | 14 ++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/drivers/usb/cdns3/drd.c b/drivers/usb/cdns3/drd.c index
> 47874fec29..cbb1334234 100644
> --- a/drivers/usb/cdns3/drd.c
> +++ b/drivers/usb/cdns3/drd.c
> @@ -217,15 +217,19 @@ static int cdns3_init_otg_mode(struct cdns3 *cdns)
> int cdns3_drd_update_mode(struct cdns3 *cdns)  {
>   int ret = 0;
> + int mode;
> 
>   switch (cdns->dr_mode) {
>   case USB_DR_MODE_PERIPHERAL:
> + mode = PHY_MODE_USB_DEVICE;
>   ret = cdns3_set_mode(cdns, USB_DR_MODE_PERIPHERAL);
>   break;
>   case USB_DR_MODE_HOST:
> + mode = PHY_MODE_USB_HOST;
>   ret = cdns3_set_mode(cdns, USB_DR_MODE_HOST);
>   break;
>   case USB_DR_MODE_OTG:
> + mode = PHY_MODE_USB_OTG;
>   ret = cdns3_init_otg_mode(cdns);
>   break;
>   default:
> @@ -234,6 +238,16 @@ int cdns3_drd_update_mode(struct cdns3 *cdns)
>   return -EINVAL;
>   }
> 
> + ret = generic_phy_set_mode(&cdns->usb2_phy, mode, 0);
> + if (ret) {
> + dev_err(cdns->dev, "Set usb 2.0 PHY mode failed %d\n", ret);
> + return ret;
> + }
> +
> + ret = generic_phy_set_mode(&cdns->usb3_phy, mode, 0);
> + if (ret)
> + dev_err(cdns->dev, "Set usb 3.0 PHY mode failed %d\n", ret);
> +
>   return ret;
>  }
> 

Hi Roger
   Is this patch OK now? Could you add review tag to this? Thanks.