From: Mason Huo <mason....@starfivetech.com>
Add the stg clocks for StarFive JH7110 PCIe controller.
Signed-off-by: Mason Huo <mason....@starfivetech.com>
Signed-off-by: Minda Chen <minda.c...@starfivetech.com>
---
drivers/clk/starfive/clk-jh7110.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/drivers/clk/starfive/clk-jh7110.c
b/drivers/clk/starfive/clk-jh7110.c
index a904852cab..7cfed7b847 100644
--- a/drivers/clk/starfive/clk-jh7110.c
+++ b/drivers/clk/starfive/clk-jh7110.c
@@ -305,6 +305,10 @@ static int jh7110_syscrg_init(struct udevice *dev)
clk_dm(JH7110_SYSCLK_AON_APB,
starfive_clk_fix_factor(priv->reg,
"aon_apb", "apb_bus_func", 1, 1));
+ clk_dm(JH7110_SYSCLK_NOCSTG_BUS,
+ starfive_clk_divider(priv->reg,
+ "nocstg_bus", "bus_root",
+ OFFSET(JH7110_SYSCLK_NOCSTG_BUS), 3));
clk_dm(JH7110_SYSCLK_QSPI_AHB,
starfive_clk_gate(priv->reg,
"qspi_ahb", "ahb1",
@@ -342,6 +346,11 @@ static int jh7110_syscrg_init(struct udevice *dev)
starfive_clk_divider(priv->reg,
"usb_125m", "gmacusb_root",
OFFSET(JH7110_SYSCLK_USB_125M), 4));
+ clk_dm(JH7110_SYSCLK_NOC_BUS_STG_AXI,
+ starfive_clk_gate(priv->reg,
+ "noc_bus_stg_axi",
+ "nocstg_bus",
+ OFFSET(JH7110_SYSCLK_NOC_BUS_STG_AXI)));
clk_dm(JH7110_SYSCLK_GMAC1_AHB,
starfive_clk_gate(priv->reg,
"gmac1_ahb", "ahb0",
@@ -512,6 +521,24 @@ static int jh7110_stgcrg_init(struct udevice *dev)
clk_dm(JH7110_STGCLK_USB_REFCLK,
starfive_clk_divider(priv->reg, "usb_refclk", "osc",
STGOFFSET(JH7110_STGCLK_USB_REFCLK), 2));
+ clk_dm(JH7110_STGCLK_PCIE0_TL,
+ starfive_clk_gate(priv->reg, "pcie0_tl", "stg_axiahb",
+ STGOFFSET(JH7110_STGCLK_PCIE0_TL)));
+ clk_dm(JH7110_STGCLK_PCIE0_AXI,
+ starfive_clk_gate(priv->reg, "pcie0_axi_mst0", "stg_axiahb",
+ STGOFFSET(JH7110_STGCLK_PCIE0_AXI)));
+ clk_dm(JH7110_STGCLK_PCIE0_APB,
+ starfive_clk_gate(priv->reg, "pcie0_apb", "stg_apb",
+ STGOFFSET(JH7110_STGCLK_PCIE0_APB)));
+ clk_dm(JH7110_STGCLK_PCIE1_TL,
+ starfive_clk_gate(priv->reg, "pcie1_tl", "stg_axiahb",
+ STGOFFSET(JH7110_STGCLK_PCIE1_TL)));
+ clk_dm(JH7110_STGCLK_PCIE1_AXI,
+ starfive_clk_gate(priv->reg, "pcie1_axi_mst0", "stg_axiahb",
+ STGOFFSET(JH7110_STGCLK_PCIE1_AXI)));
+ clk_dm(JH7110_STGCLK_PCIE1_APB,
+ starfive_clk_gate(priv->reg, "pcie1_apb", "stg_apb",
+ STGOFFSET(JH7110_STGCLK_PCIE1_APB)));
return 0;
}
--
2.17.1
