[PATCH 0/2] Fix sparse warnings
Run and fix sparse warnings in below files -arch/arm/mach-zynqmp/include/mach/sys_proto.h -common/spl/spl.c -arch/arm/mach-versal-net/include/mach/sys_proto.h -arch/arm/mach-versal/include/mach/sys_proto.h -drivers/mmc/zynq_sdhci.c -drivers/spi/zynqmp_gqspi.c Algapally Santosh Sagar (2): xilinx: zynqmp: Add missing prototype for zynqmp_mmio_write xilinx: zynqmp: Add missing prototype for board_boot_order arch/arm/mach-versal-net/include/mach/sys_proto.h | 7 +-- arch/arm/mach-versal/include/mach/sys_proto.h | 6 +- arch/arm/mach-zynqmp/include/mach/sys_proto.h | 1 + common/spl/spl.c | 1 + drivers/mmc/zynq_sdhci.c | 1 + drivers/spi/zynqmp_gqspi.c| 5 + 6 files changed, 10 insertions(+), 11 deletions(-) -- 2.17.1
[PATCH 1/2] xilinx: zynqmp: Add missing prototype for zynqmp_mmio_write
From: Algapally Santosh Sagar
Add missing prototype to fix the sparse warning, warning: no
previous prototype for 'zynqmp_mmio_write' [-Wmissing-prototypes].
Signed-off-by: Algapally Santosh Sagar
Signed-off-by: Ashok Reddy Soma
---
arch/arm/mach-versal-net/include/mach/sys_proto.h | 7 +--
arch/arm/mach-versal/include/mach/sys_proto.h | 6 +-
drivers/mmc/zynq_sdhci.c | 1 +
drivers/spi/zynqmp_gqspi.c| 5 +
4 files changed, 8 insertions(+), 11 deletions(-)
diff --git a/arch/arm/mach-versal-net/include/mach/sys_proto.h
b/arch/arm/mach-versal-net/include/mach/sys_proto.h
index 5bba9030f2..a20cf02712 100644
--- a/arch/arm/mach-versal-net/include/mach/sys_proto.h
+++ b/arch/arm/mach-versal-net/include/mach/sys_proto.h
@@ -8,9 +8,4 @@
void mem_map_fill(void);
-static inline int zynqmp_mmio_write(const u32 address, const u32 mask,
- const u32 value)
-{
- BUILD_BUG();
- return -EINVAL;
-}
+int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
diff --git a/arch/arm/mach-versal/include/mach/sys_proto.h
b/arch/arm/mach-versal/include/mach/sys_proto.h
index 8e5712e0c9..3f01508ecb 100644
--- a/arch/arm/mach-versal/include/mach/sys_proto.h
+++ b/arch/arm/mach-versal/include/mach/sys_proto.h
@@ -13,8 +13,4 @@ enum {
void tcm_init(u8 mode);
void mem_map_fill(void);
-static inline int zynqmp_mmio_write(const u32 address, const u32 mask, const
u32 value)
-{
- BUILD_BUG();
- return -EINVAL;
-}
+int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index 8b559d8a7a..9dc310663f 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -14,6 +14,7 @@
#include "mmc_private.h"
#include
#include
+#include
#include
#include
#include
diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index 335b458cb9..c4aee279aa 100644
--- a/drivers/spi/zynqmp_gqspi.c
+++ b/drivers/spi/zynqmp_gqspi.c
@@ -183,6 +183,11 @@ struct zynqmp_qspi_priv {
const struct spi_mem_op *op;
};
+__weak int zynqmp_mmio_write(const u32 address, const u32 mask, const u32
value)
+{
+ return 0;
+}
+
static int zynqmp_qspi_of_to_plat(struct udevice *bus)
{
struct zynqmp_qspi_plat *plat = dev_get_plat(bus);
--
2.17.1
[PATCH 2/2] xilinx: zynqmp: Add missing prototype for board_boot_order
From: Algapally Santosh Sagar Add missing prototype to fix the sparse warning, warning: no previous prototype for 'board_boot_order' [-Wmissing-prototypes]. Signed-off-by: Algapally Santosh Sagar Signed-off-by: Ashok Reddy Soma --- arch/arm/mach-zynqmp/include/mach/sys_proto.h | 1 + common/spl/spl.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h b/arch/arm/mach-zynqmp/include/mach/sys_proto.h index c6733ed1bb..0f648c47a3 100644 --- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h +++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h @@ -51,6 +51,7 @@ unsigned int zynqmp_get_silicon_version(void); int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value); int zynqmp_mmio_read(const u32 address, u32 *value); +void board_boot_order(u32 *spl_boot_list); void initialize_tcm(bool mode); void mem_map_fill(void); #if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP) diff --git a/common/spl/spl.c b/common/spl/spl.c index a630e79866..6e5f326481 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include -- 2.17.1
[PATCH v2 2/2] xilinx: zynqmp: Add missing prototype for board_boot_order
From: Algapally Santosh Sagar Add missing prototype to fix the sparse warning, warning: no previous prototype for 'board_boot_order' [-Wmissing-prototypes]. Signed-off-by: Algapally Santosh Sagar Signed-off-by: Ashok Reddy Soma --- Changes in v2: - Moved function prototype from sys_proto.h to include/spl.h include/spl.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/spl.h b/include/spl.h index 827bd25c88..bad12fb01f 100644 --- a/include/spl.h +++ b/include/spl.h @@ -884,5 +884,6 @@ void spl_perform_fixups(struct spl_image_info *spl_image); */ struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size); +void board_boot_order(u32 *spl_boot_list); void spl_save_restore_data(void); #endif -- 2.17.1
[PATCH v2 0/2] Fix sparse warnings
Run and fix sparse warnings in below files -arch/arm/mach-zynqmp/include/mach/sys_proto.h -common/spl/spl.c -arch/arm/mach-versal-net/include/mach/sys_proto.h -arch/arm/mach-versal/include/mach/sys_proto.h -drivers/mmc/zynq_sdhci.c -drivers/spi/zynqmp_gqspi.c Changes in v2: - Moved function prototype from sys_proto.h to include/spl.h Algapally Santosh Sagar (2): xilinx: zynqmp: Add missing prototype for zynqmp_mmio_write xilinx: zynqmp: Add missing prototype for board_boot_order arch/arm/mach-versal-net/include/mach/sys_proto.h | 7 +-- arch/arm/mach-versal/include/mach/sys_proto.h | 6 +- drivers/mmc/zynq_sdhci.c | 1 + drivers/spi/zynqmp_gqspi.c| 5 + include/spl.h | 1 + 5 files changed, 9 insertions(+), 11 deletions(-) -- 2.17.1
[PATCH v2 1/2] xilinx: zynqmp: Add missing prototype for zynqmp_mmio_write
From: Algapally Santosh Sagar
Add missing prototype to fix the sparse warning, warning: no
previous prototype for 'zynqmp_mmio_write' [-Wmissing-prototypes].
Signed-off-by: Algapally Santosh Sagar
Signed-off-by: Ashok Reddy Soma
---
(no changes since v1)
arch/arm/mach-versal-net/include/mach/sys_proto.h | 7 +--
arch/arm/mach-versal/include/mach/sys_proto.h | 6 +-
drivers/mmc/zynq_sdhci.c | 1 +
drivers/spi/zynqmp_gqspi.c| 5 +
4 files changed, 8 insertions(+), 11 deletions(-)
diff --git a/arch/arm/mach-versal-net/include/mach/sys_proto.h
b/arch/arm/mach-versal-net/include/mach/sys_proto.h
index 5bba9030f2..a20cf02712 100644
--- a/arch/arm/mach-versal-net/include/mach/sys_proto.h
+++ b/arch/arm/mach-versal-net/include/mach/sys_proto.h
@@ -8,9 +8,4 @@
void mem_map_fill(void);
-static inline int zynqmp_mmio_write(const u32 address, const u32 mask,
- const u32 value)
-{
- BUILD_BUG();
- return -EINVAL;
-}
+int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
diff --git a/arch/arm/mach-versal/include/mach/sys_proto.h
b/arch/arm/mach-versal/include/mach/sys_proto.h
index 8e5712e0c9..3f01508ecb 100644
--- a/arch/arm/mach-versal/include/mach/sys_proto.h
+++ b/arch/arm/mach-versal/include/mach/sys_proto.h
@@ -13,8 +13,4 @@ enum {
void tcm_init(u8 mode);
void mem_map_fill(void);
-static inline int zynqmp_mmio_write(const u32 address, const u32 mask, const
u32 value)
-{
- BUILD_BUG();
- return -EINVAL;
-}
+int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index 8b559d8a7a..9dc310663f 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -14,6 +14,7 @@
#include "mmc_private.h"
#include
#include
+#include
#include
#include
#include
diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index 335b458cb9..c4aee279aa 100644
--- a/drivers/spi/zynqmp_gqspi.c
+++ b/drivers/spi/zynqmp_gqspi.c
@@ -183,6 +183,11 @@ struct zynqmp_qspi_priv {
const struct spi_mem_op *op;
};
+__weak int zynqmp_mmio_write(const u32 address, const u32 mask, const u32
value)
+{
+ return 0;
+}
+
static int zynqmp_qspi_of_to_plat(struct udevice *bus)
{
struct zynqmp_qspi_plat *plat = dev_get_plat(bus);
--
2.17.1
[PATCH 0/4] Fix arasan nand driver issues
In this patch series - Remove hardcoding of NAND_BBT_USE_FLASH in nand->bbt_options - Find and update nand ofnode. - Fix nand node in zynqmp-zc1751-xm017-dc3.dts file - Enable nand-on-flash-bbt flag in zynqmp DT's by default Ashok Reddy Soma (4): mtd: nand: arasan: Remove hardcoded bbt option mtd: nand: arasan: Set ofnode value arm64: dts: zynqmp: Fix nand dt node arm64: dts: zynqmp: Enable nand-on-flash-bbt in DT by default arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 2 + arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts | 119 ++- drivers/mtd/nand/raw/arasan_nfc.c| 5 +- 3 files changed, 78 insertions(+), 48 deletions(-) -- 2.17.1
[PATCH 1/4] mtd: nand: arasan: Remove hardcoded bbt option
Bad block table option is hardcoded to read from flash with NAND_BBT_USE_FLASH option. This decision should be done based on DT property. Remove this hardcoding, to be able to use DT property. Signed-off-by: Ashok Reddy Soma --- drivers/mtd/nand/raw/arasan_nfc.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/mtd/nand/raw/arasan_nfc.c b/drivers/mtd/nand/raw/arasan_nfc.c index 4621bfb03e..ddb4cb1cba 100644 --- a/drivers/mtd/nand/raw/arasan_nfc.c +++ b/drivers/mtd/nand/raw/arasan_nfc.c @@ -1248,7 +1248,6 @@ static int arasan_probe(struct udevice *dev) /* Buffer read/write routines */ nand_chip->read_buf = arasan_nand_read_buf; nand_chip->write_buf = arasan_nand_write_buf; - nand_chip->bbt_options = NAND_BBT_USE_FLASH; writel(0x0, &info->reg->cmd_reg); writel(0x0, &info->reg->pgm_reg); -- 2.17.1
[PATCH 2/4] mtd: nand: arasan: Set ofnode value
Ofnode value is not set, so all the DT properties are not being read and due to this default values are being used. Find nand node and set chip->flash_node value. Signed-off-by: Ashok Reddy Soma --- drivers/mtd/nand/raw/arasan_nfc.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/mtd/nand/raw/arasan_nfc.c b/drivers/mtd/nand/raw/arasan_nfc.c index ddb4cb1cba..99e2681c14 100644 --- a/drivers/mtd/nand/raw/arasan_nfc.c +++ b/drivers/mtd/nand/raw/arasan_nfc.c @@ -1230,12 +1230,16 @@ static int arasan_probe(struct udevice *dev) struct nand_drv *info = &arasan->nand_ctrl; struct nand_config *nand = &info->config; struct mtd_info *mtd; + ofnode child; int err = -1; info->reg = (struct nand_regs *)dev_read_addr(dev); mtd = nand_to_mtd(nand_chip); nand_set_controller_data(nand_chip, &arasan->nand_ctrl); + ofnode_for_each_subnode(child, dev_ofnode(dev)) + nand_set_flash_node(nand_chip, child); + #ifdef CONFIG_SYS_NAND_NO_SUBPAGE_WRITE nand_chip->options |= NAND_NO_SUBPAGE_WRITE; #endif -- 2.17.1
[PATCH 3/4] arm64: dts: zynqmp: Fix nand dt node
DC3 nand node is not correct, it is showing all partitions under
controller node directly. Create two sub nand nodes with partitions for
each.
Signed-off-by: Ashok Reddy Soma
---
arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts | 117 ++-
1 file changed, 70 insertions(+), 47 deletions(-)
diff --git a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
index 13812470ae..8a06c2a90a 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
@@ -128,54 +128,77 @@
arasan,has-mdma;
num-cs = <2>;
- partition@0 { /* for testing purpose */
- label = "nand-fsbl-uboot";
- reg = <0x0 0x0 0x40>;
+ nand@0 {
+ reg = <0x0>;
+ #address-cells = <0x2>;
+ #size-cells = <0x1>;
+ nand-ecc-mode = "soft";
+ nand-ecc-algo = "bch";
+ nand-rb = <0>;
+ label = "main-storage-0";
+ nand-ecc-step-size = <1024>;
+ nand-ecc-strength = <24>;
+
+ partition@0 { /* for testing purpose */
+ label = "nand-fsbl-uboot";
+ reg = <0x0 0x0 0x40>;
+ };
+ partition@1 { /* for testing purpose */
+ label = "nand-linux";
+ reg = <0x0 0x40 0x140>;
+ };
+ partition@2 { /* for testing purpose */
+ label = "nand-device-tree";
+ reg = <0x0 0x180 0x40>;
+ };
+ partition@3 { /* for testing purpose */
+ label = "nand-rootfs";
+ reg = <0x0 0x1C0 0x140>;
+ };
+ partition@4 { /* for testing purpose */
+ label = "nand-bitstream";
+ reg = <0x0 0x300 0x40>;
+ };
+ partition@5 { /* for testing purpose */
+ label = "nand-misc";
+ reg = <0x0 0x340 0xFCC0>;
+ };
};
- partition@1 { /* for testing purpose */
- label = "nand-linux";
- reg = <0x0 0x40 0x140>;
- };
- partition@2 { /* for testing purpose */
- label = "nand-device-tree";
- reg = <0x0 0x180 0x40>;
- };
- partition@3 { /* for testing purpose */
- label = "nand-rootfs";
- reg = <0x0 0x1C0 0x140>;
- };
- partition@4 { /* for testing purpose */
- label = "nand-bitstream";
- reg = <0x0 0x300 0x40>;
- };
- partition@5 { /* for testing purpose */
- label = "nand-misc";
- reg = <0x0 0x340 0xFCC0>;
- };
-
- partition@6 { /* for testing purpose */
- label = "nand1-fsbl-uboot";
- reg = <0x1 0x0 0x40>;
- };
- partition@7 { /* for testing purpose */
- label = "nand1-linux";
- reg = <0x1 0x40 0x140>;
- };
- partition@8 { /* for testing purpose */
- label = "nand1-device-tree";
- reg = <0x1 0x180 0x40>;
- };
- partition@9 { /* for testing purpose */
- label = "nand1-rootfs";
- reg = <0x1 0x1C0 0x140>;
- };
- partition@10 { /* for testing purpose */
- label = "nand1-bitstream";
- reg = <0x1 0x300 0x40>;
- };
- partition@11 { /* for testing purpose */
- label = "nand1-misc";
- reg = <0x1 0x340 0xFCC0>;
+ nand@1 {
+ reg = <0x1>;
+ #address-cells = <0x2>;
+ #size-cells = <0x1>;
+ nand-ecc-mode = "soft";
+ nand-ecc-algo = "bch";
+ nand-rb = <0>;
+ label = "main-storage-1";
+ nand-ecc-step-size = <1024>;
+ nand-ecc-strength = <24>;
+
+ partition@0 { /* for testing purpose */
+ label = "nand1-fsbl-uboot";
+ reg = <0x0 0x0 0x40>;
+ };
+ partition@1 { /* for testing purpose */
+ label = "nand1-linux";
+ reg = <0x0 0x4
[PATCH 4/4] arm64: dts: zynqmp: Enable nand-on-flash-bbt in DT by default
By default enable nand-on-flash-bbt DT flag, so that driver always refers
to the bad block table(bbt) present on the flash device.
Signed-off-by: Ashok Reddy Soma
---
arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 2 ++
arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
index 4e6160bcd8..b6bc2f5be0 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
@@ -142,6 +142,7 @@
label = "main-storage-0";
nand-ecc-step-size = <1024>;
nand-ecc-strength = <24>;
+ nand-on-flash-bbt;
partition@0 { /* for testing purpose */
label = "nand-fsbl-uboot";
@@ -178,6 +179,7 @@
label = "main-storage-1";
nand-ecc-step-size = <1024>;
nand-ecc-strength = <24>;
+ nand-on-flash-bbt;
partition@0 { /* for testing purpose */
label = "nand1-fsbl-uboot";
diff --git a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
index 8a06c2a90a..6021f8b4e1 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
@@ -138,6 +138,7 @@
label = "main-storage-0";
nand-ecc-step-size = <1024>;
nand-ecc-strength = <24>;
+ nand-on-flash-bbt;
partition@0 { /* for testing purpose */
label = "nand-fsbl-uboot";
@@ -174,6 +175,7 @@
label = "main-storage-1";
nand-ecc-step-size = <1024>;
nand-ecc-strength = <24>;
+ nand-on-flash-bbt;
partition@0 { /* for testing purpose */
label = "nand1-fsbl-uboot";
--
2.17.1
[PATCH v3 0/2] Fix sparse warnings
Run and fix sparse warnings in below files -arch/arm/mach-zynqmp/include/mach/sys_proto.h -common/spl/spl.c -arch/arm/mach-versal-net/include/mach/sys_proto.h -arch/arm/mach-versal/include/mach/sys_proto.h -drivers/mmc/zynq_sdhci.c -drivers/spi/zynqmp_gqspi.c Changes in v3: - Replaced xilinx: zynqmp with just spl: from the commit header Changes in v2: - Moved function prototype from sys_proto.h to include/spl.h Algapally Santosh Sagar (2): xilinx: zynqmp: Add missing prototype for zynqmp_mmio_write spl: Add missing prototype for board_boot_order arch/arm/mach-versal-net/include/mach/sys_proto.h | 7 +-- arch/arm/mach-versal/include/mach/sys_proto.h | 6 +- drivers/mmc/zynq_sdhci.c | 1 + drivers/spi/zynqmp_gqspi.c| 5 + include/spl.h | 1 + 5 files changed, 9 insertions(+), 11 deletions(-) -- 2.17.1
[PATCH v3 1/2] xilinx: zynqmp: Add missing prototype for zynqmp_mmio_write
From: Algapally Santosh Sagar
Add missing prototype to fix the sparse warning, warning: no
previous prototype for 'zynqmp_mmio_write' [-Wmissing-prototypes].
Signed-off-by: Algapally Santosh Sagar
Signed-off-by: Ashok Reddy Soma
---
(no changes since v1)
arch/arm/mach-versal-net/include/mach/sys_proto.h | 7 +--
arch/arm/mach-versal/include/mach/sys_proto.h | 6 +-
drivers/mmc/zynq_sdhci.c | 1 +
drivers/spi/zynqmp_gqspi.c| 5 +
4 files changed, 8 insertions(+), 11 deletions(-)
diff --git a/arch/arm/mach-versal-net/include/mach/sys_proto.h
b/arch/arm/mach-versal-net/include/mach/sys_proto.h
index 5bba9030f2..a20cf02712 100644
--- a/arch/arm/mach-versal-net/include/mach/sys_proto.h
+++ b/arch/arm/mach-versal-net/include/mach/sys_proto.h
@@ -8,9 +8,4 @@
void mem_map_fill(void);
-static inline int zynqmp_mmio_write(const u32 address, const u32 mask,
- const u32 value)
-{
- BUILD_BUG();
- return -EINVAL;
-}
+int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
diff --git a/arch/arm/mach-versal/include/mach/sys_proto.h
b/arch/arm/mach-versal/include/mach/sys_proto.h
index 8e5712e0c9..3f01508ecb 100644
--- a/arch/arm/mach-versal/include/mach/sys_proto.h
+++ b/arch/arm/mach-versal/include/mach/sys_proto.h
@@ -13,8 +13,4 @@ enum {
void tcm_init(u8 mode);
void mem_map_fill(void);
-static inline int zynqmp_mmio_write(const u32 address, const u32 mask, const
u32 value)
-{
- BUILD_BUG();
- return -EINVAL;
-}
+int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index 8b559d8a7a..9dc310663f 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -14,6 +14,7 @@
#include "mmc_private.h"
#include
#include
+#include
#include
#include
#include
diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index 335b458cb9..c4aee279aa 100644
--- a/drivers/spi/zynqmp_gqspi.c
+++ b/drivers/spi/zynqmp_gqspi.c
@@ -183,6 +183,11 @@ struct zynqmp_qspi_priv {
const struct spi_mem_op *op;
};
+__weak int zynqmp_mmio_write(const u32 address, const u32 mask, const u32
value)
+{
+ return 0;
+}
+
static int zynqmp_qspi_of_to_plat(struct udevice *bus)
{
struct zynqmp_qspi_plat *plat = dev_get_plat(bus);
--
2.17.1
[PATCH v3 2/2] spl: Add missing prototype for board_boot_order
From: Algapally Santosh Sagar Add missing prototype to fix the sparse warning, warning: no previous prototype for 'board_boot_order' [-Wmissing-prototypes]. Signed-off-by: Algapally Santosh Sagar Signed-off-by: Ashok Reddy Soma --- Changes in v3: - Replaced xilinx: zynqmp with just spl: from the commit header Changes in v2: - Moved function prototype from sys_proto.h to include/spl.h include/spl.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/spl.h b/include/spl.h index 827bd25c88..bad12fb01f 100644 --- a/include/spl.h +++ b/include/spl.h @@ -884,5 +884,6 @@ void spl_perform_fixups(struct spl_image_info *spl_image); */ struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size); +void board_boot_order(u32 *spl_boot_list); void spl_save_restore_data(void); #endif -- 2.17.1
[PATCH] env: Fix default environment saving issue
When CONFIG_SYS_REDUNDAND_ENVIRONMENT is enabled, by default env is
getting saved to redundant environment irrespective of primary env is
present or not.
It means even if primary and redundant environment are not present, by
default, env is getting stored to redundant environment. Even if primary
env is present, it is choosing to store in redudndant env.
Ideally it should look for primary env and choose to store in primary env
if it is present. If both primary and redundant env are not present then
it should save in to primary env area.
Fix the issue by making env_valid = ENV_INVALID when both the
environments are not present.
Signed-off-by: Ashok Reddy Soma
---
env/common.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/env/common.c b/env/common.c
index 8beb8e6aa4..0ecdb248a0 100644
--- a/env/common.c
+++ b/env/common.c
@@ -353,6 +353,7 @@ int env_check_redund(const char *buf1, int buf1_read_fail,
tmp_env2->crc;
if (!crc1_ok && !crc2_ok) {
+ gd->env_valid = ENV_INVALID;
return -ENOMSG; /* needed for env_load() */
} else if (crc1_ok && !crc2_ok) {
gd->env_valid = ENV_VALID;
--
2.17.1
[PATCH] zynqmp: config: Add proper dependency for CONFIG_DFU_MMC
When CONFIG_CMD_MMC and CONFIG_MMC are disabled, still some compilation errors are seen as below due to unresolved symbols. drivers/dfu/dfu_mmc.o: in function `mmc_block_op': drivers/dfu/dfu_mmc.c:32: undefined reference to `find_mmc_device' drivers/dfu/dfu_mmc.c:54: undefined reference to `mmc_get_blk_desc' drivers/dfu/dfu_mmc.c:67: undefined reference to `mmc_get_blk_desc' drivers/dfu/dfu_mmc.c:70: undefined reference to `mmc_get_blk_desc' drivers/dfu/dfu_mmc.o: in function `dfu_fill_entity_mmc': drivers/dfu/dfu_mmc.c:369: undefined reference to `find_mmc_device' drivers/dfu/dfu_mmc.c:376: undefined reference to `mmc_init' drivers/dfu/dfu_mmc.c:403: undefined reference to `mmc_get_blk_desc' gnu/aarch64/lin/aarch64-linux/bin/aarch64-linux-gnu-ld.bfd: line 4: 31661 Segmentation fault (core dumped) $CC --sysroot=$LIBC --no-warn-rwx-segment "$@" Makefile:1760: recipe for target 'u-boot' failed make: *** [u-boot] Error 139 make: *** Deleting file 'u-boot' Add dependency of CONFIG_MMC for CONFIG_DFU_MMC config to fix the errors. Signed-off-by: Ashok Reddy Soma --- drivers/dfu/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/dfu/Kconfig b/drivers/dfu/Kconfig index 8d7f13dcb0..8e9e8eb4fe 100644 --- a/drivers/dfu/Kconfig +++ b/drivers/dfu/Kconfig @@ -35,6 +35,7 @@ config DFU_TIMEOUT config DFU_MMC bool "MMC back end for DFU" + depends on MMC help This option enables using DFU to read and write to MMC based storage. -- 2.17.1
[PATCH v2] dfu: Add proper dependency for CONFIG_DFU_MMC
When CONFIG_CMD_MMC and CONFIG_MMC are disabled, still some compilation errors are seen as below due to unresolved symbols. drivers/dfu/dfu_mmc.o: in function `mmc_block_op': drivers/dfu/dfu_mmc.c:32: undefined reference to `find_mmc_device' drivers/dfu/dfu_mmc.c:54: undefined reference to `mmc_get_blk_desc' drivers/dfu/dfu_mmc.c:67: undefined reference to `mmc_get_blk_desc' drivers/dfu/dfu_mmc.c:70: undefined reference to `mmc_get_blk_desc' drivers/dfu/dfu_mmc.o: in function `dfu_fill_entity_mmc': drivers/dfu/dfu_mmc.c:369: undefined reference to `find_mmc_device' drivers/dfu/dfu_mmc.c:376: undefined reference to `mmc_init' drivers/dfu/dfu_mmc.c:403: undefined reference to `mmc_get_blk_desc' gnu/aarch64/lin/aarch64-linux/bin/aarch64-linux-gnu-ld.bfd: line 4: 31661 Segmentation fault (core dumped) $CC --sysroot=$LIBC --no-warn-rwx-segment "$@" Makefile:1760: recipe for target 'u-boot' failed make: *** [u-boot] Error 139 make: *** Deleting file 'u-boot' Add dependency of CONFIG_MMC for CONFIG_DFU_MMC config to fix the errors. Signed-off-by: Ashok Reddy Soma --- Changes in v2: - Changed patch subject prefix to dfu from zynqmp: config drivers/dfu/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/dfu/Kconfig b/drivers/dfu/Kconfig index 8d7f13dcb0..8e9e8eb4fe 100644 --- a/drivers/dfu/Kconfig +++ b/drivers/dfu/Kconfig @@ -35,6 +35,7 @@ config DFU_TIMEOUT config DFU_MMC bool "MMC back end for DFU" + depends on MMC help This option enables using DFU to read and write to MMC based storage. -- 2.17.1
[PATCH 0/2] Fix dependencies of USB Kconfig options
When USB device driver CONFIG_USB and CONFIG_CMD_USB are disabled, some compilation issues are seen. Also CMD_THOR_DOWNLOAD should depend on CONFIG_CMD_USB. Add dependencies to resolve those issues and compile properly. Also remove unused config CONFIG_ZYNQMP_USB. Ashok Reddy Soma (2): cmd: thordown: Add proper dependency for CMD_THOR_DOWNLOAD zynqmp: config: Add proper dependencies for USB arch/arm/mach-zynqmp/Kconfig | 3 --- cmd/Kconfig | 1 + configs/xilinx_zynqmp_virt_defconfig | 1 - include/configs/xilinx_zynqmp.h | 4 ++-- 4 files changed, 3 insertions(+), 6 deletions(-) -- 2.17.1
[PATCH 2/2] zynqmp: config: Add proper dependencies for USB
When CONFIG_CMD_USB and CONFIG_USB are disabled, still some compilation
errors are seen as below.
In file included from include/configs/xilinx_zynqmp.h:173,
from include/config.h:3,
from include/common.h:16,
from env/common.c:10:
include/config_distro_bootcmd.h:302:9: error: expected '}' before
'BOOT_TARGET_DEVICES_references_USB_without_CONFIG_CMD_USB'
302 | BOOT_TARGET_DEVICES_references_USB_without_CONFIG_CMD_USB
| ^
include/config_distro_bootcmd.h:302:9: note: in definition of macro
'BOOTENV_DEV_NAME_USB'
302 | BOOT_TARGET_DEVICES_references_USB_without_CONFIG_CMD_USB
| ^
include/configs/xilinx_zynqmp.h:77:41: note: in expansion of macro
'BOOTENV_DEV_NAME'
77 | # define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0)
func(USB, usb, 1)
| ^~~~
include/configs/xilinx_zynqmp.h:168:9: note: in expansion of macro
'BOOT_TARGET_DEVICES_USB'
168 | BOOT_TARGET_DEVICES_USB(func) \
| ^~~
include/config_distro_bootcmd.h:454:25: note: in expansion of macro
'BOOT_TARGET_DEVICES'
454 | "boot_targets=" BOOT_TARGET_DEVICES(BOOTENV_DEV_NAME) "\0"
| ^~~
include/config_distro_bootcmd.h:474:9: note: in expansion of macro
'BOOTENV_BOOT_TARGETS'
474 | BOOTENV_BOOT_TARGETS \
| ^~~~
include/configs/xilinx_zynqmp.h:179:9: note: in expansion of macro
'BOOTENV'
179 | BOOTENV
| ^~~
include/env_default.h:120:9: note: in expansion of macro
'CFG_EXTRA_ENV_SETTINGS'
120 | CFG_EXTRA_ENV_SETTINGS
| ^~
In file included from env/common.c:32:
include/env_default.h:27:36: note: to match this '{'
27 | const char default_environment[] = {
|^
scripts/Makefile.build:256: recipe for target 'env/common.o' failed
make[1]: *** [env/common.o] Error 1
Makefile:1853: recipe for target 'env' failed
make: *** [env] Error 2
make: *** Waiting for unfinished jobs
Add CONFIG_USB_STORAGE as dependency for USB related macro's such as
BOOT_TARGET_DEVICES_USB() and DFU_DEFAULT_POLL_TIMEOUT and
CONFIG_THOR_RESET_OFF.
Remove CONFIG_ZYNQMP_USB from Kconfig and also from defconfig since it
is not used anywhere else.
Signed-off-by: Ashok Reddy Soma
---
arch/arm/mach-zynqmp/Kconfig | 3 ---
configs/xilinx_zynqmp_virt_defconfig | 1 -
include/configs/xilinx_zynqmp.h | 4 ++--
3 files changed, 2 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig
index fd6f07715a..26b80b7882 100644
--- a/arch/arm/mach-zynqmp/Kconfig
+++ b/arch/arm/mach-zynqmp/Kconfig
@@ -84,9 +84,6 @@ config ZYNQMP_SPL_PM_CFG_OBJ_FILE
Leave this option empty if your PMU firmware has a hard-coded
configuration object or you are loading it by any other means.
-config ZYNQMP_USB
- bool "Configure ZynqMP USB"
-
config ZYNQMP_NO_DDR
bool "Disable DDR MMU mapping"
help
diff --git a/configs/xilinx_zynqmp_virt_defconfig
b/configs/xilinx_zynqmp_virt_defconfig
index c4bbde2206..6bda4f8453 100644
--- a/configs/xilinx_zynqmp_virt_defconfig
+++ b/configs/xilinx_zynqmp_virt_defconfig
@@ -17,7 +17,6 @@ CONFIG_ENV_OFFSET_REDUND=0x1E8
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_CMD_FRU=y
-CONFIG_ZYNQMP_USB=y
CONFIG_SYS_LOAD_ADDR=0x800
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 011f0034c5..44f8914b80 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -29,7 +29,7 @@
/* Miscellaneous configurable options */
-#if defined(CONFIG_ZYNQMP_USB)
+#if defined(CONFIG_USB_STORAGE)
#define DFU_DEFAULT_POLL_TIMEOUT 300
# define PARTS_DEFAULT \
@@ -73,7 +73,7 @@
# define BOOT_TARGET_DEVICES_SCSI(func)
#endif
-#if defined(CONFIG_ZYNQMP_USB)
+#if defined(CONFIG_USB_STORAGE)
# define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) func(USB, usb, 1)
#else
# define BOOT_TARGET_DEVICES_USB(func)
--
2.17.1
[PATCH 1/2] cmd: thordown: Add proper dependency for CMD_THOR_DOWNLOAD
When CONFIG_CMD_USB and CONFIG_USB are disabled some compilation errors are seen as below. cmd/thordown.o: in function `usb_gadget_initialize': include/linux/usb/gadget.h:981: undefined reference to `board_usb_init' cmd/thordown.o: in function `do_thor_down': cmd/thordown.c:68: undefined reference to `g_dnl_unregister' cmd/thordown.o: in function `usb_gadget_release': include/linux/usb/gadget.h:986: undefined reference to `board_usb_cleanup' cmd/thordown.o: in function `do_thor_down': cmd/thordown.c:41: undefined reference to `g_dnl_register' cmd/thordown.c:48: undefined reference to `thor_init' cmd/thordown.c:56: undefined reference to `thor_handle' gnu/aarch64/lin/aarch64-linux/bin/aarch64-linux-gnu-ld.bfd: line 4: 8485 Segmentation fault (core dumped) $CC --sysroot=$LIBC --no-warn-rwx-segment "$@" Makefile:1779: recipe for target 'u-boot' failed make: *** [u-boot] Error 139 make: *** Deleting file 'u-boot' Add dependency of CMD_USB for CONFIG_CMD_THOR_DOWNLOAD to fix the errors. Signed-off-by: Ashok Reddy Soma --- cmd/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/cmd/Kconfig b/cmd/Kconfig index 02e54f1e50..b44df9d67a 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -526,6 +526,7 @@ config CMD_SPL_WRITE_SIZE config CMD_THOR_DOWNLOAD bool "thor - TIZEN 'thor' download" + depends on CMD_USB select DFU help Implements the 'thor' download protocol. This is a way of -- 2.17.1
[PATCH] clk: Dont return error when assigned-clocks is empty or missing
There is a chance that assigned-clock-rates is given and assigned-clocks
could be empty. Dont return error in that case, because the probe of the
corresponding driver will not be called at all if this fails.
Better to continue to look for it and return 0.
Signed-off-by: Ashok Reddy Soma
---
drivers/clk/clk-uclass.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index dc3e9d6a26..f186fcbcdb 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -329,7 +329,13 @@ static int clk_set_default_rates(struct udevice *dev,
dev_dbg(dev,
"could not get assigned clock %d (err = %d)\n",
index, ret);
- continue;
+ /* Skip if it is empty */
+ if (ret == -ENOENT) {
+ ret = 0;
+ continue;
+ }
+
+ return ret;
}
/* This is clk provider device trying to program itself
--
2.17.1
[PATCH] clk: zynqmp: Add set_rate support for gem rx and tsu clks
gem0_rx till gem3_rx and gem_tsu are missing from set rate function.
Add them, so that they can be set from pmu firmware via clock framework.
Signed-off-by: Ashok Reddy Soma
---
drivers/clk/clk_zynqmp.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c
index be0ee50e0e..27479391e1 100644
--- a/drivers/clk/clk_zynqmp.c
+++ b/drivers/clk/clk_zynqmp.c
@@ -718,6 +718,8 @@ static ulong zynqmp_clk_set_rate(struct clk *clk, ulong
rate)
switch (id) {
case gem0_ref ... gem3_ref:
case gem0_tx ... gem3_tx:
+ case gem0_rx ... gem3_rx:
+ case gem_tsu:
case qspi_ref ... can1_ref:
case usb0_bus_ref ... usb3_dual_ref:
return zynqmp_clk_set_peripheral_rate(priv, id,
--
2.17.1
[PATCH] clk: zynqmp: Add gem rx and tsu clocks to return register
Add gem_tsu and gem0_rx till gem3_rx to return proper register from zynqmp_clk_get_register. Otherwise firmware won't be able to set clock for these due to incorrect register address. Signed-off-by: Ashok Reddy Soma --- drivers/clk/clk_zynqmp.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c index 27479391e1..b0843fe546 100644 --- a/drivers/clk/clk_zynqmp.c +++ b/drivers/clk/clk_zynqmp.c @@ -269,17 +269,22 @@ static u32 zynqmp_clk_get_register(enum zynqmp_clk id) case usb3_dual_ref: return CRL_APB_USB3_DUAL_REF_CTRL; case gem_tsu_ref: + case gem_tsu: return CRL_APB_GEM_TSU_REF_CTRL; case gem0_tx: + case gem0_rx: case gem0_ref: return CRL_APB_GEM0_REF_CTRL; case gem1_tx: + case gem1_rx: case gem1_ref: return CRL_APB_GEM1_REF_CTRL; case gem2_tx: + case gem2_rx: case gem2_ref: return CRL_APB_GEM2_REF_CTRL; case gem3_tx: + case gem3_rx: case gem3_ref: return CRL_APB_GEM3_REF_CTRL; case usb0_bus_ref: -- 2.17.1
[PATCH 2/2] arm64: versal: Add octal spi flash mini u-boot configuration
Add configuration file for mini u-boot configuration which runs on a smaller footprint from on chip memory(OCM). This configuration has required CONFIG's enabled to support octal spi flash and uses DCC terminal for console output. Signed-off-by: Ashok Reddy Soma --- configs/xilinx_versal_mini_ospi_defconfig | 71 +++ 1 file changed, 71 insertions(+) create mode 100644 configs/xilinx_versal_mini_ospi_defconfig diff --git a/configs/xilinx_versal_mini_ospi_defconfig b/configs/xilinx_versal_mini_ospi_defconfig new file mode 100644 index 00..7212c38083 --- /dev/null +++ b/configs/xilinx_versal_mini_ospi_defconfig @@ -0,0 +1,71 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="xilinx_versal_mini_qspi" +CONFIG_ARCH_VERSAL=y +CONFIG_SYS_TEXT_BASE=0xFFFC +CONFIG_SYS_MALLOC_LEN=0x2000 +CONFIG_SYS_MALLOC_F_LEN=0x500 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x80 +# CONFIG_DM_GPIO is not set +CONFIG_DEFAULT_DEVICE_TREE="versal-mini-ospi-single" +CONFIG_SYS_MEM_RSVD_FOR_MMU=y +CONFIG_COUNTER_FREQUENCY=1 +CONFIG_VERSAL_NO_DDR=y +# CONFIG_PSCI_RESET is not set +# CONFIG_EXPERT is not set +CONFIG_SYS_LOAD_ADDR=0x800 +# CONFIG_AUTOBOOT is not set +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_BOARD_LATE_INIT is not set +# CONFIG_CMDLINE_EDITING is not set +# CONFIG_AUTO_COMPLETE is not set +# CONFIG_SYS_LONGHELP is not set +CONFIG_SYS_PROMPT="Versal> " +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTM is not set +# CONFIG_CMD_BOOTI is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_FDT is not set +# CONFIG_CMD_GO is not set +# CONFIG_CMD_RUN is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_ECHO is not set +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_PARTITIONS is not set +# CONFIG_NET is not set +# CONFIG_DM_WARN is not set +# CONFIG_DM_DEVICE_REMOVE is not set +# CONFIG_MMC is not set +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=3000 +CONFIG_SPI_FLASH_SOFT_RESET=y +CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MT35XU=y +CONFIG_ARM_DCC=y +CONFIG_SOC_XILINX_VERSAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_CADENCE_OSPI_VERSAL=y +CONFIG_HAS_CQSPI_REF_CLK=y +CONFIG_CQSPI_REF_CLK=2 +# CONFIG_LMB is not set -- 2.17.1
[PATCH 1/2] arm64: versal: Add qspi flash mini u-boot configuration
Add configuration file for mini u-boot configuration which runs on a smaller footprint from on chip memory(OCM). This configuration has required CONFIG's enabled to support qspi flash and uses DCC terminal for console output. Signed-off-by: Ashok Reddy Soma --- MAINTAINERS | 1 + configs/xilinx_versal_mini_qspi_defconfig | 74 +++ 2 files changed, 75 insertions(+) create mode 100644 configs/xilinx_versal_mini_qspi_defconfig diff --git a/MAINTAINERS b/MAINTAINERS index 83346183ee..70ad67a0ce 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -634,6 +634,7 @@ M: Michal Simek S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git F: arch/arm/mach-versal/ +F: configs/xilinx_* F: drivers/net/xilinx_axi_mrmac.* F: drivers/soc/soc_xilinx_versal.c F: drivers/spi/cadence_ospi_versal.c diff --git a/configs/xilinx_versal_mini_qspi_defconfig b/configs/xilinx_versal_mini_qspi_defconfig new file mode 100644 index 00..bb53e6c913 --- /dev/null +++ b/configs/xilinx_versal_mini_qspi_defconfig @@ -0,0 +1,74 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="xilinx_versal_mini_qspi" +CONFIG_ARCH_VERSAL=y +CONFIG_SYS_TEXT_BASE=0xFFFC +CONFIG_SYS_MALLOC_LEN=0x2000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x80 +CONFIG_DEFAULT_DEVICE_TREE="versal-mini-qspi-single" +CONFIG_SYS_MEM_RSVD_FOR_MMU=y +CONFIG_COUNTER_FREQUENCY=1 +CONFIG_VERSAL_NO_DDR=y +# CONFIG_PSCI_RESET is not set +# CONFIG_EXPERT is not set +CONFIG_SYS_LOAD_ADDR=0x800 +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +# CONFIG_AUTOBOOT is not set +CONFIG_LOGLEVEL=0 +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_BOARD_LATE_INIT is not set +# CONFIG_CMDLINE_EDITING is not set +# CONFIG_AUTO_COMPLETE is not set +# CONFIG_SYS_LONGHELP is not set +CONFIG_SYS_PROMPT="Versal> " +# CONFIG_SYS_XTRACE is not set +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTM is not set +# CONFIG_CMD_BOOTI is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_FDT is not set +# CONFIG_CMD_GO is not set +# CONFIG_CMD_RUN is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_ECHO is not set +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_PARTITIONS is not set +# CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG is not set +# CONFIG_NET is not set +# CONFIG_DM_WARN is not set +# CONFIG_DM_DEVICE_REMOVE is not set +# CONFIG_GPIO is not set +# CONFIG_I2C is not set +# CONFIG_INPUT is not set +# CONFIG_MMC is not set +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=3000 +# CONFIG_SPI_FLASH_SMART_HWCAPS is not set +# CONFIG_SPI_FLASH_UNLOCK_ALL is not set +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +# CONFIG_POWER is not set +CONFIG_ARM_DCC=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_ZYNQMP_GQSPI=y +# CONFIG_LMB is not set -- 2.17.1
[PATCH 0/2] Add quad & octal spi flash mini u-boot configuration files
Add new configuration files for quad and octal spi flash mini u-boot. With these configs's mini u-boot will run from on chip memory(OCM) and uses DCC terminal for console output. Ashok Reddy Soma (2): arm64: versal: Add qspi flash mini u-boot configuration arm64: versal: Add octal spi flash mini u-boot configuration MAINTAINERS | 1 + configs/xilinx_versal_mini_ospi_defconfig | 71 ++ configs/xilinx_versal_mini_qspi_defconfig | 74 +++ 3 files changed, 146 insertions(+) create mode 100644 configs/xilinx_versal_mini_ospi_defconfig create mode 100644 configs/xilinx_versal_mini_qspi_defconfig -- 2.17.1
[PATCH 0/3] Read mmc "power-domains" id from DT and use for firmware calls
In this patch series - Existing node_id is u8, change it to u32 to accommodate Versal node_id - Read "power-domains" id from DT and use in all firmware calls in place of node_id. - Remove static values of node_id which are set based on "device_id" - Remove "xlnx,device_id" from all dts files Ashok Reddy Soma (3): mmc: zynq_sdhci: Change node_id prototype to u32 mmc: zynq_sdhci: Read power-domains id from DT and use arm64: dts: Remove unused property device_id arch/arm/dts/versal-mini-emmc0.dts | 1 - arch/arm/dts/versal-mini-emmc1.dts | 1 - arch/arm/dts/zynqmp-mini-emmc0.dts | 1 - arch/arm/dts/zynqmp-mini-emmc1.dts | 1 - arch/arm/dts/zynqmp.dtsi | 2 -- drivers/mmc/zynq_sdhci.c | 53 +++--- 6 files changed, 27 insertions(+), 32 deletions(-) -- 2.17.1
[PATCH 1/3] mmc: zynq_sdhci: Change node_id prototype to u32
In Versal platform power domain node_id is bigger than u8, hence
change prototype to u32 to accommodate. Change u8 to u32 in the function
prototypes that use node_id and remove casting to u32 from
xilinx_pm_request() call parameters.
Signed-off-by: Ashok Reddy Soma
---
drivers/mmc/zynq_sdhci.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index 8f4071c8c2..3a4194452c 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -111,7 +111,7 @@ static const u8 mode2timing[] = {
[MMC_HS_200] = MMC_TIMING_MMC_HS200,
};
-static inline int arasan_zynqmp_set_in_tapdelay(u8 node_id, u32 itap_delay)
+static inline int arasan_zynqmp_set_in_tapdelay(u32 node_id, u32 itap_delay)
{
int ret;
@@ -155,7 +155,7 @@ static inline int arasan_zynqmp_set_in_tapdelay(u8 node_id,
u32 itap_delay)
if (ret)
return ret;
} else {
- return xilinx_pm_request(PM_IOCTL, (u32)node_id,
+ return xilinx_pm_request(PM_IOCTL, node_id,
IOCTL_SET_SD_TAPDELAY,
PM_TAPDELAY_INPUT, itap_delay, NULL);
}
@@ -163,7 +163,7 @@ static inline int arasan_zynqmp_set_in_tapdelay(u8 node_id,
u32 itap_delay)
return 0;
}
-static inline int arasan_zynqmp_set_out_tapdelay(u8 node_id, u32 otap_delay)
+static inline int arasan_zynqmp_set_out_tapdelay(u32 node_id, u32 otap_delay)
{
if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
if (node_id == NODE_SD_0)
@@ -174,13 +174,13 @@ static inline int arasan_zynqmp_set_out_tapdelay(u8
node_id, u32 otap_delay)
return zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK,
(otap_delay << 16));
} else {
- return xilinx_pm_request(PM_IOCTL, (u32)node_id,
+ return xilinx_pm_request(PM_IOCTL, node_id,
IOCTL_SET_SD_TAPDELAY,
PM_TAPDELAY_OUTPUT, otap_delay, NULL);
}
}
-static inline int zynqmp_dll_reset(u8 node_id, u32 type)
+static inline int zynqmp_dll_reset(u32 node_id, u32 type)
{
if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
if (node_id == NODE_SD_0)
@@ -192,12 +192,12 @@ static inline int zynqmp_dll_reset(u8 node_id, u32 type)
type == PM_DLL_RESET_ASSERT ?
SD1_DLL_RST : 0);
} else {
- return xilinx_pm_request(PM_IOCTL, (u32)node_id,
+ return xilinx_pm_request(PM_IOCTL, node_id,
IOCTL_SD_DLL_RESET, type, 0, NULL);
}
}
-static int arasan_zynqmp_dll_reset(struct sdhci_host *host, u8 node_id)
+static int arasan_zynqmp_dll_reset(struct sdhci_host *host, u32 node_id)
{
struct mmc *mmc = (struct mmc *)host->mmc;
struct udevice *dev = mmc->dev;
--
2.17.1
[PATCH 2/3] mmc: zynq_sdhci: Read power-domains id from DT and use
Firmware calls need node_id which is basically "power-domains" id.
At present static values are used based on the "device_id" property of
dt.
Instead of this, read "power-domains" id from dt and use it. Add a
element called node_id in priv structure and read it from dt. Replace
static node_id with this priv->node_id across the driver.
Since "device_id" is not used anywhere else simply remove it.
Signed-off-by: Ashok Reddy Soma
---
drivers/mmc/zynq_sdhci.c | 39 ---
1 file changed, 20 insertions(+), 19 deletions(-)
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index 3a4194452c..7dcf6ad842 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -61,7 +61,7 @@ struct arasan_sdhci_plat {
struct arasan_sdhci_priv {
struct sdhci_host *host;
struct arasan_sdhci_clk_data clk_data;
- u8 deviceid;
+ u32 node_id;
u8 bank;
u8 no_1p8;
struct reset_ctl_bulk resets;
@@ -250,7 +250,6 @@ static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8
opcode)
struct sdhci_host *host;
struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
- u8 node_id = priv->deviceid ? NODE_SD_1 : NODE_SD_0;
dev_dbg(mmc->dev, "%s\n", __func__);
@@ -262,7 +261,7 @@ static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8
opcode)
mdelay(1);
- arasan_zynqmp_dll_reset(host, node_id);
+ arasan_zynqmp_dll_reset(host, priv->node_id);
sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
@@ -308,7 +307,7 @@ static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8
opcode)
}
udelay(1);
- arasan_zynqmp_dll_reset(host, node_id);
+ arasan_zynqmp_dll_reset(host, priv->node_id);
/* Enable only interrupts served by the SD controller */
sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
@@ -334,7 +333,6 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct
sdhci_host *host,
struct mmc *mmc = (struct mmc *)host->mmc;
struct udevice *dev = mmc->dev;
struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
- u8 node_id = priv->deviceid ? NODE_SD_1 : NODE_SD_0;
u8 tap_delay, tap_max = 0;
int timing = mode2timing[mmc->selected_mode];
int ret;
@@ -374,14 +372,14 @@ static int sdhci_zynqmp_sdcardclk_set_phase(struct
sdhci_host *host,
tap_delay &= SDHCI_ARASAN_OTAPDLY_SEL_MASK;
/* Set the Clock Phase */
- ret = arasan_zynqmp_set_out_tapdelay(node_id, tap_delay);
+ ret = arasan_zynqmp_set_out_tapdelay(priv->node_id, tap_delay);
if (ret) {
dev_err(dev, "Error setting output Tap Delay\n");
return ret;
}
/* Release DLL Reset */
- ret = zynqmp_dll_reset(node_id, PM_DLL_RESET_RELEASE);
+ ret = zynqmp_dll_reset(priv->node_id, PM_DLL_RESET_RELEASE);
if (ret) {
dev_err(dev, "dll_reset release failed with err: %d\n", ret);
return ret;
@@ -405,7 +403,6 @@ static int sdhci_zynqmp_sampleclk_set_phase(struct
sdhci_host *host,
struct mmc *mmc = (struct mmc *)host->mmc;
struct udevice *dev = mmc->dev;
struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
- u8 node_id = priv->deviceid ? NODE_SD_1 : NODE_SD_0;
u8 tap_delay, tap_max = 0;
int timing = mode2timing[mmc->selected_mode];
int ret;
@@ -419,7 +416,7 @@ static int sdhci_zynqmp_sampleclk_set_phase(struct
sdhci_host *host,
return 0;
/* Assert DLL Reset */
- ret = zynqmp_dll_reset(node_id, PM_DLL_RESET_ASSERT);
+ ret = zynqmp_dll_reset(priv->node_id, PM_DLL_RESET_ASSERT);
if (ret) {
dev_err(dev, "dll_reset assert failed with err: %d\n", ret);
return ret;
@@ -451,7 +448,7 @@ static int sdhci_zynqmp_sampleclk_set_phase(struct
sdhci_host *host,
/* Limit input tap_delay value to 8 bits */
tap_delay &= SDHCI_ARASAN_ITAPDLY_SEL_MASK;
- ret = arasan_zynqmp_set_in_tapdelay(node_id, tap_delay);
+ ret = arasan_zynqmp_set_in_tapdelay(priv->node_id, tap_delay);
if (ret) {
dev_err(dev, "Error setting Input Tap Delay\n");
return ret;
@@ -717,14 +714,14 @@ static int sdhci_zynqmp_set_dynamic_config(struct
arasan_sdhci_priv *priv,
struct udevice *dev)
{
int ret;
- u32 node_id = priv->deviceid ? NODE_SD_1 : NODE_SD_0;
struct clk clk;
unsigned long clock, mhz;
- ret = xilinx_pm_request(PM_REQUEST_NODE, node_id,
ZYNQMP
[PATCH 3/3] arm64: dts: Remove unused property device_id
Device tree property "xlnx,device_id" is not used anymore, remove it. Signed-off-by: Ashok Reddy Soma --- arch/arm/dts/versal-mini-emmc0.dts | 1 - arch/arm/dts/versal-mini-emmc1.dts | 1 - arch/arm/dts/zynqmp-mini-emmc0.dts | 1 - arch/arm/dts/zynqmp-mini-emmc1.dts | 1 - arch/arm/dts/zynqmp.dtsi | 2 -- 5 files changed, 6 deletions(-) diff --git a/arch/arm/dts/versal-mini-emmc0.dts b/arch/arm/dts/versal-mini-emmc0.dts index 7c81a82fb9..d098c2d01b 100644 --- a/arch/arm/dts/versal-mini-emmc0.dts +++ b/arch/arm/dts/versal-mini-emmc0.dts @@ -44,7 +44,6 @@ reg = <0x0 0xf104 0x0 0x1>; clock-names = "clk_xin", "clk_ahb"; clocks = <&clk200 &clk200>; - xlnx,device_id = <0>; no-1-8-v; xlnx,mio-bank = <0>; }; diff --git a/arch/arm/dts/versal-mini-emmc1.dts b/arch/arm/dts/versal-mini-emmc1.dts index bf7569d4cc..9d4ac28359 100644 --- a/arch/arm/dts/versal-mini-emmc1.dts +++ b/arch/arm/dts/versal-mini-emmc1.dts @@ -44,7 +44,6 @@ reg = <0x0 0xf105 0x0 0x1>; clock-names = "clk_xin", "clk_ahb"; clocks = <&clk200 &clk200>; - xlnx,device_id = <1>; no-1-8-v; xlnx,mio-bank = <0>; }; diff --git a/arch/arm/dts/zynqmp-mini-emmc0.dts b/arch/arm/dts/zynqmp-mini-emmc0.dts index 8467dd8e1c..1cc4ade5e8 100644 --- a/arch/arm/dts/zynqmp-mini-emmc0.dts +++ b/arch/arm/dts/zynqmp-mini-emmc0.dts @@ -56,7 +56,6 @@ reg = <0x0 0xff16 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; clocks = <&clk_xin &clk_xin>; - xlnx,device_id = <0>; }; }; }; diff --git a/arch/arm/dts/zynqmp-mini-emmc1.dts b/arch/arm/dts/zynqmp-mini-emmc1.dts index 2afcc7751b..96b5dc2932 100644 --- a/arch/arm/dts/zynqmp-mini-emmc1.dts +++ b/arch/arm/dts/zynqmp-mini-emmc1.dts @@ -56,7 +56,6 @@ reg = <0x0 0xff17 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; clocks = <&clk_xin &clk_xin>; - xlnx,device_id = <1>; }; }; }; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index fbc6e752da..2fbd0f711b 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -720,7 +720,6 @@ interrupts = <0 48 4>; reg = <0x0 0xff16 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; - xlnx,device_id = <0>; iommus = <&smmu 0x870>; #clock-cells = <1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; @@ -736,7 +735,6 @@ interrupts = <0 49 4>; reg = <0x0 0xff17 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; - xlnx,device_id = <1>; iommus = <&smmu 0x871>; #clock-cells = <1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; -- 2.17.1
[UBOOT PATCH v2] firmware: zynqmp: Skip loading config object for Versal
SET_CONFIGURATION is not yet implemented for Versal platforms. Skip
loading config object for Versal until support is added.
Signed-off-by: Ashok Reddy Soma
---
Changes in v2:
- Call zynqmp_pmufw_node only for ZynqMP platform.
CR-1136452
branch: master-next-test
Signed-off-by: Ashok Reddy Soma
---
drivers/power/domain/zynqmp-power-domain.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/power/domain/zynqmp-power-domain.c
b/drivers/power/domain/zynqmp-power-domain.c
index 6943658be4..adbbb5fdd9 100644
--- a/drivers/power/domain/zynqmp-power-domain.c
+++ b/drivers/power/domain/zynqmp-power-domain.c
@@ -25,7 +25,10 @@ static int zynqmp_power_domain_request(struct power_domain
*power_domain)
{
dev_dbg(power_domain->dev, "Request for id: %ld\n", power_domain->id);
- return zynqmp_pmufw_node(power_domain->id);
+ if (IS_ENABLED(CONFIG_ARCH_ZYNQMP))
+ return zynqmp_pmufw_node(power_domain->id);
+
+ return 0;
}
static int zynqmp_power_domain_free(struct power_domain *power_domain)
--
2.17.1
[PATCH 0/3] cadence_qspi driver updates
In this patch series - Change driver to use plat data structure only in of_to_plat() and probe(). In probe, copy plat structure members to priv structure. Replace plat with priv across the driver. - Fix function name issue in flash reset - Add a call to read_setup in cadence_spi_read_id() before STIG read. Ashok Reddy Soma (3): spi: cadence-qspi: Correct flash reset function name spi: cadence_qspi: Call read_setup for STIG_READ spi: cadence-qspi: Use priv instead of plat across the driver drivers/spi/cadence_ospi_versal.c | 56 drivers/spi/cadence_qspi.c| 104 -- drivers/spi/cadence_qspi.h| 56 +--- drivers/spi/cadence_qspi_apb.c| 231 +++--- 4 files changed, 242 insertions(+), 205 deletions(-) -- 2.17.1
[PATCH 1/3] spi: cadence-qspi: Correct flash reset function name
In cadence_spi_probe, cadence_qspi_versal_flash_reset() is called to reset
the flash device. Looks like there is a mistake in previous series of
patches where it is defined as cadence_spi_versal_flash_reset() but
called as cadence_qspi_versal_flash_reset. Since there is a weak function
defined with the same name this issue was not caught.
Fix the issue by renaming cadence_spi_versal_flash_reset as
cadence_qspi_versal_flash_reset().
Signed-off-by: Ashok Reddy Soma
---
drivers/spi/cadence_ospi_versal.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/cadence_ospi_versal.c
b/drivers/spi/cadence_ospi_versal.c
index 52bcad053f..c756a854bc 100644
--- a/drivers/spi/cadence_ospi_versal.c
+++ b/drivers/spi/cadence_ospi_versal.c
@@ -128,7 +128,7 @@ int cadence_qspi_apb_wait_for_dma_cmplt(struct
cadence_spi_plat *plat)
}
#if defined(CONFIG_DM_GPIO)
-int cadence_spi_versal_flash_reset(struct udevice *dev)
+int cadence_qspi_versal_flash_reset(struct udevice *dev)
{
struct gpio_desc gpio;
u32 reset_gpio;
@@ -169,7 +169,7 @@ int cadence_spi_versal_flash_reset(struct udevice *dev)
return 0;
}
#else
-int cadence_spi_versal_flash_reset(struct udevice *dev)
+int cadence_qspi_versal_flash_reset(struct udevice *dev)
{
/* CRP WPROT */
writel(0, WPROT_CRP);
--
2.17.1
[PATCH 2/3] spi: cadence_qspi: Call read_setup for STIG_READ
In cadence_spi_read_id we are using STIG mode to read flash id's.
Call cadence_qspi_apb_command_read_setup() to setup cmd, addr and data
bus width properly before cadence_qspi_apb_command_read().
Signed-off-by: Ashok Reddy Soma
---
drivers/spi/cadence_qspi.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 907f5dadc4..6e50b94e14 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -59,12 +59,17 @@ static int cadence_spi_write_speed(struct udevice *bus,
uint hz)
static int cadence_spi_read_id(struct cadence_spi_plat *plat, u8 len,
u8 *idcode)
{
+ int err;
struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0x9F, 1),
SPI_MEM_OP_NO_ADDR,
SPI_MEM_OP_NO_DUMMY,
SPI_MEM_OP_DATA_IN(len, idcode, 1));
- return cadence_qspi_apb_command_read(plat, &op);
+ err = cadence_qspi_apb_command_read_setup(plat, &op);
+ if (!err)
+ err = cadence_qspi_apb_command_read(plat, &op);
+
+ return err;
}
/* Calibration sequence to determine the read data capture delay register */
--
2.17.1
[PATCH 3/3] spi: cadence-qspi: Use priv instead of plat across the driver
As per driver model we should enumerate plat structure only in
of_to_plat() and should be used only in probe(). Copy required
plat structure info into priv structure in probe() and use priv
structure across the driver. So replace plat with priv structure across
the driver.
Signed-off-by: Ashok Reddy Soma
---
drivers/spi/cadence_ospi_versal.c | 52 +++
drivers/spi/cadence_qspi.c| 101 +++--
drivers/spi/cadence_qspi.h| 56 +---
drivers/spi/cadence_qspi_apb.c| 231 +++---
4 files changed, 236 insertions(+), 204 deletions(-)
diff --git a/drivers/spi/cadence_ospi_versal.c
b/drivers/spi/cadence_ospi_versal.c
index c756a854bc..a25c50bc50 100644
--- a/drivers/spi/cadence_ospi_versal.c
+++ b/drivers/spi/cadence_ospi_versal.c
@@ -21,7 +21,7 @@
#define CMD_4BYTE_READ 0x13
#define CMD_4BYTE_FAST_READ 0x0C
-int cadence_qspi_apb_dma_read(struct cadence_spi_plat *plat,
+int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv,
const struct spi_mem_op *op)
{
u32 reg, ret, rx_rem, n_rx, bytes_to_dma, data;
@@ -34,86 +34,86 @@ int cadence_qspi_apb_dma_read(struct cadence_spi_plat *plat,
if (bytes_to_dma) {
cadence_qspi_apb_enable_linear_mode(false);
- reg = readl(plat->regbase + CQSPI_REG_CONFIG);
+ reg = readl(priv->regbase + CQSPI_REG_CONFIG);
reg |= CQSPI_REG_CONFIG_ENBL_DMA;
- writel(reg, plat->regbase + CQSPI_REG_CONFIG);
+ writel(reg, priv->regbase + CQSPI_REG_CONFIG);
- writel(bytes_to_dma, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
+ writel(bytes_to_dma, priv->regbase + CQSPI_REG_INDIRECTRDBYTES);
writel(CQSPI_DFLT_INDIR_TRIG_ADDR_RANGE,
- plat->regbase + CQSPI_REG_INDIR_TRIG_ADDR_RANGE);
+ priv->regbase + CQSPI_REG_INDIR_TRIG_ADDR_RANGE);
writel(CQSPI_DFLT_DMA_PERIPH_CFG,
- plat->regbase + CQSPI_REG_DMA_PERIPH_CFG);
- writel((unsigned long)rxbuf, plat->regbase +
+ priv->regbase + CQSPI_REG_DMA_PERIPH_CFG);
+ writel((unsigned long)rxbuf, priv->regbase +
CQSPI_DMA_DST_ADDR_REG);
- writel(plat->trigger_address, plat->regbase +
+ writel(priv->trigger_address, priv->regbase +
CQSPI_DMA_SRC_RD_ADDR_REG);
- writel(bytes_to_dma, plat->regbase +
+ writel(bytes_to_dma, priv->regbase +
CQSPI_DMA_DST_SIZE_REG);
flush_dcache_range((unsigned long)rxbuf,
(unsigned long)rxbuf + bytes_to_dma);
writel(CQSPI_DFLT_DST_CTRL_REG_VAL,
- plat->regbase + CQSPI_DMA_DST_CTRL_REG);
+ priv->regbase + CQSPI_DMA_DST_CTRL_REG);
/* Start the indirect read transfer */
- writel(CQSPI_REG_INDIRECTRD_START, plat->regbase +
+ writel(CQSPI_REG_INDIRECTRD_START, priv->regbase +
CQSPI_REG_INDIRECTRD);
/* Wait for dma to complete transfer */
- ret = cadence_qspi_apb_wait_for_dma_cmplt(plat);
+ ret = cadence_qspi_apb_wait_for_dma_cmplt(priv);
if (ret)
return ret;
/* Clear indirect completion status */
- writel(CQSPI_REG_INDIRECTRD_DONE, plat->regbase +
+ writel(CQSPI_REG_INDIRECTRD_DONE, priv->regbase +
CQSPI_REG_INDIRECTRD);
rxbuf += bytes_to_dma;
}
if (rx_rem) {
- reg = readl(plat->regbase + CQSPI_REG_CONFIG);
+ reg = readl(priv->regbase + CQSPI_REG_CONFIG);
reg &= ~CQSPI_REG_CONFIG_ENBL_DMA;
- writel(reg, plat->regbase + CQSPI_REG_CONFIG);
+ writel(reg, priv->regbase + CQSPI_REG_CONFIG);
- reg = readl(plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
+ reg = readl(priv->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
reg += bytes_to_dma;
- writel(reg, plat->regbase + CQSPI_REG_CMDADDRESS);
+ writel(reg, priv->regbase + CQSPI_REG_CMDADDRESS);
- addr_bytes = readl(plat->regbase + CQSPI_REG_SIZE) &
+ addr_bytes = readl(priv->regbase + CQSPI_REG_SIZE) &
CQSPI_REG_SIZE_ADDRESS_MASK;
opcode = CMD_4BYTE_FAST_READ;
dummy_cycles = 8;
writel((dummy_cycles << CQSPI_REG_RD_INSTR_DUMMY_LSB) | opcode,
- plat->regbase + CQSPI_REG_RD_INSTR);
+ priv->regbase + CQSPI_REG_RD_INST
[PATCH] firmware: zynqmp: Skip loading config object for Versal
SET_CONFIGURATION is not yet implemented for Versal platforms. Skip
loading config object for Versal until support is added and load it only
for ZYNQMP platforms.
Signed-off-by: Ashok Reddy Soma
---
drivers/power/domain/zynqmp-power-domain.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/power/domain/zynqmp-power-domain.c
b/drivers/power/domain/zynqmp-power-domain.c
index 6943658be4..adbbb5fdd9 100644
--- a/drivers/power/domain/zynqmp-power-domain.c
+++ b/drivers/power/domain/zynqmp-power-domain.c
@@ -25,7 +25,10 @@ static int zynqmp_power_domain_request(struct power_domain
*power_domain)
{
dev_dbg(power_domain->dev, "Request for id: %ld\n", power_domain->id);
- return zynqmp_pmufw_node(power_domain->id);
+ if (IS_ENABLED(CONFIG_ARCH_ZYNQMP))
+ return zynqmp_pmufw_node(power_domain->id);
+
+ return 0;
}
static int zynqmp_power_domain_free(struct power_domain *power_domain)
--
2.17.1
[PATCH 0/6] zynqmp_gqspi driver updates
In this patch series - Add tapdelays for Versal - Add support for IO mode - Fix issue of reading more than 32bits length in DMA - Minor code alignment - Enable zynqmp_gqspi driver for Versal platforms Ashok Reddy Soma (5): spi: zynqmp_gqspi: Add tap delays for Versal spi: zynqmp_gqspi: Add support for IO mode spi: zynqmp_gqspi: Fix issue of reading more than 32bits length spi: zynqmp_qspi: Code alignment arm64: versal: Enable zynqmp_gqspi driver Michal Simek (1): arm64: versal: Define zynqmp_mmio_write() for versal arch/arm/mach-versal/include/mach/sys_proto.h | 8 + configs/xilinx_versal_virt_defconfig | 1 + drivers/spi/zynqmp_gqspi.c| 221 +- 3 files changed, 168 insertions(+), 62 deletions(-) -- 2.17.1
[PATCH 1/6] spi: zynqmp_gqspi: Add tap delays for Versal
Add tap delays for Versal platform and re-align the tapdelays code.
Signed-off-by: Ashok Reddy Soma
---
drivers/spi/zynqmp_gqspi.c | 60 --
1 file changed, 38 insertions(+), 22 deletions(-)
diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index c772bae3cc..958432c08d 100644
--- a/drivers/spi/zynqmp_gqspi.c
+++ b/drivers/spi/zynqmp_gqspi.c
@@ -22,6 +22,7 @@
#include
#include
#include
+#include
#define GQSPI_GFIFO_STRT_MODE_MASK BIT(29)
#define GQSPI_CONFIG_MODE_EN_MASK (3 << 30)
@@ -102,8 +103,10 @@
#define TAP_DLY_BYPASS_LQSPI_RX_VALUE 0x1
#define TAP_DLY_BYPASS_LQSPI_RX_SHIFT 2
#define GQSPI_DATA_DLY_ADJ_OFST0x01F8
-#define IOU_TAPDLY_BYPASS_OFST 0xFF180390
+#define IOU_TAPDLY_BYPASS_OFST !IS_ENABLED(CONFIG_ARCH_VERSAL) ? \
+ 0xFF180390 : 0xF103003C
#define GQSPI_LPBK_DLY_ADJ_LPBK_MASK 0x0020
+#define GQSPI_FREQ_37_5MHZ 3750
#define GQSPI_FREQ_40MHZ 4000
#define GQSPI_FREQ_100MHZ 1
#define GQSPI_FREQ_150MHZ 15000
@@ -297,28 +300,41 @@ void zynqmp_qspi_set_tapdelay(struct udevice *bus, u32
baudrateval)
debug("%s, req_hz:%d, clk_rate:%d, baudrateval:%d\n",
__func__, reqhz, clk_rate, baudrateval);
- if (reqhz < GQSPI_FREQ_40MHZ) {
- zynqmp_mmio_read(IOU_TAPDLY_BYPASS_OFST, &tapdlybypass);
- tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
- TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
- } else if (reqhz <= GQSPI_FREQ_100MHZ) {
- zynqmp_mmio_read(IOU_TAPDLY_BYPASS_OFST, &tapdlybypass);
- tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
- TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
- lpbkdlyadj = readl(®s->lpbkdly);
- lpbkdlyadj |= (GQSPI_LPBK_DLY_ADJ_LPBK_MASK);
- datadlyadj = readl(®s->gqspidlyadj);
- datadlyadj |= ((GQSPI_USE_DATA_DLY << GQSPI_USE_DATA_DLY_SHIFT)
- | (GQSPI_DATA_DLY_ADJ_VALUE <<
- GQSPI_DATA_DLY_ADJ_SHIFT));
- } else if (reqhz <= GQSPI_FREQ_150MHZ) {
- lpbkdlyadj = readl(®s->lpbkdly);
- lpbkdlyadj |= ((GQSPI_LPBK_DLY_ADJ_LPBK_MASK) |
- GQSPI_LPBK_DLY_ADJ_DLY_0);
+ if (!IS_ENABLED(CONFIG_ARCH_VERSAL)) {
+ if (reqhz <= GQSPI_FREQ_40MHZ) {
+ tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
+ TAP_DLY_BYPASS_LQSPI_RX_SHIFT;
+ } else if (reqhz <= GQSPI_FREQ_100MHZ) {
+ tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
+ TAP_DLY_BYPASS_LQSPI_RX_SHIFT;
+ lpbkdlyadj = GQSPI_LPBK_DLY_ADJ_LPBK_MASK;
+ datadlyadj = (GQSPI_USE_DATA_DLY <<
+ GQSPI_USE_DATA_DLY_SHIFT) |
+ (GQSPI_DATA_DLY_ADJ_VALUE <<
+ GQSPI_DATA_DLY_ADJ_SHIFT);
+ } else if (reqhz <= GQSPI_FREQ_150MHZ) {
+ lpbkdlyadj = GQSPI_LPBK_DLY_ADJ_LPBK_MASK |
+ GQSPI_LPBK_DLY_ADJ_DLY_0;
+ }
+ zynqmp_mmio_write(IOU_TAPDLY_BYPASS_OFST,
+ IOU_TAPDLY_BYPASS_MASK, tapdlybypass);
+ } else {
+ if (reqhz <= GQSPI_FREQ_37_5MHZ) {
+ tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
+ TAP_DLY_BYPASS_LQSPI_RX_SHIFT;
+ } else if (reqhz <= GQSPI_FREQ_100MHZ) {
+ tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
+ TAP_DLY_BYPASS_LQSPI_RX_SHIFT;
+ lpbkdlyadj = GQSPI_LPBK_DLY_ADJ_LPBK_MASK;
+ datadlyadj = GQSPI_USE_DATA_DLY <<
+ GQSPI_USE_DATA_DLY_SHIFT;
+ } else if (reqhz <= GQSPI_FREQ_150MHZ) {
+ lpbkdlyadj = GQSPI_LPBK_DLY_ADJ_LPBK_MASK |
+ (GQSPI_LPBK_DLY_ADJ_DLY_1 <<
+ GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT);
+ }
+ writel(tapdlybypass, IOU_TAPDLY_BYPASS_OFST);
}
-
- zynqmp_mmio_write(IOU_TAPDLY_BYPASS_OFST, IOU_TAPDLY_BYPASS_MASK,
- tapdlybypass);
writel(lpbkdlyadj, ®s->lpbkdly);
writel(datadlyadj, ®s->gqspidlyadj);
}
--
2.17.1
[PATCH 2/6] arm64: versal: Define zynqmp_mmio_write() for versal
From: Michal Simek
GQSPI driver is using it but this function is never called for Versal
because it is removed by linker. But function should be declared to avoid
this build warning:
drivers/spi/zynqmp_gqspi.c: In function 'zynqmp_qspi_set_tapdelay':
drivers/spi/zynqmp_gqspi.c:378:3: warning: implicit declaration of function
'zynqmp_mmio_write' [-Wimplicit-function-declaration]
378 | zynqmp_mmio_write(IOU_TAPDLY_BYPASS_OFST,
Signed-off-by: Michal Simek
Signed-off-by: Ashok Reddy Soma
---
arch/arm/mach-versal/include/mach/sys_proto.h | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/mach-versal/include/mach/sys_proto.h
b/arch/arm/mach-versal/include/mach/sys_proto.h
index 05934c28d6..8e5712e0c9 100644
--- a/arch/arm/mach-versal/include/mach/sys_proto.h
+++ b/arch/arm/mach-versal/include/mach/sys_proto.h
@@ -3,6 +3,8 @@
* Copyright 2016 - 2018 Xilinx, Inc.
*/
+#include
+
enum {
TCM_LOCK,
TCM_SPLIT,
@@ -10,3 +12,9 @@ enum {
void tcm_init(u8 mode);
void mem_map_fill(void);
+
+static inline int zynqmp_mmio_write(const u32 address, const u32 mask, const
u32 value)
+{
+ BUILD_BUG();
+ return -EINVAL;
+}
--
2.17.1
[PATCH 4/6] spi: zynqmp_gqspi: Fix issue of reading more than 32bits length
As the flash sizes are increasing day by day, QSPI can have devices of
size > 512MB. In qspi driver we are trying to read all the data at once
using DMA.
The DMA descriptor destination size is only 29bits long.
QSPIDMA_DST_SIZE 0xFF0F0804
BITS: 1:0 Reserved to keep word alignment
BITS: 28:2 Number of 4-byte words the DMA will transfer
BITS: 31:29 Reserved: Returns 0 when read, writes ignored
So we can only transfer data of 0x1FF0(512MB minus 4bytes) bytes.
Anything above will overflow this register and will ignore higher bits
above 29 bits.
Change the DMA functionality if the requested size is greater than or
equal to 512MB to read 256MB chunks.
Signed-off-by: Ashok Reddy Soma
---
drivers/spi/zynqmp_gqspi.c | 62 --
1 file changed, 39 insertions(+), 23 deletions(-)
diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index 78a1b48731..d5ccb48fde 100644
--- a/drivers/spi/zynqmp_gqspi.c
+++ b/drivers/spi/zynqmp_gqspi.c
@@ -22,6 +22,7 @@
#include
#include
#include
+#include
#include
#define GQSPI_GFIFO_STRT_MODE_MASK BIT(29)
@@ -666,38 +667,53 @@ static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv
*priv,
u32 addr;
u32 size;
u32 actuallen = priv->len;
+ u32 totallen = priv->len;
int ret = 0;
struct zynqmp_qspi_dma_regs *dma_regs = priv->dma_regs;
- writel((unsigned long)buf, &dma_regs->dmadst);
- writel(roundup(priv->len, GQSPI_DMA_ALIGN), &dma_regs->dmasize);
- writel(GQSPI_DMA_DST_I_STS_MASK, &dma_regs->dmaier);
- addr = (unsigned long)buf;
- size = roundup(priv->len, GQSPI_DMA_ALIGN);
- flush_dcache_range(addr, addr + size);
+ while (totallen) {
+ if (totallen >= SZ_512M)
+ priv->len = SZ_256M;
+ else
+ priv->len = totallen;
- while (priv->len) {
- zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
- zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
+ totallen -= priv->len; /* Save remaining bytes length to read */
+ actuallen = priv->len; /* Actual number of bytes reading */
- debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd);
- }
+ writel((unsigned long)buf, &dma_regs->dmadst);
+ writel(roundup(priv->len, GQSPI_DMA_ALIGN), &dma_regs->dmasize);
+ writel(GQSPI_DMA_DST_I_STS_MASK, &dma_regs->dmaier);
+ addr = (unsigned long)buf;
+ size = roundup(priv->len, GQSPI_DMA_ALIGN);
+ flush_dcache_range(addr, addr + size);
- ret = wait_for_bit_le32(&dma_regs->dmaisr, GQSPI_DMA_DST_I_STS_DONE,
- 1, GQSPI_TIMEOUT, 1);
- if (ret) {
- printf("DMA Timeout:0x%x\n", readl(&dma_regs->dmaisr));
- return -ETIMEDOUT;
- }
+ while (priv->len) {
+ zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
+ zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
+
+ debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd);
+ }
+
+ ret = wait_for_bit_le32(&dma_regs->dmaisr,
+ GQSPI_DMA_DST_I_STS_DONE, 1,
+ GQSPI_TIMEOUT, 1);
+ if (ret) {
+ printf("DMA Timeout:0x%x\n", readl(&dma_regs->dmaisr));
+ return -ETIMEDOUT;
+ }
+
+ writel(GQSPI_DMA_DST_I_STS_DONE, &dma_regs->dmaisr);
- writel(GQSPI_DMA_DST_I_STS_DONE, &dma_regs->dmaisr);
+ debug("buf:0x%lx, rxbuf:0x%lx, *buf:0x%x len: 0x%x\n",
+ (unsigned long)buf, (unsigned long)priv->rx_buf, *buf,
+ actuallen);
- debug("buf:0x%lx, rxbuf:0x%lx, *buf:0x%x len: 0x%x\n",
- (unsigned long)buf, (unsigned long)priv->rx_buf, *buf,
- actuallen);
+ if (buf != priv->rx_buf)
+ memcpy(priv->rx_buf, buf, actuallen);
- if (buf != priv->rx_buf)
- memcpy(priv->rx_buf, buf, actuallen);
+ buf = (u32 *)((u8 *)buf + actuallen);
+ priv->rx_buf = (u8 *)priv->rx_buf + actuallen;
+ }
return 0;
}
--
2.17.1
[PATCH 5/6] spi: zynqmp_qspi: Code alignment
Few lines are extented to next line though they can fit in 80 character
limit, align them to single line. No functional change.
Signed-off-by: Ashok Reddy Soma
---
drivers/spi/zynqmp_gqspi.c | 18 ++
1 file changed, 6 insertions(+), 12 deletions(-)
diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index d5ccb48fde..4e718c545c 100644
--- a/drivers/spi/zynqmp_gqspi.c
+++ b/drivers/spi/zynqmp_gqspi.c
@@ -434,8 +434,7 @@ static int zynqmp_qspi_set_mode(struct udevice *bus, uint
mode)
debug("%s\n", __func__);
/* Set the SPI Clock phase and polarities */
confr = readl(®s->confr);
- confr &= ~(GQSPI_CONFIG_CPHA_MASK |
- GQSPI_CONFIG_CPOL_MASK);
+ confr &= ~(GQSPI_CONFIG_CPHA_MASK | GQSPI_CONFIG_CPOL_MASK);
if (mode & SPI_CPHA)
confr |= GQSPI_CONFIG_CPHA_MASK;
@@ -579,8 +578,7 @@ static int zynqmp_qspi_genfifo_fill_tx(struct
zynqmp_qspi_priv *priv)
gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(priv->op->data.buswidth);
- gen_fifo_cmd |= GQSPI_GFIFO_TX |
- GQSPI_GFIFO_DATA_XFR_MASK;
+ gen_fifo_cmd |= GQSPI_GFIFO_TX | GQSPI_GFIFO_DATA_XFR_MASK;
while (priv->len) {
len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
@@ -589,11 +587,9 @@ static int zynqmp_qspi_genfifo_fill_tx(struct
zynqmp_qspi_priv *priv)
debug("GFIFO_CMD_TX:0x%x\n", gen_fifo_cmd);
if (gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK)
- ret = zynqmp_qspi_fill_tx_fifo(priv,
- 1 << len);
+ ret = zynqmp_qspi_fill_tx_fifo(priv, 1 << len);
else
- ret = zynqmp_qspi_fill_tx_fifo(priv,
- len);
+ ret = zynqmp_qspi_fill_tx_fifo(priv, len);
if (ret)
return ret;
@@ -726,8 +722,7 @@ static int zynqmp_qspi_genfifo_fill_rx(struct
zynqmp_qspi_priv *priv)
gen_fifo_cmd = zynqmp_qspi_bus_select(priv);
gen_fifo_cmd |= zynqmp_qspi_genfifo_mode(priv->op->data.buswidth);
- gen_fifo_cmd |= GQSPI_GFIFO_RX |
- GQSPI_GFIFO_DATA_XFR_MASK;
+ gen_fifo_cmd |= GQSPI_GFIFO_RX | GQSPI_GFIFO_DATA_XFR_MASK;
/*
* Check if receive buffer is aligned to 4 byte and length
@@ -742,8 +737,7 @@ static int zynqmp_qspi_genfifo_fill_rx(struct
zynqmp_qspi_priv *priv)
return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf);
}
- ALLOC_CACHE_ALIGN_BUFFER(u8, tmp, roundup(priv->len,
- GQSPI_DMA_ALIGN));
+ ALLOC_CACHE_ALIGN_BUFFER(u8, tmp, roundup(priv->len, GQSPI_DMA_ALIGN));
buf = (u32 *)tmp;
return zynqmp_qspi_start_dma(priv, gen_fifo_cmd, buf);
}
--
2.17.1
[PATCH 3/6] spi: zynqmp_gqspi: Add support for IO mode
Add support for io-mode transfers. This is necessary for UBIFS to work
properly with spi-nor devices. The driver will work in IO mode when
"has-io-mode" is passed from device tree instead of DMA.
Signed-off-by: Ashok Reddy Soma
---
drivers/spi/zynqmp_gqspi.c | 81 +++---
1 file changed, 76 insertions(+), 5 deletions(-)
diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index 958432c08d..78a1b48731 100644
--- a/drivers/spi/zynqmp_gqspi.c
+++ b/drivers/spi/zynqmp_gqspi.c
@@ -166,6 +166,7 @@ struct zynqmp_qspi_plat {
struct zynqmp_qspi_dma_regs *dma_regs;
u32 frequency;
u32 speed_hz;
+ unsigned int io_mode;
};
struct zynqmp_qspi_priv {
@@ -174,6 +175,7 @@ struct zynqmp_qspi_priv {
const void *tx_buf;
void *rx_buf;
unsigned int len;
+ unsigned int io_mode;
int bytes_to_transfer;
int bytes_to_receive;
const struct spi_mem_op *op;
@@ -190,6 +192,8 @@ static int zynqmp_qspi_of_to_plat(struct udevice *bus)
plat->dma_regs = (struct zynqmp_qspi_dma_regs *)
(dev_read_addr(bus) + GQSPI_DMA_REG_OFFSET);
+ plat->io_mode = dev_read_bool(bus, "has-io-mode");
+
return 0;
}
@@ -209,8 +213,11 @@ static void zynqmp_qspi_init_hw(struct zynqmp_qspi_priv
*priv)
config_reg = readl(®s->confr);
config_reg &= ~(GQSPI_GFIFO_STRT_MODE_MASK |
GQSPI_CONFIG_MODE_EN_MASK);
- config_reg |= GQSPI_CONFIG_DMA_MODE | GQSPI_GFIFO_WP_HOLD |
- GQSPI_DFLT_BAUD_RATE_DIV | GQSPI_GFIFO_STRT_MODE_MASK;
+ config_reg |= GQSPI_GFIFO_WP_HOLD | GQSPI_DFLT_BAUD_RATE_DIV;
+ config_reg |= GQSPI_GFIFO_STRT_MODE_MASK;
+ if (!priv->io_mode)
+ config_reg |= GQSPI_CONFIG_DMA_MODE;
+
writel(config_reg, ®s->confr);
writel(GQSPI_ENABLE_ENABLE_MASK, ®s->enbr);
@@ -388,6 +395,7 @@ static int zynqmp_qspi_probe(struct udevice *bus)
priv->regs = plat->regs;
priv->dma_regs = plat->dma_regs;
+ priv->io_mode = plat->io_mode;
ret = clk_get_by_index(bus, 0, &clk);
if (ret < 0) {
@@ -592,6 +600,66 @@ static int zynqmp_qspi_genfifo_fill_tx(struct
zynqmp_qspi_priv *priv)
return ret;
}
+static int zynqmp_qspi_start_io(struct zynqmp_qspi_priv *priv,
+ u32 gen_fifo_cmd, u32 *buf)
+{
+ u32 len;
+ u32 actuallen = priv->len;
+ u32 config_reg, ier, isr;
+ u32 timeout = GQSPI_TIMEOUT;
+ struct zynqmp_qspi_regs *regs = priv->regs;
+ u32 last_bits;
+ u32 *traverse = buf;
+
+ while (priv->len) {
+ len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
+ /* If exponent bit is set, reset immediate to be 2^len */
+ if (gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK)
+ priv->bytes_to_receive = (1 << len);
+ else
+ priv->bytes_to_receive = len;
+ zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
+ debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd);
+ /* Manual start */
+ config_reg = readl(®s->confr);
+ config_reg |= GQSPI_STRT_GEN_FIFO;
+ writel(config_reg, ®s->confr);
+ /* Enable RX interrupts for IO mode */
+ ier = readl(®s->ier);
+ ier |= GQSPI_IXR_ALL_MASK;
+ writel(ier, ®s->ier);
+ while (priv->bytes_to_receive && timeout) {
+ isr = readl(®s->isr);
+ if (isr & GQSPI_IXR_RXNEMTY_MASK) {
+ if (priv->bytes_to_receive >= 4) {
+ *traverse = readl(®s->drxr);
+ traverse++;
+ priv->bytes_to_receive -= 4;
+ } else {
+ last_bits = readl(®s->drxr);
+ memcpy(traverse, &last_bits,
+ priv->bytes_to_receive);
+ priv->bytes_to_receive = 0;
+ }
+ timeout = GQSPI_TIMEOUT;
+ } else {
+ udelay(1);
+ timeout--;
+ }
+ }
+
+ debug("buf:0x%lx, rxbuf:0x%lx, *buf:0x%x len: 0x%x\n",
+ (unsigned long)buf, (unsigned long)priv->rx_buf,
+ *buf, actuallen);
+ if (!timeout) {
+ printf("IO timeout: %d\n", readl(®s->isr));
+ r
[PATCH 6/6] arm64: versal: Enable zynqmp_gqspi driver
Versal supports gqspi ip, so enable zynqmp_gqspi driver for Versal platforms. Signed-off-by: Ashok Reddy Soma --- configs/xilinx_versal_virt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index 6e61abd0c6..239b19d316 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -113,6 +113,7 @@ CONFIG_DM_SPI=y CONFIG_CADENCE_QSPI=y CONFIG_CADENCE_OSPI_VERSAL=y CONFIG_ZYNQ_SPI=y +CONFIG_ZYNQMP_GQSPI=y CONFIG_USB=y CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y -- 2.17.1
[PATCH] usb: Add delay for control messages to reach usb stick
We are seeing timing issues with transcend usb sticks. These devices seems to require more time than regular devices for the control messages to reach device. Add 1ms delay before sending control message to fix trancend device detection issue. Signed-off-by: Ashok Reddy Soma --- common/usb.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/common/usb.c b/common/usb.c index 6fcf1e8428..3fae32b048 100644 --- a/common/usb.c +++ b/common/usb.c @@ -241,6 +241,12 @@ int usb_control_msg(struct usb_device *dev, unsigned int pipe, request, requesttype, value, index, size); dev->status = USB_ST_NOT_PROC; /*not yet processed */ + /* Timing issues are observed with transcend usb sticks such as +* “Transcend Jetflash 350 USB2.0". Add 1ms delay for the usb +* device to get detected. +*/ + mdelay(1); + err = submit_control_msg(dev, pipe, data, size, setup_packet); if (err < 0) return err; -- 2.17.1
[PATCH] cmd: sf/nand: Print and return failure when 0 length is passed
For sf commands, when '0' length is passed for erase, update, write or
read, we might see undesired results. Ideally '0' length means nothing to
do.
So print 'size is 0' and return cmd failure when length '0' is passed to sf
commands. Samething applies for nand commands also.
Example:
ZynqMP> sf erase 0 0
'size is 0'
ZynqMP> sf write 1 0 0
'size is 0'
ZynqMP> sf read 1 0 0
'size is 0'
ZynqMP> sf update 1000 1 0
'size is 0'
ZynqMP>
Signed-off-by: Ashok Reddy Soma
---
cmd/legacy-mtd-utils.c | 5 +
cmd/sf.c | 5 +
2 files changed, 10 insertions(+)
diff --git a/cmd/legacy-mtd-utils.c b/cmd/legacy-mtd-utils.c
index ac7139f84d..7b49bfd858 100644
--- a/cmd/legacy-mtd-utils.c
+++ b/cmd/legacy-mtd-utils.c
@@ -88,6 +88,11 @@ int mtd_arg_off_size(int argc, char *const argv[], int *idx,
loff_t *off,
return -1;
}
+ if (*size == 0) {
+ printf("'size is 0'\n");
+ return -1;
+ }
+
print:
printf("device %d ", *idx);
if (*size == chipsize)
diff --git a/cmd/sf.c b/cmd/sf.c
index 11b9c25896..46b5475fe8 100644
--- a/cmd/sf.c
+++ b/cmd/sf.c
@@ -353,6 +353,11 @@ static int do_spi_flash_erase(int argc, char *const argv[])
if (ret != 1)
return CMD_RET_USAGE;
+ if (size == 0) {
+ printf("'size is 0'\n");
+ return CMD_RET_FAILURE;
+ }
+
/* Consistency checking */
if (offset + size > flash->size) {
printf("ERROR: attempting %s past flash size (%#x)\n",
--
2.17.1
[PATCH v2] cmd: sf/nand: Print and return failure when 0 length is passed
For sf commands, when '0' length is passed for erase, update, write or
read, there might be undesired results. Ideally '0' length means nothing to
do.
So print 'ERROR: Invalid size 0' and return cmd failure when length '0' is
passed to sf commands. Same thing applies for nand commands also.
Example:
ZynqMP> sf erase 0 0
ERROR: Invalid size 0
ZynqMP> sf write 1 0 0
ERROR: Invalid size 0
ZynqMP> sf read 1 0 0
ERROR: Invalid size 0
ZynqMP> sf update 1000 10000 0
ERROR: Invalid size 0
ZynqMP>
Signed-off-by: Ashok Reddy Soma
---
Changes in v2:
- Changed print from 'size is 0' to Invalid size 0 without quites.
- Modified description to be imperative
- Fixed typo in description from "samething" to "same thing"
cmd/legacy-mtd-utils.c | 5 +
cmd/sf.c | 5 +
2 files changed, 10 insertions(+)
diff --git a/cmd/legacy-mtd-utils.c b/cmd/legacy-mtd-utils.c
index ac7139f84d..61987918a4 100644
--- a/cmd/legacy-mtd-utils.c
+++ b/cmd/legacy-mtd-utils.c
@@ -88,6 +88,11 @@ int mtd_arg_off_size(int argc, char *const argv[], int *idx,
loff_t *off,
return -1;
}
+ if (*size == 0) {
+ printf("ERROR: Invalid size 0\n");
+ return -1;
+ }
+
print:
printf("device %d ", *idx);
if (*size == chipsize)
diff --git a/cmd/sf.c b/cmd/sf.c
index 11b9c25896..a6aadc2b00 100644
--- a/cmd/sf.c
+++ b/cmd/sf.c
@@ -353,6 +353,11 @@ static int do_spi_flash_erase(int argc, char *const argv[])
if (ret != 1)
return CMD_RET_USAGE;
+ if (size == 0) {
+ printf("ERROR: Invalid size 0\n");
+ return CMD_RET_FAILURE;
+ }
+
/* Consistency checking */
if (offset + size > flash->size) {
printf("ERROR: attempting %s past flash size (%#x)\n",
--
2.17.1
[PATCH 0/2] Enable ADIN phy for ZynqMP and Versal platforms
In this patch series enable support for Analog Devices ethernet phy for ZynqMP and Versal platforms. Ashok Reddy Soma (2): arm64: zynqmp: Enable ADIN ethernet phy arm64: versal: Enable ADIN ethernet phy configs/xilinx_versal_virt_defconfig | 3 ++- configs/xilinx_zynqmp_virt_defconfig | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) -- 2.17.1
[PATCH 1/2] arm64: zynqmp: Enable ADIN ethernet phy
Some of the Kria SOM and ZynqMP boards are using Analog Devices ethernet phy. So, enable CONFIG_PHY_ADIN for all ZynqMP platforms. Signed-off-by: Ashok Reddy Soma --- configs/xilinx_zynqmp_virt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index fb6bf62265..53b6287b71 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -170,6 +170,7 @@ CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_ADIN=y CONFIG_PHY_MARVELL=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y -- 2.17.1
[PATCH 2/2] arm64: versal: Enable ADIN ethernet phy
Versal VEK280 board has Analog Devices ethernet phy. So, enable CONFIG_PHY_ADIN config in Versal defconfig. Signed-off-by: Ashok Reddy Soma --- configs/xilinx_versal_virt_defconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index 018ec72765..c5d65fae95 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -7,6 +7,7 @@ CONFIG_TEXT_BASE=0x800 CONFIG_SYS_MALLOC_F_LEN=0x10 CONFIG_DEFAULT_DEVICE_TREE="xilinx-versal-virt" CONFIG_SYS_PROMPT="Versal> " +CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_ENV_OFFSET_REDUND=0x7F0 CONFIG_CMD_FRU=y @@ -97,6 +98,7 @@ CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_ADIN=y CONFIG_PHY_MARVELL=y CONFIG_PHY_NATSEMI=y CONFIG_PHY_REALTEK=y @@ -137,4 +139,3 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x03FD CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_THOR=y -CONFIG_OF_LIBFDT_OVERLAY=y -- 2.17.1
[PATCH 0/2] Update mailmap ids
In this patch series - Sort mailmap ids according to dictionary order - Update all Xilinx users mail ids to AMD Algapally Santosh Sagar (2): .mailmap: Sort the mailmap ids in dictionary order .mailmap: Map all Xilinx users mail ids to AMD .mailmap | 80 1 file changed, 64 insertions(+), 16 deletions(-) -- 2.17.1
[PATCH 1/2] .mailmap: Sort the mailmap ids in dictionary order
From: Algapally Santosh Sagar The mailmap ids are not arranged in the dictionary order. So, sort the mailmap ids in the dictionary order. Signed-off-by: Algapally Santosh Sagar Signed-off-by: Ashok Reddy Soma --- .mailmap | 28 ++-- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/.mailmap b/.mailmap index 4b3532ea9c..80076f7206 100644 --- a/.mailmap +++ b/.mailmap @@ -30,26 +30,28 @@ Eugen Hristev Fabio Estevam Heinrich Schuchardt Heinrich Schuchardt xypron.g...@gmx.de +Igor Opaniuk +Igor Opaniuk Jagan Teki <402ja...@gmail.com> Jagan Teki Jagan Teki Jagan Teki Jagan Teki Jernej Skrabec -Igor Opaniuk -Igor Opaniuk +Lukasz Majewski Marek Beh??n Marek Beh??n Marek Behun Marek Vasut Marek Vasut Marek Vasut Markus Klotzbuecher -Masahiro Yamada Masahiro Yamada +Masahiro Yamada Michal Simek -Michal Simek Michal Simek +Michal Simek Michal Simek +Mirza Neil Armstrong Nicolas Saenz Julienne Patrice Chotard @@ -57,8 +59,8 @@ Patrick Delaunay Paul Burton Prabhakar Kushwaha Rajeshwari Shinde -Ricardo Ribalda Ricardo Ribalda +Ricardo Ribalda Ruchika Gupta Sandeep Paulraj Shaohui Xie @@ -66,17 +68,15 @@ Stefan Roese Stefano Babic Tom Rini TsiChung Liew -Wolfgang Denk -Wolfgang Denk -Wolfgang Denk -Wolfgang Denk -Wolfgang Denk Wolfgang Denk Wolfgang Denk -Wolfgang Denk +Wolfgang Denk Wolfgang Denk -York Sun +Wolfgang Denk +Wolfgang Denk +Wolfgang Denk +Wolfgang Denk +Wolfgang Denk York Sun +York Sun ??ukasz Majewski -Lukasz Majewski -Mirza -- 2.17.1
[PATCH 2/2] .mailmap: Map all Xilinx users mail ids to AMD
From: Algapally Santosh Sagar The mail ids of all the current Xilinx users are to be mapped to AMD following the merger with AMD. The mailmap file is updated accordingly. The ids of Marek Behún and Michal Simek are taken as reference. Signed-off-by: Algapally Santosh Sagar Signed-off-by: Ashok Reddy Soma --- .mailmap | 54 +++--- 1 file changed, 51 insertions(+), 3 deletions(-) diff --git a/.mailmap b/.mailmap index 80076f7206..46a8619d78 100644 --- a/.mailmap +++ b/.mailmap @@ -17,27 +17,46 @@ Alexander Graf Allen Martin +Amanda Baze +Amit Kumar Mahapatra Andreas Bießmann Andreas Bießmann Aneesh V Anup Patel +Anurag Kumar Vulisha +Appana Durga Kedareswara rao +Ashok Reddy Soma Atish Patra +Bharat Kumar Gogada +Bharat Kumar Gogada +Bhargava Sreekantappa Gayathri Bin Meng Boris Brezillon Boris Brezillon +Christian Kohn Dirk Behme +Durga Challa Eugen Hristev Fabio Estevam +Harini Katakam +Harsha Heinrich Schuchardt Heinrich Schuchardt xypron.g...@gmx.de +Ibai Erkiaga Igor Opaniuk Igor Opaniuk +Izhar Ameer Shaikh Jagan Teki <402ja...@gmail.com> Jagan Teki Jagan Teki Jagan Teki Jagan Teki +Jay Buddhabhatti Jernej Skrabec +John Linn +Jyotheeswar Reddy Mutthareddyvari +Kalyani Akula +Love Kumar Lukasz Majewski Marek Behún Marek Behún Marek Behun @@ -47,27 +66,56 @@ Marek Vasut Markus Klotzbuecher Masahiro Yamada Masahiro Yamada +Michal Simek Michal Simek -Michal Simek -Michal Simek -Michal Simek +Michal Simek +Michal Simek Mirza +Mounika Grace Akula +Mubin Usman Sayyed +Nathalie Chan King Choy +Nathalie Chan King Choy +Nava kishore Manne +Neal Frager Neil Armstrong Nicolas Saenz Julienne Patrice Chotard Patrick Delaunay Paul Burton +Piyush Mehta Prabhakar Kushwaha +Punnaiah Choudary Kalluri +Radhey Shyam Pandey Rajeshwari Shinde +Raju Kumar Pothuraju +Ravi Patel Ricardo Ribalda Ricardo Ribalda +Rohit Visavalia Ruchika Gupta +Saeed Nowshadi +Sai Krishna Potthuri +Sai Pavan Boddu +Sandeep Gundlupet Raju Sandeep Paulraj +Sandeep Reddy Ghanapuram Shaohui Xie +Shravya Kumbham +Shubhrajyoti Datta +Siva Durga Prasad Paladugu +Siva Durga Prasad Paladugu +Srinivas Goud +Srinivas Neeli Stefan Roese Stefano Babic +Stefano Stabellini Tom Rini +Tomas Thoresen TsiChung Liew +Varalaxmi Bingi +Venkatesh Yadav Abbarapu +Vikhyat Goyal Wolfgang Denk Wolfgang Denk Wolfgang Denk -- 2.17.1
[PATCH v2 0/2] Update mailmap ids
In this patch series - Sort mailmap ids according to dictionary order - Update all Xilinx users mail ids to AMD Changes in v2: - Updated the missing mailids - Removed the space after mail id - Added closing brace for Vikhyat Goyal email id Algapally Santosh Sagar (2): .mailmap: Sort the mailmap ids in dictionary order .mailmap: Map all Xilinx users mail ids to AMD .mailmap | 81 +--- 1 file changed, 65 insertions(+), 16 deletions(-) -- 2.17.1
[PATCH v2 1/2] .mailmap: Sort the mailmap ids in dictionary order
From: Algapally Santosh Sagar The mailmap ids are not arranged in the dictionary order. So, sort the mailmap ids in the dictionary order. Signed-off-by: Algapally Santosh Sagar Signed-off-by: Ashok Reddy Soma --- (no changes since v1) .mailmap | 28 ++-- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/.mailmap b/.mailmap index 4b3532ea9c..80076f7206 100644 --- a/.mailmap +++ b/.mailmap @@ -30,26 +30,28 @@ Eugen Hristev Fabio Estevam Heinrich Schuchardt Heinrich Schuchardt xypron.g...@gmx.de +Igor Opaniuk +Igor Opaniuk Jagan Teki <402ja...@gmail.com> Jagan Teki Jagan Teki Jagan Teki Jagan Teki Jernej Skrabec -Igor Opaniuk -Igor Opaniuk +Lukasz Majewski Marek Beh??n Marek Beh??n Marek Behun Marek Vasut Marek Vasut Marek Vasut Markus Klotzbuecher -Masahiro Yamada Masahiro Yamada +Masahiro Yamada Michal Simek -Michal Simek Michal Simek +Michal Simek Michal Simek +Mirza Neil Armstrong Nicolas Saenz Julienne Patrice Chotard @@ -57,8 +59,8 @@ Patrick Delaunay Paul Burton Prabhakar Kushwaha Rajeshwari Shinde -Ricardo Ribalda Ricardo Ribalda +Ricardo Ribalda Ruchika Gupta Sandeep Paulraj Shaohui Xie @@ -66,17 +68,15 @@ Stefan Roese Stefano Babic Tom Rini TsiChung Liew -Wolfgang Denk -Wolfgang Denk -Wolfgang Denk -Wolfgang Denk -Wolfgang Denk Wolfgang Denk Wolfgang Denk -Wolfgang Denk +Wolfgang Denk Wolfgang Denk -York Sun +Wolfgang Denk +Wolfgang Denk +Wolfgang Denk +Wolfgang Denk +Wolfgang Denk York Sun +York Sun ??ukasz Majewski -Lukasz Majewski -Mirza -- 2.17.1
[PATCH v2 2/2] .mailmap: Map all Xilinx users mail ids to AMD
From: Algapally Santosh Sagar The mail ids of all the current Xilinx users are to be mapped to AMD following the merger with AMD. The mailmap file is updated accordingly. The ids of Marek Behún and Michal Simek are taken as reference. Signed-off-by: Algapally Santosh Sagar Signed-off-by: Ashok Reddy Soma --- Changes in v2: - Updated the missing mailids - Removed the space after mail id - Added closing brace for Vikhyat Goyal email id .mailmap | 55 --- 1 file changed, 52 insertions(+), 3 deletions(-) diff --git a/.mailmap b/.mailmap index 80076f7206..312a428dc9 100644 --- a/.mailmap +++ b/.mailmap @@ -17,27 +17,47 @@ Alexander Graf Allen Martin +Amanda Baze +Amit Kumar Mahapatra Andreas Bießmann Andreas Bießmann Aneesh V Anup Patel +Anurag Kumar Vulisha +Appana Durga Kedareswara rao +Ashok Reddy Soma Atish Patra +Bharat Kumar Gogada +Bharat Kumar Gogada +Bhargava Sreekantappa Gayathri Bin Meng Boris Brezillon Boris Brezillon +Christian Kohn Dirk Behme +Durga Challa Eugen Hristev Fabio Estevam +Harini Katakam +Harsha Heinrich Schuchardt Heinrich Schuchardt xypron.g...@gmx.de +Ibai Erkiaga Igor Opaniuk Igor Opaniuk +Izhar Ameer Shaikh Jagan Teki <402ja...@gmail.com> Jagan Teki Jagan Teki Jagan Teki Jagan Teki +Jay Buddhabhatti Jernej Skrabec +John Linn +Jyotheeswar Reddy Mutthareddyvari +Jyotheeswar Reddy Mutthareddyvari +Kalyani Akula +Love Kumar Lukasz Majewski Marek Behún Marek Behún Marek Behun @@ -47,27 +67,56 @@ Marek Vasut Markus Klotzbuecher Masahiro Yamada Masahiro Yamada +Michal Simek Michal Simek -Michal Simek -Michal Simek -Michal Simek +Michal Simek +Michal Simek Mirza +Mounika Grace Akula +Mubin Usman Sayyed +Nathalie Chan King Choy +Nathalie Chan King Choy +Nava kishore Manne +Neal Frager Neil Armstrong Nicolas Saenz Julienne Patrice Chotard Patrick Delaunay Paul Burton +Piyush Mehta Prabhakar Kushwaha +Punnaiah Choudary Kalluri +Radhey Shyam Pandey Rajeshwari Shinde +Raju Kumar Pothuraju +Ravi Patel Ricardo Ribalda Ricardo Ribalda +Rohit Visavalia Ruchika Gupta +Saeed Nowshadi +Sai Krishna Potthuri +Sai Pavan Boddu +Sandeep Gundlupet Raju Sandeep Paulraj +Sandeep Reddy Ghanapuram Shaohui Xie +Shravya Kumbham +Shubhrajyoti Datta +Siva Durga Prasad Paladugu +Siva Durga Prasad Paladugu +Srinivas Goud +Srinivas Neeli Stefan Roese Stefano Babic +Stefano Stabellini Tom Rini +Tomas Thoresen TsiChung Liew +Varalaxmi Bingi +Venkatesh Yadav Abbarapu +Vikhyat Goyal +Vishal Patel Wolfgang Denk Wolfgang Denk Wolfgang Denk -- 2.17.1
[PATCH] arm64: versal-net: Detect and display bootmode
Read boodmode register using versal_net_get_bootmode() in board_late_init
and prepare corresponding distro boot command sequence based on it.
versal_net_get_bootmode() will be changed to use smc calls later, but
for now directly reads the register.
Signed-off-by: Ashok Reddy Soma
---
.../mach-versal-net/include/mach/hardware.h | 21 +++
board/xilinx/versal-net/board.c | 126 ++
2 files changed, 147 insertions(+)
diff --git a/arch/arm/mach-versal-net/include/mach/hardware.h
b/arch/arm/mach-versal-net/include/mach/hardware.h
index c5e4e22040..89b84a2efc 100644
--- a/arch/arm/mach-versal-net/include/mach/hardware.h
+++ b/arch/arm/mach-versal-net/include/mach/hardware.h
@@ -27,7 +27,13 @@ struct iou_scntrs_regs {
u32 base_frequency_id_register; /* 0x20 */
};
+struct crp_regs {
+ u32 reserved0[128];
+ u32 boot_mode_usr; /* 0x200 */
+};
+
#define VERSAL_NET_CRL_APB_BASEADDR0xEB5E
+#define VERSAL_NET_CRP_BASEADDR0xF126
#define VERSAL_NET_IOU_SCNTR_SECURE0xEC92
#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT BIT(25)
@@ -36,6 +42,7 @@ struct iou_scntrs_regs {
#define IOU_SCNTRS_CONTROL_EN 1
#define crlapb_base ((struct crlapb_regs *)VERSAL_NET_CRL_APB_BASEADDR)
+#define crp_base ((struct crp_regs *)VERSAL_NET_CRP_BASEADDR)
#define iou_scntr_secure ((struct iou_scntrs_regs
*)VERSAL_NET_IOU_SCNTR_SECURE)
#define PMC_TAP0xF11A
@@ -49,6 +56,20 @@ struct iou_scntrs_regs {
# define PLATFORM_VERSION_MASK GENMASK(31, 28)
#define PMC_TAP_USERCODE (PMC_TAP + 0x8)
+/* Bootmode setting values */
+#define BOOT_MODES_MASK0x000F
+#define QSPI_MODE_24BIT0x0001
+#define QSPI_MODE_32BIT0x0002
+#define SD_MODE0x0003 /* sd 0 */
+#define SD_MODE1 0x0005 /* sd 1 */
+#define EMMC_MODE 0x0006
+#define USB_MODE 0x0007
+#define OSPI_MODE 0x0008
+#define SD1_LSHFT_MODE 0x000E /* SD1 Level shifter */
+#define JTAG_MODE 0x
+#define BOOT_MODE_USE_ALT 0x100
+#define BOOT_MODE_ALT_SHIFT12
+
enum versal_net_platform {
VERSAL_NET_SILICON = 0,
VERSAL_NET_SPP = 1,
diff --git a/board/xilinx/versal-net/board.c b/board/xilinx/versal-net/board.c
index 6724c7290f..c83f1c0682 100644
--- a/board/xilinx/versal-net/board.c
+++ b/board/xilinx/versal-net/board.c
@@ -10,6 +10,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -165,8 +166,32 @@ int board_early_init_r(void)
return 0;
}
+static u8 versal_net_get_bootmode(void)
+{
+ u8 bootmode;
+ u32 reg = 0;
+
+ reg = readl(&crp_base->boot_mode_usr);
+
+ if (reg >> BOOT_MODE_ALT_SHIFT)
+ reg >>= BOOT_MODE_ALT_SHIFT;
+
+ bootmode = reg & BOOT_MODES_MASK;
+
+ return bootmode;
+}
+
int board_late_init(void)
{
+ u8 bootmode;
+ struct udevice *dev;
+ int bootseq = -1;
+ int bootseq_len = 0;
+ int env_targets_len = 0;
+ const char *mode;
+ char *new_targets;
+ char *env_targets;
+
if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
debug("Saved variables - Skipping\n");
return 0;
@@ -175,6 +200,107 @@ int board_late_init(void)
if (!IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG))
return 0;
+ bootmode = versal_net_get_bootmode();
+
+ puts("Bootmode: ");
+ switch (bootmode) {
+ case USB_MODE:
+ puts("USB_MODE\n");
+ mode = "usb_dfu0 usb_dfu1";
+ break;
+ case JTAG_MODE:
+ puts("JTAG_MODE\n");
+ mode = "jtag pxe dhcp";
+ break;
+ case QSPI_MODE_24BIT:
+ puts("QSPI_MODE_24\n");
+ mode = "xspi0";
+ break;
+ case QSPI_MODE_32BIT:
+ puts("QSPI_MODE_32\n");
+ mode = "xspi0";
+ break;
+ case OSPI_MODE:
+ puts("OSPI_MODE\n");
+ mode = "xspi0";
+ break;
+ case EMMC_MODE:
+ puts("EMMC_MODE\n");
+ if (uclass_get_device_by_name(UCLASS_MMC,
+ "mmc@f105", &dev) &&
+ uclass_get_device_by_name(UCLASS_MMC,
+ "sdhci@f105", &dev)) {
+ puts("Boot from EMMC but without SD1 enabled!\n");
+ return -1;
+ }
+ debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
+ mode = "mmc";
+ bo
[PATCH v3] cmd: sf/nand: Print and return failure when 0 length is passed
For sf commands, when '0' length is passed for erase, update, write or
read, there might be undesired results. Ideally '0' length means nothing to
do.
So print 'ERROR: Invalid size 0' and return cmd failure when length '0' is
passed to sf commands. Same thing applies for nand commands also.
Example:
ZynqMP> sf erase 0 0
ERROR: Invalid size 0
ZynqMP> sf write 1 0 0
ERROR: Invalid size 0
ZynqMP> sf read 1 0 0
ERROR: Invalid size 0
ZynqMP> sf update 1000 10000 0
ERROR: Invalid size 0
ZynqMP>
Signed-off-by: Ashok Reddy Soma
---
Changes in v3:
- Change printf to debug as it is too verbose
Changes in v2:
- Changed print from 'size is 0' to Invalid size 0 without quites.
- Modified description to be imperative
- Fixed typo in description from "samething" to "same thing"
cmd/legacy-mtd-utils.c | 5 +
cmd/sf.c | 5 +
2 files changed, 10 insertions(+)
diff --git a/cmd/legacy-mtd-utils.c b/cmd/legacy-mtd-utils.c
index ac7139f84d..5903a90fe5 100644
--- a/cmd/legacy-mtd-utils.c
+++ b/cmd/legacy-mtd-utils.c
@@ -88,6 +88,11 @@ int mtd_arg_off_size(int argc, char *const argv[], int *idx,
loff_t *off,
return -1;
}
+ if (*size == 0) {
+ debug("ERROR: Invalid size 0\n");
+ return -1;
+ }
+
print:
printf("device %d ", *idx);
if (*size == chipsize)
diff --git a/cmd/sf.c b/cmd/sf.c
index 11b9c25896..55bef2f769 100644
--- a/cmd/sf.c
+++ b/cmd/sf.c
@@ -353,6 +353,11 @@ static int do_spi_flash_erase(int argc, char *const argv[])
if (ret != 1)
return CMD_RET_USAGE;
+ if (size == 0) {
+ debug("ERROR: Invalid size 0\n");
+ return CMD_RET_FAILURE;
+ }
+
/* Consistency checking */
if (offset + size > flash->size) {
printf("ERROR: attempting %s past flash size (%#x)\n",
--
2.17.1
[PATCH v2] arm64: versal-net: Detect and display bootmode
Read boodmode register using versal_net_get_bootmode() in board_late_init
and prepare corresponding distro boot command sequence based on it.
versal_net_get_bootmode() will be changed to use smc calls later, but
for now directly reads the register.
Signed-off-by: Ashok Reddy Soma
---
Changes in v2:
- Remove check for mmc/sdhci node enabled or not in EMMC bootmode
- Remove check for sdhci node enabled or not in SD0 and SD1 bootmode
.../mach-versal-net/include/mach/hardware.h | 21
board/xilinx/versal-net/board.c | 114 ++
2 files changed, 135 insertions(+)
diff --git a/arch/arm/mach-versal-net/include/mach/hardware.h
b/arch/arm/mach-versal-net/include/mach/hardware.h
index c5e4e22040..89b84a2efc 100644
--- a/arch/arm/mach-versal-net/include/mach/hardware.h
+++ b/arch/arm/mach-versal-net/include/mach/hardware.h
@@ -27,7 +27,13 @@ struct iou_scntrs_regs {
u32 base_frequency_id_register; /* 0x20 */
};
+struct crp_regs {
+ u32 reserved0[128];
+ u32 boot_mode_usr; /* 0x200 */
+};
+
#define VERSAL_NET_CRL_APB_BASEADDR0xEB5E
+#define VERSAL_NET_CRP_BASEADDR0xF126
#define VERSAL_NET_IOU_SCNTR_SECURE0xEC92
#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT BIT(25)
@@ -36,6 +42,7 @@ struct iou_scntrs_regs {
#define IOU_SCNTRS_CONTROL_EN 1
#define crlapb_base ((struct crlapb_regs *)VERSAL_NET_CRL_APB_BASEADDR)
+#define crp_base ((struct crp_regs *)VERSAL_NET_CRP_BASEADDR)
#define iou_scntr_secure ((struct iou_scntrs_regs
*)VERSAL_NET_IOU_SCNTR_SECURE)
#define PMC_TAP0xF11A
@@ -49,6 +56,20 @@ struct iou_scntrs_regs {
# define PLATFORM_VERSION_MASK GENMASK(31, 28)
#define PMC_TAP_USERCODE (PMC_TAP + 0x8)
+/* Bootmode setting values */
+#define BOOT_MODES_MASK0x000F
+#define QSPI_MODE_24BIT0x0001
+#define QSPI_MODE_32BIT0x0002
+#define SD_MODE0x0003 /* sd 0 */
+#define SD_MODE1 0x0005 /* sd 1 */
+#define EMMC_MODE 0x0006
+#define USB_MODE 0x0007
+#define OSPI_MODE 0x0008
+#define SD1_LSHFT_MODE 0x000E /* SD1 Level shifter */
+#define JTAG_MODE 0x
+#define BOOT_MODE_USE_ALT 0x100
+#define BOOT_MODE_ALT_SHIFT12
+
enum versal_net_platform {
VERSAL_NET_SILICON = 0,
VERSAL_NET_SPP = 1,
diff --git a/board/xilinx/versal-net/board.c b/board/xilinx/versal-net/board.c
index 6724c7290f..6595d6f3e8 100644
--- a/board/xilinx/versal-net/board.c
+++ b/board/xilinx/versal-net/board.c
@@ -10,6 +10,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -165,8 +166,32 @@ int board_early_init_r(void)
return 0;
}
+static u8 versal_net_get_bootmode(void)
+{
+ u8 bootmode;
+ u32 reg = 0;
+
+ reg = readl(&crp_base->boot_mode_usr);
+
+ if (reg >> BOOT_MODE_ALT_SHIFT)
+ reg >>= BOOT_MODE_ALT_SHIFT;
+
+ bootmode = reg & BOOT_MODES_MASK;
+
+ return bootmode;
+}
+
int board_late_init(void)
{
+ u8 bootmode;
+ struct udevice *dev;
+ int bootseq = -1;
+ int bootseq_len = 0;
+ int env_targets_len = 0;
+ const char *mode;
+ char *new_targets;
+ char *env_targets;
+
if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
debug("Saved variables - Skipping\n");
return 0;
@@ -175,6 +200,95 @@ int board_late_init(void)
if (!IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG))
return 0;
+ bootmode = versal_net_get_bootmode();
+
+ puts("Bootmode: ");
+ switch (bootmode) {
+ case USB_MODE:
+ puts("USB_MODE\n");
+ mode = "usb_dfu0 usb_dfu1";
+ break;
+ case JTAG_MODE:
+ puts("JTAG_MODE\n");
+ mode = "jtag pxe dhcp";
+ break;
+ case QSPI_MODE_24BIT:
+ puts("QSPI_MODE_24\n");
+ mode = "xspi0";
+ break;
+ case QSPI_MODE_32BIT:
+ puts("QSPI_MODE_32\n");
+ mode = "xspi0";
+ break;
+ case OSPI_MODE:
+ puts("OSPI_MODE\n");
+ mode = "xspi0";
+ break;
+ case EMMC_MODE:
+ puts("EMMC_MODE\n");
+ mode = "mmc";
+ bootseq = dev_seq(dev);
+ break;
+ case SD_MODE:
+ puts("SD_MODE\n");
+ if (uclass_get_device_by_name(UCLASS_MMC,
+ "mmc@f104", &dev)) {
+ puts("Boot from SD0 but without SD0 enabled!\n");
+ return -1;
+
[PATCH] board: xilinx: Add missing prototypes
From: Algapally Santosh Sagar Add missing prototypes to fix the below sparse warnings 1. warning: no previous prototype for 'soc_name_decode' [-Wmissing-prototypes] 2. warning: no previous prototype for 'soc_detection' [-Wmissing-prototypes] 3. warning: no previous prototype for 'board_name_decode' [-Wmissing-prototypes] 4. warning: no previous prototype for 'board_detection' [-Wmissing-prototypes] Signed-off-by: Algapally Santosh Sagar Signed-off-by: Ashok Reddy Soma --- board/xilinx/common/board.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/board/xilinx/common/board.h b/board/xilinx/common/board.h index 69e642429b..922c9d557a 100644 --- a/board/xilinx/common/board.h +++ b/board/xilinx/common/board.h @@ -11,4 +11,11 @@ int board_late_init_xilinx(void); int xilinx_read_eeprom(void); +char *board_name_decode(void); + +bool board_detection(void); + +char *soc_name_decode(void); + +bool soc_detection(void); #endif /* BOARD_XILINX_COMMON_BOARD_H */ -- 2.17.1
[PATCH 0/3] pinctrl: zynqmp: Add tri-state configuration support
Add support for pinctrl driver to handle 'output-enable' and 'bias-high-impedance' configurations. This support has been added in Xilinx ZynqMP Platform Management Firmware recently, hence add a version check to avoid backward compatibility issues. Ashok Reddy Soma (3): firmware: zynqmp: Add support to check feature pinctrl: zynqmp: Add version check for TRISTATE configuration pinctrl: zynqmp: Add support for output-enable and bias-high-impedance drivers/firmware/firmware-zynqmp.c | 13 + drivers/pinctrl/pinctrl-zynqmp.c | 15 +++ include/zynqmp_firmware.h | 3 +++ 3 files changed, 31 insertions(+) -- 2.17.1
[PATCH 2/3] pinctrl: zynqmp: Add version check for TRISTATE configuration
Support for configuring TRISTATE parameter is added in ZYNQMP PMUFW(Xilinx
ZynqMP Platform Management Firmware) Configuration Param Set version 2.0.
If the requested configuration is TRISTATE then check the version before
requesting Xilinx firmware to set the configuration.
Signed-off-by: Ashok Reddy Soma
---
drivers/pinctrl/pinctrl-zynqmp.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-zynqmp.c b/drivers/pinctrl/pinctrl-zynqmp.c
index 02626a7561..e9857f5ed9 100644
--- a/drivers/pinctrl/pinctrl-zynqmp.c
+++ b/drivers/pinctrl/pinctrl-zynqmp.c
@@ -158,6 +158,12 @@ static int zynqmp_pm_pinctrl_set_config(const u32 pin,
const u32 param, u32 valu
{
int ret;
+ if (param == PM_PINCTRL_CONFIG_TRI_STATE) {
+ ret = zynqmp_pm_feature(PM_PINCTRL_CONFIG_PARAM_SET);
+ if (ret < PM_PINCTRL_PARAM_SET_VERSION)
+ return -EOPNOTSUPP;
+ }
+
/* Request the pin first */
ret = xilinx_pm_request(PM_PINCTRL_REQUEST, pin, 0, 0, 0, NULL);
if (ret) {
--
2.17.1
[PATCH 1/3] firmware: zynqmp: Add support to check feature
Add firmware API to check if given feature is supported.
Signed-off-by: Ashok Reddy Soma
---
drivers/firmware/firmware-zynqmp.c | 13 +
include/zynqmp_firmware.h | 3 +++
2 files changed, 16 insertions(+)
diff --git a/drivers/firmware/firmware-zynqmp.c
b/drivers/firmware/firmware-zynqmp.c
index ab4c4f1a69..43fb7fa778 100644
--- a/drivers/firmware/firmware-zynqmp.c
+++ b/drivers/firmware/firmware-zynqmp.c
@@ -195,6 +195,19 @@ int zynqmp_pm_set_sd_config(u32 node, enum
pm_sd_config_type config, u32 value)
return ret;
}
+int zynqmp_pm_feature(const u32 api_id)
+{
+ int ret;
+ u32 ret_payload[PAYLOAD_ARG_CNT];
+
+ /* Check feature check API version */
+ ret = xilinx_pm_request(PM_FEATURE_CHECK, api_id, 0, 0, 0,
+ ret_payload);
+
+ /* Return feature check version */
+ return ret_payload[1] & FIRMWARE_VERSION_MASK;
+}
+
int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id)
{
int ret;
diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h
index 18a87d2749..73198a6a6e 100644
--- a/include/zynqmp_firmware.h
+++ b/include/zynqmp_firmware.h
@@ -456,6 +456,7 @@ int zynqmp_pm_set_gem_config(u32 node, enum
pm_gem_config_type config,
int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id);
int zynqmp_mmio_read(const u32 address, u32 *value);
int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
+int zynqmp_pm_feature(const u32 api_id);
/* Type of Config Object */
#define PM_CONFIG_OBJECT_TYPE_BASE 0x1U
@@ -492,6 +493,8 @@ enum zynqmp_pm_request_ack {
/* PM API versions */
#define PM_API_VERSION_2 2
+#define PM_PINCTRL_PARAM_SET_VERSION 2
+
struct zynqmp_ipi_msg {
size_t len;
u32 *buf;
--
2.17.1
[PATCH 3/3] pinctrl: zynqmp: Add support for output-enable and bias-high-impedance
Add support to handle 'output-enable' and 'bias-high-impedance' configurations in pinctrl driver. Signed-off-by: Ashok Reddy Soma --- drivers/pinctrl/pinctrl-zynqmp.c | 9 + 1 file changed, 9 insertions(+) diff --git a/drivers/pinctrl/pinctrl-zynqmp.c b/drivers/pinctrl/pinctrl-zynqmp.c index e9857f5ed9..517035961d 100644 --- a/drivers/pinctrl/pinctrl-zynqmp.c +++ b/drivers/pinctrl/pinctrl-zynqmp.c @@ -473,6 +473,10 @@ static int zynqmp_pinconf_set(struct udevice *dev, unsigned int pin, pin); break; case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + param = PM_PINCTRL_CONFIG_TRI_STATE; + arg = PM_PINCTRL_TRI_STATE_ENABLE; + ret = zynqmp_pm_pinctrl_set_config(pin, param, arg); + break; case PIN_CONFIG_LOW_POWER_MODE: /* * This cases are mentioned in dts but configurable @@ -481,6 +485,11 @@ static int zynqmp_pinconf_set(struct udevice *dev, unsigned int pin, */ ret = 0; break; + case PIN_CONFIG_OUTPUT_ENABLE: + param = PM_PINCTRL_CONFIG_TRI_STATE; + arg = PM_PINCTRL_TRI_STATE_DISABLE; + ret = zynqmp_pm_pinctrl_set_config(pin, param, arg); + break; default: dev_warn(dev, "unsupported configuration parameter '%u'\n", param); -- 2.17.1
[PATCH] dm: core: support reading a single indexed u64 value
Add helper function to allow reading a single indexed u64 value from a
device-tree property containing multiple u64 values, that is an array of
u64's.
Signed-off-by: Ashok Reddy Soma
---
drivers/core/of_access.c | 22 ++
drivers/core/ofnode.c| 30 ++
include/dm/of_access.h | 19 +++
include/dm/ofnode.h | 12
4 files changed, 83 insertions(+)
diff --git a/drivers/core/of_access.c b/drivers/core/of_access.c
index 57f10445b1..b5c315ac3a 100644
--- a/drivers/core/of_access.c
+++ b/drivers/core/of_access.c
@@ -570,6 +570,28 @@ int of_read_u32_index(const struct device_node *np, const
char *propname,
return 0;
}
+int of_read_u64_index(const struct device_node *np, const char *propname,
+ int index, u64 *outp)
+{
+ const __be64 *val;
+
+ debug("%s: %s: ", __func__, propname);
+ if (!np)
+ return -EINVAL;
+
+ val = of_find_property_value_of_size(np, propname,
+sizeof(*outp) * (index + 1));
+ if (IS_ERR(val)) {
+ debug("(not found)\n");
+ return PTR_ERR(val);
+ }
+
+ *outp = be64_to_cpup(val + index);
+ debug("%#x (%d)\n", *outp, *outp);
+
+ return 0;
+}
+
int of_read_u64(const struct device_node *np, const char *propname, u64 *outp)
{
const __be64 *val;
diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c
index 8df16e56af..9a43343ed3 100644
--- a/drivers/core/ofnode.c
+++ b/drivers/core/ofnode.c
@@ -344,6 +344,36 @@ int ofnode_read_u32_index(ofnode node, const char
*propname, int index,
return 0;
}
+int ofnode_read_u64_index(ofnode node, const char *propname, int index,
+ u64 *outp)
+{
+ const fdt64_t *cell;
+ int len;
+
+ assert(ofnode_valid(node));
+
+ if (ofnode_is_np(node))
+ return of_read_u64_index(ofnode_to_np(node), propname, index,
+outp);
+
+ cell = fdt_getprop(ofnode_to_fdt(node), ofnode_to_offset(node),
+ propname, &len);
+ if (!cell) {
+ debug("(not found)\n");
+ return -EINVAL;
+ }
+
+ if (len < (sizeof(int) * (index + 1))) {
+ debug("(not large enough)\n");
+ return -EOVERFLOW;
+ }
+
+ *outp = fdt64_to_cpu(cell[index]);
+ debug("%#llx (%lld)\n", *outp, *outp);
+
+ return 0;
+}
+
u32 ofnode_read_u32_index_default(ofnode node, const char *propname, int index,
u32 def)
{
diff --git a/include/dm/of_access.h b/include/dm/of_access.h
index c556a18f7d..9e027c9293 100644
--- a/include/dm/of_access.h
+++ b/include/dm/of_access.h
@@ -333,6 +333,25 @@ int of_read_u32(const struct device_node *np, const char
*propname, u32 *outp);
int of_read_u32_index(const struct device_node *np, const char *propname,
int index, u32 *outp);
+/**
+ * of_read_u64_index() - Find and read a 64-bit value from a multi-value
+ * property
+ *
+ * Search for a property in a device node and read a 64-bit value from
+ * it.
+ *
+ * @np:device node from which the property value is to be read.
+ * @propname: name of the property to be searched.
+ * @index: index of the u32 in the list of values
+ * @outp: pointer to return value, modified only if return value is 0.
+ *
+ * Return:
+ * 0 on success, -EINVAL if the property does not exist, or -EOVERFLOW if the
+ * property data isn't large enough.
+ */
+int of_read_u64_index(const struct device_node *np, const char *propname,
+ int index, u64 *outp);
+
/**
* of_read_u64() - Find and read a 64-bit integer from a property
*
diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h
index 0f38b3e736..0a85db31f3 100644
--- a/include/dm/ofnode.h
+++ b/include/dm/ofnode.h
@@ -434,6 +434,18 @@ int ofnode_read_u32(ofnode node, const char *propname, u32
*outp);
int ofnode_read_u32_index(ofnode node, const char *propname, int index,
u32 *outp);
+/**
+ * ofnode_read_u64_index() - Read a 64-bit integer from a multi-value property
+ *
+ * @node: valid node reference to read property from
+ * @propname: name of the property to read from
+ * @index: index of the integer to return
+ * @outp: place to put value (if found)
+ * Return: 0 if OK, -ve on error
+ */
+int ofnode_read_u64_index(ofnode node, const char *propname, int index,
+ u64 *outp);
+
/**
* ofnode_read_s32() - Read a 32-bit integer from a property
*
--
2.17.1
[PATCH 0/7] spi-nor: Add parallel and stacked memories support
This series adds support for Xilinx qspi parallel and stacked memeories. In parallel mode, the current implementation assumes that a maximum of two flashes are connected. The QSPI controller splits the data evenly between both the flashes so, both the flashes that are connected in parallel mode should be identical. During each operation SPI-NOR sets 0th bit for CS0 & 1st bit for CS1 in nor->flags. In stacked mode the current implementation assumes that a maximum of two flashes are connected and both the flashes are of same make but can differ in sizes. So, except the sizes all other flash parameters of both the flashes are identical Spi-nor will pass on the appropriate flash select flag to low level driver, and it will select pass all the data to that particular flash. Write operation in parallel mode are performed in page size * 2 chunks as each write operation results in writing both the flashes. For doubling the address space each operation is performed at addr/2 flash offset, where addr is the address specified by the user. Similarly for read and erase operations it will read from both flashes, so size and offset are divided by 2 and send to flash. Ashok Reddy Soma (7): dm: core: support reading a single indexed u64 value mtd: spi-nor: Add parallel and stacked memories support mtd: spi-nor: Add parallel memories support for read_sr and read_fsr mtd: spi-nor: Add parallel and stacked memories support in read_bar and write_bar spi: spi-uclass: Read chipselect and restrict capabilities spi: zynqmp_gqspi: Add parallel memories support in GQSPI driver spi: zynq_qspi: Add parallel memories support in QSPI driver drivers/core/of_access.c | 22 ++ drivers/core/ofnode.c | 30 +++ drivers/mtd/spi/spi-nor-core.c | 385 - drivers/spi/spi-uclass.c | 21 +- drivers/spi/xilinx_spi.c | 4 +- drivers/spi/zynq_qspi.c| 145 +++-- drivers/spi/zynq_spi.c | 6 +- drivers/spi/zynqmp_gqspi.c | 146 +++-- include/dm/of_access.h | 19 ++ include/dm/ofnode.h| 12 + include/linux/mtd/spi-nor.h| 13 ++ include/spi.h | 29 ++- 12 files changed, 737 insertions(+), 95 deletions(-) -- 2.17.1
[PATCH 1/7] dm: core: support reading a single indexed u64 value
Add helper function to allow reading a single indexed u64 value from a
device-tree property containing multiple u64 values, that is an array of
u64's.
Signed-off-by: Ashok Reddy Soma
---
drivers/core/of_access.c | 22 ++
drivers/core/ofnode.c| 30 ++
include/dm/of_access.h | 19 +++
include/dm/ofnode.h | 12
4 files changed, 83 insertions(+)
diff --git a/drivers/core/of_access.c b/drivers/core/of_access.c
index 57f10445b1..b5c315ac3a 100644
--- a/drivers/core/of_access.c
+++ b/drivers/core/of_access.c
@@ -570,6 +570,28 @@ int of_read_u32_index(const struct device_node *np, const
char *propname,
return 0;
}
+int of_read_u64_index(const struct device_node *np, const char *propname,
+ int index, u64 *outp)
+{
+ const __be64 *val;
+
+ debug("%s: %s: ", __func__, propname);
+ if (!np)
+ return -EINVAL;
+
+ val = of_find_property_value_of_size(np, propname,
+sizeof(*outp) * (index + 1));
+ if (IS_ERR(val)) {
+ debug("(not found)\n");
+ return PTR_ERR(val);
+ }
+
+ *outp = be64_to_cpup(val + index);
+ debug("%#x (%d)\n", *outp, *outp);
+
+ return 0;
+}
+
int of_read_u64(const struct device_node *np, const char *propname, u64 *outp)
{
const __be64 *val;
diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c
index 8df16e56af..9a43343ed3 100644
--- a/drivers/core/ofnode.c
+++ b/drivers/core/ofnode.c
@@ -344,6 +344,36 @@ int ofnode_read_u32_index(ofnode node, const char
*propname, int index,
return 0;
}
+int ofnode_read_u64_index(ofnode node, const char *propname, int index,
+ u64 *outp)
+{
+ const fdt64_t *cell;
+ int len;
+
+ assert(ofnode_valid(node));
+
+ if (ofnode_is_np(node))
+ return of_read_u64_index(ofnode_to_np(node), propname, index,
+outp);
+
+ cell = fdt_getprop(ofnode_to_fdt(node), ofnode_to_offset(node),
+ propname, &len);
+ if (!cell) {
+ debug("(not found)\n");
+ return -EINVAL;
+ }
+
+ if (len < (sizeof(int) * (index + 1))) {
+ debug("(not large enough)\n");
+ return -EOVERFLOW;
+ }
+
+ *outp = fdt64_to_cpu(cell[index]);
+ debug("%#llx (%lld)\n", *outp, *outp);
+
+ return 0;
+}
+
u32 ofnode_read_u32_index_default(ofnode node, const char *propname, int index,
u32 def)
{
diff --git a/include/dm/of_access.h b/include/dm/of_access.h
index c556a18f7d..9e027c9293 100644
--- a/include/dm/of_access.h
+++ b/include/dm/of_access.h
@@ -333,6 +333,25 @@ int of_read_u32(const struct device_node *np, const char
*propname, u32 *outp);
int of_read_u32_index(const struct device_node *np, const char *propname,
int index, u32 *outp);
+/**
+ * of_read_u64_index() - Find and read a 64-bit value from a multi-value
+ * property
+ *
+ * Search for a property in a device node and read a 64-bit value from
+ * it.
+ *
+ * @np:device node from which the property value is to be read.
+ * @propname: name of the property to be searched.
+ * @index: index of the u32 in the list of values
+ * @outp: pointer to return value, modified only if return value is 0.
+ *
+ * Return:
+ * 0 on success, -EINVAL if the property does not exist, or -EOVERFLOW if the
+ * property data isn't large enough.
+ */
+int of_read_u64_index(const struct device_node *np, const char *propname,
+ int index, u64 *outp);
+
/**
* of_read_u64() - Find and read a 64-bit integer from a property
*
diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h
index 0f38b3e736..0a85db31f3 100644
--- a/include/dm/ofnode.h
+++ b/include/dm/ofnode.h
@@ -434,6 +434,18 @@ int ofnode_read_u32(ofnode node, const char *propname, u32
*outp);
int ofnode_read_u32_index(ofnode node, const char *propname, int index,
u32 *outp);
+/**
+ * ofnode_read_u64_index() - Read a 64-bit integer from a multi-value property
+ *
+ * @node: valid node reference to read property from
+ * @propname: name of the property to read from
+ * @index: index of the integer to return
+ * @outp: place to put value (if found)
+ * Return: 0 if OK, -ve on error
+ */
+int ofnode_read_u64_index(ofnode node, const char *propname, int index,
+ u64 *outp);
+
/**
* ofnode_read_s32() - Read a 32-bit integer from a property
*
--
2.17.1
[PATCH 2/7] mtd: spi-nor: Add parallel and stacked memories support
In parallel mode, the current implementation assumes that a maximum of
two flashes are connected. The QSPI controller splits the data evenly
between both the flashes so, both the flashes that are connected in
parallel mode should be identical.
During each operation SPI-NOR sets 0th bit for CS0 & 1st bit for CS1 in
nor->flags.
In stacked mode the current implementation assumes that a maximum of two
flashes are connected and both the flashes are of same make but can
differ in sizes. So, except the sizes all other flash parameters of both
the flashes are identical
Spi-nor will pass on the appropriate flash select flag to low level
driver, and it will select pass all the data to that particular flash.
Write operation in parallel mode are performed in page size * 2 chunks as
each write operation results in writing both the flashes. For doubling
the address space each operation is performed at addr/2 flash offset,
where addr is the address specified by the user.
Similarly for read and erase operations it will read from both flashes,
so size and offset are divided by 2 and send to flash.
Signed-off-by: Ashok Reddy Soma
Signed-off-by: Venkatesh Yadav Abbarapu
---
drivers/mtd/spi/spi-nor-core.c | 280 +
include/linux/mtd/spi-nor.h| 13 ++
include/spi.h | 12 ++
3 files changed, 277 insertions(+), 28 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 6093277f17..061d88b627 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -638,12 +638,17 @@ static u8 spi_nor_convert_3to4_erase(u8 opcode)
static void spi_nor_set_4byte_opcodes(struct spi_nor *nor,
const struct flash_info *info)
{
+ bool shift = 0;
+
+ if (nor->flags & SNOR_F_HAS_PARALLEL)
+ shift = 1;
+
/* Do some manufacturer fixups first */
switch (JEDEC_MFR(info)) {
case SNOR_MFR_SPANSION:
/* No small sector erase for 4-byte command set */
nor->erase_opcode = SPINOR_OP_SE;
- nor->mtd.erasesize = info->sector_size;
+ nor->mtd.erasesize = info->sector_size << shift;
break;
default:
@@ -964,8 +969,8 @@ static int spi_nor_erase_sector(struct spi_nor *nor, u32
addr)
static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
{
struct spi_nor *nor = mtd_to_spi_nor(mtd);
+ u32 addr, len, rem, offset;
bool addr_known = false;
- u32 addr, len, rem;
int ret, err;
dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
@@ -990,6 +995,19 @@ static int spi_nor_erase(struct mtd_info *mtd, struct
erase_info *instr)
ret = -EINTR;
goto erase_err;
}
+
+ offset = addr;
+ if (nor->flags & SNOR_F_HAS_PARALLEL)
+ offset /= 2;
+
+ if (nor->flags & SNOR_F_HAS_STACKED) {
+ if (offset >= (mtd->size / 2)) {
+ offset = offset - (mtd->size / 2);
+ nor->spi->flags |= SPI_XFER_U_PAGE;
+ } else {
+ nor->spi->flags &= ~SPI_XFER_U_PAGE;
+ }
+ }
#ifdef CONFIG_SPI_FLASH_BAR
ret = write_bar(nor, addr);
if (ret < 0)
@@ -1393,6 +1411,9 @@ static const struct flash_info *spi_nor_read_id(struct
spi_nor *nor)
u8 id[SPI_NOR_MAX_ID_LEN];
const struct flash_info *info;
+ if (nor->flags & SNOR_F_HAS_PARALLEL)
+ nor->spi->flags |= SPI_XFER_LOWER;
+
tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
if (tmp < 0) {
dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp);
@@ -1417,28 +1438,57 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t
from, size_t len,
{
struct spi_nor *nor = mtd_to_spi_nor(mtd);
int ret;
+ u32 offset = from;
+ u32 stack_shift = 0;
+ u32 read_len = 0;
+ u32 rem_bank_len = 0;
+ u8 bank;
+ u8 is_ofst_odd = 0;
dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
- while (len) {
- loff_t addr = from;
- size_t read_len = len;
+ if ((nor->flags & SNOR_F_HAS_PARALLEL) && (offset & 1)) {
+ /* We can hit this case when we use file system like ubifs */
+ from = (loff_t)(from - 1);
+ len = (size_t)(len + 1);
+ is_ofst_odd = 1;
+ }
-#ifdef CONFIG_SPI_FLASH_BAR
- u32 remain_len;
+ while (len) {
+ i
[PATCH 4/7] mtd: spi-nor: Add parallel and stacked memories support in read_bar and write_bar
Add support for parallel memories and stacked memories configuration
in read_bar and write_bar functions.
Signed-off-by: Ashok Reddy Soma
Signed-off-by: Venkatesh Yadav Abbarapu
---
drivers/mtd/spi/spi-nor-core.c | 55 +-
1 file changed, 47 insertions(+), 8 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index e733b180de..4d15a90c8f 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -884,12 +884,32 @@ static int clean_bar(struct spi_nor *nor)
static int write_bar(struct spi_nor *nor, u32 offset)
{
- u8 cmd, bank_sel;
+ u8 cmd, bank_sel, upage_curr;
int ret;
+ struct mtd_info *mtd = &nor->mtd;
+
+ /* Wait until previous write command is finished */
+ if (spi_nor_wait_till_ready(nor))
+ return 1;
+
+ if (nor->flags & (SNOR_F_HAS_PARALLEL | SNOR_F_HAS_STACKED) &&
+ mtd->size <= SZ_32M)
+ return 0;
+
+ if (mtd->size <= SZ_16M)
+ return 0;
+
+ offset = offset % (u32)mtd->size;
+ bank_sel = offset >> 24;
- bank_sel = offset / SZ_16M;
- if (bank_sel == nor->bank_curr)
- goto bar_end;
+ upage_curr = nor->spi->flags & SPI_XFER_U_PAGE;
+
+ if (!(nor->flags & SNOR_F_HAS_STACKED) && bank_sel == nor->bank_curr)
+ return 0;
+ else if (upage_curr == nor->upage_prev && bank_sel == nor->bank_curr)
+ return 0;
+ else
+ nor->upage_prev = upage_curr;
cmd = nor->bank_write_cmd;
write_enable(nor);
@@ -899,15 +919,19 @@ static int write_bar(struct spi_nor *nor, u32 offset)
return ret;
}
-bar_end:
nor->bank_curr = bank_sel;
- return nor->bank_curr;
+
+ return write_disable(nor);
}
static int read_bar(struct spi_nor *nor, const struct flash_info *info)
{
u8 curr_bank = 0;
int ret;
+ struct mtd_info *mtd = &nor->mtd;
+
+ if (mtd->size <= SZ_16M)
+ return 0;
switch (JEDEC_MFR(info)) {
case SNOR_MFR_SPANSION:
@@ -919,15 +943,30 @@ static int read_bar(struct spi_nor *nor, const struct
flash_info *info)
nor->bank_write_cmd = SPINOR_OP_WREAR;
}
+ if (nor->flags & SNOR_F_HAS_PARALLEL)
+ nor->spi->flags |= SPI_XFER_LOWER;
+
ret = nor->read_reg(nor, nor->bank_read_cmd,
- &curr_bank, 1);
+ &curr_bank, 1);
if (ret) {
debug("SF: fail to read bank addr register\n");
return ret;
}
nor->bank_curr = curr_bank;
- return 0;
+ // Make sure both chips use the same BAR
+ if (nor->flags & SNOR_F_HAS_PARALLEL) {
+ write_enable(nor);
+ ret = nor->write_reg(nor, nor->bank_write_cmd, &curr_bank, 1);
+ if (ret)
+ return ret;
+
+ ret = write_disable(nor);
+ if (ret)
+ return ret;
+ }
+
+ return ret;
}
#endif
--
2.17.1
[PATCH 3/7] mtd: spi-nor: Add parallel memories support for read_sr and read_fsr
Add support for parallel memories flash configuration in read status
register and read flag status register functions.
Signed-off-by: Ashok Reddy Soma
Signed-off-by: Venkatesh Yadav Abbarapu
---
drivers/mtd/spi/spi-nor-core.c | 50 --
1 file changed, 36 insertions(+), 14 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 061d88b627..e733b180de 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -437,8 +437,9 @@ static ssize_t spi_nor_write_data(struct spi_nor *nor,
loff_t to, size_t len,
}
/*
- * Read the status register, returning its value in the location
- * Return the status register value.
+ * Return the status register value. If the chip is parallel, then the
+ * read will be striped, so we should read 2 bytes to get the sr
+ * register value from both of the parallel chips.
* Returns negative if error occurred.
*/
static int read_sr(struct spi_nor *nor)
@@ -470,18 +471,29 @@ static int read_sr(struct spi_nor *nor)
if (spi_nor_protocol_is_dtr(nor->reg_proto))
op.data.nbytes = 2;
- ret = spi_nor_read_write_reg(nor, &op, val);
- if (ret < 0) {
- pr_debug("error %d reading SR\n", (int)ret);
- return ret;
+ if (nor->flags & SNOR_F_HAS_PARALLEL) {
+ op.data.nbytes = 2;
+ ret = spi_nor_read_write_reg(nor, &op, &val[0]);
+ if (ret < 0) {
+ pr_debug("error %d reading SR\n", (int)ret);
+ return ret;
+ }
+ val[0] |= val[1];
+ } else {
+ ret = spi_nor_read_write_reg(nor, &op, &val[0]);
+ if (ret < 0) {
+ pr_debug("error %d reading SR\n", (int)ret);
+ return ret;
+ }
}
- return *val;
+ return val[0];
}
/*
- * Read the flag status register, returning its value in the location
- * Return the status register value.
+ * Return the flag status register value. If the chip is parallel, then
+ * the read will be striped, so we should read 2 bytes to get the fsr
+ * register value from both of the parallel chips.
* Returns negative if error occurred.
*/
static int read_fsr(struct spi_nor *nor)
@@ -513,13 +525,23 @@ static int read_fsr(struct spi_nor *nor)
if (spi_nor_protocol_is_dtr(nor->reg_proto))
op.data.nbytes = 2;
- ret = spi_nor_read_write_reg(nor, &op, val);
- if (ret < 0) {
- pr_debug("error %d reading FSR\n", ret);
- return ret;
+ if (nor->flags & SNOR_F_HAS_PARALLEL) {
+ op.data.nbytes = 2;
+ ret = spi_nor_read_write_reg(nor, &op, &val[0]);
+ if (ret < 0) {
+ pr_debug("error %d reading SR\n", (int)ret);
+ return ret;
+ }
+ val[0] &= val[1];
+ } else {
+ ret = spi_nor_read_write_reg(nor, &op, &val[0]);
+ if (ret < 0) {
+ pr_debug("error %d reading FSR\n", ret);
+ return ret;
+ }
}
- return *val;
+ return val[0];
}
/*
--
2.17.1
[PATCH 5/7] spi: spi-uclass: Read chipselect and restrict capabilities
Read chipselect properties from DT which are populated using 'reg'
property and save it in plat->cs[] array for later use.
Also read multi chipselect capability which is used for
parallel-memories and return errors if they are passed on using DT but
driver is not capable of handling it.
Signed-off-by: Ashok Reddy Soma
Signed-off-by: Venkatesh Yadav Abbarapu
---
drivers/spi/spi-uclass.c | 21 -
drivers/spi/xilinx_spi.c | 4 ++--
drivers/spi/zynq_qspi.c | 6 +++---
drivers/spi/zynq_spi.c | 6 +++---
include/spi.h| 2 +-
5 files changed, 25 insertions(+), 14 deletions(-)
diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
index c929e7c1d0..cdcf16d346 100644
--- a/drivers/spi/spi-uclass.c
+++ b/drivers/spi/spi-uclass.c
@@ -257,7 +257,7 @@ int spi_chip_select(struct udevice *dev)
{
struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev);
- return plat ? plat->cs : -ENOENT;
+ return plat ? plat->cs[0] : -ENOENT;
}
int spi_find_chip_select(struct udevice *bus, int cs, struct udevice **devp)
@@ -294,8 +294,8 @@ int spi_find_chip_select(struct udevice *bus, int cs,
struct udevice **devp)
struct dm_spi_slave_plat *plat;
plat = dev_get_parent_plat(dev);
- dev_dbg(bus, "%s: plat=%p, cs=%d\n", __func__, plat, plat->cs);
- if (plat->cs == cs) {
+ dev_dbg(bus, "%s: plat=%p, cs=%d\n", __func__, plat,
plat->cs[0]);
+ if (plat->cs[0] == cs) {
*devp = dev;
return 0;
}
@@ -448,7 +448,7 @@ int _spi_get_bus_and_cs(int busnum, int cs, int speed, int
mode,
return ret;
}
plat = dev_get_parent_plat(dev);
- plat->cs = cs;
+ plat->cs[0] = cs;
if (speed) {
plat->max_hz = speed;
} else {
@@ -479,6 +479,11 @@ int _spi_get_bus_and_cs(int busnum, int cs, int speed, int
mode,
slave = dev_get_parent_priv(dev);
bus_data = dev_get_uclass_priv(bus);
+ if ((dev_read_bool(dev, "parallel-memories")) && !slave->multi_cs_cap) {
+ dev_err(dev, "controller doesn't support multi CS\n");
+ return -EINVAL;
+ }
+
/*
* In case the operation speed is not yet established by
* dm_spi_claim_bus() ensure the bus is configured properly.
@@ -541,8 +546,14 @@ int spi_slave_of_to_plat(struct udevice *dev, struct
dm_spi_slave_plat *plat)
{
int mode = 0;
int value;
+ int ret;
+
+ ret = dev_read_u32_array(dev, "reg", plat->cs, SPI_CS_CNT_MAX);
+ if (ret && ret != -EOVERFLOW) {
+ dev_err(dev, "has no valid 'reg' property (%d)\n", ret);
+ return ret;
+ }
- plat->cs = dev_read_u32_default(dev, "reg", -1);
plat->max_hz = dev_read_u32_default(dev, "spi-max-frequency",
SPI_DEFAULT_SPEED_HZ);
if (dev_read_bool(dev, "spi-cpol"))
diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index b58a3f632a..7c4a9b79bb 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -270,7 +270,7 @@ static void xilinx_spi_startup_block(struct spi_slave *spi)
* Perform a dummy read as a work around for
* the startup block issue.
*/
- spi_cs_activate(spi->dev, slave_plat->cs);
+ spi_cs_activate(spi->dev, slave_plat->cs[0]);
txp = 0x9f;
start_transfer(spi, (void *)&txp, NULL, 1);
@@ -298,7 +298,7 @@ static int xilinx_spi_mem_exec_op(struct spi_slave *spi,
startup++;
}
- spi_cs_activate(spi->dev, slave_plat->cs);
+ spi_cs_activate(spi->dev, slave_plat->cs[0]);
if (op->cmd.opcode) {
ret = start_transfer(spi, (void *)&op->cmd.opcode, NULL, 1);
diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c
index cb52c0f307..069d2a77de 100644
--- a/drivers/spi/zynq_qspi.c
+++ b/drivers/spi/zynq_qspi.c
@@ -586,13 +586,13 @@ static int zynq_qspi_xfer(struct udevice *dev, unsigned
int bitlen,
struct zynq_qspi_priv *priv = dev_get_priv(bus);
struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
- priv->cs = slave_plat->cs;
+ priv->cs = slave_plat->cs[0];
priv->tx_buf = dout;
priv->rx_buf = din;
priv->len = bitlen / 8;
- debug("zynq_qspi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
- dev_seq(bus), slave_plat->cs, bitlen, priv->len, flags);
+ debug("zynq_qspi_xfer: bus:%i cs[0]:%i bitlen:%i len:%i flags:%lx\n",
[PATCH 6/7] spi: zynqmp_gqspi: Add parallel memories support in GQSPI driver
Add support for parallel memories in zynqmp_gqspi.c driver. In case of
parallel memories STRIPE bit is set and sent to the qspi ip, which will
send data bits to both the flashes in parallel. However for few commands
we should not use stripe, instead send same data to both the flashes.
Those commands are exclueded by using zynqmp_qspi_update_stripe().
Also update copyright info for this file.
Signed-off-by: Ashok Reddy Soma
Signed-off-by: Venkatesh Yadav Abbarapu
---
drivers/spi/zynqmp_gqspi.c | 146 -
include/spi.h | 12 +++
2 files changed, 140 insertions(+), 18 deletions(-)
diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index c4aee279aa..1c7483bbd8 100644
--- a/drivers/spi/zynqmp_gqspi.c
+++ b/drivers/spi/zynqmp_gqspi.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * (C) Copyright 2018 Xilinx
+ * (C) Copyright 2013 - 2022, Xilinx, Inc.
+ * (C) Copyright 2023, Advanced Micro Devices, Inc.
*
* Xilinx ZynqMP Generic Quad-SPI(QSPI) controller driver(master mode only)
*/
@@ -23,6 +24,8 @@
#include
#include
#include
+#include
+#include "../mtd/spi/sf_internal.h"
#include
#define GQSPI_GFIFO_STRT_MODE_MASK BIT(29)
@@ -86,6 +89,9 @@
#define SPI_XFER_ON_LOWER 1
#define SPI_XFER_ON_UPPER 2
+#define GQSPI_SELECT_LOWER_CS BIT(0)
+#define GQSPI_SELECT_UPPER_CS BIT(1)
+
#define GQSPI_DMA_ALIGN0x4
#define GQSPI_MAX_BAUD_RATE_VAL7
#define GQSPI_DFLT_BAUD_RATE_VAL 2
@@ -181,13 +187,14 @@ struct zynqmp_qspi_priv {
int bytes_to_transfer;
int bytes_to_receive;
const struct spi_mem_op *op;
+ unsigned int is_parallel;
+ unsigned int u_page;
+ unsigned int bus;
+ unsigned int stripe;
+ unsigned int flags;
+ u32 max_hz;
};
-__weak int zynqmp_mmio_write(const u32 address, const u32 mask, const u32
value)
-{
- return 0;
-}
-
static int zynqmp_qspi_of_to_plat(struct udevice *bus)
{
struct zynqmp_qspi_plat *plat = dev_get_plat(bus);
@@ -234,9 +241,30 @@ static u32 zynqmp_qspi_bus_select(struct zynqmp_qspi_priv
*priv)
{
u32 gqspi_fifo_reg = 0;
- gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS |
-GQSPI_GFIFO_CS_LOWER;
-
+ if (priv->is_parallel) {
+ if (priv->bus == SPI_XFER_ON_BOTH)
+ gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS |
+GQSPI_GFIFO_UP_BUS |
+GQSPI_GFIFO_CS_UPPER |
+GQSPI_GFIFO_CS_LOWER;
+ else if (priv->bus == SPI_XFER_ON_LOWER)
+ gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS |
+GQSPI_GFIFO_CS_UPPER |
+GQSPI_GFIFO_CS_LOWER;
+ else if (priv->bus == SPI_XFER_ON_UPPER)
+ gqspi_fifo_reg = GQSPI_GFIFO_UP_BUS |
+GQSPI_GFIFO_CS_LOWER |
+GQSPI_GFIFO_CS_UPPER;
+ else
+ debug("Wrong Bus selection:0x%x\n", priv->bus);
+ } else {
+ if (priv->u_page)
+ gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS |
+GQSPI_GFIFO_CS_UPPER;
+ else
+ gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS |
+GQSPI_GFIFO_CS_LOWER;
+ }
return gqspi_fifo_reg;
}
@@ -279,7 +307,6 @@ static void zynqmp_qspi_fill_gen_fifo(struct
zynqmp_qspi_priv *priv,
GQSPI_TIMEOUT, 1);
if (ret)
printf("%s Timeout\n", __func__);
-
}
static void zynqmp_qspi_chipselect(struct zynqmp_qspi_priv *priv, int is_on)
@@ -291,7 +318,13 @@ static void zynqmp_qspi_chipselect(struct zynqmp_qspi_priv
*priv, int is_on)
gqspi_fifo_reg |= GQSPI_SPI_MODE_SPI |
GQSPI_IMD_DATA_CS_ASSERT;
} else {
- gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS;
+ if (priv->is_parallel)
+ gqspi_fifo_reg = GQSPI_GFIFO_UP_BUS |
+GQSPI_GFIFO_LOW_BUS;
+ else if (priv->u_page)
+ gqspi_fifo_reg = GQSPI_GFIFO_UP_BUS;
+ else
+ gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS;
gqspi_fifo_reg |= GQSPI_IMD_DATA_CS_DEASSERT;
}
@@ -362,13 +395,15 @@ static int zynqmp_qspi_set_speed(struct udevice *bus,
uint speed)
u32 confr;
u8 baud_rate_val = 0;
- debug("%s\n", __func__);
- if (speed > plat->frequency)
- speed = plat->frequency;
+ /*
+* If speed =
[PATCH 7/7] spi: zynq_qspi: Add parallel memories support in QSPI driver
Add support for parallel memories in zynq_qspi.c driver. In case of
parallel memories STRIPE bit is set and sent to the qspi ip, which will
send data bits to both the flashes in parallel. However for few commands
we should not use stripe, instead send same data to both the flashes.
Those commands are exclueded by using zynqmp_qspi_update_stripe().
Also update copyright info for this file.
Signed-off-by: Ashok Reddy Soma
Signed-off-by: Venkatesh Yadav Abbarapu
---
drivers/spi/zynq_qspi.c | 139
include/spi.h | 3 +
2 files changed, 129 insertions(+), 13 deletions(-)
diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c
index 069d2a77de..9f4c1f487b 100644
--- a/drivers/spi/zynq_qspi.c
+++ b/drivers/spi/zynq_qspi.c
@@ -1,7 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * (C) Copyright 2013 Xilinx, Inc.
+ * (C) Copyright 2013 - 2022, Xilinx, Inc.
* (C) Copyright 2015 Jagan Teki
+ * (C) Copyright 2023, Advanced Micro Devices, Inc.
*
* Xilinx Zynq Quad-SPI(QSPI) controller driver (master mode only)
*/
@@ -13,10 +14,12 @@
#include
#include
#include
+#include
#include
#include
#include
#include
+#include "../mtd/spi/sf_internal.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -42,6 +45,22 @@ DECLARE_GLOBAL_DATA_PTR;
#define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80/* Transmit 1-byte inst */
#define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84/* Transmit 2-byte inst */
#define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88/* Transmit 3-byte inst */
+#define ZYNQ_QSPI_FR_QOUT_CODE 0x6B/* read instruction code */
+#define ZYNQ_QSPI_FR_DUALIO_CODE 0xBB
+
+#define QSPI_SELECT_LOWER_CS BIT(0)
+#define QSPI_SELECT_UPPER_CS BIT(1)
+
+/*
+ * QSPI Linear Configuration Register
+ *
+ * It is named Linear Configuration but it controls other modes when not in
+ * linear mode also.
+ */
+#define ZYNQ_QSPI_LCFG_TWO_MEM_MASK0x4000 /* QSPI Enable Bit Mask */
+#define ZYNQ_QSPI_LCFG_SEP_BUS_MASK0x2000 /* QSPI Enable Bit Mask */
+#define ZYNQ_QSPI_LCFG_U_PAGE 0x1000 /* QSPI Upper memory set */
+#define ZYNQ_QSPI_LCFG_DUMMY_SHIFT 8
#define ZYNQ_QSPI_TXFIFO_THRESHOLD 1 /* Tx FIFO threshold level*/
#define ZYNQ_QSPI_RXFIFO_THRESHOLD 32 /* Rx FIFO threshold level */
@@ -101,7 +120,12 @@ struct zynq_qspi_priv {
int bytes_to_transfer;
int bytes_to_receive;
unsigned int is_inst;
+ unsigned int is_parallel;
+ unsigned int is_stacked;
+ unsigned int is_dio;
+ unsigned int u_page;
unsigned cs_change:1;
+ unsigned is_strip:1;
};
static int zynq_qspi_of_to_plat(struct udevice *bus)
@@ -112,7 +136,6 @@ static int zynq_qspi_of_to_plat(struct udevice *bus)
plat->regs = (struct zynq_qspi_regs *)fdtdec_get_addr(blob,
node, "reg");
-
return 0;
}
@@ -147,6 +170,9 @@ static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv)
/* Disable Interrupts */
writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->idr);
+ /* Disable linear mode as the boot loader may have used it */
+ writel(0x0, ®s->lqspicfg);
+
/* Clear the TX and RX threshold reg */
writel(ZYNQ_QSPI_TXFIFO_THRESHOLD, ®s->txftr);
writel(ZYNQ_QSPI_RXFIFO_THRESHOLD, ®s->rxftr);
@@ -164,12 +190,11 @@ static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv)
confr |= ZYNQ_QSPI_CR_IFMODE_MASK | ZYNQ_QSPI_CR_MCS_MASK |
ZYNQ_QSPI_CR_PCS_MASK | ZYNQ_QSPI_CR_FW_MASK |
ZYNQ_QSPI_CR_MSTREN_MASK;
- writel(confr, ®s->cr);
- /* Disable the LQSPI feature */
- confr = readl(®s->lqspicfg);
- confr &= ~ZYNQ_QSPI_LQSPICFG_LQMODE_MASK;
- writel(confr, ®s->lqspicfg);
+ if (priv->is_stacked)
+ confr |= 0x10;
+
+ writel(confr, ®s->cr);
/* Enable SPI */
writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr);
@@ -180,6 +205,8 @@ static int zynq_qspi_child_pre_probe(struct udevice *bus)
struct spi_slave *slave = dev_get_parent_priv(bus);
struct zynq_qspi_priv *priv = dev_get_priv(bus->parent);
+ slave->multi_cs_cap = true;
+ slave->dio = priv->is_dio;
priv->max_hz = slave->max_hz;
return 0;
@@ -363,8 +390,8 @@ static void zynq_qspi_fill_tx_fifo(struct zynq_qspi_priv
*priv, u32 size)
unsigned len, offset;
struct zynq_qspi_regs *regs = priv->regs;
static const unsigned offsets[4] = {
- ZYNQ_QSPI_TXD_00_00_OFFSET, ZYNQ_QSPI_TXD_00_01_OFFSET,
- ZYNQ_QSPI_TXD_00_10_OFFSET, ZYNQ_QSPI_TXD_00_11_OFFSET };
+ ZYNQ_QSPI_TXD_00_01_OFFSET, ZYNQ_QSPI_TXD_00_10_OFFSET,
+ ZYNQ_QSPI_TXD_00_11_OFFSET, ZYNQ_QSPI_TXD_00_00_OFFSET };
while ((fifocount < size) &&
[PATCH] mtd: nand: Mark reserved blocks
Reserved blocks are used for storing bad block tables. With "nand bad"
command, these reserved blocks are shown as bad blocks. This is leading
to confusion when compared with Linux bad blocks. Hence, display
"Reserved for bbt" when printing reserved blocks with "nand bad" command.
To acheive this, return 2 which represents reserved from nand_isbad_bbt()
instead of 1 in case of reserved blocks and catch it in cmd/nand.c.
"nand bad" command display's hexadecimal numbers, so add "0x" prefix.
Example log will show up as below.
ZynqMP> nand bad
Device 0 bad blocks:
0x0040
0x1680
0x16c0
0x1700
0x3d80
0x3e40
0xe840
0xff00 <--- Reserved for bbt
0xff40 <--- Reserved for bbt
0xff80 <--- Reserved for bbt
0xffc0 <--- Reserved for bbt
0x11680
0x116c0
0x1ff00<--- Reserved for bbt
0x1ff40<--- Reserved for bbt
0x1ff80<--- Reserved for bbt
0x1ffc0<--- Reserved for bbt
Signed-off-by: Ashok Reddy Soma
---
cmd/nand.c | 9 ++---
drivers/mtd/nand/raw/nand_bbt.c | 3 ++-
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/cmd/nand.c b/cmd/nand.c
index 9a723f5757..feb6b0e3ec 100644
--- a/cmd/nand.c
+++ b/cmd/nand.c
@@ -567,9 +567,12 @@ static int do_nand(struct cmd_tbl *cmdtp, int flag, int
argc,
if (strcmp(cmd, "bad") == 0) {
printf("\nDevice %d bad blocks:\n", dev);
- for (off = 0; off < mtd->size; off += mtd->erasesize)
- if (nand_block_isbad(mtd, off))
- printf(" %08llx\n", (unsigned long long)off);
+ for (off = 0; off < mtd->size; off += mtd->erasesize) {
+ ret = nand_block_isbad(mtd, off);
+ if (ret)
+ printf(" 0x%08llx%s\n", (unsigned long
long)off,
+ ret == 2 ? "\t <--- Reserved for bbt" :
"");
+ }
return 0;
}
diff --git a/drivers/mtd/nand/raw/nand_bbt.c b/drivers/mtd/nand/raw/nand_bbt.c
index 911472e91e..cd451870a6 100644
--- a/drivers/mtd/nand/raw/nand_bbt.c
+++ b/drivers/mtd/nand/raw/nand_bbt.c
@@ -1330,6 +1330,7 @@ int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs)
* @mtd: MTD device structure
* @offs: offset in the device
* @allowbbt: allow access to bad block table region
+ * Return: 0 - good block, 1- bad block, 2 - reserved block
*/
int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt)
{
@@ -1348,7 +1349,7 @@ int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int
allowbbt)
case BBT_BLOCK_WORN:
return 1;
case BBT_BLOCK_RESERVED:
- return allowbbt ? 0 : 1;
+ return allowbbt ? 0 : 2;
}
return 1;
}
--
2.17.1
[PATCH v2] mtd: nand: Mark reserved blocks
Reserved blocks are used for storing bad block tables. With "nand bad"
command, these reserved blocks are shown as bad blocks. This is leading
to confusion when compared with Linux bad blocks. Hence, display
"bbt reserved" when printing reserved blocks with "nand bad" command.
To acheive this, return 2 which represents reserved from nand_isbad_bbt()
instead of 1 in case of reserved blocks and catch it in cmd/nand.c.
"nand bad" command display's hexadecimal numbers, so add "0x" prefix.
Example log will show up as below.
ZynqMP> nand bad
Device 0 bad blocks:
0x0040
0x1680
0x16c0
0x1700
0x3d80
0x3e40
0xe840
0xff00 (bbt reserved)
0xff40 (bbt reserved)
0xff80 (bbt reserved)
0xffc0 (bbt reserved)
0x11680
0x116c0
0x1ff00(bbt reserved)
0x1ff40(bbt reserved)
0x1ff80(bbt reserved)
0x1ffc0(bbt reserved)
Signed-off-by: Ashok Reddy Soma
Reviewed-by: Michael Trimarchi
---
Changes in v2:
- Changed "Reserved for bbt" to (bbt reserved)
- Updated description and the log in the description
cmd/nand.c | 9 ++---
drivers/mtd/nand/raw/nand_bbt.c | 3 ++-
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/cmd/nand.c b/cmd/nand.c
index 9a723f5757..b41e54ec42 100644
--- a/cmd/nand.c
+++ b/cmd/nand.c
@@ -567,9 +567,12 @@ static int do_nand(struct cmd_tbl *cmdtp, int flag, int
argc,
if (strcmp(cmd, "bad") == 0) {
printf("\nDevice %d bad blocks:\n", dev);
- for (off = 0; off < mtd->size; off += mtd->erasesize)
- if (nand_block_isbad(mtd, off))
- printf(" %08llx\n", (unsigned long long)off);
+ for (off = 0; off < mtd->size; off += mtd->erasesize) {
+ ret = nand_block_isbad(mtd, off);
+ if (ret)
+ printf(" 0x%08llx%s\n", (unsigned long
long)off,
+ ret == 2 ? "\t (bbt reserved)" : "");
+ }
return 0;
}
diff --git a/drivers/mtd/nand/raw/nand_bbt.c b/drivers/mtd/nand/raw/nand_bbt.c
index 911472e91e..cd451870a6 100644
--- a/drivers/mtd/nand/raw/nand_bbt.c
+++ b/drivers/mtd/nand/raw/nand_bbt.c
@@ -1330,6 +1330,7 @@ int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs)
* @mtd: MTD device structure
* @offs: offset in the device
* @allowbbt: allow access to bad block table region
+ * Return: 0 - good block, 1- bad block, 2 - reserved block
*/
int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt)
{
@@ -1348,7 +1349,7 @@ int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int
allowbbt)
case BBT_BLOCK_WORN:
return 1;
case BBT_BLOCK_RESERVED:
- return allowbbt ? 0 : 1;
+ return allowbbt ? 0 : 2;
}
return 1;
}
--
2.17.1
[PATCH 0/4] Fix sparse warnings
Run and fix sparse warnings in below files -drivers/mmc/zynq_sdhci.c -board/xilinx/common/board.h -drivers/gpio/zynqmp_gpio_modepin.c -board/xilinx/versal/board.c Algapally Santosh Sagar (4): xilinx: common: Add missing prototype for board_get_usable_ram_top gpio: zynqmp: Remove unused variable ret xilinx: versal: Add missing prototype drivers: mmc: Change datatype to fix a warning board/xilinx/common/board.h| 4 board/xilinx/versal/board.c| 1 + drivers/gpio/zynqmp_gpio_modepin.c | 3 +-- drivers/mmc/zynq_sdhci.c | 2 +- 4 files changed, 7 insertions(+), 3 deletions(-) -- 2.17.1
[PATCH 1/4] xilinx: common: Add missing prototype for board_get_usable_ram_top
From: Algapally Santosh Sagar Add missing prototype to fix the sparse warning, warning: no previous prototype for 'board_get_usable_ram_top' [-Wmissing-prototypes]. Signed-off-by: Algapally Santosh Sagar Signed-off-by: Ashok Reddy Soma --- board/xilinx/common/board.h | 4 1 file changed, 4 insertions(+) diff --git a/board/xilinx/common/board.h b/board/xilinx/common/board.h index 69e642429b..ef7f3f3dce 100644 --- a/board/xilinx/common/board.h +++ b/board/xilinx/common/board.h @@ -11,4 +11,8 @@ int board_late_init_xilinx(void); int xilinx_read_eeprom(void); +#if defined(CONFIG_LMB) +phys_size_t board_get_usable_ram_top(phys_size_t total_size); +#endif + #endif /* BOARD_XILINX_COMMON_BOARD_H */ -- 2.17.1
[PATCH 2/4] gpio: zynqmp: Remove unused variable ret
From: Algapally Santosh Sagar
There is a unused variable ret, due to which we are getting sparse warning
as below.
warning: variable 'ret' set but not used [-Wunused-but-set-variable].
Remove variable ret.
Signed-off-by: Algapally Santosh Sagar
Signed-off-by: Ashok Reddy Soma
---
drivers/gpio/zynqmp_gpio_modepin.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpio/zynqmp_gpio_modepin.c
b/drivers/gpio/zynqmp_gpio_modepin.c
index 078fd83395..52eda9ceb4 100644
--- a/drivers/gpio/zynqmp_gpio_modepin.c
+++ b/drivers/gpio/zynqmp_gpio_modepin.c
@@ -45,9 +45,8 @@ static int modepin_gpio_set_value(struct udevice *dev,
unsigned int offset,
{
u32 ret_payload[PAYLOAD_ARG_CNT];
u32 out_val = 0;
- int ret;
- ret = get_gpio_modepin(ret_payload);
+ get_gpio_modepin(ret_payload);
if (value)
out_val = OUTVAL(offset) | ret_payload[1];
else
--
2.17.1
[PATCH 3/4] xilinx: versal: Add missing prototype
From: Algapally Santosh Sagar Add missing prototype to fix the sparse warning, warning: no previous prototype for 'do_go_exec' [-Wmissing-prototypes]. Signed-off-by: Algapally Santosh Sagar Signed-off-by: Ashok Reddy Soma --- board/xilinx/versal/board.c | 1 + 1 file changed, 1 insertion(+) diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c index f9f5457ed2..d8562ce47a 100644 --- a/board/xilinx/versal/board.c +++ b/board/xilinx/versal/board.c @@ -22,6 +22,7 @@ #include #include #include "../common/board.h" +#include DECLARE_GLOBAL_DATA_PTR; -- 2.17.1
[PATCH 4/4] drivers: mmc: Change datatype to fix a warning
From: Algapally Santosh Sagar tuning_loop_counter is of char type. Change to int to fix below warning. warning: comparison is always false due to limited range of data type. Signed-off-by: Algapally Santosh Sagar Signed-off-by: Ashok Reddy Soma --- drivers/mmc/zynq_sdhci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 7dcf6ad842..be4075c97a 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -249,7 +249,7 @@ static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode) u32 ctrl; struct sdhci_host *host; struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev); - char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT; + int tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT; dev_dbg(mmc->dev, "%s\n", __func__); -- 2.17.1
[0/4] Add eMMC 5.1 support for Versal NET
This patch series, - Add support for eMMC5.1 on Versal NET platform by adding new compatible string and PHY support. - Add support for input and output tap delays for eMMC - Add support for enabling HS400 in host capabilities by checking quirk. - Add quirk to support HS400 for Versal NET Ashok Reddy Soma (4): mmc: zynq_sdhci: Add support for eMMC5.1 for Versal NET platform mmc: sdhci: Check and call config_dll callback functions mmc: sdhci: Enable HS400 support if available in caps mmc: zynq_sdhci: Add support and quirk for HS400 drivers/mmc/sdhci.c | 20 +++ drivers/mmc/zynq_sdhci.c | 292 ++- include/sdhci.h | 5 + 3 files changed, 314 insertions(+), 3 deletions(-) -- 2.17.1
[1/4] mmc: zynq_sdhci: Add support for eMMC5.1 for Versal NET platform
Add support for eMMC 5.1 for Versal NET platform
- Add new compatible string(xlnx,versal-net-5.1-emmc).
- Add CONFIG_ARCH_VERSAL_NET condition wherever required.
- Add DLL and Delay Chain mode support
- Add input and output tap delays for eMMC.
- Add Strobe select tap for HS400 mode.
Signed-off-by: Ashok Reddy Soma
---
drivers/mmc/zynq_sdhci.c | 287 ++-
1 file changed, 284 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index 7dcf6ad842..8415da3373 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * (C) Copyright 2013 - 2015 Xilinx, Inc.
+ * (C) Copyright 2013 - 2022, Xilinx, Inc.
+ * (C) Copyright 2022, Advanced Micro Devices, Inc.
*
* Xilinx Zynq SD Host Controller Interface
*/
@@ -16,6 +17,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -48,6 +50,41 @@
#define SD0_OTAPDLYSEL_MASKGENMASK(5, 0)
#define SD1_OTAPDLYSEL_MASKGENMASK(21, 16)
+#define MIN_PHY_CLK_HZ 5000
+
+#define PHY_CTRL_REG1 0x270
+#define PHY_CTRL_ITAPDLY_ENA_MASK BIT(0)
+#define PHY_CTRL_ITAPDLY_SEL_MASK GENMASK(5, 1)
+#define PHY_CTRL_ITAPDLY_SEL_SHIFT 1
+#define PHY_CTRL_ITAP_CHG_WIN_MASK BIT(6)
+#define PHY_CTRL_OTAPDLY_ENA_MASK BIT(8)
+#define PHY_CTRL_OTAPDLY_SEL_MASK GENMASK(15, 12)
+#define PHY_CTRL_OTAPDLY_SEL_SHIFT 12
+#define PHY_CTRL_STRB_SEL_MASK GENMASK(23, 16)
+#define PHY_CTRL_STRB_SEL_SHIFT16
+#define PHY_CTRL_TEST_CTRL_MASKGENMASK(31, 24)
+
+#define PHY_CTRL_REG2 0x274
+#define PHY_CTRL_EN_DLL_MASK BIT(0)
+#define PHY_CTRL_DLL_RDY_MASK BIT(1)
+#define PHY_CTRL_FREQ_SEL_MASK GENMASK(6, 4)
+#define PHY_CTRL_FREQ_SEL_SHIFT4
+#define PHY_CTRL_SEL_DLY_TX_MASK BIT(16)
+#define PHY_CTRL_SEL_DLY_RX_MASK BIT(17)
+#define FREQSEL_200M_170M 0x0
+#define FREQSEL_170M_140M 0x1
+#define FREQSEL_140M_110M 0x2
+#define FREQSEL_110M_80M 0x3
+#define FREQSEL_80M_50M0x4
+#define FREQSEL_275M_250M 0x5
+#define FREQSEL_250M_225M 0x6
+#define FREQSEL_225M_200M 0x7
+#define PHY_DLL_TIMEOUT_MS 100
+
+#define VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLY_CHAIN 39
+#define VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLL 146
+#define VERSAL_NET_PHY_CTRL_STRB90_STRB180_VAL 0X77
+
struct arasan_sdhci_clk_data {
int clk_phase_in[MMC_TIMING_MMC_HS400 + 1];
int clk_phase_out[MMC_TIMING_MMC_HS400 + 1];
@@ -64,6 +101,7 @@ struct arasan_sdhci_priv {
u32 node_id;
u8 bank;
u8 no_1p8;
+ bool internal_phy_reg;
struct reset_ctl_bulk resets;
};
@@ -84,7 +122,7 @@ __weak int zynqmp_pm_is_function_supported(const u32 api_id,
const u32 id)
return 1;
}
-#if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL)
+#if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL) ||
defined(CONFIG_ARCH_VERSAL_NET)
/* Default settings for ZynqMP Clock Phases */
static const u32 zynqmp_iclk_phases[] = {0, 63, 63, 0, 63, 0,
0, 183, 54, 0, 0};
@@ -97,6 +135,12 @@ static const u32 versal_iclk_phases[] = {0, 132, 132, 0,
132,
static const u32 versal_oclk_phases[] = {0, 60, 48, 0, 48, 72,
90, 36, 60, 90, 0};
+/* Default settings for versal-net eMMC Clock Phases */
+static const u32 versal_net_emmc_iclk_phases[] = {0, 0, 0, 0, 0, 0, 0, 0, 39,
+ 0, 0};
+static const u32 versal_net_emmc_oclk_phases[] = {0, 113, 0, 0, 0, 0, 0, 0,
+ 113, 79, 45};
+
static const u8 mode2timing[] = {
[MMC_LEGACY] = MMC_TIMING_LEGACY,
[MMC_HS] = MMC_TIMING_MMC_HS,
@@ -111,6 +155,121 @@ static const u8 mode2timing[] = {
[MMC_HS_200] = MMC_TIMING_MMC_HS200,
};
+#if defined(CONFIG_ARCH_VERSAL_NET)
+/**
+ * arasan_phy_set_delaychain - Set eMMC delay chain based Input/Output clock
+ *
+ * @host: Pointer to the sdhci_host structure
+ * @enable:Enable or disable Delay chain based Tx and Rx clock
+ * Return: None
+ *
+ * Enable or disable eMMC delay chain based Input and Output clock in
+ * PHY_CTRL_REG2
+ */
+static void arasan_phy_set_delaychain(struct sdhci_host *host, bool enable)
+{
+ u32 reg;
+
+ reg = sdhci_readw(host, PHY_CTRL_REG2);
+ if (enable)
+ reg |= PHY_CTRL_SEL_DLY_TX_MASK | PHY_CTRL_SEL_DLY_RX_MASK;
+ else
+ reg &= ~(PHY_CTRL_SEL_DLY_TX_MASK | PHY_CTRL_SEL_DLY_RX_MASK);
+
+ sdhci_writew(host, reg, PHY_CTRL_REG2);
+}
+
+/**
+ * arasan_phy_set_dll - Set eMMC DLL clock
+ *
+ * @host: Pointe
[2/4] mmc: sdhci: Check and call config_dll callback functions
Check if the low level driver supports config_dll callback function and
call it if it does. Call with dll disable before calling set_clock and
with dll enable after it.
Signed-off-by: Ashok Reddy Soma
---
drivers/mmc/sdhci.c | 16
include/sdhci.h | 2 ++
2 files changed, 18 insertions(+)
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index a80ad8329a..181ab9b7cb 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -396,6 +396,14 @@ int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
}
}
+ if (host->ops && host->ops->config_dll) {
+ ret = host->ops->config_dll(host, clock, false);
+ if (ret) {
+ printf("%s: Error while configuring dll\n", __func__);
+ return ret;
+ }
+ }
+
if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
/*
* Check if the Host Controller supports Programmable Clock
@@ -439,6 +447,14 @@ int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
if (host->ops && host->ops->set_clock)
host->ops->set_clock(host, div);
+ if (host->ops && host->ops->config_dll) {
+ ret = host->ops->config_dll(host, clock, true);
+ if (ret) {
+ printf("%s: Error while configuring dll\n", __func__);
+ return ret;
+ }
+ }
+
clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
<< SDHCI_DIVIDER_HI_SHIFT;
diff --git a/include/sdhci.h b/include/sdhci.h
index 24b4599b85..64a3d309da 100644
--- a/include/sdhci.h
+++ b/include/sdhci.h
@@ -272,6 +272,8 @@ struct sdhci_ops {
void(*set_clock)(struct sdhci_host *host, u32 div);
int (*platform_execute_tuning)(struct mmc *host, u8 opcode);
int (*set_delay)(struct sdhci_host *host);
+ /* Callback function to set DLL clock configuration */
+ int (*config_dll)(struct sdhci_host *host, u32 clock, bool enable);
int (*deferred_probe)(struct sdhci_host *host);
/**
--
2.17.1
[3/4] mmc: sdhci: Enable HS400 support if available in caps
HS400 is indicated in bit63 of capability register in few IP's. Add a quirk to check this and add HS400 to host capabilities. Signed-off-by: Ashok Reddy Soma --- drivers/mmc/sdhci.c | 4 include/sdhci.h | 3 +++ 2 files changed, 7 insertions(+) diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 181ab9b7cb..c6b250b9a1 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -995,6 +995,10 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, cfg->host_caps |= MMC_CAP(UHS_SDR50); } + if ((host->quirks & SDHCI_QUIRK_CAPS_BIT63_FOR_HS400) && + (caps_1 & SDHCI_SUPPORT_HS400)) + cfg->host_caps |= MMC_CAP(MMC_HS_400); + if (caps_1 & SDHCI_SUPPORT_DDR50) cfg->host_caps |= MMC_CAP(UHS_DDR50); diff --git a/include/sdhci.h b/include/sdhci.h index 64a3d309da..70fefca2a9 100644 --- a/include/sdhci.h +++ b/include/sdhci.h @@ -189,6 +189,7 @@ #define SDHCI_SUPPORT_SDR50 0x0001 #define SDHCI_SUPPORT_SDR104 0x0002 #define SDHCI_SUPPORT_DDR50 0x0004 +#define SDHCI_SUPPORT_HS400 BIT(31) #define SDHCI_USE_SDR50_TUNING0x2000 #define SDHCI_CLOCK_MUL_MASK 0x00FF @@ -248,6 +249,8 @@ #define SDHCI_QUIRK_USE_WIDE8 (1 << 8) #define SDHCI_QUIRK_NO_1_8_V (1 << 9) #define SDHCI_QUIRK_SUPPORT_SINGLE (1 << 10) +/* Capability register bit-63 indicates HS400 support */ +#define SDHCI_QUIRK_CAPS_BIT63_FOR_HS400 BIT(11) /* to make gcc happy */ struct sdhci_host; -- 2.17.1
[4/4] mmc: zynq_sdhci: Add support and quirk for HS400
Add support for HS400 in mode2timing array.
Add a quirk for Versal NET platform to indicate that HS400 is supported
through bit63 of capability register.
Signed-off-by: Ashok Reddy Soma
---
drivers/mmc/zynq_sdhci.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index 8415da3373..72de6c6227 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -153,6 +153,7 @@ static const u8 mode2timing[] = {
[UHS_DDR50] = MMC_TIMING_UHS_DDR50,
[UHS_SDR104] = MMC_TIMING_UHS_SDR104,
[MMC_HS_200] = MMC_TIMING_MMC_HS200,
+ [MMC_HS_400] = MMC_TIMING_MMC_HS400,
};
#if defined(CONFIG_ARCH_VERSAL_NET)
@@ -1133,6 +1134,10 @@ static int arasan_sdhci_probe(struct udevice *dev)
if (priv->no_1p8)
host->quirks |= SDHCI_QUIRK_NO_1_8_V;
+ if (CONFIG_IS_ENABLED(ARCH_VERSAL_NET) &&
+ device_is_compatible(dev, "xlnx,versal-net-5.1-emmc"))
+ host->quirks |= SDHCI_QUIRK_CAPS_BIT63_FOR_HS400;
+
plat->cfg.f_max = CONFIG_ZYNQ_SDHCI_MAX_FREQ;
ret = mmc_of_parse(dev, &plat->cfg);
--
2.17.1
RE: [PATCH 2/2] arm64: zynqmp: Enable seps and related video configs
Acked-by: Ashok Reddy Soma > -Original Message- > From: Michal Simek On Behalf Of Michal Simek > Sent: Thursday, January 7, 2021 6:56 PM > To: u-boot@lists.denx.de; git ; Simon Glass > > Subject: [PATCH 2/2] arm64: zynqmp: Enable seps and related video configs > > Enable this driver to get build and probe for our platform. > > Signed-off-by: Michal Simek > --- > > configs/xilinx_zynqmp_virt_defconfig | 10 ++ > 1 file changed, 10 insertions(+) > > diff --git a/configs/xilinx_zynqmp_virt_defconfig > b/configs/xilinx_zynqmp_virt_defconfig > index e400cd4702ee..0bf4b7d692e9 100644 > --- a/configs/xilinx_zynqmp_virt_defconfig > +++ b/configs/xilinx_zynqmp_virt_defconfig > @@ -54,6 +54,7 @@ CONFIG_CMD_SPI=y > CONFIG_CMD_USB=y > CONFIG_CMD_USB_MASS_STORAGE=y > CONFIG_CMD_TFTPPUT=y > +CONFIG_CMD_BMP=y > CONFIG_CMD_CACHE=y > CONFIG_CMD_TIME=y > CONFIG_CMD_TIMER=y > @@ -155,6 +156,15 @@ CONFIG_USB_ETHER=y > CONFIG_USB_ETH_CDC=y > CONFIG_USB_HOST_ETHER=y > CONFIG_USB_ETHER_ASIX=y > +CONFIG_DM_VIDEO=y > +CONFIG_VIDEO_COPY=y > +CONFIG_DISPLAY=y > +CONFIG_VIDEO_SEPS525=y > +CONFIG_LCD=y > +CONFIG_SPLASH_SCREEN=y > +CONFIG_BMP_16BPP=y > +CONFIG_BMP_24BPP=y > +CONFIG_BMP_32BPP=y > CONFIG_WDT=y > CONFIG_WDT_CDNS=y > CONFIG_PANIC_HANG=y > -- > 2.30.0
[PATCH 0/7] zynqmp_gqspi driver updates
This patch series updates xilinx qspi driver with below fixes/enhancements - Fix rounding off issue in DMA transfers - Fix DMA transfers to be word aligned - Add support for IO mode - Fix write issues in QSPI single mode - Fix zynqmp tapdelays - Add Versal tapdelays - Update tapdelay for >100Mhz for Versal This is resend for the people in CC, as i had trouble with my email server earlier. Ashok Reddy Soma (3): spi: zynqmp_gqspi: Add support for IO mode spi: zynqmp_gqspi: Fix write issues in single mode spi: zynqmp_gqspi: Add tap delays for Versal qspi Siva Durga Prasad Paladugu (1): spi: zynqmp_gqspi: Fix tap delay values T Karthik Reddy (1): spi: zynqmp_gqspi: Update tapdelay value Wojciech Tatarski (2): spi: zynqmp_gqspi: do not round immediate_data field spi: zynqmp_gqspi: DMA transfers should be word aligned drivers/spi/zynqmp_gqspi.c | 230 + 1 file changed, 180 insertions(+), 50 deletions(-) -- 2.17.1 This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.
[PATCH 2/7] spi: zynqmp_gqspi: DMA transfers should be word aligned
From: Wojciech Tatarski
According to Zynq Ultrascale TRM all the data transfers are word aligned.
So there is no reason to round up size of DMA transfer to ARCH_DMA_MINALIGN
(0x40)
Signed-off-by: Wojciech Tatarski
Signed-off-by: Tomasz Gorochowik
Tested-by: Siva Durga Prasad Paladugu
Signed-off-by: Ashok Reddy Soma
---
drivers/spi/zynqmp_gqspi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index 3e0dbb2c7b..81c5e2b22f 100644
--- a/drivers/spi/zynqmp_gqspi.c
+++ b/drivers/spi/zynqmp_gqspi.c
@@ -530,10 +530,10 @@ static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv
*priv,
struct zynqmp_qspi_dma_regs *dma_regs = priv->dma_regs;
writel((unsigned long)buf, &dma_regs->dmadst);
- writel(roundup(priv->len, ARCH_DMA_MINALIGN), &dma_regs->dmasize);
+ writel(roundup(priv->len, GQSPI_DMA_ALIGN), &dma_regs->dmasize);
writel(GQSPI_DMA_DST_I_STS_MASK, &dma_regs->dmaier);
addr = (unsigned long)buf;
- size = roundup(priv->len, ARCH_DMA_MINALIGN);
+ size = roundup(priv->len, GQSPI_DMA_ALIGN);
flush_dcache_range(addr, addr + size);
while (priv->len) {
--
2.17.1
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recipient(s) and contain(s) confidential information that may be proprietary,
privileged or copyrighted under applicable law. If you are not the intended
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Delete this email message and any attachments immediately.
[PATCH 3/7] spi: zynqmp_gqspi: Add support for IO mode
Add support for device tree "has-io-mode" flag.
The driver will be in IO mode when "has-io-mode" is passed from device
tree instead of DMA.
Signed-off-by: Ashok Reddy Soma
---
drivers/spi/zynqmp_gqspi.c | 140 -
1 file changed, 123 insertions(+), 17 deletions(-)
diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index 81c5e2b22f..ae7b70aa57 100644
--- a/drivers/spi/zynqmp_gqspi.c
+++ b/drivers/spi/zynqmp_gqspi.c
@@ -16,11 +16,13 @@
#include
#include
#include
+#include
#include
#include
#include
-#include
-#include
+#include
+#include "../mtd/spi/sf_internal.h"
+#include
#define GQSPI_GFIFO_STRT_MODE_MASK BIT(29)
#define GQSPI_CONFIG_MODE_EN_MASK (3 << 30)
@@ -38,6 +40,7 @@
#define GQSPI_IXR_TXFULL_MASK 0x0008 /* QSPI TX FIFO is full */
#define GQSPI_IXR_RXNEMTY_MASK 0x0010 /* QSPI RX FIFO Not Empty */
#define GQSPI_IXR_GFEMTY_MASK 0x0080 /* QSPI Generic FIFO Empty */
+#define GQSPI_IXR_GFNFULL_MASK 0x0200 /* QSPI GENFIFO not full */
#define GQSPI_IXR_ALL_MASK (GQSPI_IXR_TXNFULL_MASK | \
GQSPI_IXR_RXNEMTY_MASK)
@@ -75,6 +78,7 @@
#define GQSPI_GFIFO_SELECT BIT(0)
#define GQSPI_FIFO_THRESHOLD 1
+#define GQSPI_GENFIFO_THRESHOLD31
#define SPI_XFER_ON_BOTH 0
#define SPI_XFER_ON_LOWER 1
@@ -161,6 +165,7 @@ struct zynqmp_qspi_plat {
struct zynqmp_qspi_dma_regs *dma_regs;
u32 frequency;
u32 speed_hz;
+ unsigned int io_mode;
};
struct zynqmp_qspi_priv {
@@ -173,8 +178,11 @@ struct zynqmp_qspi_priv {
int bytes_to_receive;
unsigned int is_inst;
unsigned int cs_change:1;
+ unsigned int io_mode;
};
+static u8 last_cmd;
+
static int zynqmp_qspi_of_to_plat(struct udevice *bus)
{
struct zynqmp_qspi_plat *plat = dev_get_plat(bus);
@@ -186,6 +194,7 @@ static int zynqmp_qspi_of_to_plat(struct udevice *bus)
plat->dma_regs = (struct zynqmp_qspi_dma_regs *)
(dev_read_addr(bus) + GQSPI_DMA_REG_OFFSET);
+ plat->io_mode = dev_read_bool(bus, "has-io-mode");
return 0;
}
@@ -198,14 +207,20 @@ static void zynqmp_qspi_init_hw(struct zynqmp_qspi_priv
*priv)
writel(GQSPI_GFIFO_ALL_INT_MASK, ®s->idisr);
writel(GQSPI_FIFO_THRESHOLD, ®s->txftr);
writel(GQSPI_FIFO_THRESHOLD, ®s->rxftr);
+ writel(GQSPI_GENFIFO_THRESHOLD, ®s->gqfthr);
writel(GQSPI_GFIFO_ALL_INT_MASK, ®s->isr);
+ writel(0x0, ®s->enbr);
config_reg = readl(®s->confr);
- config_reg &= ~(GQSPI_GFIFO_STRT_MODE_MASK |
- GQSPI_CONFIG_MODE_EN_MASK);
- config_reg |= GQSPI_CONFIG_DMA_MODE |
- GQSPI_GFIFO_WP_HOLD |
- GQSPI_DFLT_BAUD_RATE_DIV;
+ config_reg &= ~(GQSPI_CONFIG_MODE_EN_MASK);
+ config_reg |= GQSPI_GFIFO_WP_HOLD | GQSPI_DFLT_BAUD_RATE_DIV;
+ if (priv->io_mode) {
+ config_reg |= GQSPI_GFIFO_STRT_MODE_MASK;
+ } else {
+ config_reg &= ~(GQSPI_GFIFO_STRT_MODE_MASK);
+ config_reg |= GQSPI_CONFIG_DMA_MODE;
+ }
+
writel(config_reg, ®s->confr);
writel(GQSPI_ENABLE_ENABLE_MASK, ®s->enbr);
@@ -215,8 +230,7 @@ static u32 zynqmp_qspi_bus_select(struct zynqmp_qspi_priv
*priv)
{
u32 gqspi_fifo_reg = 0;
- gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS |
-GQSPI_GFIFO_CS_LOWER;
+ gqspi_fifo_reg = GQSPI_GFIFO_LOW_BUS | GQSPI_GFIFO_CS_LOWER;
return gqspi_fifo_reg;
}
@@ -227,6 +241,7 @@ static void zynqmp_qspi_fill_gen_fifo(struct
zynqmp_qspi_priv *priv,
struct zynqmp_qspi_regs *regs = priv->regs;
int ret = 0;
+ /* Wait until the fifo is not full to write the new command */
ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_GFEMTY_MASK, 1,
GQSPI_TIMEOUT, 1);
if (ret)
@@ -343,6 +358,7 @@ static int zynqmp_qspi_probe(struct udevice *bus)
priv->regs = plat->regs;
priv->dma_regs = plat->dma_regs;
+ priv->io_mode = plat->io_mode;
ret = clk_get_by_index(bus, 0, &clk);
if (ret < 0) {
@@ -363,7 +379,7 @@ static int zynqmp_qspi_probe(struct udevice *bus)
return ret;
}
plat->frequency = clock;
- plat->speed_hz = plat->frequency / 2;
+ plat->speed_hz = plat->frequency;
/* init the zynq spi hw */
zynqmp_qspi_init_hw(priv);
@@ -395,7 +411,7 @@ static int zynqmp_qspi_set_mode(struct udevice *bus, uint
mode)
static int zynqmp_qspi_fill_tx_fifo(struct zynqmp_qspi_priv *priv, u32 size)
{
- u32 data;
+ u32 data, config_reg, ier;
[PATCH 1/7] spi: zynqmp_gqspi: do not round immediate_data field
From: Wojciech Tatarski
Immediate_data is 8 bit value in generic FIFO command. When fields
data_xfer=1 and exponent=0 this field specifies the absolute number of data
bytes to read into the RXFIFO. Values from range 0xfd to 0xff are rounded
up to 0x100. It causes overwriting the next bit field which is data_xfer.
According to Zynq Ultrascale TRM only DMA transfers should be word aligned.
So there is no reason to round up the immediate_data field.
Signed-off-by: Wojciech Tatarski
Signed-off-by: Tomasz Gorochowik
Tested-by: Siva Durga Prasad Paladugu
Signed-off-by: Ashok Reddy Soma
---
drivers/spi/zynqmp_gqspi.c | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index efcbd0557f..3e0dbb2c7b 100644
--- a/drivers/spi/zynqmp_gqspi.c
+++ b/drivers/spi/zynqmp_gqspi.c
@@ -524,7 +524,7 @@ static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv
*priv,
u32 gen_fifo_cmd, u32 *buf)
{
u32 addr;
- u32 size, len;
+ u32 size;
u32 actuallen = priv->len;
int ret = 0;
struct zynqmp_qspi_dma_regs *dma_regs = priv->dma_regs;
@@ -537,12 +537,7 @@ static int zynqmp_qspi_start_dma(struct zynqmp_qspi_priv
*priv,
flush_dcache_range(addr, addr + size);
while (priv->len) {
- len = zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
- if (!(gen_fifo_cmd & GQSPI_GFIFO_EXP_MASK) &&
- (len % ARCH_DMA_MINALIGN)) {
- gen_fifo_cmd &= ~GENMASK(7, 0);
- gen_fifo_cmd |= roundup(len, ARCH_DMA_MINALIGN);
- }
+ zynqmp_qspi_calc_exp(priv, &gen_fifo_cmd);
zynqmp_qspi_fill_gen_fifo(priv, gen_fifo_cmd);
debug("GFIFO_CMD_RX:0x%x\n", gen_fifo_cmd);
--
2.17.1
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recipient(s) and contain(s) confidential information that may be proprietary,
privileged or copyrighted under applicable law. If you are not the intended
recipient, do not read, copy, or forward this email message or any attachments.
Delete this email message and any attachments immediately.
[PATCH 4/7] spi: zynqmp_gqspi: Fix tap delay values
From: Siva Durga Prasad Paladugu
There is no need of read modify write for tapdelay settings
ans hence remove the read operations while setting tapdelays.
Also, correct tapdelay value settings at 40MHZ by modifying
the if check to <= instead of <.
Signed-off-by: Siva Durga Prasad Paladugu
Signed-off-by: Ashok Reddy Soma
---
drivers/spi/zynqmp_gqspi.c | 27 +++
1 file changed, 11 insertions(+), 16 deletions(-)
diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index ae7b70aa57..136c20f09e 100644
--- a/drivers/spi/zynqmp_gqspi.c
+++ b/drivers/spi/zynqmp_gqspi.c
@@ -282,24 +282,19 @@ void zynqmp_qspi_set_tapdelay(struct udevice *bus, u32
baudrateval)
debug("%s, req_hz:%d, clk_rate:%d, baudrateval:%d\n",
__func__, reqhz, clk_rate, baudrateval);
- if (reqhz < GQSPI_FREQ_40MHZ) {
- zynqmp_mmio_read(IOU_TAPDLY_BYPASS_OFST, &tapdlybypass);
- tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
- TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
+ if (reqhz <= GQSPI_FREQ_40MHZ) {
+ tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
+ TAP_DLY_BYPASS_LQSPI_RX_SHIFT;
} else if (reqhz <= GQSPI_FREQ_100MHZ) {
- zynqmp_mmio_read(IOU_TAPDLY_BYPASS_OFST, &tapdlybypass);
- tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
- TAP_DLY_BYPASS_LQSPI_RX_SHIFT);
- lpbkdlyadj = readl(®s->lpbkdly);
- lpbkdlyadj |= (GQSPI_LPBK_DLY_ADJ_LPBK_MASK);
- datadlyadj = readl(®s->gqspidlyadj);
- datadlyadj |= ((GQSPI_USE_DATA_DLY << GQSPI_USE_DATA_DLY_SHIFT)
- | (GQSPI_DATA_DLY_ADJ_VALUE <<
- GQSPI_DATA_DLY_ADJ_SHIFT));
+ tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
+ TAP_DLY_BYPASS_LQSPI_RX_SHIFT;
+ lpbkdlyadj = GQSPI_LPBK_DLY_ADJ_LPBK_MASK;
+ datadlyadj = (GQSPI_USE_DATA_DLY << GQSPI_USE_DATA_DLY_SHIFT) |
+ (GQSPI_DATA_DLY_ADJ_VALUE <<
+ GQSPI_DATA_DLY_ADJ_SHIFT);
} else if (reqhz <= GQSPI_FREQ_150MHZ) {
- lpbkdlyadj = readl(®s->lpbkdly);
- lpbkdlyadj |= ((GQSPI_LPBK_DLY_ADJ_LPBK_MASK) |
- GQSPI_LPBK_DLY_ADJ_DLY_0);
+ lpbkdlyadj = GQSPI_LPBK_DLY_ADJ_LPBK_MASK |
+ GQSPI_LPBK_DLY_ADJ_DLY_0;
}
zynqmp_mmio_write(IOU_TAPDLY_BYPASS_OFST, IOU_TAPDLY_BYPASS_MASK,
--
2.17.1
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recipient(s) and contain(s) confidential information that may be proprietary,
privileged or copyrighted under applicable law. If you are not the intended
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[PATCH 5/7] spi: zynqmp_gqspi: Fix write issues in single mode
Add dummy write to genfifo register in chipselect.
Enable manual start in zynqmp_qspi_fill_gen_fifo().
Also enable GQSPI_IXR_GFNFULL_MASK and check for it instead of
GQSPI_IXR_GFEMTY_MASK.
Signed-off-by: Ashok Reddy Soma
---
drivers/spi/zynqmp_gqspi.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index 136c20f09e..f50a7304ea 100644
--- a/drivers/spi/zynqmp_gqspi.c
+++ b/drivers/spi/zynqmp_gqspi.c
@@ -239,10 +239,21 @@ static void zynqmp_qspi_fill_gen_fifo(struct
zynqmp_qspi_priv *priv,
u32 gqspi_fifo_reg)
{
struct zynqmp_qspi_regs *regs = priv->regs;
+ u32 config_reg, ier;
int ret = 0;
+ config_reg = readl(®s->confr);
+ /* Manual start if needed */
+ config_reg |= GQSPI_STRT_GEN_FIFO;
+ writel(config_reg, ®s->confr);
+
+ /* Enable interrupts */
+ ier = readl(®s->ier);
+ ier |= GQSPI_IXR_GFNFULL_MASK;
+ writel(ier, ®s->ier);
+
/* Wait until the fifo is not full to write the new command */
- ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_GFEMTY_MASK, 1,
+ ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_GFNFULL_MASK, 1,
GQSPI_TIMEOUT, 1);
if (ret)
printf("%s Timeout\n", __func__);
@@ -265,6 +276,9 @@ static void zynqmp_qspi_chipselect(struct zynqmp_qspi_priv
*priv, int is_on)
debug("GFIFO_CMD_CS: 0x%x\n", gqspi_fifo_reg);
+ /* Dummy generic FIFO entry */
+ zynqmp_qspi_fill_gen_fifo(priv, 0);
+
zynqmp_qspi_fill_gen_fifo(priv, gqspi_fifo_reg);
}
--
2.17.1
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recipient(s) and contain(s) confidential information that may be proprietary,
privileged or copyrighted under applicable law. If you are not the intended
recipient, do not read, copy, or forward this email message or any attachments.
Delete this email message and any attachments immediately.
[PATCH 6/7] spi: zynqmp_gqspi: Add tap delays for Versal qspi
This patch adds tap delays for qspi in Versal platform.
Use IS_ENABLED() to address for ZynqMP and Versal and re-align the
tapdelays code.
Signed-off-by: Ashok Reddy Soma
---
drivers/spi/zynqmp_gqspi.c | 54 ++
1 file changed, 37 insertions(+), 17 deletions(-)
diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index f50a7304ea..e9726912b7 100644
--- a/drivers/spi/zynqmp_gqspi.c
+++ b/drivers/spi/zynqmp_gqspi.c
@@ -102,8 +102,10 @@
#define TAP_DLY_BYPASS_LQSPI_RX_VALUE 0x1
#define TAP_DLY_BYPASS_LQSPI_RX_SHIFT 2
#define GQSPI_DATA_DLY_ADJ_OFST0x01F8
-#define IOU_TAPDLY_BYPASS_OFST 0xFF180390
+#define IOU_TAPDLY_BYPASS_OFST !IS_ENABLED(CONFIG_ARCH_VERSAL) ? \
+ 0xFF180390 : 0xF103003C
#define GQSPI_LPBK_DLY_ADJ_LPBK_MASK 0x0020
+#define GQSPI_FREQ_37_5MHZ 3750
#define GQSPI_FREQ_40MHZ 4000
#define GQSPI_FREQ_100MHZ 1
#define GQSPI_FREQ_150MHZ 15000
@@ -296,23 +298,41 @@ void zynqmp_qspi_set_tapdelay(struct udevice *bus, u32
baudrateval)
debug("%s, req_hz:%d, clk_rate:%d, baudrateval:%d\n",
__func__, reqhz, clk_rate, baudrateval);
- if (reqhz <= GQSPI_FREQ_40MHZ) {
- tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
- TAP_DLY_BYPASS_LQSPI_RX_SHIFT;
- } else if (reqhz <= GQSPI_FREQ_100MHZ) {
- tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
- TAP_DLY_BYPASS_LQSPI_RX_SHIFT;
- lpbkdlyadj = GQSPI_LPBK_DLY_ADJ_LPBK_MASK;
- datadlyadj = (GQSPI_USE_DATA_DLY << GQSPI_USE_DATA_DLY_SHIFT) |
- (GQSPI_DATA_DLY_ADJ_VALUE <<
- GQSPI_DATA_DLY_ADJ_SHIFT);
- } else if (reqhz <= GQSPI_FREQ_150MHZ) {
- lpbkdlyadj = GQSPI_LPBK_DLY_ADJ_LPBK_MASK |
- GQSPI_LPBK_DLY_ADJ_DLY_0;
+ if (!IS_ENABLED(CONFIG_ARCH_VERSAL)) {
+ if (reqhz <= GQSPI_FREQ_40MHZ) {
+ tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
+ TAP_DLY_BYPASS_LQSPI_RX_SHIFT;
+ } else if (reqhz <= GQSPI_FREQ_100MHZ) {
+ tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
+ TAP_DLY_BYPASS_LQSPI_RX_SHIFT;
+ lpbkdlyadj = GQSPI_LPBK_DLY_ADJ_LPBK_MASK;
+ datadlyadj = (GQSPI_USE_DATA_DLY <<
+ GQSPI_USE_DATA_DLY_SHIFT) |
+ (GQSPI_DATA_DLY_ADJ_VALUE <<
+ GQSPI_DATA_DLY_ADJ_SHIFT);
+ } else if (reqhz <= GQSPI_FREQ_150MHZ) {
+ lpbkdlyadj = GQSPI_LPBK_DLY_ADJ_LPBK_MASK |
+ GQSPI_LPBK_DLY_ADJ_DLY_0;
+ }
+ zynqmp_mmio_write(IOU_TAPDLY_BYPASS_OFST,
+ IOU_TAPDLY_BYPASS_MASK, tapdlybypass);
+ } else {
+ if (reqhz <= GQSPI_FREQ_37_5MHZ) {
+ tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
+ TAP_DLY_BYPASS_LQSPI_RX_SHIFT;
+ } else if (reqhz <= GQSPI_FREQ_100MHZ) {
+ tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE <<
+ TAP_DLY_BYPASS_LQSPI_RX_SHIFT;
+ lpbkdlyadj = GQSPI_LPBK_DLY_ADJ_LPBK_MASK;
+ datadlyadj = GQSPI_USE_DATA_DLY <<
+ GQSPI_USE_DATA_DLY_SHIFT;
+ } else if (reqhz <= GQSPI_FREQ_150MHZ) {
+ lpbkdlyadj = GQSPI_LPBK_DLY_ADJ_LPBK_MASK |
+ (GQSPI_LPBK_DLY_ADJ_DLY_1 <<
+ GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT);
+ }
+ writel(tapdlybypass, IOU_TAPDLY_BYPASS_OFST);
}
-
- zynqmp_mmio_write(IOU_TAPDLY_BYPASS_OFST, IOU_TAPDLY_BYPASS_MASK,
- tapdlybypass);
writel(lpbkdlyadj, ®s->lpbkdly);
writel(datadlyadj, ®s->gqspidlyadj);
}
--
2.17.1
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recipient(s) and contain(s) confidential information that may be proprietary,
privileged or copyrighted under applicable law. If you are not the intended
recipient, do not read, copy, or forward this email message or any attachments.
Delete this email message and any attachments immediately.
[PATCH 7/7] spi: zynqmp_gqspi: Update tapdelay value
From: T Karthik Reddy Update GQSPI_LPBK_DLY_ADJ_DLY_1 tapdelay value for Versal for frequencies above 100MHz. Signed-off-by: T Karthik Reddy Signed-off-by: Ashok Reddy Soma --- drivers/spi/zynqmp_gqspi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index e9726912b7..0771541e12 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -92,7 +92,7 @@ #define GQSPI_BAUD_DIV_SHIFT 2 #define GQSPI_LPBK_DLY_ADJ_LPBK_SHIFT 5 -#define GQSPI_LPBK_DLY_ADJ_DLY_1 0x2 +#define GQSPI_LPBK_DLY_ADJ_DLY_1 0x1 #define GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT 3 #define GQSPI_LPBK_DLY_ADJ_DLY_0 0x3 #define GQSPI_USE_DATA_DLY 0x1 -- 2.17.1 This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.
RE: [PATCH] net: gem: Fix setting PCS auto-negotiation statee
Reviewed-by: Ashok Reddy Soma
> -Original Message-
> From: Michal Simek
> Sent: Monday, March 15, 2021 2:38 PM
> To: Robert Hancock ; Michal Simek
> ; T Karthik Reddy ; Ashok Reddy
> Soma
> Cc: joe.hershber...@ni.com; rfried@gmail.com; u-boot@lists.denx.de
> Subject: Re: [PATCH] net: gem: Fix setting PCS auto-negotiation statee
>
>
>
> On 3/11/21 11:55 PM, Robert Hancock wrote:
> > The code was trying to disable PCS auto-negotiation when a fixed-link
> > node is present and enable it otherwise. However, the PCS registers
> > were being written before the PCSSEL bit was set in the network
> > configuration register, and it appears that in this state, PCS
> > register writes are ignored. The result is that the intended change
> > only took effect on the second network operation that was performed,
> > since at that time PCSSEL is already enabled.
> >
> > Fix the order of register writes so that PCS registers are only
> > written to after the PCS is enabled.
> >
> > Fixes: 26e62cc971 ("net: gem: Disable PCS autonegotiation in case of
> > fixed-link")
> >
> > Signed-off-by: Robert Hancock
> > ---
> > drivers/net/zynq_gem.c | 25 +
> > 1 file changed, 17 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index
> > baf06a2ad8..ff59982267 100644
> > --- a/drivers/net/zynq_gem.c
> > +++ b/drivers/net/zynq_gem.c
> > @@ -454,14 +454,6 @@ static int zynq_gem_init(struct udevice *dev)
> > priv->int_pcs) {
> > nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL |
> > ZYNQ_GEM_NWCFG_PCS_SEL;
> > -#ifdef CONFIG_ARM64
> > - if (priv->phydev->phy_id != PHY_FIXED_ID)
> > - writel(readl(®s->pcscntrl) |
> ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
> > - ®s->pcscntrl);
> > - else
> > - writel(readl(®s->pcscntrl) &
> ~ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
> > - ®s->pcscntrl);
> > -#endif
> > }
> >
> > switch (priv->phydev->speed) {
> > @@ -480,6 +472,23 @@ static int zynq_gem_init(struct udevice *dev)
> > break;
> > }
> >
> > +#ifdef CONFIG_ARM64
> > + if (priv->interface == PHY_INTERFACE_MODE_SGMII &&
> > + priv->int_pcs) {
> > + /*
> > +* Disable AN for fixed link configuration, enable otherwise.
> > +* Must be written after PCS_SEL is set in nwconfig,
> > +* otherwise writes will not take effect.
> > +*/
> > + if (priv->phydev->phy_id != PHY_FIXED_ID)
> > + writel(readl(®s->pcscntrl) |
> ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
> > + ®s->pcscntrl);
> > + else
> > + writel(readl(®s->pcscntrl) &
> ~ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
> > + ®s->pcscntrl);
> > + }
> > +#endif
> > +
> > ret = clk_set_rate(&priv->tx_clk, clk_rate);
> > if (IS_ERR_VALUE(ret)) {
> > dev_err(dev, "failed to set tx clock rate\n");
> >
>
> Karthik/Ashok: Please retest it and reply.
Looks good.
>
> Thanks,
> Michal
[PATCH] spi: zynqmp_gqspi: Fix write issue
Enable manual start in zynqmp_qspi_fill_gen_fifo().
Also enable GQSPI_IXR_GFNFULL_MASK and check for it instead of
GQSPI_IXR_GFEMTY_MASK.
Add dummy write to genfifo register in chipselect.
Signed-off-by: Ashok Reddy Soma
---
drivers/spi/zynqmp_gqspi.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index 17780066ae..fc81b07343 100644
--- a/drivers/spi/zynqmp_gqspi.c
+++ b/drivers/spi/zynqmp_gqspi.c
@@ -39,6 +39,7 @@
#define GQSPI_IXR_TXFULL_MASK 0x0008 /* QSPI TX FIFO is full */
#define GQSPI_IXR_RXNEMTY_MASK 0x0010 /* QSPI RX FIFO Not Empty */
#define GQSPI_IXR_GFEMTY_MASK 0x0080 /* QSPI Generic FIFO Empty */
+#define GQSPI_IXR_GFNFULL_MASK 0x0200 /* QSPI GENFIFO not full */
#define GQSPI_IXR_ALL_MASK (GQSPI_IXR_TXNFULL_MASK | \
GQSPI_IXR_RXNEMTY_MASK)
@@ -238,9 +239,21 @@ static void zynqmp_qspi_fill_gen_fifo(struct
zynqmp_qspi_priv *priv,
u32 gqspi_fifo_reg)
{
struct zynqmp_qspi_regs *regs = priv->regs;
+ u32 config_reg, ier;
int ret = 0;
- ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_GFEMTY_MASK, 1,
+ config_reg = readl(®s->confr);
+ /* Manual start if needed */
+ config_reg |= GQSPI_STRT_GEN_FIFO;
+ writel(config_reg, ®s->confr);
+
+ /* Enable interrupts */
+ ier = readl(®s->ier);
+ ier |= GQSPI_IXR_GFNFULL_MASK;
+ writel(ier, ®s->ier);
+
+ /* Wait until the fifo is not full to write the new command */
+ ret = wait_for_bit_le32(®s->isr, GQSPI_IXR_GFNFULL_MASK, 1,
GQSPI_TIMEOUT, 1);
if (ret)
printf("%s Timeout\n", __func__);
@@ -263,6 +276,9 @@ static void zynqmp_qspi_chipselect(struct zynqmp_qspi_priv
*priv, int is_on)
debug("GFIFO_CMD_CS: 0x%x\n", gqspi_fifo_reg);
+ /* Dummy generic FIFO entry */
+ zynqmp_qspi_fill_gen_fifo(priv, 0);
+
zynqmp_qspi_fill_gen_fifo(priv, gqspi_fifo_reg);
}
--
2.17.1
[PATCH 0/2] Add support for 10G/25G to AXI emac driver
- Cleanup of_to_plat() to access platform data only in it - Copy plat data to priv data in probe function - Add support for 10G/25G to the AXI emac driver - Keep all phy related activity in the driver for 1G only Ashok Reddy Soma (2): net: xilinx: axi_emac: Cleanup of of_to_plat() net: xilinx: axi_emac: Add support for 10G/25G AXI ethernet drivers/net/xilinx_axi_emac.c | 193 +- 1 file changed, 142 insertions(+), 51 deletions(-) -- 2.17.1
[PATCH 1/2] net: xilinx: axi_emac: Cleanup of of_to_plat()
There are lot of accesses to priv data in of_to_plat(), which is incorrect.
Create a platform data structure and use it in of_to_plat(), then copy all
platform data to priv data in probe.
Signed-off-by: Ashok Reddy Soma
---
drivers/net/xilinx_axi_emac.c | 47 ---
1 file changed, 32 insertions(+), 15 deletions(-)
diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
index 2ce6271afe..cfc6082475 100644
--- a/drivers/net/xilinx_axi_emac.c
+++ b/drivers/net/xilinx_axi_emac.c
@@ -87,6 +87,16 @@ struct axidma_reg {
u32 tail_hi; /* TAILDESC high 32 bit */
};
+/* Platform data structures */
+struct axidma_plat {
+ struct eth_pdata eth_pdata;
+ struct axidma_reg *dmatx;
+ struct axidma_reg *dmarx;
+ int phyaddr;
+ u8 eth_hasnobuf;
+ int phy_of_handle;
+};
+
/* Private driver structures */
struct axidma_priv {
struct axidma_reg *dmatx;
@@ -690,9 +700,20 @@ static int axiemac_miiphy_write(struct mii_dev *bus, int
addr, int devad,
static int axi_emac_probe(struct udevice *dev)
{
+ struct axidma_plat *plat = dev_get_plat(dev);
+ struct eth_pdata *pdata = &plat->eth_pdata;
struct axidma_priv *priv = dev_get_priv(dev);
int ret;
+ priv->iobase = (struct axi_regs *)pdata->iobase;
+ priv->dmatx = plat->dmatx;
+ /* RX channel offset is 0x30 */
+ priv->dmarx = (struct axidma_reg *)((phys_addr_t)priv->dmatx + 0x30);
+ priv->eth_hasnobuf = plat->eth_hasnobuf;
+ priv->phyaddr = plat->phyaddr;
+ priv->phy_of_handle = plat->phy_of_handle;
+ priv->interface = pdata->phy_interface;
+
priv->bus = mdio_alloc();
priv->bus->read = axiemac_miiphy_read;
priv->bus->write = axiemac_miiphy_write;
@@ -729,14 +750,13 @@ static const struct eth_ops axi_emac_ops = {
static int axi_emac_of_to_plat(struct udevice *dev)
{
- struct eth_pdata *pdata = dev_get_plat(dev);
- struct axidma_priv *priv = dev_get_priv(dev);
+ struct axidma_plat *plat = dev_get_plat(dev);
+ struct eth_pdata *pdata = &plat->eth_pdata;
int node = dev_of_offset(dev);
int offset = 0;
const char *phy_mode;
pdata->iobase = dev_read_addr(dev);
- priv->iobase = (struct axi_regs *)pdata->iobase;
offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
"axistream-connected");
@@ -744,21 +764,19 @@ static int axi_emac_of_to_plat(struct udevice *dev)
printf("%s: axistream is not found\n", __func__);
return -EINVAL;
}
- priv->dmatx = (struct axidma_reg *)fdtdec_get_addr(gd->fdt_blob,
+ plat->dmatx = (struct axidma_reg *)fdtdec_get_addr(gd->fdt_blob,
offset, "reg");
- if (!priv->dmatx) {
+ if (!plat->dmatx) {
printf("%s: axi_dma register space not found\n", __func__);
return -EINVAL;
}
- /* RX channel offset is 0x30 */
- priv->dmarx = (struct axidma_reg *)((phys_addr_t)priv->dmatx + 0x30);
- priv->phyaddr = -1;
+ plat->phyaddr = -1;
offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
if (offset > 0) {
- priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
- priv->phy_of_handle = offset;
+ plat->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
+ plat->phy_of_handle = offset;
}
phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
@@ -768,13 +786,12 @@ static int axi_emac_of_to_plat(struct udevice *dev)
printf("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
return -EINVAL;
}
- priv->interface = pdata->phy_interface;
- priv->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node,
+ plat->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node,
"xlnx,eth-hasnobuf");
- printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase,
- priv->phyaddr, phy_string_for_interface(priv->interface));
+ printf("AXI EMAC: %lx, phyaddr %d, interface %s\n",
(ulong)pdata->iobase,
+ plat->phyaddr, phy_string_for_interface(pdata->phy_interface));
return 0;
}
@@ -793,5 +810,5 @@ U_BOOT_DRIVER(axi_emac) = {
.remove = axi_emac_remove,
.ops= &axi_emac_ops,
.priv_auto = sizeof(struct axidma_priv),
- .plat_auto = sizeof(struct eth_pdata),
+ .plat_auto = sizeof(struct axidma_plat),
};
--
2.17.1
[PATCH 2/2] net: xilinx: axi_emac: Add support for 10G/25G AXI ethernet
Add support for 10G/25G (XXV) high speed ethernet. This Makes use of
the exiting AXI DMA, similar to 1G.
Signed-off-by: Alessandro Temil
Signed-off-by: Ashok Reddy Soma
---
drivers/net/xilinx_axi_emac.c | 162 +-
1 file changed, 118 insertions(+), 44 deletions(-)
diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
index cfc6082475..2ec76d0f52 100644
--- a/drivers/net/xilinx_axi_emac.c
+++ b/drivers/net/xilinx_axi_emac.c
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
+ * Copyright (C) 2021 Waymo LLC
* Copyright (C) 2011 Michal Simek
* Copyright (C) 2011 PetaLogix
* Copyright (C) 2010 Xilinx, Inc. All rights reserved.
@@ -73,9 +74,22 @@ DECLARE_GLOBAL_DATA_PTR;
#define XAXIDMA_BD_CTRL_TXSOF_MASK 0x0800 /* First tx packet */
#define XAXIDMA_BD_CTRL_TXEOF_MASK 0x0400 /* Last tx packet */
-#define DMAALIGN 128
+/* Bitmasks for XXV Ethernet MAC */
+#define XXV_TC_TX_MASK 0x0001
+#define XXV_TC_FCS_MASK0x0002
+#define XXV_RCW1_RX_MASK 0x0001
+#define XXV_RCW1_FCS_MASK 0x0002
+
+#define DMAALIGN 128
+#define XXV_MIN_PKT_SIZE 60
static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN)));
+static u8 txminframe[XXV_MIN_PKT_SIZE] __attribute((aligned(DMAALIGN)));
+
+enum emac_variant {
+ EMAC_1G = 0,
+ EMAC_10G_25G = 1,
+};
/* Reflect dma offsets */
struct axidma_reg {
@@ -95,6 +109,7 @@ struct axidma_plat {
int phyaddr;
u8 eth_hasnobuf;
int phy_of_handle;
+ enum emac_variant mactype;
};
/* Private driver structures */
@@ -108,6 +123,7 @@ struct axidma_priv {
struct mii_dev *bus;
u8 eth_hasnobuf;
int phy_of_handle;
+ enum emac_variant mactype;
};
/* BD descriptors */
@@ -154,6 +170,14 @@ struct axi_regs {
u32 uaw1; /* 0x704: Unicast address word 1 */
};
+struct xxv_axi_regs {
+ u32 gt_reset; /* 0x0 */
+ u32 reserved[2];
+ u32 tc; /* 0xC: Tx Configuration */
+ u32 reserved2;
+ u32 rcw1; /* 0x14: Rx Configuration Word 1 */
+};
+
/* Use MII register 1 (MII status register) to detect PHY */
#define PHY_DETECT_REG 1
@@ -385,6 +409,18 @@ static void axiemac_stop(struct udevice *dev)
debug("axiemac: Halted\n");
}
+static int xxv_axi_ethernet_init(struct axidma_priv *priv)
+{
+ struct xxv_axi_regs *regs = (struct xxv_axi_regs *)priv->iobase;
+
+ writel(readl(®s->rcw1) | XXV_RCW1_FCS_MASK, ®s->rcw1);
+ writel(readl(®s->tc) | XXV_TC_FCS_MASK, ®s->tc);
+ writel(readl(®s->tc) | XXV_TC_TX_MASK, ®s->tc);
+ writel(readl(®s->rcw1) | XXV_RCW1_RX_MASK, ®s->rcw1);
+
+ return 0;
+}
+
static int axi_ethernet_init(struct axidma_priv *priv)
{
struct axi_regs *regs = priv->iobase;
@@ -440,6 +476,9 @@ static int axiemac_write_hwaddr(struct udevice *dev)
struct axidma_priv *priv = dev_get_priv(dev);
struct axi_regs *regs = priv->iobase;
+ if (priv->mactype != EMAC_1G)
+ return 0;
+
/* Set the MAC address */
int val = ((pdata->enetaddr[3] << 24) | (pdata->enetaddr[2] << 16) |
(pdata->enetaddr[1] << 8) | (pdata->enetaddr[0]));
@@ -477,7 +516,6 @@ static void axi_dma_init(struct axidma_priv *priv)
static int axiemac_start(struct udevice *dev)
{
struct axidma_priv *priv = dev_get_priv(dev);
- struct axi_regs *regs = priv->iobase;
u32 temp;
debug("axiemac: Init started\n");
@@ -490,8 +528,13 @@ static int axiemac_start(struct udevice *dev)
axi_dma_init(priv);
/* Initialize AxiEthernet hardware. */
- if (axi_ethernet_init(priv))
- return -1;
+ if (priv->mactype == EMAC_1G) {
+ if (axi_ethernet_init(priv))
+ return -1;
+ } else {
+ if (xxv_axi_ethernet_init(priv))
+ return -1;
+ }
/* Disable all RX interrupts before RxBD space setup */
temp = readl(&priv->dmarx->control);
@@ -525,15 +568,25 @@ static int axiemac_start(struct udevice *dev)
/* Rx BD is ready - start */
axienet_dma_write(&rx_bd, &priv->dmarx->tail);
- /* Enable TX */
- writel(XAE_TC_TX_MASK, ®s->tc);
- /* Enable RX */
- writel(XAE_RCW1_RX_MASK, ®s->rcw1);
+ if (priv->mactype == EMAC_1G) {
+ struct axi_regs *regs = priv->iobase;
+ /* Enable TX */
+ writel(XAE_TC_TX_MASK, ®s->tc);
+ /* Enable RX */
+ writel(XAE_RCW1_RX_MASK, ®s->rcw1);
+
+ /* PHY setup */
+ if (!setup_phy(dev)) {
+ axiemac_stop(dev);
+ return -1;
+
[PATCH 1/3] net: ethtool: Add ethernet speed macros for higher speeds
Add speed macro's for higher ethernet speeds to be used in u-boot
networking drivers. Added Macros for speeds 14G, 20G, 25G, 40G, 50G,
56G, 100G and 200G inline with linux.
Signed-off-by: Ashok Reddy Soma
---
include/linux/ethtool.h | 8
1 file changed, 8 insertions(+)
diff --git a/include/linux/ethtool.h b/include/linux/ethtool.h
index f6dbdb096d..aa7d2fd58f 100644
--- a/include/linux/ethtool.h
+++ b/include/linux/ethtool.h
@@ -620,6 +620,14 @@ enum ethtool_sfeatures_retval_bits {
#define SPEED_1000 1000
#define SPEED_2500 2500
#define SPEED_11
+#define SPEED_1400014000
+#define SPEED_22
+#define SPEED_2500025000
+#define SPEED_44
+#define SPEED_55
+#define SPEED_5600056000
+#define SPEED_10 10
+#define SPEED_20 20
/* Duplex, half or full. */
#define DUPLEX_HALF0x00
--
2.17.1
[PATCH 3/3] xilinx: versal: Enable Xilinx AXI MRMAC
Enable Xilinx AXI MRMAC for Versal platforms. Signed-off-by: Ashok Reddy Soma --- configs/xilinx_versal_virt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index f4e9a80728..75feae318e 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -89,6 +89,7 @@ CONFIG_PHY_VITESSE=y CONFIG_PHY_FIXED=y CONFIG_PHY_GIGE=y CONFIG_XILINX_AXIEMAC=y +CONFIG_XILINX_AXIMRMAC=y CONFIG_ZYNQ_GEM=y CONFIG_ARM_DCC=y CONFIG_PL01X_SERIAL=y -- 2.17.1
