from:"Alice Guo \(OSS\)"

[PATCH v1] gpio: adp5585: add gpio driver for ADP5585 I/O Expander Controller

2022-09-06 Thread Alice Guo (OSS)

From: Alice Guo 

Signed-off-by: Alice Guo 
---
 arch/arm/include/asm/arch-imx9/gpio.h |   2 +
 drivers/gpio/Kconfig  |   6 +
 drivers/gpio/Makefile |   1 +
 drivers/gpio/adp5585_gpio.c   | 238 ++
 4 files changed, 247 insertions(+)
 create mode 100644 drivers/gpio/adp5585_gpio.c

diff --git a/arch/arm/include/asm/arch-imx9/gpio.h 
b/arch/arm/include/asm/arch-imx9/gpio.h
index 40732022e7..599f7511c3 100644
--- a/arch/arm/include/asm/arch-imx9/gpio.h
+++ b/arch/arm/include/asm/arch-imx9/gpio.h
@@ -6,6 +6,8 @@
 #ifndef __ASM_ARCH_IMX9_GPIO_H
 #define __ASM_ARCH_IMX9_GPIO_H
 
+#include 
+
 struct gpio_regs {
u32 gpio_pdor;
u32 gpio_psor;
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index c949f9d2f7..550ff9c586 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -605,4 +605,10 @@ config TURRIS_OMNIA_MCU
help
   Support for GPIOs on MCU connected to Turris Omnia via i2c.
 
+config ADP5585_GPIO
+   bool "ADP5585 GPIO driver"
+   depends on DM_GPIO && DM_I2C
+   help
+ Support ADP5585 GPIO expander on i.MX platform.
+
 endif
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 9d718a554e..2f60b98384 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -75,3 +75,4 @@ obj-$(CONFIG_SL28CPLD_GPIO)   += sl28cpld-gpio.o
 obj-$(CONFIG_ZYNQMP_GPIO_MODEPIN)  += zynqmp_gpio_modepin.o
 obj-$(CONFIG_SLG7XL45106_I2C_GPO)  += gpio_slg7xl45106.o
 obj-$(CONFIG_$(SPL_TPL_)TURRIS_OMNIA_MCU)  += turris_omnia_mcu.o
+obj-$(CONFIG_ADP5585_GPIO) += adp5585_gpio.o
diff --git a/drivers/gpio/adp5585_gpio.c b/drivers/gpio/adp5585_gpio.c
new file mode 100644
index 00..ea0cb75459
--- /dev/null
+++ b/drivers/gpio/adp5585_gpio.c
@@ -0,0 +1,238 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ *
+ * ADP5585 I/O Expander Controller
+ *
+ * Author: Alice Guo 
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#define ADP5585_ID 0x00
+#define ADP5585_INT_STATUS 0x01
+#define ADP5585_STATUS 0x02
+#define ADP5585_FIFO_1 0x03
+#define ADP5585_FIFO_2 0x04
+#define ADP5585_FIFO_3 0x05
+#define ADP5585_FIFO_4 0x06
+#define ADP5585_FIFO_5 0x07
+#define ADP5585_FIFO_6 0x08
+#define ADP5585_FIFO_7 0x09
+#define ADP5585_FIFO_8 0x0A
+#define ADP5585_FIFO_9 0x0B
+#define ADP5585_FIFO_100x0C
+#define ADP5585_FIFO_110x0D
+#define ADP5585_FIFO_120x0E
+#define ADP5585_FIFO_130x0F
+#define ADP5585_FIFO_140x10
+#define ADP5585_FIFO_150x11
+#define ADP5585_FIFO_160x12
+#define ADP5585_GPI_INT_STAT_A 0x13
+#define ADP5585_GPI_INT_STAT_B 0x14
+#define ADP5585_GPI_STATUS_A   0x15
+#define ADP5585_GPI_STATUS_B   0x16
+#define ADP5585_RPULL_CONFIG_A 0x17
+#define ADP5585_RPULL_CONFIG_B 0x18
+#define ADP5585_RPULL_CONFIG_C 0x19
+#define ADP5585_RPULL_CONFIG_D 0x1A
+#define ADP5585_GPI_INT_LEVEL_A0x1B
+#define ADP5585_GPI_INT_LEVEL_B0x1C
+#define ADP5585_GPI_EVENT_EN_A 0x1D
+#define ADP5585_GPI_EVENT_EN_B 0x1E
+#define ADP5585_GPI_INTERRUPT_EN_A 0x1F
+#define ADP5585_GPI_INTERRUPT_EN_B 0x20
+#define ADP5585_DEBOUNCE_DIS_A 0x21
+#define ADP5585_DEBOUNCE_DIS_B 0x22
+#define ADP5585_GPO_DATA_OUT_A 0x23
+#define ADP5585_GPO_DATA_OUT_B 0x24
+#define ADP5585_GPO_OUT_MODE_A 0x25
+#define ADP5585_GPO_OUT_MODE_B 0x26
+#define ADP5585_GPIO_DIRECTION_A   0x27
+#define ADP5585_GPIO_DIRECTION_B   0x28
+#define ADP5585_RESET1_EVENT_A 0x29
+#define ADP5585_RESET1_EVENT_B 0x2A
+#define ADP5585_RESET1_EVENT_C 0x2B
+#define ADP5585_RESET2_EVENT_A 0x2C
+#define ADP5585_RESET2_EVENT_B 0x2D
+#define ADP5585_RESET_CFG  0x2E
+#define ADP5585_PWM_OFFT_LOW   0x2F
+#define ADP5585_PWM_OFFT_HIGH  0x30
+#define ADP5585_PWM_ONT_LOW0x31
+#define ADP5585_PWM_ONT_HIGH   0x32
+#define ADP5585_PWM_CFG0x33
+#define ADP5585_LOGIC_CFG  0x34
+#define ADP5585_LOGIC_FF_CFG   0x35
+#define ADP5585_LOGIC_INT_EVENT_EN 0x36
+#define ADP5585_POLL_PTIME_CFG 0x37
+#define ADP5585_PIN_CONFIG_A   0x38
+#define ADP5585_PIN_CONFIG_B   0x39
+#define ADP5585_PIN_CONFIG_D   0x3A
+#define ADP5585_GENERAL_CFG0x3B
+#define ADP5585_INT_EN 0x3C
+
+#define ADP5585_MAXGPIO10
+#define ADP5585_BANK(offs) ((offs) > 4)
+#define ADP5585_BIT(offs)  ((offs) > 4 ? \
+

RE: [PATCH v1] gpio: adp5585: add gpio driver for ADP5585 I/O Expander Controller

2022-09-26 Thread Alice Guo (OSS)

A friendly ping...

Best Regards,
Alice Guo

> -Original Message-
> From: U-Boot  On Behalf Of Alice Guo (OSS)
> Sent: Tuesday, September 6, 2022 5:38 PM
> To: sba...@denx.de; feste...@gmail.com; s...@chromium.org
> Cc: dl-uboot-imx ; u-boot@lists.denx.de
> Subject: [PATCH v1] gpio: adp5585: add gpio driver for ADP5585 I/O Expander
> Controller
> 
> From: Alice Guo 
> 
> Signed-off-by: Alice Guo 
> ---
>  arch/arm/include/asm/arch-imx9/gpio.h |   2 +
>  drivers/gpio/Kconfig  |   6 +
>  drivers/gpio/Makefile |   1 +
>  drivers/gpio/adp5585_gpio.c   | 238
> ++
>  4 files changed, 247 insertions(+)
>  create mode 100644 drivers/gpio/adp5585_gpio.c
> 
> diff --git a/arch/arm/include/asm/arch-imx9/gpio.h
> b/arch/arm/include/asm/arch-imx9/gpio.h
> index 40732022e7..599f7511c3 100644
> --- a/arch/arm/include/asm/arch-imx9/gpio.h
> +++ b/arch/arm/include/asm/arch-imx9/gpio.h
> @@ -6,6 +6,8 @@
>  #ifndef __ASM_ARCH_IMX9_GPIO_H
>  #define __ASM_ARCH_IMX9_GPIO_H
> 
> +#include 
> +
>  struct gpio_regs {
>   u32 gpio_pdor;
>   u32 gpio_psor;
> diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index
> c949f9d2f7..550ff9c586 100644
> --- a/drivers/gpio/Kconfig
> +++ b/drivers/gpio/Kconfig
> @@ -605,4 +605,10 @@ config TURRIS_OMNIA_MCU
>   help
>  Support for GPIOs on MCU connected to Turris Omnia via i2c.
> 
> +config ADP5585_GPIO
> + bool "ADP5585 GPIO driver"
> + depends on DM_GPIO && DM_I2C
> + help
> +   Support ADP5585 GPIO expander on i.MX platform.
> +
>  endif
> diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index
> 9d718a554e..2f60b98384 100644
> --- a/drivers/gpio/Makefile
> +++ b/drivers/gpio/Makefile
> @@ -75,3 +75,4 @@ obj-$(CONFIG_SL28CPLD_GPIO) += sl28cpld-gpio.o
>  obj-$(CONFIG_ZYNQMP_GPIO_MODEPIN)+= zynqmp_gpio_modepin.o
>  obj-$(CONFIG_SLG7XL45106_I2C_GPO)+= gpio_slg7xl45106.o
>  obj-$(CONFIG_$(SPL_TPL_)TURRIS_OMNIA_MCU)+= turris_omnia_mcu.o
> +obj-$(CONFIG_ADP5585_GPIO)   += adp5585_gpio.o
> diff --git a/drivers/gpio/adp5585_gpio.c b/drivers/gpio/adp5585_gpio.c new
> file mode 100644 index 00..ea0cb75459
> --- /dev/null
> +++ b/drivers/gpio/adp5585_gpio.c
> @@ -0,0 +1,238 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2022 NXP
> + *
> + * ADP5585 I/O Expander Controller
> + *
> + * Author: Alice Guo   */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#define ADP5585_ID   0x00
> +#define ADP5585_INT_STATUS   0x01
> +#define ADP5585_STATUS   0x02
> +#define ADP5585_FIFO_1   0x03
> +#define ADP5585_FIFO_2   0x04
> +#define ADP5585_FIFO_3   0x05
> +#define ADP5585_FIFO_4   0x06
> +#define ADP5585_FIFO_5   0x07
> +#define ADP5585_FIFO_6   0x08
> +#define ADP5585_FIFO_7   0x09
> +#define ADP5585_FIFO_8   0x0A
> +#define ADP5585_FIFO_9   0x0B
> +#define ADP5585_FIFO_10  0x0C
> +#define ADP5585_FIFO_11  0x0D
> +#define ADP5585_FIFO_12  0x0E
> +#define ADP5585_FIFO_13  0x0F
> +#define ADP5585_FIFO_14  0x10
> +#define ADP5585_FIFO_15  0x11
> +#define ADP5585_FIFO_16  0x12
> +#define ADP5585_GPI_INT_STAT_A   0x13
> +#define ADP5585_GPI_INT_STAT_B   0x14
> +#define ADP5585_GPI_STATUS_A 0x15
> +#define ADP5585_GPI_STATUS_B 0x16
> +#define ADP5585_RPULL_CONFIG_A   0x17
> +#define ADP5585_RPULL_CONFIG_B   0x18
> +#define ADP5585_RPULL_CONFIG_C   0x19
> +#define ADP5585_RPULL_CONFIG_D   0x1A
> +#define ADP5585_GPI_INT_LEVEL_A  0x1B
> +#define ADP5585_GPI_INT_LEVEL_B  0x1C
> +#define ADP5585_GPI_EVENT_EN_A   0x1D
> +#define ADP5585_GPI_EVENT_EN_B   0x1E
> +#define ADP5585_GPI_INTERRUPT_EN_A   0x1F
> +#define ADP5585_GPI_INTERRUPT_EN_B   0x20
> +#define ADP5585_DEBOUNCE_DIS_A   0x21
> +#define ADP5585_DEBOUNCE_DIS_B   0x22
> +#define ADP5585_GPO_DATA_OUT_A   0x23
> +#define ADP5585_GPO_DATA_OUT_B   0x24
> +#define ADP5585_GPO_OUT_MODE_A   0x25
> +#define ADP5585_GPO_OUT_MODE_B   0x26
> +#define ADP5585_GPIO_DIRECTION_A 0x27
> +#define ADP5585_GPIO_DIRECTION_B 0x28
> +#define ADP5585_RESET1_EVENT_A

RE: [PATCH v1] gpio: adp5585: add gpio driver for ADP5585 I/O Expander Controller

2022-09-28 Thread Alice Guo (OSS)



> -Original Message-
> From: Fabio Estevam 
> Sent: Tuesday, September 27, 2022 8:16 PM
> To: Alice Guo (OSS) 
> Cc: sba...@denx.de; s...@chromium.org; dl-uboot-imx ;
> u-boot@lists.denx.de
> Subject: Re: [PATCH v1] gpio: adp5585: add gpio driver for ADP5585 I/O
> Expander Controller
> 
> Hi Alice,
> 
> On Tue, Sep 6, 2022 at 6:37 AM Alice Guo (OSS) 
> wrote:
> >
> > From: Alice Guo 
> 
> Please add a commit log.
> 
> > Signed-off-by: Alice Guo 
> 
> > --- a/arch/arm/include/asm/arch-imx9/gpio.h
> > +++ b/arch/arm/include/asm/arch-imx9/gpio.h
> > @@ -6,6 +6,8 @@
> >  #ifndef __ASM_ARCH_IMX9_GPIO_H
> >  #define __ASM_ARCH_IMX9_GPIO_H
> >
> > +#include 
> 
> This looks like an unrelated change.

Hi Fabio,

Thanks for your reply. When compiling without "#include ", the 
following error will appear:
In file included from ./arch/arm/include/asm/gpio.h:2,
 from drivers/gpio/adp5585_gpio.c:10:
./arch/arm/include/asm/arch/gpio.h:12:9: error: unknown type name ‘u32’
   12 | u32 gpio_pdor;
  | ^~~
./arch/arm/include/asm/arch/gpio.h:13:9: error: unknown type name ‘u32’
   13 | u32 gpio_psor;
  | ^~~
./arch/arm/include/asm/arch/gpio.h:14:9: error: unknown type name ‘u32’
   14 | u32 gpio_pcor;
  | ^~~
./arch/arm/include/asm/arch/gpio.h:15:9: error: unknown type name ‘u32’
   15 | u32 gpio_ptor;
  | ^~~
./arch/arm/include/asm/arch/gpio.h:16:9: error: unknown type name ‘u32’
   16 | u32 gpio_pdir;
  | ^~~
./arch/arm/include/asm/arch/gpio.h:17:9: error: unknown type name ‘u32’
   17 | u32 gpio_pddr;
  | ^~~
./arch/arm/include/asm/arch/gpio.h:18:9: error: unknown type name ‘u32’
   18 | u32 gpio_pidr;
  | ^~~
./arch/arm/include/asm/arch/gpio.h:19:9: error: unknown type name ‘u8’
   19 | u8 gpio_pxdr[32];


Best Regards,
Alice Guo

> > +config ADP5585_GPIO
> > +   bool "ADP5585 GPIO driver"
> > +   depends on DM_GPIO && DM_I2C
> > +   help
> > + Support ADP5585 GPIO expander on i.MX platform.
> 
> Please remove "on i.MX platform" as the GPIO expander can be used on any
> platform.

[PATCH v3] imx8mq: configs: add support for distro boot commands

2021-01-14 Thread Alice Guo (OSS)

From: Alice Guo 

Supported boot device types in iMX8MQ: MMC, DHCP.

CONFIG_DISTRO_DEFAULTS is added for enabling the DISTRO_DEFAULTS option.

CONFIG_BOOTCOMMAND which is defined in include/configs/imx8mq_evk.h is
deleted because "run distro_bootcmd" is required to be the default boot
mode.

scriptaddr is the location in RAM where boot.scr.uimg/boot.scr will be
loaded to prior to execution.

kernel_addr_r is the location in RAM where the kernel will be loaded to.

Delete unnecessary environment variables because "run distro_bootcmd" is
set to be the default boot mode.

Signed-off-by: Alice Guo 
---

Changes for v3:
 - enable the DISTRO_DEFAULTS option by adding CONFIG_DISTRO_DEFAULTS=y
 - modify commit log
Changes for v2:
 - re-add boot_fdt, initrd_addr and bootm_size which may need to be used

 configs/imx8mq_evk_defconfig |  1 +
 include/configs/imx8mq_evk.h | 75 ++--
 2 files changed, 13 insertions(+), 63 deletions(-)

diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig
index de91a76d41..424301bf4d 100644
--- a/configs/imx8mq_evk_defconfig
+++ b/configs/imx8mq_evk_defconfig
@@ -36,6 +36,7 @@ CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
+CONFIG_DISTRO_DEFAULTS=y
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h
index 96bfff749c..1861ebad18 100644
--- a/include/configs/imx8mq_evk.h
+++ b/include/configs/imx8mq_evk.h
@@ -74,20 +74,20 @@
 #define IMX_FEC_BASE   0x30BE
 #endif

-#define CONFIG_MFG_ENV_SETTINGS \
-   "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
-   "rdinit=/linuxrc " \
-   "g_mass_storage.stall=0 g_mass_storage.removable=1 " \
-   "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF 
"\
-   "g_mass_storage.iSerialNumber=\"\" "\
-   "clk_ignore_unused "\
-   "\0" \
-   "initrd_addr=0x4380\0" \
-   "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} 
${fdt_addr};\0" \
+#ifndef CONFIG_SPL_BUILD
+#define BOOT_TARGET_DEVICES(func) \
+   func(MMC, mmc, 0) \
+   func(MMC, mmc, 1) \
+   func(DHCP, dhcp, na)
+
+#include 
+#endif
+
 /* Initial environment variables */
 #define CONFIG_EXTRA_ENV_SETTINGS  \
-   CONFIG_MFG_ENV_SETTINGS \
-   "script=boot.scr\0" \
+   BOOTENV \
+   "scriptaddr=0x4350\0" \
+   "kernel_addr_r=0x4088\0" \
"image=Image\0" \
"console=ttymxc0,115200\0" \
"fdt_addr=0x4300\0" \
@@ -95,59 +95,8 @@
"fdt_file=imx8mq-evk.dtb\0" \
"initrd_addr=0x4380\0"  \
"bootm_size=0x1000\0" \
-   "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
-   "mmcautodetect=yes\0" \
-   "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
-   "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} 
${script};\0" \
-   "bootscript=echo Running bootscript from mmc ...; " \
-   "source\0" \
-   "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
-   "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
-   "mmcboot=echo Booting from mmc ...; " \
-   "run mmcargs; " \
-   "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-   "if run loadfdt; then " \
-   "booti ${loadaddr} - ${fdt_addr}; " \
-   "else " \
-   "echo WARN: Cannot load the DT; " \
-   "fi; " \
-   "else " \
-   "echo wait for boot; " \
-   "fi;\0" \
-   "netargs=setenv bootargs console=${console} " \
-   "root=/dev/nfs " \
-   "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
-   "netboot=echo Booting from net ...; " \
-   "run netargs;  " \
-   "if test ${ip_dyn} = yes; then " \
-   "setenv get_cmd dhcp; " \
-   "else " \
-   "setenv get_cmd tftp; " \
-   "fi; " \
-   "${get_cmd} ${loadaddr} ${image}; " \
-   "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-   "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
-   "booti ${loadaddr} - ${fdt_addr}; " \
-   "else " \
-   "echo WARN: Cannot load the DT; " \
-   "fi; " \
-   "else " \
-   "booti; " \
-   "fi;\0"
-
-#define CONFIG_BOOTCOMMAND \
-  "mmc dev ${mmcdev}; if mmc rescan; then " \
-  "if

[PATCH v2] gpio: adp5585: add gpio driver for ADP5585 I/O Expander Controller

2022-10-08 Thread Alice Guo (OSS)

From: Alice Guo 

Add gpio driver for ADP5585 I/O Expander Controller. The ADP5585 is a 10
input/output port expander and can be used to increase the number of
I/Os available to a processor.

Signed-off-by: Alice Guo 
---

Changes for v2:
 - add a commit log
 - remove unrelated change
 - remove "on i.MX platform" in Kconfig file

 drivers/gpio/Kconfig|   6 +
 drivers/gpio/Makefile   |   1 +
 drivers/gpio/adp5585_gpio.c | 238 
 3 files changed, 245 insertions(+)
 create mode 100644 drivers/gpio/adp5585_gpio.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index c949f9d2f7..c38022d01c 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -605,4 +605,10 @@ config TURRIS_OMNIA_MCU
help
   Support for GPIOs on MCU connected to Turris Omnia via i2c.
 
+config ADP5585_GPIO
+   bool "ADP5585 GPIO driver"
+   depends on DM_GPIO && DM_I2C
+   help
+ Support ADP5585 GPIO expander.
+
 endif
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 9d718a554e..2f60b98384 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -75,3 +75,4 @@ obj-$(CONFIG_SL28CPLD_GPIO)   += sl28cpld-gpio.o
 obj-$(CONFIG_ZYNQMP_GPIO_MODEPIN)  += zynqmp_gpio_modepin.o
 obj-$(CONFIG_SLG7XL45106_I2C_GPO)  += gpio_slg7xl45106.o
 obj-$(CONFIG_$(SPL_TPL_)TURRIS_OMNIA_MCU)  += turris_omnia_mcu.o
+obj-$(CONFIG_ADP5585_GPIO) += adp5585_gpio.o
diff --git a/drivers/gpio/adp5585_gpio.c b/drivers/gpio/adp5585_gpio.c
new file mode 100644
index 00..ea0cb75459
--- /dev/null
+++ b/drivers/gpio/adp5585_gpio.c
@@ -0,0 +1,238 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ *
+ * ADP5585 I/O Expander Controller
+ *
+ * Author: Alice Guo 
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#define ADP5585_ID 0x00
+#define ADP5585_INT_STATUS 0x01
+#define ADP5585_STATUS 0x02
+#define ADP5585_FIFO_1 0x03
+#define ADP5585_FIFO_2 0x04
+#define ADP5585_FIFO_3 0x05
+#define ADP5585_FIFO_4 0x06
+#define ADP5585_FIFO_5 0x07
+#define ADP5585_FIFO_6 0x08
+#define ADP5585_FIFO_7 0x09
+#define ADP5585_FIFO_8 0x0A
+#define ADP5585_FIFO_9 0x0B
+#define ADP5585_FIFO_100x0C
+#define ADP5585_FIFO_110x0D
+#define ADP5585_FIFO_120x0E
+#define ADP5585_FIFO_130x0F
+#define ADP5585_FIFO_140x10
+#define ADP5585_FIFO_150x11
+#define ADP5585_FIFO_160x12
+#define ADP5585_GPI_INT_STAT_A 0x13
+#define ADP5585_GPI_INT_STAT_B 0x14
+#define ADP5585_GPI_STATUS_A   0x15
+#define ADP5585_GPI_STATUS_B   0x16
+#define ADP5585_RPULL_CONFIG_A 0x17
+#define ADP5585_RPULL_CONFIG_B 0x18
+#define ADP5585_RPULL_CONFIG_C 0x19
+#define ADP5585_RPULL_CONFIG_D 0x1A
+#define ADP5585_GPI_INT_LEVEL_A0x1B
+#define ADP5585_GPI_INT_LEVEL_B0x1C
+#define ADP5585_GPI_EVENT_EN_A 0x1D
+#define ADP5585_GPI_EVENT_EN_B 0x1E
+#define ADP5585_GPI_INTERRUPT_EN_A 0x1F
+#define ADP5585_GPI_INTERRUPT_EN_B 0x20
+#define ADP5585_DEBOUNCE_DIS_A 0x21
+#define ADP5585_DEBOUNCE_DIS_B 0x22
+#define ADP5585_GPO_DATA_OUT_A 0x23
+#define ADP5585_GPO_DATA_OUT_B 0x24
+#define ADP5585_GPO_OUT_MODE_A 0x25
+#define ADP5585_GPO_OUT_MODE_B 0x26
+#define ADP5585_GPIO_DIRECTION_A   0x27
+#define ADP5585_GPIO_DIRECTION_B   0x28
+#define ADP5585_RESET1_EVENT_A 0x29
+#define ADP5585_RESET1_EVENT_B 0x2A
+#define ADP5585_RESET1_EVENT_C 0x2B
+#define ADP5585_RESET2_EVENT_A 0x2C
+#define ADP5585_RESET2_EVENT_B 0x2D
+#define ADP5585_RESET_CFG  0x2E
+#define ADP5585_PWM_OFFT_LOW   0x2F
+#define ADP5585_PWM_OFFT_HIGH  0x30
+#define ADP5585_PWM_ONT_LOW0x31
+#define ADP5585_PWM_ONT_HIGH   0x32
+#define ADP5585_PWM_CFG0x33
+#define ADP5585_LOGIC_CFG  0x34
+#define ADP5585_LOGIC_FF_CFG   0x35
+#define ADP5585_LOGIC_INT_EVENT_EN 0x36
+#define ADP5585_POLL_PTIME_CFG 0x37
+#define ADP5585_PIN_CONFIG_A   0x38
+#define ADP5585_PIN_CONFIG_B   0x39
+#define ADP5585_PIN_CONFIG_D   0x3A
+#define ADP5585_GENERAL_CFG0x3B
+#define ADP5585_INT_EN 0x3C
+
+#define ADP5585_MAXGPIO10
+#define ADP5585_BANK(offs) ((offs) > 4)
+#define ADP5585_BIT(offs)  ((offs) > 4 ? \
+   1u << ((offs) - 5) : 1u << (offs))
+
+struct adp5585_plat {
+   fdt_addr_t addr;
+   u8 id;
+   u8 dat_out[2];
+   u8 dir[

[PATCH v1 0/4] ulp wdog

2022-10-09 Thread Alice Guo (OSS)

From: Alice Guo 

Alice Guo (3):
  watchdog: ulp_wdog: Update watchdog driver for imx93
  watchdog: ulp_wdog: enable watchdog interrupt on imx93
  watchdog: ulp_wdog: add driver model for ulp watchdog driver

Ye Li (1):
  ulp_wdog: Update ulp wdog driver for 32bits command

 drivers/watchdog/ulp_wdog.c | 159 ++--
 1 file changed, 135 insertions(+), 24 deletions(-)

-- 
2.17.1

[PATCH v1 1/4] ulp_wdog: Update ulp wdog driver for 32bits command

2022-10-09 Thread Alice Guo (OSS)

From: Ye Li 

To use 32bits refresh and unlock command as default, check the CMD32EN
bit to select the corresponding commands.

Signed-off-by: Ye Li 
Signed-off-by: Alice Guo 
Reviewed-by: Peng Fan 
---
 drivers/watchdog/ulp_wdog.c | 52 +
 1 file changed, 36 insertions(+), 16 deletions(-)

diff --git a/drivers/watchdog/ulp_wdog.c b/drivers/watchdog/ulp_wdog.c
index ecd35ef22a..c40e785d0a 100644
--- a/drivers/watchdog/ulp_wdog.c
+++ b/drivers/watchdog/ulp_wdog.c
@@ -28,11 +28,15 @@ struct wdog_regs {
 #define UNLOCK_WORD0 0xC520 /* 1st unlock word */
 #define UNLOCK_WORD1 0xD928 /* 2nd unlock word */
 
+#define UNLOCK_WORD 0xD928C520 /* unlock word */
+#define REFRESH_WORD 0xB480A602 /* refresh word */
+
 #define WDGCS_WDGE  BIT(7)
 #define WDGCS_WDGUPDATE BIT(5)
 
 #define WDGCS_RCS   BIT(10)
 #define WDGCS_ULK   BIT(11)
+#define WDGCS_CMD32EN   BIT(13)
 #define WDGCS_FLG   BIT(14)
 
 #define WDG_BUS_CLK  (0x0)
@@ -52,20 +56,30 @@ void hw_watchdog_reset(void)
 {
struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
 
-   dmb();
-   __raw_writel(REFRESH_WORD0, &wdog->cnt);
-   __raw_writel(REFRESH_WORD1, &wdog->cnt);
-   dmb();
+   if (readl(&wdog->cs) & WDGCS_CMD32EN) {
+   writel(REFRESH_WORD, &wdog->cnt);
+   } else {
+   dmb();
+   __raw_writel(REFRESH_WORD0, &wdog->cnt);
+   __raw_writel(REFRESH_WORD1, &wdog->cnt);
+   dmb();
+   }
 }
 
 void hw_watchdog_init(void)
 {
struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
-
-   dmb();
-   __raw_writel(UNLOCK_WORD0, &wdog->cnt);
-   __raw_writel(UNLOCK_WORD1, &wdog->cnt);
-   dmb();
+   u32 cmd32 = 0;
+
+   if (readl(&wdog->cs) & WDGCS_CMD32EN) {
+   writel(UNLOCK_WORD, &wdog->cnt);
+   cmd32 = WDGCS_CMD32EN;
+   } else {
+   dmb();
+   __raw_writel(UNLOCK_WORD0, &wdog->cnt);
+   __raw_writel(UNLOCK_WORD1, &wdog->cnt);
+   dmb();
+   }
 
/* Wait WDOG Unlock */
while (!(readl(&wdog->cs) & WDGCS_ULK))
@@ -75,7 +89,7 @@ void hw_watchdog_init(void)
writel(0, &wdog->win);
 
/* setting 1-kHz clock source, enable counter running, and clear 
interrupt */
-   writel((WDGCS_WDGE | WDGCS_WDGUPDATE |(WDG_LPO_CLK << 8) | WDGCS_FLG), 
&wdog->cs);
+   writel((cmd32 | WDGCS_WDGE | WDGCS_WDGUPDATE |(WDG_LPO_CLK << 8) | 
WDGCS_FLG), &wdog->cs);
 
/* Wait WDOG reconfiguration */
while (!(readl(&wdog->cs) & WDGCS_RCS))
@@ -87,11 +101,17 @@ void hw_watchdog_init(void)
 void reset_cpu(void)
 {
struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
-
-   dmb();
-   __raw_writel(UNLOCK_WORD0, &wdog->cnt);
-   __raw_writel(UNLOCK_WORD1, &wdog->cnt);
-   dmb();
+   u32 cmd32 = 0;
+
+   if (readl(&wdog->cs) & WDGCS_CMD32EN) {
+   writel(UNLOCK_WORD, &wdog->cnt);
+   cmd32 = WDGCS_CMD32EN;
+   } else {
+   dmb();
+   __raw_writel(UNLOCK_WORD0, &wdog->cnt);
+   __raw_writel(UNLOCK_WORD1, &wdog->cnt);
+   dmb();
+   }
 
/* Wait WDOG Unlock */
while (!(readl(&wdog->cs) & WDGCS_ULK))
@@ -101,7 +121,7 @@ void reset_cpu(void)
writel(0, &wdog->win);
 
/* enable counter running */
-   writel((WDGCS_WDGE | (WDG_LPO_CLK << 8)), &wdog->cs);
+   writel((cmd32 | WDGCS_WDGE | (WDG_LPO_CLK << 8)), &wdog->cs);
 
/* Wait WDOG reconfiguration */
while (!(readl(&wdog->cs) & WDGCS_RCS))
-- 
2.17.1

[PATCH v1 2/4] watchdog: ulp_wdog: Update watchdog driver for imx93

2022-10-09 Thread Alice Guo (OSS)

From: Alice Guo 

The WDOG clocks are sourced from the fixed 32KHz (lpo_clk).When the
timeout period exceeds 2 seconds, the value written to the TOVAL
register is larger than 16-bit can represent. Enabling watchdog
prescaler to solve this problem.

Signed-off-by: Alice Guo 
---
 drivers/watchdog/ulp_wdog.c | 12 +++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/watchdog/ulp_wdog.c b/drivers/watchdog/ulp_wdog.c
index c40e785d0a..843f95aa4f 100644
--- a/drivers/watchdog/ulp_wdog.c
+++ b/drivers/watchdog/ulp_wdog.c
@@ -36,6 +36,7 @@ struct wdog_regs {
 
 #define WDGCS_RCS   BIT(10)
 #define WDGCS_ULK   BIT(11)
+#define WDOG_CS_PRESBIT(12)
 #define WDGCS_CMD32EN   BIT(13)
 #define WDGCS_FLG   BIT(14)
 
@@ -89,7 +90,12 @@ void hw_watchdog_init(void)
writel(0, &wdog->win);
 
/* setting 1-kHz clock source, enable counter running, and clear 
interrupt */
+#if defined(CONFIG_ARCH_IMX9)
+   writel((cmd32 | WDGCS_WDGE | WDGCS_WDGUPDATE | (WDG_LPO_CLK << 8) |
+  WDGCS_FLG | WDOG_CS_PRES), &wdog->cs);
+#else
writel((cmd32 | WDGCS_WDGE | WDGCS_WDGUPDATE |(WDG_LPO_CLK << 8) | 
WDGCS_FLG), &wdog->cs);
+#endif
 
/* Wait WDOG reconfiguration */
while (!(readl(&wdog->cs) & WDGCS_RCS))
@@ -117,11 +123,15 @@ void reset_cpu(void)
while (!(readl(&wdog->cs) & WDGCS_ULK))
;
 
-   hw_watchdog_set_timeout(5); /* 5ms timeout */
+   hw_watchdog_set_timeout(5); /* 5ms timeout for general; 40ms timeout 
for imx93 */
writel(0, &wdog->win);
 
/* enable counter running */
+#if defined(CONFIG_ARCH_IMX9)
+   writel((cmd32 | WDGCS_WDGE | (WDG_LPO_CLK << 8) | WDOG_CS_PRES), 
&wdog->cs);
+#else
writel((cmd32 | WDGCS_WDGE | (WDG_LPO_CLK << 8)), &wdog->cs);
+#endif
 
/* Wait WDOG reconfiguration */
while (!(readl(&wdog->cs) & WDGCS_RCS))
-- 
2.17.1

[PATCH v1 3/4] watchdog: ulp_wdog: enable watchdog interrupt on imx93

2022-10-09 Thread Alice Guo (OSS)

From: Alice Guo 

The reset source of the external PMIC on i.MX93 is WDOG_ANY PAD and the
source of WDOG_ANY PAD is interrupt. Therefore, using PMIC to reset
needs to enable the watchdog interrupt.

Signed-off-by: Alice Guo 
---
 drivers/watchdog/ulp_wdog.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/watchdog/ulp_wdog.c b/drivers/watchdog/ulp_wdog.c
index 843f95aa4f..49f8900cd3 100644
--- a/drivers/watchdog/ulp_wdog.c
+++ b/drivers/watchdog/ulp_wdog.c
@@ -39,6 +39,7 @@ struct wdog_regs {
 #define WDOG_CS_PRESBIT(12)
 #define WDGCS_CMD32EN   BIT(13)
 #define WDGCS_FLG   BIT(14)
+#define WDGCS_INT  BIT(6)
 
 #define WDG_BUS_CLK  (0x0)
 #define WDG_LPO_CLK  (0x1)
@@ -92,7 +93,7 @@ void hw_watchdog_init(void)
/* setting 1-kHz clock source, enable counter running, and clear 
interrupt */
 #if defined(CONFIG_ARCH_IMX9)
writel((cmd32 | WDGCS_WDGE | WDGCS_WDGUPDATE | (WDG_LPO_CLK << 8) |
-  WDGCS_FLG | WDOG_CS_PRES), &wdog->cs);
+  WDGCS_FLG | WDOG_CS_PRES | WDGCS_INT), &wdog->cs);
 #else
writel((cmd32 | WDGCS_WDGE | WDGCS_WDGUPDATE |(WDG_LPO_CLK << 8) | 
WDGCS_FLG), &wdog->cs);
 #endif
@@ -128,7 +129,7 @@ void reset_cpu(void)
 
/* enable counter running */
 #if defined(CONFIG_ARCH_IMX9)
-   writel((cmd32 | WDGCS_WDGE | (WDG_LPO_CLK << 8) | WDOG_CS_PRES), 
&wdog->cs);
+   writel((cmd32 | WDGCS_WDGE | (WDG_LPO_CLK << 8) | WDOG_CS_PRES | 
WDGCS_INT), &wdog->cs);
 #else
writel((cmd32 | WDGCS_WDGE | (WDG_LPO_CLK << 8)), &wdog->cs);
 #endif
-- 
2.17.1

[PATCH v1 4/4] watchdog: ulp_wdog: add driver model for ulp watchdog driver

2022-10-09 Thread Alice Guo (OSS)

From: Alice Guo 

Enable driver model for ulp watchdog timer. When CONFIG_WDT=y and the
status of device node is "okay", initr_watchdog will be called and
finally calls ulp_wdt_probe() and ulp_wdt_start().

Signed-off-by: Alice Guo 
Reviewed-by: Ye Li 
---
 drivers/watchdog/ulp_wdog.c | 94 ++---
 1 file changed, 87 insertions(+), 7 deletions(-)

diff --git a/drivers/watchdog/ulp_wdog.c b/drivers/watchdog/ulp_wdog.c
index 49f8900cd3..93cf6e253d 100644
--- a/drivers/watchdog/ulp_wdog.c
+++ b/drivers/watchdog/ulp_wdog.c
@@ -7,6 +7,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 /*
  * MX7ULP WDOG Register Map
@@ -18,6 +20,11 @@ struct wdog_regs {
u32 win;
 };
 
+struct ulp_wdt_priv {
+   struct wdog_regs *wdog;
+   u32 clk_rate;
+};
+
 #ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS
 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 0x1500
 #endif
@@ -46,6 +53,9 @@ struct wdog_regs {
 #define WDG_32KHZ_CLK(0x2)
 #define WDG_EXT_CLK  (0x3)
 
+#define CLK_RATE_1KHZ  1000
+#define CLK_RATE_32KHZ 125
+
 void hw_watchdog_set_timeout(u16 val)
 {
/* setting timeout value */
@@ -54,10 +64,8 @@ void hw_watchdog_set_timeout(u16 val)
writel(val, &wdog->toval);
 }
 
-void hw_watchdog_reset(void)
+void ulp_watchdog_reset(struct wdog_regs *wdog)
 {
-   struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
-
if (readl(&wdog->cs) & WDGCS_CMD32EN) {
writel(REFRESH_WORD, &wdog->cnt);
} else {
@@ -68,9 +76,8 @@ void hw_watchdog_reset(void)
}
 }
 
-void hw_watchdog_init(void)
+void ulp_watchdog_init(struct wdog_regs *wdog, u16 timeout)
 {
-   struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
u32 cmd32 = 0;
 
if (readl(&wdog->cs) & WDGCS_CMD32EN) {
@@ -87,7 +94,7 @@ void hw_watchdog_init(void)
while (!(readl(&wdog->cs) & WDGCS_ULK))
;
 
-   hw_watchdog_set_timeout(CONFIG_WATCHDOG_TIMEOUT_MSECS);
+   hw_watchdog_set_timeout(timeout);
writel(0, &wdog->win);
 
/* setting 1-kHz clock source, enable counter running, and clear 
interrupt */
@@ -102,7 +109,21 @@ void hw_watchdog_init(void)
while (!(readl(&wdog->cs) & WDGCS_RCS))
;
 
-   hw_watchdog_reset();
+   ulp_watchdog_reset(wdog);
+}
+
+void hw_watchdog_reset(void)
+{
+   struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
+
+   ulp_watchdog_reset(wdog);
+}
+
+void hw_watchdog_init(void)
+{
+   struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
+
+   ulp_watchdog_init(wdog, CONFIG_WATCHDOG_TIMEOUT_MSECS);
 }
 
 void reset_cpu(void)
@@ -142,3 +163,62 @@ void reset_cpu(void)
 
while (1);
 }
+
+static int ulp_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
+{
+   struct ulp_wdt_priv *priv = dev_get_priv(dev);
+   u64 timeout = 0;
+
+   timeout = (timeout_ms * priv->clk_rate) / 1000;
+   if (timeout > U16_MAX)
+   return -EINVAL;
+
+   ulp_watchdog_init(priv->wdog, (u16)timeout);
+
+   return 0;
+}
+
+static int ulp_wdt_reset(struct udevice *dev)
+{
+   struct ulp_wdt_priv *priv = dev_get_priv(dev);
+
+   ulp_watchdog_reset(priv->wdog);
+
+   return 0;
+}
+
+static int ulp_wdt_probe(struct udevice *dev)
+{
+   struct ulp_wdt_priv *priv = dev_get_priv(dev);
+
+   priv->wdog = dev_read_addr_ptr(dev);
+   if (!priv->wdog)
+   return -EINVAL;
+
+   priv->clk_rate = (u32)dev_get_driver_data(dev);
+   if (!priv->clk_rate)
+   return -EINVAL;
+
+   return 0;
+}
+
+static const struct wdt_ops ulp_wdt_ops = {
+   .start = ulp_wdt_start,
+   .reset = ulp_wdt_reset,
+};
+
+static const struct udevice_id ulp_wdt_ids[] = {
+   { .compatible = "fsl,imx7ulp-wdt", .data = CLK_RATE_1KHZ },
+   { .compatible = "fsl,imx8ulp-wdt", .data = CLK_RATE_1KHZ },
+   { .compatible = "fsl,imx93-wdt", .data = CLK_RATE_32KHZ },
+   {}
+};
+
+U_BOOT_DRIVER(ulp_wdt) = {
+   .name   = "ulp_wdt",
+   .id = UCLASS_WDT,
+   .of_match   = ulp_wdt_ids,
+   .priv_auto  = sizeof(struct ulp_wdt_priv),
+   .probe  = ulp_wdt_probe,
+   .ops= &ulp_wdt_ops,
+};
-- 
2.17.1

[PATCH v2 0/4] ulp wdog

2022-10-21 Thread Alice Guo (OSS)

From: Alice Guo 

Alice Guo (3):
  watchdog: ulp_wdog: Update watchdog driver for imx93
  watchdog: ulp_wdog: enable watchdog interrupt on imx93
  watchdog: ulp_wdog: add driver model for ulp watchdog driver

Ye Li (1):
  ulp_wdog: Update ulp wdog driver for 32bits command

 drivers/watchdog/ulp_wdog.c | 159 ++--
 1 file changed, 135 insertions(+), 24 deletions(-)

-- 
2.17.1

[PATCH v2 1/4] ulp_wdog: Update ulp wdog driver for 32bits command

2022-10-21 Thread Alice Guo (OSS)

From: Ye Li 

To use 32bits refresh and unlock command as default, check the CMD32EN
bit to select the corresponding commands.

Signed-off-by: Ye Li 
Signed-off-by: Alice Guo 
Reviewed-by: Peng Fan 
---

Changes for v2:
 resolve a coding style issue

 drivers/watchdog/ulp_wdog.c | 52 +
 1 file changed, 36 insertions(+), 16 deletions(-)

diff --git a/drivers/watchdog/ulp_wdog.c b/drivers/watchdog/ulp_wdog.c
index ecd35ef22a..820da0f9dd 100644
--- a/drivers/watchdog/ulp_wdog.c
+++ b/drivers/watchdog/ulp_wdog.c
@@ -28,11 +28,15 @@ struct wdog_regs {
 #define UNLOCK_WORD0 0xC520 /* 1st unlock word */
 #define UNLOCK_WORD1 0xD928 /* 2nd unlock word */
 
+#define UNLOCK_WORD 0xD928C520 /* unlock word */
+#define REFRESH_WORD 0xB480A602 /* refresh word */
+
 #define WDGCS_WDGE  BIT(7)
 #define WDGCS_WDGUPDATE BIT(5)
 
 #define WDGCS_RCS   BIT(10)
 #define WDGCS_ULK   BIT(11)
+#define WDGCS_CMD32EN   BIT(13)
 #define WDGCS_FLG   BIT(14)
 
 #define WDG_BUS_CLK  (0x0)
@@ -52,20 +56,30 @@ void hw_watchdog_reset(void)
 {
struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
 
-   dmb();
-   __raw_writel(REFRESH_WORD0, &wdog->cnt);
-   __raw_writel(REFRESH_WORD1, &wdog->cnt);
-   dmb();
+   if (readl(&wdog->cs) & WDGCS_CMD32EN) {
+   writel(REFRESH_WORD, &wdog->cnt);
+   } else {
+   dmb();
+   __raw_writel(REFRESH_WORD0, &wdog->cnt);
+   __raw_writel(REFRESH_WORD1, &wdog->cnt);
+   dmb();
+   }
 }
 
 void hw_watchdog_init(void)
 {
struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
-
-   dmb();
-   __raw_writel(UNLOCK_WORD0, &wdog->cnt);
-   __raw_writel(UNLOCK_WORD1, &wdog->cnt);
-   dmb();
+   u32 cmd32 = 0;
+
+   if (readl(&wdog->cs) & WDGCS_CMD32EN) {
+   writel(UNLOCK_WORD, &wdog->cnt);
+   cmd32 = WDGCS_CMD32EN;
+   } else {
+   dmb();
+   __raw_writel(UNLOCK_WORD0, &wdog->cnt);
+   __raw_writel(UNLOCK_WORD1, &wdog->cnt);
+   dmb();
+   }
 
/* Wait WDOG Unlock */
while (!(readl(&wdog->cs) & WDGCS_ULK))
@@ -75,7 +89,7 @@ void hw_watchdog_init(void)
writel(0, &wdog->win);
 
/* setting 1-kHz clock source, enable counter running, and clear 
interrupt */
-   writel((WDGCS_WDGE | WDGCS_WDGUPDATE |(WDG_LPO_CLK << 8) | WDGCS_FLG), 
&wdog->cs);
+   writel((cmd32 | WDGCS_WDGE | WDGCS_WDGUPDATE | (WDG_LPO_CLK << 8) | 
WDGCS_FLG), &wdog->cs);
 
/* Wait WDOG reconfiguration */
while (!(readl(&wdog->cs) & WDGCS_RCS))
@@ -87,11 +101,17 @@ void hw_watchdog_init(void)
 void reset_cpu(void)
 {
struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
-
-   dmb();
-   __raw_writel(UNLOCK_WORD0, &wdog->cnt);
-   __raw_writel(UNLOCK_WORD1, &wdog->cnt);
-   dmb();
+   u32 cmd32 = 0;
+
+   if (readl(&wdog->cs) & WDGCS_CMD32EN) {
+   writel(UNLOCK_WORD, &wdog->cnt);
+   cmd32 = WDGCS_CMD32EN;
+   } else {
+   dmb();
+   __raw_writel(UNLOCK_WORD0, &wdog->cnt);
+   __raw_writel(UNLOCK_WORD1, &wdog->cnt);
+   dmb();
+   }
 
/* Wait WDOG Unlock */
while (!(readl(&wdog->cs) & WDGCS_ULK))
@@ -101,7 +121,7 @@ void reset_cpu(void)
writel(0, &wdog->win);
 
/* enable counter running */
-   writel((WDGCS_WDGE | (WDG_LPO_CLK << 8)), &wdog->cs);
+   writel((cmd32 | WDGCS_WDGE | (WDG_LPO_CLK << 8)), &wdog->cs);
 
/* Wait WDOG reconfiguration */
while (!(readl(&wdog->cs) & WDGCS_RCS))
-- 
2.17.1

[PATCH v2 2/4] watchdog: ulp_wdog: Update watchdog driver for imx93

2022-10-21 Thread Alice Guo (OSS)

From: Alice Guo 

The WDOG clocks are sourced from the fixed 32KHz (lpo_clk).When the
timeout period exceeds 2 seconds, the value written to the TOVAL
register is larger than 16-bit can represent. Enabling watchdog
prescaler to solve this problem.

Signed-off-by: Alice Guo 
---

Changes for v2:
 use 'if (IS_ENABLED(CONFIG...))' instead of '#if or #ifdef'

 drivers/watchdog/ulp_wdog.c | 15 ---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/drivers/watchdog/ulp_wdog.c b/drivers/watchdog/ulp_wdog.c
index 820da0f9dd..17778587ee 100644
--- a/drivers/watchdog/ulp_wdog.c
+++ b/drivers/watchdog/ulp_wdog.c
@@ -36,6 +36,7 @@ struct wdog_regs {
 
 #define WDGCS_RCS   BIT(10)
 #define WDGCS_ULK   BIT(11)
+#define WDOG_CS_PRESBIT(12)
 #define WDGCS_CMD32EN   BIT(13)
 #define WDGCS_FLG   BIT(14)
 
@@ -89,7 +90,12 @@ void hw_watchdog_init(void)
writel(0, &wdog->win);
 
/* setting 1-kHz clock source, enable counter running, and clear 
interrupt */
-   writel((cmd32 | WDGCS_WDGE | WDGCS_WDGUPDATE | (WDG_LPO_CLK << 8) | 
WDGCS_FLG), &wdog->cs);
+   if (IS_ENABLED(CONFIG_ARCH_IMX9))
+   writel((cmd32 | WDGCS_WDGE | WDGCS_WDGUPDATE | (WDG_LPO_CLK << 
8) |
+  WDGCS_FLG | WDOG_CS_PRES), &wdog->cs);
+   else
+   writel((cmd32 | WDGCS_WDGE | WDGCS_WDGUPDATE | (WDG_LPO_CLK << 
8) |
+  WDGCS_FLG), &wdog->cs);
 
/* Wait WDOG reconfiguration */
while (!(readl(&wdog->cs) & WDGCS_RCS))
@@ -117,11 +123,14 @@ void reset_cpu(void)
while (!(readl(&wdog->cs) & WDGCS_ULK))
;
 
-   hw_watchdog_set_timeout(5); /* 5ms timeout */
+   hw_watchdog_set_timeout(5); /* 5ms timeout for general; 40ms timeout 
for imx93 */
writel(0, &wdog->win);
 
/* enable counter running */
-   writel((cmd32 | WDGCS_WDGE | (WDG_LPO_CLK << 8)), &wdog->cs);
+   if (IS_ENABLED(CONFIG_ARCH_IMX9))
+   writel((cmd32 | WDGCS_WDGE | (WDG_LPO_CLK << 8) | 
WDOG_CS_PRES), &wdog->cs);
+   else
+   writel((cmd32 | WDGCS_WDGE | (WDG_LPO_CLK << 8)), &wdog->cs);
 
/* Wait WDOG reconfiguration */
while (!(readl(&wdog->cs) & WDGCS_RCS))
-- 
2.17.1

[PATCH v2 3/4] watchdog: ulp_wdog: enable watchdog interrupt on imx93

2022-10-21 Thread Alice Guo (OSS)

From: Alice Guo 

The reset source of the external PMIC on i.MX93 is WDOG_ANY PAD and the
source of WDOG_ANY PAD is interrupt. Therefore, using PMIC to reset
needs to enable the watchdog interrupt.

Signed-off-by: Alice Guo 
---

Changes for v2:
 none

 drivers/watchdog/ulp_wdog.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/watchdog/ulp_wdog.c b/drivers/watchdog/ulp_wdog.c
index 17778587ee..1b286816b5 100644
--- a/drivers/watchdog/ulp_wdog.c
+++ b/drivers/watchdog/ulp_wdog.c
@@ -39,6 +39,7 @@ struct wdog_regs {
 #define WDOG_CS_PRESBIT(12)
 #define WDGCS_CMD32EN   BIT(13)
 #define WDGCS_FLG   BIT(14)
+#define WDGCS_INT  BIT(6)
 
 #define WDG_BUS_CLK  (0x0)
 #define WDG_LPO_CLK  (0x1)
@@ -92,7 +93,7 @@ void hw_watchdog_init(void)
/* setting 1-kHz clock source, enable counter running, and clear 
interrupt */
if (IS_ENABLED(CONFIG_ARCH_IMX9))
writel((cmd32 | WDGCS_WDGE | WDGCS_WDGUPDATE | (WDG_LPO_CLK << 
8) |
-  WDGCS_FLG | WDOG_CS_PRES), &wdog->cs);
+  WDGCS_FLG | WDOG_CS_PRES | WDGCS_INT), &wdog->cs);
else
writel((cmd32 | WDGCS_WDGE | WDGCS_WDGUPDATE | (WDG_LPO_CLK << 
8) |
   WDGCS_FLG), &wdog->cs);
@@ -128,7 +129,8 @@ void reset_cpu(void)
 
/* enable counter running */
if (IS_ENABLED(CONFIG_ARCH_IMX9))
-   writel((cmd32 | WDGCS_WDGE | (WDG_LPO_CLK << 8) | 
WDOG_CS_PRES), &wdog->cs);
+   writel((cmd32 | WDGCS_WDGE | (WDG_LPO_CLK << 8) | WDOG_CS_PRES |
+  WDGCS_INT), &wdog->cs);
else
writel((cmd32 | WDGCS_WDGE | (WDG_LPO_CLK << 8)), &wdog->cs);
 
-- 
2.17.1

[PATCH v2 4/4] watchdog: ulp_wdog: add driver model for ulp watchdog driver

2022-10-21 Thread Alice Guo (OSS)

From: Alice Guo 

Enable driver model for ulp watchdog timer. When CONFIG_WDT=y and the
status of device node is "okay", initr_watchdog will be called and
finally calls ulp_wdt_probe() and ulp_wdt_start().

Signed-off-by: Alice Guo 
Reviewed-by: Ye Li 
---

Changes for v2:
 none

 drivers/watchdog/ulp_wdog.c | 94 ++---
 1 file changed, 87 insertions(+), 7 deletions(-)

diff --git a/drivers/watchdog/ulp_wdog.c b/drivers/watchdog/ulp_wdog.c
index 1b286816b5..e081054304 100644
--- a/drivers/watchdog/ulp_wdog.c
+++ b/drivers/watchdog/ulp_wdog.c
@@ -7,6 +7,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 /*
  * MX7ULP WDOG Register Map
@@ -18,6 +20,11 @@ struct wdog_regs {
u32 win;
 };
 
+struct ulp_wdt_priv {
+   struct wdog_regs *wdog;
+   u32 clk_rate;
+};
+
 #ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS
 #define CONFIG_WATCHDOG_TIMEOUT_MSECS 0x1500
 #endif
@@ -46,6 +53,9 @@ struct wdog_regs {
 #define WDG_32KHZ_CLK(0x2)
 #define WDG_EXT_CLK  (0x3)
 
+#define CLK_RATE_1KHZ  1000
+#define CLK_RATE_32KHZ 125
+
 void hw_watchdog_set_timeout(u16 val)
 {
/* setting timeout value */
@@ -54,10 +64,8 @@ void hw_watchdog_set_timeout(u16 val)
writel(val, &wdog->toval);
 }
 
-void hw_watchdog_reset(void)
+void ulp_watchdog_reset(struct wdog_regs *wdog)
 {
-   struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
-
if (readl(&wdog->cs) & WDGCS_CMD32EN) {
writel(REFRESH_WORD, &wdog->cnt);
} else {
@@ -68,9 +76,8 @@ void hw_watchdog_reset(void)
}
 }
 
-void hw_watchdog_init(void)
+void ulp_watchdog_init(struct wdog_regs *wdog, u16 timeout)
 {
-   struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
u32 cmd32 = 0;
 
if (readl(&wdog->cs) & WDGCS_CMD32EN) {
@@ -87,7 +94,7 @@ void hw_watchdog_init(void)
while (!(readl(&wdog->cs) & WDGCS_ULK))
;
 
-   hw_watchdog_set_timeout(CONFIG_WATCHDOG_TIMEOUT_MSECS);
+   hw_watchdog_set_timeout(timeout);
writel(0, &wdog->win);
 
/* setting 1-kHz clock source, enable counter running, and clear 
interrupt */
@@ -102,7 +109,21 @@ void hw_watchdog_init(void)
while (!(readl(&wdog->cs) & WDGCS_RCS))
;
 
-   hw_watchdog_reset();
+   ulp_watchdog_reset(wdog);
+}
+
+void hw_watchdog_reset(void)
+{
+   struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
+
+   ulp_watchdog_reset(wdog);
+}
+
+void hw_watchdog_init(void)
+{
+   struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
+
+   ulp_watchdog_init(wdog, CONFIG_WATCHDOG_TIMEOUT_MSECS);
 }
 
 void reset_cpu(void)
@@ -142,3 +163,62 @@ void reset_cpu(void)
 
while (1);
 }
+
+static int ulp_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
+{
+   struct ulp_wdt_priv *priv = dev_get_priv(dev);
+   u64 timeout = 0;
+
+   timeout = (timeout_ms * priv->clk_rate) / 1000;
+   if (timeout > U16_MAX)
+   return -EINVAL;
+
+   ulp_watchdog_init(priv->wdog, (u16)timeout);
+
+   return 0;
+}
+
+static int ulp_wdt_reset(struct udevice *dev)
+{
+   struct ulp_wdt_priv *priv = dev_get_priv(dev);
+
+   ulp_watchdog_reset(priv->wdog);
+
+   return 0;
+}
+
+static int ulp_wdt_probe(struct udevice *dev)
+{
+   struct ulp_wdt_priv *priv = dev_get_priv(dev);
+
+   priv->wdog = dev_read_addr_ptr(dev);
+   if (!priv->wdog)
+   return -EINVAL;
+
+   priv->clk_rate = (u32)dev_get_driver_data(dev);
+   if (!priv->clk_rate)
+   return -EINVAL;
+
+   return 0;
+}
+
+static const struct wdt_ops ulp_wdt_ops = {
+   .start = ulp_wdt_start,
+   .reset = ulp_wdt_reset,
+};
+
+static const struct udevice_id ulp_wdt_ids[] = {
+   { .compatible = "fsl,imx7ulp-wdt", .data = CLK_RATE_1KHZ },
+   { .compatible = "fsl,imx8ulp-wdt", .data = CLK_RATE_1KHZ },
+   { .compatible = "fsl,imx93-wdt", .data = CLK_RATE_32KHZ },
+   {}
+};
+
+U_BOOT_DRIVER(ulp_wdt) = {
+   .name   = "ulp_wdt",
+   .id = UCLASS_WDT,
+   .of_match   = ulp_wdt_ids,
+   .priv_auto  = sizeof(struct ulp_wdt_priv),
+   .probe  = ulp_wdt_probe,
+   .ops= &ulp_wdt_ops,
+};
-- 
2.17.1

[PATCH v1 1/2] imx8mm: configs: add support for distro boot commands

2020-12-12 Thread Alice Guo (OSS)

From: Alice Guo 

Supported boot device types in iMX8MM: MMC, QSPI, DHCP.

BOOTENV introduces other environment variables, so the size of ENV
should be increased. CONFIG_CMD_PART is added for command part and
CONFIG_CMD_FS_GENERIC is for command fstype.

CONFIG_BOOTCOMMAND which is defined in include/configs/imx8mm_evk.h is
moved to the place before BOOTENV because "run distro_bootcmd" is not
required to be the default boot mode. scriptaddr is the location in RAM
where boot.scr.uimg/boot.scr will be loaded to prior to execution.
script_offset_f is the location of boot.scr.uimg/boot.scr in QSPI and
script_size_f is the size of boot.scr.uimg/boot.scr. kernel_addr_r is
the location in RAM where the kernel will be loaded to.

Signed-off-by: Alice Guo 
---
 configs/imx8mm_evk_defconfig |  4 ++-
 include/configs/imx8mm_evk.h | 47 +++-
 2 files changed, 38 insertions(+), 13 deletions(-)

diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig
index 91d3bc3ac9..993b7b8835 100644
--- a/configs/imx8mm_evk_defconfig
+++ b/configs/imx8mm_evk_defconfig
@@ -5,7 +5,7 @@ CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x1
-CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x40
 CONFIG_SYS_I2C_MXC_I2C1=y
 CONFIG_SYS_I2C_MXC_I2C2=y
@@ -49,6 +49,8 @@ CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h
index 83521ad401..e6a1a0557a 100644
--- a/include/configs/imx8mm_evk.h
+++ b/include/configs/imx8mm_evk.h
@@ -32,8 +32,43 @@

 #endif

+#define CONFIG_BOOTCOMMAND \
+  "mmc dev ${mmcdev}; if mmc rescan; then " \
+  "if run loadbootscript; then " \
+  "run bootscript; " \
+  "else " \
+  "if run loadimage; then " \
+  "run mmcboot; " \
+  "else run netboot; " \
+  "fi; " \
+  "fi; " \
+  "fi;"
+
+#define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \
+   "bootcmd_" #devtypel #instance "=sf probe " #instance " 0 0 && " \
+  "sf read $scriptaddr $script_offset_f $script_size_f && 
" \
+  "source ${scriptaddr}; echo SCRIPT FAILED: 
continuing...;\0"
+
+#define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \
+   #devtypel #instance " "
+
+#ifndef CONFIG_SPL_BUILD
+#define BOOT_TARGET_DEVICES(func) \
+   func(MMC, mmc, 1) \
+   func(MMC, mmc, 2) \
+   func(QSPI, qspi, 0) \
+   func(DHCP, dhcp, na)
+
+#include 
+#endif
+
 /* Initial environment variables */
 #define CONFIG_EXTRA_ENV_SETTINGS  \
+   BOOTENV \
+   "scriptaddr=0x4350\0" \
+   "script_offset_f=0x50\0" \
+   "script_size_f=0x10\0" \
+   "kernel_addr_r=0x4088\0" \
"script=boot.scr\0" \
"image=Image\0" \
"console=ttymxc1,115200\0" \
@@ -84,18 +119,6 @@
"fi; " \
"fi;\0"

-#define CONFIG_BOOTCOMMAND \
-  "mmc dev ${mmcdev}; if mmc rescan; then " \
-  "if run loadbootscript; then " \
-  "run bootscript; " \
-  "else " \
-  "if run loadimage; then " \
-  "run mmcboot; " \
-  "else run netboot; " \
-  "fi; " \
-  "fi; " \
-  "fi;"
-
 /* Link Definitions */
 #define CONFIG_LOADADDR0x4048

--
2.17.1

[PATCH v1 2/2] board: imx8mm: add boot.cmd for distro boot on iMX8MM

2020-12-12 Thread Alice Guo (OSS)

From: Alice Guo 

Distro Boot requires a U-Boot-specific script named boot.scr or
boot.scr.uimg which contains boot commands to boot the system. The
boot.cmd is such a file. Use mkimage to generate boot.scr or
boot.scr.uimg from boot.cmd, and the command is:
mkimage -A arm -O linux -T script -C none -a 0 -e 0 -n "Distro Boot Script" -d 
boot.cmd boot.scr.uimg

QSPI in iMX8MM platform is only used to store bootloader and script so
that we do not load image or .dtb file from QSPI as is shown in
boot.cmd file.

The boot.cmd file is an example script and can be modified based on
needs.

Signed-off-by: Alice Guo 
---
 board/freescale/imx8mm_evk/boot.cmd | 35 +
 1 file changed, 35 insertions(+)
 create mode 100644 board/freescale/imx8mm_evk/boot.cmd

diff --git a/board/freescale/imx8mm_evk/boot.cmd 
b/board/freescale/imx8mm_evk/boot.cmd
new file mode 100644
index 00..fdfceec263
--- /dev/null
+++ b/board/freescale/imx8mm_evk/boot.cmd
@@ -0,0 +1,35 @@
+setenv bootargs console=${console} root=${mmcroot};
+
+for boot_target in ${boot_targets};
+do
+if test "${boot_target}" = "mmc1" ; then
+if fatload mmc 1:${mmcpart} ${kernel_addr_r} ${image}; then
+if fatload mmc 1:${mmcpart} ${fdt_addr} ${fdt_file}; 
then
+echo Load image and .dtb from SD card(mmc1);
+booti ${kernel_addr_r} - ${fdt_addr};
+exit;
+fi
+fi
+fi
+
+if test "${boot_target}" = "mmc2" ; then
+if fatload mmc 2:${mmcpart} ${kernel_addr_r} ${image}; then
+if fatload mmc 2:${mmcpart} ${fdt_addr} ${fdt_file}; 
then
+echo Load image and .dtb from eMMC(mmc2);
+booti ${kernel_addr_r} - ${fdt_addr};
+exit;
+fi
+fi
+fi
+
+if test "${boot_target}" = "dhcp" ; then
+if dhcp ${kernel_addr_r} ${serverip}:${image}; then
+if dhcp ${fdt_addr} ${serverip}:${fdt_file}; then
+echo Load image and .dtb from net(dhcp);
+booti ${kernel_addr_r} - ${fdt_addr};
+exit;
+fi
+fi
+fi
+
+done
--
2.17.1

[PATCH v2 1/2] imx8mm: configs: add support for distro boot commands

2020-12-15 Thread Alice Guo (OSS)

From: Alice Guo 

Supported boot device types in iMX8MM: MMC, DHCP.

CONFIG_CMD_PART is added for command part and CONFIG_CMD_FS_GENERIC is
for command fstype.

CONFIG_BOOTCOMMAND which is defined in include/configs/imx8mm_evk.h is
deleted because "run distro_bootcmd" is required to be the default boot
mode.

scriptaddr is the location in RAM where boot.scr.uimg/boot.scr will be
loaded to prior to execution.

kernel_addr_r is the location in RAM where the kernel will be loaded to.

Delete unnecessary environment variables.

Signed-off-by: Alice Guo 
---

Changes for v2:
 - remove supported boot device type QSPI
 - delete unnecessary environment variables
 - set "run distro_bootcmd" to be the default boot mode

 configs/imx8mm_evk_defconfig |  2 ++
 include/configs/imx8mm_evk.h | 67 +++-
 2 files changed, 14 insertions(+), 55 deletions(-)

diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig
index 91d3bc3ac9..4c0dd27e71 100644
--- a/configs/imx8mm_evk_defconfig
+++ b/configs/imx8mm_evk_defconfig
@@ -49,6 +49,8 @@ CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h
index 83521ad401..3bb2bcc287 100644
--- a/include/configs/imx8mm_evk.h
+++ b/include/configs/imx8mm_evk.h
@@ -32,69 +32,26 @@

 #endif

+#ifndef CONFIG_SPL_BUILD
+#define BOOT_TARGET_DEVICES(func) \
+   func(MMC, mmc, 1) \
+   func(MMC, mmc, 2) \
+   func(DHCP, dhcp, na)
+
+#include 
+#endif
+
 /* Initial environment variables */
 #define CONFIG_EXTRA_ENV_SETTINGS  \
-   "script=boot.scr\0" \
+   BOOTENV \
+   "scriptaddr=0x4350\0" \
+   "kernel_addr_r=0x4088\0" \
"image=Image\0" \
"console=ttymxc1,115200\0" \
"fdt_addr=0x4300\0" \
-   "boot_fit=no\0" \
"fdt_file=imx8mm-evk.dtb\0" \
-   "initrd_addr=0x4380\0"  \
-   "bootm_size=0x1000\0" \
-   "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
-   "mmcautodetect=yes\0" \
-   "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
-   "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} 
${script};\0" \
-   "bootscript=echo Running bootscript from mmc ...; " \
-   "source\0" \
-   "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
-   "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
-   "mmcboot=echo Booting from mmc ...; " \
-   "run mmcargs; " \
-   "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
-   "bootm ${loadaddr}; " \
-   "else " \
-   "if run loadfdt; then " \
-   "booti ${loadaddr} - ${fdt_addr}; " \
-   "else " \
-   "echo WARN: Cannot load the DT; " \
-   "fi; " \
-   "fi;\0" \
-   "netargs=setenv bootargs console=${console} " \
-   "root=/dev/nfs " \
-   "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
-   "netboot=echo Booting from net ...; " \
-   "run netargs;  " \
-   "if test ${ip_dyn} = yes; then " \
-   "setenv get_cmd dhcp; " \
-   "else " \
-   "setenv get_cmd tftp; " \
-   "fi; " \
-   "${get_cmd} ${loadaddr} ${image}; " \
-   "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
-   "bootm ${loadaddr}; " \
-   "else " \
-   "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
-   "booti ${loadaddr} - ${fdt_addr}; " \
-   "else " \
-   "echo WARN: Cannot load the DT; " \
-   "fi; " \
-   "fi;\0"
-
-#define CONFIG_BOOTCOMMAND \
-  "mmc dev ${mmcdev}; if mmc rescan; then " \
-  "if run loadbootscript; then " \
-  "run bootscript; " \
-  "else " \
-  "if run loadimage; then " \
-  "run mmcboot; " \
-  "else run netboot; " \
-  "fi; " \
-  "fi; " \
-  "fi;"

 /* Link Definitions */
 #define CONFIG_LOADADDR0x4048
--
2.17.1

[PATCH v2 2/2] board: imx8mm: add boot.cmd for distro boot on iMX8MM

2020-12-15 Thread Alice Guo (OSS)

From: Alice Guo 

Distro Boot requires a U-Boot-specific script named boot.scr or
boot.scr.uimg which contains boot commands to boot the system. The
boot.cmd is such a file. Use mkimage to generate boot.scr or
boot.scr.uimg from boot.cmd, and the command is:
mkimage -A arm -O linux -T script -C none -a 0 -e 0 -n "Distro Boot Script" -d 
boot.cmd boot.scr.uimg

The boot.cmd file is an example script and can be modified based on
needs. bootargs is set in this script and root uses the default value "
/dev/mmcblk1p2 rootwait rw" which can be changed by overriding mmcroot.

Signed-off-by: Alice Guo 
---

Changes for v2:
 - add the additional explanation of boot.cmd in commit message

 board/freescale/imx8mm_evk/boot.cmd | 35 +
 1 file changed, 35 insertions(+)
 create mode 100644 board/freescale/imx8mm_evk/boot.cmd

diff --git a/board/freescale/imx8mm_evk/boot.cmd 
b/board/freescale/imx8mm_evk/boot.cmd
new file mode 100644
index 00..fdfceec263
--- /dev/null
+++ b/board/freescale/imx8mm_evk/boot.cmd
@@ -0,0 +1,35 @@
+setenv bootargs console=${console} root=${mmcroot};
+
+for boot_target in ${boot_targets};
+do
+if test "${boot_target}" = "mmc1" ; then
+if fatload mmc 1:${mmcpart} ${kernel_addr_r} ${image}; then
+if fatload mmc 1:${mmcpart} ${fdt_addr} ${fdt_file}; 
then
+echo Load image and .dtb from SD card(mmc1);
+booti ${kernel_addr_r} - ${fdt_addr};
+exit;
+fi
+fi
+fi
+
+if test "${boot_target}" = "mmc2" ; then
+if fatload mmc 2:${mmcpart} ${kernel_addr_r} ${image}; then
+if fatload mmc 2:${mmcpart} ${fdt_addr} ${fdt_file}; 
then
+echo Load image and .dtb from eMMC(mmc2);
+booti ${kernel_addr_r} - ${fdt_addr};
+exit;
+fi
+fi
+fi
+
+if test "${boot_target}" = "dhcp" ; then
+if dhcp ${kernel_addr_r} ${serverip}:${image}; then
+if dhcp ${fdt_addr} ${serverip}:${fdt_file}; then
+echo Load image and .dtb from net(dhcp);
+booti ${kernel_addr_r} - ${fdt_addr};
+exit;
+fi
+fi
+fi
+
+done
--
2.17.1

[PATCH v1 1/2] imx8mq: configs: add support for distro boot commands

2020-12-16 Thread Alice Guo (OSS)

From: Alice Guo 

Supported boot device types in iMX8MQ: MMC, DHCP.

CONFIG_CMD_PART is added for command part and CONFIG_CMD_FS_GENERIC is
for command fstype.

scriptaddr is the location in RAM where boot.scr.uimg/boot.scr will be
loaded to prior to execution.

kernel_addr_r is the location in RAM where the kernel will be loaded to.

Delete unnecessary environment variables because "run distro_bootcmd" is
set to be the default boot mode.

Signed-off-by: Alice Guo 
---
 configs/imx8mq_evk_defconfig |  2 +
 include/configs/imx8mq_evk.h | 78 ++--
 2 files changed, 14 insertions(+), 66 deletions(-)

diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig
index de91a76d41..901841ea36 100644
--- a/configs/imx8mq_evk_defconfig
+++ b/configs/imx8mq_evk_defconfig
@@ -36,6 +36,8 @@ CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h
index 3f9a3bc100..1f740f0745 100644
--- a/include/configs/imx8mq_evk.h
+++ b/include/configs/imx8mq_evk.h
@@ -74,80 +74,26 @@
 #define IMX_FEC_BASE   0x30BE
 #endif

-#define CONFIG_MFG_ENV_SETTINGS \
-   "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
-   "rdinit=/linuxrc " \
-   "g_mass_storage.stall=0 g_mass_storage.removable=1 " \
-   "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF 
"\
-   "g_mass_storage.iSerialNumber=\"\" "\
-   "clk_ignore_unused "\
-   "\0" \
-   "initrd_addr=0x4380\0" \
-   "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} 
${fdt_addr};\0" \
+#ifndef CONFIG_SPL_BUILD
+#define BOOT_TARGET_DEVICES(func) \
+   func(MMC, mmc, 0) \
+   func(MMC, mmc, 1) \
+   func(DHCP, dhcp, na)
+
+#include 
+#endif
+
 /* Initial environment variables */
 #define CONFIG_EXTRA_ENV_SETTINGS  \
-   CONFIG_MFG_ENV_SETTINGS \
-   "script=boot.scr\0" \
+   BOOTENV \
+   "scriptaddr=0x4350\0" \
+   "kernel_addr_r=0x4088\0" \
"image=Image\0" \
"console=ttymxc0,115200\0" \
"fdt_addr=0x4300\0" \
-   "boot_fdt=try\0" \
"fdt_file=imx8mq-evk.dtb\0" \
-   "initrd_addr=0x4380\0"  \
-   "bootm_size=0x1000\0" \
-   "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
-   "mmcautodetect=yes\0" \
-   "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
-   "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} 
${script};\0" \
-   "bootscript=echo Running bootscript from mmc ...; " \
-   "source\0" \
-   "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
-   "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
-   "mmcboot=echo Booting from mmc ...; " \
-   "run mmcargs; " \
-   "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-   "if run loadfdt; then " \
-   "booti ${loadaddr} - ${fdt_addr}; " \
-   "else " \
-   "echo WARN: Cannot load the DT; " \
-   "fi; " \
-   "else " \
-   "echo wait for boot; " \
-   "fi;\0" \
-   "netargs=setenv bootargs console=${console} " \
-   "root=/dev/nfs " \
-   "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
-   "netboot=echo Booting from net ...; " \
-   "run netargs;  " \
-   "if test ${ip_dyn} = yes; then " \
-   "setenv get_cmd dhcp; " \
-   "else " \
-   "setenv get_cmd tftp; " \
-   "fi; " \
-   "${get_cmd} ${loadaddr} ${image}; " \
-   "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-   "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
-   "booti ${loadaddr} - ${fdt_addr}; " \
-   "else " \
-   "echo WARN: Cannot load the DT; " \
-   "fi; " \
-   "else " \
-   "booti; " \
-   "fi;\0"
-
-#define CONFIG_BOOTCOMMAND \
-  "mmc dev ${mmcdev}; if mmc rescan; then " \
-  "if run loadbootscript; then " \
-  "run bootscript; " \
-  "else " \
-  "if run loadimage; then " \
-  "run mmcboot; " \
-  "else run netboot; " \
-  "fi; " \
-

[PATCH v1 2/2] board: imx8mq: add boot.cmd for distro boot on iMX8MQ

2020-12-16 Thread Alice Guo (OSS)

From: Alice Guo 

Distro Boot requires a U-Boot-specific script named boot.scr or
boot.scr.uimg which contains boot commands to boot the system. The
boot.cmd is such a file. Use mkimage to generate boot.scr or
boot.scr.uimg from boot.cmd, and the command is:
mkimage -A arm -O linux -T script -C none -a 0 -e 0 -n "Distro Boot Script" -d 
boot.cmd boot.scr.uimg

The boot.cmd file is an example script and can be modified based on
needs. bootargs is set in this script and root uses the default value
"/dev/mmcblk1p2 rootwait rw" which can be changed by overriding mmcroot.

On the iMX8MQ platform I used, "mmc0" represents eMMC and "mmc1"
represents SD card.

Signed-off-by: Alice Guo 
---
 board/freescale/imx8mq_evk/boot.cmd | 35 +
 1 file changed, 35 insertions(+)
 create mode 100644 board/freescale/imx8mq_evk/boot.cmd

diff --git a/board/freescale/imx8mq_evk/boot.cmd 
b/board/freescale/imx8mq_evk/boot.cmd
new file mode 100644
index 00..964993e144
--- /dev/null
+++ b/board/freescale/imx8mq_evk/boot.cmd
@@ -0,0 +1,35 @@
+setenv bootargs console=${console} root=${mmcroot};
+
+for boot_target in ${boot_targets};
+do
+if test "${boot_target}" = "mmc0" ; then
+if fatload mmc 0:${mmcpart} ${kernel_addr_r} ${image}; then
+if fatload mmc 0:${mmcpart} ${fdt_addr} ${fdt_file}; 
then
+echo Load image and .dtb from eMMC(mmc0);
+booti ${kernel_addr_r} - ${fdt_addr};
+exit;
+fi
+fi
+fi
+
+if test "${boot_target}" = "mmc1" ; then
+if fatload mmc 1:${mmcpart} ${kernel_addr_r} ${image}; then
+if fatload mmc 1:${mmcpart} ${fdt_addr} ${fdt_file}; 
then
+echo Load image and .dtb from SD card(mmc1);
+booti ${kernel_addr_r} - ${fdt_addr};
+exit;
+fi
+fi
+fi
+
+if test "${boot_target}" = "dhcp" ; then
+if dhcp ${kernel_addr_r} ${serverip}:${image}; then
+if dhcp ${fdt_addr} ${serverip}:${fdt_file}; then
+echo Load image and .dtb from net(dhcp);
+booti ${kernel_addr_r} - ${fdt_addr};
+exit;
+fi
+fi
+fi
+
+done
--
2.17.1

[PATCH v1 1/2] imx8mp: configs: add support for distro boot commands

2020-12-17 Thread Alice Guo (OSS)

From: Alice Guo 

Supported boot device types in iMX8MP: MMC.

CONFIG_CMD_PART is added for command part and CONFIG_CMD_FS_GENERIC is
for command fstype.

scriptaddr is the location in RAM where boot.scr.uimg/boot.scr will be
loaded to prior to execution. kernel_addr_r is the location in RAM where
the kernel will be loaded to. Delete unnecessary environment variables
because "run distro_bootcmd" is set to be the default boot mode.

On the iMX8MP platform I used, "mmc1" represents SD card and "mmc2"
represents eMMC.

Signed-off-by: Alice Guo 
---
 configs/imx8mp_evk_defconfig |  2 ++
 include/configs/imx8mp_evk.h | 66 ++--
 2 files changed, 13 insertions(+), 55 deletions(-)

diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig
index cd5724e811..7831a940a3 100644
--- a/configs/imx8mp_evk_defconfig
+++ b/configs/imx8mp_evk_defconfig
@@ -51,6 +51,8 @@ CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h
index 8253c6aa2f..70f5fb2928 100644
--- a/include/configs/imx8mp_evk.h
+++ b/include/configs/imx8mp_evk.h
@@ -44,69 +44,25 @@

 #endif

+#ifndef CONFIG_SPL_BUILD
+#define BOOT_TARGET_DEVICES(func) \
+   func(MMC, mmc, 1) \
+   func(MMC, mmc, 2)
+
+#include 
+#endif
+
 /* Initial environment variables */
 #define CONFIG_EXTRA_ENV_SETTINGS  \
-   "script=boot.scr\0" \
+   BOOTENV \
+   "scriptaddr=0x4350\0" \
+   "kernel_addr_r=0x4088\0" \
"image=Image\0" \
"console=ttymxc1,115200 earlycon=ec_imx6q,0x3089,115200\0" \
"fdt_addr=0x4300\0" \
-   "boot_fdt=try\0" \
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
-   "initrd_addr=0x4380\0"  \
-   "bootm_size=0x1000\0" \
-   "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
-   "mmcautodetect=yes\0" \
-   "mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 
" \
-   "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} 
${script};\0" \
-   "bootscript=echo Running bootscript from mmc ...; " \
-   "source\0" \
-   "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
-   "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
-   "mmcboot=echo Booting from mmc ...; " \
-   "run mmcargs; " \
-   "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-   "if run loadfdt; then " \
-   "booti ${loadaddr} - ${fdt_addr}; " \
-   "else " \
-   "echo WARN: Cannot load the DT; " \
-   "fi; " \
-   "else " \
-   "echo wait for boot; " \
-   "fi;\0" \
-   "netargs=setenv bootargs ${jh_clk} console=${console} " \
-   "root=/dev/nfs " \
-   "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
-   "netboot=echo Booting from net ...; " \
-   "run netargs;  " \
-   "if test ${ip_dyn} = yes; then " \
-   "setenv get_cmd dhcp; " \
-   "else " \
-   "setenv get_cmd tftp; " \
-   "fi; " \
-   "${get_cmd} ${loadaddr} ${image}; " \
-   "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-   "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
-   "booti ${loadaddr} - ${fdt_addr}; " \
-   "else " \
-   "echo WARN: Cannot load the DT; " \
-   "fi; " \
-   "else " \
-   "booti; " \
-   "fi;\0"
-
-#define CONFIG_BOOTCOMMAND \
-  "mmc dev ${mmcdev}; if mmc rescan; then " \
-  "if run loadbootscript; then " \
-  "run bootscript; " \
-  "else " \
-  "if run loadimage; then " \
-  "run mmcboot; " \
-  "else run netboot; " \
-  "fi; " \
-  "fi; " \
-  "else booti ${loadaddr} - ${fdt_addr}; fi"

 /* Link Definitions */
 #define CONFIG_LOADADDR0x4048
--
2.17.1

[PATCH v1 2/2] board: imx8mp: add boot.cmd for distro boot on iMX8MP

2020-12-17 Thread Alice Guo (OSS)

From: Alice Guo 

Distro Boot requires a U-Boot-specific script named boot.scr or
boot.scr.uimg which contains boot commands to boot the system. The
boot.cmd is such a file. Use mkimage to generate boot.scr or
boot.scr.uimg from boot.cmd, and the command is:
mkimage -A arm -O linux -T script -C none -a 0 -e 0 -n "Distro Boot Script" -d 
boot.cmd boot.scr.uimg

The boot.cmd file is an example script and can be modified based on
needs. bootargs is set in this script and root uses the default value
"/dev/mmcblk1p2 rootwait rw" which can be changed by overriding mmcroot.

Signed-off-by: Alice Guo 
---
 board/freescale/imx8mp_evk/boot.cmd | 25 +
 1 file changed, 25 insertions(+)
 create mode 100644 board/freescale/imx8mp_evk/boot.cmd

diff --git a/board/freescale/imx8mp_evk/boot.cmd 
b/board/freescale/imx8mp_evk/boot.cmd
new file mode 100644
index 00..10bcced774
--- /dev/null
+++ b/board/freescale/imx8mp_evk/boot.cmd
@@ -0,0 +1,25 @@
+setenv bootargs console=${console} root=${mmcroot};
+
+for boot_target in ${boot_targets};
+do
+if test "${boot_target}" = "mmc1" ; then
+if fatload mmc 1:${mmcpart} ${kernel_addr_r} ${image}; then
+if fatload mmc 1:${mmcpart} ${fdt_addr} ${fdt_file}; 
then
+echo Load image and .dtb from SD card(mmc1);
+booti ${kernel_addr_r} - ${fdt_addr};
+exit;
+fi
+fi
+fi
+
+if test "${boot_target}" = "mmc2" ; then
+if fatload mmc 2:${mmcpart} ${kernel_addr_r} ${image}; then
+if fatload mmc 2:${mmcpart} ${fdt_addr} ${fdt_file}; 
then
+echo Load image and .dtb from eMMC(mmc2);
+booti ${kernel_addr_r} - ${fdt_addr};
+exit;
+fi
+fi
+fi
+
+done
--
2.17.1

RE: [EXT] RE: [PATCH v1 1/2] imx8mp: configs: add support for distro boot commands

2020-12-17 Thread Alice Guo (OSS)



> -Original Message-
> From: ZHIZHIKIN Andrey 
> Sent: 2020年12月17日 19:21
> To: Alice Guo (OSS) ; sba...@denx.de;
> feste...@gmail.com; Peng Fan 
> Cc: dl-uboot-imx ; Ye Li ;
> u-boot@lists.denx.de; Alice Guo 
> Subject: [EXT] RE: [PATCH v1 1/2] imx8mp: configs: add support for distro boot
> commands
> 
> Caution: EXT Email
> 
> Hello Alice,
> 
> > -Original Message-
> > From: U-Boot  On Behalf Of Alice Guo
> > (OSS)
> > Sent: Thursday, December 17, 2020 11:29 AM
> > To: sba...@denx.de; feste...@gmail.com; peng@nxp.com
> > Cc: uboot-...@nxp.com; ye...@nxp.com; u-boot@lists.denx.de; Alice Guo
> > 
> > Subject: [PATCH v1 1/2] imx8mp: configs: add support for distro boot
> > commands
> >
> > From: Alice Guo 
> >
> > Supported boot device types in iMX8MP: MMC.
> >
> > CONFIG_CMD_PART is added for command part and
> CONFIG_CMD_FS_GENERIC is
> > for command fstype.
> >
> > scriptaddr is the location in RAM where boot.scr.uimg/boot.scr will be
> > loaded to prior to execution. kernel_addr_r is the location in RAM
> > where the kernel will be loaded to. Delete unnecessary environment
> > variables because "run distro_bootcmd" is set to be the default boot mode.
> >
> > On the iMX8MP platform I used, "mmc1" represents SD card and "mmc2"
> > represents eMMC.
> >
> > Signed-off-by: Alice Guo 
> > ---
> >  configs/imx8mp_evk_defconfig |  2 ++
> >  include/configs/imx8mp_evk.h | 66
> > ++--
> >  2 files changed, 13 insertions(+), 55 deletions(-)
> >
> > diff --git a/configs/imx8mp_evk_defconfig
> > b/configs/imx8mp_evk_defconfig index cd5724e811..7831a940a3 100644
> > --- a/configs/imx8mp_evk_defconfig
> > +++ b/configs/imx8mp_evk_defconfig
> > @@ -51,6 +51,8 @@ CONFIG_CMD_EXT2=y
> >  CONFIG_CMD_EXT4=y
> >  CONFIG_CMD_EXT4_WRITE=y
> >  CONFIG_CMD_FAT=y
> > +CONFIG_CMD_PART=y
> > +CONFIG_CMD_FS_GENERIC=y
> >  CONFIG_OF_CONTROL=y
> >  CONFIG_SPL_OF_CONTROL=y
> >  CONFIG_ENV_OVERWRITE=y
> > diff --git a/include/configs/imx8mp_evk.h
> > b/include/configs/imx8mp_evk.h index 8253c6aa2f..70f5fb2928 100644
> > --- a/include/configs/imx8mp_evk.h
> > +++ b/include/configs/imx8mp_evk.h
> > @@ -44,69 +44,25 @@
> >
> >  #endif
> >
> > +#ifndef CONFIG_SPL_BUILD
> > +#define BOOT_TARGET_DEVICES(func) \
> > +   func(MMC, mmc, 1) \
> > +   func(MMC, mmc, 2)
> > +
> > +#include 
> > +#endif
> > +
> >  /* Initial environment variables */
> >  #define CONFIG_EXTRA_ENV_SETTINGS  \
> > -   "script=boot.scr\0" \
> > +   BOOTENV \
> > +   "scriptaddr=0x4350\0" \
> > +   "kernel_addr_r=0x4088\0" \
> > "image=Image\0" \
> > "console=ttymxc1,115200
> earlycon=ec_imx6q,0x3089,115200\0" \
> > "fdt_addr=0x4300\0" \
> > -   "boot_fdt=try\0" \
> > "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
> > -   "initrd_addr=0x4380\0"  \
> > -   "bootm_size=0x1000\0" \
> 
> I believe that without proper bootm_size set, FIT image cannot be loaded
> correctly.
> 
> Commit acbc1d86f1 ("imx8m: config: convert to bootm_size") had this
> addressed, and removing the "bootm_size" would break FIT load again.
> 
> Have you tested your implementation with "bootm" in boot script? So far, I see
> that only "booti" has been used.

Hi,
Thank you for your advice. I have no need to support FIT image so that I did 
not notice this problem.
I will check and modify it.

Best Regards,
Alice

> > -   "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
> > "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART)
> "\0" \
> > "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
> > -   "mmcautodetect=yes\0" \
> > -   "mmcargs=setenv bootargs ${jh_clk} console=${console}
> root=${mmcroot}\0
> > " \
> > -   "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}
> > ${script};\0" \
> > -   "bootscript=echo Running bootscript from mmc ...; " \
> > -   "source\0" \
> > -   "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}
> ${image}\0" \
> > -   &quo

[PATCH v3 1/2] imx8mm: configs: add support for distro boot commands

2020-12-17 Thread Alice Guo (OSS)

From: Alice Guo 

Supported boot device types in iMX8MM: MMC, DHCP.

CONFIG_CMD_PART is added for command part and CONFIG_CMD_FS_GENERIC is
for command fstype.

CONFIG_BOOTCOMMAND which is defined in include/configs/imx8mm_evk.h is
deleted because "run distro_bootcmd" is required to be the default boot
mode.

scriptaddr is the location in RAM where boot.scr.uimg/boot.scr will be
loaded to prior to execution.

kernel_addr_r is the location in RAM where the kernel will be loaded to.

Delete unnecessary environment variables.

Reviewed-by: Peng Fan 
Signed-off-by: Alice Guo 
---

Changes for v3:
 - add Reviewed-by
 - re-add boot_fit, initrd_addr and bootm_size which may need to be used
Changes for v2:
 - remove supported boot device type QSPI
 - delete unnecessary environment variables
 - set "run distro_bootcmd" to be the default boot mode

 configs/imx8mm_evk_defconfig |  2 ++
 include/configs/imx8mm_evk.h | 64 +++-
 2 files changed, 14 insertions(+), 52 deletions(-)

diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig
index 91d3bc3ac9..4c0dd27e71 100644
--- a/configs/imx8mm_evk_defconfig
+++ b/configs/imx8mm_evk_defconfig
@@ -49,6 +49,8 @@ CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h
index 83521ad401..6d4ae71f24 100644
--- a/include/configs/imx8mm_evk.h
+++ b/include/configs/imx8mm_evk.h
@@ -32,9 +32,20 @@

 #endif

+#ifndef CONFIG_SPL_BUILD
+#define BOOT_TARGET_DEVICES(func) \
+   func(MMC, mmc, 1) \
+   func(MMC, mmc, 2) \
+   func(DHCP, dhcp, na)
+
+#include 
+#endif
+
 /* Initial environment variables */
 #define CONFIG_EXTRA_ENV_SETTINGS  \
-   "script=boot.scr\0" \
+   BOOTENV \
+   "scriptaddr=0x4350\0" \
+   "kernel_addr_r=0x4088\0" \
"image=Image\0" \
"console=ttymxc1,115200\0" \
"fdt_addr=0x4300\0" \
@@ -42,59 +53,8 @@
"fdt_file=imx8mm-evk.dtb\0" \
"initrd_addr=0x4380\0"  \
"bootm_size=0x1000\0" \
-   "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
-   "mmcautodetect=yes\0" \
-   "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
-   "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} 
${script};\0" \
-   "bootscript=echo Running bootscript from mmc ...; " \
-   "source\0" \
-   "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
-   "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
-   "mmcboot=echo Booting from mmc ...; " \
-   "run mmcargs; " \
-   "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
-   "bootm ${loadaddr}; " \
-   "else " \
-   "if run loadfdt; then " \
-   "booti ${loadaddr} - ${fdt_addr}; " \
-   "else " \
-   "echo WARN: Cannot load the DT; " \
-   "fi; " \
-   "fi;\0" \
-   "netargs=setenv bootargs console=${console} " \
-   "root=/dev/nfs " \
-   "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
-   "netboot=echo Booting from net ...; " \
-   "run netargs;  " \
-   "if test ${ip_dyn} = yes; then " \
-   "setenv get_cmd dhcp; " \
-   "else " \
-   "setenv get_cmd tftp; " \
-   "fi; " \
-   "${get_cmd} ${loadaddr} ${image}; " \
-   "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
-   "bootm ${loadaddr}; " \
-   "else " \
-   "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
-   "booti ${loadaddr} - ${fdt_addr}; " \
-   "else " \
-   "echo WARN: Cannot load the DT; " \
-   "fi; " \
-   "fi;\0"
-
-#define CONFIG_BOOTCOMMAND \
-  "mmc dev ${mmcdev}; if mmc rescan; then " \
-  "if run loadbootscript; then " \
-  "run bootscript; " \
-  "else " \
-  "if run loadimage; then " \
-  "run mmcboot; " \
-  "else run netboot; " \
-  "fi; " \
-  "fi; " \
-  "fi;"

 /* Link Definitions */
 #define CONFIG_LOADADDR0x4048
--
2.17.1

[PATCH v3 2/2] board: imx8mm: add boot.cmd for distro boot on iMX8MM

2020-12-17 Thread Alice Guo (OSS)

From: Alice Guo 

Distro Boot requires a U-Boot-specific script named boot.scr or
boot.scr.uimg which contains boot commands to boot the system. The
boot.cmd is such a file. Use mkimage to generate boot.scr or
boot.scr.uimg from boot.cmd, and the command is:
mkimage -A arm -O linux -T script -C none -a 0 -e 0 -n "Distro Boot Script" -d 
boot.cmd boot.scr.uimg

The boot.cmd file is an example script and can be modified based on
needs. bootargs is set in this script and root uses the default value "
/dev/mmcblk1p2 rootwait rw" which can be changed by overriding mmcroot.

Reviewed-by: Peng Fan 
Signed-off-by: Alice Guo 
---

Changes for v3:
 - add Reviewed-by
Changes for v2:
 - add the additional explanation of boot.cmd in commit message

 board/freescale/imx8mm_evk/boot.cmd | 35 +
 1 file changed, 35 insertions(+)
 create mode 100644 board/freescale/imx8mm_evk/boot.cmd

diff --git a/board/freescale/imx8mm_evk/boot.cmd 
b/board/freescale/imx8mm_evk/boot.cmd
new file mode 100644
index 00..fdfceec263
--- /dev/null
+++ b/board/freescale/imx8mm_evk/boot.cmd
@@ -0,0 +1,35 @@
+setenv bootargs console=${console} root=${mmcroot};
+
+for boot_target in ${boot_targets};
+do
+if test "${boot_target}" = "mmc1" ; then
+if fatload mmc 1:${mmcpart} ${kernel_addr_r} ${image}; then
+if fatload mmc 1:${mmcpart} ${fdt_addr} ${fdt_file}; 
then
+echo Load image and .dtb from SD card(mmc1);
+booti ${kernel_addr_r} - ${fdt_addr};
+exit;
+fi
+fi
+fi
+
+if test "${boot_target}" = "mmc2" ; then
+if fatload mmc 2:${mmcpart} ${kernel_addr_r} ${image}; then
+if fatload mmc 2:${mmcpart} ${fdt_addr} ${fdt_file}; 
then
+echo Load image and .dtb from eMMC(mmc2);
+booti ${kernel_addr_r} - ${fdt_addr};
+exit;
+fi
+fi
+fi
+
+if test "${boot_target}" = "dhcp" ; then
+if dhcp ${kernel_addr_r} ${serverip}:${image}; then
+if dhcp ${fdt_addr} ${serverip}:${fdt_file}; then
+echo Load image and .dtb from net(dhcp);
+booti ${kernel_addr_r} - ${fdt_addr};
+exit;
+fi
+fi
+fi
+
+done
--
2.17.1

[PATCH v2 2/2] board: imx8mq: add boot.cmd for distro boot on iMX8MQ

2020-12-17 Thread Alice Guo (OSS)

From: Alice Guo 

Distro Boot requires a U-Boot-specific script named boot.scr or
boot.scr.uimg which contains boot commands to boot the system. The
boot.cmd is such a file. Use mkimage to generate boot.scr or
boot.scr.uimg from boot.cmd, and the command is:
mkimage -A arm -O linux -T script -C none -a 0 -e 0 -n "Distro Boot Script" -d 
boot.cmd boot.scr.uimg

The boot.cmd file is an example script and can be modified based on
needs. bootargs is set in this script and root uses the default value
"/dev/mmcblk1p2 rootwait rw" which can be changed by overriding mmcroot.

On the iMX8MQ platform I used, "mmc0" represents eMMC and "mmc1"
represents SD card.

Signed-off-by: Alice Guo 
---

Changes for v2:
 - none

 board/freescale/imx8mq_evk/boot.cmd | 35 +
 1 file changed, 35 insertions(+)
 create mode 100644 board/freescale/imx8mq_evk/boot.cmd

diff --git a/board/freescale/imx8mq_evk/boot.cmd 
b/board/freescale/imx8mq_evk/boot.cmd
new file mode 100644
index 00..964993e144
--- /dev/null
+++ b/board/freescale/imx8mq_evk/boot.cmd
@@ -0,0 +1,35 @@
+setenv bootargs console=${console} root=${mmcroot};
+
+for boot_target in ${boot_targets};
+do
+if test "${boot_target}" = "mmc0" ; then
+if fatload mmc 0:${mmcpart} ${kernel_addr_r} ${image}; then
+if fatload mmc 0:${mmcpart} ${fdt_addr} ${fdt_file}; 
then
+echo Load image and .dtb from eMMC(mmc0);
+booti ${kernel_addr_r} - ${fdt_addr};
+exit;
+fi
+fi
+fi
+
+if test "${boot_target}" = "mmc1" ; then
+if fatload mmc 1:${mmcpart} ${kernel_addr_r} ${image}; then
+if fatload mmc 1:${mmcpart} ${fdt_addr} ${fdt_file}; 
then
+echo Load image and .dtb from SD card(mmc1);
+booti ${kernel_addr_r} - ${fdt_addr};
+exit;
+fi
+fi
+fi
+
+if test "${boot_target}" = "dhcp" ; then
+if dhcp ${kernel_addr_r} ${serverip}:${image}; then
+if dhcp ${fdt_addr} ${serverip}:${fdt_file}; then
+echo Load image and .dtb from net(dhcp);
+booti ${kernel_addr_r} - ${fdt_addr};
+exit;
+fi
+fi
+fi
+
+done
--
2.17.1

[PATCH v2 1/2] imx8mq: configs: add support for distro boot commands

2020-12-17 Thread Alice Guo (OSS)

From: Alice Guo 

Supported boot device types in iMX8MQ: MMC, DHCP.

CONFIG_CMD_PART is added for command part and CONFIG_CMD_FS_GENERIC is
for command fstype.

scriptaddr is the location in RAM where boot.scr.uimg/boot.scr will be
loaded to prior to execution.

kernel_addr_r is the location in RAM where the kernel will be loaded to.

Delete unnecessary environment variables because "run distro_bootcmd" is
set to be the default boot mode.

Signed-off-by: Alice Guo 
---

Changes for v2:
 - re-add boot_fit, initrd_addr and bootm_size which may need to be used

 configs/imx8mq_evk_defconfig |  2 +
 include/configs/imx8mq_evk.h | 76 ++--
 2 files changed, 14 insertions(+), 64 deletions(-)

diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig
index de91a76d41..901841ea36 100644
--- a/configs/imx8mq_evk_defconfig
+++ b/configs/imx8mq_evk_defconfig
@@ -36,6 +36,8 @@ CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h
index 3f9a3bc100..eb5bc03403 100644
--- a/include/configs/imx8mq_evk.h
+++ b/include/configs/imx8mq_evk.h
@@ -74,80 +74,28 @@
 #define IMX_FEC_BASE   0x30BE
 #endif

-#define CONFIG_MFG_ENV_SETTINGS \
-   "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
-   "rdinit=/linuxrc " \
-   "g_mass_storage.stall=0 g_mass_storage.removable=1 " \
-   "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF 
"\
-   "g_mass_storage.iSerialNumber=\"\" "\
-   "clk_ignore_unused "\
-   "\0" \
-   "initrd_addr=0x4380\0" \
-   "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} 
${fdt_addr};\0" \
+#ifndef CONFIG_SPL_BUILD
+#define BOOT_TARGET_DEVICES(func) \
+   func(MMC, mmc, 0) \
+   func(MMC, mmc, 1) \
+   func(DHCP, dhcp, na)
+
+#include 
+#endif
+
 /* Initial environment variables */
 #define CONFIG_EXTRA_ENV_SETTINGS  \
-   CONFIG_MFG_ENV_SETTINGS \
-   "script=boot.scr\0" \
+   BOOTENV \
+   "scriptaddr=0x4350\0" \
+   "kernel_addr_r=0x4088\0" \
"image=Image\0" \
"console=ttymxc0,115200\0" \
"fdt_addr=0x4300\0" \
-   "boot_fdt=try\0" \
"fdt_file=imx8mq-evk.dtb\0" \
"initrd_addr=0x4380\0"  \
"bootm_size=0x1000\0" \
-   "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
-   "mmcautodetect=yes\0" \
-   "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
-   "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} 
${script};\0" \
-   "bootscript=echo Running bootscript from mmc ...; " \
-   "source\0" \
-   "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
-   "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
-   "mmcboot=echo Booting from mmc ...; " \
-   "run mmcargs; " \
-   "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-   "if run loadfdt; then " \
-   "booti ${loadaddr} - ${fdt_addr}; " \
-   "else " \
-   "echo WARN: Cannot load the DT; " \
-   "fi; " \
-   "else " \
-   "echo wait for boot; " \
-   "fi;\0" \
-   "netargs=setenv bootargs console=${console} " \
-   "root=/dev/nfs " \
-   "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
-   "netboot=echo Booting from net ...; " \
-   "run netargs;  " \
-   "if test ${ip_dyn} = yes; then " \
-   "setenv get_cmd dhcp; " \
-   "else " \
-   "setenv get_cmd tftp; " \
-   "fi; " \
-   "${get_cmd} ${loadaddr} ${image}; " \
-   "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-   "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
-   "booti ${loadaddr} - ${fdt_addr}; " \
-   "else " \
-   "echo WARN: Cannot load the DT; " \
-   "fi; " \
-   "else " \
-   "booti; " \
-   "fi;\0"
-
-#define CONFIG_BOOTCOMMAND \
-  "mmc dev ${mmcdev}; if mmc rescan; then " \
-  "if run loadbootscript; then " \
-  "run bootscript; " \
-  "else " \
-  "if run loadimage; then " \
-  "run mmcboot; " \

[PATCH v2 1/2] imx8mp: configs: add support for distro boot commands

2020-12-17 Thread Alice Guo (OSS)

From: Alice Guo 

Supported boot device types in iMX8MP: MMC.

CONFIG_CMD_PART is added for command part and CONFIG_CMD_FS_GENERIC is
for command fstype.

scriptaddr is the location in RAM where boot.scr.uimg/boot.scr will be
loaded to prior to execution. kernel_addr_r is the location in RAM where
the kernel will be loaded to. Delete unnecessary environment variables
because "run distro_bootcmd" is set to be the default boot mode.

On the iMX8MP platform I used, "mmc1" represents SD card and "mmc2"
represents eMMC.

Signed-off-by: Alice Guo 
---

Changes for v2:
 - re-add boot_fit, initrd_addr and bootm_size which may need to be used

 configs/imx8mp_evk_defconfig |  2 ++
 include/configs/imx8mp_evk.h | 63 +++-
 2 files changed, 13 insertions(+), 52 deletions(-)

diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig
index cd5724e811..7831a940a3 100644
--- a/configs/imx8mp_evk_defconfig
+++ b/configs/imx8mp_evk_defconfig
@@ -51,6 +51,8 @@ CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h
index 8253c6aa2f..fd7ec45b16 100644
--- a/include/configs/imx8mp_evk.h
+++ b/include/configs/imx8mp_evk.h
@@ -44,9 +44,19 @@

 #endif

+#ifndef CONFIG_SPL_BUILD
+#define BOOT_TARGET_DEVICES(func) \
+   func(MMC, mmc, 1) \
+   func(MMC, mmc, 2)
+
+#include 
+#endif
+
 /* Initial environment variables */
 #define CONFIG_EXTRA_ENV_SETTINGS  \
-   "script=boot.scr\0" \
+   BOOTENV \
+   "scriptaddr=0x4350\0" \
+   "kernel_addr_r=0x4088\0" \
"image=Image\0" \
"console=ttymxc1,115200 earlycon=ec_imx6q,0x3089,115200\0" \
"fdt_addr=0x4300\0" \
@@ -54,59 +64,8 @@
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
"initrd_addr=0x4380\0"  \
"bootm_size=0x1000\0" \
-   "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
-   "mmcautodetect=yes\0" \
-   "mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 
" \
-   "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} 
${script};\0" \
-   "bootscript=echo Running bootscript from mmc ...; " \
-   "source\0" \
-   "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
-   "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
-   "mmcboot=echo Booting from mmc ...; " \
-   "run mmcargs; " \
-   "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-   "if run loadfdt; then " \
-   "booti ${loadaddr} - ${fdt_addr}; " \
-   "else " \
-   "echo WARN: Cannot load the DT; " \
-   "fi; " \
-   "else " \
-   "echo wait for boot; " \
-   "fi;\0" \
-   "netargs=setenv bootargs ${jh_clk} console=${console} " \
-   "root=/dev/nfs " \
-   "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
-   "netboot=echo Booting from net ...; " \
-   "run netargs;  " \
-   "if test ${ip_dyn} = yes; then " \
-   "setenv get_cmd dhcp; " \
-   "else " \
-   "setenv get_cmd tftp; " \
-   "fi; " \
-   "${get_cmd} ${loadaddr} ${image}; " \
-   "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-   "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
-   "booti ${loadaddr} - ${fdt_addr}; " \
-   "else " \
-   "echo WARN: Cannot load the DT; " \
-   "fi; " \
-   "else " \
-   "booti; " \
-   "fi;\0"
-
-#define CONFIG_BOOTCOMMAND \
-  "mmc dev ${mmcdev}; if mmc rescan; then " \
-  "if run loadbootscript; then " \
-  "run bootscript; " \
-  "else " \
-  "if run loadimage; then " \
-  "run mmcboot; " \
-  "else run netboot; " \
-  "fi; " \
-  "fi; " \
-  "else booti ${loadaddr} - ${fdt_addr}; fi"

 /* Link Definitions */
 #define CONFIG_LOADADDR0x4048
--
2.17.1

[PATCH v2 2/2] board: imx8mp: add boot.cmd for distro boot on iMX8MP

2020-12-17 Thread Alice Guo (OSS)

From: Alice Guo 

Distro Boot requires a U-Boot-specific script named boot.scr or
boot.scr.uimg which contains boot commands to boot the system. The
boot.cmd is such a file. Use mkimage to generate boot.scr or
boot.scr.uimg from boot.cmd, and the command is:
mkimage -A arm -O linux -T script -C none -a 0 -e 0 -n "Distro Boot Script" -d 
boot.cmd boot.scr.uimg

The boot.cmd file is an example script and can be modified based on
needs. bootargs is set in this script and root uses the default value
"/dev/mmcblk1p2 rootwait rw" which can be changed by overriding mmcroot.

Signed-off-by: Alice Guo 
---

Changes for v2:
 - none

 board/freescale/imx8mp_evk/boot.cmd | 25 +
 1 file changed, 25 insertions(+)
 create mode 100644 board/freescale/imx8mp_evk/boot.cmd

diff --git a/board/freescale/imx8mp_evk/boot.cmd 
b/board/freescale/imx8mp_evk/boot.cmd
new file mode 100644
index 00..10bcced774
--- /dev/null
+++ b/board/freescale/imx8mp_evk/boot.cmd
@@ -0,0 +1,25 @@
+setenv bootargs console=${console} root=${mmcroot};
+
+for boot_target in ${boot_targets};
+do
+if test "${boot_target}" = "mmc1" ; then
+if fatload mmc 1:${mmcpart} ${kernel_addr_r} ${image}; then
+if fatload mmc 1:${mmcpart} ${fdt_addr} ${fdt_file}; 
then
+echo Load image and .dtb from SD card(mmc1);
+booti ${kernel_addr_r} - ${fdt_addr};
+exit;
+fi
+fi
+fi
+
+if test "${boot_target}" = "mmc2" ; then
+if fatload mmc 2:${mmcpart} ${kernel_addr_r} ${image}; then
+if fatload mmc 2:${mmcpart} ${fdt_addr} ${fdt_file}; 
then
+echo Load image and .dtb from eMMC(mmc2);
+booti ${kernel_addr_r} - ${fdt_addr};
+exit;
+fi
+fi
+fi
+
+done
--
2.17.1

RE: [EXT] Re: [PATCH v2 2/2] board: imx8mp: add boot.cmd for distro boot on iMX8MP

2020-12-18 Thread Alice Guo (OSS)



> -Original Message-
> From: Fabio Estevam 
> Sent: 2020年12月18日 19:03
> To: Alice Guo (OSS) 
> Cc: Stefano Babic ; Peng Fan ;
> dl-uboot-imx ; Ye Li ; U-Boot-Denx
> ; Alice Guo ; Otavio Salvador
> ; andrey.zhizhi...@leica-geosystems.com
> Subject: [EXT] Re: [PATCH v2 2/2] board: imx8mp: add boot.cmd for distro boot
> on iMX8MP
> 
> Caution: EXT Email
> 
> Hi Alice,
> 
> On Fri, Dec 18, 2020 at 4:20 AM Alice Guo (OSS) 
> wrote:
> 
> > +++ b/board/freescale/imx8mp_evk/boot.cmd
> > @@ -0,0 +1,25 @@
> > +setenv bootargs console=${console} root=${mmcroot};
> > +
> > +for boot_target in ${boot_targets};
> 
> This is not how distro boot support works.
> 
> boot.scr or extlinux.conf scripts should be provided by the distro itself 
> (Yocto,
> Buildroot, Debian, etc), and not from U-Boot.
> 
> Each distro has its own partitioning mechanism and may store the kernel, dtb 
> in
> different locations.

Hi,
Can you tell me where I can see more details about boot.scr? I didn't see that 
" boot.scr or extlinux.conf scripts should be provided by the distro itself".
Thank you.

Alice

RE: [EXT] Re: [PATCH v1 1/2] imx8mp: configs: add support for distro boot commands

2020-12-18 Thread Alice Guo (OSS)



> -Original Message-
> From: Fabio Estevam 
> Sent: 2020年12月18日 18:59
> To: Alice Guo (OSS) 
> Cc: Stefano Babic ; Peng Fan ;
> dl-uboot-imx ; Ye Li ; U-Boot-Denx
> ; Alice Guo 
> Subject: [EXT] Re: [PATCH v1 1/2] imx8mp: configs: add support for distro boot
> commands
> 
> Caution: EXT Email
> 
> Hi Alice,
> 
> On Thu, Dec 17, 2020 at 7:28 AM Alice Guo (OSS) 
> wrote:
> 
> > diff --git a/configs/imx8mp_evk_defconfig
> > b/configs/imx8mp_evk_defconfig index cd5724e811..7831a940a3 100644
> > --- a/configs/imx8mp_evk_defconfig
> > +++ b/configs/imx8mp_evk_defconfig
> > @@ -51,6 +51,8 @@ CONFIG_CMD_EXT2=y
> >  CONFIG_CMD_EXT4=y
> >  CONFIG_CMD_EXT4_WRITE=y
> >  CONFIG_CMD_FAT=y
> > +CONFIG_CMD_PART=y
> > +CONFIG_CMD_FS_GENERIC=y
> 
> Please read doc/README.distro, which states:
> 
> "In your board's defconfig, enable the DISTRO_DEFAULTS option by adding a line
> with "CONFIG_DISTRO_DEFAULTS=y"."

Hi,
I know "CONFIG_DISTRO_DEFAULTS=y" exists. It can work when I write like this so 
that I did not change it. I will modify as your advice.
Thank you.

Best Regards,
Alice

回复: [EXT] Re: [PATCH 08/17] scmi_protocols: update struct scmi_base_discover_list_protocols_out

2024-10-31 Thread Alice Guo (OSS)

Hi Tom,

> -邮件原件-
> 发件人: Tom Rini 
> 发送时间: 2024年10月17日 2:07
> 收件人: Alice Guo (OSS) 
> 抄送: Lukasz Majewski ; Sean Anderson
> ; Stefano Babic ; Fabio Estevam
> ; Marek Vasut ; dl-uboot-imx
> ; u-boot@lists.denx.de; Ye Li ; Alice
> Guo 
> 主题: [EXT] Re: [PATCH 08/17] scmi_protocols: update struct
> scmi_base_discover_list_protocols_out
> 
> On Wed, Oct 16, 2024 at 03:18:01PM +0800, Alice Guo wrote:
> > From: Ye Li 
> >
> > @protocols is an array of protocol identifiers that are implemented,
> > excluding the Base protocol. The number of elements of @protocols is
> > specified by callee-side. Currently, set it to 4 is enough for i.MX95.
> 
> This needs to be in the file too for documentation generation to pick up, 
> thanks.

May I ask which file you mention?

Best Regards,
Alice Guo

> --
> Tom

回复: [EXT] Re: [PATCH 14/17] imx95_evk: add i.MX95 19x19 EVK board basic support

2024-11-01 Thread Alice Guo (OSS)

Hi Fabio,

> -邮件原件-
> 发件人: Fabio Estevam 
> 发送时间: 2024年10月16日 19:36
> 收件人: Alice Guo (OSS) 
> 抄送: Tom Rini ; Lukasz Majewski ;
> Sean Anderson ; Stefano Babic ;
> Marek Vasut ; dl-uboot-imx ;
> u-boot@lists.denx.de; Ye Li ; Alice Guo ;
> Peng Fan 
> 主题: [EXT] Re: [PATCH 14/17] imx95_evk: add i.MX95 19x19 EVK board basic
> support
> 
> Caution: This is an external email. Please take care when clicking links or
> opening attachments. When in doubt, report the message using the 'Report this
> email' button
> 
> 
> Hi Alice,
> 
> On Wed, Oct 16, 2024 at 4:19 AM Alice Guo  wrote:
> >
> > From: Ye Li 
> >
> > This patch adds i.MX95 19x19 EVK board basic support.
> >
> > Signed-off-by: Ye Li 
> > Signed-off-by: Alice Guo 
> > Reviewed-by: Peng Fan 
> 
> A MAINTAINERS file is missing. CI flags this as an error.
> 
> Please make sure to run the series through CI before posting v2.
> 
> A general question: how is the flash.bin generated?
> 
> I don't see binman support here. Why?
> 
> We also need a doc/board/nxp/imx95_evk.rts file that explains how to build and
> boot the board, the firmware files it needs, etc.
> 

We will have new revision silicon that not compatible with current silicon 
container format. The current version will not goes into mass production, so I 
prefer to defer the binman work when new revision silicon arrives. With current 
patchset, I could add doc to use imx-mkimage to pack images. With new revision 
silicons ready, we could switch to binman and update doc then. Is this ok for 
your?

Best Regards,
Alice Guo

回复: [PATCH v1] mailbox: add i.MX MU driver

2024-09-29 Thread Alice Guo (OSS)

Sorry, please ignore this patch. I used the wrong mail.

> -邮件原件-
> 发件人: U-Boot  代表 Alice Guo
> 发送时间: 2024年9月29日 9:55
> 收件人: u-boot@lists.denx.de
> 抄送: tr...@konsulko.com; Peng Fan ; Viorel Suman
> ; michal.si...@amd.com; Ye Li ;
> Alice Guo 
> 主题: [PATCH v1] mailbox: add i.MX MU driver
> 
> From: Peng Fan 
> 
> Add i.MX MU based mailbox driver.
> 
> Signed-off-by: Viorel Suman 
> Signed-off-by: Peng Fan 
> Signed-off-by: Alice Guo 
> Reviewed-by: Ye Li 
> ---
>  drivers/mailbox/Kconfig   |   7 +
>  drivers/mailbox/Makefile  |   1 +
>  drivers/mailbox/imx-mailbox.c | 417
> ++
>  3 files changed, 425 insertions(+)
>  create mode 100644 drivers/mailbox/imx-mailbox.c
> 
> diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index
> 67d5ac1a74..4d9f004eba 100644
> --- a/drivers/mailbox/Kconfig
> +++ b/drivers/mailbox/Kconfig
> @@ -21,6 +21,13 @@ config APPLE_MBOX
> such as the System Management Controller (SMC) and NVMe and this
> driver is required to get that functionality up and running.
> 
> +config IMX_MU_MBOX
> + bool "Enable i.MX MU MBOX support"
> + depends on DM_MAILBOX
> + help
> +   Enable support for i.MX Messaging Unit for communication with other
> +   processors on the SoC using mailbox interface
> +
>  config SANDBOX_MBOX
>   bool "Enable the sandbox mailbox test driver"
>   depends on DM_MAILBOX && SANDBOX
> diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index
> 59e8d0de93..96a6adb709 100644
> --- a/drivers/mailbox/Makefile
> +++ b/drivers/mailbox/Makefile
> @@ -5,6 +5,7 @@
> 
>  obj-$(CONFIG_$(SPL_)DM_MAILBOX) += mailbox-uclass.o
>  obj-$(CONFIG_APPLE_MBOX) += apple-mbox.o
> +obj-$(CONFIG_IMX_MU_MBOX) += imx-mailbox.o
>  obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox.o
>  obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox-test.o
>  obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o diff --git
> a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c new file
> mode 100644 index 00..584950b20d
> --- /dev/null
> +++ b/drivers/mailbox/imx-mailbox.c
> @@ -0,0 +1,417 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2017-2023 NXP
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +/* This driver only exposes the status bits to keep with the
> + * polling methodology of u-boot.
> + */
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define IMX_MU_CHANS 24
> +
> +#define IMX_MU_V2_PAR_OFF0x4
> +#define IMX_MU_V2_TR_MASKGENMASK(7, 0)
> +#define IMX_MU_V2_RR_MASKGENMASK(15, 8)
> +
> +enum imx_mu_chan_type {
> + IMX_MU_TYPE_TX  = 0, /* Tx */
> + IMX_MU_TYPE_RX  = 1, /* Rx */
> + IMX_MU_TYPE_TXDB= 2, /* Tx doorbell */
> + IMX_MU_TYPE_RXDB= 3, /* Rx doorbell */
> + IMX_MU_TYPE_RST = 4, /* Reset */
> + IMX_MU_TYPE_TXDB_V2 = 5, /* Tx doorbell with S/W ACK */
> +};
> +
> +enum imx_mu_xcr {
> + IMX_MU_CR,
> + IMX_MU_GIER,
> + IMX_MU_GCR,
> + IMX_MU_TCR,
> + IMX_MU_RCR,
> + IMX_MU_xCR_MAX,
> +};
> +
> +enum imx_mu_xsr {
> + IMX_MU_SR,
> + IMX_MU_GSR,
> + IMX_MU_TSR,
> + IMX_MU_RSR,
> + IMX_MU_xSR_MAX,
> +};
> +
> +struct imx_mu_con_priv {
> + unsigned intidx;
> + enum imx_mu_chan_type   type;
> + struct mbox_chan*chan;
> +};
> +
> +enum imx_mu_type {
> + IMX_MU_V1,
> + IMX_MU_V2 = BIT(1),
> + IMX_MU_V2_S4 = BIT(15),
> + IMX_MU_V2_IRQ = BIT(16),
> +};
> +
> +struct imx_mu {
> + void __iomem *base;
> + const struct imx_mu_dcfg *dcfg;
> + u32 num_tr;
> + u32 num_rr;
> + /* use pointers to channel as a way to reserve channels */
> + struct mbox_chan *channels[IMX_MU_CHANS];
> + struct imx_mu_con_priv  con_priv[IMX_MU_CHANS]; };
> +
> +struct imx_mu_dcfg {
> + int (*tx)(struct imx_mu *plat, struct imx_mu_con_priv *cp, const void
> *data);
> + int (*rx)(struct imx_mu *plat, struct imx_mu_con_priv *cp);
> + int (*rxdb)(struct imx_mu *plat, struct imx_mu_con_priv *cp);
> + int (*init)(struct imx_mu *plat);
> + int (*of_xlate)(struct mbox_chan *chan, struct ofnode_phandle_args
> *args);
> + enum imx_mu_type type;
> + u32 xTR;/* Transmit Register0 */
> + u32 xRR;/* Receive Register0 */
> + u32 xSR[IMX_MU_xSR_MAX];/* Status Registers */
> + u32 xCR[IMX_MU_xCR_MAX];/* Control Registers */
> +};
> +
> +#define IMX_MU_xSR_GIPn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 +
> +(3 - (x #define IMX_MU_xSR_RFn(type, x) (type & IMX_MU_V2 ? BIT(x)
> +: BIT(24 + (3 - (x #define IMX_MU_xSR_TEn(type, x) (type &
> +IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x
> +
> +/* General Purpose Interrupt Enable */
> +#define IMX_MU_xCR_GIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 +
> +(3 - (x
> +/* Receive Interrupt Enable */
> +#define IMX

回复: 回复: [EXT] Re: [PATCH v3 02/17] firmware: scmi: smt: Interrupt communication enable

2025-01-06 Thread Alice Guo (OSS)

> 主题: Re: 回复: [EXT] Re: [PATCH v3 02/17] firmware: scmi: smt: Interrupt
> communication enable
> 
> On 1/6/25 7:17 AM, Alice Guo (OSS) wrote:
> >> On 1/3/25 7:45 AM, Alice Guo wrote:
> >>> From: Viorel Suman 
> >>>
> >>> When interrupt driven communication is supported
> >>
> >> U-Boot does not use interrupts.
> >>
> >>> , the transport allows
> >>> the caller to choose between interrupt and polling driven
> >>> communications. To make the choice, the channel flags are used.
> >>> i.MX95 uses interrupt driven communication so that Channel flags
> >>> should be set to 1.
> >>
> >> How does this work in U-Boot, which does not use interrupts ?
> >
> > Hi Marek,
> >
> > The clearer explanation will be added in the commit log.
> >
> > This is based on Arm® System Control and Management Interface Platform
> Design Document Version 3.2 (Document number: DEN0056E) 5.1.2. When
> Bit[0] of Channel flags is 1, the System Manager runs on M core will trigger
> general-purpose interrupts to A core. U-Boot polls General-purpose Status 
> (GSR)
> until GIPn is set.
> If U-Boot does polling, why does this bit need to be set, shouldn't the bit be
> cleared instead ?

My commit log may have caused your misunderstanding. If the bit is not set, the 
System Manager will not request doorbell interrupt. The following is the code 
from imx-sm:

if (callee)
{
/* Generate completion interrupt */
if ((buf->channelFlags & SMT_COMP_INT) != 0U)
{
status = RPC_SMT_DoorbellRing(smtChannel);
}
}

Best Regards,
Alice Guo

回复: [EXT] Re: [PATCH v3 01/17] mailbox: add i.MX95 Messaging Unit (MU) driver

2025-01-05 Thread Alice Guo (OSS)

> 主题: [EXT] Re: [PATCH v3 01/17] mailbox: add i.MX95 Messaging Unit (MU)
> driver
> 
> Caution: This is an external email. Please take care when clicking links or
> opening attachments. When in doubt, report the message using the 'Report this
> email' button
> 
> 
> On 1/3/25 7:45 AM, Alice Guo wrote:
> > From: Peng Fan 
> >
> > i.MX95 Messaging Unit (MU) enables 2 processors on a chip to
> > communicate and coordinate by passing messages (e.g. frame
> > information, event notices and requests) through the MU interface.
> > This patch provides a driver for i.MX95 MU using the common mailbox
> > framework. Currently, SCMI exchanges on i.MX95 uses a mailbox
> > transport with SMT format, and the hardware used is this MU.
> Is this ported from Linux ? If so, as of which mainline Linux kernel commit ?

Yes, u-boot/drivers/mailbox/imx-mailbox.c is ported v6.12.8 Linux.

> Can you add older iMX SoC support while adding this driver ? It seems
> imx6..imx95 MU IP look very similar.

This patch-set is only for i.MX95. I can add the older iMX SoC support in the 
future.

Best Regards,
Alice Guo

回复: [EXT] Re: [PATCH v3 02/17] firmware: scmi: smt: Interrupt communication enable

2025-01-05 Thread Alice Guo (OSS)

> On 1/3/25 7:45 AM, Alice Guo wrote:
> > From: Viorel Suman 
> >
> > When interrupt driven communication is supported
> 
> U-Boot does not use interrupts.
> 
> > , the transport allows
> > the caller to choose between interrupt and polling driven
> > communications. To make the choice, the channel flags are used. i.MX95
> > uses interrupt driven communication so that Channel flags should be
> > set to 1.
> 
> How does this work in U-Boot, which does not use interrupts ?

Hi Marek,

The clearer explanation will be added in the commit log.

This is based on Arm® System Control and Management Interface Platform Design 
Document Version 3.2 (Document number: DEN0056E) 5.1.2. When Bit[0] of Channel 
flags is 1, the System Manager runs on M core will trigger general-purpose 
interrupts to A core. U-Boot polls General-purpose Status (GSR) until GIPn is 
set.

> > + /* Command should complete via an interrupt so that set Channel flags
> to 1. */
> > + if (IS_ENABLED(CONFIG_IMX95))
> > + scmi_smt_enable_intr(smt, true);
> This SoC specific stuff shouldn't be in generic code.
> 
> Can this be moved elsewhere ?

Will change it in v4.

Best Regards,
Alice Guo

回复: [EXT] Re: [PATCH v2 16/17] imx95_evk: add i.MX95 19x19 EVK board basic support

2025-01-02 Thread Alice Guo (OSS)

> -邮件原件-
> 发件人: Tim Harvey 
> 发送时间: 2025年1月3日 7:13
> 收件人: Alice Guo (OSS) 
> 抄送: Tom Rini ; Stefano Babic ; Fabio
> Estevam ; dl-uboot-imx ; Lukasz
> Majewski ; Sean Anderson ; Simon
> Glass ; Alper Nebi Yasak ;
> u-boot@lists.denx.de; ma...@denx.de; Alice Guo ; Ye Li
> ; Peng Fan 
> 主题: [EXT] Re: [PATCH v2 16/17] imx95_evk: add i.MX95 19x19 EVK board
> basic support
> 
> Caution: This is an external email. Please take care when clicking links or
> opening attachments. When in doubt, report the message using the 'Report
> this email' button
> 
> 
> On Thu, Dec 19, 2024 at 6:57 PM Alice Guo  wrote:
> >
> > From: Ye Li 
> >
> > This patch adds i.MX95 19x19 EVK board basic support.
> >
> > Signed-off-by: Ye Li 
> > Signed-off-by: Alice Guo 
> > Reviewed-by: Peng Fan 
> > ---
> >  arch/arm/dts/imx95-19x19-evk-u-boot.dtsi  | 224
> ++
> >  arch/arm/mach-imx/imx9/Kconfig|   6 +
> >  arch/arm/mach-imx/imx9/scmi/container.cfg |  10 ++
> >  arch/arm/mach-imx/imx9/scmi/imximage.cfg  |  15 ++
> >  arch/arm/mach-imx/imx9/scmi/soc.c |   1 +
> >  board/freescale/imx95_evk/Kconfig |  12 ++
> >  board/freescale/imx95_evk/MAINTAINERS |   6 +
> >  board/freescale/imx95_evk/Makefile|  11 ++
> >  board/freescale/imx95_evk/imx95_19x19_evk.env |  95 +++
> >  board/freescale/imx95_evk/imx95_evk.c |  54 +++
> >  board/freescale/imx95_evk/spl.c   | 117 ++
> >  configs/imx95_19x19_evk_defconfig | 178
> 
> >  doc/board/nxp/imx95_evk.rst   | 109 +
> >  doc/board/nxp/index.rst   |   1 +
> >  include/configs/imx95_evk.h   |  36 +
> >  15 files changed, 875 insertions(+)
> >
> 
> Hi Alice,
> 
> I found some issues with imx95_19x19_evk.env (see below)
> 
> 
> > diff --git a/board/freescale/imx95_evk/imx95_19x19_evk.env
> > b/board/freescale/imx95_evk/imx95_19x19_evk.env
> > new file mode 100644
> > index
> >
> ..27e09d3d70a068efb97d6
> 9b27089
> > d1f213f39ee9
> > --- /dev/null
> > +++ b/board/freescale/imx95_evk/imx95_19x19_evk.env
> > @@ -0,0 +1,95 @@
> > +sec_boot=no
> > +initrd_addr=0x9380
> > +emmc_dev=0
> > +sd_dev=1
> > +prepare_mcore=setenv mcore_clk clk-imx95.mcore_booted
> 
> I see where mcore_clk is used but nothing uses prepare_mcore. Also there is
> no upstream Linux clk-imx95 driver yet so this really doesn't do anything
> useful. Has a clk-imx95 driver been submitted?

Hi Tim,

i.MX95 use clk-scmi.c driver, so no clk-imx95. And there is no prepare_mcore, 
this env needs to be dropped.

Thanks for pointing out my errors. I will correct them.

Best Regards,
Alice Guo

回复: [EXT] Re: [PATCH v2 16/17] imx95_evk: add i.MX95 19x19 EVK board basic support

2025-01-02 Thread Alice Guo (OSS)

> -邮件原件-
> 发件人: Tim Harvey 
> 发送时间: 2025年1月1日 4:32
> 收件人: Alice Guo (OSS) ; Simon Glass
> 
> 抄送: Tom Rini ; Stefano Babic ; Fabio
> Estevam ; dl-uboot-imx ; Lukasz
> Majewski ; Sean Anderson ; Alper
> Nebi Yasak ; u-boot@lists.denx.de;
> ma...@denx.de; Alice Guo ; Ye Li ;
> Peng Fan 
> 主题: Re: [EXT] Re: [PATCH v2 16/17] imx95_evk: add i.MX95 19x19 EVK board
> basic support
> 
> Caution: This is an external email. Please take care when clicking links or
> opening attachments. When in doubt, report the message using the 'Report this
> email' button
> 
> 
> On Mon, Dec 30, 2024 at 6:34 PM Alice Guo (OSS) 
> wrote:
> >
> > > 主题: [EXT] Re: [PATCH v2 16/17] imx95_evk: add i.MX95 19x19 EVK board
> > > basic support
> > > >
> > > I gave this series a go on top of 5cfbf8c364 origin/next on an EVK I
> > > have here and I saw no u-boot proper output after the ATF.
> > >
> > > Here is what I saw on UART2:
> > > U-Boot SPL 2025.01-rc5-00393-g9b292f7d347f (Dec 27 2024 - 16:12:20
> > > -0800) DDRMIX is powered UP Normal Boot Trying to boot from MMC2
> > > Primary set selected Load image from MMC/SD 0xdec00
> > > NOTICE:  BL31: v2.10.0  (release):lf-6.6.52-2.2.0
> > > NOTICE:  BL31: Built : 16:06:15, Dec 27 2024
> > >
> > > U-Boot SPL 2025.01-rc5-00393-g9b292f7d347f (Dec 27 2024 - 16:12:20
> > > -0800) DDRMIX is powered UP Normal Boot Trying to boot from MMC2
> > > Primary set selected Load image from MMC/SD 0xdec00
> > > NOTICE:  BL31: v2.10.0  (release):lf-6.6.52-2.2.0
> > > NOTICE:  BL31: Built : 16:06:15, Dec 27 2024 ^^^ nothing after this
> > >
> > > Any thoughts on what is wrong here?
> > >
> > > Best Regards,
> > >
> > > Tim
> >
> > Hi Tim,
> >
> > I tried it on my MX95 and it works well, so I not sure what causes this 
> > issue on
> your EVK.
> >
> 
> Hi Alice,
> 
> I discovered what happened. The first make for uboot resulted in a binman
> warning (which should be a failure but is not for some reason) and results in 
> an
> image that doesn't contain uboot proper:
> WARNING './u-boot.bin' not found, resulting binary may be not-functional
> 
> Simon, do you know why this warning doesn't result in a make failure?
> 
> Doing a second make works, so I think there is likely a binman dependency 
> issue
> going on here. You can re-create the issue with a distclean as shown here:
> 
>   COPYspl/u-boot-spl.bin
>   SYM spl/u-boot-spl.sym
>   CHECKspl/u-boot-spl.cfgout
>   CHECKu-boot-container.cfgout
> WARNING './u-boot.bin' not found, resulting binary may be not-functional
>   OBJCOPY u-boot.srec
>   OBJCOPY u-boot-nodtb.bin
>   RELOC   u-boot-nodtb.bin
>   CAT u-boot-dtb.bin
>   COPYu-boot.bin
>   SYM u-boot.sym
>   MKIMAGE u-boot.img
>   COPYu-boot.dtb
>   MKIMAGE u-boot-dtb.img
>   LDS u-boot-elf.lds
>   LD  u-boot.elf
>   BINMAN  .binman_stamp
>   OFCHK   .config
> -rw-r--r-- 1 tharvey Tim Harvey 922624 Dec 31 11:08 imx-boot-imx95.bin ^^^
> image too small... missing u-boot.bin
> 
> $ make && ls -l imx-boot-imx95.bin
>   UPD include/generated/timestamp_autogenerated.h
>   CC  common/version.o
>   AR  common/built-in.o
>   LD  u-boot
>   OBJCOPY u-boot.srec
>   OBJCOPY u-boot-nodtb.bin
>   RELOC   u-boot-nodtb.bin
>   CAT u-boot-dtb.bin
>   COPYu-boot.bin
>   SYM u-boot.sym
>   CC  spl/common/spl/spl.o
>   AR  spl/common/spl/built-in.o
>   LD  spl/u-boot-spl
>   OBJCOPY spl/u-boot-spl-nodtb.bin
>   CAT spl/u-boot-spl-dtb.bin
>   COPYspl/u-boot-spl.bin
>   SYM spl/u-boot-spl.sym
>   MKIMAGE u-boot.img
>   MKIMAGE u-boot-dtb.img
>   LD  u-boot.elf
>   CHECKu-boot-container.cfgout
>   BINMAN  .binman_stamp
>   OFCHK   .config
> -rw-r--r-- 1 tharvey Tim Harvey 1709056 Dec 31 11:10 imx-boot-imx95.bin ^^^
> now we have a proper image
> 
> Best Regards,
> 
> Tim

Hi Tim,

When using "make distclean; make imx95_19x19_evk_defconfig; make", 
imx9_image.sh will delete the line "IMAGE A55 u-boot.bin CONFIG_TEXT_BASE" in 
container.cfg for i.MX95. I correct it in v3 and will send it later.

Best Regards,
Alice Guo

回复: [EXT] Re: [PATCH v3 07/17] clk: scmi: check the clock state/parent/rate control permissions

2025-01-07 Thread Alice Guo (OSS)

> > SCMI clock management protocol driver in Linux checks clock state,
> > parent and rate control permissions. To be consistent with the kernel
> > driver, add this check here.
> >
> > When using common clock framework (CCF), use the clock signal ID to
> > get the clock registered by clk_register() in scmi_clk_probe(), and
> > then obatin the struct clk_scmi variable with container_of().
> >
> > Signed-off-by: Alice Guo 
> > Signed-off-by: Ye Li 
> > Reviewed-by: Peng Fan 
> > ---
> >   arch/sandbox/include/asm/scmi_test.h   |   2 +
> >   drivers/clk/clk_scmi.c | 173
> +++--
> >   drivers/firmware/scmi/sandbox-scmi_agent.c |  56 +-
> >   include/scmi_protocols.h   |  26 -
> Please split common/imx/sandbox changes into separate patches .

Spliting common/imx/sandbox changes into separate patches will cause bisect 
issue.

回复: 回复: [EXT] Re: [PATCH v3 03/17] pinctrl: nxp: add SCMI pin control protocol driver

2025-01-06 Thread Alice Guo (OSS)

> -邮件原件-
> 发件人: Marek Vasut 
> 发送时间: 2025年1月7日 4:46
> 收件人: Alice Guo (OSS) ; Tom Rini
> ; Stefano Babic ; Fabio Estevam
> ; dl-uboot-imx ; Lukasz
> Majewski ; Sean Anderson ; Simon
> Glass ; Alper Nebi Yasak 
> 抄送: u-boot@lists.denx.de; thar...@gateworks.com; Peng Fan
> ; Ranjani Vaidyanathan
> ; Ye Li 
> 主题: Re: 回复: [EXT] Re: [PATCH v3 03/17] pinctrl: nxp: add SCMI pin control
> protocol driver
> 
> On 1/6/25 10:56 AM, Alice Guo (OSS) wrote:
> >>> This patch provides a driver for the SCMI pin control protocol which
> >>> is based on ARM's System Control and Management Interface (SCMI) 3.2.
> >>> Currently, only the PINCTRL_CONFIG_SET command is implemented.
> >>
> >> What is the SCMI provider for this platform ?
> >
> > Hi Marek,
> >
> > System Manager which runs on M core sets pin or group configurations.
> U-Boot sends a SCMI message to System Manager to perform hardware
> operations. You can refer to the source code for details:
> https://github.com/nxp-imx/imx-sm.
> 
> Can I use optee-os as a SCMI provider instead ?

You cannot replace System Manager with optee-os.

回复: [EXT] Re: [PATCH v3 11/17] imx9: scmi: soc: Override h_spl_load_read with trampoline buffer

2025-01-07 Thread Alice Guo (OSS)

> -邮件原件-
> 发件人: Marek Vasut 
> 发送时间: 2025年1月6日 5:44
> 收件人: Alice Guo (OSS) ; Tom Rini
> ; Stefano Babic ; Fabio Estevam
> ; dl-uboot-imx ; Lukasz
> Majewski ; Sean Anderson ; Simon
> Glass ; Alper Nebi Yasak ;
> Alice Guo 
> 抄送: u-boot@lists.denx.de; thar...@gateworks.com; Ye Li ;
> Peng Fan 
> 主题: [EXT] Re: [PATCH v3 11/17] imx9: scmi: soc: Override h_spl_load_read
> with trampoline buffer
> 
> Caution: This is an external email. Please take care when clicking links or
> opening attachments. When in doubt, report the message using the 'Report this
> email' button
> 
> 
> On 1/3/25 7:45 AM, Alice Guo wrote:
> > From: Ye Li 
> >
> > When SPL loading image to secure region, for example, ATF and tee to
> > DDR secure region. Because the USDHC controller is non-secure master,
> > it can't access this region and will cause loading issue.
> >
> > So override h_spl_load_read to use a trampoline buffer in nonsecure
> > region, then use CPU to copy the image from trampoline buffer to
> > destination secure region.
> Can the attacker intercept this and rewrite the soon-to-be-secure-only 
> software
> with something that would later allow them to take over the system ? For
> example, could the attacker flip some secure-test bit in the TEE while it is 
> in
> non-secure DRAM and before it is copied in the secure location, and make TEE
> accept privileged SMC operations from any unprivileged software ?

User can authenticate OP-TEE. When authentication succeeds, OP-TEE has not been 
modified.

Best Regards,
Alice Guo

回复: [EXT] Re: [PATCH v3 03/17] pinctrl: nxp: add SCMI pin control protocol driver

2025-01-06 Thread Alice Guo (OSS)

> > This patch provides a driver for the SCMI pin control protocol which
> > is based on ARM's System Control and Management Interface (SCMI) 3.2.
> > Currently, only the PINCTRL_CONFIG_SET command is implemented.
> 
> What is the SCMI provider for this platform ?

Hi Marek,

System Manager which runs on M core sets pin or group configurations. U-Boot 
sends a SCMI message to System Manager to perform hardware operations. You can 
refer to the source code for details: https://github.com/nxp-imx/imx-sm.

> > +#include "pinctrl-imx.h"
> > +
> > +#if defined(CONFIG_IMX93)
> 
> Use IS_ENABLED() or CONFIG_IS_ENABLED()
> 
> > +#define DAISY_OFFSET 0x360
> 
> Why can this offset information not be queried from the firmware interface ?

This offset information is not provided by System Manager. DAISY_OFFSET is used 
to convert the daisy register address in imx95-pinfunc.h for System Manager to 
use.

Best Regards,
Alice Guo

> > +#endif
> > +#if defined(CONFIG_IMX95)
> > +#define DAISY_OFFSET 0x408
> > +#endif
> [...]

回复: [EXT] Re: [PATCH v3 08/17] scmi_protocols: update struct scmi_base_discover_list_protocols_out

2025-01-06 Thread Alice Guo (OSS)

> > @@ -141,11 +141,14 @@ struct scmi_base_discover_impl_version_out {
> >* @status: SCMI command status
> >* @num_protocols:  Number of SCMI protocols in @protocol
> >* @protocols:  Array of packed SCMI protocol ID's
> > + *
> > + * The number of elements of @protocols is specified by callee-side.
> > + Currently,
> > + * set it to 4 is enough for i.MX95.
> >*/
> >   struct scmi_base_discover_list_protocols_out {
> >   s32 status;
> >   u32 num_protocols;
> > - u32 protocols[3];
> > + u32 protocols[4];
> Can this be made somehow future-proof? For example, figure out how many
> protocols are supported, and then malloc this structure with the right size 
> and
> query again ?

Hi Marek,

Currently, 4 is enough. 10 protocols are defined in Arm® System Control and 
Management Interface Platform Design Document Version 3.2. I can make a new 
patch as you said in the future.

Best Regards,
Alice Guo

回复: [EXT] Re: [PATCH v2 16/17] imx95_evk: add i.MX95 19x19 EVK board basic support

2024-12-30 Thread Alice Guo (OSS)

> 主题: [EXT] Re: [PATCH v2 16/17] imx95_evk: add i.MX95 19x19 EVK board
> basic support
> > 
> I gave this series a go on top of 5cfbf8c364 origin/next on an EVK I have here
> and I saw no u-boot proper output after the ATF.
> 
> Here is what I saw on UART2:
> U-Boot SPL 2025.01-rc5-00393-g9b292f7d347f (Dec 27 2024 - 16:12:20 -0800)
> DDRMIX is powered UP Normal Boot Trying to boot from MMC2 Primary set
> selected Load image from MMC/SD 0xdec00
> NOTICE:  BL31: v2.10.0  (release):lf-6.6.52-2.2.0
> NOTICE:  BL31: Built : 16:06:15, Dec 27 2024
> 
> U-Boot SPL 2025.01-rc5-00393-g9b292f7d347f (Dec 27 2024 - 16:12:20 -0800)
> DDRMIX is powered UP Normal Boot Trying to boot from MMC2 Primary set
> selected Load image from MMC/SD 0xdec00
> NOTICE:  BL31: v2.10.0  (release):lf-6.6.52-2.2.0
> NOTICE:  BL31: Built : 16:06:15, Dec 27 2024 ^^^ nothing after this
> 
> Any thoughts on what is wrong here?
> 
> Best Regards,
> 
> Tim

Hi Tim,

I tried it on my MX95 and it works well, so I not sure what causes this issue 
on your EVK.

Best Regards,
Alice Guo

回复: [EXT] Re: [PATCH v2 16/17] imx95_evk: add i.MX95 19x19 EVK board basic support

2024-12-24 Thread Alice Guo (OSS)

> -邮件原件-
> 发件人: Simon Glass 
> 发送时间: 2024年12月21日 1:37
> 收件人: Alice Guo (OSS) 
> 抄送: Tom Rini ; Stefano Babic ; Fabio
> Estevam ; dl-uboot-imx ; Lukasz
> Majewski ; Sean Anderson ; Alper
> Nebi Yasak ; u-boot@lists.denx.de;
> ma...@denx.de; Alice Guo ; Ye Li ;
> Peng Fan 
> 主题: [EXT] Re: [PATCH v2 16/17] imx95_evk: add i.MX95 19x19 EVK board basic
> support
> 
> Caution: This is an external email. Please take care when clicking links or
> opening attachments. When in doubt, report the message using the 'Report this
> email' button
> 
> 
> Hi Alice,
> 
> On Thu, 19 Dec 2024 at 19:56, Alice Guo  wrote:
> >
> > From: Ye Li 
> >
> > This patch adds i.MX95 19x19 EVK board basic support.
> >
> > Signed-off-by: Ye Li 
> > Signed-off-by: Alice Guo 
> > Reviewed-by: Peng Fan 
> > ---
> >  arch/arm/dts/imx95-19x19-evk-u-boot.dtsi  | 224
> ++
> >  arch/arm/mach-imx/imx9/Kconfig|   6 +
> >  arch/arm/mach-imx/imx9/scmi/container.cfg |  10 ++
> >  arch/arm/mach-imx/imx9/scmi/imximage.cfg  |  15 ++
> >  arch/arm/mach-imx/imx9/scmi/soc.c |   1 +
> >  board/freescale/imx95_evk/Kconfig |  12 ++
> >  board/freescale/imx95_evk/MAINTAINERS |   6 +
> >  board/freescale/imx95_evk/Makefile|  11 ++
> >  board/freescale/imx95_evk/imx95_19x19_evk.env |  95 +++
> >  board/freescale/imx95_evk/imx95_evk.c |  54 +++
> >  board/freescale/imx95_evk/spl.c   | 117 ++
> >  configs/imx95_19x19_evk_defconfig | 178
> 
> >  doc/board/nxp/imx95_evk.rst   | 109 +
> >  doc/board/nxp/index.rst   |   1 +
> >  include/configs/imx95_evk.h   |  36 +
> >  15 files changed, 875 insertions(+)
> >
> > diff --git a/board/freescale/imx95_evk/imx95_19x19_evk.env
> > b/board/freescale/imx95_evk/imx95_19x19_evk.env
> > new file mode 100644
> > index
> >
> ..27e09d3d70a068efb97d69b
> 27089
> > d1f213f39ee9
> > --- /dev/null
> > +++ b/board/freescale/imx95_evk/imx95_19x19_evk.env
> > @@ -0,0 +1,95 @@
> > +sec_boot=no
> > +initrd_addr=0x9380
> > +emmc_dev=0
> > +sd_dev=1
> > +prepare_mcore=setenv mcore_clk clk-imx95.mcore_booted
> > +scriptaddr=0x9350
> > +kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "
> > +image=Image
> > +splashimage=0xA000
> > +console=ttyLP0,115200 earlycon
> > +fdt_addr_r=0x9300
> > +fdt_addr=0x9300
> > +cntr_addr=0xA800
> > +cntr_file=os_cntr_signed.bin
> > +boot_fit=no
> > +fdtfile=" CONFIG_DEFAULT_FDT_FILE "
> > +bootm_size=0x1000
> > +mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV)"
> > +mmcpart=1
> > +mmcroot=/dev/mmcblk1p2 rootwait rw
> > +mmcautodetect=yes
> > +mmcargs=setenv bootargs ${mcore_clk} console=${console}
> > +root=${mmcroot} loadbootscript=fatload mmc ${mmcdev}:${mmcpart}
> > +${loadaddr} ${script}; bootscript=echo Running bootscript from mmc
> > +...; source loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}
> > +${image} loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r}
> > +${fdtfile} loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr}
> > +${cntr_file} auth_os=auth_cntr ${cntr_addr} boot_os=booti ${loadaddr}
> > +- ${fdt_addr_r}; mmcboot=echo Booting from mmc ...;
> > +   run mmcargs;
> > +   if test ${sec_boot} = yes; then
> > +   if run auth_os; then
> > +   run boot_os;
> > +   else
> > +   echo ERR: failed to authenticate;
> > +   fi;
> > +   else
> > +   if test ${boot_fit} = yes || test ${boot_fit} = try;
> then
> > +   bootm ${loadaddr};
> > +   else
> > +   if run loadfdt; then
> > +   run boot_os;
> > +   else
> > +   echo WARN: Cannot load
> the DT;
> > +   fi;
> > +   fi;
> > +   fi;
> > +netargs=setenv bootargs ${mcore_clk} console=${console}
> > +   root=/dev/nfs
> > +   ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp
> > +net

回复: [EXT] Re: [PATCH v2 16/17] imx95_evk: add i.MX95 19x19 EVK board basic support

2025-01-01 Thread Alice Guo (OSS)

> -邮件原件-
> 发件人: Tim Harvey 
> 发送时间: 2025年1月1日 4:32
> 收件人: Alice Guo (OSS) ; Simon Glass
> 
> 抄送: Tom Rini ; Stefano Babic ; Fabio
> Estevam ; dl-uboot-imx ; Lukasz
> Majewski ; Sean Anderson ; Alper
> Nebi Yasak ; u-boot@lists.denx.de;
> ma...@denx.de; Alice Guo ; Ye Li ;
> Peng Fan 
> 主题: Re: [EXT] Re: [PATCH v2 16/17] imx95_evk: add i.MX95 19x19 EVK board
> basic support
> 
> Caution: This is an external email. Please take care when clicking links or
> opening attachments. When in doubt, report the message using the 'Report this
> email' button
> 
> 
> On Mon, Dec 30, 2024 at 6:34 PM Alice Guo (OSS) 
> wrote:
> >
> > > 主题: [EXT] Re: [PATCH v2 16/17] imx95_evk: add i.MX95 19x19 EVK board
> > > basic support
> > > >
> > > I gave this series a go on top of 5cfbf8c364 origin/next on an EVK I
> > > have here and I saw no u-boot proper output after the ATF.
> > >
> > > Here is what I saw on UART2:
> > > U-Boot SPL 2025.01-rc5-00393-g9b292f7d347f (Dec 27 2024 - 16:12:20
> > > -0800) DDRMIX is powered UP Normal Boot Trying to boot from MMC2
> > > Primary set selected Load image from MMC/SD 0xdec00
> > > NOTICE:  BL31: v2.10.0  (release):lf-6.6.52-2.2.0
> > > NOTICE:  BL31: Built : 16:06:15, Dec 27 2024
> > >
> > > U-Boot SPL 2025.01-rc5-00393-g9b292f7d347f (Dec 27 2024 - 16:12:20
> > > -0800) DDRMIX is powered UP Normal Boot Trying to boot from MMC2
> > > Primary set selected Load image from MMC/SD 0xdec00
> > > NOTICE:  BL31: v2.10.0  (release):lf-6.6.52-2.2.0
> > > NOTICE:  BL31: Built : 16:06:15, Dec 27 2024 ^^^ nothing after this
> > >
> > > Any thoughts on what is wrong here?
> > >
> > > Best Regards,
> > >
> > > Tim
> >
> > Hi Tim,
> >
> > I tried it on my MX95 and it works well, so I not sure what causes this 
> > issue on
> your EVK.
> >
> 
> Hi Alice,
> 
> I discovered what happened. The first make for uboot resulted in a binman
> warning (which should be a failure but is not for some reason) and results in 
> an
> image that doesn't contain uboot proper:
> WARNING './u-boot.bin' not found, resulting binary may be not-functional
> 
> Simon, do you know why this warning doesn't result in a make failure?
> 
> Doing a second make works, so I think there is likely a binman dependency 
> issue
> going on here. You can re-create the issue with a distclean as shown here:
> 

I reproduced this issue with make distclean, but not every time. I need time to 
check it.

Best Regards,
Alice Guo

回复: [EXT] Re: [PATCH v2 16/17] imx95_evk: add i.MX95 19x19 EVK board basic support

2024-12-24 Thread Alice Guo (OSS)

> -邮件原件-
> 发件人: João Paulo Gonçalves 
> 发送时间: 2024年12月24日 21:33
> 收件人: Alice Guo (OSS) 
> 抄送: Tom Rini ; Stefano Babic ; Fabio
> Estevam ; dl-uboot-imx ; Lukasz
> Majewski ; Sean Anderson ; Simon
> Glass ; Alper Nebi Yasak ;
> u-boot@lists.denx.de; ma...@denx.de; Alice Guo ; Ye Li
> ; Peng Fan ; Francesco Dolcini
> ; joao.goncal...@toradex.com
> 主题: [EXT] Re: [PATCH v2 16/17] imx95_evk: add i.MX95 19x19 EVK board
> basic support
> 
> Caution: This is an external email. Please take care when clicking links or
> opening attachments. When in doubt, report the message using the 'Report
> this email' button
> 
> 
> On Fri, Dec 20, 2024 at 10:55:14AM +0800, Alice Guo wrote:
> > From: Ye Li 
> >
> > This patch adds i.MX95 19x19 EVK board basic support.
> >
> > Signed-off-by: Ye Li 
> > Signed-off-by: Alice Guo 
> > Reviewed-by: Peng Fan 
> > ---
> >  arch/arm/dts/imx95-19x19-evk-u-boot.dtsi  | 224
> ++
> >  arch/arm/mach-imx/imx9/Kconfig|   6 +
> >  arch/arm/mach-imx/imx9/scmi/container.cfg |  10 ++
> >  arch/arm/mach-imx/imx9/scmi/imximage.cfg  |  15 ++
> >  arch/arm/mach-imx/imx9/scmi/soc.c |   1 +
> >  board/freescale/imx95_evk/Kconfig |  12 ++
> >  board/freescale/imx95_evk/MAINTAINERS |   6 +
> >  board/freescale/imx95_evk/Makefile|  11 ++
> >  board/freescale/imx95_evk/imx95_19x19_evk.env |  95 +++
> >  board/freescale/imx95_evk/imx95_evk.c |  54 +++
> >  board/freescale/imx95_evk/spl.c   | 117 ++
> >  configs/imx95_19x19_evk_defconfig | 178
> 
> >  doc/board/nxp/imx95_evk.rst   | 109 +
> >  doc/board/nxp/index.rst   |   1 +
> >  include/configs/imx95_evk.h   |  36 +
> >  15 files changed, 875 insertions(+)
> >
> > diff --git a/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi
> > b/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi
> > new file mode 100644
> > index
> >
> ..5c891518448d24204f5ca
> 2a00957
> > b47a0a24bd70
> > --- /dev/null
> > +++ b/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi
> > @@ -0,0 +1,224 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2024 NXP
> > + */
> > +
> > +#ifdef CONFIG_BINMAN
> > +/ {
> > + binman {
> > + multiple-images;
> > +
> > + m33-oei-ddrfw {
> > + filename = "m33-oei-ddrfw.bin";
> > +
> > + nxp-append-ddrfw {
> > + oei_m33_ddr_image = "oei-m33-ddr.bin";
> > + lpddr_imem =
> "lpddr5_imem_v202311.bin";
> > + lpddr_dmem =
> "lpddr5_dmem_v202311.bin";
> > + lpddr_imem_qb =
> "lpddr5_imem_qb_v202311.bin";
> > + lpddr_dmem_qb =
> "lpddr5_dmem_qb_v202311.bin";
> > + };
> > + };
> > +
> > + spl {
> > + filename = "spl.bin";
> > +
> > + mkimage {
> > + args = "-n spl/u-boot-spl.cfgout -T
> imx8image";
> > + };
> > + };
> > +
> > + u-boot {
> > + filename = "uboot.bin";
> > +
> > + mkimage {
> > + args = "-n u-boot-container.cfgout -T
> imx8image";
> > + };
> > + };
> > +
> > + imx-boot {
> > + filename = "imx-boot-imx95.bin";
> > + pad-byte = <0x00>;
> > +
> > + blob-ext@1 {
> > + align = <0x400>;
> > + align-size = <0x400>;
> > + offset = <0x0>;
> > + filename = "spl.bin";
> > + };
> > +
> > + blob-ext@2 {
> > + filename = "uboot.bin";
> > + };
> > + };
> > + };
> > +};
> > +#endif
> > +
> > +&{/soc} {
> > + bootph-all;
> > + bootp

回复: [EXT] Re: [PATCH v3 17/17] imx95_evk: add i.MX95 19x19 EVK board basic support

2025-01-14 Thread Alice Guo (OSS)

> On Thu, Jan 2, 2025 at 10:47 PM Alice Guo  wrote:
> >
> > From: Ye Li 
> >
> > This patch adds i.MX95 19x19 EVK board basic support.
> >
>
> Hi Alice,
>
> Could you add in the commit log what is and/or what is not supported?
>
> From what I see:
>
> the following is supported:
> - gpio
> - pci
> - i2c
> - mmc
>
> the following are not yet supported by this series:
> - ethernet
> - usb
>
> Best Regards,
>
> Tim

Will add it in the commit log.

Best Regards,
Alice Guo

> > Signed-off-by: Ye Li 
> > Signed-off-by: Alice Guo 
> > Reviewed-by: Peng Fan 
> > ---
> >  arch/arm/dts/imx95-19x19-evk-u-boot.dtsi  |  68 ++
> >  arch/arm/dts/imx95-u-boot.dtsi| 173
> +
> >  arch/arm/mach-imx/imx9/Kconfig|   6 +
> >  arch/arm/mach-imx/imx9/scmi/container.cfg |  10 ++
> >  arch/arm/mach-imx/imx9/scmi/imximage.cfg  |  15 +++
> >  arch/arm/mach-imx/imx9/scmi/soc.c |   1 +
> >  board/freescale/imx95_evk/Kconfig |  12 ++
> >  board/freescale/imx95_evk/MAINTAINERS |   6 +
> >  board/freescale/imx95_evk/Makefile|  11 ++
> >  board/freescale/imx95_evk/imx95_19x19_evk.env |  90 +
> >  board/freescale/imx95_evk/imx95_evk.c |  54 
> >  board/freescale/imx95_evk/spl.c   |  96 ++
> >  configs/imx95_19x19_evk_defconfig | 177
> ++
> >  doc/board/nxp/imx95_evk.rst   | 116
> +
> >  doc/board/nxp/index.rst   |   1 +
> >  include/configs/imx95_evk.h   |  30 +
> >  16 files changed, 866 insertions(+)
> >
> > diff --git a/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi
> > b/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi
> > new file mode 100644
> > index
> >
> ..36169b56ef3075a5c243f7fb
> 1afd
> > 6399b0df77ad
> > --- /dev/null
> > +++ b/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi
> > @@ -0,0 +1,68 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2024 NXP
> > + */
> > +
> > +#include "imx95-u-boot.dtsi"
> > +
> > +&gpio1 {
> > +   reg = <0 0x4740 0 0x1000>, <0 0x47400040 0 0x40>; };
> > +
> > +&lpuart1 {
> > +   clocks = <&scmi_clk IMX95_CLK_LPUART1>, <&scmi_clk
> IMX95_CLK_LPUART1>;
> > +   clock-names = "ipg", "per";
> > +   bootph-pre-ram;
> > +};
> > +
> > +&pinctrl_uart1 {
> > +   bootph-pre-ram;
> > +};
> > +
> > +&usdhc1 {
> > +   bootph-pre-ram;
> > +};
> > +
> > +&pinctrl_usdhc1 {
> > +   bootph-pre-ram;
> > +};
> > +
> > +&pinctrl_usdhc1_100mhz {
> > +   bootph-pre-ram;
> > +};
> > +
> > +&pinctrl_usdhc1_200mhz {
> > +   bootph-pre-ram;
> > +};
> > +
> > +&usdhc2 {
> > +   bootph-pre-ram;
> > +};
> > +
> > +&pinctrl_usdhc2 {
> > +   bootph-pre-ram;
> > +};
> > +
> > +&pinctrl_usdhc2_100mhz {
> > +   bootph-pre-ram;
> > +};
> > +
> > +&pinctrl_usdhc2_200mhz {
> > +   bootph-pre-ram;
> > +};
> > +
> > +&pinctrl_usdhc2_gpio {
> > +   bootph-pre-ram;
> > +};
> > +
> > +®_usdhc2_vmmc {
> > +   bootph-pre-ram;
> > +};
> > +
> > +&pinctrl_reg_usdhc2_vmmc {
> > +   bootph-pre-ram;
> > +};
> > +
> > +&wdog3 {
> > +   status = "disabled";
> > +};
> > diff --git a/arch/arm/dts/imx95-u-boot.dtsi
> > b/arch/arm/dts/imx95-u-boot.dtsi new file mode 100644 index
> >
> ..bf6b31210e0d70674d6ce7c
> 787ff
> > 7157a1cf65ed
> > --- /dev/null
> > +++ b/arch/arm/dts/imx95-u-boot.dtsi
> > @@ -0,0 +1,173 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2024 NXP
> > + */
> > +
> > +/ {
> > +binman {
> > +multiple-images;
> > +
> > +m33-oei-ddrfw {
> > +pad-byte = <0x00>;
> > +align-size = <0x8>;
> > +filename = "m33-oei-ddrfw.bin";
> > +
> > +oei-m33-ddr {
> > +align-size = <0x4>;
> > +filename = "oei-m33-ddr.bin";
> > +type = "blob-ext";
> > +};
> > +
> > +imx-lpddr {
> > +type = "nxp-header-ddrfw";
> > +
> > +imx-lpddr-imem {
> > +filename = "lpddr5_imem_v202311.bin";
> > +type = "blob-ext";
> > +};
> > +
> > +imx-lpddr-dmem {
> > +filename = "lpddr5_dmem_v202311.bin";
> > +type = "blob-ext";
> > +};
> > +};
> > +
> > +imx-lpddr-qb {
> > +type = "nxp-header-ddrfw";
> > +
> > +imx-lpddr-imem-qb {
> > +filename = "lpddr5_imem_qb_v202311.bin";
> > +type = "blob-ext";
> > +};
> > +
> > +imx-lpddr-dmem-qb {
> > +filename = "lpddr5_dmem_qb_v202311.bin";
> > +type = "blob-ext";
> > +};
> > +};
> > +};
> > +
> > +

回复: 回复: 回复: [EXT] Re: [PATCH v3 02/17] firmware: scmi: smt: Interrupt communication enable

2025-01-07 Thread Alice Guo (OSS)

> -邮件原件-
> 发件人: Marek Vasut 
> 发送时间: 2025年1月7日 19:11
> 收件人: Alice Guo (OSS) ; Tom Rini
> ; Stefano Babic ; Fabio Estevam
> ; dl-uboot-imx ; Lukasz
> Majewski ; Sean Anderson ; Simon
> Glass ; Alper Nebi Yasak 
> 抄送: u-boot@lists.denx.de; thar...@gateworks.com; Viorel Suman
> ; Ye Li 
> 主题: Re: 回复: 回复: [EXT] Re: [PATCH v3 02/17] firmware: scmi: smt:
> Interrupt communication enable
> 
> On 1/7/25 4:24 AM, Alice Guo (OSS) wrote:
> >> 主题: Re: 回复: [EXT] Re: [PATCH v3 02/17] firmware: scmi: smt: Interrupt
> >> communication enable
> >>
> >> On 1/6/25 7:17 AM, Alice Guo (OSS) wrote:
> >>>> On 1/3/25 7:45 AM, Alice Guo wrote:
> >>>>> From: Viorel Suman 
> >>>>>
> >>>>> When interrupt driven communication is supported
> >>>>
> >>>> U-Boot does not use interrupts.
> >>>>
> >>>>> , the transport allows
> >>>>> the caller to choose between interrupt and polling driven
> >>>>> communications. To make the choice, the channel flags are used.
> >>>>> i.MX95 uses interrupt driven communication so that Channel flags
> >>>>> should be set to 1.
> >>>>
> >>>> How does this work in U-Boot, which does not use interrupts ?
> >>>
> >>> Hi Marek,
> >>>
> >>> The clearer explanation will be added in the commit log.
> >>>
> >>> This is based on Arm® System Control and Management Interface
> >>> Platform
> >> Design Document Version 3.2 (Document number: DEN0056E) 5.1.2. When
> >> Bit[0] of Channel flags is 1, the System Manager runs on M core will
> >> trigger general-purpose interrupts to A core. U-Boot polls
> >> General-purpose Status (GSR) until GIPn is set.
> >> If U-Boot does polling, why does this bit need to be set, shouldn't
> >> the bit be cleared instead ?
> >
> > My commit log may have caused your misunderstanding. If the bit is not set,
> the System Manager will not request doorbell interrupt. The following is the
> code from imx-sm:
> >
> >  if (callee)
> >  {
> >  /* Generate completion interrupt */
> >  if ((buf->channelFlags & SMT_COMP_INT) != 0U)
> >  {
> >  status = RPC_SMT_DoorbellRing(smtChannel);
> >  }
> >  }
> Can the SM be updated instead ?

System Manager not only interacts with U-Boot, but also with Linux/QNX/RTOS. 
System Manager cannot be changed.

回复: [EXT] Re: [PATCH v4 20/20] imx95_evk: add i.MX95 19x19 EVK board basic support

2025-01-16 Thread Alice Guo (OSS)

> -邮件原件-
> 发件人: Tim Harvey 
> 发送时间: 2025年1月17日 6:48
> 收件人: Alice Guo (OSS) 
> 抄送: Tom Rini ; Stefano Babic ; Fabio
> Estevam ; dl-uboot-imx ; Lukasz
> Majewski ; Sean Anderson ; Simon
> Glass ; Alper Nebi Yasak ;
> ma...@denx.de; u-boot@lists.denx.de; Alice Guo ; Ye Li
> ; Peng Fan 
> 主题: [EXT] Re: [PATCH v4 20/20] imx95_evk: add i.MX95 19x19 EVK board basic
> support
> 
> Caution: This is an external email. Please take care when clicking links or
> opening attachments. When in doubt, report the message using the 'Report this
> email' button
> 
> 
> On Thu, Jan 16, 2025 at 11:42 AM Tim Harvey 
> wrote:
> >
> > On Thu, Jan 16, 2025 at 11:38 AM Tim Harvey 
> wrote:
> > >
> > > On Wed, Jan 15, 2025 at 5:30 AM Alice Guo 
> wrote:
> > > >
> > > > From: Ye Li 
> > > >
> > > > This patch adds i.MX95 19x19 EVK board basic support.
> > > >
> > > > Messaging unit for EdgeLock Secure Enclave, messaging unit for
> > > > System Manager, uSDHC for SD Card, gpio, lpuart are supported now.
> > > >
> > > > Signed-off-by: Ye Li 
> > > > Signed-off-by: Alice Guo 
> > > > Reviewed-by: Peng Fan 
> > > > ---
> > > 
> > > > diff --git a/board/freescale/imx95_evk/imx95_evk.c
> > > > b/board/freescale/imx95_evk/imx95_evk.c
> > > > new file mode 100644
> > > > index
> > > >
> ..1ed15ca47b157067a7376b0
> b
> > > > 32101dc7f9899f4f
> > > > --- /dev/null
> > > > +++ b/board/freescale/imx95_evk/imx95_evk.c
> > > > @@ -0,0 +1,54 @@
> > > > +// SPDX-License-Identifier: GPL-2.0+
> > > > +/*
> > > > + * Copyright 2025 NXP
> > > > + */
> > > > +
> > > > +#include 
> > > > +#include 
> > > > +#include 
> > > > +#include  #include 
> > > > +#include  #include  #include
> > > > + #include  #include
> > > > + #include  #include  #include
> > > > + #include  #include
> > > > + #include  #include
> > > > +"../../../dts/upstream/src/arm64/freescale/imx95-clock.h"
> > > > +#include "../../../dts/upstream/src/arm64/freescale/imx95-power.h"
> > >
> > > Hi Alice,
> > >
> > > Most of the above are not needed (and should be alphabetized anyway)
> > >
> > > The only ones needed are:
> > > #include 
> > > #include 
> > > #include 
> > >
> > > > +
> > > > +DECLARE_GLOBAL_DATA_PTR;
> > >
> > > not needed as you don't use gd
> > >
> > > Best Regards,
> > >
> > > Tim
> >
> > Hi Alic,
> >
> > One more thing to do for next series. Refresh your
> > imx95_19x19_evk_defconfig as its very out of sync:
> >
> > make imx95_19x19_evk_defconfig
> > make savedefconfig
> > cp defconfig configs/imx95_19x19_evk_defconfig
> >
> 
> Hi Alice,
> 
> I'm also seeing the following files left around after a build that are also 
> not
> removed after a clean/distclean:
> mkimage-out.imx-boot.spl
> mkimage-out.imx-boot.u-boot
> mkimage.imx-boot.spl
> mkimage.imx-boot.u-boot
> 
> Best Regards,
> 
> Tim

Will improve these in v5.

Best Regards,
Alice Guo

回复: 回复: [PATCH v4 04/20] firmware: scmi: add pin control protocol support to SCMI agent

2025-02-20 Thread Alice Guo (OSS)

> -邮件原件-
> 发件人: Marek Vasut 
> 发送时间: 2025年2月21日 6:35
> 收件人: Alice Guo (OSS) ; Tom Rini
> ; Stefano Babic ; Fabio Estevam
> ; dl-uboot-imx ; Lukasz
> Majewski ; Sean Anderson ; Simon
> Glass ; Alper Nebi Yasak 
> 抄送: u-boot@lists.denx.de; thar...@gateworks.com; Alice Guo
> 
> 主题: Re: 回复: [PATCH v4 04/20] firmware: scmi: add pin control protocol
> support to SCMI agent
> 
> On 2/18/25 12:53 PM, Alice Guo (OSS) wrote:
> 
> [...]
> 
> >>> @@ -436,6 +442,11 @@ static int scmi_bind_protocols(struct udevice
> *dev)
> >>>   drv = 
> >>> DM_DRIVER_GET(scmi_voltage_domain);
> >>>   }
> >>>   break;
> >>> + case SCMI_PROTOCOL_ID_PINCTRL:
> >>> + if (IS_ENABLED(CONFIG_PINCTRL_IMX_SCMI) &&
> >>
> >> Is this pinctrl protocol really imx specific ?
> >>
> >> If not, this needs to use some other config option to gate access to it.
> >
> > Currently, it is used for some product families of the i.MX9 series 
> > products.
> Is the protocol iMX specific or is it generic protocol ?

SCMI_PROTOCOL_ID_PINCTRL is not unique to iMX, but 
drivers/pinctrl/nxp/pinctrl-scmi.c (drv = DM_DRIVER_GET(scmi_pinctrl_imx)) is 
only for iMX.

回复: [EXT] Re: [PATCH v4 05/20] scmi_protocols: add SCMI misc protocol protocol_id and message_id for getting the ROM passover data

2025-02-21 Thread Alice Guo (OSS)

> -邮件原件-
> 发件人: Marek Vasut 
> 发送时间: 2025年1月24日 21:57
> 收件人: Alice Guo (OSS) ; Tom Rini
> ; Stefano Babic ; Fabio Estevam
> ; dl-uboot-imx ; Lukasz
> Majewski ; Sean Anderson ; Simon
> Glass ; Alper Nebi Yasak 
> 抄送: u-boot@lists.denx.de; thar...@gateworks.com; Alice Guo
> ; Peng Fan ; Ye Li 
> 主题: [EXT] Re: [PATCH v4 05/20] scmi_protocols: add SCMI misc protocol
> protocol_id and message_id for getting the ROM passover data
> 
> Caution: This is an external email. Please take care when clicking links or
> opening attachments. When in doubt, report the message using the 'Report this
> email' button
> 
> 
> On 1/15/25 2:28 PM, Alice Guo wrote:
> > From: Peng Fan 
> >
> > SCMI misc protocol is intended for miscellaneous functions which are
> > device specific and are usually defined to access bit fields. This
> > patch adds SCMI misc protocol protocol_id and message_id for getting
> > the ROM passover data.
> Is this iMX specific or is this generic protocol ?
> 
> If generic , then the symbol SCMI_PROTOCOL_ID_IMX_MISC should not contain
> _IMX substring .

SCMI_PROTOCOL_ID_IMX_MISC is IMX specific protocol.

回复: [PATCH v4 04/20] firmware: scmi: add pin control protocol support to SCMI agent

2025-02-18 Thread Alice Guo (OSS)

> -邮件原件-
> 发件人: Marek Vasut 
> 发送时间: 2025年1月24日 21:55
> 收件人: Alice Guo (OSS) ; Tom Rini
> ; Stefano Babic ; Fabio Estevam
> ; dl-uboot-imx ; Lukasz
> Majewski ; Sean Anderson ; Simon
> Glass ; Alper Nebi Yasak 
> 抄送: u-boot@lists.denx.de; thar...@gateworks.com; Alice Guo
> 
> 主题: Re: [PATCH v4 04/20] firmware: scmi: add pin control protocol support to
> SCMI agent
> 
> On 1/15/25 2:28 PM, Alice Guo wrote:
> > From: Alice Guo 
> >
> > This patch adds SCMI pin control protocol support so that the pin
> > controller driver based on SCMI, such as
> > drivers/pinctrl/nxp/pinctrl-scmi.c, can be bound to the SCMI agent
> > device whose protocol id is 0x19.
> >
> > Signed-off-by: Alice Guo 
> > ---
> >   drivers/firmware/scmi/scmi_agent-uclass.c | 11 +++
> >   include/scmi_agent-uclass.h   |  2 ++
> >   2 files changed, 13 insertions(+)
> >
> > diff --git a/drivers/firmware/scmi/scmi_agent-uclass.c
> > b/drivers/firmware/scmi/scmi_agent-uclass.c
> > index
> >
> 8c907c3b0328095c4b35ba089ed608fcda48b567..5f101f4ede8b585f8c562a428
> 86e
> > a7be4ef09953 100644
> > --- a/drivers/firmware/scmi/scmi_agent-uclass.c
> > +++ b/drivers/firmware/scmi/scmi_agent-uclass.c
> > @@ -97,6 +97,9 @@ struct udevice *scmi_get_protocol(struct udevice *dev,
> > case SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN:
> > proto = priv->voltagedom_dev;
> > break;
> > +   case SCMI_PROTOCOL_ID_PINCTRL:
> > +   proto = priv->pinctrl_dev;
> > +   break;
> > default:
> > dev_err(dev, "Protocol not supported\n");
> > proto = NULL;
> > @@ -147,6 +150,9 @@ static int scmi_add_protocol(struct udevice *dev,
> > case SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN:
> > priv->voltagedom_dev = proto;
> > break;
> > +   case SCMI_PROTOCOL_ID_PINCTRL:
> > +   priv->pinctrl_dev = proto;
> > +   break;
> > default:
> > dev_err(dev, "Protocol not supported\n");
> > return -EPROTO;
> > @@ -436,6 +442,11 @@ static int scmi_bind_protocols(struct udevice *dev)
> > drv = DM_DRIVER_GET(scmi_voltage_domain);
> > }
> > break;
> > +   case SCMI_PROTOCOL_ID_PINCTRL:
> > +   if (IS_ENABLED(CONFIG_PINCTRL_IMX_SCMI) &&
> 
> Is this pinctrl protocol really imx specific ?
> 
> If not, this needs to use some other config option to gate access to it.

Currently, it is used for some product families of the i.MX9 series products.

Best Regards,
Alice Guo

[PATCH v5 01/20] mailbox: add i.MX Messaging Unit (MU) driver

2025-02-18 Thread Alice Guo (OSS)

From: Peng Fan 

This patch provides a driver for i.MX Messaging Unit (MU) using the
commom mailbox framework.

This is ported from Linux (v6.12.8) driver
drivers/mailbox/imx-mailbox.c. Its commit SHA is:
39d7d6177f0c ("mailbox: imx: use device name in interrupt name")

Signed-off-by: Viorel Suman 
Signed-off-by: Peng Fan 
Signed-off-by: Alice Guo 
Reviewed-by: Ye Li 
---
 MAINTAINERS   |   1 +
 drivers/mailbox/Kconfig   |   7 +
 drivers/mailbox/Makefile  |   1 +
 drivers/mailbox/imx-mailbox.c | 430 ++
 4 files changed, 439 insertions(+)
 create mode 100644 drivers/mailbox/imx-mailbox.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 10f7f1fd180..605e3002fea 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -313,6 +313,7 @@ F:  board/freescale/*mx*/
 F: board/freescale/common/
 F: common/spl/spl_imx_container.c
 F: doc/imx/
+F: drivers/mailbox/imx-mailbox.c
 F: drivers/serial/serial_mxc.c
 F: include/imx_container.h
 
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index 67d5ac1a742..4d9f004ebad 100644
--- a/drivers/mailbox/Kconfig
+++ b/drivers/mailbox/Kconfig
@@ -21,6 +21,13 @@ config APPLE_MBOX
  such as the System Management Controller (SMC) and NVMe and this
  driver is required to get that functionality up and running.
 
+config IMX_MU_MBOX
+   bool "Enable i.MX MU MBOX support"
+   depends on DM_MAILBOX
+   help
+ Enable support for i.MX Messaging Unit for communication with other
+ processors on the SoC using mailbox interface
+
 config SANDBOX_MBOX
bool "Enable the sandbox mailbox test driver"
depends on DM_MAILBOX && SANDBOX
diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
index 6072fa1956b..574add60005 100644
--- a/drivers/mailbox/Makefile
+++ b/drivers/mailbox/Makefile
@@ -5,6 +5,7 @@
 
 obj-$(CONFIG_$(XPL_)DM_MAILBOX) += mailbox-uclass.o
 obj-$(CONFIG_APPLE_MBOX) += apple-mbox.o
+obj-$(CONFIG_IMX_MU_MBOX) += imx-mailbox.o
 obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox.o
 obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox-test.o
 obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o
diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c
new file mode 100644
index 000..a33356ea7bd
--- /dev/null
+++ b/drivers/mailbox/imx-mailbox.c
@@ -0,0 +1,430 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 NXP
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* This driver only exposes the status bits to keep with the
+ * polling methodology of u-boot.
+ */
+DECLARE_GLOBAL_DATA_PTR;
+
+#define IMX_MU_CHANS   24
+
+#define IMX_MU_V2_PAR_OFF  0x4
+#define IMX_MU_V2_TR_MASK  GENMASK(7, 0)
+#define IMX_MU_V2_RR_MASK  GENMASK(15, 8)
+
+enum imx_mu_chan_type {
+   IMX_MU_TYPE_TX  = 0, /* Tx */
+   IMX_MU_TYPE_RX  = 1, /* Rx */
+   IMX_MU_TYPE_TXDB= 2, /* Tx doorbell */
+   IMX_MU_TYPE_RXDB= 3, /* Rx doorbell */
+   IMX_MU_TYPE_RST = 4, /* Reset */
+   IMX_MU_TYPE_TXDB_V2 = 5, /* Tx doorbell with S/W ACK */
+};
+
+enum imx_mu_xcr {
+   IMX_MU_CR,
+   IMX_MU_GIER,
+   IMX_MU_GCR,
+   IMX_MU_TCR,
+   IMX_MU_RCR,
+   IMX_MU_xCR_MAX,
+};
+
+enum imx_mu_xsr {
+   IMX_MU_SR,
+   IMX_MU_GSR,
+   IMX_MU_TSR,
+   IMX_MU_RSR,
+   IMX_MU_xSR_MAX,
+};
+
+struct imx_mu_con_priv {
+   unsigned intidx;
+   enum imx_mu_chan_type   type;
+   struct mbox_chan*chan;
+};
+
+enum imx_mu_type {
+   IMX_MU_V1,
+   IMX_MU_V2 = BIT(1),
+   IMX_MU_V2_S4 = BIT(15),
+   IMX_MU_V2_IRQ = BIT(16),
+};
+
+struct imx_mu {
+   void __iomem *base;
+   const struct imx_mu_dcfg *dcfg;
+   u32 num_tr;
+   u32 num_rr;
+   /* use pointers to channel as a way to reserve channels */
+   struct mbox_chan *channels[IMX_MU_CHANS];
+   struct imx_mu_con_priv  con_priv[IMX_MU_CHANS];
+};
+
+struct imx_mu_dcfg {
+   int (*tx)(struct imx_mu *plat, struct imx_mu_con_priv *cp, const void 
*data);
+   int (*rx)(struct imx_mu *plat, struct imx_mu_con_priv *cp);
+   int (*rxdb)(struct imx_mu *plat, struct imx_mu_con_priv *cp);
+   int (*init)(struct imx_mu *plat);
+   int (*of_xlate)(struct mbox_chan *chan, struct ofnode_phandle_args 
*args);
+   enum imx_mu_type type;
+   u32 xTR;/* Transmit Register0 */
+   u32 xRR;/* Receive Register0 */
+   u32 xSR[IMX_MU_xSR_MAX];/* Status Registers */
+   u32 xCR[IMX_MU_xCR_MAX];/* Control Registers */
+};
+
+#define IMX_MU_xSR_GIPn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - 
(x
+#define IMX_MU_xSR_RFn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - 
(x
+#define IMX_MU_xSR_TEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - 
(x
+
+/* General Purpose Interrupt Enable

[PATCH v5 04/20] firmware: scmi: add pin control protocol support to SCMI agent

2025-02-18 Thread Alice Guo (OSS)

From: Alice Guo 

This patch adds SCMI pin control protocol support so that the pin
controller driver based on SCMI, such as
drivers/pinctrl/nxp/pinctrl-scmi.c, can be bound to the SCMI agent
device whose protocol id is 0x19.

Signed-off-by: Alice Guo 
---
 drivers/firmware/scmi/scmi_agent-uclass.c | 11 +++
 include/scmi_agent-uclass.h   |  2 ++
 2 files changed, 13 insertions(+)

diff --git a/drivers/firmware/scmi/scmi_agent-uclass.c 
b/drivers/firmware/scmi/scmi_agent-uclass.c
index 8c907c3b032..5f101f4ede8 100644
--- a/drivers/firmware/scmi/scmi_agent-uclass.c
+++ b/drivers/firmware/scmi/scmi_agent-uclass.c
@@ -97,6 +97,9 @@ struct udevice *scmi_get_protocol(struct udevice *dev,
case SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN:
proto = priv->voltagedom_dev;
break;
+   case SCMI_PROTOCOL_ID_PINCTRL:
+   proto = priv->pinctrl_dev;
+   break;
default:
dev_err(dev, "Protocol not supported\n");
proto = NULL;
@@ -147,6 +150,9 @@ static int scmi_add_protocol(struct udevice *dev,
case SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN:
priv->voltagedom_dev = proto;
break;
+   case SCMI_PROTOCOL_ID_PINCTRL:
+   priv->pinctrl_dev = proto;
+   break;
default:
dev_err(dev, "Protocol not supported\n");
return -EPROTO;
@@ -436,6 +442,11 @@ static int scmi_bind_protocols(struct udevice *dev)
drv = DM_DRIVER_GET(scmi_voltage_domain);
}
break;
+   case SCMI_PROTOCOL_ID_PINCTRL:
+   if (IS_ENABLED(CONFIG_PINCTRL_IMX_SCMI) &&
+   scmi_protocol_is_supported(dev, protocol_id))
+   drv = DM_DRIVER_GET(scmi_pinctrl_imx);
+   break;
default:
break;
}
diff --git a/include/scmi_agent-uclass.h b/include/scmi_agent-uclass.h
index 33e0e18c30d..4beec43cb08 100644
--- a/include/scmi_agent-uclass.h
+++ b/include/scmi_agent-uclass.h
@@ -27,6 +27,7 @@ struct scmi_channel;
  * @clock_dev: SCMI clock protocol device
  * @resetdom_dev:  SCMI reset domain protocol device
  * @voltagedom_dev:SCMI voltage domain protocol device
+ * @pinctrl_dev:   SCMI pin control protocol device
  */
 struct scmi_agent_priv {
u32 version;
@@ -43,6 +44,7 @@ struct scmi_agent_priv {
struct udevice *clock_dev;
struct udevice *resetdom_dev;
struct udevice *voltagedom_dev;
+   struct udevice *pinctrl_dev;
 };
 
 static inline u32 scmi_version(struct udevice *dev)
-- 
2.43.0

[PATCH v5 00/20] imx: add i.MX95 support

2025-02-18 Thread Alice Guo (OSS)

From: Alice Guo 

Changes in v5:
 - add support for the mailbox whose type is IMX_MU_V1
 - move scmi_smt_enable_intr into drivers/firmware/scmi/smt.c
 - use the imx95 pinctrl patch from 
https://source.denx.de/u-boot/custodians/u-boot-usb/-/commit/3191ef0497c629017da4d88bf6a14ff0ad7c0032
 - update drivers/clk/clk_scmi.c
 - delete the macro SCMI_MSG
 - sort the select lists of config IMX95
 - update the depends on of config IMX8_ROMAPI
 - delete unnecessary DECLARE_GLOBAL_DATA_PTR
 - refresh imx95_19x19_evk_defconfig
 - add mkimage-out.imx-boot.spl, mkimage-out.imx-boot.u-boot,
   mkimage.imx-boot.spl and mkimage.imx-boot.u-boot to CLEAN_FILES

Alice Guo (9):
  pinctrl: nxp: add a pin controller driver based on SCMI pin control
protocol
  firmware: scmi: add pin control protocol support to SCMI agent
  clk: scmi: check the clock state/parent/rate control permissions
  sandbox: add SCMI clock control permissions to sandbox
  imx: Kconfig: IMX8_ROMAPI is not configured for i.MX95
  binman: add a new entry type for packing DDR PHY firmware images
  tools: imx8image: add i.MX95 support
  doc: imx: add document for i.MX95 Image Container Format
  Makefile: add some files to CLEAN_FILES

Peng Fan (5):
  mailbox: add i.MX Messaging Unit (MU) driver
  scmi_protocols: add SCMI misc protocol protocol_id and message_id for
getting the ROM passover data
  scmi_protocols: add SCMI Performance domain management protocol
message IDs
  clk: scmi: add the command CLOCK_PARENT_SET
  imx9: scmi: add i.MX95 SoC and clock related code

Teo Hall (1):
  imx: add V2X container support on i.MX95

Viorel Suman (1):
  firmware: scmi: smt: Interrupt communication enable

Ye Li (4):
  scmi_protocols: update struct scmi_base_discover_list_protocols_out
  spl: imx: use trampoline buffer to load images to secure region
  imx9: add i.MX95 Kconfig and Makefile
  imx95_evk: add i.MX95 19x19 EVK board basic support

 MAINTAINERS   |   1 +
 Makefile  |   3 +-
 arch/arm/dts/imx95-19x19-evk-u-boot.dtsi  |  62 ++
 arch/arm/dts/imx95-u-boot.dtsi| 157 
 arch/arm/include/asm/arch-imx/cpu.h   |   2 +
 arch/arm/include/asm/arch-imx9/clock.h|  10 +
 arch/arm/include/asm/arch-imx9/imx-regs.h |   5 +
 arch/arm/include/asm/arch-imx9/sys_proto.h|   1 +
 arch/arm/include/asm/mach-imx/sys_proto.h |  39 +
 arch/arm/mach-imx/Kconfig |   2 +-
 arch/arm/mach-imx/image-container.c   |  63 +-
 arch/arm/mach-imx/imx9/Kconfig|  14 +
 arch/arm/mach-imx/imx9/Makefile   |   9 +-
 arch/arm/mach-imx/imx9/scmi/Makefile  |   6 +
 arch/arm/mach-imx/imx9/scmi/clock.c   | 105 +++
 arch/arm/mach-imx/imx9/scmi/clock_scmi.c  | 133 +++
 arch/arm/mach-imx/imx9/scmi/container.cfg |  10 +
 arch/arm/mach-imx/imx9/scmi/imximage.cfg  |  15 +
 arch/arm/mach-imx/imx9/scmi/soc.c | 806 ++
 arch/sandbox/include/asm/scmi_test.h  |   4 +-
 board/freescale/imx95_evk/Kconfig |  12 +
 board/freescale/imx95_evk/MAINTAINERS |   6 +
 board/freescale/imx95_evk/Makefile|  11 +
 board/freescale/imx95_evk/imx95_19x19_evk.env |  90 ++
 board/freescale/imx95_evk/imx95_evk.c |  36 +
 board/freescale/imx95_evk/spl.c   |  72 ++
 common/spl/Kconfig|   6 +
 common/spl/spl_imx_container.c|  41 +-
 configs/imx95_19x19_evk_defconfig | 160 
 doc/board/nxp/imx95_evk.rst   | 114 +++
 doc/board/nxp/index.rst   |   1 +
 doc/imx/imx95_container.txt   | 136 +++
 drivers/clk/clk_scmi.c| 190 -
 drivers/firmware/scmi/Kconfig |   6 +
 drivers/firmware/scmi/sandbox-scmi_agent.c|  56 +-
 drivers/firmware/scmi/scmi_agent-uclass.c |  11 +
 drivers/firmware/scmi/smt.c   |  13 +
 drivers/mailbox/Kconfig   |   7 +
 drivers/mailbox/Makefile  |   1 +
 drivers/mailbox/imx-mailbox.c | 430 ++
 drivers/pinctrl/nxp/Kconfig   |  13 +
 drivers/pinctrl/nxp/Makefile  |   1 +
 drivers/pinctrl/nxp/pinctrl-scmi.c| 143 
 include/configs/imx95_evk.h   |  24 +
 include/imx8image.h   |  19 +-
 include/scmi_agent-uclass.h   |   2 +
 include/scmi_protocols.h  | 107 ++-
 tools/binman/entries.rst  |  10 +
 tools/binman/etype/nxp_header_ddrfw.py|  32 +
 tools/binman/ftest.py |  11 +
 tools/binman/test/346_nxp_ddrfw_imx95.dts |  24 +
 tools/imx8image.c | 143 +++-
 tools/imx9_image.sh   |   8 +
 53 files changed, 3319 insertions(+), 64 deletions(-)
 create mode 100644 arch/arm/dts/imx95-19

[PATCH v5 02/20] firmware: scmi: smt: Interrupt communication enable

2025-02-18 Thread Alice Guo (OSS)

From: Viorel Suman 

i.MX95 System Manager uses interrupt driven communication which requires
the caller to set Bit[0] of channel flags to 1. When transmission
completes and the previous general purpose interrupt has been processed
by the other core, i.MX95 System Manager will set General Purpose
Interrupt Control Register (GCR). U-Boot polls General-purpose Status
(GSR) to check if the operation is finished.

Signed-off-by: Viorel Suman 
Signed-off-by: Alice Guo 
Reviewed-by: Ye Li 
---
 drivers/firmware/scmi/Kconfig |  6 ++
 drivers/firmware/scmi/smt.c   | 13 +
 2 files changed, 19 insertions(+)

diff --git a/drivers/firmware/scmi/Kconfig b/drivers/firmware/scmi/Kconfig
index 8cf85f0d7a1..eb62b88615b 100644
--- a/drivers/firmware/scmi/Kconfig
+++ b/drivers/firmware/scmi/Kconfig
@@ -41,3 +41,9 @@ config SCMI_AGENT_OPTEE
help
  Enable the SCMI communication channel based on OP-TEE transport
  for compatible "linaro,scmi-optee".
+
+config SCMI_TRANSPORT_SMT_INTR
+   bool
+   depends on SCMI_FIRMWARE
+   help
+ Enable interrupt communication of shared memory based transport.
diff --git a/drivers/firmware/scmi/smt.c b/drivers/firmware/scmi/smt.c
index 67d2f450024..a0489f9718a 100644
--- a/drivers/firmware/scmi/smt.c
+++ b/drivers/firmware/scmi/smt.c
@@ -20,6 +20,16 @@
 
 #include "smt.h"
 
+static void scmi_smt_enable_intr(struct scmi_smt *smt, bool enable)
+{
+   struct scmi_smt_header *hdr = (void *)smt->buf;
+
+   if (enable)
+   hdr->flags |= SCMI_SHMEM_FLAG_INTR_ENABLED;
+   else
+   hdr->flags &= ~SCMI_SHMEM_FLAG_INTR_ENABLED;
+}
+
 /**
  * Get shared memory configuration defined by the referred DT phandle
  * Return with a errno compliant value.
@@ -48,6 +58,9 @@ int scmi_dt_get_smt_buffer(struct udevice *dev, struct 
scmi_smt *smt)
if (!smt->buf)
return -ENOMEM;
 
+   if (IS_ENABLED(CONFIG_SCMI_TRANSPORT_SMT_INTR))
+   scmi_smt_enable_intr(smt, true);
+
 #ifdef CONFIG_ARM
if (dcache_status())
mmu_set_region_dcache_behaviour(ALIGN_DOWN((uintptr_t)smt->buf, 
MMU_SECTION_SIZE),
-- 
2.43.0

[PATCH v5 03/20] pinctrl: nxp: add a pin controller driver based on SCMI pin control protocol

2025-02-18 Thread Alice Guo (OSS)

From: Alice Guo 

This patch provides a pinctrl driver based on SCMI pin control protocol.
Currently, only the PINCTRL_CONFIG_SET command is implemented.

Signed-off-by: Ranjani Vaidyanathan 
Signed-off-by: Peng Fan 
Signed-off-by: Alice Guo 
Reviewed-by: Ye Li 
---
 drivers/pinctrl/nxp/Kconfig|  13 +++
 drivers/pinctrl/nxp/Makefile   |   1 +
 drivers/pinctrl/nxp/pinctrl-scmi.c | 143 +
 include/scmi_protocols.h   |  36 
 4 files changed, 193 insertions(+)
 create mode 100644 drivers/pinctrl/nxp/pinctrl-scmi.c

diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig
index d13c5f2a6d5..84d9a3641ff 100644
--- a/drivers/pinctrl/nxp/Kconfig
+++ b/drivers/pinctrl/nxp/Kconfig
@@ -139,6 +139,19 @@ config PINCTRL_IMXRT
  only parses the 'fsl,pins' property and configure related
  registers.
 
+config PINCTRL_IMX_SCMI
+   bool "IMX pinctrl SCMI driver"
+   depends on ARCH_IMX9 && PINCTRL_FULL
+   select PINCTRL_IMX
+   help
+ This provides a simple pinctrl driver for i.MX SoC which supports
+ SCMI. This feature depends on device tree configuration. This driver
+ is different from the linux one, this is a simple implementation,
+ only parses the 'fsl,pins' property and configure related
+ registers.
+
+ Say Y here to enable the imx pinctrl SCMI driver
+
 config PINCTRL_VYBRID
bool "Vybrid (vf610) pinctrl driver"
depends on ARCH_VF610 && PINCTRL_FULL
diff --git a/drivers/pinctrl/nxp/Makefile b/drivers/pinctrl/nxp/Makefile
index 44e37c631e5..9ef675d18c6 100644
--- a/drivers/pinctrl/nxp/Makefile
+++ b/drivers/pinctrl/nxp/Makefile
@@ -11,3 +11,4 @@ obj-$(CONFIG_PINCTRL_IMX93)   += pinctrl-imx93.o
 obj-$(CONFIG_PINCTRL_MXS)  += pinctrl-mxs.o
 obj-$(CONFIG_PINCTRL_VYBRID)   += pinctrl-vf610.o
 obj-$(CONFIG_PINCTRL_IMXRT)+= pinctrl-imxrt.o
+obj-$(CONFIG_PINCTRL_IMX_SCMI) += pinctrl-scmi.o
diff --git a/drivers/pinctrl/nxp/pinctrl-scmi.c 
b/drivers/pinctrl/nxp/pinctrl-scmi.c
new file mode 100644
index 000..4a791b7e951
--- /dev/null
+++ b/drivers/pinctrl/nxp/pinctrl-scmi.c
@@ -0,0 +1,143 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 NXP
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "pinctrl-imx.h"
+
+#define DAISY_OFFSET_IMX93 0x360
+#define DAISY_OFFSET_IMX95 0x408
+
+/* SCMI pin control types */
+#define PINCTRL_TYPE_MUX192
+#define PINCTRL_TYPE_CONFIG 193
+#define PINCTRL_TYPE_DAISY_ID   194
+#define PINCTRL_TYPE_DAISY_CFG  195
+#define PINCTRL_NUM_CFGS_SHIFT  2
+
+struct imx_scmi_pinctrl_priv {
+   u16 daisy_offset;
+};
+
+static int imx_pinconf_scmi_set(struct udevice *dev, u32 mux_ofs, u32 mux, u32 
config_val,
+   u32 input_ofs, u32 input_val)
+{
+   struct imx_scmi_pinctrl_priv *priv = dev_get_priv(dev);
+   int ret, num_cfgs = 0;
+   struct scmi_msg msg;
+
+   /* Call SCMI API to set the pin mux and configuration. */
+   struct scmi_pinctrl_config_set_out out;
+   struct scmi_pinctrl_config_set_in in = {
+   .identifier = mux_ofs / 4,
+   .function_id = 0x,
+   .attributes = 0,
+   };
+
+   if (mux_ofs != 0) {
+   in.configs[num_cfgs].type = PINCTRL_TYPE_MUX;
+   in.configs[num_cfgs].val = mux;
+   num_cfgs++;
+   }
+
+   if (config_val != 0) {
+   in.configs[num_cfgs].type = PINCTRL_TYPE_CONFIG;
+   in.configs[num_cfgs].val = config_val;
+   num_cfgs++;
+   }
+
+   if (input_ofs != 0) {
+   in.configs[num_cfgs].type = PINCTRL_TYPE_DAISY_ID;
+   in.configs[num_cfgs].val = (input_ofs -  priv->daisy_offset) / 
4;
+   num_cfgs++;
+   in.configs[num_cfgs].type = PINCTRL_TYPE_DAISY_CFG;
+   in.configs[num_cfgs].val = input_val;
+   num_cfgs++;
+   }
+
+   /* Update the number of configs sent in this call. */
+   in.attributes = num_cfgs << PINCTRL_NUM_CFGS_SHIFT;
+
+   msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_PINCTRL,
+ SCMI_MSG_PINCTRL_CONFIG_SET, in, out);
+
+   ret = devm_scmi_process_msg(dev, &msg);
+   if (ret || out.status != 0) {
+   dev_err(dev, "Failed to set PAD = %d, daisy = %d, scmi_err = 
%d, ret = %d\n",
+   mux_ofs / 4, input_ofs / 4, out.status, ret);
+   }
+
+   return ret;
+}
+
+static int imx_pinctrl_set_state_scmi(struct udevice *dev, struct udevice 
*config)
+{
+   int mux_ofs, mux, config_val, input_reg, input_val;
+   u32 *pin_data;
+   int i, j = 0;
+   int npins;
+   int ret;
+
+   ret = imx_pinctrl_set_state_common(dev, config, FSL_PIN_SIZE,
+  &pin_data, &npins);
+   if

[PATCH v5 08/20] clk: scmi: check the clock state/parent/rate control permissions

2025-02-18 Thread Alice Guo (OSS)

From: Alice Guo 

Clock driver based on SCMI clock management protocol in Linux checks
clock state, parent and rate control permissions. To be consistent with
the kernel driver, add this check here.

When using common clock framework (CCF), use the clock signal ID to get
the clock registered by clk_register() in scmi_clk_probe(), and then
obatin the struct clk_scmi variable with container_of().

Signed-off-by: Alice Guo 
Signed-off-by: Ye Li 
Reviewed-by: Peng Fan 
---
 drivers/clk/clk_scmi.c   | 172 ---
 include/scmi_protocols.h |  26 +-
 2 files changed, 187 insertions(+), 11 deletions(-)

diff --git a/drivers/clk/clk_scmi.c b/drivers/clk/clk_scmi.c
index 84333cdd0cc..4fce92d064f 100644
--- a/drivers/clk/clk_scmi.c
+++ b/drivers/clk/clk_scmi.c
@@ -12,6 +12,56 @@
 #include 
 #include 
 
+struct clk_scmi {
+   struct clk clk;
+   u32 ctrl_flags;
+};
+
+static int scmi_clk_get_permissions(struct udevice *dev, int clkid, u32 *perm)
+{
+   u32 version;
+   int ret;
+
+   ret = scmi_generic_protocol_version(dev, SCMI_PROTOCOL_ID_CLOCK, 
&version);
+   if (ret) {
+   debug("get SCMI clock management protocol version failed\n");
+   return ret;
+   }
+
+   if (version < CLOCK_PROTOCOL_VERSION_3_0) {
+   debug("SCMI clock management protocol version is less than 
3.0.\n");
+   return -EINVAL;
+   }
+
+   struct scmi_clk_get_permissions_in in = {
+   .clock_id = clkid,
+   };
+   struct scmi_clk_get_permissions_out out;
+   struct scmi_msg msg = {
+   .protocol_id = SCMI_PROTOCOL_ID_CLOCK,
+   .message_id = SCMI_CLOCK_GET_PERMISSIONS,
+   .in_msg = (u8 *)&in,
+   .in_msg_sz = sizeof(in),
+   .out_msg = (u8 *)&out,
+   .out_msg_sz = sizeof(out),
+   };
+
+   ret = devm_scmi_process_msg(dev, &msg);
+   if (ret) {
+   debug("get SCMI clock management protocol permissions 
failed\n");
+   return ret;
+   }
+
+   ret = scmi_to_linux_errno(out.status);
+   if (ret < 0) {
+   debug("the status code of getting permissions: %d\n", ret);
+   return ret;
+   }
+
+   *perm = out.permissions;
+   return 0;
+}
+
 static int scmi_clk_get_num_clock(struct udevice *dev, size_t *num_clocks)
 {
struct scmi_clk_protocol_attr_out out;
@@ -32,7 +82,8 @@ static int scmi_clk_get_num_clock(struct udevice *dev, size_t 
*num_clocks)
return 0;
 }
 
-static int scmi_clk_get_attibute(struct udevice *dev, int clkid, char **name)
+static int scmi_clk_get_attibute(struct udevice *dev, int clkid, char **name,
+u32 *attr)
 {
struct scmi_clk_attribute_in in = {
.clock_id = clkid,
@@ -53,6 +104,7 @@ static int scmi_clk_get_attibute(struct udevice *dev, int 
clkid, char **name)
return ret;
 
*name = strdup(out.clock_name);
+   *attr = out.attributes;
 
return 0;
 }
@@ -78,11 +130,49 @@ static int scmi_clk_gate(struct clk *clk, int enable)
 
 static int scmi_clk_enable(struct clk *clk)
 {
+   struct clk_scmi *clkscmi;
+   struct clk *c;
+   int ret;
+
+   if (CONFIG_IS_ENABLED(CLK_CCF)) {
+   ret = clk_get_by_id(clk->id, &c);
+   if (ret)
+   return ret;
+
+   clkscmi = container_of(c, struct clk_scmi, clk);
+
+   if (clkscmi->ctrl_flags & SUPPORT_CLK_STAT_CONTROL)
+   return scmi_clk_gate(clk, 1);
+
+   /* Following Linux drivers/clk/clk-scmi.c, directly return 0 if 
agent has no permission. */
+   debug("SCMI CLOCK: the clock cannot be enabled by the 
agent.\n");
+   return 0;
+   }
+
return scmi_clk_gate(clk, 1);
 }
 
 static int scmi_clk_disable(struct clk *clk)
 {
+   struct clk_scmi *clkscmi;
+   struct clk *c;
+   int ret;
+
+   if (CONFIG_IS_ENABLED(CLK_CCF)) {
+   ret = clk_get_by_id(clk->id, &c);
+   if (ret)
+   return ret;
+
+   clkscmi = container_of(c, struct clk_scmi, clk);
+
+   if (clkscmi->ctrl_flags & SUPPORT_CLK_STAT_CONTROL)
+   return scmi_clk_gate(clk, 0);
+
+   /* Following Linux drivers/clk/clk-scmi.c, directly return 0 if 
agent has no permission. */
+   debug("SCMI CLOCK: the clock cannot be disabled by the 
agent.\n");
+   return 0;
+   }
+
return scmi_clk_gate(clk, 0);
 }
 
@@ -108,7 +198,7 @@ static ulong scmi_clk_get_rate(struct clk *clk)
return (ulong)(((u64)out.rate_msb << 32) | out.rate_lsb);
 }
 
-static ulong scmi_clk_set_rate(struct clk *clk, ulong rate)
+static ulong __scmi_clk_set_rate(struct clk *clk, ulong rate)
 {
struct scmi_clk_rate_set_in in = {
.clock_id = clk->id,
@@ -

[PATCH v5 06/20] scmi_protocols: add SCMI Performance domain management protocol message IDs

2025-02-18 Thread Alice Guo (OSS)

From: Peng Fan 

SCMI Performance domain management protocol is intended for performance
management of groups of devices or APs that run in the same performance
domain. The functionality provided by the callee-side can be used by
passing the corresponding message_id.

Signed-off-by: Peng Fan 
Signed-off-by: Alice Guo 
Reviewed-by: Ye Li 
---
 include/scmi_protocols.h | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/include/scmi_protocols.h b/include/scmi_protocols.h
index 06de4a601f8..34f272c448c 100644
--- a/include/scmi_protocols.h
+++ b/include/scmi_protocols.h
@@ -1046,4 +1046,22 @@ struct scmi_pinctrl_config_set_out {
s32 status;
 };
 
+/* SCMI Perf Protocol */
+enum scmi_perf_message_id {
+   SCMI_PERF_DOMAIN_ATTRIBUTES = 0x3,
+   SCMI_PERF_DESCRIBE_LEVELS = 0x4,
+   SCMI_PERF_LIMITS_SET = 0x5,
+   SCMI_PERF_LIMITS_GET = 0x6,
+   SCMI_PERF_LEVEL_SET = 0x7,
+   SCMI_PERF_LEVEL_GET = 0x8
+};
+
+struct scmi_perf_in {
+   u32 domain_id;
+   u32 perf_level;
+};
+
+struct scmi_perf_out {
+   s32 status;
+};
 #endif /* _SCMI_PROTOCOLS_H */
-- 
2.43.0

[PATCH v5 07/20] clk: scmi: add the command CLOCK_PARENT_SET

2025-02-18 Thread Alice Guo (OSS)

From: Peng Fan 

This patch adds the command CLOCK_PARENT_SET that can be used to set the
parent of a clock. ARM SCMI Version 3.2 supports to change the parent of
a clock device.

Signed-off-by: Peng Fan 
Signed-off-by: Alice Guo 
Reviewed-by: Ye Li 
---
 drivers/clk/clk_scmi.c   | 20 
 include/scmi_protocols.h | 19 +++
 2 files changed, 39 insertions(+)

diff --git a/drivers/clk/clk_scmi.c b/drivers/clk/clk_scmi.c
index e42d2032d45..84333cdd0cc 100644
--- a/drivers/clk/clk_scmi.c
+++ b/drivers/clk/clk_scmi.c
@@ -178,11 +178,31 @@ static int scmi_clk_probe(struct udevice *dev)
return 0;
 }
 
+static int scmi_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+   struct scmi_clk_parent_set_in in = {
+   .clock_id = clk->id,
+   .parent_clk = parent->id,
+   };
+   struct scmi_clk_parent_set_out out;
+   struct scmi_msg msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_CLOCK,
+ SCMI_CLOCK_PARENT_SET,
+ in, out);
+   int ret;
+
+   ret = devm_scmi_process_msg(clk->dev, &msg);
+   if (ret < 0)
+   return ret;
+
+   return scmi_to_linux_errno(out.status);
+}
+
 static const struct clk_ops scmi_clk_ops = {
.enable = scmi_clk_enable,
.disable = scmi_clk_disable,
.get_rate = scmi_clk_get_rate,
.set_rate = scmi_clk_set_rate,
+   .set_parent = scmi_clk_set_parent,
 };
 
 U_BOOT_DRIVER(scmi_clock) = {
diff --git a/include/scmi_protocols.h b/include/scmi_protocols.h
index 34f272c448c..0d8c177025c 100644
--- a/include/scmi_protocols.h
+++ b/include/scmi_protocols.h
@@ -737,6 +737,7 @@ enum scmi_clock_message_id {
SCMI_CLOCK_RATE_SET = 0x5,
SCMI_CLOCK_RATE_GET = 0x6,
SCMI_CLOCK_CONFIG_SET = 0x7,
+   SCMI_CLOCK_PARENT_SET = 0xD
 };
 
 #define SCMI_CLK_PROTO_ATTR_COUNT_MASK GENMASK(15, 0)
@@ -839,6 +840,24 @@ struct scmi_clk_rate_set_out {
s32 status;
 };
 
+/**
+ * struct scmi_clk_parent_state_in - Message payload for CLOCK_PARENT_SET 
command
+ * @clock_id:  SCMI clock ID
+ * @parent_clk:SCMI clock ID
+ */
+struct scmi_clk_parent_set_in {
+   u32 clock_id;
+   u32 parent_clk;
+};
+
+/**
+ * struct scmi_clk_parent_set_out - Response payload for CLOCK_PARENT_SET 
command
+ * @status:SCMI command status
+ */
+struct scmi_clk_parent_set_out {
+   s32 status;
+};
+
 /*
  * SCMI Reset Domain Protocol
  */
-- 
2.43.0

[PATCH v5 05/20] scmi_protocols: add SCMI misc protocol protocol_id and message_id for getting the ROM passover data

2025-02-18 Thread Alice Guo (OSS)

From: Peng Fan 

SCMI misc protocol is intended for miscellaneous functions which are
device specific and are usually defined to access bit fields. This patch
adds SCMI misc protocol protocol_id and message_id for getting the ROM
passover data.

Signed-off-by: Peng Fan 
Signed-off-by: Alice Guo 
Reviewed-by: Ye Li 
---
 include/scmi_protocols.h | 5 +
 1 file changed, 5 insertions(+)

diff --git a/include/scmi_protocols.h b/include/scmi_protocols.h
index 279ebbad440..06de4a601f8 100644
--- a/include/scmi_protocols.h
+++ b/include/scmi_protocols.h
@@ -25,6 +25,7 @@ enum scmi_std_protocol {
SCMI_PROTOCOL_ID_RESET_DOMAIN = 0x16,
SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN = 0x17,
SCMI_PROTOCOL_ID_PINCTRL = 0x19,
+   SCMI_PROTOCOL_ID_IMX_MISC = 0x84,
 };
 
 enum scmi_status_code {
@@ -50,6 +51,10 @@ enum scmi_discovery_id {
SCMI_PROTOCOL_MESSAGE_ATTRIBUTES = 0x2,
 };
 
+enum scmi_imx_misc_message_id {
+   SCMI_MISC_ROM_PASSOVER_GET = 0x7
+};
+
 /*
  * SCMI Base Protocol
  */
-- 
2.43.0

[PATCH v5 11/20] imx9: scmi: add i.MX95 SoC and clock related code

2025-02-18 Thread Alice Guo (OSS)

From: Peng Fan 

This patch adds i.MX95 SoC and clock related code. Because they are
based on SCMI, put them in the scmi subfolder.

Signed-off-by: Ye Li 
Signed-off-by: Peng Fan 
Signed-off-by: Alice Guo 
Reviewed-by: Peng Fan 
---
 arch/arm/include/asm/arch-imx/cpu.h|   2 +
 arch/arm/include/asm/arch-imx9/clock.h |  10 +
 arch/arm/include/asm/arch-imx9/imx-regs.h  |   5 +
 arch/arm/include/asm/arch-imx9/sys_proto.h |   1 +
 arch/arm/include/asm/mach-imx/sys_proto.h  |  39 +
 arch/arm/mach-imx/imx9/scmi/Makefile   |   6 +
 arch/arm/mach-imx/imx9/scmi/clock.c| 105 +++
 arch/arm/mach-imx/imx9/scmi/clock_scmi.c   | 133 
 arch/arm/mach-imx/imx9/scmi/soc.c  | 788 +
 arch/sandbox/include/asm/scmi_test.h   |   2 +-
 10 files changed, 1090 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-imx/imx9/scmi/Makefile
 create mode 100644 arch/arm/mach-imx/imx9/scmi/clock.c
 create mode 100644 arch/arm/mach-imx/imx9/scmi/clock_scmi.c
 create mode 100644 arch/arm/mach-imx/imx9/scmi/soc.c

diff --git a/arch/arm/include/asm/arch-imx/cpu.h 
b/arch/arm/include/asm/arch-imx/cpu.h
index 0d7a5734616..1f669c72d00 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -76,6 +76,8 @@
 #define MXC_CPU_IMX91110xCD /* dummy ID */
 #define MXC_CPU_IMX91010xCE /* dummy ID */
 
+#define MXC_CPU_IMX95  0x1C1 /* dummy ID */
+
 #define MXC_SOC_MX60x60
 #define MXC_SOC_MX70x70
 #define MXC_SOC_IMX8M  0x80
diff --git a/arch/arm/include/asm/arch-imx9/clock.h 
b/arch/arm/include/asm/arch-imx9/clock.h
index 60d48b13b11..ffaf6b5f7d8 100644
--- a/arch/arm/include/asm/arch-imx9/clock.h
+++ b/arch/arm/include/asm/arch-imx9/clock.h
@@ -255,5 +255,15 @@ int ccm_shared_gpr_tz_access(u32 gpr, bool non_secure, 
bool user_mode, bool lock
 void enable_usboh3_clk(unsigned char enable);
 int set_clk_enet(enum enet_freq type);
 int set_clk_eqos(enum enet_freq type);
+
+int imx_clk_scmi_enable(u32 clock_id, bool enable);
+ulong imx_clk_scmi_set_rate(u32 clock_id, ulong rate);
+ulong imx_clk_scmi_get_rate(u32 clock_id);
+int imx_clk_scmi_set_parent(u32 clock_id, u32 parent_id);
 void set_arm_clk(ulong freq);
+
+int imx_clk_scmi_enable(u32 clock_id, bool enable);
+ulong imx_clk_scmi_set_rate(u32 clock_id, ulong rate);
+ulong imx_clk_scmi_get_rate(u32 clock_id);
+int imx_clk_scmi_set_parent(u32 clock_id, u32 parent_id);
 #endif
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h 
b/arch/arm/include/asm/arch-imx9/imx-regs.h
index ef9538bd42e..f7f9c706e13 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -20,6 +20,11 @@
 #define WDG4_BASE_ADDR  0x424aUL
 #define WDG5_BASE_ADDR  0x424bUL
 
+#define GPIO2_BASE_ADDR0x4381UL
+#define GPIO3_BASE_ADDR0x4382UL
+#define GPIO4_BASE_ADDR0x4384UL
+#define GPIO5_BASE_ADDR0x4385UL
+
 #define FSB_BASE_ADDR   0x4751UL
 
 #define ANATOP_BASE_ADDR0x4448UL
diff --git a/arch/arm/include/asm/arch-imx9/sys_proto.h 
b/arch/arm/include/asm/arch-imx9/sys_proto.h
index e4bf6a63424..df2148a53c7 100644
--- a/arch/arm/include/asm/arch-imx9/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx9/sys_proto.h
@@ -12,6 +12,7 @@ enum imx9_soc_voltage_mode {
VOLT_LOW_DRIVE = 0,
VOLT_NOMINAL_DRIVE,
VOLT_OVER_DRIVE,
+   VOLT_SUPER_OVER_DRIVE,
 };
 
 void soc_power_init(void);
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h 
b/arch/arm/include/asm/mach-imx/sys_proto.h
index 109a806852a..0780f99b49a 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -97,6 +97,8 @@ struct bd_info;
 #define is_imx9302() (is_cpu_type(MXC_CPU_IMX9302))
 #define is_imx9301() (is_cpu_type(MXC_CPU_IMX9301))
 
+#define is_imx95() (is_cpu_type(MXC_CPU_IMX95))
+
 #define is_imx9121() (is_cpu_type(MXC_CPU_IMX9121))
 #define is_imx9111() (is_cpu_type(MXC_CPU_IMX9111))
 #define is_imx9101() (is_cpu_type(MXC_CPU_IMX9101))
@@ -216,6 +218,43 @@ ulong spl_romapi_get_uboot_base(u32 image_offset, u32 
rom_bt_dev);
 u32 rom_api_download_image(u8 *dest, u32 offset, u32 size);
 u32 rom_api_query_boot_infor(u32 info_type, u32 *info);
 
+#if IS_ENABLED(CONFIG_SCMI_FIRMWARE)
+typedef struct rom_passover {
+   u16 tag;   // Tag
+   u8  len;   // Fixed value of 0x80
+   u8  ver;   // Version
+   u32 boot_mode; // Boot mode
+   u32 card_addr_mode;// SD card address mode
+   u32 bad_blks_of_img_set0;  // NAND bad block count skipped 1
+   u32 ap_mu_id;  // AP MU ID
+   u32 bad_blks_of_img_set1;  // NAND bad block count skipped 1
+   u8  boot_stage;// Boot stage
+   u8  img_set_sel;   // Image set booted from
+   u8  rsv0[2];   //

[PATCH v5 12/20] spl: imx: use trampoline buffer to load images to secure region

2025-02-18 Thread Alice Guo (OSS)

From: Ye Li 

When SPL loading image to secure region, for example, ATF and tee to
DDR secure region. Because the USDHC controller is non-secure master,
it can't access this region and will cause loading issue.

So use a trampoline buffer in non-secure region, then use CPU to copy the
image from trampoline buffer to destination secure region.

Signed-off-by: Ye Li 
Signed-off-by: Alice Guo 
Reviewed-by: Peng Fan 
---
 arch/arm/mach-imx/imx9/scmi/soc.c | 18 ++
 common/spl/Kconfig|  6 +
 common/spl/spl_imx_container.c| 41 ++-
 3 files changed, 59 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-imx/imx9/scmi/soc.c 
b/arch/arm/mach-imx/imx9/scmi/soc.c
index 217e7ed41a4..1bacf526577 100644
--- a/arch/arm/mach-imx/imx9/scmi/soc.c
+++ b/arch/arm/mach-imx/imx9/scmi/soc.c
@@ -786,3 +786,21 @@ enum boot_device get_boot_device(void)
return boot_dev;
 }
 #endif
+
+bool arch_check_dst_in_secure(void *start, ulong size)
+{
+   ulong ns_end = CFG_SYS_SDRAM_BASE + PHYS_SDRAM_SIZE;
+#ifdef PHYS_SDRAM_2_SIZE
+   ns_end += PHYS_SDRAM_2_SIZE;
+#endif
+
+   if ((ulong)start < CFG_SYS_SDRAM_BASE || (ulong)start + size > ns_end)
+   return true;
+
+   return false;
+}
+
+void *arch_get_container_trampoline(void)
+{
+   return (void *)((ulong)CFG_SYS_SDRAM_BASE + PHYS_SDRAM_SIZE - SZ_16M);
+}
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 7d6780936d1..29bc119bb2e 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -362,6 +362,12 @@ config SPL_LOAD_IMX_CONTAINER
  Support booting U-Boot from an i.MX8 container image. If you are not
  using i.MX8, say 'n'.
 
+config SPL_IMX_CONTAINER_USE_TRAMPOLINE
+   bool
+   depends on SPL
+   help
+ Enable SPL load reader to load data to a trampoline buffer.
+
 config IMX_CONTAINER_CFG
string "i.MX8 Container config file"
depends on SPL && SPL_LOAD_IMX_CONTAINER
diff --git a/common/spl/spl_imx_container.c b/common/spl/spl_imx_container.c
index 2c31777fcd3..47fb2e65e34 100644
--- a/common/spl/spl_imx_container.c
+++ b/common/spl/spl_imx_container.c
@@ -14,6 +14,16 @@
 #include 
 #endif
 
+__weak bool arch_check_dst_in_secure(void *start, ulong size)
+{
+   return false;
+}
+
+__weak void *arch_get_container_trampoline(void)
+{
+   return NULL;
+}
+
 static struct boot_img_t *read_auth_image(struct spl_image_info *spl_image,
  struct spl_load_info *info,
  struct container_hdr *container,
@@ -22,6 +32,7 @@ static struct boot_img_t *read_auth_image(struct 
spl_image_info *spl_image,
 {
struct boot_img_t *images;
ulong offset, overhead, size;
+   void *buf, *trampoline;
 
if (image_index > container->num_images) {
debug("Invalid image number\n");
@@ -42,12 +53,30 @@ static struct boot_img_t *read_auth_image(struct 
spl_image_info *spl_image,
 
debug("%s: container: %p offset: %lu size: %lu\n", __func__,
  container, offset, size);
-   if (info->read(info, offset, size,
-  map_sysmem(images[image_index].dst - overhead,
- images[image_index].size)) <
-   images[image_index].size) {
-   printf("%s wrong\n", __func__);
-   return NULL;
+
+   buf = map_sysmem(images[image_index].dst - overhead, 
images[image_index].size);
+   if (IS_ENABLED(CONFIG_SPL_IMX_CONTAINER_USE_TRAMPOLINE) &&
+   arch_check_dst_in_secure(buf, size)) {
+   trampoline = arch_get_container_trampoline();
+   if (!trampoline) {
+   printf("%s: trampoline size is zero\n", __func__);
+   return NULL;
+   }
+
+   if (info->read(info, offset, size, trampoline) < 
images[image_index].size) {
+   printf("%s wrong\n", __func__);
+   return NULL;
+   }
+
+   memcpy(buf, trampoline, images[image_index].size);
+   } else {
+   if (info->read(info, offset, size,
+  map_sysmem(images[image_index].dst - overhead,
+ images[image_index].size)) <
+   images[image_index].size) {
+   printf("%s wrong\n", __func__);
+   return NULL;
+   }
}
 
 #ifdef CONFIG_AHAB_BOOT
-- 
2.43.0

[PATCH v5 10/20] scmi_protocols: update struct scmi_base_discover_list_protocols_out

2025-02-18 Thread Alice Guo (OSS)

From: Ye Li 

@protocols is an array of protocol identifiers that are implemented,
excluding the Base protocol. The number of elements of @protocols is
specified by callee-side. Currently, set it to 4 is enough for i.MX95.

Signed-off-by: Ye Li 
Signed-off-by: Alice Guo 
---
 include/scmi_protocols.h | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/include/scmi_protocols.h b/include/scmi_protocols.h
index 2684f4177dd..7ce73ddfae2 100644
--- a/include/scmi_protocols.h
+++ b/include/scmi_protocols.h
@@ -141,11 +141,14 @@ struct scmi_base_discover_impl_version_out {
  * @status:SCMI command status
  * @num_protocols: Number of SCMI protocols in @protocol
  * @protocols: Array of packed SCMI protocol ID's
+ *
+ * The number of elements of @protocols is specified by callee-side. Currently,
+ * set it to 4 is enough for i.MX95.
  */
 struct scmi_base_discover_list_protocols_out {
s32 status;
u32 num_protocols;
-   u32 protocols[3];
+   u32 protocols[4];
 };
 
 /**
-- 
2.43.0

[PATCH v5 13/20] imx9: add i.MX95 Kconfig and Makefile

2025-02-18 Thread Alice Guo (OSS)

From: Ye Li 

This patch adds i.MX95 Kconfig and Makefile. i.MX95 uses SCMI.

Signed-off-by: Ye Li 
Signed-off-by: Alice Guo 
Reviewed-by: Peng Fan 
---
 arch/arm/mach-imx/imx9/Kconfig  | 8 
 arch/arm/mach-imx/imx9/Makefile | 9 +++--
 2 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig
index 49220c0955e..ef364ca1a2f 100644
--- a/arch/arm/mach-imx/imx9/Kconfig
+++ b/arch/arm/mach-imx/imx9/Kconfig
@@ -21,6 +21,14 @@ config IMX91
select IMX9
select ARMV8_SPL_EXCEPTION_VECTORS
 
+config IMX95
+   bool
+   select ARMV8_SPL_EXCEPTION_VECTORS
+   select IMX9
+   select DM_MAILBOX
+   select SCMI_FIRMWARE
+   select SCMI_TRANSPORT_SMT_INTR
+   select SPL_IMX_CONTAINER_USE_TRAMPOLINE
 
 config SYS_SOC
default "imx9"
diff --git a/arch/arm/mach-imx/imx9/Makefile b/arch/arm/mach-imx/imx9/Makefile
index 45a9105a75a..53cc97c6b47 100644
--- a/arch/arm/mach-imx/imx9/Makefile
+++ b/arch/arm/mach-imx/imx9/Makefile
@@ -3,8 +3,13 @@
 # Copyright 2022 NXP
 
 obj-y += lowlevel_init.o
+
+ifeq ($(CONFIG_SCMI_FIRMWARE),y)
+obj-y += scmi/
+else
 obj-y += soc.o clock.o clock_root.o trdc.o
+endif
 
-#ifndef CONFIG_XPL_BUILD
+ifneq ($(CONFIG_SPL_BUILD),y)
 obj-y += imx_bootaux.o
-#endif
+endif
\ No newline at end of file
-- 
2.43.0

[PATCH v5 14/20] imx: Kconfig: IMX8_ROMAPI is not configured for i.MX95

2025-02-18 Thread Alice Guo (OSS)

From: Alice Guo 

i.MX95 only supports low power boot, which means A55 is kicked by M33.
There is no ROM runs on A55 in such case so that deselect IMX8_ROMAPI
for i.MX95.

Signed-off-by: Alice Guo 
---
 arch/arm/mach-imx/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 134e42028c3..f38f3b2d338 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -180,7 +180,7 @@ config DDRMC_VF610_CALIBRATION
 
 config IMX8_ROMAPI
def_bool y
-   depends on IMX8MN || IMX8MP || IMX8ULP || IMX9
+   depends on IMX8MN || IMX8MP || IMX8ULP || IMX93 || IMX91
 
 config SPL_IMX_ROMAPI_LOADADDR
hex "Default load address to load image through ROM API"
-- 
2.43.0

[PATCH v5 17/20] imx: add V2X container support on i.MX95

2025-02-18 Thread Alice Guo (OSS)

From: Teo Hall 

This patch adds V2X container support on i.MX95.

Signed-off-by: Ye Li 
Signed-off-by: Teo Hall 
Signed-off-by: Alice Guo 
---
 arch/arm/mach-imx/image-container.c | 63 ++---
 1 file changed, 40 insertions(+), 23 deletions(-)

diff --git a/arch/arm/mach-imx/image-container.c 
b/arch/arm/mach-imx/image-container.c
index 2afe9d38a06..54ae7721888 100644
--- a/arch/arm/mach-imx/image-container.c
+++ b/arch/arm/mach-imx/image-container.c
@@ -231,45 +231,62 @@ static unsigned long get_boot_device_offset(void *dev, 
int dev_type)
return offset;
 }
 
-static int get_imageset_end(void *dev, int dev_type)
+static ulong get_imageset_end(void *dev, int dev_type)
 {
-   unsigned long offset1 = 0, offset2 = 0;
-   int value_container[2];
+   unsigned long offset[3] = {};
+   int value_container[3] = {};
u16 hdr_length;
 
-   offset1 = get_boot_device_offset(dev, dev_type);
-   offset2 = CONTAINER_HDR_ALIGNMENT + offset1;
+   offset[0] = get_boot_device_offset(dev, dev_type);
 
-   value_container[0] = get_dev_container_size(dev, dev_type, offset1, 
&hdr_length);
+   value_container[0] = get_dev_container_size(dev, dev_type, offset[0], 
&hdr_length);
if (value_container[0] < 0) {
printf("Parse seco container failed %d\n", value_container[0]);
-   return value_container[0];
+   return 0;
}
 
debug("seco container size 0x%x\n", value_container[0]);
 
-   value_container[1] = get_dev_container_size(dev, dev_type, offset2, 
&hdr_length);
-   if (value_container[1] < 0) {
-   debug("Parse scu container failed %d, only seco container\n",
- value_container[1]);
-   /* return seco container total size */
-   return value_container[0] + offset1;
+   if (is_imx95()) {
+   offset[1] = ALIGN(hdr_length, CONTAINER_HDR_ALIGNMENT) + 
offset[0];
+
+   value_container[1] = get_dev_container_size(dev, dev_type, 
offset[1], &hdr_length);
+   if (value_container[1] < 0) {
+   printf("Parse v2x container failed %d\n", 
value_container[1]);
+   return value_container[0] + offset[0]; /* return seco 
container total size */
+   }
+
+   debug("v2x container size 0x%x\n", value_container[1]);
+
+   offset[2] = ALIGN(hdr_length, CONTAINER_HDR_ALIGNMENT) + 
offset[1];
+   } else {
+   /* Skip offset[1] */
+   offset[2] = ALIGN(hdr_length, CONTAINER_HDR_ALIGNMENT) + 
offset[0];
}
 
-   debug("scu container size 0x%x\n", value_container[1]);
+   value_container[2] = get_dev_container_size(dev, dev_type, offset[2], 
&hdr_length);
+   if (value_container[2] < 0) {
+   debug("Parse scu container image failed %d, only seco 
container\n", value_container[2]);
+   if (is_imx95())
+   return value_container[1] + offset[1]; /* return seco + 
v2x container total size */
+   else
+   return value_container[0] + offset[0]; /* return seco 
container total size */
+   }
 
-   return value_container[1] + offset2;
+   debug("scu container size 0x%x\n", value_container[2]);
+
+   return value_container[2] + offset[2];
 }
 
 #ifdef CONFIG_SPL_SPI_LOAD
 unsigned int spl_spi_get_uboot_offs(struct spi_flash *flash)
 {
-   int end;
+   ulong end;
 
end = get_imageset_end(flash, QSPI_DEV);
end = ROUND(end, SZ_1K);
 
-   printf("Load image from QSPI 0x%x\n", end);
+   printf("Load image from QSPI 0x%lx\n", end);
 
return end;
 }
@@ -279,12 +296,12 @@ unsigned int spl_spi_get_uboot_offs(struct spi_flash 
*flash)
 unsigned long arch_spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
unsigned long raw_sect)
 {
-   int end;
+   ulong end;
 
end = get_imageset_end(mmc, MMC_DEV);
end = ROUND(end, SZ_1K);
 
-   printf("Load image from MMC/SD 0x%x\n", end);
+   printf("Load image from MMC/SD 0x%lx\n", end);
 
return end / mmc->read_bl_len;
 }
@@ -312,12 +329,12 @@ int spl_mmc_emmc_boot_partition(struct mmc *mmc)
 #ifdef CONFIG_SPL_NAND_SUPPORT
 uint32_t spl_nand_get_uboot_raw_page(void)
 {
-   int end;
+   ulong end;
 
end = get_imageset_end((void *)NULL, NAND_DEV);
end = ROUND(end, SZ_16K);
 
-   printf("Load image from NAND 0x%x\n", end);
+   printf("Load image from NAND 0x%lx\n", end);
 
return end;
 }
@@ -326,7 +343,7 @@ uint32_t spl_nand_get_uboot_raw_page(void)
 #ifdef CONFIG_SPL_NOR_SUPPORT
 unsigned long spl_nor_get_uboot_base(void)
 {
-   int end;
+   ulong end;
 
/* Calculate the image set end,
 * if it is less than CFG_SYS_UBOOT_BASE(0x8281000),
@@ -339,7 +356,7 @@ unsigned long spl_nor_get_uboot_base(void)
els

[PATCH v5 19/20] imx95_evk: add i.MX95 19x19 EVK board basic support

2025-02-18 Thread Alice Guo (OSS)

From: Ye Li 

This patch adds i.MX95 19x19 EVK board basic support.

Messaging unit for EdgeLock Secure Enclave, messaging unit for System
Manager, uSDHC for SD Card, gpio, lpuart are supported now.

Signed-off-by: Ye Li 
Signed-off-by: Alice Guo 
Reviewed-by: Peng Fan 
---
 arch/arm/dts/imx95-19x19-evk-u-boot.dtsi  |  62 +++
 arch/arm/dts/imx95-u-boot.dtsi| 157 +
 arch/arm/mach-imx/imx9/Kconfig|   6 +
 arch/arm/mach-imx/imx9/scmi/container.cfg |  10 ++
 arch/arm/mach-imx/imx9/scmi/imximage.cfg  |  15 ++
 board/freescale/imx95_evk/Kconfig |  12 ++
 board/freescale/imx95_evk/MAINTAINERS |   6 +
 board/freescale/imx95_evk/Makefile|  11 ++
 board/freescale/imx95_evk/imx95_19x19_evk.env |  90 ++
 board/freescale/imx95_evk/imx95_evk.c |  36 
 board/freescale/imx95_evk/spl.c   |  72 
 configs/imx95_19x19_evk_defconfig | 160 ++
 doc/board/nxp/imx95_evk.rst   | 114 +
 doc/board/nxp/index.rst   |   1 +
 include/configs/imx95_evk.h   |  24 +++
 15 files changed, 776 insertions(+)
 create mode 100644 arch/arm/dts/imx95-19x19-evk-u-boot.dtsi
 create mode 100644 arch/arm/dts/imx95-u-boot.dtsi
 create mode 100644 arch/arm/mach-imx/imx9/scmi/container.cfg
 create mode 100644 arch/arm/mach-imx/imx9/scmi/imximage.cfg
 create mode 100644 board/freescale/imx95_evk/Kconfig
 create mode 100644 board/freescale/imx95_evk/MAINTAINERS
 create mode 100644 board/freescale/imx95_evk/Makefile
 create mode 100644 board/freescale/imx95_evk/imx95_19x19_evk.env
 create mode 100644 board/freescale/imx95_evk/imx95_evk.c
 create mode 100644 board/freescale/imx95_evk/spl.c
 create mode 100644 configs/imx95_19x19_evk_defconfig
 create mode 100644 doc/board/nxp/imx95_evk.rst
 create mode 100644 include/configs/imx95_evk.h

diff --git a/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi 
b/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi
new file mode 100644
index 000..2d1f02baa5f
--- /dev/null
+++ b/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 NXP
+ */
+
+#include "imx95-u-boot.dtsi"
+
+&lpuart1 {
+   bootph-pre-ram;
+};
+
+®_usdhc2_vmmc {
+   bootph-pre-ram;
+};
+
+&usdhc1 {
+   bootph-pre-ram;
+};
+
+&usdhc2 {
+   bootph-pre-ram;
+};
+
+&wdog3 {
+   status = "disabled";
+};
+
+&pinctrl_uart1 {
+   bootph-pre-ram;
+};
+
+&pinctrl_usdhc1 {
+   bootph-pre-ram;
+};
+
+&pinctrl_usdhc1_100mhz {
+   bootph-pre-ram;
+};
+
+&pinctrl_usdhc1_200mhz {
+   bootph-pre-ram;
+};
+
+&pinctrl_usdhc2 {
+   bootph-pre-ram;
+};
+
+&pinctrl_usdhc2_100mhz {
+   bootph-pre-ram;
+};
+
+&pinctrl_usdhc2_200mhz {
+   bootph-pre-ram;
+};
+
+&pinctrl_usdhc2_gpio {
+   bootph-pre-ram;
+};
+
+&pinctrl_reg_usdhc2_vmmc {
+   bootph-pre-ram;
+};
diff --git a/arch/arm/dts/imx95-u-boot.dtsi b/arch/arm/dts/imx95-u-boot.dtsi
new file mode 100644
index 000..b0dcf765a77
--- /dev/null
+++ b/arch/arm/dts/imx95-u-boot.dtsi
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 NXP
+ */
+
+/ {
+   binman {
+   multiple-images;
+
+   m33-oei-ddrfw {
+   pad-byte = <0x00>;
+   align-size = <0x8>;
+   filename = "m33-oei-ddrfw.bin";
+
+   oei-m33-ddr {
+   align-size = <0x4>;
+   filename = "oei-m33-ddr.bin";
+   type = "blob-ext";
+   };
+
+   imx-lpddr {
+   type = "nxp-header-ddrfw";
+
+   imx-lpddr-imem {
+   filename = "lpddr5_imem_v202311.bin";
+   type = "blob-ext";
+   };
+
+   imx-lpddr-dmem {
+   filename = "lpddr5_dmem_v202311.bin";
+   type = "blob-ext";
+   };
+   };
+
+   imx-lpddr-qb {
+   type = "nxp-header-ddrfw";
+
+   imx-lpddr-imem-qb {
+   filename = "lpddr5_imem_qb_v202311.bin";
+   type = "blob-ext";
+   };
+
+   imx-lpddr-dmem-qb {
+   filename = "lpddr5_dmem_qb_v202311.bin";
+   type = "blob-ext";
+   };
+   };
+   };
+
+   imx-boot {
+   filename = "flash.bin";
+   pad-byte = <0x00>;
+

[PATCH v5 16/20] tools: imx8image: add i.MX95 support

2025-02-18 Thread Alice Guo (OSS)

From: Alice Guo 

i.MX95 uses binman to invoke mkimage to create image container. 2 image
containers are needed currently. The first one is composed of
ahab-container.img, LPDDR firmware images, OEI images, System Manager
image and u-boot-spl.bin. The second one is consisted of ARM Trusted
firmware and u-boot.bin.

Because DDR OEI image and LPDDR firmware images have to be packaged
together and named as m33-oei-ddrfw.bin by binman, so imx9_image.sh does
not check if m33-oei-ddrfw.bin exists.

When using "make imx95_19x19_evk_defconfig; make", imx9_image.sh will
delete the line for u-boot.bin in container.cfg. In fact, binman is
always called after the u-boot.bin is built, so imx9_image.sh does not
check if u-boot.bin exists.

Signed-off-by: Alice Guo 
---
 include/imx8image.h |  19 +-
 tools/imx8image.c   | 143 +++-
 tools/imx9_image.sh |   8 +++
 3 files changed, 153 insertions(+), 17 deletions(-)

diff --git a/include/imx8image.h b/include/imx8image.h
index 6b95e93fb50..b48e2b03969 100644
--- a/include/imx8image.h
+++ b/include/imx8image.h
@@ -157,7 +157,9 @@ enum imx8image_cmd {
CMD_SOC_TYPE,
CMD_CONTAINER,
CMD_IMAGE,
-   CMD_DATA
+   CMD_DATA,
+   CMD_DUMMY_V2X,
+   CMD_HOLD
 };
 
 enum imx8image_core_type {
@@ -169,7 +171,9 @@ enum imx8image_core_type {
CFG_A35,
CFG_A55,
CFG_A53,
-   CFG_A72
+   CFG_A72,
+   CFG_M33,
+   CFG_OEI
 };
 
 enum imx8image_fld_types {
@@ -208,7 +212,10 @@ typedef enum option_type {
FILEOFF,
MSG_BLOCK,
SENTINEL,
-   UPOWER
+   UPOWER,
+   OEI,
+   DUMMY_V2X,
+   HOLD
 } option_type_t;
 
 typedef struct {
@@ -227,12 +234,16 @@ typedef struct {
 #define CORE_CA35   4
 #define CORE_CA72   5
 #define CORE_SECO   6
+#define CORE_M337
 
 #define CORE_ULP_CM33  0x1
 #define CORE_ULP_CA35  0x2
 #define CORE_ULP_UPOWER0x4
 #define CORE_ULP_SENTINEL  0x6
 
+#define CORE_IMX95_M33P0
+#define CORE_IMX95_A55C0   2
+
 #define SC_R_OTP   357U
 #define SC_R_DEBUG 354U
 #define SC_R_ROM_0 236U
@@ -246,10 +257,12 @@ typedef struct {
 #define IMG_TYPE_EXEC0x03   /* Executable image type */
 #define IMG_TYPE_DATA0x04   /* Data image type */
 #define IMG_TYPE_DCD_DDR 0x05   /* DCD/DDR image type */
+#define IMG_TYPE_OEI 0x05   /* Optional Executable image type */
 #define IMG_TYPE_SECO0x06   /* SECO image type */
 #define IMG_TYPE_SENTINEL 0x06 /* SENTINEL image type */
 #define IMG_TYPE_PROV0x07   /* Provisioning image type */
 #define IMG_TYPE_DEK 0x08   /* DEK validation type */
+#define IMG_TYPE_V2X_DUMMY 0x0E /* V2X Dummy image */
 
 #define IMG_TYPE_SHIFT   0
 #define IMG_TYPE_MASK0x1f
diff --git a/tools/imx8image.c b/tools/imx8image.c
index 15510d3e712..9c4b4317455 100644
--- a/tools/imx8image.c
+++ b/tools/imx8image.c
@@ -7,6 +7,7 @@
 
 #include "imx8image.h"
 #include 
+#include 
 
 static int p_idx;
 static int sector_size;
@@ -54,6 +55,8 @@ static table_entry_t imx8image_cmds[] = {
{CMD_CONTAINER, "CONTAINER","new container",  },
{CMD_IMAGE, "IMAGE","new image",  },
{CMD_DATA,  "DATA", "new data",   },
+   {CMD_DUMMY_V2X, "DUMMY_V2X","v2x",},
+   {CMD_HOLD,  "HOLD", "hold",   },
{-1,"", "",   },
 };
 
@@ -66,6 +69,8 @@ static table_entry_t imx8image_core_entries[] = {
{CFG_A55,   "A55",  "A55 core", },
{CFG_A53,   "A53",  "A53 core", },
{CFG_A72,   "A72",  "A72 core", },
+   {CFG_OEI,   "OEI",  "OEI", },
+   {CFG_M33,   "M33",  "M33 core", },
{-1,"", "", },
 };
 
@@ -144,6 +149,14 @@ static void parse_cfg_cmd(image_t *param_stack, int32_t 
cmd, char *token,
exit(EXIT_FAILURE);
}
break;
+   case CMD_DUMMY_V2X:
+   param_stack[p_idx].option = DUMMY_V2X;
+   param_stack[p_idx++].entry = (uint32_t)strtoll(token, NULL, 0);
+   break;
+   case CMD_HOLD:
+   param_stack[p_idx].option = HOLD;
+   param_stack[p_idx].entry = (uint32_t)strtoll(token, NULL, 0);
+   param_stack[p_idx++].filename = NULL;
default:
break;
}
@@ -221,6 +234,16 @@ static void parse_cfg_fld(image_t *param_stack, int32_t 
*cmd, char *token,
(*cmd == CMD_DATA) ? DATA : AP;
param_stack[p_idx].filename = token;
break;
+   case CFG_OEI:
+

[PATCH v5 15/20] binman: add a new entry type for packing DDR PHY firmware images

2025-02-18 Thread Alice Guo (OSS)

From: Alice Guo 

i.MX95 needs to combine DDR PHY firmware images and their byte counts
together, so add a new entry type nxp-header-ddrfw for this requirement.

Signed-off-by: Alice Guo 
---
 tools/binman/entries.rst  | 10 +++
 tools/binman/etype/nxp_header_ddrfw.py| 32 +++
 tools/binman/ftest.py | 11 
 tools/binman/test/346_nxp_ddrfw_imx95.dts | 24 +
 4 files changed, 77 insertions(+)
 create mode 100644 tools/binman/etype/nxp_header_ddrfw.py
 create mode 100644 tools/binman/test/346_nxp_ddrfw_imx95.dts

diff --git a/tools/binman/entries.rst b/tools/binman/entries.rst
index 780e9817fb6..6da3f0b9046 100644
--- a/tools/binman/entries.rst
+++ b/tools/binman/entries.rst
@@ -1663,6 +1663,16 @@ Properties / Entry arguments:
 
 
 
+.. _etype_nxp_header_ddrfw:
+
+Entry: nxp-header-ddrfw: add a header to DDR PHY firmware images
+---
+
+This entry is used to combine DDR PHY firmware images and their byte counts
+together. See imx95_evk.rst for how to get DDR PHY Firmware Images.
+
+
+
 .. _etype_opensbi:
 
 Entry: opensbi: RISC-V OpenSBI fw_dynamic blob
diff --git a/tools/binman/etype/nxp_header_ddrfw.py 
b/tools/binman/etype/nxp_header_ddrfw.py
new file mode 100644
index 000..80e0611df60
--- /dev/null
+++ b/tools/binman/etype/nxp_header_ddrfw.py
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2025 NXP
+
+from binman.etype.section import Entry_section
+
+class Entry_nxp_header_ddrfw(Entry_section):
+"""Add a header to DDR PHY firmware images
+
+This entry is used for i.MX95 to combine DDR PHY firmware images and their
+byte counts together.
+
+See imx95_evk.rst for how to get DDR PHY Firmware Images.
+"""
+
+def __init__(self, section, etype, node):
+super().__init__(section, etype, node)
+
+def BuildSectionData(self, required):
+section_data = bytearray()
+header_data = bytearray()
+
+for entry in self._entries.values():
+entry_data = entry.GetData(required)
+
+if not required and entry_data is None:
+return None
+
+section_data += entry_data
+header_data += entry.contents_size.to_bytes(4, 'little')
+
+return header_data + section_data
diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py
index a553ca9e564..62acc1d885c 100644
--- a/tools/binman/ftest.py
+++ b/tools/binman/ftest.py
@@ -104,6 +104,8 @@ PRE_LOAD_VERSION  = 0x11223344.to_bytes(4, 'big')
 PRE_LOAD_HDR_SIZE = 0x1000.to_bytes(4, 'big')
 TI_BOARD_CONFIG_DATA  = 
b'\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00'
 TI_UNSECURE_DATA  = b'unsecuredata'
+IMX_LPDDR_IMEM_DATA   = b'qwertyuiop1234567890'
+IMX_LPDDR_DMEM_DATA   = b'asdfghjklzxcvbnm'
 
 # Subdirectory of the input dir to use to put test FDTs
 TEST_FDT_SUBDIR   = 'fdts'
@@ -202,6 +204,8 @@ class TestFunctional(unittest.TestCase):
 TestFunctional._MakeInputFile('fsp_m.bin', FSP_M_DATA)
 TestFunctional._MakeInputFile('fsp_s.bin', FSP_S_DATA)
 TestFunctional._MakeInputFile('fsp_t.bin', FSP_T_DATA)
+TestFunctional._MakeInputFile('lpddr5_imem.bin', IMX_LPDDR_IMEM_DATA)
+TestFunctional._MakeInputFile('lpddr5_dmem.bin', IMX_LPDDR_DMEM_DATA)
 
 cls._elf_testdir = os.path.join(cls._indir, 'elftest')
 elf_test.BuildElfTestFiles(cls._elf_testdir)
@@ -7826,6 +7830,13 @@ fdt fdtmapExtract the devicetree 
blob from the fdtmap
 """Test that binman can produce an iMX8 image"""
 self._DoTestFile('339_nxp_imx8.dts')
 
+def testNxpHeaderDdrfw(self):
+"""Test that binman can add a header to DDR PHY firmware images"""
+data = self._DoReadFile('346_nxp_ddrfw_imx95.dts')
+self.assertEqual(len(IMX_LPDDR_IMEM_DATA).to_bytes(4, 'little') +
+ len(IMX_LPDDR_DMEM_DATA).to_bytes(4, 'little') +
+ IMX_LPDDR_IMEM_DATA + IMX_LPDDR_DMEM_DATA, data)
+
 def testFitSignSimple(self):
 """Test that image with FIT and signature nodes can be signed"""
 if not elf.ELF_TOOLS:
diff --git a/tools/binman/test/346_nxp_ddrfw_imx95.dts 
b/tools/binman/test/346_nxp_ddrfw_imx95.dts
new file mode 100644
index 000..889f6f29860
--- /dev/null
+++ b/tools/binman/test/346_nxp_ddrfw_imx95.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   binman {
+   imx-lpddr {
+   type = "nxp-header-ddrfw";
+
+   imx-lpddr-imem {
+   filename = "lpddr5_imem.bin";
+   type = "blob-ext";
+   };
+
+   imx-lpddr-dmem {
+   filename = "lpddr5_dmem.bin";
+   ty

[PATCH v5 18/20] doc: imx: add document for i.MX95 Image Container Format

2025-02-18 Thread Alice Guo (OSS)

From: Alice Guo 

This patch add a document for i.MX95 Image Container Format.

Signed-off-by: Alice Guo 
---
 doc/imx/imx95_container.txt | 136 
 1 file changed, 136 insertions(+)
 create mode 100644 doc/imx/imx95_container.txt

diff --git a/doc/imx/imx95_container.txt b/doc/imx/imx95_container.txt
new file mode 100644
index 000..2ad57345069
--- /dev/null
+++ b/doc/imx/imx95_container.txt
@@ -0,0 +1,136 @@
+i.MX95 Image Container Format
+-
+
+The image container set consists of some image containers, and image container
+contains boot images. Each image container has its own container header which 
is
+defined in Figure 1. All container headers are placed together in a continuous
+8KB space at the beginning of the image container set - image container set 
header.
+
+ROM code addresses image containers in image container set one by one based on
+their headers’ order in image container set header.
+
+If ELE container exists, its container header must be the 1st one in the image
+container set header.
+
+If V2X container exists, its container header must be the 2nd one in the image
+container set header. V2X must be combined with ELE container.
+
+The information of boot images are recorded in image container header. System
+ROM code needs to retrieve the information from the image container header, 
like
+the offset on boot source, the target address in RAM, the length of boot image.
+The order of ROM code handling these boot images is based on the order of each
+boot image information present in image container header.
+
+Figure 1:
+--- 
+--+--+--+--+
+  ^ |Tag   |Length|Length|Version  
 |
+  | 
+--+--+--+--+
+  | |   Flags  
 |
+  | 
+--+--+--+--+
+  | |# of Images   |Fuse version  |SW version  
 |
+Image | 
+--+--+--+--+
+Conatiner | |Reserved |Signature Block Offset  
 |
+Header| --- 
+--+--+--+--+
+  |   ^ |Image0: Offset, Size, LoadAddr, EntryPoint, Flags, Hash, 
IV|
+  |   | 
+--+--+--+--+
+  | Image | |Image1: Offset, Size, LoadAddr, EntryPoint, Flags, Hash, 
IV|
+  | Array | 
+--+--+--+--+
+  |   | |...   
 |
+  |   | 
+--+--+--+--+
+  v   v |ImageN: Offset, Size, LoadAddr, EntryPoint, Flags, Hash, 
IV|
+--- 
+--+--+--+--+
+|...   
 |
+--- 
+--+--+--+--+ <-- SignOffset
+  ^ |Tag   |Length|Length|Version  
 |
+  | 
+--+--+--+--+
+  | |SRK table offset |Certificate Offset  
 |
+  | 
+--+--+--+--+
+  | |Blob Offset  |Signature Offset
 |
+  | 
+--+--+--+--+
+Signature | | SRK Table
 |
+Block | 
+--+--+--+--+
+  | | Signature
 |
+  | 
+--+--+--+--+
+  | |   Certificate (optional) 
 |
+  | 
+--+--+--+--+
+  v |  Blob (optional) 
 |
+--- 
+--+--+--+--+
+|...   
 |
+
+--+--+--+--+ <-- Image0Offset
+|   Image0 
 |
+
+--+--+--+--+
+|...   
 |
+
+--+--+--+--+ <-- ImageNOffset
+|

[PATCH v5 20/20] Makefile: add some files to CLEAN_FILES

2025-02-18 Thread Alice Guo (OSS)

From: Alice Guo 

When building the flash.bin of i.MX95 with binman,
mkimage.imx-boot.spl, mkimage.imx-boot.u-boot,
mkimage-out.imx-boot.spl and mkimage-out.imx-boot.u-boot are created.
Add these files to CLEAN_FILES so that they can be removed when running
"make clean".

Signed-off-by: Alice Guo 
---
 Makefile | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index d4fedd87fe6..dd9d85e8a0b 100644
--- a/Makefile
+++ b/Makefile
@@ -2227,7 +2227,8 @@ CLEAN_FILES += include/autoconf.mk* include/bmp_logo.h 
include/bmp_logo_data.h \
   itb.fit.fit itb.fit.itb itb.map spl.map mkimage-out.rom.mkimage \
   mkimage.rom.mkimage mkimage-in-simple-bin* rom.map simple-bin* \
   idbloader-spi.img lib/efi_loader/helloworld_efi.S *.itb \
-  Test* capsule*.*.efi-capsule capsule*.map
+  Test* capsule*.*.efi-capsule capsule*.map mkimage.imx-boot.spl \
+  mkimage.imx-boot.u-boot mkimage-out.imx-boot.spl 
mkimage-out.imx-boot.u-boot
 
 # Directories & files removed with 'make mrproper'
 MRPROPER_DIRS  += include/config include/generated spl tpl vpl \
-- 
2.43.0

[PATCH v5 09/20] sandbox: add SCMI clock control permissions to sandbox

2025-02-18 Thread Alice Guo (OSS)

From: Alice Guo 

This patch is used to add SCMI clock control permissions to sandbox for
testing.

Signed-off-by: Alice Guo 
---
 arch/sandbox/include/asm/scmi_test.h   |  2 +
 drivers/firmware/scmi/sandbox-scmi_agent.c | 56 --
 2 files changed, 55 insertions(+), 3 deletions(-)

diff --git a/arch/sandbox/include/asm/scmi_test.h 
b/arch/sandbox/include/asm/scmi_test.h
index 619f8f5098c..b30e536a357 100644
--- a/arch/sandbox/include/asm/scmi_test.h
+++ b/arch/sandbox/include/asm/scmi_test.h
@@ -27,10 +27,12 @@ struct sandbox_scmi_pwd {
  * @id:Identifier of the clock used in the SCMI protocol
  * @enabled:   Clock state: true if enabled, false if disabled
  * @rate:  Clock rate in Hertz
+ * @perm:  Indicating state/parent/rate permission
  */
 struct sandbox_scmi_clk {
bool enabled;
ulong rate;
+   u32 perm;
 };
 
 /**
diff --git a/drivers/firmware/scmi/sandbox-scmi_agent.c 
b/drivers/firmware/scmi/sandbox-scmi_agent.c
index 19be280ec44..74a87832dcb 100644
--- a/drivers/firmware/scmi/sandbox-scmi_agent.c
+++ b/drivers/firmware/scmi/sandbox-scmi_agent.c
@@ -80,9 +80,9 @@ static struct sandbox_scmi_pwd scmi_pwdom[] = {
 };
 
 static struct sandbox_scmi_clk scmi_clk[] = {
-   { .rate = 333 },
-   { .rate = 200 },
-   { .rate = 1000 },
+   { .rate = 333, .perm = 0xE000 },
+   { .rate = 200, .perm = 0xE000 },
+   { .rate = 1000, .perm = 0xE000 },
 };
 
 static struct sandbox_scmi_reset scmi_reset[] = {
@@ -700,6 +700,21 @@ static int sandbox_scmi_pwd_name_get(struct udevice *dev, 
struct scmi_msg *msg)
 
 /* Clock Protocol */
 
+static int sandbox_scmi_clock_protocol_version(struct udevice *dev,
+  struct scmi_msg *msg)
+{
+   struct scmi_protocol_version_out *out = NULL;
+
+   if (!msg->out_msg || msg->out_msg_sz < sizeof(*out))
+   return -EINVAL;
+
+   out = (struct scmi_protocol_version_out *)msg->out_msg;
+   out->version = 0x3;
+   out->status = SCMI_SUCCESS;
+
+   return 0;
+}
+
 static int sandbox_scmi_clock_protocol_attribs(struct udevice *dev,
   struct scmi_msg *msg)
 {
@@ -740,6 +755,9 @@ static int sandbox_scmi_clock_attribs(struct udevice *dev, 
struct scmi_msg *msg)
if (clk_state->enabled)
out->attributes = 1;
 
+   /* Restricted clock */
+   out->attributes |= BIT(1);
+
ret = snprintf(out->clock_name, sizeof(out->clock_name),
   "clk%u", in->clock_id);
assert(ret > 0 && ret < sizeof(out->clock_name));
@@ -837,6 +855,34 @@ static int sandbox_scmi_clock_gate(struct udevice *dev, 
struct scmi_msg *msg)
return 0;
 }
 
+static int sandbox_scmi_clock_permissions_get(struct udevice *dev,
+ struct scmi_msg *msg)
+{
+   struct scmi_clk_get_permissions_in *in = NULL;
+   struct scmi_clk_get_permissions_out *out = NULL;
+   struct sandbox_scmi_clk *clk_state = NULL;
+
+   if (!msg->in_msg || msg->in_msg_sz < sizeof(*in) ||
+   !msg->out_msg || msg->out_msg_sz < sizeof(*out))
+   return -EINVAL;
+
+   in = (struct scmi_clk_get_permissions_in *)msg->in_msg;
+   out = (struct scmi_clk_get_permissions_out *)msg->out_msg;
+
+   clk_state = get_scmi_clk_state(in->clock_id);
+   if (!clk_state) {
+   dev_err(dev, "Unexpected clock ID %u\n", in->clock_id);
+
+   out->status = SCMI_NOT_FOUND;
+   } else {
+   out->permissions = clk_state->perm;
+
+   out->status = SCMI_SUCCESS;
+   }
+
+   return 0;
+}
+
 static int sandbox_scmi_rd_attribs(struct udevice *dev, struct scmi_msg *msg)
 {
struct scmi_rd_attr_in *in = NULL;
@@ -1193,6 +1239,8 @@ static int sandbox_scmi_test_process_msg(struct udevice 
*dev,
return sandbox_proto_not_supported(msg);
 
switch (msg->message_id) {
+   case SCMI_PROTOCOL_VERSION:
+   return sandbox_scmi_clock_protocol_version(dev, msg);
case SCMI_PROTOCOL_ATTRIBUTES:
return sandbox_scmi_clock_protocol_attribs(dev, msg);
case SCMI_CLOCK_ATTRIBUTES:
@@ -1203,6 +1251,8 @@ static int sandbox_scmi_test_process_msg(struct udevice 
*dev,
return sandbox_scmi_clock_rate_get(dev, msg);
case SCMI_CLOCK_CONFIG_SET:
return sandbox_scmi_clock_gate(dev, msg);
+   case SCMI_CLOCK_GET_PERMISSIONS:
+   return sandbox_scmi_clock_permissions_get(dev, msg);
default:
break;
}
-- 
2.43.0

[PATCH v6 06/20] scmi_protocols: add SCMI Performance domain management protocol message IDs

2025-02-28 Thread Alice Guo (OSS)

From: Peng Fan 

SCMI Performance domain management protocol is intended for performance
management of groups of devices or APs that run in the same performance
domain. The functionality provided by the callee-side can be used by
passing the corresponding message_id.

Signed-off-by: Peng Fan 
Signed-off-by: Alice Guo 
Reviewed-by: Ye Li 
---
 include/scmi_protocols.h | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/include/scmi_protocols.h b/include/scmi_protocols.h
index 06de4a601f..34f272c448 100644
--- a/include/scmi_protocols.h
+++ b/include/scmi_protocols.h
@@ -1046,4 +1046,22 @@ struct scmi_pinctrl_config_set_out {
s32 status;
 };
 
+/* SCMI Perf Protocol */
+enum scmi_perf_message_id {
+   SCMI_PERF_DOMAIN_ATTRIBUTES = 0x3,
+   SCMI_PERF_DESCRIBE_LEVELS = 0x4,
+   SCMI_PERF_LIMITS_SET = 0x5,
+   SCMI_PERF_LIMITS_GET = 0x6,
+   SCMI_PERF_LEVEL_SET = 0x7,
+   SCMI_PERF_LEVEL_GET = 0x8
+};
+
+struct scmi_perf_in {
+   u32 domain_id;
+   u32 perf_level;
+};
+
+struct scmi_perf_out {
+   s32 status;
+};
 #endif /* _SCMI_PROTOCOLS_H */

-- 
2.43.0

[PATCH v6 08/20] clk: scmi: check the clock state/parent/rate control permissions

2025-02-28 Thread Alice Guo (OSS)

From: Alice Guo 

Clock driver based on SCMI clock management protocol in Linux checks
clock state, parent and rate control permissions. To be consistent with
the kernel driver, add this check here.

When using common clock framework (CCF), use the clock signal ID to get
the clock registered by clk_register() in scmi_clk_probe(), and then
obatin the struct clk_scmi variable with container_of().

Signed-off-by: Alice Guo 
Signed-off-by: Ye Li 
Reviewed-by: Peng Fan 
---
 drivers/clk/clk_scmi.c   | 172 ---
 include/scmi_protocols.h |  26 ++-
 2 files changed, 187 insertions(+), 11 deletions(-)

diff --git a/drivers/clk/clk_scmi.c b/drivers/clk/clk_scmi.c
index 84333cdd0c..4fce92d064 100644
--- a/drivers/clk/clk_scmi.c
+++ b/drivers/clk/clk_scmi.c
@@ -12,6 +12,56 @@
 #include 
 #include 
 
+struct clk_scmi {
+   struct clk clk;
+   u32 ctrl_flags;
+};
+
+static int scmi_clk_get_permissions(struct udevice *dev, int clkid, u32 *perm)
+{
+   u32 version;
+   int ret;
+
+   ret = scmi_generic_protocol_version(dev, SCMI_PROTOCOL_ID_CLOCK, 
&version);
+   if (ret) {
+   debug("get SCMI clock management protocol version failed\n");
+   return ret;
+   }
+
+   if (version < CLOCK_PROTOCOL_VERSION_3_0) {
+   debug("SCMI clock management protocol version is less than 
3.0.\n");
+   return -EINVAL;
+   }
+
+   struct scmi_clk_get_permissions_in in = {
+   .clock_id = clkid,
+   };
+   struct scmi_clk_get_permissions_out out;
+   struct scmi_msg msg = {
+   .protocol_id = SCMI_PROTOCOL_ID_CLOCK,
+   .message_id = SCMI_CLOCK_GET_PERMISSIONS,
+   .in_msg = (u8 *)&in,
+   .in_msg_sz = sizeof(in),
+   .out_msg = (u8 *)&out,
+   .out_msg_sz = sizeof(out),
+   };
+
+   ret = devm_scmi_process_msg(dev, &msg);
+   if (ret) {
+   debug("get SCMI clock management protocol permissions 
failed\n");
+   return ret;
+   }
+
+   ret = scmi_to_linux_errno(out.status);
+   if (ret < 0) {
+   debug("the status code of getting permissions: %d\n", ret);
+   return ret;
+   }
+
+   *perm = out.permissions;
+   return 0;
+}
+
 static int scmi_clk_get_num_clock(struct udevice *dev, size_t *num_clocks)
 {
struct scmi_clk_protocol_attr_out out;
@@ -32,7 +82,8 @@ static int scmi_clk_get_num_clock(struct udevice *dev, size_t 
*num_clocks)
return 0;
 }
 
-static int scmi_clk_get_attibute(struct udevice *dev, int clkid, char **name)
+static int scmi_clk_get_attibute(struct udevice *dev, int clkid, char **name,
+u32 *attr)
 {
struct scmi_clk_attribute_in in = {
.clock_id = clkid,
@@ -53,6 +104,7 @@ static int scmi_clk_get_attibute(struct udevice *dev, int 
clkid, char **name)
return ret;
 
*name = strdup(out.clock_name);
+   *attr = out.attributes;
 
return 0;
 }
@@ -78,11 +130,49 @@ static int scmi_clk_gate(struct clk *clk, int enable)
 
 static int scmi_clk_enable(struct clk *clk)
 {
+   struct clk_scmi *clkscmi;
+   struct clk *c;
+   int ret;
+
+   if (CONFIG_IS_ENABLED(CLK_CCF)) {
+   ret = clk_get_by_id(clk->id, &c);
+   if (ret)
+   return ret;
+
+   clkscmi = container_of(c, struct clk_scmi, clk);
+
+   if (clkscmi->ctrl_flags & SUPPORT_CLK_STAT_CONTROL)
+   return scmi_clk_gate(clk, 1);
+
+   /* Following Linux drivers/clk/clk-scmi.c, directly return 0 if 
agent has no permission. */
+   debug("SCMI CLOCK: the clock cannot be enabled by the 
agent.\n");
+   return 0;
+   }
+
return scmi_clk_gate(clk, 1);
 }
 
 static int scmi_clk_disable(struct clk *clk)
 {
+   struct clk_scmi *clkscmi;
+   struct clk *c;
+   int ret;
+
+   if (CONFIG_IS_ENABLED(CLK_CCF)) {
+   ret = clk_get_by_id(clk->id, &c);
+   if (ret)
+   return ret;
+
+   clkscmi = container_of(c, struct clk_scmi, clk);
+
+   if (clkscmi->ctrl_flags & SUPPORT_CLK_STAT_CONTROL)
+   return scmi_clk_gate(clk, 0);
+
+   /* Following Linux drivers/clk/clk-scmi.c, directly return 0 if 
agent has no permission. */
+   debug("SCMI CLOCK: the clock cannot be disabled by the 
agent.\n");
+   return 0;
+   }
+
return scmi_clk_gate(clk, 0);
 }
 
@@ -108,7 +198,7 @@ static ulong scmi_clk_get_rate(struct clk *clk)
return (ulong)(((u64)out.rate_msb << 32) | out.rate_lsb);
 }
 
-static ulong scmi_clk_set_rate(struct clk *clk, ulong rate)
+static ulong __scmi_clk_set_rate(struct clk *clk, ulong rate)
 {
struct scmi_clk_rate_set_in in = {
.clock_id = clk->i

[PATCH v6 01/20] mailbox: add i.MX Messaging Unit (MU) driver

2025-02-28 Thread Alice Guo (OSS)

From: Peng Fan 

This patch provides a driver for i.MX Messaging Unit (MU) using the
commom mailbox framework.

This is ported from Linux (v6.12.8) driver
drivers/mailbox/imx-mailbox.c. Its commit SHA is:
39d7d6177f0c ("mailbox: imx: use device name in interrupt name")

Signed-off-by: Viorel Suman 
Signed-off-by: Peng Fan 
Signed-off-by: Alice Guo 
Reviewed-by: Ye Li 
---
 MAINTAINERS   |   1 +
 drivers/mailbox/Kconfig   |   7 +
 drivers/mailbox/Makefile  |   1 +
 drivers/mailbox/imx-mailbox.c | 430 ++
 4 files changed, 439 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 687262b355..f13629bc87 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -315,6 +315,7 @@ F:  board/freescale/*mx*/
 F: board/freescale/common/
 F: common/spl/spl_imx_container.c
 F: doc/imx/
+F: drivers/mailbox/imx-mailbox.c
 F: drivers/serial/serial_mxc.c
 F: include/imx_container.h
 
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index 67d5ac1a74..4d9f004eba 100644
--- a/drivers/mailbox/Kconfig
+++ b/drivers/mailbox/Kconfig
@@ -21,6 +21,13 @@ config APPLE_MBOX
  such as the System Management Controller (SMC) and NVMe and this
  driver is required to get that functionality up and running.
 
+config IMX_MU_MBOX
+   bool "Enable i.MX MU MBOX support"
+   depends on DM_MAILBOX
+   help
+ Enable support for i.MX Messaging Unit for communication with other
+ processors on the SoC using mailbox interface
+
 config SANDBOX_MBOX
bool "Enable the sandbox mailbox test driver"
depends on DM_MAILBOX && SANDBOX
diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
index 6072fa1956..574add6000 100644
--- a/drivers/mailbox/Makefile
+++ b/drivers/mailbox/Makefile
@@ -5,6 +5,7 @@
 
 obj-$(CONFIG_$(XPL_)DM_MAILBOX) += mailbox-uclass.o
 obj-$(CONFIG_APPLE_MBOX) += apple-mbox.o
+obj-$(CONFIG_IMX_MU_MBOX) += imx-mailbox.o
 obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox.o
 obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox-test.o
 obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o
diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c
new file mode 100644
index 00..a33356ea7b
--- /dev/null
+++ b/drivers/mailbox/imx-mailbox.c
@@ -0,0 +1,430 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 NXP
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* This driver only exposes the status bits to keep with the
+ * polling methodology of u-boot.
+ */
+DECLARE_GLOBAL_DATA_PTR;
+
+#define IMX_MU_CHANS   24
+
+#define IMX_MU_V2_PAR_OFF  0x4
+#define IMX_MU_V2_TR_MASK  GENMASK(7, 0)
+#define IMX_MU_V2_RR_MASK  GENMASK(15, 8)
+
+enum imx_mu_chan_type {
+   IMX_MU_TYPE_TX  = 0, /* Tx */
+   IMX_MU_TYPE_RX  = 1, /* Rx */
+   IMX_MU_TYPE_TXDB= 2, /* Tx doorbell */
+   IMX_MU_TYPE_RXDB= 3, /* Rx doorbell */
+   IMX_MU_TYPE_RST = 4, /* Reset */
+   IMX_MU_TYPE_TXDB_V2 = 5, /* Tx doorbell with S/W ACK */
+};
+
+enum imx_mu_xcr {
+   IMX_MU_CR,
+   IMX_MU_GIER,
+   IMX_MU_GCR,
+   IMX_MU_TCR,
+   IMX_MU_RCR,
+   IMX_MU_xCR_MAX,
+};
+
+enum imx_mu_xsr {
+   IMX_MU_SR,
+   IMX_MU_GSR,
+   IMX_MU_TSR,
+   IMX_MU_RSR,
+   IMX_MU_xSR_MAX,
+};
+
+struct imx_mu_con_priv {
+   unsigned intidx;
+   enum imx_mu_chan_type   type;
+   struct mbox_chan*chan;
+};
+
+enum imx_mu_type {
+   IMX_MU_V1,
+   IMX_MU_V2 = BIT(1),
+   IMX_MU_V2_S4 = BIT(15),
+   IMX_MU_V2_IRQ = BIT(16),
+};
+
+struct imx_mu {
+   void __iomem *base;
+   const struct imx_mu_dcfg *dcfg;
+   u32 num_tr;
+   u32 num_rr;
+   /* use pointers to channel as a way to reserve channels */
+   struct mbox_chan *channels[IMX_MU_CHANS];
+   struct imx_mu_con_priv  con_priv[IMX_MU_CHANS];
+};
+
+struct imx_mu_dcfg {
+   int (*tx)(struct imx_mu *plat, struct imx_mu_con_priv *cp, const void 
*data);
+   int (*rx)(struct imx_mu *plat, struct imx_mu_con_priv *cp);
+   int (*rxdb)(struct imx_mu *plat, struct imx_mu_con_priv *cp);
+   int (*init)(struct imx_mu *plat);
+   int (*of_xlate)(struct mbox_chan *chan, struct ofnode_phandle_args 
*args);
+   enum imx_mu_type type;
+   u32 xTR;/* Transmit Register0 */
+   u32 xRR;/* Receive Register0 */
+   u32 xSR[IMX_MU_xSR_MAX];/* Status Registers */
+   u32 xCR[IMX_MU_xCR_MAX];/* Control Registers */
+};
+
+#define IMX_MU_xSR_GIPn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - 
(x
+#define IMX_MU_xSR_RFn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - 
(x
+#define IMX_MU_xSR_TEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - 
(x
+
+/* General Purpose Interrupt Enable */
+#define IMX_MU_xCR_GIEn(type, x) (type & IMX_M

[PATCH v6 00/20] imx: add i.MX95 support

2025-02-28 Thread Alice Guo (OSS)

Changes in v6:
- add BOOTSTD
- add an explanation in the commit log that i.MX specific protoc6:
- remove unused code from etype nxp_header_ddrfw to make code coverage
  100%

Signed-off-by: Alice Guo 
---
Alice Guo (9):
  pinctrl: nxp: add a pin controller driver based on SCMI pin control 
protocol
  firmware: scmi: add pin control protocol support to SCMI agent
  clk: scmi: check the clock state/parent/rate control permissions
  sandbox: add SCMI clock control permissions to sandbox
  imx: Kconfig: IMX8_ROMAPI is not configured for i.MX95
  binman: add a new entry type for packing DDR PHY firmware images
  tools: imx8image: add i.MX95 support
  doc: imx: add document for i.MX95 Image Container Format
  Makefile: add some files to CLEAN_FILES

Peng Fan (5):
  mailbox: add i.MX Messaging Unit (MU) driver
  scmi_protocols: add SCMI misc protocol protocol_id and message_id for 
getting the ROM passover data
  scmi_protocols: add SCMI Performance domain management protocol message 
IDs
  clk: scmi: add the command CLOCK_PARENT_SET
  imx9: scmi: add i.MX95 SoC and clock related code

Teo Hall (1):
  imx: add V2X container support on i.MX95

Viorel Suman (1):
  firmware: scmi: smt: Interrupt communication enable

Ye Li (4):
  scmi_protocols: update struct scmi_base_discover_list_protocols_out
  spl: imx: use trampoline buffer to load images to secure region
  imx9: add i.MX95 Kconfig and Makefile
  imx95_evk: add i.MX95 19x19 EVK board basic support

 MAINTAINERS   |   1 +
 Makefile  |   3 +-
 arch/arm/dts/imx95-19x19-evk-u-boot.dtsi  |  62 ++
 arch/arm/dts/imx95-u-boot.dtsi| 157 +
 arch/arm/include/asm/arch-imx/cpu.h   |   2 +
 arch/arm/include/asm/arch-imx9/clock.h|  10 +
 arch/arm/include/asm/arch-imx9/imx-regs.h |   5 +
 arch/arm/include/asm/arch-imx9/sys_proto.h|   1 +
 arch/arm/include/asm/mach-imx/sys_proto.h |  39 ++
 arch/arm/mach-imx/Kconfig |   2 +-
 arch/arm/mach-imx/image-container.c   |  63 +-
 arch/arm/mach-imx/imx9/Kconfig|  16 +
 arch/arm/mach-imx/imx9/Makefile   |   9 +-
 arch/arm/mach-imx/imx9/scmi/Makefile  |   6 +
 arch/arm/mach-imx/imx9/scmi/clock.c   | 105 
 arch/arm/mach-imx/imx9/scmi/clock_scmi.c  | 133 +
 arch/arm/mach-imx/imx9/scmi/container.cfg |  10 +
 arch/arm/mach-imx/imx9/scmi/imximage.cfg  |  15 +
 arch/arm/mach-imx/imx9/scmi/soc.c | 806 ++
 arch/sandbox/include/asm/scmi_test.h  |   4 +-
 board/freescale/imx95_evk/Kconfig |  12 +
 board/freescale/imx95_evk/MAINTAINERS |   6 +
 board/freescale/imx95_evk/Makefile|  11 +
 board/freescale/imx95_evk/imx95_19x19_evk.env |  91 +++
 board/freescale/imx95_evk/imx95_evk.c |  36 ++
 board/freescale/imx95_evk/spl.c   |  72 +++
 common/spl/Kconfig|   6 +
 common/spl/spl_imx_container.c|  41 +-
 configs/imx95_19x19_evk_defconfig | 152 +
 doc/board/nxp/imx95_evk.rst   | 114 
 doc/board/nxp/index.rst   |   1 +
 doc/imx/imx95_container.txt   | 136 +
 drivers/clk/clk_scmi.c| 190 +-
 drivers/firmware/scmi/Kconfig |   6 +
 drivers/firmware/scmi/sandbox-scmi_agent.c|  56 +-
 drivers/firmware/scmi/scmi_agent-uclass.c |  11 +
 drivers/firmware/scmi/smt.c   |  13 +
 drivers/mailbox/Kconfig   |   7 +
 drivers/mailbox/Makefile  |   1 +
 drivers/mailbox/imx-mailbox.c | 430 ++
 drivers/pinctrl/nxp/Kconfig   |  13 +
 drivers/pinctrl/nxp/Makefile  |   1 +
 drivers/pinctrl/nxp/pinctrl-scmi.c| 143 +
 include/configs/imx95_evk.h   |  24 +
 include/imx8image.h   |  19 +-
 include/scmi_agent-uclass.h   |   2 +
 include/scmi_protocols.h  | 107 +++-
 tools/binman/entries.rst  |  10 +
 tools/binman/etype/nxp_header_ddrfw.py|  29 +
 tools/binman/ftest.py |  11 +
 tools/binman/test/346_nxp_ddrfw_imx95.dts |  24 +
 tools/imx8image.c | 143 -
 tools/imx9_image.sh   |   8 +
 53 files changed, 3311 insertions(+), 64 deletions(-)
---
base-commit: 8dd7186ca7821446c6f46b6cccefab502912f2e0
change-id: 20250227-imx95-21a30f5b1994

Best regards,
-- 
Alice Guo

[PATCH v6 03/20] pinctrl: nxp: add a pin controller driver based on SCMI pin control protocol

2025-02-28 Thread Alice Guo (OSS)

From: Alice Guo 

This patch provides a pinctrl driver based on SCMI pin control protocol.
Currently, only the PINCTRL_CONFIG_SET command is implemented.

Signed-off-by: Ranjani Vaidyanathan 
Signed-off-by: Peng Fan 
Signed-off-by: Alice Guo 
Reviewed-by: Ye Li 
---
 drivers/pinctrl/nxp/Kconfig|  13 
 drivers/pinctrl/nxp/Makefile   |   1 +
 drivers/pinctrl/nxp/pinctrl-scmi.c | 143 +
 include/scmi_protocols.h   |  36 ++
 4 files changed, 193 insertions(+)

diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig
index d13c5f2a6d..84d9a3641f 100644
--- a/drivers/pinctrl/nxp/Kconfig
+++ b/drivers/pinctrl/nxp/Kconfig
@@ -139,6 +139,19 @@ config PINCTRL_IMXRT
  only parses the 'fsl,pins' property and configure related
  registers.
 
+config PINCTRL_IMX_SCMI
+   bool "IMX pinctrl SCMI driver"
+   depends on ARCH_IMX9 && PINCTRL_FULL
+   select PINCTRL_IMX
+   help
+ This provides a simple pinctrl driver for i.MX SoC which supports
+ SCMI. This feature depends on device tree configuration. This driver
+ is different from the linux one, this is a simple implementation,
+ only parses the 'fsl,pins' property and configure related
+ registers.
+
+ Say Y here to enable the imx pinctrl SCMI driver
+
 config PINCTRL_VYBRID
bool "Vybrid (vf610) pinctrl driver"
depends on ARCH_VF610 && PINCTRL_FULL
diff --git a/drivers/pinctrl/nxp/Makefile b/drivers/pinctrl/nxp/Makefile
index 44e37c631e..9ef675d18c 100644
--- a/drivers/pinctrl/nxp/Makefile
+++ b/drivers/pinctrl/nxp/Makefile
@@ -11,3 +11,4 @@ obj-$(CONFIG_PINCTRL_IMX93)   += pinctrl-imx93.o
 obj-$(CONFIG_PINCTRL_MXS)  += pinctrl-mxs.o
 obj-$(CONFIG_PINCTRL_VYBRID)   += pinctrl-vf610.o
 obj-$(CONFIG_PINCTRL_IMXRT)+= pinctrl-imxrt.o
+obj-$(CONFIG_PINCTRL_IMX_SCMI) += pinctrl-scmi.o
diff --git a/drivers/pinctrl/nxp/pinctrl-scmi.c 
b/drivers/pinctrl/nxp/pinctrl-scmi.c
new file mode 100644
index 00..4a791b7e95
--- /dev/null
+++ b/drivers/pinctrl/nxp/pinctrl-scmi.c
@@ -0,0 +1,143 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 NXP
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "pinctrl-imx.h"
+
+#define DAISY_OFFSET_IMX93 0x360
+#define DAISY_OFFSET_IMX95 0x408
+
+/* SCMI pin control types */
+#define PINCTRL_TYPE_MUX192
+#define PINCTRL_TYPE_CONFIG 193
+#define PINCTRL_TYPE_DAISY_ID   194
+#define PINCTRL_TYPE_DAISY_CFG  195
+#define PINCTRL_NUM_CFGS_SHIFT  2
+
+struct imx_scmi_pinctrl_priv {
+   u16 daisy_offset;
+};
+
+static int imx_pinconf_scmi_set(struct udevice *dev, u32 mux_ofs, u32 mux, u32 
config_val,
+   u32 input_ofs, u32 input_val)
+{
+   struct imx_scmi_pinctrl_priv *priv = dev_get_priv(dev);
+   int ret, num_cfgs = 0;
+   struct scmi_msg msg;
+
+   /* Call SCMI API to set the pin mux and configuration. */
+   struct scmi_pinctrl_config_set_out out;
+   struct scmi_pinctrl_config_set_in in = {
+   .identifier = mux_ofs / 4,
+   .function_id = 0x,
+   .attributes = 0,
+   };
+
+   if (mux_ofs != 0) {
+   in.configs[num_cfgs].type = PINCTRL_TYPE_MUX;
+   in.configs[num_cfgs].val = mux;
+   num_cfgs++;
+   }
+
+   if (config_val != 0) {
+   in.configs[num_cfgs].type = PINCTRL_TYPE_CONFIG;
+   in.configs[num_cfgs].val = config_val;
+   num_cfgs++;
+   }
+
+   if (input_ofs != 0) {
+   in.configs[num_cfgs].type = PINCTRL_TYPE_DAISY_ID;
+   in.configs[num_cfgs].val = (input_ofs -  priv->daisy_offset) / 
4;
+   num_cfgs++;
+   in.configs[num_cfgs].type = PINCTRL_TYPE_DAISY_CFG;
+   in.configs[num_cfgs].val = input_val;
+   num_cfgs++;
+   }
+
+   /* Update the number of configs sent in this call. */
+   in.attributes = num_cfgs << PINCTRL_NUM_CFGS_SHIFT;
+
+   msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_PINCTRL,
+ SCMI_MSG_PINCTRL_CONFIG_SET, in, out);
+
+   ret = devm_scmi_process_msg(dev, &msg);
+   if (ret || out.status != 0) {
+   dev_err(dev, "Failed to set PAD = %d, daisy = %d, scmi_err = 
%d, ret = %d\n",
+   mux_ofs / 4, input_ofs / 4, out.status, ret);
+   }
+
+   return ret;
+}
+
+static int imx_pinctrl_set_state_scmi(struct udevice *dev, struct udevice 
*config)
+{
+   int mux_ofs, mux, config_val, input_reg, input_val;
+   u32 *pin_data;
+   int i, j = 0;
+   int npins;
+   int ret;
+
+   ret = imx_pinctrl_set_state_common(dev, config, FSL_PIN_SIZE,
+  &pin_data, &npins);
+   if (ret)
+   return ret;
+
+   /*
+

[PATCH v6 07/20] clk: scmi: add the command CLOCK_PARENT_SET

2025-02-28 Thread Alice Guo (OSS)

From: Peng Fan 

This patch adds the command CLOCK_PARENT_SET that can be used to set the
parent of a clock. ARM SCMI Version 3.2 supports to change the parent of
a clock device.

Signed-off-by: Peng Fan 
Signed-off-by: Alice Guo 
Reviewed-by: Ye Li 
---
 drivers/clk/clk_scmi.c   | 20 
 include/scmi_protocols.h | 19 +++
 2 files changed, 39 insertions(+)

diff --git a/drivers/clk/clk_scmi.c b/drivers/clk/clk_scmi.c
index e42d2032d4..84333cdd0c 100644
--- a/drivers/clk/clk_scmi.c
+++ b/drivers/clk/clk_scmi.c
@@ -178,11 +178,31 @@ static int scmi_clk_probe(struct udevice *dev)
return 0;
 }
 
+static int scmi_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+   struct scmi_clk_parent_set_in in = {
+   .clock_id = clk->id,
+   .parent_clk = parent->id,
+   };
+   struct scmi_clk_parent_set_out out;
+   struct scmi_msg msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_CLOCK,
+ SCMI_CLOCK_PARENT_SET,
+ in, out);
+   int ret;
+
+   ret = devm_scmi_process_msg(clk->dev, &msg);
+   if (ret < 0)
+   return ret;
+
+   return scmi_to_linux_errno(out.status);
+}
+
 static const struct clk_ops scmi_clk_ops = {
.enable = scmi_clk_enable,
.disable = scmi_clk_disable,
.get_rate = scmi_clk_get_rate,
.set_rate = scmi_clk_set_rate,
+   .set_parent = scmi_clk_set_parent,
 };
 
 U_BOOT_DRIVER(scmi_clock) = {
diff --git a/include/scmi_protocols.h b/include/scmi_protocols.h
index 34f272c448..0d8c177025 100644
--- a/include/scmi_protocols.h
+++ b/include/scmi_protocols.h
@@ -737,6 +737,7 @@ enum scmi_clock_message_id {
SCMI_CLOCK_RATE_SET = 0x5,
SCMI_CLOCK_RATE_GET = 0x6,
SCMI_CLOCK_CONFIG_SET = 0x7,
+   SCMI_CLOCK_PARENT_SET = 0xD
 };
 
 #define SCMI_CLK_PROTO_ATTR_COUNT_MASK GENMASK(15, 0)
@@ -839,6 +840,24 @@ struct scmi_clk_rate_set_out {
s32 status;
 };
 
+/**
+ * struct scmi_clk_parent_state_in - Message payload for CLOCK_PARENT_SET 
command
+ * @clock_id:  SCMI clock ID
+ * @parent_clk:SCMI clock ID
+ */
+struct scmi_clk_parent_set_in {
+   u32 clock_id;
+   u32 parent_clk;
+};
+
+/**
+ * struct scmi_clk_parent_set_out - Response payload for CLOCK_PARENT_SET 
command
+ * @status:SCMI command status
+ */
+struct scmi_clk_parent_set_out {
+   s32 status;
+};
+
 /*
  * SCMI Reset Domain Protocol
  */

-- 
2.43.0

[PATCH v6 05/20] scmi_protocols: add SCMI misc protocol protocol_id and message_id for getting the ROM passover data

2025-02-28 Thread Alice Guo (OSS)

From: Peng Fan 

SCMI misc protocol is intended for miscellaneous functions which are
device specific and are usually defined to access bit fields. It is i.MX
specific. This patch adds SCMI misc protocol protocol_id and message_id
for getting the ROM passover data.

Signed-off-by: Peng Fan 
Signed-off-by: Alice Guo 
Reviewed-by: Ye Li 
---
 include/scmi_protocols.h | 5 +
 1 file changed, 5 insertions(+)

diff --git a/include/scmi_protocols.h b/include/scmi_protocols.h
index 279ebbad44..06de4a601f 100644
--- a/include/scmi_protocols.h
+++ b/include/scmi_protocols.h
@@ -25,6 +25,7 @@ enum scmi_std_protocol {
SCMI_PROTOCOL_ID_RESET_DOMAIN = 0x16,
SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN = 0x17,
SCMI_PROTOCOL_ID_PINCTRL = 0x19,
+   SCMI_PROTOCOL_ID_IMX_MISC = 0x84,
 };
 
 enum scmi_status_code {
@@ -50,6 +51,10 @@ enum scmi_discovery_id {
SCMI_PROTOCOL_MESSAGE_ATTRIBUTES = 0x2,
 };
 
+enum scmi_imx_misc_message_id {
+   SCMI_MISC_ROM_PASSOVER_GET = 0x7
+};
+
 /*
  * SCMI Base Protocol
  */

-- 
2.43.0

[PATCH v6 04/20] firmware: scmi: add pin control protocol support to SCMI agent

2025-02-28 Thread Alice Guo (OSS)

From: Alice Guo 

This patch adds SCMI pin control protocol support so that the pin
controller driver based on SCMI, such as
drivers/pinctrl/nxp/pinctrl-scmi.c, can be bound to the SCMI agent
device whose protocol id is 0x19.

Signed-off-by: Alice Guo 
---
 drivers/firmware/scmi/scmi_agent-uclass.c | 11 +++
 include/scmi_agent-uclass.h   |  2 ++
 2 files changed, 13 insertions(+)

diff --git a/drivers/firmware/scmi/scmi_agent-uclass.c 
b/drivers/firmware/scmi/scmi_agent-uclass.c
index 8c907c3b03..5f101f4ede 100644
--- a/drivers/firmware/scmi/scmi_agent-uclass.c
+++ b/drivers/firmware/scmi/scmi_agent-uclass.c
@@ -97,6 +97,9 @@ struct udevice *scmi_get_protocol(struct udevice *dev,
case SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN:
proto = priv->voltagedom_dev;
break;
+   case SCMI_PROTOCOL_ID_PINCTRL:
+   proto = priv->pinctrl_dev;
+   break;
default:
dev_err(dev, "Protocol not supported\n");
proto = NULL;
@@ -147,6 +150,9 @@ static int scmi_add_protocol(struct udevice *dev,
case SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN:
priv->voltagedom_dev = proto;
break;
+   case SCMI_PROTOCOL_ID_PINCTRL:
+   priv->pinctrl_dev = proto;
+   break;
default:
dev_err(dev, "Protocol not supported\n");
return -EPROTO;
@@ -436,6 +442,11 @@ static int scmi_bind_protocols(struct udevice *dev)
drv = DM_DRIVER_GET(scmi_voltage_domain);
}
break;
+   case SCMI_PROTOCOL_ID_PINCTRL:
+   if (IS_ENABLED(CONFIG_PINCTRL_IMX_SCMI) &&
+   scmi_protocol_is_supported(dev, protocol_id))
+   drv = DM_DRIVER_GET(scmi_pinctrl_imx);
+   break;
default:
break;
}
diff --git a/include/scmi_agent-uclass.h b/include/scmi_agent-uclass.h
index 33e0e18c30..4beec43cb0 100644
--- a/include/scmi_agent-uclass.h
+++ b/include/scmi_agent-uclass.h
@@ -27,6 +27,7 @@ struct scmi_channel;
  * @clock_dev: SCMI clock protocol device
  * @resetdom_dev:  SCMI reset domain protocol device
  * @voltagedom_dev:SCMI voltage domain protocol device
+ * @pinctrl_dev:   SCMI pin control protocol device
  */
 struct scmi_agent_priv {
u32 version;
@@ -43,6 +44,7 @@ struct scmi_agent_priv {
struct udevice *clock_dev;
struct udevice *resetdom_dev;
struct udevice *voltagedom_dev;
+   struct udevice *pinctrl_dev;
 };
 
 static inline u32 scmi_version(struct udevice *dev)

-- 
2.43.0

[PATCH v6 02/20] firmware: scmi: smt: Interrupt communication enable

2025-02-28 Thread Alice Guo (OSS)

From: Viorel Suman 

i.MX95 System Manager uses interrupt driven communication which requires
the caller to set Bit[0] of channel flags to 1. When transmission
completes and the previous general purpose interrupt has been processed
by the other core, i.MX95 System Manager will set General Purpose
Interrupt Control Register (GCR). U-Boot polls General-purpose Status
(GSR) to check if the operation is finished.

Signed-off-by: Viorel Suman 
Signed-off-by: Alice Guo 
Reviewed-by: Ye Li 
---
 drivers/firmware/scmi/Kconfig |  6 ++
 drivers/firmware/scmi/smt.c   | 13 +
 2 files changed, 19 insertions(+)

diff --git a/drivers/firmware/scmi/Kconfig b/drivers/firmware/scmi/Kconfig
index 8cf85f0d7a..eb62b88615 100644
--- a/drivers/firmware/scmi/Kconfig
+++ b/drivers/firmware/scmi/Kconfig
@@ -41,3 +41,9 @@ config SCMI_AGENT_OPTEE
help
  Enable the SCMI communication channel based on OP-TEE transport
  for compatible "linaro,scmi-optee".
+
+config SCMI_TRANSPORT_SMT_INTR
+   bool
+   depends on SCMI_FIRMWARE
+   help
+ Enable interrupt communication of shared memory based transport.
diff --git a/drivers/firmware/scmi/smt.c b/drivers/firmware/scmi/smt.c
index 67d2f45002..a0489f9718 100644
--- a/drivers/firmware/scmi/smt.c
+++ b/drivers/firmware/scmi/smt.c
@@ -20,6 +20,16 @@
 
 #include "smt.h"
 
+static void scmi_smt_enable_intr(struct scmi_smt *smt, bool enable)
+{
+   struct scmi_smt_header *hdr = (void *)smt->buf;
+
+   if (enable)
+   hdr->flags |= SCMI_SHMEM_FLAG_INTR_ENABLED;
+   else
+   hdr->flags &= ~SCMI_SHMEM_FLAG_INTR_ENABLED;
+}
+
 /**
  * Get shared memory configuration defined by the referred DT phandle
  * Return with a errno compliant value.
@@ -48,6 +58,9 @@ int scmi_dt_get_smt_buffer(struct udevice *dev, struct 
scmi_smt *smt)
if (!smt->buf)
return -ENOMEM;
 
+   if (IS_ENABLED(CONFIG_SCMI_TRANSPORT_SMT_INTR))
+   scmi_smt_enable_intr(smt, true);
+
 #ifdef CONFIG_ARM
if (dcache_status())
mmu_set_region_dcache_behaviour(ALIGN_DOWN((uintptr_t)smt->buf, 
MMU_SECTION_SIZE),

-- 
2.43.0

[PATCH v6 10/20] scmi_protocols: update struct scmi_base_discover_list_protocols_out

2025-02-28 Thread Alice Guo (OSS)

From: Ye Li 

@protocols is an array of protocol identifiers that are implemented,
excluding the Base protocol. The number of elements of @protocols is
specified by callee-side. Currently, set it to 4 is enough for i.MX95.

Signed-off-by: Ye Li 
Signed-off-by: Alice Guo 
---
 include/scmi_protocols.h | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/include/scmi_protocols.h b/include/scmi_protocols.h
index 2684f4177d..7ce73ddfae 100644
--- a/include/scmi_protocols.h
+++ b/include/scmi_protocols.h
@@ -141,11 +141,14 @@ struct scmi_base_discover_impl_version_out {
  * @status:SCMI command status
  * @num_protocols: Number of SCMI protocols in @protocol
  * @protocols: Array of packed SCMI protocol ID's
+ *
+ * The number of elements of @protocols is specified by callee-side. Currently,
+ * set it to 4 is enough for i.MX95.
  */
 struct scmi_base_discover_list_protocols_out {
s32 status;
u32 num_protocols;
-   u32 protocols[3];
+   u32 protocols[4];
 };
 
 /**

-- 
2.43.0

[PATCH v6 11/20] imx9: scmi: add i.MX95 SoC and clock related code

2025-02-28 Thread Alice Guo (OSS)

From: Peng Fan 

This patch adds i.MX95 SoC and clock related code. Because they are
based on SCMI, put them in the scmi subfolder.

Signed-off-by: Ye Li 
Signed-off-by: Peng Fan 
Signed-off-by: Alice Guo 
Reviewed-by: Peng Fan 
---
 arch/arm/include/asm/arch-imx/cpu.h|   2 +
 arch/arm/include/asm/arch-imx9/clock.h |  10 +
 arch/arm/include/asm/arch-imx9/imx-regs.h  |   5 +
 arch/arm/include/asm/arch-imx9/sys_proto.h |   1 +
 arch/arm/include/asm/mach-imx/sys_proto.h  |  39 ++
 arch/arm/mach-imx/imx9/scmi/Makefile   |   6 +
 arch/arm/mach-imx/imx9/scmi/clock.c| 105 
 arch/arm/mach-imx/imx9/scmi/clock_scmi.c   | 133 +
 arch/arm/mach-imx/imx9/scmi/soc.c  | 788 +
 arch/sandbox/include/asm/scmi_test.h   |   2 +-
 10 files changed, 1090 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-imx/cpu.h 
b/arch/arm/include/asm/arch-imx/cpu.h
index 0d7a573461..1f669c72d0 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -76,6 +76,8 @@
 #define MXC_CPU_IMX91110xCD /* dummy ID */
 #define MXC_CPU_IMX91010xCE /* dummy ID */
 
+#define MXC_CPU_IMX95  0x1C1 /* dummy ID */
+
 #define MXC_SOC_MX60x60
 #define MXC_SOC_MX70x70
 #define MXC_SOC_IMX8M  0x80
diff --git a/arch/arm/include/asm/arch-imx9/clock.h 
b/arch/arm/include/asm/arch-imx9/clock.h
index 60d48b13b1..ffaf6b5f7d 100644
--- a/arch/arm/include/asm/arch-imx9/clock.h
+++ b/arch/arm/include/asm/arch-imx9/clock.h
@@ -255,5 +255,15 @@ int ccm_shared_gpr_tz_access(u32 gpr, bool non_secure, 
bool user_mode, bool lock
 void enable_usboh3_clk(unsigned char enable);
 int set_clk_enet(enum enet_freq type);
 int set_clk_eqos(enum enet_freq type);
+
+int imx_clk_scmi_enable(u32 clock_id, bool enable);
+ulong imx_clk_scmi_set_rate(u32 clock_id, ulong rate);
+ulong imx_clk_scmi_get_rate(u32 clock_id);
+int imx_clk_scmi_set_parent(u32 clock_id, u32 parent_id);
 void set_arm_clk(ulong freq);
+
+int imx_clk_scmi_enable(u32 clock_id, bool enable);
+ulong imx_clk_scmi_set_rate(u32 clock_id, ulong rate);
+ulong imx_clk_scmi_get_rate(u32 clock_id);
+int imx_clk_scmi_set_parent(u32 clock_id, u32 parent_id);
 #endif
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h 
b/arch/arm/include/asm/arch-imx9/imx-regs.h
index ef9538bd42..f7f9c706e1 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -20,6 +20,11 @@
 #define WDG4_BASE_ADDR  0x424aUL
 #define WDG5_BASE_ADDR  0x424bUL
 
+#define GPIO2_BASE_ADDR0x4381UL
+#define GPIO3_BASE_ADDR0x4382UL
+#define GPIO4_BASE_ADDR0x4384UL
+#define GPIO5_BASE_ADDR0x4385UL
+
 #define FSB_BASE_ADDR   0x4751UL
 
 #define ANATOP_BASE_ADDR0x4448UL
diff --git a/arch/arm/include/asm/arch-imx9/sys_proto.h 
b/arch/arm/include/asm/arch-imx9/sys_proto.h
index e4bf6a6342..df2148a53c 100644
--- a/arch/arm/include/asm/arch-imx9/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx9/sys_proto.h
@@ -12,6 +12,7 @@ enum imx9_soc_voltage_mode {
VOLT_LOW_DRIVE = 0,
VOLT_NOMINAL_DRIVE,
VOLT_OVER_DRIVE,
+   VOLT_SUPER_OVER_DRIVE,
 };
 
 void soc_power_init(void);
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h 
b/arch/arm/include/asm/mach-imx/sys_proto.h
index 109a806852..0780f99b49 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -97,6 +97,8 @@ struct bd_info;
 #define is_imx9302() (is_cpu_type(MXC_CPU_IMX9302))
 #define is_imx9301() (is_cpu_type(MXC_CPU_IMX9301))
 
+#define is_imx95() (is_cpu_type(MXC_CPU_IMX95))
+
 #define is_imx9121() (is_cpu_type(MXC_CPU_IMX9121))
 #define is_imx9111() (is_cpu_type(MXC_CPU_IMX9111))
 #define is_imx9101() (is_cpu_type(MXC_CPU_IMX9101))
@@ -216,6 +218,43 @@ ulong spl_romapi_get_uboot_base(u32 image_offset, u32 
rom_bt_dev);
 u32 rom_api_download_image(u8 *dest, u32 offset, u32 size);
 u32 rom_api_query_boot_infor(u32 info_type, u32 *info);
 
+#if IS_ENABLED(CONFIG_SCMI_FIRMWARE)
+typedef struct rom_passover {
+   u16 tag;   // Tag
+   u8  len;   // Fixed value of 0x80
+   u8  ver;   // Version
+   u32 boot_mode; // Boot mode
+   u32 card_addr_mode;// SD card address mode
+   u32 bad_blks_of_img_set0;  // NAND bad block count skipped 1
+   u32 ap_mu_id;  // AP MU ID
+   u32 bad_blks_of_img_set1;  // NAND bad block count skipped 1
+   u8  boot_stage;// Boot stage
+   u8  img_set_sel;   // Image set booted from
+   u8  rsv0[2];   // Reserved
+   u32 img_set_end;   // Offset of Image End
+   u32 rom_version;   // ROM version
+   u8  boot_dev_state;// Boot device state
+   u8  boot_dev_inst; // Boot device type

[PATCH v6 12/20] spl: imx: use trampoline buffer to load images to secure region

2025-02-28 Thread Alice Guo (OSS)

From: Ye Li 

When SPL loading image to secure region, for example, ATF and tee to
DDR secure region. Because the USDHC controller is non-secure master,
it can't access this region and will cause loading issue.

So use a trampoline buffer in non-secure region, then use CPU to copy the
image from trampoline buffer to destination secure region.

Signed-off-by: Ye Li 
Signed-off-by: Alice Guo 
Reviewed-by: Peng Fan 
---
 arch/arm/mach-imx/imx9/scmi/soc.c | 18 +
 common/spl/Kconfig|  6 ++
 common/spl/spl_imx_container.c| 41 +--
 3 files changed, 59 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-imx/imx9/scmi/soc.c 
b/arch/arm/mach-imx/imx9/scmi/soc.c
index 217e7ed41a..1bacf52657 100644
--- a/arch/arm/mach-imx/imx9/scmi/soc.c
+++ b/arch/arm/mach-imx/imx9/scmi/soc.c
@@ -786,3 +786,21 @@ enum boot_device get_boot_device(void)
return boot_dev;
 }
 #endif
+
+bool arch_check_dst_in_secure(void *start, ulong size)
+{
+   ulong ns_end = CFG_SYS_SDRAM_BASE + PHYS_SDRAM_SIZE;
+#ifdef PHYS_SDRAM_2_SIZE
+   ns_end += PHYS_SDRAM_2_SIZE;
+#endif
+
+   if ((ulong)start < CFG_SYS_SDRAM_BASE || (ulong)start + size > ns_end)
+   return true;
+
+   return false;
+}
+
+void *arch_get_container_trampoline(void)
+{
+   return (void *)((ulong)CFG_SYS_SDRAM_BASE + PHYS_SDRAM_SIZE - SZ_16M);
+}
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 7d6780936d..29bc119bb2 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -362,6 +362,12 @@ config SPL_LOAD_IMX_CONTAINER
  Support booting U-Boot from an i.MX8 container image. If you are not
  using i.MX8, say 'n'.
 
+config SPL_IMX_CONTAINER_USE_TRAMPOLINE
+   bool
+   depends on SPL
+   help
+ Enable SPL load reader to load data to a trampoline buffer.
+
 config IMX_CONTAINER_CFG
string "i.MX8 Container config file"
depends on SPL && SPL_LOAD_IMX_CONTAINER
diff --git a/common/spl/spl_imx_container.c b/common/spl/spl_imx_container.c
index 2c31777fcd..47fb2e65e3 100644
--- a/common/spl/spl_imx_container.c
+++ b/common/spl/spl_imx_container.c
@@ -14,6 +14,16 @@
 #include 
 #endif
 
+__weak bool arch_check_dst_in_secure(void *start, ulong size)
+{
+   return false;
+}
+
+__weak void *arch_get_container_trampoline(void)
+{
+   return NULL;
+}
+
 static struct boot_img_t *read_auth_image(struct spl_image_info *spl_image,
  struct spl_load_info *info,
  struct container_hdr *container,
@@ -22,6 +32,7 @@ static struct boot_img_t *read_auth_image(struct 
spl_image_info *spl_image,
 {
struct boot_img_t *images;
ulong offset, overhead, size;
+   void *buf, *trampoline;
 
if (image_index > container->num_images) {
debug("Invalid image number\n");
@@ -42,12 +53,30 @@ static struct boot_img_t *read_auth_image(struct 
spl_image_info *spl_image,
 
debug("%s: container: %p offset: %lu size: %lu\n", __func__,
  container, offset, size);
-   if (info->read(info, offset, size,
-  map_sysmem(images[image_index].dst - overhead,
- images[image_index].size)) <
-   images[image_index].size) {
-   printf("%s wrong\n", __func__);
-   return NULL;
+
+   buf = map_sysmem(images[image_index].dst - overhead, 
images[image_index].size);
+   if (IS_ENABLED(CONFIG_SPL_IMX_CONTAINER_USE_TRAMPOLINE) &&
+   arch_check_dst_in_secure(buf, size)) {
+   trampoline = arch_get_container_trampoline();
+   if (!trampoline) {
+   printf("%s: trampoline size is zero\n", __func__);
+   return NULL;
+   }
+
+   if (info->read(info, offset, size, trampoline) < 
images[image_index].size) {
+   printf("%s wrong\n", __func__);
+   return NULL;
+   }
+
+   memcpy(buf, trampoline, images[image_index].size);
+   } else {
+   if (info->read(info, offset, size,
+  map_sysmem(images[image_index].dst - overhead,
+ images[image_index].size)) <
+   images[image_index].size) {
+   printf("%s wrong\n", __func__);
+   return NULL;
+   }
}
 
 #ifdef CONFIG_AHAB_BOOT

-- 
2.43.0

[PATCH v6 14/20] imx: Kconfig: IMX8_ROMAPI is not configured for i.MX95

2025-02-28 Thread Alice Guo (OSS)

From: Alice Guo 

i.MX95 only supports low power boot, which means A55 is kicked by M33.
There is no ROM runs on A55 in such case so that deselect IMX8_ROMAPI
for i.MX95.

Signed-off-by: Alice Guo 
---
 arch/arm/mach-imx/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 134e42028c..f38f3b2d33 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -180,7 +180,7 @@ config DDRMC_VF610_CALIBRATION
 
 config IMX8_ROMAPI
def_bool y
-   depends on IMX8MN || IMX8MP || IMX8ULP || IMX9
+   depends on IMX8MN || IMX8MP || IMX8ULP || IMX93 || IMX91
 
 config SPL_IMX_ROMAPI_LOADADDR
hex "Default load address to load image through ROM API"

-- 
2.43.0

[PATCH v6 13/20] imx9: add i.MX95 Kconfig and Makefile

2025-02-28 Thread Alice Guo (OSS)

From: Ye Li 

This patch adds i.MX95 Kconfig and Makefile. i.MX95 uses SCMI.

Signed-off-by: Ye Li 
Signed-off-by: Alice Guo 
Reviewed-by: Peng Fan 
---
 arch/arm/mach-imx/imx9/Kconfig  | 8 
 arch/arm/mach-imx/imx9/Makefile | 9 +++--
 2 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig
index 49220c0955..ef364ca1a2 100644
--- a/arch/arm/mach-imx/imx9/Kconfig
+++ b/arch/arm/mach-imx/imx9/Kconfig
@@ -21,6 +21,14 @@ config IMX91
select IMX9
select ARMV8_SPL_EXCEPTION_VECTORS
 
+config IMX95
+   bool
+   select ARMV8_SPL_EXCEPTION_VECTORS
+   select IMX9
+   select DM_MAILBOX
+   select SCMI_FIRMWARE
+   select SCMI_TRANSPORT_SMT_INTR
+   select SPL_IMX_CONTAINER_USE_TRAMPOLINE
 
 config SYS_SOC
default "imx9"
diff --git a/arch/arm/mach-imx/imx9/Makefile b/arch/arm/mach-imx/imx9/Makefile
index 45a9105a75..53cc97c6b4 100644
--- a/arch/arm/mach-imx/imx9/Makefile
+++ b/arch/arm/mach-imx/imx9/Makefile
@@ -3,8 +3,13 @@
 # Copyright 2022 NXP
 
 obj-y += lowlevel_init.o
+
+ifeq ($(CONFIG_SCMI_FIRMWARE),y)
+obj-y += scmi/
+else
 obj-y += soc.o clock.o clock_root.o trdc.o
+endif
 
-#ifndef CONFIG_XPL_BUILD
+ifneq ($(CONFIG_SPL_BUILD),y)
 obj-y += imx_bootaux.o
-#endif
+endif
\ No newline at end of file

-- 
2.43.0

[PATCH v6 19/20] imx95_evk: add i.MX95 19x19 EVK board basic support

2025-02-28 Thread Alice Guo (OSS)

From: Ye Li 

This patch adds i.MX95 19x19 EVK board basic support.

Messaging unit for EdgeLock Secure Enclave, messaging unit for System
Manager, uSDHC for SD Card, gpio, lpuart are supported now.

Signed-off-by: Ye Li 
Signed-off-by: Alice Guo 
Reviewed-by: Peng Fan 
---
 arch/arm/dts/imx95-19x19-evk-u-boot.dtsi  |  62 ++
 arch/arm/dts/imx95-u-boot.dtsi| 157 ++
 arch/arm/mach-imx/imx9/Kconfig|   8 ++
 arch/arm/mach-imx/imx9/scmi/container.cfg |  10 ++
 arch/arm/mach-imx/imx9/scmi/imximage.cfg  |  15 +++
 board/freescale/imx95_evk/Kconfig |  12 ++
 board/freescale/imx95_evk/MAINTAINERS |   6 +
 board/freescale/imx95_evk/Makefile|  11 ++
 board/freescale/imx95_evk/imx95_19x19_evk.env |  91 +++
 board/freescale/imx95_evk/imx95_evk.c |  36 ++
 board/freescale/imx95_evk/spl.c   |  72 
 configs/imx95_19x19_evk_defconfig | 152 +
 doc/board/nxp/imx95_evk.rst   | 114 +++
 doc/board/nxp/index.rst   |   1 +
 include/configs/imx95_evk.h   |  24 
 15 files changed, 771 insertions(+)

diff --git a/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi 
b/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi
new file mode 100644
index 00..2d1f02baa5
--- /dev/null
+++ b/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 NXP
+ */
+
+#include "imx95-u-boot.dtsi"
+
+&lpuart1 {
+   bootph-pre-ram;
+};
+
+®_usdhc2_vmmc {
+   bootph-pre-ram;
+};
+
+&usdhc1 {
+   bootph-pre-ram;
+};
+
+&usdhc2 {
+   bootph-pre-ram;
+};
+
+&wdog3 {
+   status = "disabled";
+};
+
+&pinctrl_uart1 {
+   bootph-pre-ram;
+};
+
+&pinctrl_usdhc1 {
+   bootph-pre-ram;
+};
+
+&pinctrl_usdhc1_100mhz {
+   bootph-pre-ram;
+};
+
+&pinctrl_usdhc1_200mhz {
+   bootph-pre-ram;
+};
+
+&pinctrl_usdhc2 {
+   bootph-pre-ram;
+};
+
+&pinctrl_usdhc2_100mhz {
+   bootph-pre-ram;
+};
+
+&pinctrl_usdhc2_200mhz {
+   bootph-pre-ram;
+};
+
+&pinctrl_usdhc2_gpio {
+   bootph-pre-ram;
+};
+
+&pinctrl_reg_usdhc2_vmmc {
+   bootph-pre-ram;
+};
diff --git a/arch/arm/dts/imx95-u-boot.dtsi b/arch/arm/dts/imx95-u-boot.dtsi
new file mode 100644
index 00..b0dcf765a7
--- /dev/null
+++ b/arch/arm/dts/imx95-u-boot.dtsi
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 NXP
+ */
+
+/ {
+   binman {
+   multiple-images;
+
+   m33-oei-ddrfw {
+   pad-byte = <0x00>;
+   align-size = <0x8>;
+   filename = "m33-oei-ddrfw.bin";
+
+   oei-m33-ddr {
+   align-size = <0x4>;
+   filename = "oei-m33-ddr.bin";
+   type = "blob-ext";
+   };
+
+   imx-lpddr {
+   type = "nxp-header-ddrfw";
+
+   imx-lpddr-imem {
+   filename = "lpddr5_imem_v202311.bin";
+   type = "blob-ext";
+   };
+
+   imx-lpddr-dmem {
+   filename = "lpddr5_dmem_v202311.bin";
+   type = "blob-ext";
+   };
+   };
+
+   imx-lpddr-qb {
+   type = "nxp-header-ddrfw";
+
+   imx-lpddr-imem-qb {
+   filename = "lpddr5_imem_qb_v202311.bin";
+   type = "blob-ext";
+   };
+
+   imx-lpddr-dmem-qb {
+   filename = "lpddr5_dmem_qb_v202311.bin";
+   type = "blob-ext";
+   };
+   };
+   };
+
+   imx-boot {
+   filename = "flash.bin";
+   pad-byte = <0x00>;
+
+   spl {
+   align = <0x400>;
+   align-size = <0x400>;
+   type = "mkimage";
+   args = "-n spl/u-boot-spl.cfgout -T imx8image";
+   };
+
+   u-boot {
+   type = "mkimage";
+   args = "-n u-boot-container.cfgout -T 
imx8image";
+   };
+   };
+   };
+};
+
+&aips1 {
+   bootph-all;
+};
+
+&aips2 {
+   bootph-all;
+};
+
+&aips3 {
+   bootph-pre-ram;
+};
+
+&clk_ext1 {
+   bootph-all;
+};
+
+&elemu3 {
+   c

[PATCH v6 15/20] binman: add a new entry type for packing DDR PHY firmware images

2025-02-28 Thread Alice Guo (OSS)

From: Alice Guo 

i.MX95 needs to combine DDR PHY firmware images and their byte counts
together, so add a new entry type nxp-header-ddrfw for this requirement.

Signed-off-by: Alice Guo 
---
 tools/binman/entries.rst  | 10 ++
 tools/binman/etype/nxp_header_ddrfw.py| 29 +
 tools/binman/ftest.py | 11 +++
 tools/binman/test/346_nxp_ddrfw_imx95.dts | 24 
 4 files changed, 74 insertions(+)

diff --git a/tools/binman/entries.rst b/tools/binman/entries.rst
index 780e9817fb..6da3f0b904 100644
--- a/tools/binman/entries.rst
+++ b/tools/binman/entries.rst
@@ -1663,6 +1663,16 @@ Properties / Entry arguments:
 
 
 
+.. _etype_nxp_header_ddrfw:
+
+Entry: nxp-header-ddrfw: add a header to DDR PHY firmware images
+---
+
+This entry is used to combine DDR PHY firmware images and their byte counts
+together. See imx95_evk.rst for how to get DDR PHY Firmware Images.
+
+
+
 .. _etype_opensbi:
 
 Entry: opensbi: RISC-V OpenSBI fw_dynamic blob
diff --git a/tools/binman/etype/nxp_header_ddrfw.py 
b/tools/binman/etype/nxp_header_ddrfw.py
new file mode 100644
index 00..655699e6ff
--- /dev/null
+++ b/tools/binman/etype/nxp_header_ddrfw.py
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2025 NXP
+
+from binman.etype.section import Entry_section
+
+class Entry_nxp_header_ddrfw(Entry_section):
+"""Add a header to DDR PHY firmware images
+
+This entry is used for i.MX95 to combine DDR PHY firmware images and their
+byte counts together.
+
+See imx95_evk.rst for how to get DDR PHY Firmware Images.
+"""
+
+def __init__(self, section, etype, node):
+super().__init__(section, etype, node)
+
+def BuildSectionData(self, required):
+section_data = bytearray()
+header_data = bytearray()
+
+for entry in self._entries.values():
+entry_data = entry.GetData(required)
+
+section_data += entry_data
+header_data += entry.contents_size.to_bytes(4, 'little')
+
+return header_data + section_data
diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py
index d2802f67e2..811f6514eb 100644
--- a/tools/binman/ftest.py
+++ b/tools/binman/ftest.py
@@ -104,6 +104,8 @@ PRE_LOAD_VERSION  = 0x11223344.to_bytes(4, 'big')
 PRE_LOAD_HDR_SIZE = 0x1000.to_bytes(4, 'big')
 TI_BOARD_CONFIG_DATA  = 
b'\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00'
 TI_UNSECURE_DATA  = b'unsecuredata'
+IMX_LPDDR_IMEM_DATA   = b'qwertyuiop1234567890'
+IMX_LPDDR_DMEM_DATA   = b'asdfghjklzxcvbnm'
 
 # Subdirectory of the input dir to use to put test FDTs
 TEST_FDT_SUBDIR   = 'fdts'
@@ -202,6 +204,8 @@ class TestFunctional(unittest.TestCase):
 TestFunctional._MakeInputFile('fsp_m.bin', FSP_M_DATA)
 TestFunctional._MakeInputFile('fsp_s.bin', FSP_S_DATA)
 TestFunctional._MakeInputFile('fsp_t.bin', FSP_T_DATA)
+TestFunctional._MakeInputFile('lpddr5_imem.bin', IMX_LPDDR_IMEM_DATA)
+TestFunctional._MakeInputFile('lpddr5_dmem.bin', IMX_LPDDR_DMEM_DATA)
 
 cls._elf_testdir = os.path.join(cls._indir, 'elftest')
 elf_test.BuildElfTestFiles(cls._elf_testdir)
@@ -7827,6 +7831,13 @@ fdt fdtmapExtract the devicetree 
blob from the fdtmap
 """Test that binman can produce an iMX8 image"""
 self._DoTestFile('339_nxp_imx8.dts')
 
+def testNxpHeaderDdrfw(self):
+"""Test that binman can add a header to DDR PHY firmware images"""
+data = self._DoReadFile('346_nxp_ddrfw_imx95.dts')
+self.assertEqual(len(IMX_LPDDR_IMEM_DATA).to_bytes(4, 'little') +
+ len(IMX_LPDDR_DMEM_DATA).to_bytes(4, 'little') +
+ IMX_LPDDR_IMEM_DATA + IMX_LPDDR_DMEM_DATA, data)
+
 def testFitSignSimple(self):
 """Test that image with FIT and signature nodes can be signed"""
 if not elf.ELF_TOOLS:
diff --git a/tools/binman/test/346_nxp_ddrfw_imx95.dts 
b/tools/binman/test/346_nxp_ddrfw_imx95.dts
new file mode 100644
index 00..889f6f2986
--- /dev/null
+++ b/tools/binman/test/346_nxp_ddrfw_imx95.dts
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   binman {
+   imx-lpddr {
+   type = "nxp-header-ddrfw";
+
+   imx-lpddr-imem {
+   filename = "lpddr5_imem.bin";
+   type = "blob-ext";
+   };
+
+   imx-lpddr-dmem {
+   filename = "lpddr5_dmem.bin";
+   type = "blob-ext";
+   };
+   };
+   };
+};

-- 
2.43.0

[PATCH v6 16/20] tools: imx8image: add i.MX95 support

2025-02-28 Thread Alice Guo (OSS)

From: Alice Guo 

i.MX95 uses binman to invoke mkimage to create image container. 2 image
containers are needed currently. The first one is composed of
ahab-container.img, LPDDR firmware images, OEI images, System Manager
image and u-boot-spl.bin. The second one is consisted of ARM Trusted
firmware and u-boot.bin.

Because DDR OEI image and LPDDR firmware images have to be packaged
together and named as m33-oei-ddrfw.bin by binman, so imx9_image.sh does
not check if m33-oei-ddrfw.bin exists.

When using "make imx95_19x19_evk_defconfig; make", imx9_image.sh will
delete the line for u-boot.bin in container.cfg. In fact, binman is
always called after the u-boot.bin is built, so imx9_image.sh does not
check if u-boot.bin exists.

Signed-off-by: Alice Guo 
---
 include/imx8image.h |  19 +--
 tools/imx8image.c   | 143 +++-
 tools/imx9_image.sh |   8 +++
 3 files changed, 153 insertions(+), 17 deletions(-)

diff --git a/include/imx8image.h b/include/imx8image.h
index 6b95e93fb5..b48e2b0396 100644
--- a/include/imx8image.h
+++ b/include/imx8image.h
@@ -157,7 +157,9 @@ enum imx8image_cmd {
CMD_SOC_TYPE,
CMD_CONTAINER,
CMD_IMAGE,
-   CMD_DATA
+   CMD_DATA,
+   CMD_DUMMY_V2X,
+   CMD_HOLD
 };
 
 enum imx8image_core_type {
@@ -169,7 +171,9 @@ enum imx8image_core_type {
CFG_A35,
CFG_A55,
CFG_A53,
-   CFG_A72
+   CFG_A72,
+   CFG_M33,
+   CFG_OEI
 };
 
 enum imx8image_fld_types {
@@ -208,7 +212,10 @@ typedef enum option_type {
FILEOFF,
MSG_BLOCK,
SENTINEL,
-   UPOWER
+   UPOWER,
+   OEI,
+   DUMMY_V2X,
+   HOLD
 } option_type_t;
 
 typedef struct {
@@ -227,12 +234,16 @@ typedef struct {
 #define CORE_CA35   4
 #define CORE_CA72   5
 #define CORE_SECO   6
+#define CORE_M337
 
 #define CORE_ULP_CM33  0x1
 #define CORE_ULP_CA35  0x2
 #define CORE_ULP_UPOWER0x4
 #define CORE_ULP_SENTINEL  0x6
 
+#define CORE_IMX95_M33P0
+#define CORE_IMX95_A55C0   2
+
 #define SC_R_OTP   357U
 #define SC_R_DEBUG 354U
 #define SC_R_ROM_0 236U
@@ -246,10 +257,12 @@ typedef struct {
 #define IMG_TYPE_EXEC0x03   /* Executable image type */
 #define IMG_TYPE_DATA0x04   /* Data image type */
 #define IMG_TYPE_DCD_DDR 0x05   /* DCD/DDR image type */
+#define IMG_TYPE_OEI 0x05   /* Optional Executable image type */
 #define IMG_TYPE_SECO0x06   /* SECO image type */
 #define IMG_TYPE_SENTINEL 0x06 /* SENTINEL image type */
 #define IMG_TYPE_PROV0x07   /* Provisioning image type */
 #define IMG_TYPE_DEK 0x08   /* DEK validation type */
+#define IMG_TYPE_V2X_DUMMY 0x0E /* V2X Dummy image */
 
 #define IMG_TYPE_SHIFT   0
 #define IMG_TYPE_MASK0x1f
diff --git a/tools/imx8image.c b/tools/imx8image.c
index 15510d3e71..9c4b431745 100644
--- a/tools/imx8image.c
+++ b/tools/imx8image.c
@@ -7,6 +7,7 @@
 
 #include "imx8image.h"
 #include 
+#include 
 
 static int p_idx;
 static int sector_size;
@@ -54,6 +55,8 @@ static table_entry_t imx8image_cmds[] = {
{CMD_CONTAINER, "CONTAINER","new container",  },
{CMD_IMAGE, "IMAGE","new image",  },
{CMD_DATA,  "DATA", "new data",   },
+   {CMD_DUMMY_V2X, "DUMMY_V2X","v2x",},
+   {CMD_HOLD,  "HOLD", "hold",   },
{-1,"", "",   },
 };
 
@@ -66,6 +69,8 @@ static table_entry_t imx8image_core_entries[] = {
{CFG_A55,   "A55",  "A55 core", },
{CFG_A53,   "A53",  "A53 core", },
{CFG_A72,   "A72",  "A72 core", },
+   {CFG_OEI,   "OEI",  "OEI", },
+   {CFG_M33,   "M33",  "M33 core", },
{-1,"", "", },
 };
 
@@ -144,6 +149,14 @@ static void parse_cfg_cmd(image_t *param_stack, int32_t 
cmd, char *token,
exit(EXIT_FAILURE);
}
break;
+   case CMD_DUMMY_V2X:
+   param_stack[p_idx].option = DUMMY_V2X;
+   param_stack[p_idx++].entry = (uint32_t)strtoll(token, NULL, 0);
+   break;
+   case CMD_HOLD:
+   param_stack[p_idx].option = HOLD;
+   param_stack[p_idx].entry = (uint32_t)strtoll(token, NULL, 0);
+   param_stack[p_idx++].filename = NULL;
default:
break;
}
@@ -221,6 +234,16 @@ static void parse_cfg_fld(image_t *param_stack, int32_t 
*cmd, char *token,
(*cmd == CMD_DATA) ? DATA : AP;
param_stack[p_idx].filename = token;
break;
+   case CFG_OEI:
+

[PATCH v6 17/20] imx: add V2X container support on i.MX95

2025-02-28 Thread Alice Guo (OSS)

From: Teo Hall 

This patch adds V2X container support on i.MX95.

Signed-off-by: Ye Li 
Signed-off-by: Teo Hall 
Signed-off-by: Alice Guo 
---
 arch/arm/mach-imx/image-container.c | 63 +++--
 1 file changed, 40 insertions(+), 23 deletions(-)

diff --git a/arch/arm/mach-imx/image-container.c 
b/arch/arm/mach-imx/image-container.c
index 2afe9d38a0..54ae772188 100644
--- a/arch/arm/mach-imx/image-container.c
+++ b/arch/arm/mach-imx/image-container.c
@@ -231,45 +231,62 @@ static unsigned long get_boot_device_offset(void *dev, 
int dev_type)
return offset;
 }
 
-static int get_imageset_end(void *dev, int dev_type)
+static ulong get_imageset_end(void *dev, int dev_type)
 {
-   unsigned long offset1 = 0, offset2 = 0;
-   int value_container[2];
+   unsigned long offset[3] = {};
+   int value_container[3] = {};
u16 hdr_length;
 
-   offset1 = get_boot_device_offset(dev, dev_type);
-   offset2 = CONTAINER_HDR_ALIGNMENT + offset1;
+   offset[0] = get_boot_device_offset(dev, dev_type);
 
-   value_container[0] = get_dev_container_size(dev, dev_type, offset1, 
&hdr_length);
+   value_container[0] = get_dev_container_size(dev, dev_type, offset[0], 
&hdr_length);
if (value_container[0] < 0) {
printf("Parse seco container failed %d\n", value_container[0]);
-   return value_container[0];
+   return 0;
}
 
debug("seco container size 0x%x\n", value_container[0]);
 
-   value_container[1] = get_dev_container_size(dev, dev_type, offset2, 
&hdr_length);
-   if (value_container[1] < 0) {
-   debug("Parse scu container failed %d, only seco container\n",
- value_container[1]);
-   /* return seco container total size */
-   return value_container[0] + offset1;
+   if (is_imx95()) {
+   offset[1] = ALIGN(hdr_length, CONTAINER_HDR_ALIGNMENT) + 
offset[0];
+
+   value_container[1] = get_dev_container_size(dev, dev_type, 
offset[1], &hdr_length);
+   if (value_container[1] < 0) {
+   printf("Parse v2x container failed %d\n", 
value_container[1]);
+   return value_container[0] + offset[0]; /* return seco 
container total size */
+   }
+
+   debug("v2x container size 0x%x\n", value_container[1]);
+
+   offset[2] = ALIGN(hdr_length, CONTAINER_HDR_ALIGNMENT) + 
offset[1];
+   } else {
+   /* Skip offset[1] */
+   offset[2] = ALIGN(hdr_length, CONTAINER_HDR_ALIGNMENT) + 
offset[0];
}
 
-   debug("scu container size 0x%x\n", value_container[1]);
+   value_container[2] = get_dev_container_size(dev, dev_type, offset[2], 
&hdr_length);
+   if (value_container[2] < 0) {
+   debug("Parse scu container image failed %d, only seco 
container\n", value_container[2]);
+   if (is_imx95())
+   return value_container[1] + offset[1]; /* return seco + 
v2x container total size */
+   else
+   return value_container[0] + offset[0]; /* return seco 
container total size */
+   }
 
-   return value_container[1] + offset2;
+   debug("scu container size 0x%x\n", value_container[2]);
+
+   return value_container[2] + offset[2];
 }
 
 #ifdef CONFIG_SPL_SPI_LOAD
 unsigned int spl_spi_get_uboot_offs(struct spi_flash *flash)
 {
-   int end;
+   ulong end;
 
end = get_imageset_end(flash, QSPI_DEV);
end = ROUND(end, SZ_1K);
 
-   printf("Load image from QSPI 0x%x\n", end);
+   printf("Load image from QSPI 0x%lx\n", end);
 
return end;
 }
@@ -279,12 +296,12 @@ unsigned int spl_spi_get_uboot_offs(struct spi_flash 
*flash)
 unsigned long arch_spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
unsigned long raw_sect)
 {
-   int end;
+   ulong end;
 
end = get_imageset_end(mmc, MMC_DEV);
end = ROUND(end, SZ_1K);
 
-   printf("Load image from MMC/SD 0x%x\n", end);
+   printf("Load image from MMC/SD 0x%lx\n", end);
 
return end / mmc->read_bl_len;
 }
@@ -312,12 +329,12 @@ int spl_mmc_emmc_boot_partition(struct mmc *mmc)
 #ifdef CONFIG_SPL_NAND_SUPPORT
 uint32_t spl_nand_get_uboot_raw_page(void)
 {
-   int end;
+   ulong end;
 
end = get_imageset_end((void *)NULL, NAND_DEV);
end = ROUND(end, SZ_16K);
 
-   printf("Load image from NAND 0x%x\n", end);
+   printf("Load image from NAND 0x%lx\n", end);
 
return end;
 }
@@ -326,7 +343,7 @@ uint32_t spl_nand_get_uboot_raw_page(void)
 #ifdef CONFIG_SPL_NOR_SUPPORT
 unsigned long spl_nor_get_uboot_base(void)
 {
-   int end;
+   ulong end;
 
/* Calculate the image set end,
 * if it is less than CFG_SYS_UBOOT_BASE(0x8281000),
@@ -339,7 +356,7 @@ unsigned long spl_nor_get_uboot_base(void)

[PATCH v6 18/20] doc: imx: add document for i.MX95 Image Container Format

2025-02-28 Thread Alice Guo (OSS)

From: Alice Guo 

This patch add a document for i.MX95 Image Container Format.

Signed-off-by: Alice Guo 
---
 doc/imx/imx95_container.txt | 136 
 1 file changed, 136 insertions(+)

diff --git a/doc/imx/imx95_container.txt b/doc/imx/imx95_container.txt
new file mode 100644
index 00..2ad5734506
--- /dev/null
+++ b/doc/imx/imx95_container.txt
@@ -0,0 +1,136 @@
+i.MX95 Image Container Format
+-
+
+The image container set consists of some image containers, and image container
+contains boot images. Each image container has its own container header which 
is
+defined in Figure 1. All container headers are placed together in a continuous
+8KB space at the beginning of the image container set - image container set 
header.
+
+ROM code addresses image containers in image container set one by one based on
+their headers’ order in image container set header.
+
+If ELE container exists, its container header must be the 1st one in the image
+container set header.
+
+If V2X container exists, its container header must be the 2nd one in the image
+container set header. V2X must be combined with ELE container.
+
+The information of boot images are recorded in image container header. System
+ROM code needs to retrieve the information from the image container header, 
like
+the offset on boot source, the target address in RAM, the length of boot image.
+The order of ROM code handling these boot images is based on the order of each
+boot image information present in image container header.
+
+Figure 1:
+--- 
+--+--+--+--+
+  ^ |Tag   |Length|Length|Version  
 |
+  | 
+--+--+--+--+
+  | |   Flags  
 |
+  | 
+--+--+--+--+
+  | |# of Images   |Fuse version  |SW version  
 |
+Image | 
+--+--+--+--+
+Conatiner | |Reserved |Signature Block Offset  
 |
+Header| --- 
+--+--+--+--+
+  |   ^ |Image0: Offset, Size, LoadAddr, EntryPoint, Flags, Hash, 
IV|
+  |   | 
+--+--+--+--+
+  | Image | |Image1: Offset, Size, LoadAddr, EntryPoint, Flags, Hash, 
IV|
+  | Array | 
+--+--+--+--+
+  |   | |...   
 |
+  |   | 
+--+--+--+--+
+  v   v |ImageN: Offset, Size, LoadAddr, EntryPoint, Flags, Hash, 
IV|
+--- 
+--+--+--+--+
+|...   
 |
+--- 
+--+--+--+--+ <-- SignOffset
+  ^ |Tag   |Length|Length|Version  
 |
+  | 
+--+--+--+--+
+  | |SRK table offset |Certificate Offset  
 |
+  | 
+--+--+--+--+
+  | |Blob Offset  |Signature Offset
 |
+  | 
+--+--+--+--+
+Signature | | SRK Table
 |
+Block | 
+--+--+--+--+
+  | | Signature
 |
+  | 
+--+--+--+--+
+  | |   Certificate (optional) 
 |
+  | 
+--+--+--+--+
+  v |  Blob (optional) 
 |
+--- 
+--+--+--+--+
+|...   
 |
+
+--+--+--+--+ <-- Image0Offset
+|   Image0 
 |
+
+--+--+--+--+
+|...   
 |
+
+--+--+--+--+ <-- ImageNOffset
+|   ImageN 
 |
+

回复: [PATCH v6 03/20] pinctrl: nxp: add a pin controller driver based on SCMI pin control protocol

2025-03-02 Thread Alice Guo (OSS)

> -邮件原件-
> 发件人: Marek Vasut 
> 发送时间: 2025年3月1日 3:17
> 收件人: Alice Guo (OSS) ; Tom Rini
> ; Stefano Babic ; Fabio Estevam
> ; dl-uboot-imx ; Lukasz
> Majewski ; Sean Anderson ; Simon
> Glass ; Alper Nebi Yasak ;
> Alice Guo 
> 抄送: u-boot@lists.denx.de; Ranjani Vaidyanathan
> ; Peng Fan ; Ye Li
> 
> 主题: Re: [PATCH v6 03/20] pinctrl: nxp: add a pin controller driver based on
> SCMI pin control protocol
> 
> On 2/28/25 11:53 AM, Alice Guo (OSS) wrote:
> > From: Alice Guo 
> >
> > This patch provides a pinctrl driver based on SCMI pin control protocol.
> > Currently, only the PINCTRL_CONFIG_SET command is implemented.
> 
> This can also be a separate patch and go in separately , right ?
> 
> If so, send this as separate patch.
> 
> [...]
> 
> > diff --git a/drivers/pinctrl/nxp/pinctrl-scmi.c
> > b/drivers/pinctrl/nxp/pinctrl-scmi.c
> > new file mode 100644
> > index 00..4a791b7e95
> > --- /dev/null
> > +++ b/drivers/pinctrl/nxp/pinctrl-scmi.c
> > @@ -0,0 +1,143 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2025 NXP
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +#include "pinctrl-imx.h"
> > +
> > +#define DAISY_OFFSET_IMX93 0x360
> > +#define DAISY_OFFSET_IMX95 0x408
> > +
> > +/* SCMI pin control types */
> > +#define PINCTRL_TYPE_MUX192
> > +#define PINCTRL_TYPE_CONFIG 193
> > +#define PINCTRL_TYPE_DAISY_ID   194
> > +#define PINCTRL_TYPE_DAISY_CFG  195
> > +#define PINCTRL_NUM_CFGS_SHIFT  2
> > +
> > +struct imx_scmi_pinctrl_priv {
> > +   u16 daisy_offset;
> > +};
> > +
> > +static int imx_pinconf_scmi_set(struct udevice *dev, u32 mux_ofs, u32 mux,
> u32 config_val,
> > +   u32 input_ofs, u32 input_val)
> > +{
> > +   struct imx_scmi_pinctrl_priv *priv = dev_get_priv(dev);
> > +   int ret, num_cfgs = 0;
> > +   struct scmi_msg msg;
> > +
> > +   /* Call SCMI API to set the pin mux and configuration. */
> > +   struct scmi_pinctrl_config_set_out out;
> > +   struct scmi_pinctrl_config_set_in in = {
> > +   .identifier = mux_ofs / 4,
> > +   .function_id = 0x,
> > +   .attributes = 0,
> > +   };
> > +
> > +   if (mux_ofs != 0) {
> 
> if (mux) { ... } is enough, the !=0 is unnecessary.
> 
> > +   in.configs[num_cfgs].type = PINCTRL_TYPE_MUX;
> > +   in.configs[num_cfgs].val = mux;
> > +   num_cfgs++;
> > +   }
> > +
> > +   if (config_val != 0) {
> 
> DTTO
> 
> > +   in.configs[num_cfgs].type = PINCTRL_TYPE_CONFIG;
> > +   in.configs[num_cfgs].val = config_val;
> > +   num_cfgs++;
> > +   }
> > +
> > +   if (input_ofs != 0) {
> 
> DTTO
> 
> > +   in.configs[num_cfgs].type = PINCTRL_TYPE_DAISY_ID;
> > +   in.configs[num_cfgs].val = (input_ofs -  priv->daisy_offset) / 
> > 4;
> > +   num_cfgs++;
> > +   in.configs[num_cfgs].type = PINCTRL_TYPE_DAISY_CFG;
> > +   in.configs[num_cfgs].val = input_val;
> > +   num_cfgs++;
> > +   }
> > +
> > +   /* Update the number of configs sent in this call. */
> > +   in.attributes = num_cfgs << PINCTRL_NUM_CFGS_SHIFT;
> > +
> > +   msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_PINCTRL,
> > + SCMI_MSG_PINCTRL_CONFIG_SET, in, out);
> > +
> > +   ret = devm_scmi_process_msg(dev, &msg);
> > +   if (ret || out.status != 0) {
> > +   dev_err(dev, "Failed to set PAD = %d, daisy = %d, scmi_err = 
> > %d, ret
> = %d\n",
> > +   mux_ofs / 4, input_ofs / 4, out.status, ret);
> > +   }
> > +
> > +   return ret;
> 
> [...]
> 
> > diff --git a/include/scmi_protocols.h b/include/scmi_protocols.h index
> > 7abb2a6f36..279ebbad44 100644
> > --- a/include/scmi_protocols.h
> > +++ b/include/scmi_protocols.h
> > @@ -24,6 +24,7 @@ enum scmi_std_protocol {
> > SCMI_PROTOCOL_ID_SENSOR = 0x15,
> > SCMI_PROTOCOL_ID_RESET_DOMAIN = 0x16,
> > SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN = 0x17,
> > +   SCMI_PROTOCOL_ID_PINCTRL = 0x19,
> This is the custom iMX specific pinctrl protocol, isn't it ?

Hi Marek,

Protocol id 0x19 is not i.MX specific, and it is defined in Arm® System Control 
and Management Interface Platform Design Document Non-Confidential Version 3.2.

For pin control protocol, drivers/pinctrl/nxp/pinctrl-scmi.c are used on i.MX95.

Best Regards,
Alice Guo

> Can you rename it to some SCMI_PROTOCOL_ID_NXP_IMX9_PINCTRL to make
> it clear this is custom protocol ?

[PATCH v1] mailbox: add i.MX Messaging Unit (MU) driver

2025-03-02 Thread Alice Guo (OSS)

From: Peng Fan 

This patch provides a driver for i.MX Messaging Unit (MU) using the
commom mailbox framework.

This is ported from Linux (v6.12.8) driver
drivers/mailbox/imx-mailbox.c. Its commit SHA is:
39d7d6177f0c ("mailbox: imx: use device name in interrupt name")

Signed-off-by: Viorel Suman 
Signed-off-by: Peng Fan 
Signed-off-by: Alice Guo 
Reviewed-by: Ye Li 
---

Changes for v1:
 - separate this patch from the patch set "add i.MX95 support"
 - add support for i.MX7ULP and i.MX8ULP

 MAINTAINERS   |   1 +
 drivers/mailbox/Kconfig   |   7 +
 drivers/mailbox/Makefile  |   1 +
 drivers/mailbox/imx-mailbox.c | 456 ++
 4 files changed, 465 insertions(+)
 create mode 100644 drivers/mailbox/imx-mailbox.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 687262b355..f13629bc87 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -315,6 +315,7 @@ F:  board/freescale/*mx*/
 F: board/freescale/common/
 F: common/spl/spl_imx_container.c
 F: doc/imx/
+F: drivers/mailbox/imx-mailbox.c
 F: drivers/serial/serial_mxc.c
 F: include/imx_container.h
 
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index 67d5ac1a74..4d9f004eba 100644
--- a/drivers/mailbox/Kconfig
+++ b/drivers/mailbox/Kconfig
@@ -21,6 +21,13 @@ config APPLE_MBOX
  such as the System Management Controller (SMC) and NVMe and this
  driver is required to get that functionality up and running.
 
+config IMX_MU_MBOX
+   bool "Enable i.MX MU MBOX support"
+   depends on DM_MAILBOX
+   help
+ Enable support for i.MX Messaging Unit for communication with other
+ processors on the SoC using mailbox interface
+
 config SANDBOX_MBOX
bool "Enable the sandbox mailbox test driver"
depends on DM_MAILBOX && SANDBOX
diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
index 6072fa1956..574add6000 100644
--- a/drivers/mailbox/Makefile
+++ b/drivers/mailbox/Makefile
@@ -5,6 +5,7 @@
 
 obj-$(CONFIG_$(XPL_)DM_MAILBOX) += mailbox-uclass.o
 obj-$(CONFIG_APPLE_MBOX) += apple-mbox.o
+obj-$(CONFIG_IMX_MU_MBOX) += imx-mailbox.o
 obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox.o
 obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox-test.o
 obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o
diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c
new file mode 100644
index 00..e774cbb1dc
--- /dev/null
+++ b/drivers/mailbox/imx-mailbox.c
@@ -0,0 +1,456 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 NXP
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* This driver only exposes the status bits to keep with the
+ * polling methodology of u-boot.
+ */
+DECLARE_GLOBAL_DATA_PTR;
+
+#define IMX_MU_CHANS   24
+
+#define IMX_MU_V2_PAR_OFF  0x4
+#define IMX_MU_V2_TR_MASK  GENMASK(7, 0)
+#define IMX_MU_V2_RR_MASK  GENMASK(15, 8)
+
+enum imx_mu_chan_type {
+   IMX_MU_TYPE_TX  = 0, /* Tx */
+   IMX_MU_TYPE_RX  = 1, /* Rx */
+   IMX_MU_TYPE_TXDB= 2, /* Tx doorbell */
+   IMX_MU_TYPE_RXDB= 3, /* Rx doorbell */
+   IMX_MU_TYPE_RST = 4, /* Reset */
+   IMX_MU_TYPE_TXDB_V2 = 5, /* Tx doorbell with S/W ACK */
+};
+
+enum imx_mu_xcr {
+   IMX_MU_CR,
+   IMX_MU_GIER,
+   IMX_MU_GCR,
+   IMX_MU_TCR,
+   IMX_MU_RCR,
+   IMX_MU_xCR_MAX,
+};
+
+enum imx_mu_xsr {
+   IMX_MU_SR,
+   IMX_MU_GSR,
+   IMX_MU_TSR,
+   IMX_MU_RSR,
+   IMX_MU_xSR_MAX,
+};
+
+struct imx_mu_con_priv {
+   unsigned intidx;
+   enum imx_mu_chan_type   type;
+   struct mbox_chan*chan;
+};
+
+enum imx_mu_type {
+   IMX_MU_V1,
+   IMX_MU_V2 = BIT(1),
+   IMX_MU_V2_S4 = BIT(15),
+   IMX_MU_V2_IRQ = BIT(16),
+};
+
+struct imx_mu {
+   void __iomem *base;
+   const struct imx_mu_dcfg *dcfg;
+   u32 num_tr;
+   u32 num_rr;
+   /* use pointers to channel as a way to reserve channels */
+   struct mbox_chan *channels[IMX_MU_CHANS];
+   struct imx_mu_con_priv  con_priv[IMX_MU_CHANS];
+};
+
+struct imx_mu_dcfg {
+   int (*tx)(struct imx_mu *plat, struct imx_mu_con_priv *cp, const void 
*data);
+   int (*rx)(struct imx_mu *plat, struct imx_mu_con_priv *cp);
+   int (*rxdb)(struct imx_mu *plat, struct imx_mu_con_priv *cp);
+   int (*init)(struct imx_mu *plat);
+   int (*of_xlate)(struct mbox_chan *chan, struct ofnode_phandle_args 
*args);
+   enum imx_mu_type type;
+   u32 xTR;/* Transmit Register0 */
+   u32 xRR;/* Receive Register0 */
+   u32 xSR[IMX_MU_xSR_MAX];/* Status Registers */
+   u32 xCR[IMX_MU_xCR_MAX];/* Control Registers */
+};
+
+#define IMX_MU_xSR_GIPn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - 
(x
+#define IMX_MU_xSR_RFn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - 
(x
+#define

回复: [PATCH v6 04/20] firmware: scmi: add pin control protocol support to SCMI agent

2025-03-03 Thread Alice Guo (OSS)

> -邮件原件-
> 发件人: Marek Vasut 
> 发送时间: 2025年3月1日 3:18
> 收件人: Alice Guo (OSS) ; Tom Rini
> ; Stefano Babic ; Fabio Estevam
> ; dl-uboot-imx ; Lukasz
> Majewski ; Sean Anderson ; Simon
> Glass ; Alper Nebi Yasak ;
> Alice Guo 
> 抄送: u-boot@lists.denx.de
> 主题: Re: [PATCH v6 04/20] firmware: scmi: add pin control protocol support to
> SCMI agent
> 
> On 2/28/25 11:53 AM, Alice Guo (OSS) wrote:
> > From: Alice Guo 
> >
> > This patch adds SCMI pin control protocol support so that the pin
> > controller driver based on SCMI, such as
> > drivers/pinctrl/nxp/pinctrl-scmi.c, can be bound to the SCMI agent
> > device whose protocol id is 0x19.
> >
> > Signed-off-by: Alice Guo 
> > ---
> >   drivers/firmware/scmi/scmi_agent-uclass.c | 11 +++
> >   include/scmi_agent-uclass.h   |  2 ++
> >   2 files changed, 13 insertions(+)
> >
> > diff --git a/drivers/firmware/scmi/scmi_agent-uclass.c
> > b/drivers/firmware/scmi/scmi_agent-uclass.c
> > index 8c907c3b03..5f101f4ede 100644
> > --- a/drivers/firmware/scmi/scmi_agent-uclass.c
> > +++ b/drivers/firmware/scmi/scmi_agent-uclass.c
> > @@ -97,6 +97,9 @@ struct udevice *scmi_get_protocol(struct udevice *dev,
> > case SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN:
> > proto = priv->voltagedom_dev;
> > break;
> > +   case SCMI_PROTOCOL_ID_PINCTRL:
> > +   proto = priv->pinctrl_dev;
> > +   break;
> > default:
> > dev_err(dev, "Protocol not supported\n");
> > proto = NULL;
> > @@ -147,6 +150,9 @@ static int scmi_add_protocol(struct udevice *dev,
> > case SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN:
> > priv->voltagedom_dev = proto;
> > break;
> > +   case SCMI_PROTOCOL_ID_PINCTRL:
> > +   priv->pinctrl_dev = proto;
> > +   break;
> > default:
> > dev_err(dev, "Protocol not supported\n");
> > return -EPROTO;
> > @@ -436,6 +442,11 @@ static int scmi_bind_protocols(struct udevice *dev)
> > drv = DM_DRIVER_GET(scmi_voltage_domain);
> > }
> > break;
> > +   case SCMI_PROTOCOL_ID_PINCTRL:
> > +   if (IS_ENABLED(CONFIG_PINCTRL_IMX_SCMI) &&
> This really shouldn't be in common code, see my previous comment on V4 .

Move drivers/pinctrl/nxp/pinctrl-scmi.c to drivers/pinctrl/pinctrl-scmi.c. 
Change its name to "scmi_pinctrl". If the generic scmi-pinctrl driver is needed 
in the future, it can be merged with my driver.

Is this OK?

Best Regards,
Alice Guo

回复: [PATCH v6 10/20] scmi_protocols: update struct scmi_base_discover_list_protocols_out

2025-03-03 Thread Alice Guo (OSS)

> -邮件原件-
> 发件人: Marek Vasut 
> 发送时间: 2025年3月1日 3:25
> 收件人: Alice Guo (OSS) ; Tom Rini
> ; Stefano Babic ; Fabio Estevam
> ; dl-uboot-imx ; Lukasz
> Majewski ; Sean Anderson ; Simon
> Glass ; Alper Nebi Yasak ;
> Alice Guo 
> 抄送: u-boot@lists.denx.de; Ye Li 
> 主题: Re: [PATCH v6 10/20] scmi_protocols: update struct
> scmi_base_discover_list_protocols_out
> 
> On 2/28/25 11:54 AM, Alice Guo (OSS) wrote:
> > From: Ye Li 
> >
> > @protocols is an array of protocol identifiers that are implemented,
> > excluding the Base protocol. The number of elements of @protocols is
> > specified by callee-side. Currently, set it to 4 is enough for i.MX95.
> >
> > Signed-off-by: Ye Li 
> > Signed-off-by: Alice Guo 
> > ---
> >   include/scmi_protocols.h | 5 -
> >   1 file changed, 4 insertions(+), 1 deletion(-)
> >
> > diff --git a/include/scmi_protocols.h b/include/scmi_protocols.h index
> > 2684f4177d..7ce73ddfae 100644
> > --- a/include/scmi_protocols.h
> > +++ b/include/scmi_protocols.h
> > @@ -141,11 +141,14 @@ struct scmi_base_discover_impl_version_out {
> >* @status:   SCMI command status
> >* @num_protocols:Number of SCMI protocols in @protocol
> >* @protocols:Array of packed SCMI protocol ID's
> > + *
> > + * The number of elements of @protocols is specified by callee-side.
> > + Currently,
> > + * set it to 4 is enough for i.MX95.
> >*/
> >   struct scmi_base_discover_list_protocols_out {
> > s32 status;
> > u32 num_protocols;
> > -   u32 protocols[3];
> > +   u32 protocols[4];
> 
> Can this be made dynamic ? I think I already asked about this last time, but 
> v4
> feedback was not addressed, can you please double-check that v4 feedback ? I
> will review next version once it is addressed .

Sorry for not replying to your comments for v4. I have just replied in v4 and 
want to discuss this change with you.

回复: [EXT] Re: [PATCH v4 10/20] scmi_protocols: update struct scmi_base_discover_list_protocols_out

2025-03-03 Thread Alice Guo (OSS)

> -邮件原件-
> 发件人: Marek Vasut 
> 发送时间: 2025年1月24日 22:38
> 收件人: Alice Guo (OSS) ; Tom Rini
> ; Stefano Babic ; Fabio Estevam
> ; dl-uboot-imx ; Lukasz
> Majewski ; Sean Anderson ; Simon
> Glass ; Alper Nebi Yasak 
> 抄送: u-boot@lists.denx.de; thar...@gateworks.com; Alice Guo
> ; Ye Li 
> 主题: [EXT] Re: [PATCH v4 10/20] scmi_protocols: update struct
> scmi_base_discover_list_protocols_out
> 
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> opening attachments. When in doubt, report the message using the 'Report this
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> 
> 
> On 1/15/25 2:28 PM, Alice Guo wrote:
> > From: Ye Li 
> >
> > @protocols is an array of protocol identifiers that are implemented,
> > excluding the Base protocol. The number of elements of @protocols is
> > specified by callee-side. Currently, set it to 4 is enough for i.MX95.
> Can you please try something like this instead ? That should be
> future-proof:
> 
> diff --git a/drivers/firmware/scmi/base.c b/drivers/firmware/scmi/base.c index
> f4e3974ff5b..92d278edfaf 100644
> --- a/drivers/firmware/scmi/base.c
> +++ b/drivers/firmware/scmi/base.c
> @@ -258,17 +258,16 @@ static int
> scmi_base_discover_impl_version_int(struct udevice *dev,
>   static int scmi_base_discover_list_protocols_int(struct udevice *dev,
>  u8 **protocols)
>   {
> -   struct scmi_base_discover_list_protocols_out out;
> +   struct scmi_base_discover_list_protocols_out *out;
> int cur;
> struct scmi_msg msg = {
> .protocol_id = SCMI_PROTOCOL_ID_BASE,
> .message_id = SCMI_BASE_DISCOVER_LIST_PROTOCOLS,
> .in_msg = (u8 *)&cur,
> .in_msg_sz = sizeof(cur),
> -   .out_msg = (u8 *)&out,
> -   .out_msg_sz = sizeof(out),

The pointer and byte size of the buffer where the response message is stored 
should be provided before sending a BASE_DISCOVER_LIST PROTOCOLS message.

There is a more reasonable way. Number of protocols that are implemented, 
excluding the Base protocol, can be obtained by sending a PROTOCOL_ATTRIBUTES 
message. But now this command is not supported in U-Boot. In this patch, 
ec8727b7e1 ("firmware: scmi: implement SCMI base protocol"), "u32 
protocols[3];" is used. So, I think setting the array of packed SCMI protocol 
ID's to a fixed size is acceptable.

Best Regards,
Alice Guo

> };
> u32 num_agents, num_protocols;
> +   int size;
> u8 *buf;
> int i, ret;
> 
> @@ -276,29 +275,34 @@ static int
> scmi_base_discover_list_protocols_int(struct udevice *dev,
> if (ret)
> return ret;
> 
> -   buf = calloc(sizeof(u8), num_protocols);
> -   if (!buf)
> +   size = sizeof(*out) + sizeof(u8) * num_protocols;
> +   out = calloc(1, size);
> +   if (!out)
> return -ENOMEM;
> 
> +   msg.out_msg = (u8 *)out;
> +   msg.out_msg_sz = size;
> +   buf = (u8 *)out->protocols;
> +
> cur = 0;
> do {
> ret = devm_scmi_process_msg(dev, &msg);
> if (ret)
> goto err;
> -   if (out.status) {
> -   ret = scmi_to_linux_errno(out.status);
> +   if (out->status) {
> +   ret = scmi_to_linux_errno(out->status);
> goto err;
> }
> 
> -   for (i = 0; i < out.num_protocols; i++, cur++)
> -   buf[cur] = out.protocols[i / 4] >> ((i % 4) * 8);
> +   for (i = 0; i < out->num_protocols; i++, cur++)
> +   buf[cur] = out->protocols[i / 4] >> ((i % 4) *
> + 8);
> } while (cur < num_protocols);
> 
> *protocols = buf;
> 
> return num_protocols;
>   err:
> -   free(buf);
> +   free(out);
> 
> return ret;
>   }
> diff --git a/include/scmi_protocols.h b/include/scmi_protocols.h index
> a51234eda5c..29a7fd85cc0 100644
> --- a/include/scmi_protocols.h
> +++ b/include/scmi_protocols.h
> @@ -148,7 +148,7 @@ struct scmi_base_discover_impl_version_out {
>   struct scmi_base_discover_list_protocols_out {
> s32 status;
> u32 num_protocols;
> -   u32 protocols[4];
> +   u32 protocols[];
>   };
> 
>   /**

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