Re: usb:composite: data abort on second ums launch
On 3/24/25 11:42 AM, Zixun LI wrote: Hi, I encountered a data abort on the 2nd "ums 0 mmc 0" command on u-boot-at91 2024.07 with sam9x60-curiosity board. U-Boot> ums 0 mmc 0 UMS: LUN 0, dev mmc 0, hwpart 0, sector 0x0, count 0x1d29000 CTRL+C - Operation aborted U-Boot> ums 0 mmc 0 UMS: LUN 0, dev mmc 0, hwpart 0, sector 0x0, count 0x1d29000 data abort pc : [<27f93428>] lr : [<27ef7e80>] reloc pc : [<23f16428>]lr : [<23e7ae80>] sp : 27ef4cf0 ip : a520 fp : 23f6915c r10: deadbeef r9 : 27ef7e80 r8 : 27f7d2a0 r7 : a520 r6 : r5 : r4 : 27f01668 r3 : r2 : r1 : 27fe1d88 r0 : 27f01668 Flags: nzCV IRQs off FIQs off Mode SVC_32 (T) Code: 45ac d017 68c5 4667 (60fd) 60af From backtrace the abort happened in fREe_impl(), with some debugging I've localized the abort in fact happened in fsg buffer allocation in fsg_common_init() [1] It looks like the buffer is not freed on driver unregister since fsg_common_release() is only called if fsg_common_init() met an error. Can you reproduce this on u-boot/master too ?
Re: [PATCH] usb: dwc3: gadget: Fix match_ep callback for NXP UUU tool
On 3/24/25 1:30 PM, Francesco Dolcini wrote: On Mon, Mar 24, 2025 at 09:26:03AM +0100, Mattijs Korpershoek wrote: Hi Francesco, On lun., mars 24, 2025 at 09:03, Francesco Dolcini wrote: Hello Mattijs, Marek On Thu, Mar 20, 2025 at 10:47:02AM +0100, Mattijs Korpershoek wrote: On mer., mars 19, 2025 at 23:07, Marek Vasut wrote: The UUU tool excepts the interrupt-in endpoint to be ep1in, otherwise it crashes. This is a result of the previous hard-coded EP setup in drivers/usb/gadget/epautoconf.c which did special-case EP allocation for SPL builds, and which was since converted to this callback, but without the special-case EP allocation in SPL part. This reinstates the SPL part in an isolated manner, only for NXP iMX SoCs, only for SPL builds, and only for the ep1in interrupt-in endpoint. UUU can (and in our case is) used also on non-NXP i.MX platforms. What should we do? Do reproduce the problem (UUU tool crashes) on those platforms with recent U-Boot versions (v2024.10+) ? Not tested, my comment is purely based on the code and the commit message. Older U-Boot versions (up to v2024.04, included) are working fine, with UUU used with TI K3 SoCs (AM69, AM62, AM62P). Are you talking about the NXP UUU ? https://github.com/NXPmicro/mfgtools.git
[resend v3 10/12] test: cmd: Add simple test for i3c
From: Dinesh Maniyam
Add simple test to check i3c controller defined in sandbox test DT.
Basically, this test case will check validity of the i3c controller
by probing it and perform basic commands of cmd/i3c.c
Signed-off-by: Dinesh Maniyam
---
test/cmd/Makefile | 1 +
test/cmd/i3c.c| 52 +++
2 files changed, 53 insertions(+)
create mode 100644 test/cmd/i3c.c
diff --git a/test/cmd/Makefile b/test/cmd/Makefile
index d8a5e77402d..d1c49e2c97a 100644
--- a/test/cmd/Makefile
+++ b/test/cmd/Makefile
@@ -34,6 +34,7 @@ obj-$(CONFIG_CMD_PWM) += pwm.o
obj-$(CONFIG_CMD_READ) += rw.o
obj-$(CONFIG_CMD_SETEXPR) += setexpr.o
obj-$(CONFIG_CMD_TEMPERATURE) += temperature.o
+obj-$(CONFIG_CMD_I3C) += i3c.o
ifdef CONFIG_NET
obj-$(CONFIG_CMD_WGET) += wget.o
endif
diff --git a/test/cmd/i3c.c b/test/cmd/i3c.c
new file mode 100644
index 000..471dfacd5c7
--- /dev/null
+++ b/test/cmd/i3c.c
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025 Altera Corporation
+ */
+
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Basic test for probing i3c controller with invalid name */
+static int dm_test_i3c_cmd_probe_invalid_master(struct unit_test_state *uts)
+{
+ ut_asserteq(1, run_command("i3c any", 0));
+ ut_assert_nextline("i3c0 (i3c_sandbox)");
+ ut_assert_nextline("i3c1 (i3c_sandbox)");
+ ut_assert_nextline("i3c master controller is not initialized: any");
+ ut_assert_console_end();
+
+ return 0;
+}
+DM_TEST(dm_test_i3c_cmd_probe_invalid_master, UTF_SCAN_PDATA | UTF_SCAN_FDT |
UTF_DM);
+
+/* Basic test of the i3c controller for valid name as per test DT */
+static int dm_test_i3c_cmd_probe_valid_master(struct unit_test_state *uts)
+{
+ ut_asserteq(0, run_command("i3c i3c0", 0));
+ ut_assert_nextline("current dev: i3c0");
+ ut_assert_console_end();
+
+ ut_asserteq(0, run_command("i3c current", 0));
+ ut_assert_nextline("current dev: i3c0");
+ ut_assert_console_end();
+
+ ut_asserteq(0, run_command("i3c i3c1", 0));
+ ut_assert_nextline("current dev: i3c1");
+ ut_assert_console_end();
+
+ ut_asserteq(0, run_command("i3c current", 0));
+ ut_assert_nextline("current dev: i3c1");
+ ut_assert_console_end();
+
+ ut_asserteq(0, run_command("i3c list", 0));
+ ut_assert_nextline("i3c0 (i3c_sandbox)");
+ ut_assert_nextline("i3c1 (i3c_sandbox)");
+ ut_assert_console_end();
+
+ return 0;
+}
+DM_TEST(dm_test_i3c_cmd_probe_valid_master, UTF_SCAN_PDATA | UTF_SCAN_FDT |
UTF_DM);
--
2.26.2
[resend v3 08/12] i3c: master: dw-i3c-master: Fix OD_TIMING for spike filter
From: Dinesh Maniyam
Fix the I3C device with spike filter unable to detect issue by setting
tHIGH_INIT to 200ns for first broadcast address.
This is according to MIPI SPEC 1.1.1 for first broadcast address
which is already part of linux upstreamed patch.
Signed-off-by: Dinesh Maniyam
---
drivers/i3c/master/dw-i3c-master.c | 23 +++
include/dw-i3c.h | 1 +
include/linux/i3c/master.h | 1 +
3 files changed, 25 insertions(+)
diff --git a/drivers/i3c/master/dw-i3c-master.c
b/drivers/i3c/master/dw-i3c-master.c
index b3c5bf210c6..af6e472f232 100644
--- a/drivers/i3c/master/dw-i3c-master.c
+++ b/drivers/i3c/master/dw-i3c-master.c
@@ -330,6 +330,14 @@ static int dw_i3c_clk_cfg(struct dw_i3c_master *master)
if (hcnt < SCL_I3C_TIMING_CNT_MIN)
hcnt = SCL_I3C_TIMING_CNT_MIN;
+ /* set back to THIGH_MAX_NS, after disable spike filter */
+ if (!master->first_broadcast) {
+ lcnt = SCL_I3C_TIMING_LCNT(readl(master->regs +
SCL_I3C_OD_TIMING));
+ scl_timing = SCL_I3C_TIMING_HCNT(hcnt) | lcnt;
+ writel(scl_timing, master->regs + SCL_I3C_OD_TIMING);
+ return 0;
+ }
+
lcnt = DIV_ROUND_UP(core_rate, master->base.bus.scl_rate.i3c) - hcnt;
if (lcnt < SCL_I3C_TIMING_CNT_MIN)
lcnt = SCL_I3C_TIMING_CNT_MIN;
@@ -347,6 +355,9 @@ static int dw_i3c_clk_cfg(struct dw_i3c_master *master)
lcnt = max_t(u8,
DIV_ROUND_UP(I3C_BUS_TLOW_OD_MIN_NS, core_period), lcnt);
+ /* first broadcast thigh to 200ns, to disable spike filter */
+ hcnt = DIV_ROUND_UP(I3C_BUS_THIGH_INIT_OD_MIN_NS, core_period);
+
scl_timing = SCL_I3C_TIMING_HCNT(hcnt) | SCL_I3C_TIMING_LCNT(lcnt);
writel(scl_timing, master->regs + SCL_I3C_OD_TIMING);
@@ -402,6 +413,9 @@ static int dw_i3c_master_bus_init(struct
i3c_master_controller *m)
u32 thld_ctrl;
int ret;
+ /* first broadcast to disable spike filter */
+ master->first_broadcast = true;
+
switch (bus->mode) {
case I3C_BUS_MODE_MIXED_FAST:
case I3C_BUS_MODE_MIXED_LIMITED:
@@ -481,6 +495,15 @@ static void dw_i3c_master_irq_handler(struct dw_i3c_master
*master)
if (status & INTR_TRANSFER_ERR_STAT)
writel(INTR_TRANSFER_ERR_STAT, master->regs + INTR_STATUS);
+ /* set back to THIGH_MAX_NS, after disable spike filter */
+ if (master->first_broadcast) {
+ master->first_broadcast = false;
+ int ret = dw_i3c_clk_cfg(master);
+
+ if (ret)
+ pr_err("Failed to set clk cfg\n");
+ }
+
spin_unlock(&master->xferqueue.lock);
}
diff --git a/include/dw-i3c.h b/include/dw-i3c.h
index 920f18bccb4..42c37d6dfa2 100644
--- a/include/dw-i3c.h
+++ b/include/dw-i3c.h
@@ -240,6 +240,7 @@ struct dw_i3c_master {
char version[5];
char type[5];
u8 addrs[MAX_DEVS];
+ bool first_broadcast;
};
struct dw_i3c_i2c_dev_data {
diff --git a/include/linux/i3c/master.h b/include/linux/i3c/master.h
index bafb1448b57..c2391170ae1 100644
--- a/include/linux/i3c/master.h
+++ b/include/linux/i3c/master.h
@@ -278,6 +278,7 @@ struct i3c_device {
#define I3C_BUS_I2C_FM_PLUS_SCL_RATE 100
#define I3C_BUS_I2C_FM_SCL_RATE40
#define I3C_BUS_TLOW_OD_MIN_NS 200
+#define I3C_BUS_THIGH_INIT_OD_MIN_NS 200
/**
* enum i3c_bus_mode - I3C bus mode
--
2.26.2
Re: [PATCH] efi_loader: fix ipv4 device path node conversion
On 24.03.25 09:34, Vincent Stehlé wrote:
When converting an IPv4 device path node to text, the
EFI_DEVICE_PATH_TO_TEXT_PROTOCOL will produce the following string:
IPv4(5.6.7.8,TCP,UDP,0x6,DHCP,1.2.3.4,9.10.11.12,255.255.255.0)
This string erroneously contains multiple protocols: TCP, UDP and 0x6.
Add the missing `break' statements in the dp_msging() function to fix this
and obtain the following expected string instead:
IPv4(5.6.7.8,TCP,DHCP,1.2.3.4,9.10.11.12,255.255.255.0)
Fixes: aaf63429a112 ("efi_loader: add IPv4() to device path to text protocol")
Signed-off-by: Vincent Stehlé
Cc: Heinrich Schuchardt
Cc: Ilias Apalodimas
Cc: Adriano Cordova
Cc: Tom Rini
Reviewed-by: Heinrich Schuchardt
---
lib/efi_loader/efi_device_path_to_text.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/lib/efi_loader/efi_device_path_to_text.c
b/lib/efi_loader/efi_device_path_to_text.c
index f6889cb7399..452ec1b2e8b 100644
--- a/lib/efi_loader/efi_device_path_to_text.c
+++ b/lib/efi_loader/efi_device_path_to_text.c
@@ -181,10 +181,13 @@ static char *dp_msging(char *s, struct efi_device_path
*dp)
switch (idp->protocol) {
case IPPROTO_TCP:
s += sprintf(s, "TCP,");
+ break;
case IPPROTO_UDP:
s += sprintf(s, "UDP,");
+ break;
default:
s += sprintf(s, "0x%x,", idp->protocol);
+ break;
}
s += sprintf(s, idp->static_ip_address ? "Static" : "DHCP");
s += sprintf(s, ",%pI4", &idp->local_ip_address);
Re: [PATCH 1/3] mux: Kconfig: Add Kconfig options for MUX_MMIO
On Thu, Mar 20, 2025 at 12:00:02PM +0530, Anurag Dutta wrote: > Add Kconfig options for MUX_MMIO so that it can be enabled > in SPL stage. > > Signed-off-by: Anurag Dutta > --- > drivers/mux/Kconfig | 10 ++ > 1 file changed, 10 insertions(+) > > diff --git a/drivers/mux/Kconfig b/drivers/mux/Kconfig > index f15ee4f833f..2b95eb02177 100644 > --- a/drivers/mux/Kconfig > +++ b/drivers/mux/Kconfig > @@ -10,6 +10,16 @@ config MULTIPLEXER > > if MULTIPLEXER > > +config SPL_MUX_MMIO > + bool "MMIO register bitfield-controlled Multiplexer" > +depends on MULTIPLEXER && SYSCON > +help > + MMIO register bitfield-controlled Multiplexer controller. > + > + The driver builds multiplexer controllers for bitfields in a syscon > + register. For N bit wide bitfields, there will be 2^N possible > + multiplexer states. > + > config MUX_MMIO > bool "MMIO register bitfield-controlled Multiplexer" > depends on MULTIPLEXER && SYSCON First, "config SPL_FOO" should follow "config FOO". Second, "config MUX_MMIO" is written wrong because doing: if MULTIPLEXER config MUX_MMIO bool "..." depends on MULTIPLEXER endif Is redundant. Lets fix that and then not repeat it when adding SPL_MUX_MMIO. Next, it should be "default y if MUX_MMIO" _unless_ it's really not going to be needed in most cases, and then yes, what you did is right. Finally, SPL_MUX_MMIO should depend on SPL_SYSCON as that symbol does exist. Thanks. -- Tom signature.asc Description: PGP signature
[PATCH v2] cmd: pmic: add fall through comment
Make fall through explicit via a fallthrough statement to allow building
with -Wimplicit-fallthrough.
Signed-off-by: Heinrich Schuchardt
---
v2:
in commit message replace 'comment' by 'statement'.
---
cmd/pmic.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/cmd/pmic.c b/cmd/pmic.c
index 3ad1b8aa375..c5eea766a31 100644
--- a/cmd/pmic.c
+++ b/cmd/pmic.c
@@ -34,6 +34,7 @@ static int do_dev(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
printf("Can't get PMIC: %s!\n", name);
return failure(ret);
}
+ fallthrough;
case 1:
if (!currdev) {
printf("PMIC device is not set!\n\n");
--
2.48.1
[PATCH 3/6] ARM: dts: stm32: add display support on stm32f769-disco
[backport from Linux commit 598e5adfeb6062f5d4d352c0ef888b2b29d7e215]
The patch adds display support on the stm32f769-disco board.
Signed-off-by: Dario Binacchi
---
arch/arm/dts/stm32f769-disco-u-boot.dtsi | 34 --
arch/arm/dts/stm32f769-disco.dts | 58
2 files changed, 58 insertions(+), 34 deletions(-)
diff --git a/arch/arm/dts/stm32f769-disco-u-boot.dtsi
b/arch/arm/dts/stm32f769-disco-u-boot.dtsi
index c5ae753debe6..16a9eecd4a99 100644
--- a/arch/arm/dts/stm32f769-disco-u-boot.dtsi
+++ b/arch/arm/dts/stm32f769-disco-u-boot.dtsi
@@ -32,18 +32,6 @@
compatible = "st,led1";
led-gpio = <&gpioj 5 0>;
};
-
- panel: panel {
- compatible = "orisetech,otm8009a";
- reset-gpios = <&gpioj 15 1>;
- status = "okay";
-
- port {
- panel_in: endpoint {
- remote-endpoint = <&dsi_out>;
- };
- };
- };
};
&dsi {
@@ -52,33 +40,11 @@
<&clk_hse>;
clock-names = "pclk", "px_clk", "ref";
bootph-all;
- status = "okay";
-
- ports {
- port@0 {
- dsi_out: endpoint {
- remote-endpoint = <&panel_in>;
- };
- };
- port@1 {
- dsi_in: endpoint {
- remote-endpoint = <&dp_out>;
- };
- };
- };
};
;
bootph-all;
-
- ports {
- port@0 {
- dp_out: endpoint {
- remote-endpoint = <&dsi_in>;
- };
- };
- };
};
&fmc {
diff --git a/arch/arm/dts/stm32f769-disco.dts b/arch/arm/dts/stm32f769-disco.dts
index b4e240a8e3eb..3fd5140ec5eb 100644
--- a/arch/arm/dts/stm32f769-disco.dts
+++ b/arch/arm/dts/stm32f769-disco.dts
@@ -24,6 +24,19 @@
reg = <0xC000 0x100>;
};
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ linux,dma {
+ compatible = "shared-dma-pool";
+ linux,dma-default;
+ no-map;
+ size = <0x10>;
+ };
+ };
+
aliases {
serial0 = &usart1;
};
@@ -78,6 +91,45 @@
clock-frequency = <2500>;
};
+&dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi_in: endpoint {
+ remote-endpoint = <;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi_out: endpoint {
+ remote-endpoint = <&dsi_panel_in>;
+ };
+ };
+ };
+
+ panel0: panel@0 {
+ compatible = "orisetech,otm8009a";
+ reg = <0>; /* dsi virtual channel (0..3) */
+ reset-gpios = <&gpioj 15 GPIO_ACTIVE_LOW>;
+ power-supply = <&vcc_3v3>;
+ status = "okay";
+
+ port {
+ dsi_panel_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+ };
+};
+
&i2c1 {
pinctrl-0 = <&i2c1_pins_b>;
pinctrl-names = "default";
@@ -88,6 +140,12 @@
;
+ };
+ };
};
&rtc {
--
2.43.0
[PATCH 2/6] ARM: dts: stm32: rename mmc_vcard to vcc-3v3 on stm32f769-disco
[backport from Linux commit f1317928fa03203929665af61e6d9ac0e29ea84d]
In the schematics of document UM2033, the power supply for the micro SD
card is the same 3v3 voltage that is used to power other devices on the
board. By generalizing the name of the voltage regulator, it can be
referenced by other nodes in the device tree without creating
misunderstandings.
This patch is preparatory for future developments.
Signed-off-by: Dario Binacchi
---
arch/arm/dts/stm32f769-disco.dts | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/stm32f769-disco.dts b/arch/arm/dts/stm32f769-disco.dts
index ad1b442055e1..b4e240a8e3eb 100644
--- a/arch/arm/dts/stm32f769-disco.dts
+++ b/arch/arm/dts/stm32f769-disco.dts
@@ -56,9 +56,9 @@
clock-names = "main_clk";
};
- mmc_vcard: mmc_vcard {
+ vcc_3v3: vcc-3v3 {
compatible = "regulator-fixed";
- regulator-name = "mmc_vcard";
+ regulator-name = "vcc_3v3";
regulator-min-microvolt = <330>;
regulator-max-microvolt = <330>;
};
@@ -96,7 +96,7 @@
&sdio2 {
status = "okay";
- vmmc-supply = <&mmc_vcard>;
+ vmmc-supply = <&vcc_3v3>;
cd-gpios = <&gpioi 15 GPIO_ACTIVE_LOW>;
broken-cd;
pinctrl-names = "default", "opendrain";
--
2.43.0
[PATCH 6/6] board: stm32f769-disco: support FRD400B25025-A-CTK display
Support FRIDA FRD400B25025-A-CTK display on stm32f769-disco board. As reported in the section 8.3 (i. e. Board revision history) of document UM2033 (i. e. Discovery kit with STM32F769NI MCU) these are the changes related to the board revision addressed by the patch: - Board MB1166 revision A-09: - LCD FRIDA FRD397B25009-D-CTK replaced by FRIDA FRD400B25025-A-CTK This means that the MB1166-A09 is using an NT35510 panel controller, unlike the previous versions which use an OTM8009A controller. Therefore, let's add support for NT35510 panel handling to the stm32f769-disco board configurations. Signed-off-by: Dario Binacchi --- configs/stm32f769-disco_defconfig | 2 ++ configs/stm32f769-disco_spl_defconfig | 2 ++ 2 files changed, 4 insertions(+) diff --git a/configs/stm32f769-disco_defconfig b/configs/stm32f769-disco_defconfig index 5be221afd2fa..e50d62e93bd6 100644 --- a/configs/stm32f769-disco_defconfig +++ b/configs/stm32f769-disco_defconfig @@ -52,12 +52,14 @@ CONFIG_DW_ALTDESCRIPTOR=y CONFIG_MII=y # CONFIG_PINCTRL_FULL is not set CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_STM32_QSPI=y CONFIG_VIDEO=y CONFIG_VIDEO_LOGO=y CONFIG_BACKLIGHT_GPIO=y +CONFIG_VIDEO_LCD_NOVATEK_NT35510=y CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y CONFIG_VIDEO_STM32=y CONFIG_VIDEO_STM32_DSI=y diff --git a/configs/stm32f769-disco_spl_defconfig b/configs/stm32f769-disco_spl_defconfig index 7d4bda440685..6229ee5089f5 100644 --- a/configs/stm32f769-disco_spl_defconfig +++ b/configs/stm32f769-disco_spl_defconfig @@ -75,6 +75,7 @@ CONFIG_MII=y # CONFIG_PINCTRL_FULL is not set CONFIG_SPL_PINCTRL=y CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y CONFIG_SPL_RAM=y CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_SPI=y @@ -84,6 +85,7 @@ CONFIG_SPL_TIMER=y CONFIG_VIDEO=y CONFIG_VIDEO_LOGO=y CONFIG_BACKLIGHT_GPIO=y +CONFIG_VIDEO_LCD_NOVATEK_NT35510=y CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y CONFIG_VIDEO_STM32=y CONFIG_VIDEO_STM32_DSI=y -- 2.43.0
[PATCH 4/6] ARM: dts: add stm32f769-disco-mb1166-reva09
[backport from Linux commit db4fc2c79c533986795a7750e9a12caf9d620b48]
As reported in the section 8.3 (i. e. Board revision history) of document
UM2033 (i. e. Discovery kit with STM32F769NI MCU) these are the changes
related to the board revision addressed by the patch:
- Board MB1166 revision A-09:
- LCD FRIDA FRD397B25009-D-CTK replaced by FRIDA FRD400B25025-A-CTK
The patch adds the DTS support for the new display which belongs to the
the Novatek NT35510-based panel family.
Signed-off-by: Dario Binacchi
---
arch/arm/dts/Makefile | 1 +
.../dts/stm32f769-disco-mb1166-reva09-u-boot.dtsi | 6 ++
arch/arm/dts/stm32f769-disco-mb1166-reva09.dts | 13 +
3 files changed, 20 insertions(+)
create mode 100644 arch/arm/dts/stm32f769-disco-mb1166-reva09-u-boot.dtsi
create mode 100644 arch/arm/dts/stm32f769-disco-mb1166-reva09.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 267b0179a5f2..8719b58152fd 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -523,6 +523,7 @@ dtb-$(CONFIG_STM32F4) += stm32f429-disco.dtb \
dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb \
stm32f769-disco.dtb \
+ stm32f769-disco-mb1166-reva09.dtb \
stm32746g-eval.dtb
dtb-$(CONFIG_STM32H7) += stm32h743i-disco.dtb \
stm32h743i-eval.dtb \
diff --git a/arch/arm/dts/stm32f769-disco-mb1166-reva09-u-boot.dtsi
b/arch/arm/dts/stm32f769-disco-mb1166-reva09-u-boot.dtsi
new file mode 100644
index ..43dd3b993d5e
--- /dev/null
+++ b/arch/arm/dts/stm32f769-disco-mb1166-reva09-u-boot.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright (c) 2025 Dario Binacchi
+//
+
+#include
diff --git a/arch/arm/dts/stm32f769-disco-mb1166-reva09.dts
b/arch/arm/dts/stm32f769-disco-mb1166-reva09.dts
new file mode 100644
index ..ff7ff32371d0
--- /dev/null
+++ b/arch/arm/dts/stm32f769-disco-mb1166-reva09.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023 Dario Binacchi
+ */
+
+#include "stm32f769-disco.dts"
+
+&panel0 {
+ compatible = "frida,frd400b25025", "novatek,nt35510";
+ vddi-supply = <&vcc_3v3>;
+ vdd-supply = <&vcc_3v3>;
+ /delete-property/power-supply;
+};
--
2.43.0
Re: [PATCH v2 2/4] net: ravb: Add optional reset deassertion
On 3/24/25 10:57 AM, Paul Barker wrote:
On 24/03/2025 01:08, Marek Vasut wrote:
On 3/19/25 1:03 PM, Paul Barker wrote:
[...]
static int ravb_probe(struct udevice *dev)
{
+ struct ravb_device_ops *device_ops =
+ (struct ravb_device_ops *)dev_get_driver_data(dev);
struct eth_pdata *pdata = dev_get_plat(dev);
struct ravb_priv *eth = dev_get_priv(dev);
struct mii_dev *mdiodev;
@@ -648,16 +653,32 @@ static int ravb_probe(struct udevice *dev)
if (ret)
goto err_clk_enable;
+ if (device_ops->has_reset) {
+ ret = reset_get_by_index(dev, 0, ð->rst);
Can devm_reset_control_get_optional() maybe be used here instead of the
flag ?
The Ethernet device tree nodes for RZ/G2{H,M,N,E} also contain a reset,
so we can't use the _optional() function here to perform the reset only
for RZ/G2L.
Does it pose a problem if we trigger a reset on RZ/G2(non-L) ?
Re: [PATCH 2/2] sunxi: H616: dram: Improve address wrapping detection
On Sun, 9 Mar 2025 07:31:43 +0100
Jernej Skrabec wrote:
Hi,
> It turns out that checking just one write is not enough. Due to
> unexplained reasons scan procedure detected double the size. By making
> 16 dword writes and comparisons that never happens.
>
> New procedure is also inverted. Instead of writing two different values
> to base address and some offset and then reading both and comparing
> values, simplify this by writing pattern at the base address and then
> search for this pattern at some offset.
>
> Signed-off-by: Jernej Skrabec
Thanks for improving this, I guess we want to eventually move this to
more generic code, and use this for more SoCs?
Anyway:
Reviewed-by: Andre Przywara
Cheers,
Andre
> ---
> arch/arm/mach-sunxi/dram_sun50i_h616.c | 58 +-
> 1 file changed, 56 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c
> b/arch/arm/mach-sunxi/dram_sun50i_h616.c
> index 6f84e59e39cd..1e21f5dd451f 100644
> --- a/arch/arm/mach-sunxi/dram_sun50i_h616.c
> +++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c
> @@ -1360,38 +1360,92 @@ static void mctl_auto_detect_rank_width(const struct
> dram_para *para,
> panic("This DRAM setup is currently not supported.\n");
> }
>
> +static void mctl_write_pattern(void)
> +{
> + unsigned int i;
> + u32 *ptr, val;
> +
> + ptr = (u32 *)CFG_SYS_SDRAM_BASE;
> + for (i = 0; i < 16; ptr++, i++) {
> + if (i & 1)
> + val = ~(ulong)ptr;
> + else
> + val = (ulong)ptr;
> + writel(val, ptr);
> + }
> +}
> +
> +static bool mctl_check_pattern(ulong offset)
> +{
> + unsigned int i;
> + u32 *ptr, val;
> +
> + ptr = (u32 *)CFG_SYS_SDRAM_BASE;
> + for (i = 0; i < 16; ptr++, i++) {
> + if (i & 1)
> + val = ~(ulong)ptr;
> + else
> + val = (ulong)ptr;
> + if (val != *(ptr + offset / 4))
> + return false;
> + }
> +
> + return true;
> +}
> +
> static void mctl_auto_detect_dram_size(const struct dram_para *para,
> struct dram_config *config)
> {
> unsigned int shift, cols, rows;
> + u32 buffer[16];
>
> /* max. config for columns, but not rows */
> config->cols = 11;
> config->rows = 13;
> mctl_core_init(para, config);
>
> + /*
> + * Store content so it can be restored later. This is important
> + * if controller was already initialized and holds any data
> + * which is important for restoring system.
> + */
> + memcpy(buffer, (u32 *)CFG_SYS_SDRAM_BASE, sizeof(buffer));
> +
> + mctl_write_pattern();
> +
> shift = config->bus_full_width + 1;
>
> /* detect column address bits */
> for (cols = 8; cols < 11; cols++) {
> - if (mctl_mem_matches(1ULL << (cols + shift)))
> + if (mctl_check_pattern(1ULL << (cols + shift)))
> break;
> }
> debug("detected %u columns\n", cols);
>
> + /* restore data */
> + memcpy((u32 *)CFG_SYS_SDRAM_BASE, buffer, sizeof(buffer));
> +
> /* reconfigure to make sure that all active rows are accessible */
> config->cols = 8;
> config->rows = 17;
> mctl_core_init(para, config);
>
> + /* store data again as it might be moved */
> + memcpy(buffer, (u32 *)CFG_SYS_SDRAM_BASE, sizeof(buffer));
> +
> + mctl_write_pattern();
> +
> /* detect row address bits */
> shift = config->bus_full_width + 4 + config->cols;
> for (rows = 13; rows < 17; rows++) {
> - if (mctl_mem_matches(1ULL << (rows + shift)))
> + if (mctl_check_pattern(1ULL << (rows + shift)))
> break;
> }
> debug("detected %u rows\n", rows);
>
> + /* restore data again */
> + memcpy((u32 *)CFG_SYS_SDRAM_BASE, buffer, sizeof(buffer));
> +
> config->cols = cols;
> config->rows = rows;
> }
Re: [PATCH] usb: dwc3: gadget: Fix match_ep callback for NXP UUU tool
On Mon, Mar 24, 2025 at 02:53:23PM +0100, Marek Vasut wrote: > On 3/24/25 1:30 PM, Francesco Dolcini wrote: > > On Mon, Mar 24, 2025 at 09:26:03AM +0100, Mattijs Korpershoek wrote: > > > Hi Francesco, > > > > > > On lun., mars 24, 2025 at 09:03, Francesco Dolcini > > > wrote: > > > > > > > Hello Mattijs, Marek > > > > > > > > On Thu, Mar 20, 2025 at 10:47:02AM +0100, Mattijs Korpershoek wrote: > > > > > On mer., mars 19, 2025 at 23:07, Marek Vasut wrote: > > > > > > > > > > > The UUU tool excepts the interrupt-in endpoint to be ep1in, > > > > > > otherwise > > > > > > it crashes. This is a result of the previous hard-coded EP setup in > > > > > > drivers/usb/gadget/epautoconf.c which did special-case EP allocation > > > > > > for SPL builds, and which was since converted to this callback, but > > > > > > without the special-case EP allocation in SPL part. > > > > > > > > > > > > This reinstates the SPL part in an isolated manner, only for NXP iMX > > > > > > SoCs, only for SPL builds, and only for the ep1in interrupt-in > > > > > > endpoint. > > > > > > > > UUU can (and in our case is) used also on non-NXP i.MX platforms. > > > > What should we do? > > > > > > Do reproduce the problem (UUU tool crashes) on those platforms with > > > recent U-Boot versions (v2024.10+) ? > > > > Not tested, my comment is purely based on the code and the commit message. > > Older U-Boot versions (up to v2024.04, included) are working fine, with UUU > > used > > with TI K3 SoCs (AM69, AM62, AM62P). > Are you talking about the NXP UUU ? yes, it works just fine on not-NXP SoC. Francesco
Re: [PATCH] usb: dwc3: gadget: Fix match_ep callback for NXP UUU tool
Hi Neil,
On lun., mars 24, 2025 at 10:20, Neil Armstrong
wrote:
> On 19/03/2025 23:07, Marek Vasut wrote:
>> The UUU tool excepts the interrupt-in endpoint to be ep1in, otherwise
>> it crashes. This is a result of the previous hard-coded EP setup in
>> drivers/usb/gadget/epautoconf.c which did special-case EP allocation
>> for SPL builds, and which was since converted to this callback, but
>> without the special-case EP allocation in SPL part.
>>
>> This reinstates the SPL part in an isolated manner, only for NXP iMX
>> SoCs, only for SPL builds, and only for the ep1in interrupt-in endpoint.
>>
>> Fixes: 1918b8010c32 ("usb: dwc3: gadget: Convert epautoconf workaround to
>> match_ep callback")
>> Signed-off-by: Marek Vasut
>> ---
>> Cc: Alexander Sverdlin
>> Cc: Felipe Balbi
>> Cc: Lukasz Majewski
>> Cc: Marek Vasut
>> Cc: Mattijs Korpershoek
>> Cc: Neil Armstrong
>> Cc: Thinh Nguyen
>> Cc: Tom Rini
>> Cc: u-boot@lists.denx.de
>> ---
>> NOTE: This should go into master as a bugfix.
>> ---
>> drivers/usb/dwc3/gadget.c | 19 ++-
>> 1 file changed, 18 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
>> index e5a383407a2..477ecd02098 100644
>> --- a/drivers/usb/dwc3/gadget.c
>> +++ b/drivers/usb/dwc3/gadget.c
>> @@ -1631,8 +1631,25 @@ usb_ep *dwc3_gadget_match_ep(struct usb_gadget
>> *gadget,
>> return dwc3_find_ep(gadget, "ep1in");
>> if (usb_endpoint_is_bulk_out(desc))
>> return dwc3_find_ep(gadget, "ep2out");
>> -if (usb_endpoint_is_int_in(desc))
>> +if (usb_endpoint_is_int_in(desc)) {
>> +/*
>> + * Special workaround for NXP UUU tool in SPL.
>> + *
>> + * The tool excepts the interrupt-in endpoint to be ep1in,
>
> Small nit: expects
Argh, I missed this :( The code already landed in master:
https://source.denx.de/u-boot/u-boot/-/commit/0916053ebc566245b06d0a179533f6622b6ad392
If we have to modify this again we can fixup the comment typo at the
same time.
Thanks for catching it!
>
>> + * otherwise it crashes. This is a result of the previous
>> + * hard-coded EP setup in drivers/usb/gadget/epautoconf.c
>> + * which did special-case EP allocation for SPL builds,
>> + * and which was since converted to this callback, but
>> + * without the special-case EP allocation in SPL part.
>> + *
>> + * This reinstates the SPL part in an isolated manner,
>> + * only for NXP iMX SoCs, only for SPL builds, and only
>> + * for the ep1in interrupt-in endpoint.
>> + */
>> +if (IS_ENABLED(CONFIG_MACH_IMX) && IS_ENABLED(CONFIG_XPL_BUILD))
>> +return dwc3_find_ep(gadget, "ep1in");
>> return dwc3_find_ep(gadget, "ep3in");
>> +}
>>
>> return NULL;
>> }
Re: [PATCH 1/2] mach-snapdragon: of_fixup: fix property length at writing
On 2/27/25 10:45, Rui Miguel Silva wrote:
The length of a property includes '\0' in a string type one, so
the length passed by needs to have that in account, if not,
when getting the property value it will fail because it
has the wrong size.
Signed-off-by: Rui Miguel Silva
Tested-by: # db845c
Reviewed-by: Caleb Connolly
---
arch/arm/mach-snapdragon/of_fixup.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-snapdragon/of_fixup.c
b/arch/arm/mach-snapdragon/of_fixup.c
index 55368dd43b66..ea956a4791d0 100644
--- a/arch/arm/mach-snapdragon/of_fixup.c
+++ b/arch/arm/mach-snapdragon/of_fixup.c
@@ -86,13 +86,13 @@ static int fixup_qcom_dwc3(struct device_node *glue_np)
}
/* Overwrite "phy-names" to only contain a single entry */
- ret = of_write_prop(dwc3, "phy-names", strlen("usb2-phy"), "usb2-phy");
+ ret = of_write_prop(dwc3, "phy-names", strlen("usb2-phy") + 1,
"usb2-phy");
if (ret) {
log_err("Failed to overwrite 'phy-names' property: %d\n", ret);
return ret;
}
- ret = of_write_prop(dwc3, "maximum-speed", strlen("high-speed"), "high-speed");
+ ret = of_write_prop(dwc3, "maximum-speed", strlen("high-speed") + 1,
"high-speed");
if (ret) {
log_err("Failed to set 'maximum-speed' property: %d\n", ret);
return ret;
--
Caleb (they/them)
[PATCH 5/6] video: support FRIDA FRD400B25025-A-CTK
[backport from Linux commits 9b26d5c044d6a29ebfb1845408e0f2a7c5f89818 and 219a1f49094f50bf9c382830d06149e677f76bed] The patch adds the FRIDA FRD400B25025-A-CTK panel, which belongs to the Novatek NT35510-based panel family. Signed-off-by: Dario Binacchi --- drivers/video/Kconfig |7 + drivers/video/Makefile |1 + drivers/video/novatek-nt35510.c | 1253 +++ 3 files changed, 1261 insertions(+) create mode 100644 drivers/video/novatek-nt35510.c diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 3c3cebaacd02..76dc2d65a6d3 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -550,6 +550,13 @@ config VIDEO_LCD_HIMAX_HX8394 Say Y here if you want to enable support for Himax HX8394 dsi 4dl panel. +config VIDEO_LCD_NOVATEK_NT35510 + bool "Novatek NT35510 DSI LCD panel support" + select VIDEO_MIPI_DSI + help + Say Y here if you want to enable support for Novatek nt35510 + dsi panel. + config VIDEO_LCD_ORISETECH_OTM8009A bool "OTM8009A DSI LCD panel support" select VIDEO_MIPI_DSI diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 5a00438ce064..ff9c9e1c2512 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -59,6 +59,7 @@ obj-$(CONFIG_VIDEO_LCD_ENDEAVORU) += endeavoru-panel.o obj-$(CONFIG_VIDEO_LCD_HIMAX_HX8394) += himax-hx8394.o obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o obj-$(CONFIG_VIDEO_LCD_LG_LD070WX3) += lg-ld070wx3.o +obj-$(CONFIG_VIDEO_LCD_NOVATEK_NT35510) += novatek-nt35510.o obj-$(CONFIG_VIDEO_LCD_ORISETECH_OTM8009A) += orisetech_otm8009a.o obj-$(CONFIG_VIDEO_LCD_RAYDIUM_RM68200) += raydium-rm68200.o obj-$(CONFIG_VIDEO_LCD_RENESAS_R61307) += renesas-r61307.o diff --git a/drivers/video/novatek-nt35510.c b/drivers/video/novatek-nt35510.c new file mode 100644 index ..f3432939c0cb --- /dev/null +++ b/drivers/video/novatek-nt35510.c @@ -0,0 +1,1253 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025 Amarula Solutions, Dario Binacchi + * + * Inspired from the Linux kernel driver panel-novatek-nt35510.c + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define NT35510_CMD_CORRECT_GAMMA BIT(0) +#define NT35510_CMD_CONTROL_DISPLAY BIT(1) +#define NT35510_CMD_SETVCMOFF BIT(2) + +#define MCS_CMD_MAUCCTR0xF0 /* Manufacturer command enable */ +#define MCS_CMD_READ_ID1 0xDA +#define MCS_CMD_READ_ID2 0xDB +#define MCS_CMD_READ_ID3 0xDC +#define MCS_CMD_MTP_READ_SETTING 0xF8 /* Uncertain about name */ +#define MCS_CMD_MTP_READ_PARAM 0xFF /* Uncertain about name */ + +/* + * These manufacturer commands are available after we enable manufacturer + * command set (MCS) for page 0. + */ +#define NT35510_P0_DOPCTR 0xB1 +#define NT35510_P0_SDHDTCTR 0xB6 +#define NT35510_P0_GSEQCTR 0xB7 +#define NT35510_P0_SDEQCTR 0xB8 +#define NT35510_P0_SDVPCTR 0xBA +#define NT35510_P0_DPFRCTR1 0xBD +#define NT35510_P0_DPFRCTR2 0xBE +#define NT35510_P0_DPFRCTR3 0xBF +#define NT35510_P0_DPMCTR12 0xCC + +#define NT35510_P0_DOPCTR_LEN 2 +#define NT35510_P0_GSEQCTR_LEN 2 +#define NT35510_P0_SDEQCTR_LEN 4 +#define NT35510_P0_SDVPCTR_LEN 1 +#define NT35510_P0_DPFRCTR1_LEN 5 +#define NT35510_P0_DPFRCTR2_LEN 5 +#define NT35510_P0_DPFRCTR3_LEN 5 +#define NT35510_P0_DPMCTR12_LEN 3 + +#define NT35510_DOPCTR_0_RAMKP BIT(7) /* Contents kept in sleep */ +#define NT35510_DOPCTR_0_DSITE BIT(6) /* Enable TE signal */ +#define NT35510_DOPCTR_0_DSIG BIT(5) /* Enable generic read/write */ +#define NT35510_DOPCTR_0_DSIM BIT(4) /* Enable video mode on DSI */ +#define NT35510_DOPCTR_0_EOTP BIT(3) /* Support EoTP */ +#define NT35510_DOPCTR_0_N565 BIT(2) /* RGB or BGR pixel format */ +#define NT35510_DOPCTR_1_TW_PWR_SEL BIT(4) /* TE power selector */ +#define NT35510_DOPCTR_1_CRGB BIT(3) /* RGB or BGR byte order */ +#define NT35510_DOPCTR_1_CTB BIT(2) /* Vertical scanning direction */ +#define NT35510_DOPCTR_1_CRL BIT(1) /* Source driver data shift */ +#define NT35510_P0_SDVPCTR_PRG BIT(2) /* 0 = normal operation, 1 = VGLO */ +#define NT35510_P0_SDVPCTR_AVDD 0 /* source driver output = AVDD */ +#define NT35510_P0_SDVPCTR_OFFCOL 1 /* source driver output = off color */ +#define NT35510_P0_SDVPCTR_AVSS 2 /* source driver output = AVSS */ +#define NT35510_P0_SDVPCTR_HI_Z 3 /* source driver output = High impedance */ + +/* + * These manufacturer commands are available after we enable manufacturer + * command set (MCS) for page 1. + */ +#define NT35510_P1_SETAVDD 0xB0 +#define NT35510_P1_SETAVEE 0xB1 +#define NT35510_P1_SETVCL 0xB2 +#define NT35510_P1_SETVGH 0xB3 +#define NT35510_P1_SETVRGH 0xB4 +#define NT35510_P1_SETVGL 0xB5 +#define NT35510_P1_BT1CTR 0xB6 +#define NT35510_P1_BT2CTR 0xB7 +#define NT35510_P1_BT3CTR 0xB8 +#define NT35510_P1_BT4CTR 0xB9 /* VGH boosting times/freq */ +#define NT35510_P1_BT5CTR 0xBA +#define NT35510_P1_PFMCTR 0xBB +#def
[PATCH 1/4] clk/stub: add sdm845 rpmh clock
Necessary for UFS to successfully probe all clocks.
Signed-off-by: Caleb Connolly
---
drivers/clk/clk-stub.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/clk-stub.c b/drivers/clk/clk-stub.c
index
343fa5cd3fe1704c6bb15a8c9852b9b4e4990351..521ecfc5917b45f8ffaf2f25aabcc5abb4863cea
100644
--- a/drivers/clk/clk-stub.c
+++ b/drivers/clk/clk-stub.c
@@ -49,8 +49,9 @@ static struct clk_ops stub_clk_ops = {
};
static const struct udevice_id stub_clk_ids[] = {
{ .compatible = "qcom,rpmcc" },
+ { .compatible = "qcom,sdm845-rpmh-clk" },
{ .compatible = "qcom,sc7280-rpmh-clk" },
{ .compatible = "qcom,sm8150-rpmh-clk" },
{ .compatible = "qcom,sm8250-rpmh-clk" },
{ .compatible = "qcom,sm8550-rpmh-clk" },
--
2.49.0
[PATCH 0/4] Qualcomm: fix sdm845 clocks and enable fastboot
Fix clock init failures for USB and UFS on SDM845 devices, stub the RPMh clock controller, enable DM_USB_GADGET and fastboot support for all Qualcomm platforms supported by qcom_defconfig. Fastboot isn't super useful yet, but can be used for flashing MMC (either internal or sdcard). Depends on https://lore.kernel.org/u-boot/20250319-sdm845-usb-clocks-v1-1-ddea854f6...@samcday.com Depends on https://lore.kernel.org/u-boot/20250227094911.497219-2-rui.si...@linaro.org/ --- Caleb Connolly (4): clk/stub: add sdm845 rpmh clock clk/qcom: sdm845: add GCC_AGGRE_UFS_PHY_AXI_CLK mach-snapdragon: enable DM_USB_GADGET by default qcom_defconfig: enable fastboot arch/arm/Kconfig | 1 + configs/dragonboard410c_defconfig | 1 + configs/qcom_defconfig| 5 + drivers/clk/clk-stub.c| 1 + drivers/clk/qcom/clock-sdm845.c | 1 + 5 files changed, 9 insertions(+) --- base-commit: dcb6a5e7651f4a6cebfad4389119407e2a852783 Caleb Connolly
[PATCH 4/4] qcom_defconfig: enable fastboot
Enable fastboot support over USB, using MMC as the backend. This will be the internal eMMC on devices that have it, or the sdcard slot on devices with UFS (if available). We don't use a fixed address for the fastboot buffer because it's allocated at runtime per-board. Entering fastboot mode should be done by executing "run fastboot" or manually running: fastboot -l $fastboot_addr_r usb 0 Signed-off-by: Caleb Connolly --- configs/qcom_defconfig | 5 + 1 file changed, 5 insertions(+) diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index ba4d38d100e053e3708ee2623bf3530787b6b94f..f5c005d9c4093e4902b05213ab2f54c8ca70208a 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -61,8 +61,13 @@ CONFIG_CLK_QCOM_SC7280=y CONFIG_CLK_QCOM_X1E80100=y CONFIG_DFU_MMC=y CONFIG_DFU_SCSI=y CONFIG_SYS_DFU_DATA_BUF_SIZE=0x20 +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x0 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_MMC_USER_SUPPORT=y CONFIG_MSM_GPIO=y CONFIG_QCOM_PMIC_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_QUP=y -- 2.49.0
[PATCH 2/4] clk/qcom: sdm845: add GCC_AGGRE_UFS_PHY_AXI_CLK
Missing for UFS.
Signed-off-by: Caleb Connolly
---
drivers/clk/qcom/clock-sdm845.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c
index
7fd875e55d5443f170801172a373e0405041e1d1..5c8702ef2fe00a46a30dbdfddd6e649d20465006
100644
--- a/drivers/clk/qcom/clock-sdm845.c
+++ b/drivers/clk/qcom/clock-sdm845.c
@@ -113,8 +113,9 @@ static const struct gate_clk sdm845_clks[] = {
GATE_CLK(GCC_UFS_CARD_RX_SYMBOL_1_CLK, 0x750a8, 0x0001),
GATE_CLK(GCC_UFS_CARD_TX_SYMBOL_0_CLK, 0x75014, 0x0001),
GATE_CLK(GCC_UFS_CARD_UNIPRO_CORE_CLK, 0x75054, 0x0001),
GATE_CLK(GCC_UFS_MEM_CLKREF_CLK,0x8c000, 0x0001),
+ GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x82024, 0x0001),
GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x77010, 0x0001),
GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x7700c, 0x0001),
GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x77058, 0x0001),
GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x7708c, 0x0001),
--
2.49.0
[resend v3 04/12] drivers: Enabled Kconfig and Makefile for i3c support
From: Dinesh Maniyam Add new i3c driver to U-Boot drivers. Signed-off-by: Dinesh Maniyam --- MAINTAINERS | 7 +++ drivers/Kconfig | 2 ++ drivers/Makefile | 1 + drivers/i3c/Kconfig | 16 drivers/i3c/Makefile | 3 +++ 5 files changed, 29 insertions(+) create mode 100644 drivers/i3c/Kconfig create mode 100644 drivers/i3c/Makefile diff --git a/MAINTAINERS b/MAINTAINERS index 0315c606744..6dcc566eb72 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1230,6 +1230,13 @@ S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-i2c.git F: drivers/i2c/ +I3C +M: Dinesh +S: Maintained +T: git https://source.denx.de/u-boot/u-boot.git +F: cmd/i3c.c +F: drivers/i3c/ + KWBIMAGE / KWBOOT TOOLS M: Pali Rohár M: Marek Behún diff --git a/drivers/Kconfig b/drivers/Kconfig index a073230c26d..0b0c610e629 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -56,6 +56,8 @@ source "drivers/hwspinlock/Kconfig" source "drivers/i2c/Kconfig" +source "drivers/i3c/Kconfig" + source "drivers/input/Kconfig" source "drivers/iommu/Kconfig" diff --git a/drivers/Makefile b/drivers/Makefile index 0e1f58c515b..fd155835ab6 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_$(PHASE_)DRIVERS_MISC) += misc/ obj-$(CONFIG_$(PHASE_)SYSRESET) += sysreset/ obj-$(CONFIG_$(PHASE_)FIRMWARE) +=firmware/ obj-$(CONFIG_$(PHASE_)I2C) += i2c/ +obj-$(CONFIG_$(PHASE_)I3C) += i3c/ obj-$(CONFIG_$(PHASE_)INPUT) += input/ obj-$(CONFIG_$(PHASE_)LED) += led/ obj-$(CONFIG_$(PHASE_)MMC) += mmc/ diff --git a/drivers/i3c/Kconfig b/drivers/i3c/Kconfig new file mode 100644 index 000..fa68612787b --- /dev/null +++ b/drivers/i3c/Kconfig @@ -0,0 +1,16 @@ +menuconfig I3C + tristate "I3C support" + select I2C + help + I3C is a serial protocol standardized by the MIPI alliance. + + It's supposed to be backward compatible with I2C while providing + support for high speed transfers and native interrupt support + without the need for extra pins. + + The I3C protocol also standardizes the slave device types and is + mainly designed to communicate with sensors. + + If you want I3C support, you should say Y here and also to the + specific driver for your bus adapter(s) below. + diff --git a/drivers/i3c/Makefile b/drivers/i3c/Makefile new file mode 100644 index 000..5bb44a8d64f --- /dev/null +++ b/drivers/i3c/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y := i3c-uclass.o device.o master.o -- 2.26.2
[PATCH 0/6] Support NT35510 panel controller on stm32f769i-disco board
The series, inspired by some of my patches already merged into Linux, adds support for the Novatek NT35510 panel on the stm32f769i-disco board. Indeed, the MB1166 board comes in different hardware revisions. The MB1166-A09 is utilizing a NT35510 panel controller while prior versions are utilizing an OTM8009a controller. Dario Binacchi (6): ARM: dts: stm32: add DSI support on stm32f769 ARM: dts: stm32: rename mmc_vcard to vcc-3v3 on stm32f769-disco ARM: dts: stm32: add display support on stm32f769-disco ARM: dts: add stm32f769-disco-mb1166-reva09 video: support FRIDA FRD400B25025-A-CTK board: stm32f769-disco: support FRD400B25025-A-CTK display arch/arm/dts/Makefile |1 + .../stm32f769-disco-mb1166-reva09-u-boot.dtsi |6 + .../arm/dts/stm32f769-disco-mb1166-reva09.dts | 13 + arch/arm/dts/stm32f769-disco-u-boot.dtsi | 53 +- arch/arm/dts/stm32f769-disco.dts | 66 +- arch/arm/dts/stm32f769.dtsi | 20 + configs/stm32f769-disco_defconfig |2 + configs/stm32f769-disco_spl_defconfig |2 + drivers/video/Kconfig |7 + drivers/video/Makefile|1 + drivers/video/novatek-nt35510.c | 1253 + 11 files changed, 1374 insertions(+), 50 deletions(-) create mode 100644 arch/arm/dts/stm32f769-disco-mb1166-reva09-u-boot.dtsi create mode 100644 arch/arm/dts/stm32f769-disco-mb1166-reva09.dts create mode 100644 arch/arm/dts/stm32f769.dtsi create mode 100644 drivers/video/novatek-nt35510.c -- 2.43.0
Re: [PATCH V4 4/7] cpu: imx8_cpu: Print Speed grade if IMX_TMU.
On 3/25/25 3:54 AM, Adam Ford wrote: Much of the data that is display by imx8_cpu.c is also displayed from arch/arm/mach-imx/cpu.c, except the temperature grade and active temperature are only displayed when SoC is an i.MX9. Since IMX9 now implies IMX_TMU, change this to check for IMX_TMU in the same way it's done in mach-imx/cpu.c to enable displaying this information for any SoC with either of this config enabled. Since additional text may appear due to this commit, remove the extra space in the message displaying the temperature grade. Before: CPU: NXP i.MX8MP Rev1.1 A53 at 1200 MHz Model: Beacon EmbeddedWorks i.MX8MPlus Development kit After: CPU: NXP i.MX8MP Rev1.1 A53 at 1200 MHz CPU: Industrial temperature grade (-40C to 105C) at 28C Model: Beacon EmbeddedWorks i.MX8MPlus Development kit Signed-off-by: Adam Ford Please drop the fullstop at the end of Subject and then add Reviewed-by: Marek Vasut To the whole series. Thanks !
[PATCH 1/6] ARM: dts: stm32: add DSI support on stm32f769
[backport from Linux commit a995fd2e8b3c6defd1dcdd3fb350c224e41ea1d0]
Add support for MIPI DSI Host controller. Since MIPI DSI is not
available on stm32f746, the patch adds the "stm32f769.dtsi" file
containing the dsi node inside.
Signed-off-by: Dario Binacchi
---
arch/arm/dts/stm32f769-disco-u-boot.dtsi | 41 +++-
arch/arm/dts/stm32f769-disco.dts | 2 +-
arch/arm/dts/stm32f769.dtsi | 20
3 files changed, 39 insertions(+), 24 deletions(-)
create mode 100644 arch/arm/dts/stm32f769.dtsi
diff --git a/arch/arm/dts/stm32f769-disco-u-boot.dtsi
b/arch/arm/dts/stm32f769-disco-u-boot.dtsi
index add55c96e21f..c5ae753debe6 100644
--- a/arch/arm/dts/stm32f769-disco-u-boot.dtsi
+++ b/arch/arm/dts/stm32f769-disco-u-boot.dtsi
@@ -44,30 +44,25 @@
};
};
};
+};
- soc {
- dsi: dsi@40016c00 {
- compatible = "st,stm32-dsi";
- reg = <0x40016c00 0x800>;
- resets = <&rcc STM32F7_APB2_RESET(DSI)>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(DSI)>,
- <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>,
- <&clk_hse>;
- clock-names = "pclk", "px_clk", "ref";
- bootph-all;
- status = "okay";
-
- ports {
- port@0 {
- dsi_out: endpoint {
- remote-endpoint = <&panel_in>;
- };
- };
- port@1 {
- dsi_in: endpoint {
- remote-endpoint = <&dp_out>;
- };
- };
+&dsi {
+ clocks = <&rcc 0 STM32F7_APB2_CLOCK(DSI)>,
+<&rcc 0 STM32F7_APB2_CLOCK(LTDC)>,
+<&clk_hse>;
+ clock-names = "pclk", "px_clk", "ref";
+ bootph-all;
+ status = "okay";
+
+ ports {
+ port@0 {
+ dsi_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ port@1 {
+ dsi_in: endpoint {
+ remote-endpoint = <&dp_out>;
};
};
};
diff --git a/arch/arm/dts/stm32f769-disco.dts b/arch/arm/dts/stm32f769-disco.dts
index d63cd2ba7eb4..ad1b442055e1 100644
--- a/arch/arm/dts/stm32f769-disco.dts
+++ b/arch/arm/dts/stm32f769-disco.dts
@@ -5,7 +5,7 @@
*/
/dts-v1/;
-#include "stm32f746.dtsi"
+#include "stm32f769.dtsi"
#include "stm32f769-pinctrl.dtsi"
#include
#include
diff --git a/arch/arm/dts/stm32f769.dtsi b/arch/arm/dts/stm32f769.dtsi
new file mode 100644
index ..4e7d9032149c
--- /dev/null
+++ b/arch/arm/dts/stm32f769.dtsi
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023 Dario Binacchi
+ */
+
+#include "stm32f746.dtsi"
+
+/ {
+ soc {
+ dsi: dsi@40016c00 {
+ compatible = "st,stm32-dsi";
+ reg = <0x40016c00 0x800>;
+ clocks = <&rcc 1 CLK_F769_DSI>, <&clk_hse>;
+ clock-names = "pclk", "ref";
+ resets = <&rcc STM32F7_APB2_RESET(DSI)>;
+ reset-names = "apb";
+ status = "disabled";
+ };
+ };
+};
--
2.43.0
[ANN] U-Boot v2025.04-rc5 released
Hey all, So it's release day and I have tagged and pushed things out. This will be merged to -next shortly. One thing to note is that just today a bug was reported due to a missing 'fallthrough;' line and in turn we need to fix that in a number of places and ensure it doesn't return. This will happen between now and the release as I think it's clear enough. While we have been having regular meetings after an -rc release, I have assorted personal appointments this week and need to reschedule for next week instead. Repeating what I said on the -rc3 release, I've been looking in to seeing how we could get modern project governance setup and some umbrella organization to handle financial matters, etc. To that end, I've been talking with the Software Freedom Conservancy (https://sfconservancy.org/). I continue to need to post a bit longer of an email explaining my thoughts and looking for volunteers to help with organization. In terms of a changelog, git log --merges v2025.04-rc4..v2025.04-rc5 As always, more details in pull requests (or the tags referenced by them) will result in more details here. I plan to have the final release will be 07 April 2025. Thanks all! -- Tom signature.asc Description: PGP signature
Re: [PATCH] board: beacon: imx8mp: Fix GIC clock for Overdrive mode
On Mon, Mar 24, 2025 at 6:34 PM Fabio Estevam wrote:
>
> Hi Adam,
>
> On Mon, Mar 24, 2025 at 8:27 PM Adam Ford wrote:
> >
> > There is a config option to run the PMIC at nominal voltages
> > which is not enabled on the i.MX8MP Beacon kit, so it the PMIC
> > runs at overdrive voltages. Unfortuately, the check for this
> > condition to set the GIC clock parent and rate is backwards from
> > what it should be, and accidentally sets the GIC clock to nominal
> > if the PMIC is in overdrive, and sets the GIC clock to overdrive
> > if the PMIC is in nominal. Fix this by inverting the logic on the
> > check.
> >
> > Fixes: ab53bd43dbde ("arm64: imx: Add support for imx8mp-beacon-kit")
> > Signed-off-by: Adam Ford
>
> Is this U-Boot 2025.04 material, or can it wait until 2025.07?
It's been wrong since the beginning, and I only ran into it by
accident, so it's not obvious. It can wait until 2025.07.
thanks
adam
[PATCH] board: beacon: imx8mp: Fix GIC clock for Overdrive mode
There is a config option to run the PMIC at nominal voltages
which is not enabled on the i.MX8MP Beacon kit, so it the PMIC
runs at overdrive voltages. Unfortuately, the check for this
condition to set the GIC clock parent and rate is backwards from
what it should be, and accidentally sets the GIC clock to nominal
if the PMIC is in overdrive, and sets the GIC clock to overdrive
if the PMIC is in nominal. Fix this by inverting the logic on the
check.
Fixes: ab53bd43dbde ("arm64: imx: Add support for imx8mp-beacon-kit")
Signed-off-by: Adam Ford
diff --git a/board/beacon/imx8mp/spl.c b/board/beacon/imx8mp/spl.c
index 6b357d90a3f..027fae38278 100644
--- a/board/beacon/imx8mp/spl.c
+++ b/board/beacon/imx8mp/spl.c
@@ -50,7 +50,7 @@ void spl_board_init(void)
* setting done. Default is 400Mhz (system_pll1_800m with div = 2)
* set by ROM for ND VDD_SOC
*/
- if (IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV)) {
+ if (!IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV)) {
clock_enable(CCGR_GIC, 0);
clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON |
CLK_ROOT_SOURCE_SEL(5));
clock_enable(CCGR_GIC, 1);
--
2.45.2
[PATCH V4 5/7] imx: imx8m: Imply CPU_IMX by default
The imx8_cpu driver is a CPU Driver that supports the i.MX8M family, and when it is enabled, it acts as an alternative to arch/arm/mach-imx/cpu.c, but the imx8_cpu supports the driver model where cpu.c does not. Imply this newer driver by default. Signed-off-by: Adam Ford --- arch/arm/mach-imx/imx8m/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 8ee699a343c..31f2f003d35 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -8,6 +8,8 @@ config IMX8M select LTO select ROM_UNIFIED_SECTIONS select ARMV8_CRYPTO + imply CPU + imply CPU_IMX imply IMX_TMU config IMX8MQ -- 2.45.2
Re: [PATCH] efi_loader: remove EFI_BOUNCE_BUFFER
On 17.03.25 14:38, Ilias Apalodimas wrote:
%s/EFI_BOUNCE_BUFFER/CONFIG_EFI_LOADER_BOUNCE_BUFFER/
The EFI subsystem defines its own bounce buffer for devices that
can't transfer data > 4GB. U-Boot already has a generic BOUNCE_BUFFER
which can be reused instead of defining another symbol.
The only limitation for EFI is that we don't know how big the file a user
chooses to transfer is and as a result we can't depend on allocating the
memory from the malloc area, which can prove too small.
So allocate an EFI buffer of the correct size and pass it to the DM,
which already supports bounce buffering via bounce_buffer_start_extalign()
Looking at
if (IS_ENABLED(CONFIG_BOUNCE_BUFFER) && desc->bb) {
in drivers/block/blk-uclass.c the bounce buffer has to be explicitly
enabled by the device driver. Only the scsi drivers sets bb = true.
Cf. 81bd22e935dc ("rockchip: block: blk-uclass: add bounce buffer flag
to blk_desc")
Which device-drivers of the boards mentioned below do actually need
bounce buffering?
Best regards
Heinrich
Signed-off-by: Ilias Apalodimas
---
arch/arm/Kconfig | 8 ++
configs/ls1028aqds_tfa_SECURE_BOOT_defconfig | 1 -
configs/ls1028aqds_tfa_defconfig | 1 -
configs/ls1028aqds_tfa_lpuart_defconfig | 1 -
configs/ls1028ardb_tfa_SECURE_BOOT_defconfig | 1 -
configs/ls1028ardb_tfa_defconfig | 1 -
configs/ls1043ardb_tfa_SECURE_BOOT_defconfig | 1 -
configs/ls1043ardb_tfa_defconfig | 1 -
configs/ls1046ardb_tfa_SECURE_BOOT_defconfig | 1 -
configs/ls1046ardb_tfa_defconfig | 1 -
configs/ls1088aqds_tfa_defconfig | 1 -
configs/ls1088ardb_tfa_SECURE_BOOT_defconfig | 1 -
configs/ls1088ardb_tfa_defconfig | 1 -
configs/ls2088aqds_tfa_defconfig | 1 -
configs/ls2088ardb_tfa_SECURE_BOOT_defconfig | 1 -
configs/ls2088ardb_tfa_defconfig | 1 -
configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 1 -
configs/lx2160aqds_tfa_defconfig | 1 -
configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 1 -
configs/lx2160ardb_tfa_defconfig | 1 -
configs/lx2160ardb_tfa_stmm_defconfig | 1 -
configs/lx2162aqds_tfa_SECURE_BOOT_defconfig | 1 -
configs/lx2162aqds_tfa_defconfig | 1 -
.../lx2162aqds_tfa_verified_boot_defconfig| 1 -
configs/ten64_tfa_defconfig | 1 -
include/efi_loader.h | 4 -
lib/efi_loader/Kconfig| 7 --
lib/efi_loader/efi_disk.c | 78 +++
lib/efi_loader/efi_memory.c | 16
29 files changed, 36 insertions(+), 101 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index cf08fe63f1e7..bb946e69254c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1417,6 +1417,7 @@ config TARGET_LS2080A_EMU
select ARCH_LS2080A
select ARM64
select ARMV8_MULTIENTRY
+ select BOUNCE_BUFFER
select FSL_DDR_SYNC_REFRESH
select GPIO_EXTRA_HEADER
help
@@ -1432,6 +1433,7 @@ config TARGET_LS1088AQDS
select ARMV8_MULTIENTRY
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
+ select BOUNCE_BUFFER
select GPIO_EXTRA_HEADER
select SUPPORT_SPL
select FSL_DDR_INTERACTIVE if !SD_BOOT
@@ -1448,6 +1450,7 @@ config TARGET_LS2080AQDS
select ARMV8_MULTIENTRY
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
+ select BOUNCE_BUFFER
select GPIO_EXTRA_HEADER
select SUPPORT_SPL
imply SCSI
@@ -1467,6 +1470,7 @@ config TARGET_LS2080ARDB
select ARMV8_MULTIENTRY
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
+ select BOUNCE_BUFFER
select SUPPORT_SPL
select FSL_DDR_BIST
select FSL_DDR_INTERACTIVE if !SPL
@@ -1485,6 +1489,7 @@ config TARGET_LS2081ARDB
select ARM64
select ARMV8_MULTIENTRY
select BOARD_LATE_INIT
+ select BOUNCE_BUFFER
select GPIO_EXTRA_HEADER
select SUPPORT_SPL
help
@@ -1500,6 +1505,7 @@ config TARGET_LX2160ARDB
select ARMV8_MULTIENTRY
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
+ select BOUNCE_BUFFER
select GPIO_EXTRA_HEADER
help
Support for NXP LX2160ARDB platform.
@@ -1514,6 +1520,7 @@ config TARGET_LX2160AQDS
select ARMV8_MULTIENTRY
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
+ select BOUNCE_BUFFER
select GPIO_EXTRA_HEADER
help
Support for NXP LX2160AQDS platform.
@@ -1529,6 +1536,7 @@ config TARGET_LX2162AQDS
select ARMV8_MULTIENTRY
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
+ select BOUNCE_BUFFER
select GPIO_EXTRA_HEADER
help
Support for NXP LX2162AQDS platform.
diff --git a/config
Re: usb:composite: data abort on second ums launch
On Mon, Mar 24, 2025 at 3:12 PM Marek Vasut wrote: > Can you reproduce this on u-boot/master too ? Yes I can reproduce it on master 2025.04-244e61f, since fsg init/deinit code are the same.
Re: [PATCH 0/4] Support UART over MicroSD slot on Transformer T20
Hello Thanks for quick response. I know UARTD is the dedicated UART for debugging on TF101, but exposing UART over microSD is a handy trick useful for development. As I'm doing development on this tablet (bringing U-Boot's UEFI support and latest Linux), and also still using the device on old OS I'd like to avoid disassembling and reassembling it over and over again. Others too may find the feature useful e. g. to avoid having to solder which requires specialized equipment, skills and is potentially dangerous for the board. Also, there already seems to be support for that on Sunxi platforms through CONFIG_UART0_PORT_F. Apart from pinmux changes, would it be acceptable to include an option to allow switching UARTA mux to SDB/SDD (currently this has to be selected from board's Kconfig file). Doing so would allow to enable UART over microSD without patching U-Boot's source without changing any existing configuration. Then I would keep DTS overlays and config changes local. Also, today, after running U-Boot with debug enabled, I discovered some failed assertions in pinmux code probably caused by my changes, I will get that fixed before sending v2. Best regards Artur Kowalski W dniu 18.03.2025 o 09:54, Svyatoslav Ryhel pisze: вт, 18 бер. 2025 р. о 10:31 Artur Kowalski пише: The first patch in the series brings general pinmux support for exposing UART over SDB/SDD pins on T20. The following patches bring support Transformer T20 allowing to enable UART over uSD by setting CONFIG_TEGRA_ENABLE_UARTA=y CONFIG_DEVICE_TREE_INCLUDES="tegra20-asus-transformer-uart-usd.dtsi" Similarily, support for UART over uSD could be brought to Ventana which has uSD on the same pins as TF101, and other Ventana-based boards. Hey there, thank you for looking into U-Boot for Tegra. If something I will say hurts or offends you, I am sorry it was not intentional. Anyway, apart funcmux changes, all other changes you propose are redundant. Asus dedicated uart for logging and console is UARTD any other uart configuration must not be added since it will disrupt existing configuration. If you need uart and cannot resolve an issue without it you can always solder to uart-d or locally mux sd to uart console fix your issue and remove it. Uart is not intended way to interact with Asus TF101 and doesn't need to be exposed, panel and fastboot console are and can be used to resolve most of issues. Best regards, Svyatoslav R. Artur Kowalski (4): tegra: add funcmux for exposing UART over uSD slot on Tegra 20 tegra: respect CONFIG_TEGRA_ENABLE_UART* options on Transformer T20 ARM: tegra: expose UART-A over uSD on Transformer T20 board: asus: transformer: add DTSI file for enabling UART over uSD slot .../tegra20-asus-transformer-uart-usd.dtsi| 31 +++ arch/arm/include/asm/arch-tegra20/funcmux.h | 1 + arch/arm/mach-tegra/board.c | 4 ++- arch/arm/mach-tegra/tegra20/Kconfig | 4 +++ drivers/pinctrl/tegra/funcmux-tegra20.c | 9 +- include/configs/transformer-t20.h | 10 ++ 6 files changed, 57 insertions(+), 2 deletions(-) create mode 100644 arch/arm/dts/tegra20-asus-transformer-uart-usd.dtsi -- 2.48.1
Re: usb:composite: data abort on second ums launch
On Mon, Mar 24, 2025 at 6:21 PM Mattijs Korpershoek wrote: > I've tried to reproduce this on master (2025.04-rc4-g244e61fbb7f5) and I > don't reproduce this with the VIM3 board using > khadas-vim3_android_ab_defconfig: > > I'll try to understand why it's behaving differently between the > sam9x60-curiosity and the vim3. Thank you for your test, I think it's because VIM3 is a large SoC with plenty of RAM (SYS_MALLOC_LEN=0x0800) while SAM9X60 is much smaller (SYS_MALLOC_LEN=0x81000). Each time when ums is called 2*FSG_BUFLEN, 256kB buffer is allocated and it seems not freed as fsg_common_release() is not called. Zixun
Re: [PATCH] sunxi: mmc: Improve reset procedure
On Sun, 9 Mar 2025 07:12:41 +0100
Jernej Skrabec wrote:
Hi Jernej,
many thanks for your investigation and this fix here! Not having
working eMMC access was a major annoyance for those TV boxes, and this
indeed seems to be fixed now, judging by my experiments. Also checked
boot partition access, works fine (though data partitions seem to take
precedence on most devices).
> Cards should always be reset and threshold set. This fixes eMMC on H616.
>
> Signed-off-by: Jernej Skrabec
Acked-by: Andre Przywara
Cheers,
Andre
> ---
> drivers/mmc/sunxi_mmc.c | 28 ++--
> drivers/mmc/sunxi_mmc.h | 15 +--
> 2 files changed, 35 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
> index 0b56d1405bee..335def4b9738 100644
> --- a/drivers/mmc/sunxi_mmc.c
> +++ b/drivers/mmc/sunxi_mmc.c
> @@ -442,6 +442,26 @@ out:
> return error;
> }
>
> +static void sunxi_mmc_reset(struct sunxi_mmc *regs)
> +{
> + /* Reset controller */
> + writel(SUNXI_MMC_GCTRL_RESET, ®s->gctrl);
> + udelay(1000);
> +
> + if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) ||
> IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) {
> + /* Reset card */
> + writel(SUNXI_MMC_HWRST_ASSERT, ®s->hwrst);
> + udelay(10);
> + writel(SUNXI_MMC_HWRST_DEASSERT, ®s->hwrst);
> + udelay(300);
> +
> + /* Setup FIFO R/W threshold. Needed on H616. */
> + writel(SUNXI_MMC_THLDC_READ_THLD(512) |
> +SUNXI_MMC_THLDC_WRITE_EN |
> +SUNXI_MMC_THLDC_READ_EN, ®s->thldc);
> + }
> +}
> +
> /* non-DM code here is used by the (ARM) SPL only */
>
> #if !CONFIG_IS_ENABLED(DM_MMC)
> @@ -489,9 +509,7 @@ static int sunxi_mmc_core_init(struct mmc *mmc)
> {
> struct sunxi_mmc_priv *priv = mmc->priv;
>
> - /* Reset controller */
> - writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
> - udelay(1000);
> + sunxi_mmc_reset(priv->reg);
>
> return 0;
> }
> @@ -684,9 +702,7 @@ static int sunxi_mmc_probe(struct udevice *dev)
>
> upriv->mmc = &plat->mmc;
>
> - /* Reset controller */
> - writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
> - udelay(1000);
> + sunxi_mmc_reset(priv->reg);
>
> return 0;
> }
> diff --git a/drivers/mmc/sunxi_mmc.h b/drivers/mmc/sunxi_mmc.h
> index f4ae5a790c87..9d55904c213c 100644
> --- a/drivers/mmc/sunxi_mmc.h
> +++ b/drivers/mmc/sunxi_mmc.h
> @@ -37,7 +37,9 @@ struct sunxi_mmc {
> u32 res0; /* 0x54 reserved */
> u32 a12a; /* 0x58 Auto command 12 argument */
> u32 ntsr; /* 0x5c New timing set register */
> - u32 res1[8];
> + u32 res1[6];
> + u32 hwrst; /* 0x78 Hardware Reset */
> + u32 res5;
> u32 dmac; /* 0x80 internal DMA control */
> u32 dlba; /* 0x84 internal DMA descr list base address */
> u32 idst; /* 0x88 internal DMA status */
> @@ -46,7 +48,8 @@ struct sunxi_mmc {
> u32 cbda; /* 0x94 */
> u32 res2[26];
> #if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) ||
> defined(CONFIG_SUNXI_GEN_NCAT2)
> - u32 res3[17];
> + u32 thldc; /* 0x100 Threshold control */
> + u32 res3[16];
> u32 samp_dl;
> u32 res4[46];
> #endif
> @@ -123,6 +126,9 @@ struct sunxi_mmc {
>
> #define SUNXI_MMC_NTSR_MODE_SEL_NEW (0x1 << 31)
>
> +#define SUNXI_MMC_HWRST_ASSERT (0x0 << 0)
> +#define SUNXI_MMC_HWRST_DEASSERT (0x1 << 0)
> +
> #define SUNXI_MMC_IDMAC_RESET(0x1 << 0)
> #define SUNXI_MMC_IDMAC_FIXBURST (0x1 << 1)
> #define SUNXI_MMC_IDMAC_ENABLE (0x1 << 7)
> @@ -133,6 +139,11 @@ struct sunxi_mmc {
> #define SUNXI_MMC_COMMON_CLK_GATE(1 << 16)
> #define SUNXI_MMC_COMMON_RESET (1 << 18)
>
> +#define SUNXI_MMC_THLDC_READ_EN (0x1 << 0)
> +#define SUNXI_MMC_THLDC_BSY_CLR_INT_EN (0x1 << 1)
> +#define SUNXI_MMC_THLDC_WRITE_EN (0x1 << 2)
> +#define SUNXI_MMC_THLDC_READ_THLD(x) (((x) & 0xfff) << 16)
> +
> #define SUNXI_MMC_CAL_DL_SW_EN (0x1 << 7)
>
> #endif /* _SUNXI_MMC_H */
[PATCH V4 1/7] imx: imx9: Imply IMX_TMU
If the CPU Information is displayed from imx8_cpu, it displays the cpu temperature grade and operating temperature if CONFIG_IMX9 is defined. This behavior is similar to what happens arch/arm/mach-imx/cpu.c except that the latter checks for CONFIG_IMX_THERMAL or CONFIG_IMX_TMU. In preparation to make imx8_cpu act like the previous implementation for any CPU, make IMX9 imply IMX_TMU, so it will be always displayed unless a user decides to disable it. Signed-off-by: Adam Ford --- arch/arm/mach-imx/imx9/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig index 49220c0955e..c3e758e103a 100644 --- a/arch/arm/mach-imx/imx9/Kconfig +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -10,6 +10,7 @@ config IMX9 select BINMAN select HAS_CAAM select ROM_UNIFIED_SECTIONS + imply IMX_TMU config IMX93 bool -- 2.45.2
[PATCH V4 2/7] cpu: imx8_cpu: Expand get_imx_type_str list of supported CPUs
The imx8_cpu is capable of running on IMX8, IMX8M, and IMX9
families, but the CPU list is limited on the 8M variants. Expand
this list to show more variants and their respective names.
Signed-off-by: Adam Ford
---
drivers/cpu/imx8_cpu.c | 44 +++---
1 file changed, 41 insertions(+), 3 deletions(-)
diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c
index 53d31b3c0bf..39b3c194131 100644
--- a/drivers/cpu/imx8_cpu.c
+++ b/drivers/cpu/imx8_cpu.c
@@ -35,11 +35,49 @@ static const char *get_imx_type_str(u32 imxtype)
{
switch (imxtype) {
case MXC_CPU_IMX8MM:
- return "8MM";
+ return "8MMQ"; /* Quad-core version of the imx8mm */
+ case MXC_CPU_IMX8MML:
+ return "8MMQL"; /* Quad-core Lite version of the imx8mm */
+ case MXC_CPU_IMX8MMD:
+ return "8MMD"; /* Dual-core version of the imx8mm */
+ case MXC_CPU_IMX8MMDL:
+ return "8MMDL"; /* Dual-core Lite version of the imx8mm */
+ case MXC_CPU_IMX8MMS:
+ return "8MMS"; /* Single-core version of the imx8mm */
+ case MXC_CPU_IMX8MMSL:
+ return "8MMSL"; /* Single-core Lite version of the imx8mm */
case MXC_CPU_IMX8MN:
- return "8MN";
+ return "8MNano Quad"; /* Quad-core version */
+ case MXC_CPU_IMX8MND:
+ return "8MNano Dual"; /* Dual-core version */
+ case MXC_CPU_IMX8MNS:
+ return "8MNano Solo"; /* Single-core version */
+ case MXC_CPU_IMX8MNL:
+ return "8MNano QuadLite"; /* Quad-core Lite version */
+ case MXC_CPU_IMX8MNDL:
+ return "8MNano DualLite"; /* Dual-core Lite version */
+ case MXC_CPU_IMX8MNSL:
+ return "8MNano SoloLite";/* Single-core Lite version of the
imx8mn */
+ case MXC_CPU_IMX8MNUQ:
+ return "8MNano UltraLite Quad";/* Quad-core UltraLite version
of the imx8mn */
+ case MXC_CPU_IMX8MNUD:
+ return "8MNano UltraLite Dual";/* Dual-core UltraLite version
of the imx8mn */
+ case MXC_CPU_IMX8MNUS:
+ return "8MNano UltraLite Solo";/* Single-core UltraLite version
of the imx8mn */
case MXC_CPU_IMX8MP:
- return "8MP";
+ return "8MP[8]";/* Quad-core version of the imx8mp */
+ case MXC_CPU_IMX8MPD:
+ return "8MP Dual[3]"; /* Dual-core version of the imx8mp */
+ case MXC_CPU_IMX8MPL:
+ return "8MP Lite[4]"; /* Quad-core Lite version of the imx8mp
*/
+ case MXC_CPU_IMX8MP6:
+ return "8MP[6]";/* Quad-core version of the imx8mp, NPU
fused */
+ case MXC_CPU_IMX8MQ:
+ return "8MQ"; /* Quad-core version of the imx8mq */
+ case MXC_CPU_IMX8MQL:
+ return "8MQLite"; /* Quad-core Lite version of the imx8mq
*/
+ case MXC_CPU_IMX8MD:
+ return "8MD"; /* Dual-core version of the imx8mq */
case MXC_CPU_IMX8QXP:
case MXC_CPU_IMX8QXP_A0:
return "8QXP";
--
2.45.2
[PATCH V4 4/7] cpu: imx8_cpu: Print Speed grade if IMX_TMU.
Much of the data that is display by imx8_cpu.c is also displayed from
arch/arm/mach-imx/cpu.c, except the temperature grade and active
temperature are only displayed when SoC is an i.MX9. Since IMX9 now
implies IMX_TMU, change this to check for IMX_TMU in the same way
it's done in mach-imx/cpu.c to enable displaying this information
for any SoC with either of this config enabled.
Since additional text may appear due to this commit, remove
the extra space in the message displaying the temperature
grade.
Before:
CPU: NXP i.MX8MP Rev1.1 A53 at 1200 MHz
Model: Beacon EmbeddedWorks i.MX8MPlus Development kit
After:
CPU: NXP i.MX8MP Rev1.1 A53 at 1200 MHz
CPU: Industrial temperature grade (-40C to 105C) at 28C
Model: Beacon EmbeddedWorks i.MX8MPlus Development kit
Signed-off-by: Adam Ford
---
drivers/cpu/imx8_cpu.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c
index 39b3c194131..4e1eccaa5b0 100644
--- a/drivers/cpu/imx8_cpu.c
+++ b/drivers/cpu/imx8_cpu.c
@@ -215,19 +215,19 @@ static int cpu_imx_get_desc(const struct udevice *dev,
char *buf, int size)
ret = snprintf(buf, size, "NXP i.MX%s Rev%s %s at %u MHz",
plat->type, plat->rev, plat->name, plat->freq_mhz);
- if (IS_ENABLED(CONFIG_IMX9)) {
+ if (IS_ENABLED(CONFIG_IMX_TMU)) {
switch (get_cpu_temp_grade(&minc, &maxc)) {
case TEMP_AUTOMOTIVE:
- grade = "Automotive temperature grade ";
+ grade = "Automotive temperature grade";
break;
case TEMP_INDUSTRIAL:
- grade = "Industrial temperature grade ";
+ grade = "Industrial temperature grade";
break;
case TEMP_EXTCOMMERCIAL:
- grade = "Extended Consumer temperature grade ";
+ grade = "Extended Consumer temperature grade";
break;
default:
- grade = "Consumer temperature grade ";
+ grade = "Consumer temperature grade";
break;
}
--
2.45.2
[PATCH V4 7/7] imx: imx9: Imply CPU_IMX by default
The imx8_cpu driver is a CPU Driver that supports the i.MX9 family to display the CPU type, temperature grade and current operating temperature. The older file, arch/arm/mach-imx/cpu.c, does not support i.MX9, so this config is enabled in various IMX9 boards. Instead of having this option enabled in every IMX9, select this driver by default for the platform. Signed-off-by: Adam Ford --- arch/arm/mach-imx/imx9/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig index c3e758e103a..1ccdb1cf64f 100644 --- a/arch/arm/mach-imx/imx9/Kconfig +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -8,6 +8,8 @@ config AHAB_BOOT config IMX9 bool select BINMAN + select CPU + select CPU_IMX select HAS_CAAM select ROM_UNIFIED_SECTIONS imply IMX_TMU -- 2.45.2
[PATCH V4 6/7] imx: imx8: Imply CPU_IMX by default
The imx8_cpu driver is a CPU Driver that supports the i.MX8Q family. When it is enabled, it acts as an alternative to arch/arm/mach-imx/cpu.c, but the imx8_cpu supports the driver model where cpu.c does not. Imply this newer driver by default. Signed-off-by: Adam Ford --- arch/arm/mach-imx/imx8/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 9a43beda6fa..257c14e61b6 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -9,6 +9,8 @@ config AHAB_BOOT config IMX8 bool select HAS_CAAM + imply CPU + imply CPU_IMX config MU_BASE_SPL hex "MU base address used in SPL" -- 2.45.2
Re: [PATCH v2 1/4] riscv: lib: Add a default implementation of board_fdt_blob_setup
On Fri, Mar 07, 2025 at 01:13:41PM +, Yao Zi wrote: > It's common for S-Mode proper U-Boot to retrieve a FDT blob along with > taking control from SBI firmware. Add a weak version of > board_fdt_blob_setup to make use of it by default, avoiding copy-pasting > similar functions among boards. > > Signed-off-by: Yao Zi > --- > arch/riscv/lib/Makefile | 1 + > arch/riscv/lib/board.c | 19 +++ > 2 files changed, 20 insertions(+) > create mode 100644 arch/riscv/lib/board.c Reviewed-by: Leo Yu-Chi Liang
[PATCH 1/8] arm: dts: k3-am625-phyboard-lyra-rdk: Add boot phase tag to phy_gmii_sel
Add bootph-all tag to phy_gmii_sel node. This is needed for booting via
Ethernet. While at it, drop main_pktdma reg redefinitions which are already
provided by the top-level SoC device tree file.
Signed-off-by: Wadim Egorov
---
.../arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi | 14 --
1 file changed, 4 insertions(+), 10 deletions(-)
diff --git a/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi
b/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi
index 2bc5acbec23..253ca297e12 100644
--- a/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi
@@ -42,6 +42,10 @@
bootph-all;
};
+&phy_gmii_sel {
+ bootph-all;
+};
+
&fss {
bootph-all;
};
@@ -86,16 +90,6 @@
&main_pktdma {
bootph-all;
- reg = <0x00 0x485c 0x00 0x100>,
- <0x00 0x4a80 0x00 0x2>,
- <0x00 0x4aa0 0x00 0x2>,
- <0x00 0x4b80 0x00 0x20>,
- <0x00 0x485e 0x00 0x1>,
- <0x00 0x484a 0x00 0x2000>,
- <0x00 0x484c 0x00 0x2000>,
- <0x00 0x4843 0x00 0x1000>;
- reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
- "cfg", "tchan", "rchan", "rflow";
};
&main_rgmii1_pins_default {
--
2.34.1
[PATCH 6/8] arch: arm: mach-k3: r5: am62ax: Update SoC auto-gen data to enable CPSW boot
From: Andreas Dannenberg
This data was generated using the ksswtool-autogen project with the
followig commit:
eed7492 ("soc: am62ax: Add cpsw_3guss_main_0 id to the dev list")
Signed-off-by: Andreas Dannenberg
Signed-off-by: Nathan Morrisson
Signed-off-by: Wadim Egorov
---
arch/arm/mach-k3/r5/am62ax/clk-data.c | 51 +--
arch/arm/mach-k3/r5/am62ax/dev-data.c | 29 ---
2 files changed, 65 insertions(+), 15 deletions(-)
diff --git a/arch/arm/mach-k3/r5/am62ax/clk-data.c
b/arch/arm/mach-k3/r5/am62ax/clk-data.c
index d950b35e0be..7f1b6d5b4e0 100644
--- a/arch/arm/mach-k3/r5/am62ax/clk-data.c
+++ b/arch/arm/mach-k3/r5/am62ax/clk-data.c
@@ -67,6 +67,17 @@ static const char * const clkout0_ctrl_out0_parents[] = {
"hsdiv4_16fft_main_2_hsdivout1_clk",
};
+static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = {
+ "postdiv4_16ff_main_2_hsdivout5_clk",
+ "postdiv4_16ff_main_0_hsdivout6_clk",
+ "board_0_cp_gemac_cpts0_rft_clk_out",
+ NULL,
+ "board_0_mcu_ext_refclk0_out",
+ "board_0_ext_refclk1_out",
+ "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk",
+ "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
+};
+
static const char * const main_emmcsd0_refclk_sel_out0_parents[] = {
"postdiv4_16ff_main_0_hsdivout5_clk",
"hsdiv4_16fft_main_2_hsdivout2_clk",
@@ -137,7 +148,16 @@ static const struct clk_data clk_list[] = {
CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0),
CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0),
CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0),
+ CLK_FIXED_RATE("board_0_rgmii1_rxc_out", 0, 0),
+ CLK_FIXED_RATE("board_0_rgmii1_txc_out", 0, 0),
+ CLK_FIXED_RATE("board_0_rgmii2_rxc_out", 0, 0),
+ CLK_FIXED_RATE("board_0_rgmii2_txc_out", 0, 0),
+ CLK_FIXED_RATE("board_0_rmii1_ref_clk_out", 0, 0),
+ CLK_FIXED_RATE("board_0_rmii2_ref_clk_out", 0, 0),
CLK_FIXED_RATE("board_0_tck_out", 0, 0),
+ CLK_FIXED_RATE("cpsw_3guss_main_0_mdio_mdclk_o", 0, 0),
+ CLK_FIXED_RATE("cpsw_3guss_main_0_rgmii1_txc_o", 0, 0),
+ CLK_FIXED_RATE("cpsw_3guss_main_0_rgmii2_txc_o", 0, 0),
CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
CLK_FIXED_RATE("emmcsd8ss_main_0_emmcsdss_io_clk_o", 0, 0),
CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0),
@@ -187,6 +207,7 @@ static const struct clk_data clk_list[] = {
CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk",
sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x402, 0),
CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk",
"sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0),
CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0,
1, 0),
+ CLK_MUX("main_cp_gemac_cpts_clk_sel_out0",
main_cp_gemac_cpts_clk_sel_out0_parents, 8, 0x108140, 0, 3, 0),
CLK_MUX("main_emmcsd0_refclk_sel_out0",
main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0),
CLK_MUX("main_emmcsd1_refclk_sel_out0",
main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0),
CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8,
0x43008030, 0, 3, 0),
@@ -203,6 +224,29 @@ static const struct clk_data clk_list[] = {
};
static const struct dev_clk soc_dev_clk_data[] = {
+ DEV_CLK(13, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(13, 3, "main_cp_gemac_cpts_clk_sel_out0"),
+ DEV_CLK(13, 4, "postdiv4_16ff_main_2_hsdivout5_clk"),
+ DEV_CLK(13, 5, "postdiv4_16ff_main_0_hsdivout6_clk"),
+ DEV_CLK(13, 6, "board_0_cp_gemac_cpts0_rft_clk_out"),
+ DEV_CLK(13, 8, "board_0_mcu_ext_refclk0_out"),
+ DEV_CLK(13, 9, "board_0_ext_refclk1_out"),
+ DEV_CLK(13, 10, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
+ DEV_CLK(13, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(13, 13, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 14, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 15, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 16, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 17, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 19, "board_0_rgmii1_rxc_out"),
+ DEV_CLK(13, 20, "board_0_rgmii1_txc_out"),
+ DEV_CLK(13, 22, "board_0_rgmii2_rxc_out"),
+ DEV_CLK(13, 23, "board_0_rgmii2_txc_out"),
+ DEV_CLK(13, 25, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 26, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 27, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+ DEV_CLK(13, 28, "board_0_rmii1_ref_clk_out"),
+ DEV_CLK(13, 29, "board_0_rmii2_ref_clk_out"),
DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"),
DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
@@ -277,11 +321,14 @@ static const struct dev_clk soc_dev_c
[PATCH 5/8] arch: arm: mach-k3: am62a7: Probe CPSW NUSS in board_init_f()
From: Nathan Morrisson
Probe CPSW NUSS in am62a7 board_init_f() to support ethernet boot.
Signed-off-by: Nathan Morrisson
Signed-off-by: Wadim Egorov
---
arch/arm/mach-k3/am62ax/am62a7_init.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/mach-k3/am62ax/am62a7_init.c
b/arch/arm/mach-k3/am62ax/am62a7_init.c
index 698e6d5c587..52a21277227 100644
--- a/arch/arm/mach-k3/am62ax/am62a7_init.c
+++ b/arch/arm/mach-k3/am62ax/am62a7_init.c
@@ -194,6 +194,15 @@ void board_init_f(ulong dummy)
setup_qos();
+ if (IS_ENABLED(CONFIG_SPL_ETH) && IS_ENABLED(CONFIG_TI_AM65_CPSW_NUSS)
&&
+ spl_boot_device() == BOOT_DEVICE_ETHERNET) {
+ struct udevice *cpswdev;
+
+ if (uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(am65_cpsw_nuss),
+ &cpswdev))
+ printf("Failed to probe am65_cpsw_nuss driver\n");
+ }
+
debug("am62a_init: %s done\n", __func__);
}
--
2.34.1
[PATCH 2/8] configs: Add phycore_am62x_r5_ethboot_defconfig
Provide a defconfig for booting the phycore-am62x via Ethernet. We need a separate defconfig because the AM62x has not enough internal SRAM to support all boot sources. Signed-off-by: Wadim Egorov --- board/phytec/phycore_am62x/MAINTAINERS | 1 + configs/phycore_am62x_r5_ethboot_defconfig | 43 ++ 2 files changed, 44 insertions(+) create mode 100644 configs/phycore_am62x_r5_ethboot_defconfig diff --git a/board/phytec/phycore_am62x/MAINTAINERS b/board/phytec/phycore_am62x/MAINTAINERS index 670c7473481..106b4b80121 100644 --- a/board/phytec/phycore_am62x/MAINTAINERS +++ b/board/phytec/phycore_am62x/MAINTAINERS @@ -9,6 +9,7 @@ F: arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts F: board/phytec/phycore_am62x/ F: configs/phycore_am62x_a53_defconfig F: configs/phycore_am62x_r5_defconfig +F: configs/phycore_am62x_r5_ethboot_defconfig F: configs/phycore_am62x_r5_usbdfu_defconfig F: include/configs/phycore_am62x.h F: doc/board/phytec/phycore-am62x.rst diff --git a/configs/phycore_am62x_r5_ethboot_defconfig b/configs/phycore_am62x_r5_ethboot_defconfig new file mode 100644 index 000..3bc426821e9 --- /dev/null +++ b/configs/phycore_am62x_r5_ethboot_defconfig @@ -0,0 +1,43 @@ +#include + +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SOC_K3_AM625=y +CONFIG_TARGET_PHYCORE_AM62X_R5=y +CONFIG_DEFAULT_DEVICE_TREE="k3-am625-r5-phycore-som-2gb" + +CONFIG_SPL_GPIO=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x20 +CONFIG_SPL_DMA=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_ETH=y +CONFIG_SPL_I2C=y +CONFIG_SPL_NET=y +CONFIG_SPL_NET_VCI_STRING="AM62X U-Boot R5 SPL" +CONFIG_SPL_SYSCON=y +CONFIG_DMA_CHANNELS=y +CONFIG_TI_K3_NAVSS_UDMA=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_OMAP24XX=y +CONFIG_PHY_TI_DP83867=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_TI_AM65_CPSW_NUSS=y +CONFIG_SPL_MMC=n +CONFIG_SPL_DM_SPI=n +CONFIG_SPL_MMC=n +CONFIG_SPL_SPI_FLASH_SUPPORT=n +CONFIG_SPL_SPI=n +CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=n +CONFIG_SPL_SPI_LOAD=n +CONFIG_SPL_YMODEM_SUPPORT=n +CONFIG_DM_SPI_FLASH=n +CONFIG_SPI_FLASH_SFDP_SUPPORT=n +CONFIG_SPI_FLASH_SOFT_RESET=n +CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=n +CONFIG_SPI_FLASH_STMICRO=n +CONFIG_SPI_FLASH_MT35XU=n +CONFIG_SPI=n +CONFIG_DM_SPI=n +CONFIG_CADENCE_QSPI=n +CONFIG_SPL_DM_SPI=n -- 2.34.1
[PATCH 7/8] board: phytec: phycore_am62ax: Share ethernet resources with boot r5 core
From: Nathan Morrisson During the U-Boot SPL R5 boot stage the code is running on the MAIN R5 core, which means a host ID of 36 is used for DM/TIFS communication, see [1]. In order to enable Ethernet boot update the DMA resources used to be shared with the MAIN R5 core instead of the MCU R5 core. [1] https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/am62ax/hosts.html Based on patch 19 from https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1307981/sk-am62a-lp-rgmii-boot-mode-problem Signed-off-by: Nathan Morrisson Signed-off-by: Wadim Egorov --- board/phytec/phycore_am62ax/rm-cfg.yaml | 10 ++-- board/phytec/phycore_am62ax/tifs-rm-cfg.yaml | 48 +++- 2 files changed, 32 insertions(+), 26 deletions(-) diff --git a/board/phytec/phycore_am62ax/rm-cfg.yaml b/board/phytec/phycore_am62ax/rm-cfg.yaml index cbd087de797..0f34b8c1bc0 100644 --- a/board/phytec/phycore_am62ax/rm-cfg.yaml +++ b/board/phytec/phycore_am62ax/rm-cfg.yaml @@ -713,7 +713,7 @@ rm-cfg: start_resource: 19 num_resource: 64 type: 1937 -host_id: 30 +host_id: 36 reserved: 0 - start_resource: 83 @@ -767,7 +767,7 @@ rm-cfg: start_resource: 118 num_resource: 16 type: 1943 -host_id: 30 +host_id: 36 reserved: 0 - start_resource: 134 @@ -833,7 +833,7 @@ rm-cfg: start_resource: 19 num_resource: 8 type: 1956 -host_id: 30 +host_id: 36 reserved: 0 - start_resource: 27 @@ -917,7 +917,7 @@ rm-cfg: start_resource: 19 num_resource: 1 type: 1963 -host_id: 30 +host_id: 36 reserved: 0 - start_resource: 19 @@ -929,7 +929,7 @@ rm-cfg: start_resource: 19 num_resource: 16 type: 1964 -host_id: 30 +host_id: 36 reserved: 0 - start_resource: 20 diff --git a/board/phytec/phycore_am62ax/tifs-rm-cfg.yaml b/board/phytec/phycore_am62ax/tifs-rm-cfg.yaml index 151cd599b1b..23dcd784615 100644 --- a/board/phytec/phycore_am62ax/tifs-rm-cfg.yaml +++ b/board/phytec/phycore_am62ax/tifs-rm-cfg.yaml @@ -24,26 +24,26 @@ tifs-rm-cfg: allowed_priority: 0x allowed_sched_priority: 0xAA - # 2 -host_id: 30 +host_id: 20 allowed_atype: 0x2A allowed_qos: 0x allowed_orderid: 0x allowed_priority: 0x allowed_sched_priority: 0xAA - # 3 -host_id: 36 +host_id: 30 allowed_atype: 0x2A allowed_qos: 0x allowed_orderid: 0x allowed_priority: 0x allowed_sched_priority: 0xAA - # 4 -host_id: 0 -allowed_atype: 0 -allowed_qos: 0 -allowed_orderid: 0 -allowed_priority: 0 -allowed_sched_priority: 0 +host_id: 36 +allowed_atype: 0x2A +allowed_qos: 0x +allowed_orderid: 0x +allowed_priority: 0x +allowed_sched_priority: 0xAA - # 5 host_id: 0 allowed_atype: 0 @@ -244,7 +244,7 @@ tifs-rm-cfg: subhdr: magic: 0x7B25 size: 8 -resasg_entries_size: 872 +resasg_entries_size: 880 reserved: 0 resasg_entries: - @@ -257,7 +257,7 @@ tifs-rm-cfg: start_resource: 18 num_resource: 6 type: 1677 -host_id: 35 +host_id: 20 reserved: 0 - start_resource: 18 @@ -287,7 +287,7 @@ tifs-rm-cfg: start_resource: 72 num_resource: 6 type: 1678 -host_id: 35 +host_id: 20 reserved: 0 - start_resource: 72 @@ -317,7 +317,7 @@ tifs-rm-cfg: start_resource: 44 num_resource: 6 type: 1679 -host_id: 35 +host_id: 20 reserved: 0 - start_resource: 44 @@ -347,7 +347,7 @@ tifs-rm-cfg: start_resource: 18 num_resource: 6 type: 1696 -host_id: 35 +host_id: 20 reserved: 0 - start_resource: 18 @@ -377,7 +377,7 @@ tifs-rm-cfg:
[PATCH 8/8] configs: Add phycore_am62ax_r5_ethboot_defconfig
Provide a defconfig for booting the phycore-am62ax via Ethernet. Signed-off-by: Wadim Egorov --- board/phytec/phycore_am62ax/MAINTAINERS | 1 + configs/phycore_am62ax_r5_ethboot_defconfig | 43 + 2 files changed, 44 insertions(+) create mode 100644 configs/phycore_am62ax_r5_ethboot_defconfig diff --git a/board/phytec/phycore_am62ax/MAINTAINERS b/board/phytec/phycore_am62ax/MAINTAINERS index 3e4e2feff4e..9169651c459 100644 --- a/board/phytec/phycore_am62ax/MAINTAINERS +++ b/board/phytec/phycore_am62ax/MAINTAINERS @@ -10,5 +10,6 @@ F:arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts F: board/phytec/phycore_am62ax/ F: configs/phycore_am62ax_a53_defconfig F: configs/phycore_am62ax_r5_defconfig +F: configs/phycore_am62ax_r5_ethboot_defconfig F: include/configs/phycore_am62ax.h F: doc/board/phytec/phycore-am62ax.rst diff --git a/configs/phycore_am62ax_r5_ethboot_defconfig b/configs/phycore_am62ax_r5_ethboot_defconfig new file mode 100644 index 000..81a7f5b0784 --- /dev/null +++ b/configs/phycore_am62ax_r5_ethboot_defconfig @@ -0,0 +1,43 @@ +#include + +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SOC_K3_AM62A7=y +CONFIG_TARGET_PHYCORE_AM62AX_R5=y +CONFIG_DEFAULT_DEVICE_TREE="k3-am62a7-r5-phycore-som-2gb" + +CONFIG_SPL_GPIO=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x20 +CONFIG_SPL_BSS_MAX_SIZE=0x3100 +CONFIG_SPL_DMA=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_ETH=y +CONFIG_SPL_I2C=y +CONFIG_SPL_NET=y +CONFIG_SPL_NET_VCI_STRING="AM62AX U-Boot R5 SPL" +CONFIG_SPL_SYSCON=y +CONFIG_DMA_CHANNELS=y +CONFIG_TI_K3_NAVSS_UDMA=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_OMAP24XX=y +CONFIG_PHY_TI_DP83867=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_TI_AM65_CPSW_NUSS=y +CONFIG_SPL_MMC=n +CONFIG_SPL_DM_SPI=n +CONFIG_SPL_MMC=n +CONFIG_SPL_SPI_FLASH_SUPPORT=n +CONFIG_SPL_SPI=n +CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=n +CONFIG_SPL_SPI_LOAD=n +CONFIG_SPL_YMODEM_SUPPORT=n +CONFIG_DM_SPI_FLASH=n +CONFIG_SPI_FLASH_SFDP_SUPPORT=n +CONFIG_SPI_FLASH_SOFT_RESET=n +CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=n +CONFIG_SPI_FLASH_STMICRO=n +CONFIG_SPI_FLASH_MT35XU=n +CONFIG_SPI=n +CONFIG_DM_SPI=n +CONFIG_CADENCE_QSPI=n -- 2.34.1
[PATCH 4/8] arch: arm: dts: k3-am62a7-phyboard-lyra-rdk-u-boot: Disable Ethernet2
From: Daniel Schultz
Don't initialize Ethernet2 in SPL. We cannot boot from that source anyways
and it throws an error during boot.
This will remove following error message during network boot:
Error: ethernet@800port@2 No valid MAC address found.ethernet@800port@1
Waiting for PHY auto negotiation to complete... done
Signed-off-by: Daniel Schultz
Signed-off-by: Wadim Egorov
---
arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi
b/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi
index 41692c8f670..e2a086e6b90 100644
--- a/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi
@@ -66,7 +66,7 @@
};
&cpsw_port2 {
- bootph-all;
+ status = "disabled";
};
&dmsc {
--
2.34.1
Re: [PATCH] RISCV: config: Remove CFG_SYS_SDRAM_BASE
On Mon, Mar 10, 2025 at 09:47:48AM +0800, Jimmy Ho wrote: > Remove CFG_SYS_SDRAM_BASE so that we can get DRAM base from dt instead of > compile time config. > Removing this config helps the u-boot more portable. > > Signed-off-by: Jimmy Ho > --- > include/configs/sifive-unleashed.h | 1 - > include/configs/sifive-unmatched.h | 1 - > 2 files changed, 2 deletions(-) Reviewed-by: Leo Yu-Chi Liang
Re: block devices on MTD and UBI
On 20-03-2025 17:03, Mike Looijmans wrote:
On 19-03-2025 15:06, Heiko Schocher wrote:
Hello Mike,
On 18.03.25 10:04, Mike Looijmans wrote:
I think I have everything set up to access MTD (and UBI) devices as
"block", however, lsblk always ignores them, and refuses to list
anything but the mmc. I can read ubifs and boot from it though, and
since UBI runs on top of MTD block devices, MTD block device should
be working, right?
Yes. I must admit, I have no device on which I have such a setup...
added Alexey (who introduced ubi block support), may he can give some
hints.
I also have UBI_BLOCK enabled, so I would expect UBI volumes to
appear in the "lsblk" as well.
good, that would have been my first question, if you have enabled
"UBI_BLOCK"
Example U-boot session:
Zynq> mtd list
SF: Detected n25q256ax1 with page size 256 Bytes, erase size 64 KiB,
total 32 MiB
List of MTD devices:
* nor0
- device: flash@0
- parent: spi@e000d000
- driver: jedec_spi_nor
- path: /axi/spi@e000d000/flash@0
- type: NOR flash
- block size: 0x1 bytes
- min I/O: 0x1 bytes
- 0x-0x0200 : "nor0"
- 0x-0x0010 : "qspi-boot-bin"
- 0x0010-0x0200 : "qspi-rootfs"
Aha, SPI NOR. I fear this is not supported yet.
Do you have somehow called ubi_part() ?
Can you try "ubi part" and look if this helps?
See below I guess...
Zynq> lsblk
Block Driver Devices
-
efi_blk :
mmc_blk : mmc 0
mtd_blk :
ubi_blk :
Here (and for mtd) seems something missing!
usb_storage_blk :
Zynq> ubi part qspi-rootfs
Zynq> ubi list
0: qspi-rootfs
Zynq> lsblk
Block Driver Devices
-
efi_blk :
mmc_blk : mmc 0
mtd_blk :
ubi_blk :
usb_storage_blk :
I would have expected the SPI NOR flash to appear in the "mtd_blk"
devices, and would expect the UBI volumes to appear in the "ubi_blk"
list.
What am I missing?
It seems to me, that you have to implement this like it is done for
spi nand:
drivers/mtd/nand/spi/core.c
1180 static int spinand_bind(struct udevice *dev)
1181 {
1182 if (blk_enabled()) {
1183 struct spinand_plat *plat = dev_get_plat(dev);
1184 int ret;
1185
1186 if (CONFIG_IS_ENABLED(MTD_BLOCK)) {
1187 ret = mtd_bind(dev, &plat->mtd);
1188 if (ret)
1189 return ret;
1190 }
1191
1192 if (CONFIG_IS_ENABLED(UBI_BLOCK))
1193 return ubi_bind(dev);
1194 }
1195
1196 return 0;
1197 }
I guess that shouldn't be to hard to implement... I'll send a patch if
that fixes the MTD missing...
Not as simple as one would think. The spi flash struct has its own "mtd"
member which isn't a pointer but was already filled in. So I cannot
simply call mtd_bind().
I tried calling ubi_bind anyway, which had some effect:
Zynq> lsblk
Block Driver Devices
-
efi_blk :
mmc_blk : mmc 0
mtd_blk :
ubi_blk : mtd 0
usb_storage_blk :
But that didn't get me any further. I'm quite puzzled by UBI block
support...
I have a squashfs filesystem put into an ubi block on a static volume.
In Linux I can do this:
root@tdkz30:~# ubiattach -m 1
UBI device number 0, total 496 LEBs (32442368 bytes, 30.9 MiB),
available 0 LEBs (0 bytes), LEB size 65408 bytes (63.8 KiB)
root@tdkz30:~# ubiblock --create /dev/ubi0_0
root@tdkz30:~# mount /dev/ubiblock0_0 /run/s
root@tdkz30:~# ls -al /run/s
drwxr-xr-x 16 root root 236 Mar 9 2018 .
drwxr-xr-x 13 root root 380 Mar 24 13:21 ..
drwxr-xr-x 2 root root 1023 Mar 9 2018 bin
drwxr-xr-x 3 root root 123 Mar 9 2018 boot
drwxr-xr-x 2 root root 3 Mar 9 2018 dev
drwxr-xr-x 19 root root 959 Mar 9 2018 etc
...
I have no clue what the equivalent in U-boot would be. I can see that
the static volume is there:
zynq-uboot> ubi part qspi-rootfs
SF: Detected n25q256ax1 with page size 256 Bytes, erase size 64 KiB,
total 32 MiB
ubi0: attaching mtd2
ubi0: scanning is finished
ubi0: attached mtd2 (name "qspi-rootfs", size 31 MiB)
ubi0: PEB size: 65536 bytes (64 KiB), LEB size: 65408 bytes
ubi0: min./max. I/O unit sizes: 1/256, sub-page size 1
ubi0: VID header offset: 64 (aligned 64), data offset: 128
ubi0: good PEBs: 496, bad PEBs: 0, corrupted PEBs: 0
ubi0: user volume: 1, internal volumes: 1, max. volumes count: 128
ubi0: max/mean erase counter: 16/11, WL threshold: 4096, image sequence
number: 2011979467
ubi0: available PEBs: 0, total reserved PEBs: 496, PEBs reserved for bad
PEB handling: 0
zynq-uboot> ubi list
0: qspi-rootfs
zynq-uboot> ubi in
[resend v3 00/12] Add Synopsys MIPI I3C Driver support
From: Dinesh Maniyam This patchset add Synopsys MIPI I3C Driver support for Intel Agilex5 devices. The i3c driver is leveraged from the master/dw-i3c-master.c, i3c/device.c and i3c/master.c Linux version 6.6.37 LTS And few header files included to be part of the migration; i3c/internals.h, include/linux/i3c/ccc.h, include/linux/i3c/device.h and include/linux/i3c/master.h. Additional i3c uclass driver and command files added to support i3c read and write in U-Boot. Patch status: Detail changelog can find in commit message. v3->v2: - Squash commit 10 to commit 9 - Resolve index for new files to pass the checkpatch Commit: sandbox_defconfig: Enable configs for sandbox i3c Commit: agilex5_defconfig: Enable i3c configs for agilex5 - use savedefconfig drivers: Enabled Kconfig and Makefile for i3c support - Add maintainer for i3c drivers: i3c: Enabled Kconfig and Makefile for DWI3C - Add empty lines for if/endif drivers: i3c: Add i3c sandbox simple test. - Removed DECLARE_GLOBAL_DATA_PTR v1->v2: Reorder commits. Added commits: - drivers: i3c: Add i3c sandbox simple test. - test: cmd: Add simple test for i3c - configs: sandbox_defconfig: Enable configs for sandbox i3c - configs: agilex5_defconfig: Enable i3c configs for agilex5 History: [v1]: https://patchwork.ozlabs.org/project/uboot/cover/20250218025705.50051-1-dinesh.mani...@intel.com/ [v2]: https://patchwork.ozlabs.org/project/uboot/cover/20250314040902.43621-1-dinesh.mani...@altera.com/ Dinesh Maniyam (12): drivers: i3c: Add new i3c uclass id drivers: i3c: Add driver for MIPI DWI3C drivers: i3c: Add i3c uclass driver. drivers: Enabled Kconfig and Makefile for i3c support drivers: i3c: Enabled Kconfig and Makefile for DWI3C drivers: i3c: Add i3c sandbox simple test. drivers: i3c: master: Enable probe i3c without slave device i3c: master: dw-i3c-master: Fix OD_TIMING for spike filter cmd: Add i3c command support. test: cmd: Add simple test for i3c configs: sandbox_defconfig: Enable configs for sandbox i3c configs: agilex5_defconfig: Enable i3c configs for agilex5 MAINTAINERS|7 + arch/sandbox/dts/test.dts |8 + cmd/Kconfig|6 + cmd/Makefile |1 + cmd/i3c.c | 193 +++ configs/sandbox_defconfig |4 + configs/socfpga_agilex5_defconfig |3 + doc/usage/cmd/i3c.rst | 98 ++ drivers/Kconfig|2 + drivers/Makefile |1 + drivers/i3c/Kconfig| 27 + drivers/i3c/Makefile |5 + drivers/i3c/device.c | 262 drivers/i3c/i3c-uclass.c | 38 + drivers/i3c/internals.h| 26 + drivers/i3c/master.c | 2072 drivers/i3c/master/Kconfig | 11 + drivers/i3c/master/Makefile|3 + drivers/i3c/master/dw-i3c-master.c | 1058 ++ drivers/i3c/sandbox_i3c.c | 56 + include/dm/device.h|2 + include/dm/uclass-id.h |1 + include/dw-i3c.h | 252 include/i3c.h | 67 + include/linux/i3c/ccc.h| 385 ++ include/linux/i3c/device.h | 286 include/linux/i3c/master.h | 698 ++ test/cmd/Makefile |1 + test/cmd/i3c.c | 52 + test/dm/Makefile |1 + test/dm/i3c.c | 34 + 31 files changed, 5660 insertions(+) create mode 100644 cmd/i3c.c create mode 100644 doc/usage/cmd/i3c.rst create mode 100644 drivers/i3c/Kconfig create mode 100644 drivers/i3c/Makefile create mode 100644 drivers/i3c/device.c create mode 100644 drivers/i3c/i3c-uclass.c create mode 100644 drivers/i3c/internals.h create mode 100644 drivers/i3c/master.c create mode 100644 drivers/i3c/master/Kconfig create mode 100644 drivers/i3c/master/Makefile create mode 100644 drivers/i3c/master/dw-i3c-master.c create mode 100644 drivers/i3c/sandbox_i3c.c create mode 100644 include/dw-i3c.h create mode 100644 include/i3c.h create mode 100644 include/linux/i3c/ccc.h create mode 100644 include/linux/i3c/device.h create mode 100644 include/linux/i3c/master.h create mode 100644 test/cmd/i3c.c create mode 100644 test/dm/i3c.c -- 2.26.2
[PATCH] bootm: Add support for passing arguments to elf app
This extends the bootm command to allow passing arguments to standalone ELF applications. Signed-off-by: Niu Zhihong --- boot/bootm_os.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boot/bootm_os.c b/boot/bootm_os.c index e9522cd3299..7e41e1f6141 100644 --- a/boot/bootm_os.c +++ b/boot/bootm_os.c @@ -402,7 +402,7 @@ static int do_bootm_elf(int flag, struct bootm_info *bmi) if (flag != BOOTM_STATE_OS_GO) return 0; - bootelf(bmi->images->ep, flags, 0, NULL); + bootelf(bmi->images->ep, flags, bmi->argc, bmi->argv); return 1; } -- 2.39.5 (Apple Git-154)
Re: [PATCH v2 00/11] Rockchip VOP2 support
Hello, First of all, thanks for your work on this Rockchip upstream code. We have tested your patches on RK3566 board (Radxa CM3 IO) and HDMI output in U-Boot works great. We didn't have success with MIPI yet so far, though. > HDMI should work flawlessly but there's still some timings issue with > DW MIPI DSI, perhaps that's something to look into later. I wanted to confirm whether you have had success with the MIPI as well, and what exactly do you mean by these issues? Thanks, -- Maciej Pijanowski Engineering Manager GPG: 9963C36AAC3B2B46 https://3mdeb.com | @3mdeb_com OpenPGP_0x9963C36AAC3B2B46.asc Description: OpenPGP public key OpenPGP_signature.asc Description: OpenPGP digital signature
[resend v3 12/12] configs: agilex5_defconfig: Enable i3c configs for agilex5
From: Dinesh Maniyam Enable configs for i3c in agilex5. Signed-off-by: Dinesh Maniyam --- configs/socfpga_agilex5_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/socfpga_agilex5_defconfig b/configs/socfpga_agilex5_defconfig index 8577ac610c2..87febc9f4ce 100644 --- a/configs/socfpga_agilex5_defconfig +++ b/configs/socfpga_agilex5_defconfig @@ -44,6 +44,7 @@ CONFIG_CMD_NVEDIT_SELECT=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y +CONFIG_CMD_I3C=y CONFIG_CMD_MTD=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y @@ -66,6 +67,8 @@ CONFIG_SPL_ALTERA_SDRAM=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y +CONFIG_I3C=y +CONFIG_DW_I3C_MASTER=y CONFIG_MISC=y CONFIG_DM_MTD=y CONFIG_SPI_FLASH_SPANSION=y -- 2.26.2
Re: [PATCH v1 00/11] Amlogic: ADNL and Optimus protocols support
On Wed Mar 19, 2025 at 8:20 PM UTC, Arseniy Krasnov via groups.io wrote: > This patchset adds support of two Amlogic firmware burning protocols: > ADNL and Optimus. Each protocol is supported on the following SoC: > > axg, g12a, g12b, sm1 - Optimus. > a1, s4, a5, c1, c2, c3, sc2, t3, t7, p1 - ADNL. > Out of curiosity, don't GXL and GXBB also support Optimus? Or is it completely different? > Both work in fastboot manner, but significant feature is that they are > supported by current Amlogic BootROMs. As transport both use USB: > device is switched to gadget mode and then it can communicate with PC. > On PC side protocols are supported by: > > 1) https://github.com/superna/pyamlboot (with some limitation) > >For example: >pyamlboot/./ubt.py --img --wipe all --reset > >Note, image has special format, specific for Amlogic. Awesome :) Regards.
Re: [PATCH 6/8] env: Rename ENV_MMC_PARTITION to ENV_SDMMC_SW_PARTITION
Hi Marek, On 3/22/25 10:55 PM, Marek Vasut wrote: Rename the variable and add ENV_ prefix, so that all configuration options which are related to environment would have an CONFIG_ENV_ prefix. No functional change. Use ENV_SDMMC_SW_PARTITION to clarify this is the SD/MMC software partition table entry selector. Update the help text accordingly. Signed-off-by: Marek Vasut --- Cc: Paul Barker Cc: Quentin Schulz Cc: Simon Glass Cc: Tom Rini --- doc/device-tree-bindings/config.txt | 2 +- env/Kconfig | 21 - env/mmc.c | 4 ++-- 3 files changed, 15 insertions(+), 12 deletions(-) diff --git a/doc/device-tree-bindings/config.txt b/doc/device-tree-bindings/config.txt index 8584cc6dcf4..3c92d5d 100644 --- a/doc/device-tree-bindings/config.txt +++ b/doc/device-tree-bindings/config.txt @@ -76,7 +76,7 @@ u-boot,mmc-env-partition (int) precedence. In that case, only if the partition is not found, mmc-env-offset* will be tried. - Note that CONFIG_ENV_MMC_PARTITION overrides this device-tree setting. + Note that CONFIG_ENV_SDMMC_SW_PARTITION overrides this device-tree setting. u-boot,no-apm-finalize (bool) For x86 devices running on coreboot, this tells U-Boot not to lock diff --git a/env/Kconfig b/env/Kconfig index fbc03777040..19bc34f8663 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -677,7 +677,7 @@ config ENV_SDMMC_DEVICE_INDEX matches the 'mmc list' command output. config ENV_SDMMC_EMMC_HW_PARTITION - int "mmc partition number" + int "eMMC hardware partition number" This should have been in the previous patch I believe. depends on ENV_IS_IN_MMC || ENV_IS_IN_FAT default 0 help @@ -687,17 +687,20 @@ config ENV_SDMMC_EMMC_HW_PARTITION partition 0 or the first boot partition, which is 1 or some other defined partition. -config USE_ENV_MMC_PARTITION - bool "use the mmc environment partition name" +config ENV_SDMMC_USE_SW_PARTITION + bool "Use SD/MMC environment software partition name" depends on ENV_IS_IN_MMC -config ENV_MMC_PARTITION - string "mmc environment partition name" - depends on USE_ENV_MMC_PARTITION +config ENV_SDMMC_SW_PARTITION + bool "SD/MMC environment software partition name" + depends on ENV_SDMMC_USE_SW_PARTITION help - MMC partition name used to save environment variables. - If this variable is unset, u-boot will try to get the env partition name - from the device-tree's /config node. + SD/MMC software partition name used to save environment variables. + This is a software partition name, i.e. one in partition table, not + an eMMC HW partition (see ENV_SDMMC_EMMC_HW_PARTITION for eMMC HW s/HW/hardware/ + partition configuration). If this variable is unset, u-boot will s/u-boot/U-Boot/ + try to get the env partition name from the device-tree's /config + node. Should we also have the same (or very similar) help text for ENV_SDMMC_USE_SW_PARTITION? The issue is that one would need to use the search function to find ENV_SDMMC_SW_PARTITION since it won't be displayed until ENV_SDMMC_USE_SW_PARTITION is enabled, a symbol that we do not currently document. config ENV_MMC_USE_DT bool "Read partition name and offset in DT" diff --git a/env/mmc.c b/env/mmc.c index 4155a5c72f1..f49af88bf5f 100644 --- a/env/mmc.c +++ b/env/mmc.c @@ -161,8 +161,8 @@ static inline s64 mmc_offset(struct mmc *mmc, int copy) hwpart = mmc_get_env_part(mmc); #endif -#if defined(CONFIG_ENV_MMC_PARTITION) - str = CONFIG_ENV_MMC_PARTITION; +#if defined(CONFIG_ENV_SDMMC_SW_PARTITION) + str = CONFIG_ENV_SDMMC_SW_PARTITION; #else /* look for the partition in mmc CONFIG_ENV_SDMMC_DEVICE_INDEX */ This comment seems incorrect no? (unrelated to this patch though). Cheers, Quentin
Re: [PATCH] usb: dwc3: gadget: Fix match_ep callback for NXP UUU tool
On 3/24/25 3:16 PM, Francesco Dolcini wrote: On Mon, Mar 24, 2025 at 02:53:23PM +0100, Marek Vasut wrote: On 3/24/25 1:30 PM, Francesco Dolcini wrote: On Mon, Mar 24, 2025 at 09:26:03AM +0100, Mattijs Korpershoek wrote: Hi Francesco, On lun., mars 24, 2025 at 09:03, Francesco Dolcini wrote: Hello Mattijs, Marek On Thu, Mar 20, 2025 at 10:47:02AM +0100, Mattijs Korpershoek wrote: On mer., mars 19, 2025 at 23:07, Marek Vasut wrote: The UUU tool excepts the interrupt-in endpoint to be ep1in, otherwise it crashes. This is a result of the previous hard-coded EP setup in drivers/usb/gadget/epautoconf.c which did special-case EP allocation for SPL builds, and which was since converted to this callback, but without the special-case EP allocation in SPL part. This reinstates the SPL part in an isolated manner, only for NXP iMX SoCs, only for SPL builds, and only for the ep1in interrupt-in endpoint. UUU can (and in our case is) used also on non-NXP i.MX platforms. What should we do? Do reproduce the problem (UUU tool crashes) on those platforms with recent U-Boot versions (v2024.10+) ? Not tested, my comment is purely based on the code and the commit message. Older U-Boot versions (up to v2024.04, included) are working fine, with UUU used with TI K3 SoCs (AM69, AM62, AM62P). Are you talking about the NXP UUU ? yes, it works just fine on not-NXP SoC. Then please test if it still works, and if not, this patch needs to be expanded to cover TI ... or apply unconditionally in SPL (sigh).
Re: [PATCH] usb: dwc3: gadget: Fix excepts/expects typo
On 24/03/2025 15:39, Marek Vasut wrote:
Fix the excepts typo to expects , no functional change.
Fixes: 0916053ebc56 ("usb: dwc3: gadget: Fix match_ep callback for NXP UUU
tool")
Signed-off-by: Marek Vasut
---
Cc: Alexander Sverdlin
Cc: Felipe Balbi
Cc: Mattijs Korpershoek
Cc: Neil Armstrong
Cc: Thinh Nguyen
Cc: Tom Rini
Cc: u-boot@lists.denx.de
---
drivers/usb/dwc3/gadget.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index 477ecd02098..2b01113d54c 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -1635,7 +1635,7 @@ usb_ep *dwc3_gadget_match_ep(struct usb_gadget *gadget,
/*
* Special workaround for NXP UUU tool in SPL.
*
-* The tool excepts the interrupt-in endpoint to be ep1in,
+* The tool expects the interrupt-in endpoint to be ep1in,
* otherwise it crashes. This is a result of the previous
* hard-coded EP setup in drivers/usb/gadget/epautoconf.c
* which did special-case EP allocation for SPL builds,
Reviewed-by: Neil Armstrong
usb:composite: data abort on second ums launch
Hi, I encountered a data abort on the 2nd "ums 0 mmc 0" command on u-boot-at91 2024.07 with sam9x60-curiosity board. U-Boot> ums 0 mmc 0 UMS: LUN 0, dev mmc 0, hwpart 0, sector 0x0, count 0x1d29000 CTRL+C - Operation aborted U-Boot> ums 0 mmc 0 UMS: LUN 0, dev mmc 0, hwpart 0, sector 0x0, count 0x1d29000 data abort pc : [<27f93428>] lr : [<27ef7e80>] reloc pc : [<23f16428>]lr : [<23e7ae80>] sp : 27ef4cf0 ip : a520 fp : 23f6915c r10: deadbeef r9 : 27ef7e80 r8 : 27f7d2a0 r7 : a520 r6 : r5 : r4 : 27f01668 r3 : r2 : r1 : 27fe1d88 r0 : 27f01668 Flags: nzCV IRQs off FIQs off Mode SVC_32 (T) Code: 45ac d017 68c5 4667 (60fd) 60af >From backtrace the abort happened in fREe_impl(), with some debugging I've localized the abort in fact happened in fsg buffer allocation in fsg_common_init() [1] It looks like the buffer is not freed on driver unregister since fsg_common_release() is only called if fsg_common_init() met an error. [1] https://elixir.bootlin.com/u-boot/v2025.01/source/drivers/usb/gadget/f_mass_storage.c#L2511
[resend v3 03/12] drivers: i3c: Add i3c uclass driver.
From: Dinesh Maniyam
Enable i3c general uclass driver. This uclass driver will have
genaral read and write api to call the specific i3c driver.
Signed-off-by: Dinesh Maniyam
---
drivers/i3c/i3c-uclass.c | 38
include/dw-i3c.h | 1 +
include/i3c.h| 63
3 files changed, 102 insertions(+)
create mode 100644 drivers/i3c/i3c-uclass.c
create mode 100644 include/i3c.h
diff --git a/drivers/i3c/i3c-uclass.c b/drivers/i3c/i3c-uclass.c
new file mode 100644
index 000..644f5788898
--- /dev/null
+++ b/drivers/i3c/i3c-uclass.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025 Altera Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+int dm_i3c_read(struct udevice *dev, u8 dev_number,
+ u8 *buf, int num_bytes)
+{
+ struct dm_i3c_ops *ops = i3c_get_ops(dev);
+
+ if (!ops->read)
+ return -ENOSYS;
+
+ return ops->read(dev, dev_number, buf, num_bytes);
+}
+
+int dm_i3c_write(struct udevice *dev, u8 dev_number,
+u8 *buf, int num_bytes)
+{
+ struct dm_i3c_ops *ops = i3c_get_ops(dev);
+
+ if (!ops->write)
+ return -ENOSYS;
+
+ return ops->write(dev, dev_number, buf, num_bytes);
+}
+
+UCLASS_DRIVER(i3c) = {
+ .id = UCLASS_I3C,
+ .name = "i3c",
+};
diff --git a/include/dw-i3c.h b/include/dw-i3c.h
index e37fd4dc325..920f18bccb4 100644
--- a/include/dw-i3c.h
+++ b/include/dw-i3c.h
@@ -7,6 +7,7 @@
#define _DW_I3C_H_
#include
+#include
#include
#include
#include
diff --git a/include/i3c.h b/include/i3c.h
new file mode 100644
index 000..6ef4982dcf6
--- /dev/null
+++ b/include/i3c.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2025 Altera Corporation
+ */
+
+#include
+
+/**
+ * struct dm_i3c_ops - driver operations for i3c uclass
+ *
+ * Drivers should support these operations unless otherwise noted. These
+ * operations are intended to be used by uclass code, not directly from
+ * other code.
+ */
+struct dm_i3c_ops {
+ /**
+* Transfer messages in I3C mode.
+*
+* @see i3c_transfer
+*
+* @param dev Pointer to controller device driver instance.
+* @param target Pointer to target device descriptor.
+* @param msg Pointer to I3C messages.
+* @param num_msgs Number of messages to transfer.
+*
+* @return @see i3c_transfer
+*/
+ int (*i3c_xfers)(struct i3c_dev_desc *dev,
+struct i3c_priv_xfer *i3c_xfers,
+int i3c_nxfers);
+};
+
+#define i3c_get_ops(dev) ((struct dm_i3c_ops *)(dev)->driver->ops)
+
+/**
+ * @brief Do i3c write
+ *
+ * Uclass general function to start write to i3c target
+ *
+ * @udevice pointer to i3c controller.
+ * @dev_number target device number.
+ * @buf target Buffer to write.
+ * @num_bytes length of bytes to write.
+ *
+ * @return 0 for success
+ */
+int dm_i3c_write(struct udevice *dev, u8 dev_number,
+u8 *buf, int num_bytes);
+
+/**
+ * @brief Do i3c read
+ *
+ * Uclass general function to start read from i3c target
+ *
+ * @udevice pointer to i3c controller.
+ * @dev_number target device number.
+ * @buf target Buffer to read.
+ * @num_bytes length of bytes to read.
+ *
+ * @return 0 for success
+ */
+int dm_i3c_read(struct udevice *dev, u8 dev_number,
+ u8 *buf, int num_bytes);
--
2.26.2
[resend v3 05/12] drivers: i3c: Enabled Kconfig and Makefile for DWI3C
From: Dinesh Maniyam Enable the Kconfig and Makefile for the MIPI DWI3C driver. Signed-off-by: Dinesh Maniyam --- drivers/i3c/Kconfig | 5 + drivers/i3c/Makefile| 1 + drivers/i3c/master/Kconfig | 11 +++ drivers/i3c/master/Makefile | 3 +++ 4 files changed, 20 insertions(+) create mode 100644 drivers/i3c/master/Kconfig create mode 100644 drivers/i3c/master/Makefile diff --git a/drivers/i3c/Kconfig b/drivers/i3c/Kconfig index fa68612787b..d4451057de0 100644 --- a/drivers/i3c/Kconfig +++ b/drivers/i3c/Kconfig @@ -14,3 +14,8 @@ menuconfig I3C If you want I3C support, you should say Y here and also to the specific driver for your bus adapter(s) below. +if I3C + +source "drivers/i3c/master/Kconfig" + +endif # I3C diff --git a/drivers/i3c/Makefile b/drivers/i3c/Makefile index 5bb44a8d64f..5ddc4743c86 100644 --- a/drivers/i3c/Makefile +++ b/drivers/i3c/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 obj-y := i3c-uclass.o device.o master.o +obj-y += master/ diff --git a/drivers/i3c/master/Kconfig b/drivers/i3c/master/Kconfig new file mode 100644 index 000..22bb7c21ea1 --- /dev/null +++ b/drivers/i3c/master/Kconfig @@ -0,0 +1,11 @@ +config DW_I3C_MASTER + tristate "Synospsys DesignWare I3C master driver" + depends on I3C + help + Support for Synopsys DesignWare MIPI I3C Controller. + + For details please see + https://www.synopsys.com/dw/ipdir.php?ds=mipi_i3c + + This driver can also be built as a module. If so, the module + will be called dw-i3c-master. diff --git a/drivers/i3c/master/Makefile b/drivers/i3c/master/Makefile new file mode 100644 index 000..c7562f1aa33 --- /dev/null +++ b/drivers/i3c/master/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_DW_I3C_MASTER) += dw-i3c-master.o -- 2.26.2
[resend v3 01/12] drivers: i3c: Add new i3c uclass id
From: Dinesh Maniyam
Add i3c general uclass id.
Signed-off-by: Dinesh Maniyam
---
include/dm/uclass-id.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 270088ad94f..1d259b439ff 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -78,6 +78,7 @@ enum uclass_id {
UCLASS_I2C_GENERIC, /* Generic I2C device */
UCLASS_I2C_MUX, /* I2C multiplexer */
UCLASS_I2S, /* I2S bus */
+ UCLASS_I3C, /* I3C bus */
UCLASS_IDE, /* IDE device */
UCLASS_IOMMU, /* IOMMU */
UCLASS_IRQ, /* Interrupt controller */
--
2.26.2
[resend v3 06/12] drivers: i3c: Add i3c sandbox simple test.
From: Dinesh Maniyam
Add s simple test for the I3C uclass in sandbox.
Signed-off-by: Dinesh Maniyam
---
arch/sandbox/dts/test.dts | 8 ++
drivers/i3c/Kconfig | 6 +
drivers/i3c/Makefile | 1 +
drivers/i3c/sandbox_i3c.c | 56 +++
test/dm/Makefile | 1 +
test/dm/i3c.c | 34
6 files changed, 106 insertions(+)
create mode 100644 drivers/i3c/sandbox_i3c.c
create mode 100644 test/dm/i3c.c
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index b8f3012873e..491c7dd56b1 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -935,6 +935,14 @@
};
};
+ i3c0 {
+ compatible = "sandbox,i3c";
+ };
+
+ i3c1 {
+ compatible = "sandbox,i3c";
+ };
+
bootcount@0 {
compatible = "u-boot,bootcount-rtc";
rtc = <&rtc_1>;
diff --git a/drivers/i3c/Kconfig b/drivers/i3c/Kconfig
index d4451057de0..d877a744353 100644
--- a/drivers/i3c/Kconfig
+++ b/drivers/i3c/Kconfig
@@ -14,6 +14,12 @@ menuconfig I3C
If you want I3C support, you should say Y here and also to the
specific driver for your bus adapter(s) below.
+config I3C_SANDBOX
+ bool "Enable support for the sandbox I3C"
+ help
+ This is a sandbox I3C used for testing. It provides 2 interfaces and
+ records the settings passed into it.
+
if I3C
source "drivers/i3c/master/Kconfig"
diff --git a/drivers/i3c/Makefile b/drivers/i3c/Makefile
index 5ddc4743c86..d38d2350c9a 100644
--- a/drivers/i3c/Makefile
+++ b/drivers/i3c/Makefile
@@ -2,3 +2,4 @@
obj-y := i3c-uclass.o device.o master.o
obj-y += master/
+obj-$(CONFIG_I3C_SANDBOX) += sandbox_i3c.o
diff --git a/drivers/i3c/sandbox_i3c.c b/drivers/i3c/sandbox_i3c.c
new file mode 100644
index 000..1b497a49041
--- /dev/null
+++ b/drivers/i3c/sandbox_i3c.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025 Altera Corporation
+ */
+
+#include
+#include
+#include
+#include
+
+struct sandbox_i3c_priv {
+ struct i3c_priv_xfer i3c_xfers;
+};
+
+static int sandbox_i3c_priv_read(struct udevice *dev, u8 dev_number,
+u8 *buf, int buf_size)
+{
+ struct sandbox_i3c_priv *priv = dev_get_priv(dev);
+ struct i3c_priv_xfer i3c_xfers;
+
+ i3c_xfers = priv->i3c_xfers;
+ i3c_xfers.data.in = buf;
+ i3c_xfers.len = buf_size;
+
+ return 0;
+}
+
+static int sandbox_i3c_priv_write(struct udevice *dev, u8 dev_number,
+ u8 *buf, int buf_size)
+{
+ struct sandbox_i3c_priv *priv = dev_get_priv(dev);
+ struct i3c_priv_xfer i3c_xfers;
+
+ i3c_xfers = priv->i3c_xfers;
+ i3c_xfers.data.out = buf;
+ i3c_xfers.len = buf_size;
+
+ return 0;
+}
+
+static const struct dm_i3c_ops sandbox_i3c_ops = {
+ .read = sandbox_i3c_priv_read,
+ .write = sandbox_i3c_priv_write,
+};
+
+static const struct udevice_id sandbox_i3c_ids[] = {
+ { .compatible = "sandbox,i3c" },
+ { }
+};
+
+U_BOOT_DRIVER(i3c_sandbox) = {
+ .name = "i3c_sandbox",
+ .id = UCLASS_I3C,
+ .of_match = sandbox_i3c_ids,
+ .ops= &sandbox_i3c_ops,
+};
diff --git a/test/dm/Makefile b/test/dm/Makefile
index e44f3d89e77..c6c12713d7f 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -59,6 +59,7 @@ obj-$(CONFIG_FWU_MDATA_GPT_BLK) += fwu_mdata.o
obj-$(CONFIG_SANDBOX) += host.o
obj-$(CONFIG_DM_HWSPINLOCK) += hwspinlock.o
obj-$(CONFIG_DM_I2C) += i2c.o
+obj-$(CONFIG_I3C) += i3c.o
obj-$(CONFIG_SOUND) += i2s.o
obj-$(CONFIG_CLK_K210_SET_RATE) += k210_pll.o
obj-$(CONFIG_IOMMU) += iommu.o
diff --git a/test/dm/i3c.c b/test/dm/i3c.c
new file mode 100644
index 000..81336e67555
--- /dev/null
+++ b/test/dm/i3c.c
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025 Altera Corporation
+ */
+
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Basic test of the i3c uclass */
+static int dm_test_i3c_base(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+
+ ut_assertok(uclass_get_device(UCLASS_I3C, 0, &dev));
+ ut_assertok(dm_i3c_read(dev, 0, NULL, 1));
+ ut_assertok(dm_i3c_read(dev, 0, NULL, 4));
+ ut_assertok(dm_i3c_write(dev, 0, "AABB", 2));
+ ut_assertok(dm_i3c_write(dev, 0, "AABBCCDD", 4));
+
+ ut_assertok(uclass_get_device(UCLASS_I3C, 1, &dev));
+ ut_assertok(dm_i3c_read(dev, 1, NULL, 1));
+ ut_assertok(dm_i3c_read(dev, 1, NULL, 4));
+ ut_assertok(dm_i3c_write(dev, 1, "AABB", 2));
+ ut_assertok(dm_i3c_write(dev, 1, "AABBCCDD", 4));
+
+ ut_asserteq(-ENODEV, uclass_get_device(UCLASS_I3C, 2, &dev));
+
+ return 0;
+}
+DM_TEST(dm_test_i3c_base, UTF_SCAN_PDATA | UTF_SCAN_FDT);
--
2.26.2
[resend v3 07/12] drivers: i3c: master: Enable probe i3c without slave device
From: Dinesh Maniyam Picked linux i3c driver upstraming patch to fix the issue to probe for i3c controller without slave device attached. With this fix, the ret check will be on command error and will success without slave device attached. Signed-off-by: Dinesh Maniyam --- drivers/i3c/master.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c index a4f2de1302d..6df6410bb12 100644 --- a/drivers/i3c/master.c +++ b/drivers/i3c/master.c @@ -454,6 +454,9 @@ static int i3c_master_rstdaa_locked(struct i3c_master_controller *master, i3c_ccc_cmd_dest_cleanup(&dest); + if (ret) + ret = cmd.err; + return ret; } @@ -509,6 +512,9 @@ static int i3c_master_enec_disec_locked(struct i3c_master_controller *master, ret = i3c_master_send_ccc_cmd_locked(master, &cmd); i3c_ccc_cmd_dest_cleanup(&dest); + if (ret) + ret = cmd.err; + return ret; } -- 2.26.2
[resend v3 09/12] cmd: Add i3c command support.
From: Dinesh Maniyam
Add i3c command file to support select, get i3c device
target list, read and write operation.
Signed-off-by: Dinesh Maniyam
---
cmd/Kconfig| 6 +
cmd/Makefile | 1 +
cmd/i3c.c | 193 +
doc/usage/cmd/i3c.rst | 98 +++
drivers/i3c/master/dw-i3c-master.c | 35 +-
include/dw-i3c.h | 2 +
include/i3c.h | 4 +
7 files changed, 338 insertions(+), 1 deletion(-)
create mode 100644 cmd/i3c.c
create mode 100644 doc/usage/cmd/i3c.rst
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 642cc1116e8..551959731f0 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1327,6 +1327,12 @@ config CMD_I2C
help
I2C support.
+config CMD_I3C
+ bool "i3c"
+ help
+ Enable command to list i3c devices connected to the i3c controller
+ and perform read and write on the connected i3c devices.
+
config CMD_W1
depends on W1
default y if W1
diff --git a/cmd/Makefile b/cmd/Makefile
index 8410be576bb..082470fa104 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -95,6 +95,7 @@ obj-$(CONFIG_CMD_GPIO) += gpio.o
obj-$(CONFIG_CMD_HISTORY) += history.o
obj-$(CONFIG_CMD_HVC) += smccc.o
obj-$(CONFIG_CMD_I2C) += i2c.o
+obj-$(CONFIG_CMD_I3C) += i3c.o
obj-$(CONFIG_CMD_IOTRACE) += iotrace.o
obj-$(CONFIG_CMD_HASH) += hash.o
obj-$(CONFIG_CMD_IDE) += ide.o disk.o
diff --git a/cmd/i3c.c b/cmd/i3c.c
new file mode 100644
index 000..5631f487cc2
--- /dev/null
+++ b/cmd/i3c.c
@@ -0,0 +1,193 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2023 Intel Coporation.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+static struct udevice *currdev;
+static struct udevice *prevdev;
+static struct dw_i3c_master *master;
+
+void low_to_high_bytes(void *data, size_t size)
+{
+ unsigned char *byte_data = (unsigned char *)data;
+ size_t start = 0;
+ size_t end = size - 1;
+
+ while (start < end) {
+ unsigned char temp = byte_data[start];
+
+ byte_data[start] = byte_data[end];
+ byte_data[end] = temp;
+ start++;
+ end--;
+ }
+}
+
+/**
+ * do_i3c() - Handle the "i3c" command-line command
+ * @cmdtp:Command data struct pointer
+ * @flag:Command flag
+ * @argc:Command-line argument count
+ * @argv:Array of command-line arguments
+ *
+ * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
+ * on error.
+ */
+static int do_i3c(struct cmd_tbl *cmdtp, int flag, int argc, char *const
argv[])
+{
+ struct uclass *uc;
+ int ret;
+ struct udevice *dev_list;
+ u32 length, bytes;
+ u8 *data;
+ u8 *rdata;
+ u8 device_num;
+
+ if (argc > 1) {
+ ret = uclass_get_device_by_name(UCLASS_I3C, argv[1], &currdev);
+ if (ret) {
+ if (!strcmp(argv[1], "help"))
+ return CMD_RET_USAGE;
+
+ currdev = prevdev;
+ if (!currdev) {
+ ret = uclass_get(UCLASS_I3C, &uc);
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ uclass_foreach_dev(dev_list, uc)
+ printf("%s (%s)\n", dev_list->name,
dev_list->driver->name);
+
+ printf("i3c master controller is not
initialized: %s\n", argv[1]);
+ return CMD_RET_FAILURE;
+ }
+ } else {
+ master = dev_get_priv(currdev);
+ printf("current dev: %s\n", currdev->name);
+ prevdev = currdev;
+ }
+ } else {
+ if (!currdev) {
+ printf("No i3c device set!\n");
+ return CMD_RET_FAILURE;
+ }
+ printf("dev: %s\n", currdev->name);
+ }
+
+ if (!strcmp(argv[1], "list")) {
+ ret = uclass_get(UCLASS_I3C, &uc);
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ uclass_foreach_dev(dev_list, uc)
+ printf("%s (%s)\n", dev_list->name, dev_list->driver->name);
+ }
+
+ if (!strcmp(argv[1], "current")) {
+ if (!currdev)
+ printf("no current dev!\n");
+ else
+ printf("current dev: %s\n", currdev->name);
+ }
+
+ if ((!strcmp(argv[1], "write")) && !(argv[2] == NULL) && !(argv[3] ==
NULL) &&
+ !(argv[4] == NULL)) {
+ length = hextoul(argv[3], NULL);
+
+ data = (u8 *)malloc(si
Re: [PATCH] efi_loader: remove EFI_BOUNCE_BUFFER
> From: Ilias Apalodimas
> Date: Mon, 17 Mar 2025 21:06:26 +0200
Hi Ilias,
> Hi Mark,
> Thanks for taking a look
>
> On Mon, 17 Mar 2025 at 18:18, Mark Kettenis wrote:
> >
> > > From: Ilias Apalodimas
> > > Date: Mon, 17 Mar 2025 15:38:36 +0200
> > >
> > > The EFI subsystem defines its own bounce buffer for devices that
> > > can't transfer data > 4GB. U-Boot already has a generic BOUNCE_BUFFER
> > > which can be reused instead of defining another symbol.
> > > The only limitation for EFI is that we don't know how big the file a user
> > > chooses to transfer is and as a result we can't depend on allocating the
> > > memory from the malloc area, which can prove too small.
> > >
> > > So allocate an EFI buffer of the correct size and pass it to the DM,
> > > which already supports bounce buffering via bounce_buffer_start_extalign()
> >
> > The existing bounce buffer code servers a completely different purpose
> > though. It exists to make sure that hardware with cache-incoherent
> > DMA can safely do the required cache flushes.
> >
> > This means that:
> >
> > * SoCs with cache-coherent DMA don't necessarily set BOUNCE_BUFFER.
> > Looks like you added that option to all the SoCs where you remove
> > EFI_LOADER_BOUNCE_BUFFER.
>
> Yes, and that has a side effect I should have probably added to the
> commit message. Using the existing bounce buffer will flush caches
> even if it's pointless.
>
> >
> > * SoCs that (now) set BOUNCE_BUFFER may double bounce if the buffers
> > aren't properly aligned. I suppose that this won't happen since
> > efi_disk_add_dev() sets medio.io_align to the device block size
> > which is typically larger than the cache line size.
>
> I think it won't happen indeed but for a different reason. The EFI
> memory we allocate and pass to bounce_buffer_start_extalign() is
> page-aligned.
> The DM subsystem will call that function with either
> blk_buffer_aligned() which always returns 1 or whatever the device has
> defined. The strictest one I found was the virtio one which requires
> page alignment.
>
> Allocating memory from EFI is needed, simply because the current
> bounce buffer API will use the malloc area, which might not be enough.
> Do you think the extra cache flush is a no-go and we should leave the
> code as-is?
I think it is undesirable. I believe it will measurably slow down
loading large files.
So probably best to leave the code as-is. If somebody really cares,
they should probably separate out the cache flushing code from
CONFIG_BOUNCE_BUFFER first. And maybe fix the DM bounce buffer code
such that it supports large buffers.
> > Still the commit message is somewhat misleading; this code doesn't
> > really make us use the DM bounce buffering code.
> >
> > I also spotted a few bugs in the implementation. See below.
>
> [...]
>
> > > +++ b/lib/efi_loader/efi_disk.c
> > > @@ -105,6 +105,8 @@ static efi_status_t efi_disk_rw_blocks(struct
> > > efi_block_io *this,
> > > int blksz;
> > > int blocks;
> > > unsigned long n;
> > > + u64 bb = 0x;
> > > + void *bb_ptr = buffer;
> > >
> > > diskobj = container_of(this, struct efi_disk_obj, ops);
> > > blksz = diskobj->media.block_size;
> > > @@ -113,27 +115,35 @@ static efi_status_t efi_disk_rw_blocks(struct
> > > efi_block_io *this,
> > > EFI_PRINT("blocks=%x lba=%llx blksz=%x dir=%d\n",
> > > blocks, lba, blksz, direction);
> > >
> > > + if (IS_ENABLED(CONFIG_BOUNCE_BUFFER) && (uintptr_t)buffer >= SZ_4G
> > > + buffer_size - 1) {
> >
> > Shouldn't that check be
> >
> > if (IS_ENABLED(CONFIG_BOUNCE_BUFFER) && (uintptr_t)buffer +
> > buffer_size - 1 >= SZ_4G) {
> >
> > ?
>
> Yes...
> I originally had (uintptr_t)buffer > SZ_4G - buffer_size - 1 and avoid
> potential overflows, but then I started to think what happens if
> buffer_size is 4GB and completely messed this up ...
> I think it's (uintptr_t)buffer + buffer_size + 1 >= SZ_4G though,
> because SZ_4G is 0x1. Anyway yes, you are right, I'll fix it
> in v2, but using subtractions.
>
> >
> > > + if (efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS,
> > > EFI_BOOT_SERVICES_DATA,
> > > +buffer_size >> EFI_PAGE_SHIFT, &bb)
> > > != EFI_SUCCESS)
> > > + return EFI_OUT_OF_RESOURCES;
> > > +
> > > + bb_ptr = (void *)(uintptr_t)bb;
> > > + }
> > > /* We only support full block access */
> > > - if (buffer_size & (blksz - 1))
> > > + if (buffer_size & (blksz - 1)) {
> > > + if (buffer != bb_ptr)
> > > + efi_free_pages(bb, buffer_size >> EFI_PAGE_SHIFT);
> > > return EFI_BAD_BUFFER_SIZE;
> > > + }
> >
> > Any reason why you don't check the buffer_size check before allocating
> > the bounce buffer? That way you don't have to worry about freeing it
> > here.
>
> Nop, that code was already there and I didn't move it. I'll move i
Re: Rockchip VOP2 support
> HDMI should work flawlessly but there's still some timings issue with > DW MIPI DSI, perhaps that's something to look into later. Are there still issues are expected with MIPI with this V2 patchset? We are testing this patches with RK3566 and works flawlessly for HDMI, but still no luck with MIPI (although the problem may be somewhere else as well). -- Maciej Pijanowski Engineering Manager GPG: 9963C36AAC3B2B46 https://3mdeb.com | @3mdeb_com OpenPGP_0x9963C36AAC3B2B46.asc Description: OpenPGP public key OpenPGP_signature.asc Description: OpenPGP digital signature
[PATCH] usb: dwc3: gadget: Fix excepts/expects typo
Fix the excepts typo to expects , no functional change.
Fixes: 0916053ebc56 ("usb: dwc3: gadget: Fix match_ep callback for NXP UUU
tool")
Signed-off-by: Marek Vasut
---
Cc: Alexander Sverdlin
Cc: Felipe Balbi
Cc: Mattijs Korpershoek
Cc: Neil Armstrong
Cc: Thinh Nguyen
Cc: Tom Rini
Cc: u-boot@lists.denx.de
---
drivers/usb/dwc3/gadget.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index 477ecd02098..2b01113d54c 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -1635,7 +1635,7 @@ usb_ep *dwc3_gadget_match_ep(struct usb_gadget *gadget,
/*
* Special workaround for NXP UUU tool in SPL.
*
-* The tool excepts the interrupt-in endpoint to be ep1in,
+* The tool expects the interrupt-in endpoint to be ep1in,
* otherwise it crashes. This is a result of the previous
* hard-coded EP setup in drivers/usb/gadget/epautoconf.c
* which did special-case EP allocation for SPL builds,
--
2.47.2
Re: [PATCH] cmd: pmic: add fall through comment
On Mon, Mar 24, 2025 at 06:12:43PM +0100, Heinrich Schuchardt wrote: > Make fall through explicit via comment to allow building with > -Wimplicit-fallthrough. > > Signed-off-by: Heinrich Schuchardt We should say "statement" not "comment" because it's not '/* fallthrough */' and looking at the linux kernel now, using 'fallthrough;' is the way to go as it will use the attribute when possible. -- Tom signature.asc Description: PGP signature
Re: usb:composite: data abort on second ums launch
Hi, Thank you for the report. On lun., mars 24, 2025 at 15:03, Marek Vasut wrote: > On 3/24/25 11:42 AM, Zixun LI wrote: >> Hi, >> >> I encountered a data abort on the 2nd "ums 0 mmc 0" command on >> u-boot-at91 2024.07 with sam9x60-curiosity board. >> >> U-Boot> ums 0 mmc 0 >> UMS: LUN 0, dev mmc 0, hwpart 0, sector 0x0, count 0x1d29000 >> CTRL+C - Operation aborted >> U-Boot> ums 0 mmc 0 >> UMS: LUN 0, dev mmc 0, hwpart 0, sector 0x0, count 0x1d29000 >> data abort >> pc : [<27f93428>] lr : [<27ef7e80>] >> reloc pc : [<23f16428>]lr : [<23e7ae80>] >> sp : 27ef4cf0 ip : a520 fp : 23f6915c >> r10: deadbeef r9 : 27ef7e80 r8 : 27f7d2a0 >> r7 : a520 r6 : r5 : r4 : 27f01668 >> r3 : r2 : r1 : 27fe1d88 r0 : 27f01668 >> Flags: nzCV IRQs off FIQs off Mode SVC_32 (T) >> Code: 45ac d017 68c5 4667 (60fd) 60af >> >> From backtrace the abort happened in fREe_impl(), with some debugging >> I've localized the abort in fact happened in fsg buffer allocation in >> fsg_common_init() [1] >> >> It looks like the buffer is not freed on driver unregister since >> fsg_common_release() is only called if fsg_common_init() met an error. > Can you reproduce this on u-boot/master too ? I've tried to reproduce this on master (2025.04-rc4-g244e61fbb7f5) and I don't reproduce this with the VIM3 board using khadas-vim3_android_ab_defconfig: U-Boot 2025.04-rc4-g244e61fbb7f5 (Mar 24 2025 - 18:15:36 +0100) khadas-vim3 Model: Khadas VIM3 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2) DRAM: 2 GiB (effective 3.8 GiB) Core: 407 devices, 36 uclasses, devicetree: separate MMC: mmc@ffe03000: 0, mmc@ffe05000: 1, mmc@ffe07000: 2 Loading Environment from MMC... MMC Device -1 not found *** Warning - No MMC card found, using default environment In:usbkbd,serial Out: vidconsole,serial Err: vidconsole,serial Net: eth0: ethernet@ff3f Hit any key to stop autoboot: 0 => ums 0 mmc 2 UMS: LUN 0, dev mmc 2, hwpart 0, sector 0x0, count 0x3a3e000 |crq->brequest:0x0 CTRL+C - Operation aborted => ums 0 mmc 2 UMS: LUN 0, dev mmc 2, hwpart 0, sector 0x0, count 0x3a3e000 CTRL+C - Operation aborted => I'll try to understand why it's behaving differently between the sam9x60-curiosity and the vim3. Thanks, Mattijs
Re: [PATCH 3/3] arm: dts: am335x: Add nodes for lcdc, panel and backlight
On Wed, Mar 19, 2025 at 01:25:16PM -0700, Sukrut Bellary wrote: > For AM335x EVM[1], enable nodes required to enable the support for LCD > and PWM backlight. > This is required for the splash screen support. > > [1] AM335x EVM - https://www.ti.com/tool/TMDXEVM3358 > > Signed-off-by: Sukrut Bellary > --- > arch/arm/dts/am335x-evm.dts | 15 ++- > 1 file changed, 14 insertions(+), 1 deletion(-) Can you see how hard moving to OF_UPSTREAM here is first please? Thanks. -- Tom signature.asc Description: PGP signature
Re: [PATCH] usb: dwc3: gadget: Fix excepts/expects typo
Hi Marek,
Thank you for the patch.
On lun., mars 24, 2025 at 15:39, Marek Vasut wrote:
> Fix the excepts typo to expects , no functional change.
>
> Fixes: 0916053ebc56 ("usb: dwc3: gadget: Fix match_ep callback for NXP UUU
> tool")
> Signed-off-by: Marek Vasut
> ---
> Cc: Alexander Sverdlin
> Cc: Felipe Balbi
> Cc: Mattijs Korpershoek
> Cc: Neil Armstrong
> Cc: Thinh Nguyen
> Cc: Tom Rini
> Cc: u-boot@lists.denx.de
> ---
> drivers/usb/dwc3/gadget.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Mattijs Korpershoek
>
[...]
> --
> 2.47.2
[PATCH 3/4] mach-snapdragon: enable DM_USB_GADGET by default
This is required for gadget modes to work on most platforms. It must be disabled for dragonboard410c since that doesn't use dwc3. USB on other MSM8916 platforms isn't supported by qcom_defconfig anyway. Signed-off-by: Caleb Connolly --- arch/arm/Kconfig | 1 + configs/dragonboard410c_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 32b80da9869a1647b7b295d3070964fa11f4fc65..63aefeda9575fec8fc57194358df0819397d088e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1120,8 +1120,9 @@ config ARCH_SNAPDRAGON select SYSRESET select SYSRESET_PSCI imply OF_UPSTREAM imply CMD_DM + imply DM_USB_GADGET config ARCH_SOCFPGA bool "Altera SOCFPGA family" select ARCH_EARLY_INIT_R diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig index 967817f4f58e901fc827b4ed991ddd61d1167efa..5870aae83b4fc8d6897eb0f18cc4eb153d299c11 100644 --- a/configs/dragonboard410c_defconfig +++ b/configs/dragonboard410c_defconfig @@ -59,8 +59,9 @@ CONFIG_DM_PMIC=y CONFIG_PMIC_QCOM=y CONFIG_MSM_SERIAL=y CONFIG_SPMI_MSM=y CONFIG_USB=y +# CONFIG_DM_USB_GADGET is not set CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_MSM=y CONFIG_USB_ULPI_VIEWPORT=y CONFIG_USB_ULPI=y -- 2.49.0
Re: [PATCH v2] cmd: pmic: add fall through comment
On Mon, Mar 24, 2025 at 06:52:53PM +0100, Heinrich Schuchardt wrote: > Make fall through explicit via a fallthrough statement to allow building > with -Wimplicit-fallthrough. > > Signed-off-by: Heinrich Schuchardt Reviewed-by: Tom Rini -- Tom signature.asc Description: PGP signature
Re: [PATCH] lmb: change the return code on lmb_alloc_addr()
On Fri, 14 Mar 2025 12:57:02 +0200, Ilias Apalodimas wrote: > Ben reports a failure to boot the kernel on hardware that starts its > physical memory from 0x0. > The reason is that lmb_alloc_addr(), which is supposed to reserve a > specific address, takes the address as the first argument, but then also > returns the address for success or failure and treats 0 as a failure. > > Since we already know the address change the prototype to return an int. > > [...] Applied to u-boot/master, thanks! [1/1] lmb: change the return code on lmb_alloc_addr() commit: 67be24906feb6efecce70cd5bfdc2ba8f06d3d5b -- Tom
Re: [PATCH v2 00/24] clk: Add clk_resolve_parent_clk() and fix up iMX clock drivers
On Sun, Mar 23, 2025 at 04:58:29PM +0100, Marek Vasut wrote: >Add clk_resolve_parent_clk() to resolve parent clock udevice name >based on clock-names DT property. This is used in SoC clock drivers >to look up the clock name in clock tables, which matches a clock >name in DT clock-names property, and convert it into udevice name >which is used by U-Boot clock framework to look up parent clock in >e.g. clk_register() using uclass_get_device_by_name(UCLASS_CLK, >parent_name, &parent); > >Pass struct udevice pointer through the various iMX clock drivers. Thanks for the effort. Acked-by: Peng Fan BTW: this could only fix partial of the current clk code. The current clock framework is kind of a bit mess. There is more issue is not support multiple clk provider, name should be unique. I was thinking to drop using device for clk, following linux clk driver to use a clk_hw structure for each clk. Regards, Peng > >Marek Vasut (24): > clk: Add clk_resolve_parent_clk() > clk: clk-mux: Fold clk_register_mux() > clk: clk-mux: Use struct udevice instead of struct device > clk: clk-mux: Resolve parent clock by name > clk: imx: Pass struct udevice into imx_clk_mux*() > clk: imx: Pass struct udevice to clk_register_mux() > clk: clk-gate: Use struct udevice instead of struct device > clk: clk-gate: Resolve parent clock by name > clk: imx: gate2: Use struct udevice instead of struct device > clk: imx: gate2: Resolve parent clock by name > clk: imx: Pass struct udevice into imx_clk_gate*() > clk: imx: Pass struct udevice to clk_register_gate*() > clk: clk-composite: Use struct udevice instead of struct device > clk: clk-composite: Resolve parent clock by name > clk: imx: Pass struct udevice into imx_clk_composite*() > clk: imx: Convert clock-osc-* back to osc_* > clk: imx: Pass struct udevice into imx_clk_pllv3*() > clk: imx: pllv3: Resolve parent clock by name > clk: clk-divider: Use struct udevice instead of struct device > clk: imx: Pass struct udevice into imx_clk_divider*() > clk: clk-divider: Resolve parent clock by name > clk: clk-fixed-factor: Use struct udevice instead of struct device > clk: clk-fixed-factor: Resolve parent clock by name > clk: imx: Pass struct udevice into imx_clk_fixed_factor*() > > drivers/clk/clk-composite.c| 4 +- > drivers/clk/clk-divider.c | 7 +- > drivers/clk/clk-fixed-factor.c | 6 +- > drivers/clk/clk-gate.c | 5 +- > drivers/clk/clk-mux.c | 47 +--- > drivers/clk/clk-uclass.c | 18 ++ > drivers/clk/imx/clk-composite-8m.c | 4 +- > drivers/clk/imx/clk-gate2.c| 5 +- > drivers/clk/imx/clk-imx6q.c| 80 +++ > drivers/clk/imx/clk-imx8mm.c | 254 +++-- > drivers/clk/imx/clk-imx8mn.c | 246 ++-- > drivers/clk/imx/clk-imx8mp.c | 348 ++--- > drivers/clk/imx/clk-imx8mq.c | 226 +-- > drivers/clk/imx/clk-imx93.c| 8 +- > drivers/clk/imx/clk-imxrt1020.c| 42 ++-- > drivers/clk/imx/clk-imxrt1050.c| 78 +++ > drivers/clk/imx/clk-imxrt1170.c| 30 +-- > drivers/clk/imx/clk-pllv3.c| 9 +- > drivers/clk/imx/clk.h | 116 +- > include/clk.h | 9 + > include/linux/clk-provider.h | 10 +- > 21 files changed, 783 insertions(+), 769 deletions(-) > >--- >Cc: Adam Ford >Cc: Christoph Niedermaier >Cc: Dong Aisheng >Cc: Fabio Estevam >Cc: Hou Zhiqiang >Cc: Michael Trimarchi >Cc: Peng Fan >Cc: Tim Harvey >Cc: Tom Rini >Cc: u-boot@lists.denx.de >Cc: uboot-...@nxp.com > >-- >2.47.2 >
Re: [PATCH v2 1/4] riscv: dt-binding: k1: Add reset driver binding definition.
On Tue, Mar 11, 2025 at 09:38:48AM +0800, Huan Zhou wrote: > Add dt-binding for reset driver. > > Signed-off-by: Huan Zhou > --- > include/dt-bindings/reset/spacemit-k1-reset.h | 118 > ++ > 1 file changed, 118 insertions(+) Reviewed-by: Leo Yu-Chi Liang
[PATCH V4 0/7] Migrate IMX8, IMX8M and IMX9 to use imx8_cpu
The imx8_cpu driver uses the driver model to represent the processor cores in the dm tree as well as display the processor type and speed on boot. Currently, the imx8_cpu driver only displays the temperature grade of the processor if the processor is IMX9, so in order to display that info, the check in imx8_cpu is changed to check for IMX_TMU and IMX_TMU is implied for IMX8, IMX8M and IMX9 SoC familes. If users want to fall back to the older method to display the SoC type or remove the temperature grade information, they can. Doing this at the SoC family level reduces the number of duplicated config options for each board, and was done at the request of the IMX U-Boot custodian. V4: Make IMX9 select CPU_IMX instead of imply since it appears to be required for all in the platform. Fixed some whitespace in imx8_cpu around the temperature grade message. Re-ordered some items in Kconfig to keep them alphabetical Added more CPU items to the list inside imx8_cpu to match what was done from arch/arm/mach-imx/cpu.c. V3: Added the imply IMX_TMU for the 8M family and added the imply for CPU and CPU_IMX to IMX8, IMX8M and IMX9 families. CPU_IMX depends on CPU, so both have to be selected. V2: Changed the check in imx8_cpu to drop the IMX9 check and instead imply IMX_TMU in the IMX9 family Adam Ford (7): imx: imx9: Imply IMX_TMU cpu: imx8_cpu: Expand get_imx_type_str list of supported CPUs imx: imx8m: Imply IMX_TMU cpu: imx8_cpu: Print Speed grade if IMX_TMU. imx: imx8m: Imply CPU_IMX by default imx: imx8: Imply CPU_IMX by default imx: imx9: Imply CPU_IMX by default arch/arm/mach-imx/imx8/Kconfig | 2 ++ arch/arm/mach-imx/imx8m/Kconfig | 3 ++ arch/arm/mach-imx/imx9/Kconfig | 3 ++ drivers/cpu/imx8_cpu.c | 54 - 4 files changed, 54 insertions(+), 8 deletions(-) -- 2.45.2
[PATCH 0/8] *** Add Ethernet boot support for AM62Ax + phyCORE-AM62 SoMs ***
Add general ethernet boot support for AM62Ax SoC. Some of the work is based on TI's downstream u-boot patches found in [1], patches touching code in mach-k3 and *.yaml board config files. Also, provide defconfigs and device tree changes for phyCORE-AM62x and phyCORE-AM62Ax to support booting via ethernet. [1] https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1307981/sk-am62a-lp-rgmii-boot-mode-problem Andreas Dannenberg (1): arch: arm: mach-k3: r5: am62ax: Update SoC auto-gen data to enable CPSW boot Daniel Schultz (1): arch: arm: dts: k3-am62a7-phyboard-lyra-rdk-u-boot: Disable Ethernet2 Nathan Morrisson (2): arch: arm: mach-k3: am62a7: Probe CPSW NUSS in board_init_f() board: phytec: phycore_am62ax: Share ethernet resources with boot r5 core Wadim Egorov (4): arm: dts: k3-am625-phyboard-lyra-rdk: Add boot phase tag to phy_gmii_sel configs: Add phycore_am62x_r5_ethboot_defconfig configs: phycore_am62x_a53_defconfig: Update for ethernet boot configs: Add phycore_am62ax_r5_ethboot_defconfig .../k3-am625-phyboard-lyra-rdk-u-boot.dtsi| 14 ++--- .../k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi | 2 +- arch/arm/mach-k3/am62ax/am62a7_init.c | 9 arch/arm/mach-k3/r5/am62ax/clk-data.c | 51 ++- arch/arm/mach-k3/r5/am62ax/dev-data.c | 29 ++- board/phytec/phycore_am62ax/MAINTAINERS | 1 + board/phytec/phycore_am62ax/rm-cfg.yaml | 10 ++-- board/phytec/phycore_am62ax/tifs-rm-cfg.yaml | 48 + board/phytec/phycore_am62x/MAINTAINERS| 1 + configs/phycore_am62ax_r5_ethboot_defconfig | 43 configs/phycore_am62x_a53_defconfig | 9 +++- configs/phycore_am62x_r5_ethboot_defconfig| 43 12 files changed, 206 insertions(+), 54 deletions(-) create mode 100644 configs/phycore_am62ax_r5_ethboot_defconfig create mode 100644 configs/phycore_am62x_r5_ethboot_defconfig -- 2.34.1
[PATCH V4 3/7] imx: imx8m: Imply IMX_TMU
If the CPU Information is displayed from imx8_cpu, it displays the cpu temperature grade and operating temperature if CONFIG_IMX9 is defined. This behavior is similar to what happens mach-imx/cpu.c, except that the latter checks for IMX_THERMAL or IMX_TMU. In preparation to make imx8_cpu act like the previous implementation for any CPU, make IMX8M imply IMX_TMU so it will be always displayed unless a user decides to disable it. Signed-off-by: Adam Ford --- arch/arm/mach-imx/imx8m/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 89f2b50c8a2..8ee699a343c 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -8,6 +8,7 @@ config IMX8M select LTO select ROM_UNIFIED_SECTIONS select ARMV8_CRYPTO + imply IMX_TMU config IMX8MQ bool -- 2.45.2
Re: [PATCH v8 02/19] pinctrl: nxp: add a pin controller driver based on SCMI pin control protocol
On Sat, Mar 22, 2025 at 01:46:02AM +0100, Marek Vasut wrote:
>On 3/21/25 8:15 AM, Alice Guo (OSS) wrote:
>
>[...]
>
>> +static int imx_scmi_pinctrl_probe(struct udevice *dev)
>> +{
>> +struct imx_scmi_pinctrl_priv *priv = dev_get_priv(dev);
>> +
>> +priv->daisy_offset = is_imx93() ? DAISY_OFFSET_IMX93 :
>> DAISY_OFFSET_IMX95;
>> +
>> +return devm_scmi_of_get_channel(dev);
>> +}
>> +
>> +static int imx_scmi_pinctrl_bind(struct udevice *dev)
>> +{
>> +if (IS_ENABLED(CONFIG_IMX95))
>> +return 0;
>
>Why does this driver support iMX93 , but it is explicitly not going to bind
>on iMX93 ?
>
>In case the MX93 support is going to be added, you probably need something
>like:
>
>if (IS_ENABLED(CONFIG_IMX95) && is_imx95())
> return 0;
>
>Because IS_ENABLED(CONFIG_IMX95) does not automatically imply that this code
>is started on MX95 , that is when is_imx95() comes into play and does runtime
>check for MX95 .
>
>> +return -ENODEV;
>> +}
>> +
>> +U_BOOT_DRIVER(scmi_pinctrl_imx) = {
>> +.name = "scmi_pinctrl_imx",
>> +.id = UCLASS_PINCTRL,
>> +.bind = imx_scmi_pinctrl_bind,
>> +.probe = imx_scmi_pinctrl_probe,
>> +.priv_auto = sizeof(struct imx_scmi_pinctrl_priv),
>> +.ops = &imx_scmi_pinctrl_ops,
>> +.flags = DM_FLAG_PRE_RELOC,
>> +};
>> diff --git a/include/scmi_protocols.h b/include/scmi_protocols.h
>> index 7abb2a6f36b..279ebbad440 100644
>> --- a/include/scmi_protocols.h
>> +++ b/include/scmi_protocols.h
>> @@ -24,6 +24,7 @@ enum scmi_std_protocol {
>> SCMI_PROTOCOL_ID_SENSOR = 0x15,
>> SCMI_PROTOCOL_ID_RESET_DOMAIN = 0x16,
>> SCMI_PROTOCOL_ID_VOLTAGE_DOMAIN = 0x17,
>> +SCMI_PROTOCOL_ID_PINCTRL = 0x19,
>If this is the IMX specific pinctrl protocol, please make sure to name it
>accordingly , SCMI_PROTOCOL_ID_PINCTRL_IMX or something .
This ID is generic ID, not i.MX specific.
i.MX SCMI pinctrl follows ARM SCMI spec, but i.MX pinctrl bindings
are different compared with ARM SCMI generic pinconf bindings, so we
need a separate driver for i.MX.
Regards,
Peng
Re: [PATCH v2 3/4] riscv: dts: k1: add reset controller node in device tree
On Tue, Mar 11, 2025 at 09:38:50AM +0800, Huan Zhou wrote: > Add reset-controller in k1 device tree. > > Signed-off-by: Huan Zhou > --- > arch/riscv/dts/k1.dtsi | 15 +++ > 1 file changed, 15 insertions(+) Reviewed-by: Leo Yu-Chi Liang
Re: Problem with UART in U-Boot.
On Sat, Mar 22, 2025 at 06:49:11PM +1000, . wrote: > Device: Orange Pi 5. > > U-Boot is installed in the SPI memory. I connected the device to my laptop > > via UART, CH340G adapter, 150 baud rate. Connected: gnd-gnd, tx-rx, > > rx-tx. Are you sure your serial adapter works at the same voltage level as your board? It sounds like an electrical/hardware problem instead of fault of U-Boot code. > > As a result, when connecting a more powerful power supply, the output to > > the terminal works, but the input does not work from the word at all. > > When connecting a less powerful power supply, the input works partially: > > there was an inscription like "press any key to interrupt startup", I > > pressed Enter and everything worked, but when I tried to enter something, > > either question marks (�) were entered, or nothing was entered, or even the > > text was erased. > > > > When installing EDK2-RK3588 (UEFI) instead of U-Boot, both input and output > > worked on any power supply, and everything worked fine, the speed was the > > same — 1500,000 baud, and the same adapter. > > > > It is necessary to install U-Boot. Can you tell me how to fix the input in > > U-Boot? Version v2025.01. >- 0 ' Thanks, Yao Zi
Re: [PATCH] riscv: dts: cv18xx: Drop unused dummy clocks
On Fri, Mar 07, 2025 at 05:09:22PM +, Yao Zi wrote:
> Introduced in commit 5a4e0625ac77 ("riscv: dts: sophgo: Add ethernet
> node"), eth_{csrclk,ptpclk} were used as placeholders for ethernet
> controller. As the real clock controller has been added, drop them to
> clean the devicetree up.
>
> Signed-off-by: Yao Zi
> ---
> arch/riscv/dts/cv18xx.dtsi | 14 --
> 1 file changed, 14 deletions(-)
Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH v2 2/4] riscv: reset: k1: Add reset driver
On Tue, Mar 11, 2025 at 09:38:49AM +0800, Huan Zhou wrote: > Add spacemit reset driver. > > Signed-off-by: Huan Zhou > --- > drivers/reset/Kconfig | 7 + > drivers/reset/Makefile| 1 + > drivers/reset/reset-spacemit-k1.c | 548 > ++ > 3 files changed, 556 insertions(+) Reviewed-by: Leo Yu-Chi Liang
[PATCH 3/8] configs: phycore_am62x_a53_defconfig: Update for ethernet boot
Add support for ethernet boot in the A53 SPL. Increase the SPL Size limit and update SPL_STACK_R_ADDR. Signed-off-by: Wadim Egorov --- configs/phycore_am62x_a53_defconfig | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/configs/phycore_am62x_a53_defconfig b/configs/phycore_am62x_a53_defconfig index 0494fc408b7..0111ad12e20 100644 --- a/configs/phycore_am62x_a53_defconfig +++ b/configs/phycore_am62x_a53_defconfig @@ -19,14 +19,15 @@ CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y -CONFIG_SPL_STACK_R_ADDR=0x8200 +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK_R_ADDR=0x8300 CONFIG_SPL_TEXT_BASE=0x8008 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x80c8 CONFIG_SPL_BSS_MAX_SIZE=0x8 CONFIG_SPL_STACK_R=y CONFIG_SYS_BOOTM_LEN=0x80 -CONFIG_SPL_SIZE_LIMIT=0x4 +CONFIG_SPL_SIZE_LIMIT=0x8 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x800 CONFIG_ENV_OFFSET_REDUND=0x6c CONFIG_SPL_FS_FAT=y @@ -51,11 +52,15 @@ CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MMCSD_RAW_MODE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 +CONFIG_SPL_DMA=y CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_ETH=y CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_NET=y +CONFIG_SPL_NET_VCI_STRING="AM62X U-Boot A53 SPL" CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_DEVICE=y # CONFIG_SPL_SPI_FLASH_TINY is not set -- 2.34.1
Re: [PATCH v2 4/4] Add reset config options for k1
On Tue, Mar 11, 2025 at 09:38:51AM +0800, Huan Zhou wrote: > Add RESET_SPACEMIT_K1 option in config > > Signed-off-by: Huan Zhou > --- > arch/riscv/cpu/k1/Kconfig | 1 + > configs/bananapi-f3_defconfig | 1 + > 2 files changed, 2 insertions(+) Reviewed-by: Leo Yu-Chi Liang
Re: [PATCH v2 00/24] clk: Add clk_resolve_parent_clk() and fix up iMX clock drivers
On 3/25/25 12:33 AM, Adam Ford wrote: On Sun, Mar 23, 2025 at 11:01 AM Marek Vasut wrote: Add clk_resolve_parent_clk() to resolve parent clock udevice name based on clock-names DT property. This is used in SoC clock drivers to look up the clock name in clock tables, which matches a clock name in DT clock-names property, and convert it into udevice name which is used by U-Boot clock framework to look up parent clock in e.g. clk_register() using uclass_get_device_by_name(UCLASS_CLK, parent_name, &parent); Pass struct udevice pointer through the various iMX clock drivers. Marek Vasut (24): clk: Add clk_resolve_parent_clk() clk: clk-mux: Fold clk_register_mux() clk: clk-mux: Use struct udevice instead of struct device clk: clk-mux: Resolve parent clock by name clk: imx: Pass struct udevice into imx_clk_mux*() clk: imx: Pass struct udevice to clk_register_mux() clk: clk-gate: Use struct udevice instead of struct device clk: clk-gate: Resolve parent clock by name clk: imx: gate2: Use struct udevice instead of struct device clk: imx: gate2: Resolve parent clock by name clk: imx: Pass struct udevice into imx_clk_gate*() clk: imx: Pass struct udevice to clk_register_gate*() clk: clk-composite: Use struct udevice instead of struct device clk: clk-composite: Resolve parent clock by name clk: imx: Pass struct udevice into imx_clk_composite*() clk: imx: Convert clock-osc-* back to osc_* clk: imx: Pass struct udevice into imx_clk_pllv3*() clk: imx: pllv3: Resolve parent clock by name clk: clk-divider: Use struct udevice instead of struct device clk: imx: Pass struct udevice into imx_clk_divider*() clk: clk-divider: Resolve parent clock by name clk: clk-fixed-factor: Use struct udevice instead of struct device clk: clk-fixed-factor: Resolve parent clock by name clk: imx: Pass struct udevice into imx_clk_fixed_factor*() drivers/clk/clk-composite.c| 4 +- drivers/clk/clk-divider.c | 7 +- drivers/clk/clk-fixed-factor.c | 6 +- drivers/clk/clk-gate.c | 5 +- drivers/clk/clk-mux.c | 47 +--- drivers/clk/clk-uclass.c | 18 ++ drivers/clk/imx/clk-composite-8m.c | 4 +- drivers/clk/imx/clk-gate2.c| 5 +- drivers/clk/imx/clk-imx6q.c| 80 +++ drivers/clk/imx/clk-imx8mm.c | 254 +++-- drivers/clk/imx/clk-imx8mn.c | 246 ++-- drivers/clk/imx/clk-imx8mp.c | 348 ++--- drivers/clk/imx/clk-imx8mq.c | 226 +-- drivers/clk/imx/clk-imx93.c| 8 +- drivers/clk/imx/clk-imxrt1020.c| 42 ++-- drivers/clk/imx/clk-imxrt1050.c| 78 +++ drivers/clk/imx/clk-imxrt1170.c| 30 +-- drivers/clk/imx/clk-pllv3.c| 9 +- drivers/clk/imx/clk.h | 116 +- include/clk.h | 9 + include/linux/clk-provider.h | 10 +- 21 files changed, 783 insertions(+), 769 deletions(-) For the series: Tested-by: Adam Ford #imx8[mnp] beacon-kit Thank you !
[PATCH v2 03/10] test/py/tests: Move "setup_image" from test_ut.py to fs_helper.py
The generic function in test_ut.py to create a disk image with partition
table can be useful outside of test_ut.py so move it to be available
more clearly.
To make this a bit more easily used library function, make use of
check_call directly rather than calling things though u_boot_utils. In
turn, to more easily handle stdin here, use the shell "printf" utility
to pass sfdisk the specification to create as we do not have an actual
file descriptor to use here.
Signed-off-by: Tom Rini
---
Changes in v2:
- Rebase on next after the ubman series.
---
test/py/tests/fs_helper.py | 34 ++
test/py/tests/test_ut.py | 38 --
2 files changed, 38 insertions(+), 34 deletions(-)
diff --git a/test/py/tests/fs_helper.py b/test/py/tests/fs_helper.py
index ccfc0201a49f..f3e81b6bc61b 100644
--- a/test/py/tests/fs_helper.py
+++ b/test/py/tests/fs_helper.py
@@ -69,6 +69,40 @@ def mk_fs(config, fs_type, size, prefix, src_dir=None,
size_gran = 0x10):
call(f'rm -f {fs_img}', shell=True)
raise
+def setup_image(ubman, devnum, part_type, img_size=20, second_part=False,
+basename='mmc'):
+"""Create a disk image with a single partition
+
+Args:
+ubman (ConsoleBase): Console to use
+devnum (int): Device number to use, e.g. 1
+part_type (int): Partition type, e.g. 0xc for FAT32
+img_size (int): Image size in MiB
+second_part (bool): True to contain a small second partition
+basename (str): Base name to use in the filename, e.g. 'mmc'
+
+Returns:
+tuple:
+str: Filename of MMC image
+str: Directory name of scratch directory
+"""
+fname = os.path.join(ubman.config.source_dir, f'{basename}{devnum}.img')
+mnt = os.path.join(ubman.config.persistent_data_dir, 'scratch')
+
+spec = f'type={part_type:x}, size={img_size - 2}M, start=1M, bootable'
+if second_part:
+spec += '\ntype=c'
+
+try:
+check_call(f'mkdir -p {mnt}', shell=True)
+check_call(f'qemu-img create {fname} 20M', shell=True)
+check_call(f'printf "{spec}" | sfdisk {fname}', shell=True)
+except CalledProcessError:
+call(f'rm -f {fname}', shell=True)
+raise
+
+return fname, mnt
+
# Just for trying out
if __name__ == "__main__":
import collections
diff --git a/test/py/tests/test_ut.py b/test/py/tests/test_ut.py
index ea0c43cd4fcc..3a3f12d08984 100644
--- a/test/py/tests/test_ut.py
+++ b/test/py/tests/test_ut.py
@@ -27,43 +27,13 @@ def mkdir_cond(dirname):
if not os.path.exists(dirname):
os.mkdir(dirname)
-def setup_image(ubman, devnum, part_type, img_size=20, second_part=False,
-basename='mmc'):
-"""Create a disk image with a single partition
-
-Args:
-ubman (ConsoleBase): Console to use
-devnum (int): Device number to use, e.g. 1
-part_type (int): Partition type, e.g. 0xc for FAT32
-img_size (int): Image size in MiB
-second_part (bool): True to contain a small second partition
-basename (str): Base name to use in the filename, e.g. 'mmc'
-
-Returns:
-tuple:
-str: Filename of MMC image
-str: Directory name of scratch directory
-"""
-fname = os.path.join(ubman.config.source_dir, f'{basename}{devnum}.img')
-mnt = os.path.join(ubman.config.persistent_data_dir, 'scratch')
-mkdir_cond(mnt)
-
-spec = f'type={part_type:x}, size={img_size - 2}M, start=1M, bootable'
-if second_part:
-spec += '\ntype=c'
-
-utils.run_and_log(ubman, f'qemu-img create {fname} 20M')
-utils.run_and_log(ubman, f'sfdisk {fname}',
- stdin=spec.encode('utf-8'))
-return fname, mnt
-
def setup_bootmenu_image(ubman):
"""Create a 20MB disk image with a single ext4 partition
This is modelled on Armbian 22.08 Jammy
"""
mmc_dev = 4
-fname, mnt = setup_image(ubman, mmc_dev, 0x83)
+fname, mnt = fs_helper.setup_image(ubman, mmc_dev, 0x83)
script = '''# DO NOT EDIT THIS FILE
#
@@ -179,7 +149,7 @@ booti ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}
def setup_bootflow_image(ubman):
"""Create a 20MB disk image with a single FAT partition"""
mmc_dev = 1
-fname, mnt = setup_image(ubman, mmc_dev, 0xc, second_part=True)
+fname, mnt = fs_helper.setup_image(ubman, mmc_dev, 0xc, second_part=True)
vmlinux = 'vmlinuz-5.3.7-301.fc31.armv7hl'
initrd = 'initramfs-5.3.7-301.fc31.armv7hl.img'
@@ -545,8 +515,8 @@ def setup_efi_image(ubman):
"""Create a 20MB disk image with an EFI app on it"""
devnum = 1
basename = 'flash'
-fname, mnt = setup_image(ubman, devnum, 0xc, second_part=True,
- basename=basename)
+fname, mnt = fs_helper.setup_image(ubman, devnum, 0xc, second_part=True,
+ basename=basename)
efi_dir
[PATCH v2 17/24] clk: imx: Pass struct udevice into imx_clk_pllv3*()
Pass struct udevice * into imx_clk_pllv3*() functions, so the
clock core would have access to parent struct udevice *.
Signed-off-by: Marek Vasut
---
Cc: Adam Ford
Cc: Christoph Niedermaier
Cc: Dong Aisheng
Cc: Fabio Estevam
Cc: Hou Zhiqiang
Cc: Michael Trimarchi
Cc: Peng Fan
Cc: Tim Harvey
Cc: Tom Rini
Cc: u-boot@lists.denx.de
Cc: uboot-...@nxp.com
---
V2: Rebase on u-boot/next with additional clock patches
---
drivers/clk/imx/clk-imx6q.c | 6 +++---
drivers/clk/imx/clk-imxrt1020.c | 4 ++--
drivers/clk/imx/clk-imxrt1050.c | 8
drivers/clk/imx/clk-imxrt1170.c | 6 +++---
drivers/clk/imx/clk-pllv3.c | 6 +++---
drivers/clk/imx/clk.h | 6 +++---
6 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index d9eb43d82be..8327aea8950 100644
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -46,10 +46,10 @@ static int imx6q_clk_probe(struct udevice *dev)
base = (void *)ANATOP_BASE_ADDR;
clk_dm(IMX6QDL_CLK_PLL2,
- imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc",
+ imx_clk_pllv3(dev, IMX_PLLV3_GENERIC, "pll2_bus", "osc",
base + 0x30, 0x1));
clk_dm(IMX6QDL_CLK_PLL3_USB_OTG,
- imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc",
+ imx_clk_pllv3(dev, IMX_PLLV3_USB, "pll3_usb_otg", "osc",
base + 0x10, 0x3));
clk_dm(IMX6QDL_CLK_PLL3_60M,
imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8));
@@ -58,7 +58,7 @@ static int imx6q_clk_probe(struct udevice *dev)
clk_dm(IMX6QDL_CLK_PLL2_PFD2_396M,
imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2));
clk_dm(IMX6QDL_CLK_PLL6,
- imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3));
+ imx_clk_pllv3(dev, IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0,
0x3));
clk_dm(IMX6QDL_CLK_PLL6_ENET,
imx_clk_gate(dev, "pll6_enet", "pll6", base + 0xe0, 13));
diff --git a/drivers/clk/imx/clk-imxrt1020.c b/drivers/clk/imx/clk-imxrt1020.c
index 40cba218c29..62c00ba3314 100644
--- a/drivers/clk/imx/clk-imxrt1020.c
+++ b/drivers/clk/imx/clk-imxrt1020.c
@@ -38,10 +38,10 @@ static int imxrt1020_clk_probe(struct udevice *dev)
base = (void *)ofnode_get_addr(ofnode_by_compatible(ofnode_null(),
"fsl,imxrt-anatop"));
clk_dm(IMXRT1020_CLK_PLL2_SYS,
- imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_sys", "osc",
+ imx_clk_pllv3(dev, IMX_PLLV3_GENERIC, "pll2_sys", "osc",
base + 0x30, 0x1));
clk_dm(IMXRT1020_CLK_PLL3_USB_OTG,
- imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc",
+ imx_clk_pllv3(dev, IMX_PLLV3_USB, "pll3_usb_otg", "osc",
base + 0x10, 0x1));
/* PLL bypass out */
diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c
index 71d5fa8a90e..02f7b05da5f 100644
--- a/drivers/clk/imx/clk-imxrt1050.c
+++ b/drivers/clk/imx/clk-imxrt1050.c
@@ -49,17 +49,17 @@ static int imxrt1050_clk_probe(struct udevice *dev)
pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
clk_dm(IMXRT1050_CLK_PLL1_ARM,
- imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_arm", "pll1_arm_ref_sel",
+ imx_clk_pllv3(dev, IMX_PLLV3_SYS, "pll1_arm", "pll1_arm_ref_sel",
base + 0x0, 0x7f));
clk_dm(IMXRT1050_CLK_PLL2_SYS,
- imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_sys", "pll2_sys_ref_sel",
+ imx_clk_pllv3(dev, IMX_PLLV3_GENERIC, "pll2_sys",
"pll2_sys_ref_sel",
base + 0x30, 0x1));
clk_dm(IMXRT1050_CLK_PLL3_USB_OTG,
- imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg",
+ imx_clk_pllv3(dev, IMX_PLLV3_USB, "pll3_usb_otg",
"pll3_usb_otg_ref_sel",
base + 0x10, 0x1));
clk_dm(IMXRT1050_CLK_PLL5_VIDEO,
- imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "pll5_video_ref_sel",
+ imx_clk_pllv3(dev, IMX_PLLV3_AV, "pll5_video",
"pll5_video_ref_sel",
base + 0xa0, 0x7f));
/* PLL bypass out */
diff --git a/drivers/clk/imx/clk-imxrt1170.c b/drivers/clk/imx/clk-imxrt1170.c
index 7e06504584f..caf34a55459 100644
--- a/drivers/clk/imx/clk-imxrt1170.c
+++ b/drivers/clk/imx/clk-imxrt1170.c
@@ -121,13 +121,13 @@ static int imxrt1170_clk_probe(struct udevice *dev)
imx_clk_fixed_factor("rcosc48M_div2", "rcosc48M", 1, 2));
clk_dm(IMXRT1170_CLK_PLL_ARM,
- imx_clk_pllv3(IMX_PLLV3_SYS, "pll_arm", "osc",
+ imx_clk_pllv3(dev, IMX_PLLV3_SYS, "pll_arm", "osc",
base + 0x200, 0xff));
clk_dm(IMXRT1170_CLK_PLL3,
- imx_clk_pllv3(IMX_PLLV3_GENERICV2, "pll3_sys", "osc"
[PATCH v2] net: dhcp6: Send DHCPv6 using multicast MAC
From: Sean Edmond
In IPv6, the broadcast MAC address is not used. Instead, it should use
the multicast address (see RFC RFC2464).
Add IPV6_ALL_NODE_ETH_ADDR macro for clarity.
Signed-off-by: Sean Edmond
---
include/net6.h | 10 ++
net/dhcpv6.c | 12 ++--
net/dhcpv6.h | 8 +++-
3 files changed, 23 insertions(+), 7 deletions(-)
diff --git a/include/net6.h b/include/net6.h
index 1ed989e584a..2ceeaba0639 100644
--- a/include/net6.h
+++ b/include/net6.h
@@ -90,6 +90,16 @@ struct udp_hdr {
0x00, 0x00, 0x00, 0x00, \
0x00, 0x00, 0x00, 0x00, \
0x00, 0x00, 0x00, 0x02 } } }
+/*
+ * With IPv6, the broadcast MAC address is not used. Instead, it should use
+ * the multicast address (see RFC RFC2464 section 7)
+ */
+#define IPV6_ALL_NODE_ETH_ADDR(_ip6_addr) {0x33, \
+ 0x33, \
+ _ip6_addr.in6_u.u6_addr8[12], \
+ _ip6_addr.in6_u.u6_addr8[13], \
+ _ip6_addr.in6_u.u6_addr8[14], \
+ _ip6_addr.in6_u.u6_addr8[15]}
#define IPV6_LINK_LOCAL_PREFIX 0xfe80
#define IPV6_LINK_LOCAL_MASK 0xffb0 /* The first 10-bit of address mask. */
diff --git a/net/dhcpv6.c b/net/dhcpv6.c
index 54619ee6983..984a64a4ff3 100644
--- a/net/dhcpv6.c
+++ b/net/dhcpv6.c
@@ -29,6 +29,10 @@
int updated_sol_max_rt_ms = SOL_MAX_RT_MS;
/* state machine parameters/variables */
struct dhcp6_sm_params sm_params;
+/* DHCPv6 all server IP6 address */
+const struct in6_addr dhcp_mcast_ip6 = DHCP6_MULTICAST_ADDR;
+/* IPv6 multicast ethernet address */
+const u8 net_dhcp6_mcast_ethaddr[6] = IPV6_ALL_NODE_ETH_ADDR(dhcp_mcast_ip6);
static void dhcp6_state_machine(bool timeout, uchar *rx_pkt, unsigned int len);
@@ -171,7 +175,6 @@ static int dhcp6_add_option(int option_id, uchar *pkt)
*/
static void dhcp6_send_solicit_packet(void)
{
- struct in6_addr dhcp_bcast_ip6;
int len = 0;
uchar *pkt;
uchar *dhcp_pkt_start_ptr;
@@ -200,9 +203,8 @@ static void dhcp6_send_solicit_packet(void)
len = pkt - dhcp_pkt_start_ptr;
/* send UDP packet to DHCP6 multicast address */
- string_to_ip6(DHCP6_MULTICAST_ADDR, sizeof(DHCP6_MULTICAST_ADDR),
&dhcp_bcast_ip6);
net_set_udp_handler(dhcp6_handler);
- net_send_udp_packet6((uchar *)net_bcast_ethaddr, &dhcp_bcast_ip6,
+ net_send_udp_packet6((uchar *)net_dhcp6_mcast_ethaddr, (struct in6_addr
*)&dhcp_mcast_ip6,
PORT_DHCP6_S, PORT_DHCP6_C, len);
}
@@ -218,7 +220,6 @@ static void dhcp6_send_solicit_packet(void)
*/
static void dhcp6_send_request_packet(void)
{
- struct in6_addr dhcp_bcast_ip6;
int len = 0;
uchar *pkt;
uchar *dhcp_pkt_start_ptr;
@@ -252,9 +253,8 @@ static void dhcp6_send_request_packet(void)
len = pkt - dhcp_pkt_start_ptr;
/* send UDP packet to DHCP6 multicast address */
- string_to_ip6(DHCP6_MULTICAST_ADDR, strlen(DHCP6_MULTICAST_ADDR),
&dhcp_bcast_ip6);
net_set_udp_handler(dhcp6_handler);
- net_send_udp_packet6((uchar *)net_bcast_ethaddr, &dhcp_bcast_ip6,
+ net_send_udp_packet6((uchar *)net_dhcp6_mcast_ethaddr, (struct in6_addr
*)&dhcp_mcast_ip6,
PORT_DHCP6_S, PORT_DHCP6_C, len);
}
diff --git a/net/dhcpv6.h b/net/dhcpv6.h
index 65c8e4c71d3..d41a3c30615 100644
--- a/net/dhcpv6.h
+++ b/net/dhcpv6.h
@@ -40,7 +40,13 @@
/* vendor-class-data to send in vendor clas option */
#define DHCP6_VCI_STRING "U-Boot"
-#define DHCP6_MULTICAST_ADDR "ff02::1:2" /* DHCP multicast address */
+/*
+ * All-DHCPv6 server multicast address
+ */
+#define DHCP6_MULTICAST_ADDR { { { 0xFF, 0x02, 0x00, 0x00, \
+ 0x00, 0x00,
0x00, 0x00, \
+ 0x00, 0x00,
0x00, 0x00, \
+ 0x00, 0x01,
0x00, 0x02 } } }
/* DHCP6 States supported */
enum dhcp6_state {
--
2.34.1
Re: [PATCH 2/8] env: Rename SYS_REDUNDAND_ENVIRONMENT to ENV_REDUNDAND_ENVIRONMENT
On 3/24/25 1:33 PM, Quentin Schulz wrote: Hi Marek, On 3/22/25 10:55 PM, Marek Vasut wrote: Rename the variable and add ENV_ prefix, so that all configuration options which are related to environment would have an CONFIG_ENV_ prefix. No functional change. Signed-off-by: Marek Vasut --- [...] diff --git a/env/Kconfig b/env/Kconfig index a177a354c8b..9ef45a7e3fe 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -463,7 +463,7 @@ config ENV_IS_IN_UBI the environment in. This will enable redundant environments in UBI. It is assumed that both volumes are in the same MTD partition. -config SYS_REDUNDAND_ENVIRONMENT +config ENV_REDUNDAND_ENVIRONMENT Do either of the following: 1) fix typo: s/REDUNDAND/REDUNDANT/ 2) shorten name to be consistent with other symbols and avoid "env[...]environment" redundancy: config ENV_REDUND CONFIG_ENV_REDUNDANT works for you ?
[PATCH v1 1/2] pinctrl: qcom: add driver for SA8775P SoC
Add pinctrl and GPIO driver for SA8775P. Driver code is based on the
similar U-Boot and Linux drivers.
Signed-off-by: Varadarajan Narayanan
---
drivers/pinctrl/qcom/Kconfig | 7 +
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-sa8775p.c | 623 +
3 files changed, 631 insertions(+)
create mode 100644 drivers/pinctrl/qcom/pinctrl-sa8775p.c
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index d3eb6998551..b7dbe0ac0d6 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -41,6 +41,13 @@ config PINCTRL_QCOM_QCS404
Say Y here to enable support for pinctrl on the Snapdragon QCS404 SoC,
as well as the associated GPIO driver.
+config PINCTRL_QCOM_SA8775P
+ bool "Qualcomm SA8775P Pinctrl"
+ select PINCTRL_QCOM
+ help
+ Say Y here to enable support for pinctrl on the Snapdragon SA8775P
SoC,
+ as well as the associated GPIO driver.
+
config PINCTRL_QCOM_SDM845
bool "Qualcomm SDM845 GCC"
select PINCTRL_QCOM
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 06d3c95f93a..2379464ed32 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_PINCTRL_QCOM_IPQ4019) += pinctrl-ipq4019.o
obj-$(CONFIG_PINCTRL_QCOM_APQ8096) += pinctrl-apq8096.o
obj-$(CONFIG_PINCTRL_QCOM_QCM2290) += pinctrl-qcm2290.o
obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o
+obj-$(CONFIG_PINCTRL_QCOM_SA8775P) += pinctrl-sa8775p.o
obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o
obj-$(CONFIG_PINCTRL_QCOM_SM6115) += pinctrl-sm6115.o
obj-$(CONFIG_PINCTRL_QCOM_SM8150) += pinctrl-sm8150.o
diff --git a/drivers/pinctrl/qcom/pinctrl-sa8775p.c
b/drivers/pinctrl/qcom/pinctrl-sa8775p.c
new file mode 100644
index 000..c719efb0b1c
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-sa8775p.c
@@ -0,0 +1,623 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#include
+
+#include "pinctrl-qcom.h"
+
+#define MAX_PIN_NAME_LEN 32
+static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
+
+typedef unsigned int msm_pin_function[10];
+#define SA8775_PIN_OFFSET 0x10
+
+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9)\
+ { \
+ msm_mux_gpio, /* gpio mode */ \
+ msm_mux_##f1, \
+ msm_mux_##f2, \
+ msm_mux_##f3, \
+ msm_mux_##f4, \
+ msm_mux_##f5, \
+ msm_mux_##f6, \
+ msm_mux_##f7, \
+ msm_mux_##f8, \
+ msm_mux_##f9\
+ }
+
+#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
+ { \
+ .name = pg_name,\
+ .ctl_reg = ctl, \
+ .io_reg = 0,\
+ .pull_bit = pull, \
+ .drv_bit = drv, \
+ .oe_bit = -1, \
+ .in_bit = -1, \
+ .out_bit = -1, \
+ }
+
+#define UFS_RESET(pg_name, ctl)\
+ { \
+ .name = pg_name,\
+ .ctl_reg = ctl, \
+ .io_reg = ctl + 0x4,\
+ .pull_bit = 3, \
+ .drv_bit = 0, \
+ .oe_bit = -1, \
+ .in_bit = -1, \
+ .out_bit = 0, \
+ }
+
+enum sa8775p_functions {
+ msm_mux_gpio,
+ msm_mux_atest_char,
+ msm_mux_atest_usb2,
+ msm_mux_audio_ref,
+ msm_mux_cam_mclk,
+ msm_mux_cci_async,
+ msm_mux_cci_i2c,
+ msm_mux_cci_timer0,
+ msm_mux_cci_timer1,
+ msm_mux_cci_timer2,
+ msm_mux_cci_timer3,
+ msm_mux_cci_timer4,
+ msm_mux_cci_timer5,
+ msm_mux_cci_timer6,
+ msm_mux_cci_timer7,
+ msm_mux_cci_timer8,
+ msm_mux_cci_timer9,
+ msm_mux_cri_trng,
+ msm_mux_cri_trng0,
+ msm_mux_cri_trng1,
+ msm_mux_dbg_out,
+ msm_mux_ddr_bist,
+ msm_mux_ddr_pxi0,
+ msm_mux_ddr_pxi1,
+ msm_mux_ddr_pxi2,
+ msm_mux_ddr_pxi3,
+ msm_mux_ddr_pxi4,
+ msm_mux_ddr_pxi5,
+ msm_mux_edp0_hot,
+ msm_mux_
Re: [PATCH] usb: dwc3: gadget: Fix match_ep callback for NXP UUU tool
Hello Mattijs, Marek On Thu, Mar 20, 2025 at 10:47:02AM +0100, Mattijs Korpershoek wrote: > On mer., mars 19, 2025 at 23:07, Marek Vasut wrote: > > > The UUU tool excepts the interrupt-in endpoint to be ep1in, otherwise > > it crashes. This is a result of the previous hard-coded EP setup in > > drivers/usb/gadget/epautoconf.c which did special-case EP allocation > > for SPL builds, and which was since converted to this callback, but > > without the special-case EP allocation in SPL part. > > > > This reinstates the SPL part in an isolated manner, only for NXP iMX > > SoCs, only for SPL builds, and only for the ep1in interrupt-in endpoint. UUU can (and in our case is) used also on non-NXP i.MX platforms. What should we do? Francesco
[PATCH v1 2/2] qcom_defconfig: enable pinctrl for SA8775P
Enable the pinctrl driver for SA8775P Signed-off-by: Varadarajan Narayanan --- configs/qcom_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index 661a484f7bf..20c49223201 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -97,6 +97,7 @@ CONFIG_PINCTRL_QCOM_APQ8016=y CONFIG_PINCTRL_QCOM_APQ8096=y CONFIG_PINCTRL_QCOM_QCM2290=y CONFIG_PINCTRL_QCOM_QCS404=y +CONFIG_PINCTRL_QCOM_SA8775P=y CONFIG_PINCTRL_QCOM_SDM845=y CONFIG_PINCTRL_QCOM_SM6115=y CONFIG_PINCTRL_QCOM_SM8150=y -- 2.34.1
[PATCH v2 10/24] clk: imx: gate2: Resolve parent clock by name
Use clock-names property which is accessible via parent clock OF node
to look up the parent clock by name instead of depending on unreliable
global clock name to perform look up.
Signed-off-by: Marek Vasut
---
Cc: Adam Ford
Cc: Christoph Niedermaier
Cc: Dong Aisheng
Cc: Fabio Estevam
Cc: Hou Zhiqiang
Cc: Michael Trimarchi
Cc: Peng Fan
Cc: Tim Harvey
Cc: Tom Rini
Cc: u-boot@lists.denx.de
Cc: uboot-...@nxp.com
---
V2: Rebase on u-boot/next with additional clock patches
---
drivers/clk/imx/clk-gate2.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-gate2.c b/drivers/clk/imx/clk-gate2.c
index 400121a8ae1..fa07b13249b 100644
--- a/drivers/clk/imx/clk-gate2.c
+++ b/drivers/clk/imx/clk-gate2.c
@@ -111,7 +111,8 @@ struct clk *clk_register_gate2(struct udevice *dev, const
char *name,
clk = &gate->clk;
- ret = clk_register(clk, UBOOT_DM_CLK_IMX_GATE2, name, parent_name);
+ ret = clk_register(clk, UBOOT_DM_CLK_IMX_GATE2, name,
+ clk_resolve_parent_clk(dev, parent_name));
if (ret) {
kfree(gate);
return ERR_PTR(ret);
--
2.47.2
[PATCH v2 15/24] clk: imx: Pass struct udevice into imx_clk_composite*()
Pass struct udevice * into imx_clk_composite*() functions, so the
clock core would have access to parent struct udevice *.
Signed-off-by: Marek Vasut
---
Cc: Adam Ford
Cc: Christoph Niedermaier
Cc: Dong Aisheng
Cc: Fabio Estevam
Cc: Hou Zhiqiang
Cc: Michael Trimarchi
Cc: Peng Fan
Cc: Tim Harvey
Cc: Tom Rini
Cc: u-boot@lists.denx.de
Cc: uboot-...@nxp.com
---
V2: Rebase on u-boot/next with additional clock patches
---
drivers/clk/imx/clk-composite-8m.c | 4 +-
drivers/clk/imx/clk-imx8mm.c | 74 +-
drivers/clk/imx/clk-imx8mn.c | 60 ++---
drivers/clk/imx/clk-imx8mp.c | 84 +++---
drivers/clk/imx/clk-imx8mq.c | 52 +-
drivers/clk/imx/clk.h | 14 ++---
6 files changed, 143 insertions(+), 145 deletions(-)
diff --git a/drivers/clk/imx/clk-composite-8m.c
b/drivers/clk/imx/clk-composite-8m.c
index 64bffa3b181..14c5b92939c 100644
--- a/drivers/clk/imx/clk-composite-8m.c
+++ b/drivers/clk/imx/clk-composite-8m.c
@@ -151,7 +151,7 @@ const struct clk_ops imx8m_clk_mux_ops = {
.set_parent = imx8m_clk_mux_set_parent,
};
-struct clk *imx8m_clk_composite_flags(const char *name,
+struct clk *imx8m_clk_composite_flags(struct udevice *dev, const char *name,
const char * const *parent_names,
int num_parents, void __iomem *reg,
unsigned long flags)
@@ -187,7 +187,7 @@ struct clk *imx8m_clk_composite_flags(const char *name,
gate->reg = reg;
gate->bit_idx = PCG_CGC_SHIFT;
- clk = clk_register_composite(NULL, name,
+ clk = clk_register_composite(dev, name,
parent_names, num_parents,
&mux->clk, &imx8m_clk_mux_ops, &div->clk,
&imx8m_clk_composite_divider_ops,
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 30762666754..c9d6954ac75 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -300,71 +300,69 @@ static int imx8mm_clk_probe(struct udevice *dev)
base + 0x8000, 0, 3));
clk_dm(IMX8MM_CLK_AHB,
- imx8m_clk_composite_critical("ahb", imx8mm_ahb_sels,
+ imx8m_clk_composite_critical(dev, "ahb", imx8mm_ahb_sels,
base + 0x9000));
clk_dm(IMX8MM_CLK_IPG_ROOT,
imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1));
clk_dm(IMX8MM_CLK_NAND_USDHC_BUS,
- imx8m_clk_composite_critical("nand_usdhc_bus",
+ imx8m_clk_composite_critical(dev, "nand_usdhc_bus",
imx8mm_nand_usdhc_sels,
base + 0x8900));
clk_dm(IMX8MM_CLK_USB_BUS,
- imx8m_clk_composite("usb_bus", imx8mm_usb_bus_sels, base +
0x8b80));
+ imx8m_clk_composite(dev, "usb_bus", imx8mm_usb_bus_sels, base +
0x8b80));
/* IP */
#if CONFIG_IS_ENABLED(PCIE_DW_IMX)
clk_dm(IMX8MM_CLK_PCIE1_CTRL,
- imx8m_clk_composite("pcie1_ctrl", imx8mm_pcie1_ctrl_sels,
+ imx8m_clk_composite(dev, "pcie1_ctrl", imx8mm_pcie1_ctrl_sels,
base + 0xa300));
clk_dm(IMX8MM_CLK_PCIE1_PHY,
- imx8m_clk_composite("pcie1_phy", imx8mm_pcie1_phy_sels,
+ imx8m_clk_composite(dev, "pcie1_phy", imx8mm_pcie1_phy_sels,
base + 0xa380));
clk_dm(IMX8MM_CLK_PCIE1_AUX,
- imx8m_clk_composite("pcie1_aux", imx8mm_pcie1_aux_sels,
+ imx8m_clk_composite(dev, "pcie1_aux", imx8mm_pcie1_aux_sels,
base + 0xa400));
#endif
clk_dm(IMX8MM_CLK_USDHC1,
- imx8m_clk_composite("usdhc1", imx8mm_usdhc1_sels,
+ imx8m_clk_composite(dev, "usdhc1", imx8mm_usdhc1_sels,
base + 0xac00));
clk_dm(IMX8MM_CLK_USDHC2,
- imx8m_clk_composite("usdhc2", imx8mm_usdhc2_sels,
+ imx8m_clk_composite(dev, "usdhc2", imx8mm_usdhc2_sels,
base + 0xac80));
clk_dm(IMX8MM_CLK_I2C1,
- imx8m_clk_composite("i2c1", imx8mm_i2c1_sels, base + 0xad00));
+ imx8m_clk_composite(dev, "i2c1", imx8mm_i2c1_sels, base +
0xad00));
clk_dm(IMX8MM_CLK_I2C2,
- imx8m_clk_composite("i2c2", imx8mm_i2c2_sels, base + 0xad80));
+ imx8m_clk_composite(dev, "i2c2", imx8mm_i2c2_sels, base +
0xad80));
clk_dm(IMX8MM_CLK_I2C3,
- imx8m_clk_composite("i2c3", imx8mm_i2c3_sels, base + 0xae00));
+ imx8m_clk_composite(dev, "i2c3", imx8mm_i2c3_sels, base +
0xae00));
clk_dm(IMX8MM_CLK_I2C4,
- imx8m_clk_composite("i2c4", im
Re: [PATCH] usb: dwc3: gadget: Fix match_ep callback for NXP UUU tool
On 19/03/2025 23:07, Marek Vasut wrote:
The UUU tool excepts the interrupt-in endpoint to be ep1in, otherwise
it crashes. This is a result of the previous hard-coded EP setup in
drivers/usb/gadget/epautoconf.c which did special-case EP allocation
for SPL builds, and which was since converted to this callback, but
without the special-case EP allocation in SPL part.
This reinstates the SPL part in an isolated manner, only for NXP iMX
SoCs, only for SPL builds, and only for the ep1in interrupt-in endpoint.
Fixes: 1918b8010c32 ("usb: dwc3: gadget: Convert epautoconf workaround to match_ep
callback")
Signed-off-by: Marek Vasut
---
Cc: Alexander Sverdlin
Cc: Felipe Balbi
Cc: Lukasz Majewski
Cc: Marek Vasut
Cc: Mattijs Korpershoek
Cc: Neil Armstrong
Cc: Thinh Nguyen
Cc: Tom Rini
Cc: u-boot@lists.denx.de
---
NOTE: This should go into master as a bugfix.
---
drivers/usb/dwc3/gadget.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index e5a383407a2..477ecd02098 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -1631,8 +1631,25 @@ usb_ep *dwc3_gadget_match_ep(struct usb_gadget *gadget,
return dwc3_find_ep(gadget, "ep1in");
if (usb_endpoint_is_bulk_out(desc))
return dwc3_find_ep(gadget, "ep2out");
- if (usb_endpoint_is_int_in(desc))
+ if (usb_endpoint_is_int_in(desc)) {
+ /*
+* Special workaround for NXP UUU tool in SPL.
+*
+* The tool excepts the interrupt-in endpoint to be ep1in,
Small nit: expects
+* otherwise it crashes. This is a result of the previous
+* hard-coded EP setup in drivers/usb/gadget/epautoconf.c
+* which did special-case EP allocation for SPL builds,
+* and which was since converted to this callback, but
+* without the special-case EP allocation in SPL part.
+*
+* This reinstates the SPL part in an isolated manner,
+* only for NXP iMX SoCs, only for SPL builds, and only
+* for the ep1in interrupt-in endpoint.
+*/
+ if (IS_ENABLED(CONFIG_MACH_IMX) && IS_ENABLED(CONFIG_XPL_BUILD))
+ return dwc3_find_ep(gadget, "ep1in");
return dwc3_find_ep(gadget, "ep3in");
+ }
return NULL;
}
Re: [PATCH] usb: gadget: atmel: Add SAM9X60 support
On 3/22/25 22:56, Zixun LI wrote:
> Add compatible "microchip,sam9x60-udc" and device tree binding.
> Compared to SAM9X5 the only difference is the DPRAM memory from the
> USB High Speed Device Port (UDPHS) hardware block was increased,
> so we can reuse the same endpoint data.
>
> Tested on SAM9X60-Curiosity board with nfs and ums commands.
Why no patch to enable it on the board as well then ?
>
> Signed-off-by: Zixun LI
> ---
> arch/arm/dts/sam9x60.dtsi| 14 ++
> arch/arm/mach-at91/include/mach/atmel_usba_udc.h | 2 +-
> drivers/usb/gadget/atmel_usba_udc.c | 1 +
Device tree and driver changes should be separate commits.
> 3 files changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/dts/sam9x60.dtsi
> index 3b684fc63d5..96a8faf09b3 100644
> --- a/arch/arm/dts/sam9x60.dtsi
> +++ b/arch/arm/dts/sam9x60.dtsi
> @@ -69,6 +69,20 @@
> #size-cells = <1>;
> ranges;
>
> + usb0: gadget@50 {
> + compatible = "microchip,sam9x60-udc";
> + reg = <0x50 0x10>,
> + <0xf803c000 0x400>;
> + #address-cells = <1>;
> + #size-cells = <0>;
Can you please reorder these to have them in the same order as in Linux
DTS ? (easier to diff...)
> + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>;
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc
> PMC_TYPE_CORE 8>;
> + clock-names = "pclk", "hclk";
> + assigned-clocks = <&pmc PMC_TYPE_CORE 8>;
> + assigned-clock-rates = <48000>;
> + status = "disabled";
> + };
> +
> usb1: usb@60 {
> compatible = "atmel,at91rm9200-ohci", "usb-ohci";
> reg = <0x0060 0x10>;
> diff --git a/arch/arm/mach-at91/include/mach/atmel_usba_udc.h
> b/arch/arm/mach-at91/include/mach/atmel_usba_udc.h
> index 835b47d91ba..23c71985c90 100644
> --- a/arch/arm/mach-at91/include/mach/atmel_usba_udc.h
> +++ b/arch/arm/mach-at91/include/mach/atmel_usba_udc.h
> @@ -20,7 +20,7 @@
> }
>
> #if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \
> - defined(CONFIG_AT91SAM9X5)
> + defined(CONFIG_AT91SAM9X5) || defined(CONFIG_SAM9X60)
> static struct usba_ep_data usba_udc_ep[] = {
> EP("ep0", 0, 64, 1, 0, 0),
> EP("ep1", 1, 1024, 2, 1, 1),
> diff --git a/drivers/usb/gadget/atmel_usba_udc.c
> b/drivers/usb/gadget/atmel_usba_udc.c
> index a77037a7094..f9326f0a7e7 100644
> --- a/drivers/usb/gadget/atmel_usba_udc.c
> +++ b/drivers/usb/gadget/atmel_usba_udc.c
> @@ -1443,6 +1443,7 @@ static const struct udevice_id usba_udc_ids[] = {
> { .compatible = "atmel,at91sam9rl-udc" },
> { .compatible = "atmel,at91sam9g45-udc" },
> { .compatible = "atmel,sama5d3-udc" },
> + { .compatible = "microchip,sam9x60-udc" },
> {}
> };
>
Re: [PATCH] cmd: fuse: add switch for quiet operation
Hi Rogerio, On 3/17/25 11:53 PM, Rogerio Guerra Borin wrote: [You don't often get email from rogerio.bo...@gmail.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ] Add switch -q for quiet operation to all fuse subcommands. This helps avoid bloating the console with messages that can be distracting to users (particularly when the command is employed by scripts and multiple fuse values are read/compared/programmed). For example, the "fuse cmp" command normally produces five lines of output: U-Boot # fuse cmp 6 0 0x70af49db Comparing bank 6: Word 0x: Value 0x70af49db:0x70af49db passed U-Boot # echo $? 0 But scripts issuing the command do not know or care about that output since the command exit code is the only relevant information visible to them. With the new switch one can avoid the unnecessary output: U-Boot # fuse cmp -q 6 0 0x70af49db U-Boot # echo $? 0 I think this is a reasonable expectation. I'm wondering if we shouldn't think about using the log architecture we have to have a generic solution rather than expecting each command driver to handle (possibly in their own way) a quiet flag. https://docs.u-boot.org/en/latest/develop/logging.html The idea I have in mind is that we could dynamically set the loglevel for a specific command driver (or at least for the command subsystem (by e.g. defining an LOG_CATEGORY LOGC_CMD) and use log_* functions in the command driver rather than IF_NOT_QUIET() below. This would also allow different log levels to be used. Maybe there's something to be done with filters, or something new needs to be added to set the log level for a category maybe? I don't know, not too verse in our log system. Another option to have a generic logic would be to depend on an environment variable instead of needing to expand each command driver's logic. Cheers, Quentin
Re: [PATCH 5/8] env: Rename SYS_MMC_ENV_PART to ENV_SDMMC_EMMC_HW_PARTITION
Hi Marek, On 3/22/25 10:55 PM, Marek Vasut wrote: Rename the variable and add ENV_ prefix, so that all configuration options which are related to environment would have an CONFIG_ENV_ prefix. No functional change. Use ENV_SDMMC_EMMC_HW_PARTITION to clarify this is the eMMC hardware Same disagreement as previous patch for the MMC->SDMMC rename, I haven't checked the next patches but the same remark would apply as well. [...] diff --git a/env/Kconfig b/env/Kconfig index 6bb882baa9e..fbc03777040 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -219,7 +219,7 @@ config ENV_IS_IN_MMC Specifies which MMC device the environment is stored in. - CONFIG_SYS_MMC_ENV_PART (optional): + CONFIG_ENV_SDMMC_EMMC_HW_PARTITION (optional): Specifies which MMC partition the environment is stored in. If not "which eMMC hardware partition" set, defaults to partition 0, the user area. Common values might be Outside of this git context: "(first eMMC hardware boot partition), 2 (second eMMC hardware boot partition)" maybe? @@ -252,7 +252,7 @@ config ENV_IS_IN_MMC This value may also be positive or negative; this is handled in the same way as CONFIG_ENV_OFFSET. - In case CONFIG_SYS_MMC_ENV_PART is 1 (i.e. environment in eMMC boot + In case CONFIG_ENV_SDMMC_EMMC_HW_PARTITION is 1 (i.e. environment in eMMC boot partition) then setting CONFIG_ENV_OFFSET_REDUND to the same value as CONFIG_ENV_OFFSET makes use of the second eMMC boot partition for the redundant environment copy. @@ -676,7 +676,7 @@ config ENV_SDMMC_DEVICE_INDEX The index is often derived from DT aliases mmcN node ordering, and matches the 'mmc list' command output. -config SYS_MMC_ENV_PART +config ENV_SDMMC_EMMC_HW_PARTITION int "mmc partition number" Should we say "eMMC hardware partition number" here? Cheers, Quentin
