Please pull u-boot-ubi
Hello Tom, please pull from: The following changes since commit fc97ff2695d6d7fbea7d5fda7b080f405d6ee744: Merge https://source.denx.de/u-boot/custodians/u-boot-sunxi (2022-07-19 10:52:15 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-ubi.git for-v2022.10 for you to fetch changes up to e2e6caa01ba97bcdb82100c6b928b5743e3aae6c: ubifs: Use U-Boot assert() from in UBI/UBIFS code (2022-07-20 05:50:13 +0200) ubifs changes for 2022.10 UBIFS fixes from Pali Rohar: - ubifs: Fix ubifs_assert_cmt_locked - ubifs: Use U-Boot assert() from Pali Rohár (2): ubifs: Fix ubifs_assert_cmt_locked() ubifs: Use U-Boot assert() from in UBI/UBIFS code drivers/mtd/ubi/debug.h | 9 ++--- fs/ubifs/debug.h| 17 +++-- 2 files changed, 5 insertions(+), 21 deletions(-) Azure build: https://dev.azure.com/hs0298/hs/_build/results?buildId=84&view=results Thanks! bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: h...@denx.de
Re: [PATCH 2/2] tools: kwboot: use pkg-config to get -ltinfo
On Wednesday 20 July 2022 08:06:28 Heiko Thiery wrote: > Hi, > > > Am Di., 19. Juli 2022 um 21:20 Uhr schrieb Pali Rohár : > > > > On Tuesday 19 July 2022 20:38:39 Heiko Thiery wrote: > > > Instead of hardcoding -ltinfo as the flags needed to build > > > kwboot, use pkg-config when available. > > > > > > We gracefully fallback on the previous behavior of hardcoding -ltinfo > > > if pkg-config is not available or fails with an error. > > > > > > Signed-off-by: Heiko Thiery > > > > So... in current form this patch is OK. > > I already sent a v2 that introduced the cflags. I will send a v3 that > removes adding this again. Ok? Ou, sorry for that :-( Anyway, details about this issue are described here: https://source.denx.de/u-boot/u-boot/-/blob/master/tools/termios_linux.h https://source.denx.de/u-boot/u-boot/-/commit/e8d26e8276358fcd1c2fe28293d3b4c82a735731 > > Reviewed-by: Pali Rohár > > > > > --- > > > tools/Makefile | 4 +++- > > > 1 file changed, 3 insertions(+), 1 deletion(-) > > > > > > diff --git a/tools/Makefile b/tools/Makefile > > > index 9f6b282ad8..45195a8ce7 100644 > > > --- a/tools/Makefile > > > +++ b/tools/Makefile > > > @@ -198,7 +198,9 @@ hostprogs-$(CONFIG_EXYNOS5420) += mkexynosspl > > > HOSTCFLAGS_mkexynosspl.o := -pedantic > > > > > > HOSTCFLAGS_kwboot.o += -pthread > > > -HOSTLDLIBS_kwboot += -pthread -ltinfo > > > +HOSTLDLIBS_kwboot += -pthread > > > +HOSTLDLIBS_kwboot += \ > > > + $(shell pkg-config --libs tinfo 2> /dev/null || echo "-ltinfo") > > > > > > ifdtool-objs := $(LIBFDT_OBJS) ifdtool.o > > > hostprogs-$(CONFIG_X86) += ifdtool > > > -- > > > 2.30.2 > > >
[PATCH] Provide more details of exactly how configuration signatures are calculated
I have just spent a week reverse-engineering this, so I thought I'd
contribute the work back to the community
diff --git a/doc/uImage.FIT/signature.txt b/doc/uImage.FIT/signature.txt
index 61a72db3c7..61cdd55e40 100644
--- a/doc/uImage.FIT/signature.txt
+++ b/doc/uImage.FIT/signature.txt
@@ -382,6 +382,25 @@ verified later even if the FIT has been signed
with other keys in the
meantime.
+Details
+---
+The signature node contains a property ('hashed-nodes') which lists all the
+nodes that the signature was made over. The image is walked in order and each
+tag processed as follows:
+- DTB_BEGIN_NODE: The tag and the following name are added to the signature if
+ the node or its parent are present in 'hashed-nodes'
+- DTB_END_NODE: The tag is added to the signature if the node or its parent are
+ present in 'hashed-nodes'
+- DTB_PROPERTY: The tag, the length word, the offset in the string table, and
+ the data are all included if the node is present in 'hashed-nodes' and the
+ property name is not 'data'.
+- DTB_END: The tag is always included.
+
+In addition, the signature contains a property 'hashed-strings' which contains
+the offset and length in the string table of the strings that are to be added
+to the signature (this is always done at the end).
+
+
Verification
FITs are verified when loaded. After the configuration is selected a list
--
Martin
Re: [PATCH] Provide more details of exactly how configuration signatures are calculated
There are a couple of uncertainties still remaining:
- The "hashed-nodes" property is created by mkimage in image order.
What happens if somebody manipulates a signed image to change the
order? Does it make any difference? Do u-boot and fit_check_sign
handle it in the same way? (My preference would be that both fail the
signature on the grounds that there is no good reason for the nodes to
be out of order, and it suggests an attacker is trying to be clever.)
- What happens if the image contains a DTB_NOP tag? Is it included or
not? (Again, I would fail the signature if it does.)
Martin
On Wed, 20 Jul 2022 at 08:14, Martin Bonner wrote:
>
> I have just spent a week reverse-engineering this, so I thought I'd
> contribute the work back to the community
>
> diff --git a/doc/uImage.FIT/signature.txt b/doc/uImage.FIT/signature.txt
> index 61a72db3c7..61cdd55e40 100644
> --- a/doc/uImage.FIT/signature.txt
> +++ b/doc/uImage.FIT/signature.txt
> @@ -382,6 +382,25 @@ verified later even if the FIT has been signed
> with other keys in the
> meantime.
>
>
> +Details
> +---
> +The signature node contains a property ('hashed-nodes') which lists all the
> +nodes that the signature was made over. The image is walked in order and
> each
> +tag processed as follows:
> +- DTB_BEGIN_NODE: The tag and the following name are added to the signature
> if
> + the node or its parent are present in 'hashed-nodes'
> +- DTB_END_NODE: The tag is added to the signature if the node or its parent
> are
> + present in 'hashed-nodes'
> +- DTB_PROPERTY: The tag, the length word, the offset in the string table, and
> + the data are all included if the node is present in 'hashed-nodes' and the
> + property name is not 'data'.
> +- DTB_END: The tag is always included.
> +
> +In addition, the signature contains a property 'hashed-strings' which
> contains
> +the offset and length in the string table of the strings that are to be added
> +to the signature (this is always done at the end).
> +
> +
> Verification
>
> FITs are verified when loaded. After the configuration is selected a list
>
> --
> Martin
Re: [PATCH v1] imx: romapi: fix spurious ampersand in address print
Hi
On Wed, Jul 20, 2022 at 9:29 AM Francesco Dolcini
wrote:
>
> From: Marcel Ziswiler
>
> Fix spurious ampersand in address print e.g.
>
> Find img info 0x&480331a0, size 855
>
> Signed-off-by: Marcel Ziswiler
> Signed-off-by: Francesco Dolcini
> ---
> arch/arm/mach-imx/spl_imx_romapi.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-imx/spl_imx_romapi.c
> b/arch/arm/mach-imx/spl_imx_romapi.c
> index c47f5a6bdb44..2996d2761690 100644
> --- a/arch/arm/mach-imx/spl_imx_romapi.c
> +++ b/arch/arm/mach-imx/spl_imx_romapi.c
> @@ -306,7 +306,7 @@ static int spl_romapi_load_image_stream(struct
> spl_image_info *spl_image,
> }
>
> imagesize = img_info_size(phdr);
> - printf("Find img info 0x&%p, size %d\n", phdr, imagesize);
> + printf("Find img info 0x%p, size %d\n", phdr, imagesize);
>
> if (p - phdr < imagesize) {
> imagesize -= p - phdr;
> --
> 2.25.1
>
I have already seen a similar patch from Fabio.
Reviewed-by: Michael Trimarchi "
Re: [PATCH v7 08/13] FWU: Add boot time checks as highlighted by the FWU specification
Hi Sughosh,
>
> > + nimages = CONFIG_FWU_NUM_IMAGES_PER_BANK;
> > + active_bank = mdata->active_index;
> > + img_entry = &mdata->img_entry[0];
> > + for (i = 0; i < nimages; i++) {
> > + img_bank_info = &img_entry[i].img_bank_info[active_bank];
> > + if (!img_bank_info->accepted) {
> > + trial_state = 1;
> > + break;
> > + }
> > + }
>
> Is this used elsewhere in the patchset? The function is starting to
> be big, so perhaps moving this in a static bool "in_trial_state()" or
> similar would make it more readable.
>
There was a discussion about this on the synquacer thread for A/B
updates. Once you split those in a function, it's better to extend
the bootcount API with an EFI backed storage. The reasoning that a
user might disable editing env variables for security reasons and that
device might not be able to preserve RAM or store the counter in CPU
registers across reboots.
If we extend the bootcount API with this code we can plug in the
functionality seamlessly based on the hardware capabilities.
[...]
Regards
/Ilias
Re: [RESEND v9 1/9] efi_loader: move udevice pointer into struct efi_object
On 7/20/22 07:23, Takahiro Akashi wrote:
On Sun, Jul 17, 2022 at 01:23:41PM +0200, Heinrich Schuchardt wrote:
On 7/17/22 10:09, Heinrich Schuchardt wrote:
On 7/15/22 16:47, Masahisa Kojima wrote:
This is a preparation patch to provide the unified method
to access udevice pointer associated with the block io device.
The EFI handles of both EFI block io driver implemented in
lib/efi_loader/efi_disk.c and EFI block io driver implemented
as EFI payload can posess the udevice pointer in the struct efi_object.
We can use this udevice pointer to get the U-Boot friendly
block device name(e.g. mmc 0:1, nvme 0:1) through efi_handle_t.
Signed-off-by: Masahisa Kojima
---
Newly created in v9
include/efi_loader.h | 8
lib/efi_loader/efi_disk.c | 20 +---
2 files changed, 21 insertions(+), 7 deletions(-)
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 3a63a1f75f..bba5ffd482 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -226,6 +226,12 @@ const char *__efi_nesting_dec(void);
#define EFI_CACHELINE_SIZE 128
#endif
+/**
+ * efi_handle_to_udev - accessor to the DM device associated to the
EFI handle
+ * @handle: pointer to the EFI handle
+ */
+#define efi_handle_to_udev(handle) (((struct efi_object *)handle)->dev)
This conversion will hide errors if handle is not of type efi_handle_t.
We should avoid the conversion and see build time errors instead.
Please, remove the macro.
For every handle of type efi_handle_t you can access the field
handle->dev directly.
For struct efi_disk_obj we can use disk->header.dev.
+
/* Key identifying current memory map */
extern efi_uintn_t efi_memory_map_key;
@@ -375,6 +381,7 @@ enum efi_object_type {
* @protocols: linked list with the protocol interfaces installed
on this
* handle
* @type: image type if the handle relates to an image
+ * @dev: pointer to the DM device which is associated with this
EFI handle
*
* UEFI offers a flexible and expandable object model. The objects
in the UEFI
* API are devices, drivers, and loaded images. struct efi_object is
our storage
@@ -392,6 +399,7 @@ struct efi_object {
/* The list of protocols */
struct list_head protocols;
enum efi_object_type type;
+ struct udevice *dev;
};
enum efi_image_auth_status {
diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c
index 1d700b2a6b..a8e8521e3e 100644
--- a/lib/efi_loader/efi_disk.c
+++ b/lib/efi_loader/efi_disk.c
@@ -46,7 +46,6 @@ struct efi_disk_obj {
struct efi_device_path *dp;
unsigned int part;
struct efi_simple_file_system_protocol *volume;
- struct udevice *dev; /* TODO: move it to efi_object */
ok
};
/**
@@ -124,16 +123,16 @@ static efi_status_t efi_disk_rw_blocks(struct
efi_block_io *this,
return EFI_BAD_BUFFER_SIZE;
if (CONFIG_IS_ENABLED(PARTITIONS) &&
- device_get_uclass_id(diskobj->dev) == UCLASS_PARTITION) {
+ device_get_uclass_id(efi_handle_to_udev(diskobj)) ==
UCLASS_PARTITION) {
device_get_uclass_id(diskobj->header.hdev)) == UCLASS_PARTITION) {
if (direction == EFI_DISK_READ)
- n = dev_read(diskobj->dev, lba, blocks, buffer);
+ n = dev_read(efi_handle_to_udev(diskobj), lba, blocks,
buffer);
dev_read(diskobj->header.hdev)
else
- n = dev_write(diskobj->dev, lba, blocks, buffer);
+ n = dev_write(efi_handle_to_udev(diskobj), lba, blocks,
buffer);
dev_write(diskobj->header.hdev)
} else {
/* dev is a block device (UCLASS_BLK) */
struct blk_desc *desc;
- desc = dev_get_uclass_plat(diskobj->dev);
+ desc = dev_get_uclass_plat(efi_handle_to_udev(diskobj));
dev_get_uclass(diskobj->header.hdev)
if (direction == EFI_DISK_READ)
n = blk_dread(desc, lba, blocks, buffer);
else
@@ -552,7 +551,7 @@ static int efi_disk_create_raw(struct udevice *dev)
return -1;
}
- disk->dev = dev;
+ efi_handle_to_udev(disk) = dev;
if (dev_tag_set_ptr(dev, DM_TAG_EFI, &disk->header)) {
efi_free_pool(disk->dp);
efi_delete_handle(&disk->header);
@@ -609,7 +608,7 @@ static int efi_disk_create_part(struct udevice *dev)
log_err("Adding partition for %s failed\n", dev->name);
return -1;
}
- disk->dev = dev;
+ efi_handle_to_udev(disk) = dev;
disk->header.dev = dev;
if (dev_tag_set_ptr(dev, DM_TAG_EFI, &disk->header)) {
efi_free_pool(disk->dp);
efi_delete_handle(&disk->header);
@@ -656,6 +655,13 @@ static int efi_disk_probe(void *ctx, struct event
*event)
ret = efi_disk_create_raw(dev);
if (ret)
return -1;
+ } else {
+ efi_handle_t handle;
+
+ if (dev_tag_get_ptr(dev, DM_TAG_EFI, (void **)&handle))
Setting handle->dev can be done more easily in efi_bl_bind():
Re: [PATCH 0/9] Add DM support for atmel NAND driver
On 7/19/22 13:46, Balamanikandan Gunasundar wrote: > This patch series adds support for NAND flash. The series adds DM > support and replaces the existing NAND driver NAND_ATMEL. The drivers > are ported from Linux based on the work done by Boris brezillon If you're going to resubmit, it would be helpful to specify on top of which kernel version your work is based on. This would help to backport fixes or new support in the future. ta > > Balamanikandan Gunasundar (9): > nand: atmel: Add DM based NAND driver > nand: atmel: Add pmecc driver > mfd: syscon: Add atmel-matrix registers definition > memory: atmel-ebi: add Atmel EBI (External Bus Interface) driver > mfd: syscon: atmel-smc: Add driver for atmel SMC > configs: at91: sam9x60ek: Enable DM based nand driver > ARM: dts: at91: sam9x60: Add nodes for EBI and NAND > ARM: dts: at91: sam9x60ek: Enable NAND support > board: sam9x60ek: remove nand init from board file > > MAINTAINERS |1 + > arch/arm/dts/sam9x60.dtsi| 42 + > arch/arm/dts/sam9x60ek.dts | 103 + > board/atmel/sam9x60ek/sam9x60ek.c| 59 - > configs/sam9x60ek_mmc_defconfig |9 +- > configs/sam9x60ek_nandflash_defconfig|9 +- > configs/sam9x60ek_qspiflash_defconfig|8 +- > drivers/Kconfig |2 + > drivers/Makefile |1 + > drivers/memory/Kconfig |7 + > drivers/memory/Makefile |1 + > drivers/memory/atmel_ebi.c | 37 + > drivers/mfd/Kconfig |4 + > drivers/mfd/Makefile |1 + > drivers/mfd/atmel-smc.c | 364 +++ > drivers/mtd/nand/raw/Kconfig |8 + > drivers/mtd/nand/raw/Makefile|1 + > drivers/mtd/nand/raw/atmel/Makefile |5 + > drivers/mtd/nand/raw/atmel/nand-controller.c | 2300 ++ > drivers/mtd/nand/raw/atmel/pmecc.c | 969 > drivers/mtd/nand/raw/atmel/pmecc.h | 94 + > include/linux/mfd/syscon/atmel-matrix.h | 112 + > include/linux/mfd/syscon/atmel-smc.h | 119 + > 23 files changed, 4188 insertions(+), 68 deletions(-) > create mode 100644 drivers/memory/atmel_ebi.c > create mode 100644 drivers/mfd/Kconfig > create mode 100644 drivers/mfd/Makefile > create mode 100644 drivers/mfd/atmel-smc.c > create mode 100644 drivers/mtd/nand/raw/atmel/Makefile > create mode 100644 drivers/mtd/nand/raw/atmel/nand-controller.c > create mode 100644 drivers/mtd/nand/raw/atmel/pmecc.c > create mode 100644 drivers/mtd/nand/raw/atmel/pmecc.h > create mode 100644 include/linux/mfd/syscon/atmel-matrix.h > create mode 100644 include/linux/mfd/syscon/atmel-smc.h >
Re: [RESEND v9 1/9] efi_loader: move udevice pointer into struct efi_object
On 7/20/22 01:56, Takahiro Akashi wrote:
On Sun, Jul 17, 2022 at 10:09:42AM +0200, Heinrich Schuchardt wrote:
On 7/15/22 16:47, Masahisa Kojima wrote:
This is a preparation patch to provide the unified method
to access udevice pointer associated with the block io device.
The EFI handles of both EFI block io driver implemented in
lib/efi_loader/efi_disk.c and EFI block io driver implemented
as EFI payload can posess the udevice pointer in the struct efi_object.
We can use this udevice pointer to get the U-Boot friendly
block device name(e.g. mmc 0:1, nvme 0:1) through efi_handle_t.
Signed-off-by: Masahisa Kojima
---
Newly created in v9
include/efi_loader.h | 8
lib/efi_loader/efi_disk.c | 20 +---
2 files changed, 21 insertions(+), 7 deletions(-)
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 3a63a1f75f..bba5ffd482 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -226,6 +226,12 @@ const char *__efi_nesting_dec(void);
#define EFI_CACHELINE_SIZE 128
#endif
+/**
+ * efi_handle_to_udev - accessor to the DM device associated to the EFI handle
+ * @handle:pointer to the EFI handle
+ */
+#define efi_handle_to_udev(handle) (((struct efi_object *)handle)->dev)
This conversion will hide errors if handle is not of type efi_handle_t.
We should avoid the conversion and see build time errors instead.
Please, remove the macro.
I don't think we should remove the macro itself, but only the type casting.
I think it is a good practice to hide an implementation how the relationship
between udev and efi_object is maintained *behind* accessor macros.
For every handle of type efi_handle_t you can access the field
handle->dev directly.
For struct efi_disk_obj we can use disk->header.dev.
This is a good example for hiding the implementation from the rest of code.
Such a macro is pure code obfuscation.
I won't take such a patch.
Best regards
Heinrich
+
/* Key identifying current memory map */
extern efi_uintn_t efi_memory_map_key;
@@ -375,6 +381,7 @@ enum efi_object_type {
* @protocols: linked list with the protocol interfaces installed on
this
* handle
* @type:image type if the handle relates to an image
+ * @dev: pointer to the DM device which is associated with this EFI
handle
*
* UEFI offers a flexible and expandable object model. The objects in the
UEFI
* API are devices, drivers, and loaded images. struct efi_object is our
storage
@@ -392,6 +399,7 @@ struct efi_object {
/* The list of protocols */
struct list_head protocols;
enum efi_object_type type;
+ struct udevice *dev;
};
enum efi_image_auth_status {
diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c
index 1d700b2a6b..a8e8521e3e 100644
--- a/lib/efi_loader/efi_disk.c
+++ b/lib/efi_loader/efi_disk.c
@@ -46,7 +46,6 @@ struct efi_disk_obj {
struct efi_device_path *dp;
unsigned int part;
struct efi_simple_file_system_protocol *volume;
- struct udevice *dev; /* TODO: move it to efi_object */
ok
};
/**
@@ -124,16 +123,16 @@ static efi_status_t efi_disk_rw_blocks(struct
efi_block_io *this,
return EFI_BAD_BUFFER_SIZE;
if (CONFIG_IS_ENABLED(PARTITIONS) &&
- device_get_uclass_id(diskobj->dev) == UCLASS_PARTITION) {
+ device_get_uclass_id(efi_handle_to_udev(diskobj)) ==
UCLASS_PARTITION) {
device_get_uclass_id(diskobj->header.hdev)) == UCLASS_PARTITION) {
if (direction == EFI_DISK_READ)
- n = dev_read(diskobj->dev, lba, blocks, buffer);
+ n = dev_read(efi_handle_to_udev(diskobj), lba, blocks,
buffer);
dev_read(diskobj->header.hdev)
else
- n = dev_write(diskobj->dev, lba, blocks, buffer);
+ n = dev_write(efi_handle_to_udev(diskobj), lba, blocks,
buffer);
dev_write(diskobj->header.hdev)
} else {
/* dev is a block device (UCLASS_BLK) */
struct blk_desc *desc;
- desc = dev_get_uclass_plat(diskobj->dev);
+ desc = dev_get_uclass_plat(efi_handle_to_udev(diskobj));
dev_get_uclass(diskobj->header.hdev)
if (direction == EFI_DISK_READ)
n = blk_dread(desc, lba, blocks, buffer);
else
@@ -552,7 +551,7 @@ static int efi_disk_create_raw(struct udevice *dev)
return -1;
}
- disk->dev = dev;
+ efi_handle_to_udev(disk) = dev;
if (dev_tag_set_ptr(dev, DM_TAG_EFI, &disk->header)) {
efi_free_pool(disk->dp);
efi_delete_handle(&disk->header);
@@ -609,7 +608,7 @@ static int efi_disk_create_part(struct udevice *dev)
log_err("Adding partition for %s failed\n", dev->name);
return -1;
}
- disk->dev = dev;
+ efi_handle_to_u
Re: [PATCH 1/9] nand: atmel: Add DM based NAND driver
Hi On Tue, Jul 19, 2022 at 12:46 PM Balamanikandan Gunasundar wrote: > > This implementation is ported from the rework done by Boris Brezillon > in Linux. The driver is tested in sam9x60ek, sama5d3_xplained, > sam9x75eb and sama7g54-ddr3-eb. > The reference implementation come from linux-?? , please give anyway a reference starting version > Signed-off-by: Balamanikandan Gunasundar > > --- > drivers/mtd/nand/raw/Kconfig |8 + > drivers/mtd/nand/raw/Makefile|1 + > drivers/mtd/nand/raw/atmel/Makefile |4 + > drivers/mtd/nand/raw/atmel/nand-controller.c | 2300 ++ > 4 files changed, 2313 insertions(+) > create mode 100644 drivers/mtd/nand/raw/atmel/Makefile > create mode 100644 drivers/mtd/nand/raw/atmel/nand-controller.c > > diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig > index 190300fc17..c795310c5d 100644 > --- a/drivers/mtd/nand/raw/Kconfig > +++ b/drivers/mtd/nand/raw/Kconfig > @@ -37,6 +37,14 @@ config SYS_NAND_USE_FLASH_BBT > help > Enable the BBT (Bad Block Table) usage. > > +config DM_NAND_ATMEL > + bool "Support Atmel NAND controller with DM support" > + select SYS_NAND_SELF_INIT > + imply SYS_NAND_USE_FLASH_BBT > + help > + Enable this driver for NAND flash platforms using an Atmel NAND > + controller. > + > config NAND_ATMEL > bool "Support Atmel NAND controller" > select SYS_NAND_SELF_INIT > diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile > index e3f6b903f7..a3acf3cbb3 100644 > --- a/drivers/mtd/nand/raw/Makefile > +++ b/drivers/mtd/nand/raw/Makefile > @@ -40,6 +40,7 @@ ifdef NORMAL_DRIVERS > obj-$(CONFIG_NAND_ECC_BCH) += nand_bch.o > > obj-$(CONFIG_NAND_ATMEL) += atmel_nand.o > +obj-$(CONFIG_DM_NAND_ATMEL) += atmel/ > obj-$(CONFIG_NAND_ARASAN) += arasan_nfc.o > obj-$(CONFIG_NAND_BRCMNAND) += brcmnand/ > obj-$(CONFIG_NAND_DAVINCI) += davinci_nand.o > diff --git a/drivers/mtd/nand/raw/atmel/Makefile > b/drivers/mtd/nand/raw/atmel/Makefile > new file mode 100644 > index 00..6708416983 > --- /dev/null > +++ b/drivers/mtd/nand/raw/atmel/Makefile > @@ -0,0 +1,4 @@ > +# SPDX-License-Identifier: GPL-2.0-only > +obj-$(CONFIG_DM_NAND_ATMEL)+= atmel-nand-controller.o > + > +atmel-nand-controller-objs := nand-controller.o > diff --git a/drivers/mtd/nand/raw/atmel/nand-controller.c > b/drivers/mtd/nand/raw/atmel/nand-controller.c > new file mode 100644 > index 00..87166b005d > --- /dev/null > +++ b/drivers/mtd/nand/raw/atmel/nand-controller.c > @@ -0,0 +1,2300 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright 2022 ATMEL > + * Copyright 2017 Free Electrons > + * > + * Author: Boris Brezillon > + * > + * Derived from the atmel_nand.c driver which contained the following > + * copyrights: > + * > + * Copyright 2003 Rick Bronson > + * > + * Derived from drivers/mtd/nand/autcpu12.c (removed in v3.8) > + * Copyright 2001 Thomas Gleixner (gleix...@autronix.de) > + * > + * Derived from drivers/mtd/spia.c (removed in v3.8) > + * Copyright 2000 Steven J. Hill (sjh...@cotw.com) > + * > + * > + * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263 > + * Richard Genoud (richard.gen...@gmail.com), Adeneo Copyright 2007 > + * > + * Derived from Das U-Boot source code > + * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c) > + * Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas > + * > + * Add Programmable Multibit ECC support for various AT91 SoC > + * Copyright 2012 ATMEL, Hong Xu > + * > + * Add Nand Flash Controller support for SAMA5 SoC > + * Copyright 2013 ATMEL, Josh Wu (josh...@atmel.com) > + * > + * Port from Linux > + * Balamanikandan Gunasundar(balamanikandan.gunasun...@microchip.com) > + * Copyright (C) 2022 Microchip Technology Inc. > + * > + * A few words about the naming convention in this file. This convention > + * applies to structure and function names. > + * > + * Prefixes: > + * > + * - atmel_nand_: all generic structures/functions > + * - atmel_smc_nand_: all structures/functions specific to the SMC interface > + * (at91sam9 and avr32 SoCs) > + * - atmel_hsmc_nand_: all structures/functions specific to the HSMC > interface > + *(sama5 SoCs and later) > + * - atmel_nfc_: all structures/functions used to manipulate the NFC > sub-block > + * that is available in the HSMC block > + * - _nand_: all SoC specific structures/functions > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include "pmecc.h" > + > +#define NSEC_PER_SEC10L > + > +#define ATMEL_HSMC_NFC_CFG 0x0 > +#define ATMEL_HSMC_NFC_CFG_SPARESIZE(x)
Re: [PATCH v5 19/23] FWU: synquacer: Add FWU Multi bank update support for DeveloperBox
Hi Jassi,
On Tue, 19 Jul 2022 at 18:27, Jassi Brar wrote:
>
> On Mon, 18 Jul 2022 at 16:00, Tom Rini wrote:
> > On Mon, Jul 18, 2022 at 10:31:56AM -0500, Jassi Brar wrote:
>
> > > > > > >
> > > > > > > > > +
> > > > > > > > > +#define PLAT_METADATA_OFFSET 0x51
> > > > > > > > > +#define PLAT_METADATA_SIZE (sizeof(struct devbox_metadata))
> > > > > > > > > +
> > > > > > > > > +struct __packed devbox_metadata {
> > > > > > > > > + u32 boot_index;
> > > > > > > > > + u32 boot_count;
> > > > > > > >
> > > > > > > > There is the whole bootcount infrastructure for this. I think
> > > > > > > > it would be much
> > > > > > > > better to use that framework instead of creating parallel one.
> > > > > > > >
> > > > > > > Yes, this goes too.
> > > > > >
> > > > > > Is bootcount really suited for this case?
> > > > > > AFAIK bootcount either requires device specific registers (which
> > > > > > won't
> > > > > > reset on reboots), or an environment you can write data to.
> > > > > > But what if a user wants to disable writing the env variables and
> > > > > > the
> > > > > > device doesn't have a set of registers we can use?
> > > > > >
> > > > > Maybe it should be moved in 'struct fwu_mdata' ?
> > > >
> > > > I was mostly thinking on moving this count as another 'bootcount'
> > > > method. So in case the user has disabled writing evn variables but he
> > > > is booting with EFI he can use that.
> > >
> > > Sorry, not sure I understand IIUIC there has to be some persistent
> > > storage.
> >
> > No, there just has to be "somewhere" to do the counting. We've got a
> > DDR backed driver, for example. So yes, I think we should try and use
> > the bootcount framework here.
> >
> OK, for platforms that can preserve ram across reboot, using
> non-persistent storage can work.
> My platform neither preserves ram, nor has any warmreset-proof
> registers. So I have to choose between saving the bootcount in efi-env
> or in vendor specific structure next to the metadata. I prefer
> metadata because it is common to all stages of boot. Any corrections
> to this approach?
The metadata is defined by a spec and they don't have a field for
bootcounting. Once Sughosh resends his patches he'll include a
bootcount backend that reuses EFI variables. Can't we just use that?
>
> Thanks
Re: [PATCH 0/9] Add DM support for atmel NAND driver
Hi On Wed, Jul 20, 2022 at 9:40 AM wrote: > > On 7/19/22 13:46, Balamanikandan Gunasundar wrote: > > This patch series adds support for NAND flash. The series adds DM > > support and replaces the existing NAND driver NAND_ATMEL. The drivers > > are ported from Linux based on the work done by Boris brezillon > > If you're going to resubmit, it would be helpful to specify on top of > which kernel version your work is based on. This would help to backport > fixes or new support in the future. > Please in commit message mention what was changed/dropped for example: - force poll instead of interrupt - move platform_device to udevice - use of dm_gpio instead of gpiod Michael > > > > > Balamanikandan Gunasundar (9): > > nand: atmel: Add DM based NAND driver > > nand: atmel: Add pmecc driver > > mfd: syscon: Add atmel-matrix registers definition > > memory: atmel-ebi: add Atmel EBI (External Bus Interface) driver > > mfd: syscon: atmel-smc: Add driver for atmel SMC > > configs: at91: sam9x60ek: Enable DM based nand driver > > ARM: dts: at91: sam9x60: Add nodes for EBI and NAND > > ARM: dts: at91: sam9x60ek: Enable NAND support > > board: sam9x60ek: remove nand init from board file > > > > MAINTAINERS |1 + > > arch/arm/dts/sam9x60.dtsi| 42 + > > arch/arm/dts/sam9x60ek.dts | 103 + > > board/atmel/sam9x60ek/sam9x60ek.c| 59 - > > configs/sam9x60ek_mmc_defconfig |9 +- > > configs/sam9x60ek_nandflash_defconfig|9 +- > > configs/sam9x60ek_qspiflash_defconfig|8 +- > > drivers/Kconfig |2 + > > drivers/Makefile |1 + > > drivers/memory/Kconfig |7 + > > drivers/memory/Makefile |1 + > > drivers/memory/atmel_ebi.c | 37 + > > drivers/mfd/Kconfig |4 + > > drivers/mfd/Makefile |1 + > > drivers/mfd/atmel-smc.c | 364 +++ > > drivers/mtd/nand/raw/Kconfig |8 + > > drivers/mtd/nand/raw/Makefile|1 + > > drivers/mtd/nand/raw/atmel/Makefile |5 + > > drivers/mtd/nand/raw/atmel/nand-controller.c | 2300 ++ > > drivers/mtd/nand/raw/atmel/pmecc.c | 969 > > drivers/mtd/nand/raw/atmel/pmecc.h | 94 + > > include/linux/mfd/syscon/atmel-matrix.h | 112 + > > include/linux/mfd/syscon/atmel-smc.h | 119 + > > 23 files changed, 4188 insertions(+), 68 deletions(-) > > create mode 100644 drivers/memory/atmel_ebi.c > > create mode 100644 drivers/mfd/Kconfig > > create mode 100644 drivers/mfd/Makefile > > create mode 100644 drivers/mfd/atmel-smc.c > > create mode 100644 drivers/mtd/nand/raw/atmel/Makefile > > create mode 100644 drivers/mtd/nand/raw/atmel/nand-controller.c > > create mode 100644 drivers/mtd/nand/raw/atmel/pmecc.c > > create mode 100644 drivers/mtd/nand/raw/atmel/pmecc.h > > create mode 100644 include/linux/mfd/syscon/atmel-matrix.h > > create mode 100644 include/linux/mfd/syscon/atmel-smc.h > > > -- Michael Nazzareno Trimarchi Co-Founder & Chief Executive Officer M. +39 347 913 2170 mich...@amarulasolutions.com __ Amarula Solutions BV Joop Geesinkweg 125, 1114 AB, Amsterdam, NL T. +31 (0)85 111 9172 i...@amarulasolutions.com www.amarulasolutions.com
Re: [PATCH] Provide more details of exactly how configuration signatures are calculated
OK. I've just realized there is an important warning missing from
this (if you verify a configuration signature outside u-boot, you
_must_ verify the hashes for the kernel, fdt, and ramdisk images match
too). What is the protocol for handling that? Submit a new patch
with title "[Patch v2] ..."?
I will hold off submitting that in case there are other comments that
need to be addressed.
Martin
On Wed, 20 Jul 2022 at 08:23, Martin Bonner wrote:
>
> There are a couple of uncertainties still remaining:
> - The "hashed-nodes" property is created by mkimage in image order.
> What happens if somebody manipulates a signed image to change the
> order? Does it make any difference? Do u-boot and fit_check_sign
> handle it in the same way? (My preference would be that both fail the
> signature on the grounds that there is no good reason for the nodes to
> be out of order, and it suggests an attacker is trying to be clever.)
> - What happens if the image contains a DTB_NOP tag? Is it included or
> not? (Again, I would fail the signature if it does.)
>
> Martin
>
> On Wed, 20 Jul 2022 at 08:14, Martin Bonner wrote:
> >
> > I have just spent a week reverse-engineering this, so I thought I'd
> > contribute the work back to the community
> >
> > diff --git a/doc/uImage.FIT/signature.txt b/doc/uImage.FIT/signature.txt
> > index 61a72db3c7..61cdd55e40 100644
> > --- a/doc/uImage.FIT/signature.txt
> > +++ b/doc/uImage.FIT/signature.txt
> > @@ -382,6 +382,25 @@ verified later even if the FIT has been signed
> > with other keys in the
> > meantime.
> >
> >
> > +Details
> > +---
> > +The signature node contains a property ('hashed-nodes') which lists all the
> > +nodes that the signature was made over. The image is walked in order and
> > each
> > +tag processed as follows:
> > +- DTB_BEGIN_NODE: The tag and the following name are added to the
> > signature if
> > + the node or its parent are present in 'hashed-nodes'
> > +- DTB_END_NODE: The tag is added to the signature if the node or its
> > parent are
> > + present in 'hashed-nodes'
> > +- DTB_PROPERTY: The tag, the length word, the offset in the string table,
> > and
> > + the data are all included if the node is present in 'hashed-nodes' and
> > the
> > + property name is not 'data'.
> > +- DTB_END: The tag is always included.
> > +
> > +In addition, the signature contains a property 'hashed-strings' which
> > contains
> > +the offset and length in the string table of the strings that are to be
> > added
> > +to the signature (this is always done at the end).
> > +
> > +
> > Verification
> >
> > FITs are verified when loaded. After the configuration is selected a list
> >
> > --
> > Martin
Re: u-boot and IPv6
On Wed, 20 Jul 2022, 5:02 AM Dhananjay Phadke, wrote: > > > On Wed, 13 Jul 2022, Chris Packham wrote: > > > On Tue, Jul 12, 2022 at 7:40 PM Chris Packham > wrote: > >> > >> Hi Sean and Dhananjay, > >> > >> Adding U-Boot ML to the Cc > >> > > [...] > > >> > >> IPv6 support is definitely something I want to get landed in upstream > U-Boot. > >> > >> It seemed to be fairly well received last time I posted the series. The > main thing lacking was tests. That's pretty much where things were at last > time I touched it. As usual life and work commitments have stopped me from > progressing it further. > >> > >> In the meantime U-Boot's testing infrastructure has improved a lot > which should make adding the tests easier. I know there have been some more > changes in net that will conflict but not badly. > >> > >> At $dayjob we have merged a newer u-boot version into our fork so I do > have something that is effectively a post state for the merge conflict to > refer to but it's not the broken out series that I'd like to submit. > >> > >> I think I should be able to get the series rebased against master (or > the just released 2022.07 might be more useful as a base). I can probably > get that up on github in the next couple of days. > > > > I've rebased my series against v2022.07 you can get the code from the > > ipv6 branch of https://github.com/cpackham/u-boot.git > > > > I've only lightly compile tested it so I've no idea if it's still > functional > > Hi Chris, > > Thank you for refreshing the topic and rebasing. Are you planning to post > a v4? > Besides tests, you had identified some gaps in previous series (DHCP, > SLAAC, etc). > We are looking for having IPv6 in upstream, happy to fill in what will > help it. > I wasn't planning on sumbitting v4 until I had some reasonable test coverage. I haven't got much time to spend on adding test right now. I will try to spend some on it over the next few weekends. DHCP and SLAAC would be decent follow on features from the initial support for static addressing. I think both of these were requested when I initially proposed IPv6 support for u-boot. If you're keen to contribute tests or DHCP/SLAAC I'd be happy to add them to my series. > Regards, > Dhananjay >
[PATCH 1/3] reset: zynqmp: Add reset driver support for versal
From: T Karthik Reddy
Add support for versal platform by adding "xlnx,versal-reset"
compatible string in zynqmp-reset driver. Reset numbering schema
for versal is not same as zynqmp, so nr_reset and reset_id are
set to zero. In case of assert/dessert, required device reset id
is sent from respective driver through struct reset_ctl.
Signed-off-by: T Karthik Reddy
Signed-off-by: Ashok Reddy Soma
---
drivers/reset/Kconfig| 6 +++---
drivers/reset/reset-zynqmp.c | 10 +++---
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index b57714111b..69a7b4ccba 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -199,11 +199,11 @@ config RESET_SCMI
protocol communication with a SCMI server.
config RESET_ZYNQMP
- bool "Reset Driver for Xilinx ZynqMP SoC's"
+ bool "Reset Driver for Xilinx ZynqMP & Versal SoC's"
depends on DM_RESET && ZYNQMP_FIRMWARE
help
- Support for reset controller on Xilinx ZynqMP SoC. Driver is only
- passing request via Xilinx firmware interface to TF-A and PMU
+ Support for reset controller on Xilinx ZynqMP & Versal SoC's. Driver
+ is only passing request via Xilinx firmware interface to TF-A and PMU
firmware.
config RESET_DRA7
diff --git a/drivers/reset/reset-zynqmp.c b/drivers/reset/reset-zynqmp.c
index 4e3f907980..52c08c4722 100644
--- a/drivers/reset/reset-zynqmp.c
+++ b/drivers/reset/reset-zynqmp.c
@@ -53,7 +53,7 @@ static int zynqmp_reset_request(struct reset_ctl *rst)
dev_dbg(rst->dev, "%s(rst=%p) (id=%lu) (nr_reset=%d)\n", __func__,
rst, rst->id, priv->nr_reset);
- if (rst->id > priv->nr_reset)
+ if (priv->nr_reset && rst->id > priv->nr_reset)
return -EINVAL;
return 0;
@@ -63,8 +63,11 @@ static int zynqmp_reset_probe(struct udevice *dev)
{
struct zynqmp_reset_priv *priv = dev_get_priv(dev);
- priv->reset_id = ZYNQMP_RESET_ID;
- priv->nr_reset = ZYNQMP_NR_RESETS;
+ if (device_is_compatible(dev, "xlnx,zynqmp-reset")) {
+ priv->reset_id = ZYNQMP_RESET_ID;
+ priv->nr_reset = ZYNQMP_NR_RESETS;
+ }
+
return 0;
}
@@ -76,6 +79,7 @@ const struct reset_ops zynqmp_reset_ops = {
static const struct udevice_id zynqmp_reset_ids[] = {
{ .compatible = "xlnx,zynqmp-reset" },
+ { .compatible = "xlnx,versal-reset" },
{ }
};
--
2.17.1
[PATCH 0/3] Add reset driver support for ZynqMP and Versal
This patch series does following things - Add reset driver support for Versal platform - Enable reset driver support for ZynqMP and Versal platforms Ashok Reddy Soma (1): arm64: zynqmp: Enable reset driver Michal Simek (1): arm64: versal: Enable reset driver for versal T Karthik Reddy (1): reset: zynqmp: Add reset driver support for versal configs/xilinx_versal_virt_defconfig | 2 ++ configs/xilinx_zynqmp_virt_defconfig | 2 ++ drivers/reset/Kconfig| 6 +++--- drivers/reset/reset-zynqmp.c | 10 +++--- 4 files changed, 14 insertions(+), 6 deletions(-) -- 2.17.1
[PATCH 2/3] arm64: versal: Enable reset driver for versal
From: Michal Simek Add CONFIG_DM_RESET and CONFIG_RESET_ZYNQMP configs in versal default configuration to enable support for reset driver for versal platform. Signed-off-by: Michal Simek Signed-off-by: T Karthik Reddy Signed-off-by: Ashok Reddy Soma --- configs/xilinx_versal_virt_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index 7f0bcb2eaa..d2490fe7c5 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -100,6 +100,8 @@ CONFIG_PHY_GIGE=y CONFIG_XILINX_AXIEMAC=y CONFIG_XILINX_AXIMRMAC=y CONFIG_ZYNQ_GEM=y +CONFIG_DM_RESET=y +CONFIG_RESET_ZYNQMP=y CONFIG_ARM_DCC=y CONFIG_PL01X_SERIAL=y CONFIG_XILINX_UARTLITE=y -- 2.17.1
[PATCH 3/3] arm64: zynqmp: Enable reset driver
Enable reset driver for ZynqMP platforms. This will enable us to reset the IP's using generic reset_assert and reset_deassert calls. Signed-off-by: T Karthik Reddy Signed-off-by: Ashok Reddy Soma --- configs/xilinx_zynqmp_virt_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 89622d18f8..71f71ff905 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -184,6 +184,8 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_PWM=y CONFIG_PWM_CADENCE_TTC=y +CONFIG_DM_RESET=y +CONFIG_RESET_ZYNQMP=y CONFIG_DM_RTC=y CONFIG_RTC_EMULATION=y CONFIG_RTC_ZYNQMP=y -- 2.17.1
[PATCH] spi: cadence_ospi_versal: Reset ospi controller using reset driver api's
From: T Karthik Reddy
Add a new function to reset the ospi controller. Use reset_assert,
reset_deassert api's to reset the ospi controller. In mini U-Boot
case as ZYNQMP_FIRMWARE config is disabled, reset the controller
directly using register writes.
Signed-off-by: T Karthik Reddy
Signed-off-by: Ashok Reddy Soma
---
arch/arm/mach-versal/include/mach/hardware.h | 1 +
drivers/spi/cadence_ospi_versal.c| 29
drivers/spi/cadence_qspi.h | 1 +
3 files changed, 31 insertions(+)
diff --git a/arch/arm/mach-versal/include/mach/hardware.h
b/arch/arm/mach-versal/include/mach/hardware.h
index 000af974e8..429765234f 100644
--- a/arch/arm/mach-versal/include/mach/hardware.h
+++ b/arch/arm/mach-versal/include/mach/hardware.h
@@ -61,6 +61,7 @@ struct rpu_regs {
#define VERSAL_SLCR_BASEADDR 0xF106
#define VERSAL_AXI_MUX_SEL (VERSAL_SLCR_BASEADDR + 0x504)
#define VERSAL_OSPI_LINEAR_MODEBIT(1)
+#define VERSAL_OSPI_CTRL_RST (VERSAL_CRP_BASEADDR + 0x304)
struct crp_regs {
u32 reserved0[128];
diff --git a/drivers/spi/cadence_ospi_versal.c
b/drivers/spi/cadence_ospi_versal.c
index 52bcad053f..a9c5daff20 100644
--- a/drivers/spi/cadence_ospi_versal.c
+++ b/drivers/spi/cadence_ospi_versal.c
@@ -127,6 +127,35 @@ int cadence_qspi_apb_wait_for_dma_cmplt(struct
cadence_spi_plat *plat)
return 0;
}
+int cadence_spi_versal_ctrl_reset(struct cadence_spi_priv *priv)
+{
+ int ret;
+
+ if (CONFIG_IS_ENABLED(ZYNQMP_FIRMWARE)) {
+ /* Assert ospi controller */
+ ret = reset_assert(priv->resets->resets);
+ if (ret)
+ return ret;
+
+ udelay(10);
+
+ /* Deassert ospi controller */
+ ret = reset_deassert(priv->resets->resets);
+ if (ret)
+ return ret;
+ } else {
+ /* Assert ospi controller */
+ setbits_le32((u32 *)VERSAL_OSPI_CTRL_RST, 1);
+
+ udelay(10);
+
+ /* Deassert ospi controller */
+ clrbits_le32((u32 *)VERSAL_OSPI_CTRL_RST, 1);
+ }
+
+ return 0;
+}
+
#if defined(CONFIG_DM_GPIO)
int cadence_spi_versal_flash_reset(struct udevice *dev)
{
diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
index c8d16bb0e4..3f5f45282d 100644
--- a/drivers/spi/cadence_qspi.h
+++ b/drivers/spi/cadence_qspi.h
@@ -285,5 +285,6 @@ int cadence_qspi_apb_wait_for_dma_cmplt(struct
cadence_spi_plat *plat);
int cadence_qspi_apb_exec_flash_cmd(void *reg_base, unsigned int reg);
int cadence_qspi_versal_flash_reset(struct udevice *dev);
void cadence_qspi_apb_enable_linear_mode(bool enable);
+int cadence_spi_versal_ctrl_reset(struct cadence_spi_priv *priv);
#endif /* __CADENCE_QSPI_H__ */
--
2.17.1
[PATCH v3 1/2] tools: mkeficapsule: use pkg-config to get -luuid and -lgnutls
Instead of hardcoding -luuid -lgnutls as the flags needed to build mkeficapsule, use pkg-config when available. We gracefully fallback on the previous behavior of hardcoding -luuid -lgnutls if pkg-config is not available or fails with an error. Reviewed-by: Heinrich Schuchardt Signed-off-by: Heiko Thiery --- v3: - added reviewed-by v2: - also add cflags detection via pkg-config (Thanks Pali) tools/Makefile | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/tools/Makefile b/tools/Makefile index 9f2339666a..aab06aec93 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -242,7 +242,10 @@ hostprogs-$(CONFIG_MIPS) += mips-relocs hostprogs-$(CONFIG_ASN1_COMPILER) += asn1_compiler HOSTCFLAGS_asn1_compiler.o = -idirafter $(srctree)/include -HOSTLDLIBS_mkeficapsule += -lgnutls -luuid +HOSTCFLAGS_mkeficapsule.o += \ + $(shell pkg-config --cflags gnutls uuid 2> /dev/null || echo "") +HOSTLDLIBS_mkeficapsule += \ + $(shell pkg-config --libs gnutls uuid 2> /dev/null || echo "-lgnutls -luuid") hostprogs-$(CONFIG_TOOLS_MKEFICAPSULE) += mkeficapsule # We build some files with extra pedantic flags to try to minimize things -- 2.30.2
[PATCH v3 2/2] tools: kwboot: use pkg-config to get -ltinfo
Instead of hardcoding -ltinfo as the flags needed to build kwboot, use pkg-config when available. We gracefully fallback on the previous behavior of hardcoding -ltinfo if pkg-config is not available or fails with an error. Reviewed-by: Pali Rohár Signed-off-by: Heiko Thiery --- v3: - remove cflags detection again - added reviewed-by v2: - also add cflags detection via pkg-config (Thanks Pali) tools/Makefile | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tools/Makefile b/tools/Makefile index aab06aec93..005e7362a3 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -198,7 +198,9 @@ hostprogs-$(CONFIG_EXYNOS5420) += mkexynosspl HOSTCFLAGS_mkexynosspl.o := -pedantic HOSTCFLAGS_kwboot.o += -pthread -HOSTLDLIBS_kwboot += -pthread -ltinfo +HOSTLDLIBS_kwboot += -pthread +HOSTLDLIBS_kwboot += \ + $(shell pkg-config --libs tinfo 2> /dev/null || echo "-ltinfo") ifdtool-objs := $(LIBFDT_OBJS) ifdtool.o hostprogs-$(CONFIG_X86) += ifdtool -- 2.30.2
Reading GPIOs with DM_GPIO before device tree is loaded
Hi,
in board_early_init_f(), i call a custom function get_som_revision() to read
some GPIOs that are used to determine the SOM revision. This function basically
sets the iomux, and then uses gpio_request/gpio_direction_input/gpio_get_value
functions to read the GPIOs. Then, this SOM revision information is used in
board_fit_config_name_match() to decide which device tree to load.
This works perfectly fine without CONFIG_DM_GPIO. However, if I enable
CONFIG_DM_GPIO, it doesn't work anymore. There is an error when calling
gpio_request().
What is the correct way to read GPIOs BEFORE any device tree is loaded?
My board uses an MX6Q SOM.
Here is part of the code I am using:
static iomux_v3_cfg_t const boardcfg_pads[] = {
MX6_PAD_DISP0_DAT15__GPIO5_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_DISP0_DAT8__GPIO4_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_DISP0_DAT0__GPIO4_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_ENET_RXD1__GPIO1_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static int som_revision = -1;
static const int boardcfg_gpio[] = {
IMX_GPIO_NR(5, 9),
IMX_GPIO_NR(4, 29),
IMX_GPIO_NR(4, 21),
IMX_GPIO_NR(1, 27),
IMX_GPIO_NR(1, 26),
};
static void get_som_revision(void)
{
int i;
int rc;
som_revision = 0;
SETUP_IOMUX_PADS(boardcfg_pads);
for (i = 0; i < ARRAY_SIZE(boardcfg_gpio); ++i) {
int v;
rc = gpio_request(boardcfg_gpio[i], "som-revision-gpio");
if (rc) {
printf("%s(): gpio request %d failed\n", __func__, i);
som_revision = -1;
return;
}
gpio_direction_input(boardcfg_gpio[i]);
v = gpio_get_value(boardcfg_gpio[i]);
if ((v == 0) || (v == 1))
som_revision |= v << i;
else {
som_revision = -1;
return;
}
}
}
int board_early_init_f(void)
{
setup_iomux_uart();
get_som_revision();
return 0;
}
Thank you,
Hugo Villeneuve.
Booting from SPI-NAND
Hello, I have an Allwinner suniv f1c100s and trying to boot the device from SPI-NAND. Booting from SD-Cards works without problems. I'm using "sunxi-next" branch from "sunxi U-Boot Custodian Tree". The SPI-NAND device is detected with "mtd list", but when flashing u-boot with spl to the SPI-NAND, the device doesn't boot. Not even the SPL Boot Message is showing up. I attached the output of "mtd list" and the config at the end of this message. Can someone give me a hint? List of MTD devices: * spi-nand0 - device: w25n512@0 - parent: spi@1c05000 - driver: spi_nand - path: /soc/spi@1c05000/w25n512@0 - type: NAND flash - block size: 0x2 bytes - min I/O: 0x800 bytes - OOB size: 64 bytes - OOB available: 24 bytes - 0x-0x0800 : "spi-nand0" - 0x-0x0008 : "u-boot" - 0x0008-0x0400 : "linux" config: CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_SUNXI=y CONFIG_ENV_SIZE=0x8000 CONFIG_ENV_OFFSET=0xf8000 CONFIG_ENV_SECT_SIZE=0x800 CONFIG_DEFAULT_DEVICE_TREE="suniv-f1c100s-mc4l" CONFIG_SPL=y CONFIG_MACH_SUNIV=y CONFIG_DRAM_CLK=156 CONFIG_DRAM_ZQ=0 # CONFIG_VIDEO_SUNXI is not set CONFIG_SPL_SPI_SUNXI=y CONFIG_SD_BOOT=y CONFIG_SPI_BOOT=y CONFIG_LOG=y CONFIG_LOG_MAX_LEVEL=7 CONFIG_SPL_SHOW_ERRORS=y CONFIG_SHOW_ERRORS=y CONFIG_SPL_MTD_SUPPORT=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set CONFIG_CMD_CLK=y CONFIG_CMD_MTD=y # CONFIG_CMD_SF is not set CONFIG_CMD_SPI=y CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y # CONFIG_NET is not set CONFIG_DM=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_SPI_NAND=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y CONFIG_SPI=y
Re: [PATCH v3 1/2] tools: mkeficapsule: use pkg-config to get -luuid and -lgnutls
On Wed, Jul 20, 2022 at 12:31:33PM +0200, Heiko Thiery wrote: > Instead of hardcoding -luuid -lgnutls as the flags needed to build > mkeficapsule, use pkg-config when available. > > We gracefully fallback on the previous behavior of hardcoding -luuid > -lgnutls if pkg-config is not available or fails with an error. > > Reviewed-by: Heinrich Schuchardt > Signed-off-by: Heiko Thiery > --- > v3: > - added reviewed-by > > v2: > - also add cflags detection via pkg-config (Thanks Pali) > > tools/Makefile | 5 - > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/tools/Makefile b/tools/Makefile > index 9f2339666a..aab06aec93 100644 > --- a/tools/Makefile > +++ b/tools/Makefile > @@ -242,7 +242,10 @@ hostprogs-$(CONFIG_MIPS) += mips-relocs > hostprogs-$(CONFIG_ASN1_COMPILER)+= asn1_compiler > HOSTCFLAGS_asn1_compiler.o = -idirafter $(srctree)/include > > -HOSTLDLIBS_mkeficapsule += -lgnutls -luuid > +HOSTCFLAGS_mkeficapsule.o += \ > + $(shell pkg-config --cflags gnutls uuid 2> /dev/null || echo "") > +HOSTLDLIBS_mkeficapsule += \ > + $(shell pkg-config --libs gnutls uuid 2> /dev/null || echo "-lgnutls > -luuid") It would be logically better to call pkg-config for each library, that is, HOSTLDLIBS_mkeficapsule += \ $(shell pkg-config --libs gnutls 2> /dev/null || echo " -lgnutls") HOSTLDLIBS_mkeficapsule += \ $(shell pkg-config --libs uuid 2> /dev/null || echo " -luuid") Thanks, -Takahiro Akashi > hostprogs-$(CONFIG_TOOLS_MKEFICAPSULE) += mkeficapsule > > # We build some files with extra pedantic flags to try to minimize things > -- > 2.30.2 >
Re: Please pull u-boot-i2c
On Tue, Jul 19, 2022 at 05:24:59PM +0200, Heiko Schocher wrote: > Hello Tom, > > please pull from: > > The following changes since commit 26f6f7fb5c0651d65afdee6d8ed36063606179a8: > > Merge branch '2022-07-14-migrate-wiki-to-sphinx' (2022-07-14 18:43:51 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-i2c.git tags/for-v2022.10 > > for you to fetch changes up to 49f3a42edf097fbaca76aef9bfcd98d871b442cb: > > i2c: avoid dynamic stack use in dm_i2c_write (2022-07-19 13:46:28 +0200) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-usb/master
On Tue, Jul 19, 2022 at 08:55:48PM +0200, Marek Vasut wrote: > The following changes since commit 26f6f7fb5c0651d65afdee6d8ed36063606179a8: > > Merge branch '2022-07-14-migrate-wiki-to-sphinx' (2022-07-14 18:43:51 > -0400) > > are available in the Git repository at: > > git://source.denx.de/u-boot-usb.git master > > for you to fetch changes up to 9674c09b7495d15017b68a3d462b17040c12ff70: > > musb: sunxi: Allow host-side USB with external VBUS (2022-07-15 14:10:39 > +0200) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: Please pull u-boot-ubi
On Wed, Jul 20, 2022 at 09:02:41AM +0200, Heiko Schocher wrote: > Hello Tom, > > please pull from: > > The following changes since commit fc97ff2695d6d7fbea7d5fda7b080f405d6ee744: > > Merge https://source.denx.de/u-boot/custodians/u-boot-sunxi (2022-07-19 > 10:52:15 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-ubi.git for-v2022.10 fatal: couldn't find remote ref for-v2022.10 Did you forget to push the tag maybe? -- Tom signature.asc Description: PGP signature
Re: Please pull u-boot-ubi
Hello Tom, On 20.07.22 13:12, Tom Rini wrote: > On Wed, Jul 20, 2022 at 09:02:41AM +0200, Heiko Schocher wrote: >> Hello Tom, >> >> please pull from: >> >> The following changes since commit fc97ff2695d6d7fbea7d5fda7b080f405d6ee744: >> >> Merge https://source.denx.de/u-boot/custodians/u-boot-sunxi (2022-07-19 >> 10:52:15 -0400) >> >> are available in the Git repository at: >> >> https://source.denx.de/u-boot/custodians/u-boot-ubi.git for-v2022.10 > > fatal: couldn't find remote ref for-v2022.10 > > Did you forget to push the tag maybe? Hmm.. Yes ... seems so ... the commit is there: https://source.denx.de/u-boot/custodians/u-boot-ubi/-/commit/e2e6caa01ba97bcdb82100c6b928b5743e3aae6c $ git push g...@source.denx.de:u-boot/custodians/u-boot-ubi.git +for-v2022.10 [...] To source.denx.de:u-boot/custodians/u-boot-ubi.git * [new tag] for-v2022.10 -> for-v2022.10 ...please try again, sorry. bye, Heiko -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: h...@denx.de
Re: Please pull u-boot-ubi
On Wed, Jul 20, 2022 at 01:36:10PM +0200, Heiko Schocher wrote: > Hello Tom, > > On 20.07.22 13:12, Tom Rini wrote: > > On Wed, Jul 20, 2022 at 09:02:41AM +0200, Heiko Schocher wrote: > >> Hello Tom, > >> > >> please pull from: > >> > >> The following changes since commit > >> fc97ff2695d6d7fbea7d5fda7b080f405d6ee744: > >> > >> Merge https://source.denx.de/u-boot/custodians/u-boot-sunxi (2022-07-19 > >> 10:52:15 -0400) > >> > >> are available in the Git repository at: > >> > >> https://source.denx.de/u-boot/custodians/u-boot-ubi.git for-v2022.10 > > > > fatal: couldn't find remote ref for-v2022.10 > > > > Did you forget to push the tag maybe? > > Hmm.. Yes ... seems so ... the commit is there: > https://source.denx.de/u-boot/custodians/u-boot-ubi/-/commit/e2e6caa01ba97bcdb82100c6b928b5743e3aae6c > > > $ git push g...@source.denx.de:u-boot/custodians/u-boot-ubi.git +for-v2022.10 > [...] > To source.denx.de:u-boot/custodians/u-boot-ubi.git > * [new tag] for-v2022.10 -> for-v2022.10 > > ...please try again, sorry. Got it now, thanks. -- Tom signature.asc Description: PGP signature
[PATCH v7 0/7] tpm: rng: Move TPM RNG functionality to driver model
The TPM device provides the random number generator(RNG) functionality, whereby sending a command to the TPM device results in the TPM device responding with random bytes. There was a discussion on the mailing list earlier[1], where it was explained that platforms with a TPM device can install the EFI_RNG_PROTOCOL for getting the random bytes instead of populating the dtb with the kaslr-seed property. That would make it possible to measure the dtb. The TPM uclass driver adds the RNG child device as part of it's post_probe function. Some additional changes have also been made to facilitate the use of the RNG devices, including extending the 'rng' command to take the RNG device as one of the command-line parameters. This series depends on a patch[2] from Simon Glass for moving the TPM device version detection functions to the tpm_api.h header as static inline functions. These patches were under discussion earlier, specifically the patch to add the RNG functionality under the TPM device as a child, either through manual binding or through the device tree. Ilias had commented on the discussion last[3]. The discussion can be resumed through this version. I have dropped certain patches which were changing some of the TPM API functions to return an int instead of the current u32. These patches have been dropped due to review comments from Simon[4]. This work can be taken up separately, if desired. [1] - https://lore.kernel.org/u-boot/20220103120738.47835-1-ilias.apalodi...@linaro.org/ [2] - https://lore.kernel.org/u-boot/20220301001125.1554442-2-...@chromium.org/T/#u [3] - https://lists.denx.de/pipermail/u-boot/2022-April/481708.html [4] - https://lists.denx.de/pipermail/u-boot/2022-March/477883.html Simon Glass (1): tpm: Export the TPM-version functions Sughosh Ganu (6): tpm: rng: Add driver model interface for TPM RNG device tpm: Add the RNG child device cmd: rng: Add support for selecting RNG device cmd: rng: Use a statically allocated array for random bytes doc: rng: Add documentation for the rng command test: rng: Add a UT testcase for the rng command cmd/Kconfig | 1 + cmd/rng.c| 42 +++-- doc/usage/cmd/rng.rst| 26 +++ doc/usage/index.rst | 1 + drivers/rng/Kconfig | 9 drivers/rng/Makefile | 1 + drivers/rng/tpm_rng.c| 23 ++ drivers/tpm/tpm-uclass.c | 37 +-- include/tpm_api.h| 10 lib/Kconfig | 1 + lib/tpm_api.c| 98 ++-- test/dm/rng.c| 29 12 files changed, 205 insertions(+), 73 deletions(-) create mode 100644 doc/usage/cmd/rng.rst create mode 100644 drivers/rng/tpm_rng.c -- 2.34.1
[PATCH v7 1/7] tpm: Export the TPM-version functions
From: Simon Glass
These functions should really be available outside the TPM code, so that
other callers can find out which version the TPM is. Rename them to have
a tpm_ prefix() and add them to the header file.
Signed-off-by: Simon Glass
---
Changes since V6: None
include/tpm_api.h | 10 ++
lib/tpm_api.c | 92 +--
2 files changed, 51 insertions(+), 51 deletions(-)
diff --git a/include/tpm_api.h b/include/tpm_api.h
index ef45b43a8f..11aa14eb79 100644
--- a/include/tpm_api.h
+++ b/include/tpm_api.h
@@ -319,4 +319,14 @@ u32 tpm_write_lock(struct udevice *dev, u32 index);
*/
u32 tpm_resume(struct udevice *dev);
+static inline bool tpm_is_v1(struct udevice *dev)
+{
+ return IS_ENABLED(CONFIG_TPM_V1) && tpm_get_version(dev) == TPM_V1;
+}
+
+static inline bool tpm_is_v2(struct udevice *dev)
+{
+ return IS_ENABLED(CONFIG_TPM_V2) && tpm_get_version(dev) == TPM_V2;
+}
+
#endif /* __TPM_API_H */
diff --git a/lib/tpm_api.c b/lib/tpm_api.c
index 4c662640a9..4ac4612c81 100644
--- a/lib/tpm_api.c
+++ b/lib/tpm_api.c
@@ -11,21 +11,11 @@
#include
#include
-static bool is_tpm1(struct udevice *dev)
-{
- return IS_ENABLED(CONFIG_TPM_V1) && tpm_get_version(dev) == TPM_V1;
-}
-
-static bool is_tpm2(struct udevice *dev)
-{
- return IS_ENABLED(CONFIG_TPM_V2) && tpm_get_version(dev) == TPM_V2;
-}
-
u32 tpm_startup(struct udevice *dev, enum tpm_startup_type mode)
{
- if (is_tpm1(dev)) {
+ if (tpm_is_v1(dev)) {
return tpm1_startup(dev, mode);
- } else if (is_tpm2(dev)) {
+ } else if (tpm_is_v2(dev)) {
enum tpm2_startup_types type;
switch (mode) {
@@ -47,9 +37,9 @@ u32 tpm_startup(struct udevice *dev, enum tpm_startup_type
mode)
u32 tpm_resume(struct udevice *dev)
{
- if (is_tpm1(dev))
+ if (tpm_is_v1(dev))
return tpm1_startup(dev, TPM_ST_STATE);
- else if (is_tpm2(dev))
+ else if (tpm_is_v2(dev))
return tpm2_startup(dev, TPM2_SU_STATE);
else
return -ENOSYS;
@@ -57,9 +47,9 @@ u32 tpm_resume(struct udevice *dev)
u32 tpm_self_test_full(struct udevice *dev)
{
- if (is_tpm1(dev))
+ if (tpm_is_v1(dev))
return tpm1_self_test_full(dev);
- else if (is_tpm2(dev))
+ else if (tpm_is_v2(dev))
return tpm2_self_test(dev, TPMI_YES);
else
return -ENOSYS;
@@ -67,9 +57,9 @@ u32 tpm_self_test_full(struct udevice *dev)
u32 tpm_continue_self_test(struct udevice *dev)
{
- if (is_tpm1(dev))
+ if (tpm_is_v1(dev))
return tpm1_continue_self_test(dev);
- else if (is_tpm2(dev))
+ else if (tpm_is_v2(dev))
return tpm2_self_test(dev, TPMI_NO);
else
return -ENOSYS;
@@ -86,7 +76,7 @@ u32 tpm_clear_and_reenable(struct udevice *dev)
return ret;
}
- if (is_tpm1(dev)) {
+ if (tpm_is_v1(dev)) {
ret = tpm1_physical_enable(dev);
if (ret != TPM_SUCCESS) {
log_err("TPM: Can't set enabled state\n");
@@ -105,9 +95,9 @@ u32 tpm_clear_and_reenable(struct udevice *dev)
u32 tpm_nv_enable_locking(struct udevice *dev)
{
- if (is_tpm1(dev))
+ if (tpm_is_v1(dev))
return tpm1_nv_define_space(dev, TPM_NV_INDEX_LOCK, 0, 0);
- else if (is_tpm2(dev))
+ else if (tpm_is_v2(dev))
return -ENOSYS;
else
return -ENOSYS;
@@ -115,9 +105,9 @@ u32 tpm_nv_enable_locking(struct udevice *dev)
u32 tpm_nv_read_value(struct udevice *dev, u32 index, void *data, u32 count)
{
- if (is_tpm1(dev))
+ if (tpm_is_v1(dev))
return tpm1_nv_read_value(dev, index, data, count);
- else if (is_tpm2(dev))
+ else if (tpm_is_v2(dev))
return tpm2_nv_read_value(dev, index, data, count);
else
return -ENOSYS;
@@ -126,9 +116,9 @@ u32 tpm_nv_read_value(struct udevice *dev, u32 index, void
*data, u32 count)
u32 tpm_nv_write_value(struct udevice *dev, u32 index, const void *data,
u32 count)
{
- if (is_tpm1(dev))
+ if (tpm_is_v1(dev))
return tpm1_nv_write_value(dev, index, data, count);
- else if (is_tpm2(dev))
+ else if (tpm_is_v2(dev))
return tpm2_nv_write_value(dev, index, data, count);
else
return -ENOSYS;
@@ -141,9 +131,9 @@ u32 tpm_set_global_lock(struct udevice *dev)
u32 tpm_write_lock(struct udevice *dev, u32 index)
{
- if (is_tpm1(dev))
+ if (tpm_is_v1(dev))
return -ENOSYS;
- else if (is_tpm2(dev))
+ else if (tpm_is_v2(dev))
return tpm2_write_lock(dev, index);
else
return -ENOSYS;
@@ -152,9 +142,9 @@ u32 tpm_write_lock(struct udevice *dev, u32 index)
u32 tpm_pcr
[PATCH v7 2/7] tpm: rng: Add driver model interface for TPM RNG device
The TPM device has a builtin random number generator(RNG)
functionality. Expose the RNG functions of the TPM device to the
driver model so that they can be used by the EFI_RNG_PROTOCOL if the
protocol is installed.
Also change the function arguments and return type of the random
number functions to comply with the driver model api.
Signed-off-by: Sughosh Ganu
---
Changes since V6:
* Remove the changes made in tpm-v[12].c to return -EIO instead of
TPM_LIB_ERROR as suggested by Simon
drivers/rng/Kconfig | 9 +
drivers/rng/Makefile | 1 +
drivers/rng/tpm_rng.c | 23 +++
lib/Kconfig | 1 +
lib/tpm_api.c | 6 +++---
5 files changed, 37 insertions(+), 3 deletions(-)
create mode 100644 drivers/rng/tpm_rng.c
diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig
index 21a9ff0195..16143681da 100644
--- a/drivers/rng/Kconfig
+++ b/drivers/rng/Kconfig
@@ -74,4 +74,13 @@ config RNG_SMCCC_TRNG
Enable random number generator for platforms that support Arm
SMCCC TRNG interface.
+config TPM_RNG
+ bool "Enable random number generator on TPM device"
+ depends on TPM
+ default y
+ help
+ The TPM device has an inbuilt random number generator
+ functionality. Enable random number generator on TPM
+ devices.
+
endif
diff --git a/drivers/rng/Makefile b/drivers/rng/Makefile
index 2494717d7c..78f61051ac 100644
--- a/drivers/rng/Makefile
+++ b/drivers/rng/Makefile
@@ -13,3 +13,4 @@ obj-$(CONFIG_RNG_STM32MP1) += stm32mp1_rng.o
obj-$(CONFIG_RNG_ROCKCHIP) += rockchip_rng.o
obj-$(CONFIG_RNG_IPROC200) += iproc_rng200.o
obj-$(CONFIG_RNG_SMCCC_TRNG) += smccc_trng.o
+obj-$(CONFIG_TPM_RNG) += tpm_rng.o
diff --git a/drivers/rng/tpm_rng.c b/drivers/rng/tpm_rng.c
new file mode 100644
index 00..1a5e9e2e4b
--- /dev/null
+++ b/drivers/rng/tpm_rng.c
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2022, Linaro Limited
+ */
+
+#include
+#include
+#include
+
+static int rng_tpm_random_read(struct udevice *dev, void *data, size_t count)
+{
+ return tpm_get_random(dev_get_parent(dev), data, count);
+}
+
+static const struct dm_rng_ops tpm_rng_ops = {
+ .read = rng_tpm_random_read,
+};
+
+U_BOOT_DRIVER(tpm_rng) = {
+ .name = "tpm-rng",
+ .id = UCLASS_RNG,
+ .ops= &tpm_rng_ops,
+};
diff --git a/lib/Kconfig b/lib/Kconfig
index 7dd777b56a..e888c29245 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -360,6 +360,7 @@ source lib/crypt/Kconfig
config TPM
bool "Trusted Platform Module (TPM) Support"
depends on DM
+ imply DM_RNG
help
This enables support for TPMs which can be used to provide security
features for your board. The TPM can be connected via LPC or I2C
diff --git a/lib/tpm_api.c b/lib/tpm_api.c
index 4ac4612c81..032f383ca0 100644
--- a/lib/tpm_api.c
+++ b/lib/tpm_api.c
@@ -269,7 +269,7 @@ u32 tpm_get_random(struct udevice *dev, void *data, u32
count)
if (tpm_is_v1(dev))
return tpm1_get_random(dev, data, count);
else if (tpm_is_v2(dev))
- return -ENOSYS; /* not implemented yet */
- else
- return -ENOSYS;
+ return tpm2_get_random(dev, data, count);
+
+ return -ENOSYS;
}
--
2.34.1
[PATCH v7 3/7] tpm: Add the RNG child device
The TPM device comes with the random number generator(RNG)
functionality which is built into the TPM device. Add logic to add the
RNG child device in the TPM uclass post probe callback.
The RNG device can then be used to pass a set of random bytes to the
linux kernel, need for address space randomisation through the
EFI_RNG_PROTOCOL interface.
Signed-off-by: Sughosh Ganu
---
Changes since V6: None
drivers/tpm/tpm-uclass.c | 37 +
1 file changed, 33 insertions(+), 4 deletions(-)
diff --git a/drivers/tpm/tpm-uclass.c b/drivers/tpm/tpm-uclass.c
index f67fe1019b..e1f1ef01e1 100644
--- a/drivers/tpm/tpm-uclass.c
+++ b/drivers/tpm/tpm-uclass.c
@@ -11,10 +11,15 @@
#include
#include
#include
+#include
#include
#include
#include "tpm_internal.h"
+#include
+
+#define TPM_RNG_DRV_NAME "tpm-rng"
+
int tpm_open(struct udevice *dev)
{
struct tpm_ops *ops = tpm_get_ops(dev);
@@ -136,12 +141,36 @@ int tpm_xfer(struct udevice *dev, const uint8_t *sendbuf,
size_t send_size,
return 0;
}
+static int tpm_uclass_post_probe(struct udevice *dev)
+{
+ int ret;
+ const char *drv = TPM_RNG_DRV_NAME;
+ struct udevice *child;
+
+ if (CONFIG_IS_ENABLED(TPM_RNG)) {
+ ret = device_find_first_child_by_uclass(dev, UCLASS_RNG,
+ &child);
+
+ if (ret != -ENODEV) {
+ log_debug("RNG child already added to the TPM
device\n");
+ return ret;
+ }
+
+ ret = device_bind_driver(dev, drv, "tpm-rng0", &child);
+ if (ret)
+ return log_msg_ret("bind", ret);
+ }
+
+ return 0;
+}
+
UCLASS_DRIVER(tpm) = {
- .id = UCLASS_TPM,
- .name = "tpm",
- .flags = DM_UC_FLAG_SEQ_ALIAS,
+ .id = UCLASS_TPM,
+ .name = "tpm",
+ .flags = DM_UC_FLAG_SEQ_ALIAS,
#if CONFIG_IS_ENABLED(OF_REAL)
- .post_bind = dm_scan_fdt_dev,
+ .post_bind = dm_scan_fdt_dev,
#endif
+ .post_probe = tpm_uclass_post_probe,
.per_device_auto= sizeof(struct tpm_chip_priv),
};
--
2.34.1
[PATCH v7 4/7] cmd: rng: Add support for selecting RNG device
The 'rng' u-boot command is used for printing a select number of
random bytes on the console. Currently, the RNG device from which the
random bytes are read is fixed. However, a platform can have multiple
RNG devices, one example being qemu, which has a virtio RNG device and
the RNG pseudo device through the TPM chip.
Extend the 'rng' command so that the user can provide the RNG device
number from which the random bytes are to be read. This will be the
device index under the RNG uclass.
Signed-off-by: Sughosh Ganu
Tested-by: Heinrich Schuchardt
Reviewed-by: Ilias Apalodimas
---
Changes since V6: None
cmd/rng.c | 31 +++
1 file changed, 23 insertions(+), 8 deletions(-)
diff --git a/cmd/rng.c b/cmd/rng.c
index 1ad5a096c0..2ddf27545f 100644
--- a/cmd/rng.c
+++ b/cmd/rng.c
@@ -13,19 +13,34 @@
static int do_rng(struct cmd_tbl *cmdtp, int flag, int argc, char *const
argv[])
{
- size_t n = 0x40;
+ size_t n;
struct udevice *dev;
void *buf;
+ int devnum;
int ret = CMD_RET_SUCCESS;
- if (uclass_get_device(UCLASS_RNG, 0, &dev) || !dev) {
+ switch (argc) {
+ case 1:
+ devnum = 0;
+ n = 0x40;
+ break;
+ case 2:
+ devnum = hextoul(argv[1], NULL);
+ n = 0x40;
+ break;
+ case 3:
+ devnum = hextoul(argv[1], NULL);
+ n = hextoul(argv[2], NULL);
+ break;
+ default:
+ return CMD_RET_USAGE;
+ }
+
+ if (uclass_get_device_by_seq(UCLASS_RNG, devnum, &dev) || !dev) {
printf("No RNG device\n");
return CMD_RET_FAILURE;
}
- if (argc >= 2)
- n = hextoul(argv[1], NULL);
-
buf = malloc(n);
if (!buf) {
printf("Out of memory\n");
@@ -46,12 +61,12 @@ static int do_rng(struct cmd_tbl *cmdtp, int flag, int
argc, char *const argv[])
#ifdef CONFIG_SYS_LONGHELP
static char rng_help_text[] =
- "[n]\n"
- " - print n random bytes\n";
+ "[dev [n]]\n"
+ " - print n random bytes read from dev\n";
#endif
U_BOOT_CMD(
- rng, 2, 0, do_rng,
+ rng, 3, 0, do_rng,
"print bytes from the hardware random number generator",
rng_help_text
);
--
2.34.1
[PATCH v7 5/7] cmd: rng: Use a statically allocated array for random bytes
Use a statically allocated buffer on stack instead of using malloc for
reading the random bytes. Using a local array is faster than
allocating heap memory on every initiation of the command.
Signed-off-by: Sughosh Ganu
---
Changes since V6: None
cmd/rng.c | 17 +++--
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/cmd/rng.c b/cmd/rng.c
index 2ddf27545f..81a23964b8 100644
--- a/cmd/rng.c
+++ b/cmd/rng.c
@@ -14,9 +14,9 @@
static int do_rng(struct cmd_tbl *cmdtp, int flag, int argc, char *const
argv[])
{
size_t n;
- struct udevice *dev;
- void *buf;
+ u8 buf[64];
int devnum;
+ struct udevice *dev;
int ret = CMD_RET_SUCCESS;
switch (argc) {
@@ -41,11 +41,10 @@ static int do_rng(struct cmd_tbl *cmdtp, int flag, int
argc, char *const argv[])
return CMD_RET_FAILURE;
}
- buf = malloc(n);
- if (!buf) {
- printf("Out of memory\n");
- return CMD_RET_FAILURE;
- }
+ if (!n)
+ return 0;
+
+ n = min(n, sizeof(buf));
if (dm_rng_read(dev, buf, n)) {
printf("Reading RNG failed\n");
@@ -54,15 +53,13 @@ static int do_rng(struct cmd_tbl *cmdtp, int flag, int
argc, char *const argv[])
print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, n);
}
- free(buf);
-
return ret;
}
#ifdef CONFIG_SYS_LONGHELP
static char rng_help_text[] =
"[dev [n]]\n"
- " - print n random bytes read from dev\n";
+ " - print n random bytes(max 64) read from dev\n";
#endif
U_BOOT_CMD(
--
2.34.1
[PATCH v7 6/7] doc: rng: Add documentation for the rng command
Add a usage document for the 'rng' u-boot command. Signed-off-by: Sughosh Ganu Reviewed-by: Ilias Apalodimas Reviewed-by: Simon Glass --- Changes since V6: None doc/usage/cmd/rng.rst | 26 ++ doc/usage/index.rst | 1 + 2 files changed, 27 insertions(+) create mode 100644 doc/usage/cmd/rng.rst diff --git a/doc/usage/cmd/rng.rst b/doc/usage/cmd/rng.rst new file mode 100644 index 00..1a352da41a --- /dev/null +++ b/doc/usage/cmd/rng.rst @@ -0,0 +1,26 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +rng command +=== + +Synopsis + + +:: + +rng [devnum [n]] + +Description +--- + +The *rng* command reads the random number generator(RNG) device and +prints the random bytes read on the console. A maximum of 64 bytes can +be read in one invocation of the command. + +devnum +The RNG device from which the random bytes are to be +read. Defaults to 0. + +n +Number of random bytes to be read and displayed on the +console. Default value is 0x40. Max value is 0x40. diff --git a/doc/usage/index.rst b/doc/usage/index.rst index 8b98629d6b..366c8bb4b0 100644 --- a/doc/usage/index.rst +++ b/doc/usage/index.rst @@ -55,6 +55,7 @@ Shell commands cmd/pstore cmd/qfw cmd/reset + cmd/rng cmd/sbi cmd/sf cmd/scp03 -- 2.34.1
[PATCH v7 7/7] test: rng: Add a UT testcase for the rng command
The 'rng' command dumps a number of random bytes on the console. Add a
set of tests for the 'rng' command. The test function performs basic
sanity testing of the command.
Since a unit test is being added for the command, enable it by default
in the sandbox platforms.
Signed-off-by: Sughosh Ganu
Reviewed-by: Simon Glass
---
Changes since V6: None
cmd/Kconfig | 1 +
test/dm/rng.c | 29 +
2 files changed, 30 insertions(+)
diff --git a/cmd/Kconfig b/cmd/Kconfig
index d5f842136c..76878ce307 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1961,6 +1961,7 @@ config CMD_GETTIME
config CMD_RNG
bool "rng command"
depends on DM_RNG
+ default y if SANDBOX
select HEXDUMP
help
Print bytes from the hardware random number generator.
diff --git a/test/dm/rng.c b/test/dm/rng.c
index 5b34c93ed6..6d1f68848d 100644
--- a/test/dm/rng.c
+++ b/test/dm/rng.c
@@ -25,3 +25,32 @@ static int dm_test_rng_read(struct unit_test_state *uts)
return 0;
}
DM_TEST(dm_test_rng_read, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+
+/* Test the rng command */
+static int dm_test_rng_cmd(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+
+ ut_assertok(uclass_get_device(UCLASS_RNG, 0, &dev));
+ ut_assertnonnull(dev);
+
+ ut_assertok(console_record_reset_enable());
+
+ run_command("rng", 0);
+ ut_assert_nextlinen(":");
+ ut_assert_nextlinen("0010:");
+ ut_assert_nextlinen("0020:");
+ ut_assert_nextlinen("0030:");
+ ut_assert_console_end();
+
+ run_command("rng 0 10", 0);
+ ut_assert_nextlinen(":");
+ ut_assert_console_end();
+
+ run_command("rng 20", 0);
+ ut_assert_nextlinen("No RNG device");
+ ut_assert_console_end();
+
+ return 0;
+}
+DM_TEST(dm_test_rng_cmd, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT |
UT_TESTF_CONSOLE_REC);
--
2.34.1
Re: [PATCH] Improve Window's build documentation
On Wed, Jul 20, 2022 at 2:50 PM Martin Bonner wrote: > > I have recently build the u-boot tools on Windows and ran into > difficulties. This patch to the documentation would have avoided > those difficulties. Contentious points: > > * While I have run the document through a rst previewer, I haven't run > the full test suite. I know, I know, everyone thinks _they_ don't > need to run the tests because reasons, but I think it's true this > time. > * I have removed the version numbers from the list of packages. I > don't think they are helpful, and are just maintenance overhead. (I > don't think I got those versions for example). > > I'd be grateful if @Bin Meng could review this, because `git blame` > says the file I am changing is all his. > > Are there any other formalities I need to complete before this can be > accepted into u-boot? Thanks for the patch! Please refer to the Linux kernel documentation on how to document your changes in the commit message: https://www.kernel.org/doc/html/latest/process/submitting-patches.html > > --- > diff --git a/doc/build/tools.rst b/doc/build/tools.rst > index c06f915274..95f1246617 100644 > --- a/doc/build/tools.rst > +++ b/doc/build/tools.rst > @@ -24,14 +24,20 @@ you can use MSYS2, a software distro and building > platform for Windows. > Download the MSYS2 installer from https://www.msys2.org. Make sure you have > installed all required packages below in order to build these host tools:: > > - * gcc (9.1.0) > - * make (4.2.1) > - * bison (3.4.2) > - * diffutils (3.7) > - * openssl-devel (1.1.1.d) > - > -Note the version numbers in these parentheses above are the package versions > -at the time being when writing this document. The MSYS2 installer tested is > + * gcc > + * make > + * bison > + * diffutils > + * openssl-devel > + * flex > + * libgnutls-devel > + * libuuid-devel > + > +You probably want ``git`` as well. You can install all these with:: > + > +$ pacman -S gcc make bison diffutils openssl=devel flex s/=/- > libgnutls-devel libuuid-devel git > + > +The MSYS2 installer tested is > http://repo.msys2.org/distrib/x86_64/msys2-x86_64-20190524.exe. > > There are 3 MSYS subsystems installed: MSYS2, MinGW32 and MinGW64. Each > Regards, Bin
[PATCH 00/53] NXP-IMX pending patches
From: Peng Fan This is to resend the pending patches [1,2,3] for Stefano to pick Patchset base: fc97ff2695d6d7fbea7d5fda7b080f405d6ee744 (origin/master, origin/HEAD, imx/master) Merge https://source.denx.de/u-boot/custodians/u-boot-sunxi Rebased patches to avoid buid break. 1. https://patchwork.ozlabs.org/project/uboot/patch/20220711071853.9299-1-peng@oss.nxp.com/ 2. https://patchwork.ozlabs.org/project/uboot/cover/20220705060644.4509-1-peng@oss.nxp.com/ 3. https://patchwork.ozlabs.org/project/uboot/cover/20220627034130.5892-1-peng@oss.nxp.com/ CI: https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq/-/pipelines/12806 THere is one error is arm32 build exceed 1 hour fail, which i think not because of this patchset. Alice Guo (3): misc: imx8ulp: move fuse.c from imx8ulp to sentinel misc: fuse: support to access fuse on i.MX93 misc: fuse: update the code for accessing fuse of i.MX93 Jian Li (1): imx: imx9: Add function to initialize timer Peng Fan (35): spl: imx8mm: enlarge SPL_MAX_SIZE arm: makefile: cleanup mach-imx usage imx: simplify dependency with SPL_BOOTROM_SUPPORT imx: move get_boot_device to common header imx: move get_boot_device to common file imx: add USB2_BOOT type imx: add basic i.MX9 support fsl_lpuart: add i.MX9 support gpio: pca953x: support pcal6524 imx: pinctrl: add pinctrl and pinfunc file for i.MX93 imx: imx9: Add CCM and clock API support mmc: fsl_esdhc_imx: Support i.MX9 spl: Use SPL_FIT_IMAGE_TINY for iMX9 imx: imx9: support romapi misc: s4mu: Support iMX93 with Sentinel MU misc: S400_API: New API for FW status and chip info misc: s400_api: introduce ahab_release_m33_trout imx: imx9: Get the chip revision through S400 API imx: imx9: Add MIX power init imx: imx9: Add M33 release prepare function imx: imx9: Support booting m33 from Acore arm: dts: Add i.MX93 SoC DTSi file imx: imx93_evk: Add basic board support imx: imx93_evk: Set ARM clock to 1.7Ghz net: fec_mxc: support i.MX93 net: dwc_eth_qos: fix build break when CLK not enabled net: dwc_eth_qos: public some functions net: dwc_eth_qos: move i.MX code out net: dwc_eth_qos: introduce eqos hook eqos_get_enetaddr board: freescale: imx93_evk: support ethernet tools: image: support i.MX93 arm: dts: imx8m: update binman ddr firmware node name ddr: imx8m: helper: load ddr firmware according to binman symbols arm: dts: imx8m: shrink ddr firmware size to actual file size imx: imx8mm-icore: migrate to use BINMAN Ye Li (14): imx: Change USB boot device type imx: spl: Allow iMX7/8/8M to overwrite spl_board_boot_device imx: imx9: disable watchdog misc: imx: S400_API: Move S400 MU and API to a common place misc: S400_API: Update release RDC API imx: imx9: Add TRDC driver for TRDC init imx: imx9: Add AHAB boot support misc: S400_API: Rename imx8ulp_s400_msg to sentinel_msg imx: imx9: Add gpio registers structure imx: imx9: Support multiple env storages at runtime imx: imx9: clock: Add DDR clock support ddr: imx: Add i.MX9 DDR controller driver ddr: imx9: enable Performance monitor counter net: eqos: add function to get phy node and address arch/arm/Kconfig | 16 + arch/arm/Makefile | 12 +- arch/arm/dts/Makefile |3 + arch/arm/dts/imx8mm-u-boot.dtsi | 16 +- arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi| 20 +- .../dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi |8 +- arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 20 +- arch/arm/dts/imx8mn-evk-u-boot.dtsi | 20 +- .../dts/imx8mn-var-som-symphony-u-boot.dtsi | 16 +- arch/arm/dts/imx8mn-venice-u-boot.dtsi| 16 +- arch/arm/dts/imx8mp-u-boot.dtsi | 20 +- arch/arm/dts/imx8mq-cm-u-boot.dtsi| 20 +- arch/arm/dts/imx8mq-u-boot.dtsi | 16 +- arch/arm/dts/imx93-11x11-evk-u-boot.dtsi | 157 ++ arch/arm/dts/imx93-11x11-evk.dts | 527 ++ arch/arm/dts/imx93-pinfunc.h | 625 +++ arch/arm/dts/imx93.dtsi | 688 arch/arm/include/asm/arch-imx/cpu.h |2 + arch/arm/include/asm/arch-imx8/sys_proto.h|1 - arch/arm/include/asm/arch-imx8m/ddr.h |6 +- arch/arm/include/asm/arch-imx8m/sys_proto.h |2 +- arch/arm/include/asm/arch-imx8ulp/sys_proto.h |5 - arch/arm/include/asm/arch-imx9/ccm_regs.h | 266 +++ arch/arm/include/asm/arch-imx9/clock.h| 244 +++ arch/arm/include/asm/arch-imx9/ddr.h | 126 ++ arch/arm/include/asm/arch-imx9/gpio.h | 20 + arch/arm/include/asm/arch-imx9/imx-regs.h | 234 +++ arch/arm/include/asm/arch-imx9/imx93_pins.h | 729 arch/arm/include/asm/arch-imx9/sys_proto.h| 14 + arch/arm/include/asm/arch-imx9/trdc.h | 19 + arch/arm/include/asm/arch-mx7/sys_proto.h |1 - arch/arm/include/asm/arc
[PATCH 02/53] arm: makefile: cleanup mach-imx usage
From: Peng Fan All the SoCs use mach-imx has CONFIG_MACH_IMX selected, so the macro could be the gate to build arch/arm/mach-imx to simplify the rules. Signed-off-by: Peng Fan --- arch/arm/Makefile | 12 ++-- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/arch/arm/Makefile b/arch/arm/Makefile index a37603035d8..1f4a1d57883 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -92,6 +92,8 @@ machine-$(CONFIG_ARCH_ZYNQ) += zynq machine-$(CONFIG_ARCH_ZYNQMP) += zynqmp machine-$(CONFIG_ARCH_ZYNQMP_R5) += zynqmp-r5 +machine-$(CONFIG_MACH_IMX) += imx + machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y)) PLATFORM_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs)) @@ -110,16 +112,6 @@ libs-y += arch/arm/cpu/$(CPU)/ libs-y += arch/arm/cpu/ libs-y += arch/arm/lib/ -ifeq ($(CONFIG_SPL_BUILD),y) -ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imx8ulp imxrt)) -libs-y += arch/arm/mach-imx/ -endif -else -ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx7ulp mx31 mx35 mxs imx8m imx8 imx8ulp imxrt vf610)) -libs-y += arch/arm/mach-imx/ -endif -endif - ifneq (,$(filter $(SOC), kirkwood)) libs-y += arch/arm/mach-mvebu/ endif -- 2.36.0
[PATCH 03/53] imx: Change USB boot device type
From: Ye Li The SPL SDP is configured as BOOT_DEVICE_BOARD, so when booting from USB, change its type to BOOT_DEVICE_BOARD, so we can use SDP. Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/spl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index 64ca2967721..e89e2277ef7 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -177,7 +177,7 @@ u32 spl_boot_device(void) case QSPI_BOOT: return BOOT_DEVICE_NOR; case USB_BOOT: - return BOOT_DEVICE_USB; + return BOOT_DEVICE_BOARD; default: return BOOT_DEVICE_NONE; } -- 2.36.0
[PATCH 01/53] spl: imx8mm: enlarge SPL_MAX_SIZE
From: Peng Fan
The CONFIG_SPL_MAX_SIZE could be 0x27000 for i.MX8MM when SPL_TEXT_BASE
set to 0x7E1000.
The DDR firmware max uses 96KB, there is a 4KB padding header before
SPL_TEXT_BASE, so the SPL MAX SIZE is `256KB - 96KB - 4KB`.
Signed-off-by: Peng Fan
Reviewed-by: Fabio Estevam
---
common/spl/Kconfig| 1 +
configs/imx8mm-cl-iot-gate-optee_defconfig| 1 -
configs/imx8mm-cl-iot-gate_defconfig | 1 -
configs/imx8mm-icore-mx8mm-ctouch2_defconfig | 1 -
configs/imx8mm-icore-mx8mm-edimm2.2_defconfig | 1 -
configs/imx8mm-mx8menlo_defconfig | 1 -
configs/imx8mm_beacon_defconfig | 1 -
configs/imx8mm_data_modul_edm_sbc_defconfig | 1 -
configs/imx8mm_evk_defconfig | 1 -
configs/imx8mm_venice_defconfig | 1 -
configs/kontron-sl-mx8mm_defconfig| 1 -
configs/phycore-imx8mm_defconfig | 1 -
configs/verdin-imx8mm_defconfig | 1 -
13 files changed, 1 insertion(+), 12 deletions(-)
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 908d7d17fda..0867d18f290 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -83,6 +83,7 @@ config SPL_MAX_SIZE
default 0x7000 if RCAR_GEN3
default 0x5fa0 if SUNXI_SRAM_ADDRESS = 0x0
default 0x1 if ASPEED_AST2600
+ default 0x27000 if IMX8MM && SPL_TEXT_BASE = 0x7E1000
default 0x0
help
Maximum size of the SPL image (text, data, rodata, and linker lists
diff --git a/configs/imx8mm-cl-iot-gate-optee_defconfig
b/configs/imx8mm-cl-iot-gate-optee_defconfig
index 2a209bcfe47..3476eae82f8 100644
--- a/configs/imx8mm-cl-iot-gate-optee_defconfig
+++ b/configs/imx8mm-cl-iot-gate-optee_defconfig
@@ -23,7 +23,6 @@ CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOARD_LATE_INIT=y
-CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x91
CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mm-cl-iot-gate_defconfig
b/configs/imx8mm-cl-iot-gate_defconfig
index 07084988139..7e7a59ffb3c 100644
--- a/configs/imx8mm-cl-iot-gate_defconfig
+++ b/configs/imx8mm-cl-iot-gate_defconfig
@@ -25,7 +25,6 @@ CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_BOARD_LATE_INIT=y
-CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x91
CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig
b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig
index 7040d782ef6..b9fb3c69cb7 100644
--- a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig
+++ b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig
@@ -23,7 +23,6 @@ CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="imx8mm-icore-mx8mm-ctouch2.dtb"
-CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x91
CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
index 0488ec223f0..1149bb68c04 100644
--- a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
+++ b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
@@ -23,7 +23,6 @@ CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="imx8mm-icore-mx8mm-edimm2.2.dtb"
-CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x91
CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mm-mx8menlo_defconfig
b/configs/imx8mm-mx8menlo_defconfig
index ec672f8764e..2a6f3b7c412 100644
--- a/configs/imx8mm-mx8menlo_defconfig
+++ b/configs/imx8mm-mx8menlo_defconfig
@@ -34,7 +34,6 @@ CONFIG_LOG=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_LATE_INIT=y
-CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x91
CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig
index 1a0672879e5..6d8fc9a27cf 100644
--- a/configs/imx8mm_beacon_defconfig
+++ b/configs/imx8mm_beacon_defconfig
@@ -25,7 +25,6 @@ CONFIG_OF_SYSTEM_SETUP=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run
loadbootscript; then run bootscript; else if run loadimage; then run mmcboot;
else run netboot; fi; fi; fi;"
CONFIG_DEFAULT_FDT_FILE="imx8mm-beacon-kit.dtb"
-CONFIG_SPL_MAX_SIZE=0x25000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x91
CONFIG_SPL_BSS_MAX_SIZE=0x2000
diff --git a/configs/imx8mm_data_modul_edm_sbc_defconfig
b/configs/imx8mm_data_modul_edm_sbc_defconfig
index 30c1eac4476..7e67b3ba640 100644
--- a/configs/imx8mm_data_modul_edm_sbc_defconfig
+++ b/configs/imx8mm_data_modul_edm_sbc_defconfig
@@ -41,7 +41,6 @@ CO
[PATCH 04/53] imx: spl: Allow iMX7/8/8M to overwrite spl_board_boot_device
From: Ye Li
Move the default mapping of spl_boot_device to weak function of
spl_board_boot_device. So that every board of iMX7/8/8M can overwrite
this function to implement specific mapping.
Reviewed-by: Peng Fan
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/spl.c | 80 -
1 file changed, 38 insertions(+), 42 deletions(-)
diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
index e89e2277ef7..e5ad993b8d9 100644
--- a/arch/arm/mach-imx/spl.c
+++ b/arch/arm/mach-imx/spl.c
@@ -25,7 +25,43 @@ DECLARE_GLOBAL_DATA_PTR;
__weak int spl_board_boot_device(enum boot_device boot_dev_spl)
{
- return 0;
+ switch (boot_dev_spl) {
+#if defined(CONFIG_MX7)
+ case SD1_BOOT:
+ case MMC1_BOOT:
+ case SD2_BOOT:
+ case MMC2_BOOT:
+ case SD3_BOOT:
+ case MMC3_BOOT:
+ return BOOT_DEVICE_MMC1;
+#elif defined(CONFIG_IMX8)
+ case MMC1_BOOT:
+ return BOOT_DEVICE_MMC1;
+ case SD2_BOOT:
+ return BOOT_DEVICE_MMC2_2;
+ case SD3_BOOT:
+ return BOOT_DEVICE_MMC1;
+ case FLEXSPI_BOOT:
+ return BOOT_DEVICE_SPI;
+#elif defined(CONFIG_IMX8M)
+ case SD1_BOOT:
+ case MMC1_BOOT:
+ return BOOT_DEVICE_MMC1;
+ case SD2_BOOT:
+ case MMC2_BOOT:
+ return BOOT_DEVICE_MMC2;
+#endif
+ case NAND_BOOT:
+ return BOOT_DEVICE_NAND;
+ case SPI_NOR_BOOT:
+ return BOOT_DEVICE_SPI;
+ case QSPI_BOOT:
+ return BOOT_DEVICE_NOR;
+ case USB_BOOT:
+ return BOOT_DEVICE_BOARD;
+ default:
+ return BOOT_DEVICE_NONE;
+ }
}
#if defined(CONFIG_MX6)
@@ -140,47 +176,7 @@ u32 spl_boot_device(void)
enum boot_device boot_device_spl = get_boot_device();
- if (IS_ENABLED(CONFIG_IMX8MM) || IS_ENABLED(CONFIG_IMX8MN) ||
- IS_ENABLED(CONFIG_IMX8MP))
- return spl_board_boot_device(boot_device_spl);
-
- switch (boot_device_spl) {
-#if defined(CONFIG_MX7)
- case SD1_BOOT:
- case MMC1_BOOT:
- case SD2_BOOT:
- case MMC2_BOOT:
- case SD3_BOOT:
- case MMC3_BOOT:
- return BOOT_DEVICE_MMC1;
-#elif defined(CONFIG_IMX8)
- case MMC1_BOOT:
- return BOOT_DEVICE_MMC1;
- case SD2_BOOT:
- return BOOT_DEVICE_MMC2_2;
- case SD3_BOOT:
- return BOOT_DEVICE_MMC1;
- case FLEXSPI_BOOT:
- return BOOT_DEVICE_SPI;
-#elif defined(CONFIG_IMX8M)
- case SD1_BOOT:
- case MMC1_BOOT:
- return BOOT_DEVICE_MMC1;
- case SD2_BOOT:
- case MMC2_BOOT:
- return BOOT_DEVICE_MMC2;
-#endif
- case NAND_BOOT:
- return BOOT_DEVICE_NAND;
- case SPI_NOR_BOOT:
- return BOOT_DEVICE_SPI;
- case QSPI_BOOT:
- return BOOT_DEVICE_NOR;
- case USB_BOOT:
- return BOOT_DEVICE_BOARD;
- default:
- return BOOT_DEVICE_NONE;
- }
+ return spl_board_boot_device(boot_device_spl);
}
#endif /* CONFIG_MX7 || CONFIG_IMX8M || CONFIG_IMX8 */
--
2.36.0
[PATCH 05/53] imx: simplify dependency with SPL_BOOTROM_SUPPORT
From: Peng Fan
For SoCs support ROM API, CONFIG_SPL_BOOTROM_SUPPORT is needed,
so use this macro to guard the code to avoid extend the list.
And drop the guard with structure definition, there is no need.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/mach-imx/sys_proto.h | 2 --
arch/arm/mach-imx/Kconfig | 3 ++-
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h
b/arch/arm/include/asm/mach-imx/sys_proto.h
index fdbbfb169cb..fc5e5c66aad 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -146,7 +146,6 @@ struct rproc_att {
u32 size; /* size of reg range */
};
-#if defined(CONFIG_IMX8M) || defined(CONFIG_IMX8ULP)
struct rom_api {
u16 ver;
u16 tag;
@@ -178,7 +177,6 @@ enum boot_dev_type_e {
#define ROM_API_OKAY 0xF0
extern struct rom_api *g_rom_api;
-#endif
/* For i.MX ULP */
#define BT0CFG_LPBOOT_MASK 0x1
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index ad0fb365023..5e9c4d9b355 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -166,7 +166,8 @@ config DDRMC_VF610_CALIBRATION
config SPL_IMX_ROMAPI_LOADADDR
hex "Default load address to load image through ROM API"
- depends on IMX8MN || IMX8MP || IMX8ULP
+ depends on SPL_BOOTROM_SUPPORT
+ default 0
config IMX_DCD_ADDR
hex "DCD Blocks location on the image"
--
2.36.0
[PATCH 07/53] imx: move get_boot_device to common file
From: Peng Fan
i.MX8MN/P/ULP supports ROM API, they have almost same get_boot_device
implementation, so move to a common file. And when support i.MX9,
no need to include the other function copy.
Since sys_proto.h is included in imx_romapi.c, there will be build
warning for i.MX8M because wdog_regs not defined, so include imx-regs.h
in i.MX8M sys_proro.h
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8m/sys_proto.h | 1 +
arch/arm/mach-imx/Makefile | 1 +
arch/arm/mach-imx/imx8m/soc.c | 47
arch/arm/mach-imx/imx8ulp/soc.c | 44 ---
arch/arm/mach-imx/imx_romapi.c | 60 +
5 files changed, 62 insertions(+), 91 deletions(-)
create mode 100644 arch/arm/mach-imx/imx_romapi.c
diff --git a/arch/arm/include/asm/arch-imx8m/sys_proto.h
b/arch/arm/include/asm/arch-imx8m/sys_proto.h
index f8854e77128..55b46afaf78 100644
--- a/arch/arm/include/asm/arch-imx8m/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8m/sys_proto.h
@@ -7,6 +7,7 @@
#define __ARCH_NMX8M_SYS_PROTO_H
#include
+#include
void set_wdog_reset(struct wdog_regs *wdog);
void enable_tzc380(void);
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index aa0b6447f14..c5be63dfe4f 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -242,4 +242,5 @@ obj-$(CONFIG_IMX8M) += imx8m/
obj-$(CONFIG_ARCH_IMX8) += imx8/
obj-$(CONFIG_ARCH_IMXRT) += imxrt/
+obj-$(CONFIG_IMX8MN)$(CONFIG_IMX8MP)$(CONFIG_IMX8ULP) += imx_romapi.o
obj-$(CONFIG_SPL_BOOTROM_SUPPORT) += spl_imx_romapi.o
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index e4e56079cf3..d115b25a5b6 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -599,53 +599,6 @@ int arch_cpu_init(void)
#if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
struct rom_api *g_rom_api = (struct rom_api *)0x980;
-
-enum boot_device get_boot_device(void)
-{
- volatile gd_t *pgd = gd;
- int ret;
- u32 boot;
- u16 boot_type;
- u8 boot_instance;
- enum boot_device boot_dev = SD1_BOOT;
-
- ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
- ((uintptr_t)&boot) ^ QUERY_BT_DEV);
- set_gd(pgd);
-
- if (ret != ROM_API_OKAY) {
- puts("ROMAPI: failure at query_boot_info\n");
- return -1;
- }
-
- boot_type = boot >> 16;
- boot_instance = (boot >> 8) & 0xff;
-
- switch (boot_type) {
- case BT_DEV_TYPE_SD:
- boot_dev = boot_instance + SD1_BOOT;
- break;
- case BT_DEV_TYPE_MMC:
- boot_dev = boot_instance + MMC1_BOOT;
- break;
- case BT_DEV_TYPE_NAND:
- boot_dev = NAND_BOOT;
- break;
- case BT_DEV_TYPE_FLEXSPINOR:
- boot_dev = QSPI_BOOT;
- break;
- case BT_DEV_TYPE_SPI_NOR:
- boot_dev = SPI_NOR_BOOT;
- break;
- case BT_DEV_TYPE_USB:
- boot_dev = USB_BOOT;
- break;
- default:
- break;
- }
-
- return boot_dev;
-}
#endif
#if defined(CONFIG_IMX8M)
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index 35020c9714d..529fda4594e 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -34,50 +34,6 @@ DECLARE_GLOBAL_DATA_PTR;
struct rom_api *g_rom_api = (struct rom_api *)0x1980;
-enum boot_device get_boot_device(void)
-{
- volatile gd_t *pgd = gd;
- int ret;
- u32 boot;
- u16 boot_type;
- u8 boot_instance;
- enum boot_device boot_dev = SD1_BOOT;
-
- ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
- ((uintptr_t)&boot) ^ QUERY_BT_DEV);
- set_gd(pgd);
-
- if (ret != ROM_API_OKAY) {
- puts("ROMAPI: failure at query_boot_info\n");
- return -1;
- }
-
- boot_type = boot >> 16;
- boot_instance = (boot >> 8) & 0xff;
-
- switch (boot_type) {
- case BT_DEV_TYPE_SD:
- boot_dev = boot_instance + SD1_BOOT;
- break;
- case BT_DEV_TYPE_MMC:
- boot_dev = boot_instance + MMC1_BOOT;
- break;
- case BT_DEV_TYPE_NAND:
- boot_dev = NAND_BOOT;
- break;
- case BT_DEV_TYPE_FLEXSPINOR:
- boot_dev = QSPI_BOOT;
- break;
- case BT_DEV_TYPE_USB:
- boot_dev = USB_BOOT;
- break;
- default:
- break;
- }
-
- return boot_dev;
-}
-
bool is_usb_boot(void)
{
return get_boot_device() == USB_BOOT;
diff --git a/arch/arm/mach-imx/imx_romapi.c b/arch/arm/mach-imx/imx_romapi.c
new file mode 100644
index 000..3b2cc6935dc
--- /dev/null
+++ b/arch/arm/mach-
[PATCH 06/53] imx: move get_boot_device to common header
From: Peng Fan
Most i.MX implements get_boot_device, move it to common header to
simplify code
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8/sys_proto.h| 1 -
arch/arm/include/asm/arch-imx8m/sys_proto.h | 1 -
arch/arm/include/asm/arch-imx8ulp/sys_proto.h | 1 -
arch/arm/include/asm/arch-mx7/sys_proto.h | 1 -
arch/arm/include/asm/arch-mx7ulp/sys_proto.h | 1 -
arch/arm/include/asm/mach-imx/sys_proto.h | 2 ++
6 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx8/sys_proto.h
b/arch/arm/include/asm/arch-imx8/sys_proto.h
index 6f1fc8f999d..d38f606e07e 100644
--- a/arch/arm/include/asm/arch-imx8/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8/sys_proto.h
@@ -23,7 +23,6 @@ struct pass_over_info_t {
extern unsigned long boot_pointer[];
void build_info(void);
-enum boot_device get_boot_device(void);
int print_bootinfo(void);
int sc_pm_setup_uart(sc_rsrc_t uart_rsrc, sc_pm_clock_rate_t clk_rate);
int imx8_power_domain_lookup_name(const char *name,
diff --git a/arch/arm/include/asm/arch-imx8m/sys_proto.h
b/arch/arm/include/asm/arch-imx8m/sys_proto.h
index d328542ece2..f8854e77128 100644
--- a/arch/arm/include/asm/arch-imx8m/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8m/sys_proto.h
@@ -12,6 +12,5 @@ void set_wdog_reset(struct wdog_regs *wdog);
void enable_tzc380(void);
void restore_boot_params(void);
extern unsigned long rom_pointer[];
-enum boot_device get_boot_device(void);
bool is_usb_boot(void);
#endif
diff --git a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
index 5f030eaa0ad..05859dfc2aa 100644
--- a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
@@ -15,7 +15,6 @@ ulong spl_romapi_get_uboot_base(u32 image_offset, u32
rom_bt_dev);
enum bt_mode get_boot_mode(void);
int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm);
int xrdc_config_pdac_openacc(u32 bridge, u32 index);
-enum boot_device get_boot_device(void);
void set_lpav_qos(void);
void load_lposc_fuse(void);
bool m33_image_booted(void);
diff --git a/arch/arm/include/asm/arch-mx7/sys_proto.h
b/arch/arm/include/asm/arch-mx7/sys_proto.h
index e46a02198d6..634736cc09c 100644
--- a/arch/arm/include/asm/arch-mx7/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx7/sys_proto.h
@@ -8,6 +8,5 @@
#include
void set_wdog_reset(struct wdog_regs *wdog);
-enum boot_device get_boot_device(void);
#endif /* __SYS_PROTO_IMX7_ */
diff --git a/arch/arm/include/asm/arch-mx7ulp/sys_proto.h
b/arch/arm/include/asm/arch-mx7ulp/sys_proto.h
index 0daa922fad9..7adf4720fec 100644
--- a/arch/arm/include/asm/arch-mx7ulp/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx7ulp/sys_proto.h
@@ -8,5 +8,4 @@
#include
-enum boot_device get_boot_device(void);
#endif
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h
b/arch/arm/include/asm/mach-imx/sys_proto.h
index fc5e5c66aad..cd69384d8ef 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -243,4 +243,6 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
void enable_ca7_smp(void);
#endif
+enum boot_device get_boot_device(void);
+
#endif
--
2.36.0
[PATCH 10/53] fsl_lpuart: add i.MX9 support
From: Peng Fan
i.MX9 shares same register layout as i.MX7ULP, so
add the i.MX9 define here.
Signed-off-by: Peng Fan
---
include/fsl_lpuart.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/fsl_lpuart.h b/include/fsl_lpuart.h
index 18e5cc15d61..93c996b764b 100644
--- a/include/fsl_lpuart.h
+++ b/include/fsl_lpuart.h
@@ -5,7 +5,7 @@
*/
#if defined(CONFIG_ARCH_MX7ULP) || defined(CONFIG_ARCH_IMX8) || \
- defined(CONFIG_ARCH_IMXRT) || defined(CONFIG_ARCH_IMX8ULP)
+ defined(CONFIG_ARCH_IMXRT) || defined(CONFIG_ARCH_IMX8ULP) ||
defined(CONFIG_ARCH_IMX9)
struct lpuart_fsl_reg32 {
u32 verid;
u32 param;
--
2.36.0
[PATCH 11/53] gpio: pca953x: support pcal6524
From: Peng Fan
Support pcal6524 IO expander driver
Signed-off-by: Peng Fan
---
drivers/gpio/pca953x_gpio.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpio/pca953x_gpio.c b/drivers/gpio/pca953x_gpio.c
index e98e1e56dbc..4654f9e0989 100644
--- a/drivers/gpio/pca953x_gpio.c
+++ b/drivers/gpio/pca953x_gpio.c
@@ -43,6 +43,8 @@
#define PCA_GPIO_MASK 0x00FF
#define PCA_INT 0x0100
+#define PCA_PCAL BIT(9)
+#define PCA_LATCH_INT (PCA_PCAL | PCA_INT)
#define PCA953X_TYPE0x1000
#define PCA957X_TYPE0x2000
#define PCA_TYPE_MASK 0xF000
@@ -393,6 +395,8 @@ static const struct udevice_id pca953x_ids[] = {
{ .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
{ .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
+ { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), },
+
{ .compatible = "maxim,max7310", .data = OF_953X(8, 0), },
{ .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },
{ .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },
--
2.36.0
[PATCH 15/53] spl: Use SPL_FIT_IMAGE_TINY for iMX9
From: Peng Fan Select SPL_FIT_IMAGE_TINY for i.MX9 Signed-off-by: Peng Fan --- common/spl/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 0867d18f290..8f7715f403c 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -563,7 +563,7 @@ config SPL_FIT_IMAGE_TINY bool "Remove functionality from SPL FIT loading to reduce size" depends on SPL_FIT default y if MACH_SUN50I || MACH_SUN50I_H5 || SUN50I_GEN_H6 - default y if ARCH_IMX8M + default y if ARCH_IMX8M || ARCH_IMX9 help Enable this to reduce the size of the FIT image loading code in SPL, if space for the SPL binary is very tight. -- 2.36.0
[PATCH 09/53] imx: add basic i.MX9 support
From: Peng Fan
Add i.MX9 Kconfig and basic files for the new SoC
Signed-off-by: Peng Fan
---
arch/arm/Kconfig| 11 +
arch/arm/include/asm/arch-imx/cpu.h | 2 +
arch/arm/include/asm/arch-imx9/clock.h | 0
arch/arm/include/asm/arch-imx9/gpio.h | 0
arch/arm/include/asm/arch-imx9/imx-regs.h | 13 +
arch/arm/include/asm/arch-imx9/imx93_pins.h | 729
arch/arm/include/asm/arch-imx9/sys_proto.h | 11 +
arch/arm/include/asm/mach-imx/iomux-v3.h| 11 +-
arch/arm/include/asm/mach-imx/sys_proto.h | 3 +
arch/arm/mach-imx/Makefile | 11 +-
arch/arm/mach-imx/imx9/Kconfig | 17 +
arch/arm/mach-imx/imx9/Makefile | 6 +
arch/arm/mach-imx/imx9/clock.c | 27 +
arch/arm/mach-imx/imx9/lowlevel_init.S | 26 +
arch/arm/mach-imx/imx9/soc.c| 127
arch/arm/mach-imx/spl.c | 2 +-
16 files changed, 991 insertions(+), 5 deletions(-)
create mode 100644 arch/arm/include/asm/arch-imx9/clock.h
create mode 100644 arch/arm/include/asm/arch-imx9/gpio.h
create mode 100644 arch/arm/include/asm/arch-imx9/imx-regs.h
create mode 100644 arch/arm/include/asm/arch-imx9/imx93_pins.h
create mode 100644 arch/arm/include/asm/arch-imx9/sys_proto.h
create mode 100644 arch/arm/mach-imx/imx9/Kconfig
create mode 100644 arch/arm/mach-imx/imx9/Makefile
create mode 100644 arch/arm/mach-imx/imx9/clock.c
create mode 100644 arch/arm/mach-imx/imx9/lowlevel_init.S
create mode 100644 arch/arm/mach-imx/imx9/soc.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index d4fc83318a6..2802b9b3fa5 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -908,6 +908,15 @@ config ARCH_IMX8ULP
imply CMD_DM
imply DM_EVENT
+config ARCH_IMX9
+ bool "NXP i.MX9 platform"
+ select ARM64
+ select DM
+ select MACH_IMX
+ select SUPPORT_SPL
+ imply CMD_DM
+ imply DM_EVENT
+
config ARCH_IMXRT
bool "NXP i.MXRT platform"
select CPU_V7M
@@ -2228,6 +2237,8 @@ source "arch/arm/mach-imx/imx8m/Kconfig"
source "arch/arm/mach-imx/imx8ulp/Kconfig"
+source "arch/arm/mach-imx/imx9/Kconfig"
+
source "arch/arm/mach-imx/imxrt/Kconfig"
source "arch/arm/mach-imx/mxs/Kconfig"
diff --git a/arch/arm/include/asm/arch-imx/cpu.h
b/arch/arm/include/asm/arch-imx/cpu.h
index 4f63803765e..d54e6e63352 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -59,6 +59,7 @@
#define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */
#define MXC_CPU_VF610 0xF6 /* dummy ID */
+#define MXC_CPU_IMX93 0xC1 /* dummy ID */
#define MXC_SOC_MX60x60
#define MXC_SOC_MX70x70
@@ -66,6 +67,7 @@
#define MXC_SOC_IMX8 0x90 /* dummy */
#define MXC_SOC_IMXRT 0xB0 /* dummy */
#define MXC_SOC_MX7ULP 0xE0 /* dummy */
+#define MXC_SOC_IMX9 0xC0 /* dummy */
#define CHIP_REV_1_00x10
#define CHIP_REV_1_10x11
diff --git a/arch/arm/include/asm/arch-imx9/clock.h
b/arch/arm/include/asm/arch-imx9/clock.h
new file mode 100644
index 000..e69de29bb2d
diff --git a/arch/arm/include/asm/arch-imx9/gpio.h
b/arch/arm/include/asm/arch-imx9/gpio.h
new file mode 100644
index 000..e69de29bb2d
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h
b/arch/arm/include/asm/arch-imx9/imx-regs.h
new file mode 100644
index 000..2adbdadf03c
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX9_REGS_H__
+#define __ASM_ARCH_IMX9_REGS_H__
+
+#define ARCH_MXC
+
+#define IOMUXC_BASE_ADDR 0x443CUL
+
+#endif
diff --git a/arch/arm/include/asm/arch-imx9/imx93_pins.h
b/arch/arm/include/asm/arch-imx9/imx93_pins.h
new file mode 100644
index 000..f13aef5619c
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx9/imx93_pins.h
@@ -0,0 +1,729 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX93_PINS_H__
+#define __ASM_ARCH_IMX93_PINS_H__
+
+#include
+
+enum {
+ MX93_PAD_DAP_TDI__JTAG_MUX_TDI = IOMUX_PAD(0x1B0,
0x, 0, 0x3D8, 0, 0),
+ MX93_PAD_DAP_TDI__MQS2_LEFT = IOMUX_PAD(0x1B0,
0x, 1, 0x, 0, 0),
+ MX93_PAD_DAP_TDI__CAN2_TX = IOMUX_PAD(0x1B0,
0x, 3, 0x, 0, 0),
+ MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 = IOMUX_PAD(0x1B0,
0x, 4, 0x, 0, 0),
+ MX93_PAD_DAP_TDI__GPIO3_IO28= IOMUX_PAD(0x1B0,
0x, 5, 0x, 0, 0),
+ MX93_PAD_DAP_TDI__LPUART5_RX= IOMUX_PAD(0x1B0,
0x, 6, 0x430, 0, 0),
+
+ MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS= IOMUX_PAD(0x1B4,
0x0004, 0, 0x3DC, 0, 0),
+ MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31= IOMUX_PAD(
[PATCH 16/53] imx: imx9: Add function to initialize timer
From: Jian Li
Add timer_init to update ARM arch timer with correct frequency
from system counter and enable system counter.
Signed-off-by: Jian Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/imx-regs.h | 1 +
arch/arm/mach-imx/imx9/soc.c | 19 +++
2 files changed, 20 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h
b/arch/arm/include/asm/arch-imx9/imx-regs.h
index 50ec902987d..32c76ce9c3b 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -11,6 +11,7 @@
#define IOMUXC_BASE_ADDR 0x443CUL
#define CCM_BASE_ADDR 0x4445UL
#define CCM_CCGR_BASE_ADDR 0x44458000UL
+#define SYSCNT_CTRL_BASE_ADDR 0x4429
#define ANATOP_BASE_ADDR0x4448UL
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index d4a97729c67..4b8f1ca30d5 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -128,3 +128,22 @@ int arch_cpu_init(void)
return 0;
}
+
+int timer_init(void)
+{
+#ifdef CONFIG_SPL_BUILD
+ struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
+ unsigned long freq = readl(&sctr->cntfid0);
+
+ /* Update with accurate clock frequency */
+ asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
+
+ clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
+ SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
+#endif
+
+ gd->arch.tbl = 0;
+ gd->arch.tbu = 0;
+
+ return 0;
+}
--
2.36.0
[PATCH 12/53] imx: pinctrl: add pinctrl and pinfunc file for i.MX93
From: Peng Fan Add the pinctrl driver and pinfunc header file to support iMX93 Signed-off-by: Peng Fan --- arch/arm/dts/imx93-pinfunc.h| 625 drivers/pinctrl/nxp/Kconfig | 13 + drivers/pinctrl/nxp/Makefile| 1 + drivers/pinctrl/nxp/pinctrl-imx93.c | 37 ++ 4 files changed, 676 insertions(+) create mode 100644 arch/arm/dts/imx93-pinfunc.h create mode 100644 drivers/pinctrl/nxp/pinctrl-imx93.c diff --git a/arch/arm/dts/imx93-pinfunc.h b/arch/arm/dts/imx93-pinfunc.h new file mode 100644 index 000..7f0136c70b6 --- /dev/null +++ b/arch/arm/dts/imx93-pinfunc.h @@ -0,0 +1,625 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 NXP + */ + +#ifndef __DTS_IMX93_PINFUNC_H +#define __DTS_IMX93_PINFUNC_H + +/* + * The pin function ID is a tuple of + * + */ +#define MX93_PAD_DAP_TDI__JTAG_MUX_TDI0x 0x01B0 0x03E0 0x0 0x0 +#define MX93_PAD_DAP_TDI__MQS2_LEFT 0x 0x01B0 0x 0x1 0x0 +#define MX93_PAD_DAP_TDI__CAN2_TX 0x 0x01B0 0x 0x3 0x0 +#define MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO300x 0x01B0 0x 0x4 0x0 +#define MX93_PAD_DAP_TDI__GPIO3_IO28 0x 0x01B0 0x03CC 0x5 0x0 +#define MX93_PAD_DAP_TDI__LPUART5_RX 0x 0x01B0 0x0438 0x6 0x0 +#define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01B4 0x03E4 0x0 0x0 +#define MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01B4 0x 0x4 0x0 +#define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO290x0004 0x01B4 0x03D0 0x5 0x0 +#define MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01B4 0x 0x6 0x0 +#define MX93_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x0008 0x01B8 0x03DC 0x0 0x0 +#define MX93_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30 0x0008 0x01B8 0x 0x4 0x0 +#define MX93_PAD_DAP_TCLK_SWCLK__GPIO3_IO30 0x0008 0x01B8 0x 0x5 0x0 +#define MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B0x0008 0x01B8 0x0434 0x6 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x000C 0x01BC 0x 0x0 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT 0x000C 0x01BC 0x 0x1 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__CAN2_RX0x000C 0x01BC 0x0364 0x3 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31 0x000C 0x01BC 0x 0x4 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__GPIO3_IO31 0x000C 0x01BC 0x 0x5 0x0 +#define MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x000C 0x01BC 0x043C 0x6 0x0 +#define MX93_PAD_GPIO_IO00__GPIO2_IO000x0010 0x01C0 0x 0x0 0x0 +#define MX93_PAD_GPIO_IO00__LPI2C3_SDA0x0010 0x01C0 0x03EC 0x1 0x0 +#define MX93_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK 0x0010 0x01C0 0x 0x2 0x0 +#define MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x0010 0x01C0 0x 0x3 0x0 +#define MX93_PAD_GPIO_IO00__LPSPI6_PCS0 0x0010 0x01C0 0x 0x4 0x0 +#define MX93_PAD_GPIO_IO00__LPUART5_TX0x0010 0x01C0 0x043C 0x5 0x1 +#define MX93_PAD_GPIO_IO00__LPI2C5_SDA0x0010 0x01C0 0x03F4 0x6 0x0 +#define MX93_PAD_GPIO_IO00__FLEXIO1_FLEXIO00 0x0010 0x01C0 0x036C 0x7 0x0 +#define MX93_PAD_GPIO_IO01__GPIO2_IO010x0014 0x01C4 0x 0x0 0x0 +#define MX93_PAD_GPIO_IO01__LPI2C3_SCL0x0014 0x01C4 0x03E8 0x1 0x0 +#define MX93_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA00 0x0014 0x01C4 0x 0x2 0x0 +#define MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x0014 0x01C4 0x 0x3 0x0 +#define MX93_PAD_GPIO_IO01__LPSPI6_SIN0x0014 0x01C4 0x 0x4 0x0 +#define MX93_PAD_GPIO_IO01__LPUART5_RX0x0014 0x01C4 0x0438 0x5 0x1 +#define MX93_PAD_GPIO_IO01__LPI2C5_SCL0x0014 0x01C4 0x03F0 0x6 0x0 +#define MX93_PAD_GPIO_IO01__FLEXIO1_FLEXIO01 0x0014 0x01C4 0x0370 0x7 0x0 +#define MX93_PAD_GPIO_IO02__GPIO2_IO020x0018 0x01C8 0x 0x0 0x0 +#define MX93_PAD_GPIO_IO02__LPI2C4_SDA0x0018 0x01C8 0x 0x1 0x0 +#define MX93_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC0x0018 0x01C8 0x 0x2 0x0 +#define MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x0018 0x01C8 0x 0x3 0x0 +#define MX93_PAD_GPIO_IO02__LPSPI6_SOUT 0x0018 0x01C8 0x 0x4 0x0 +#define MX93_PAD_GPIO_IO02__LPUART5_CTS_B 0x0018 0x01C8 0x0434 0x5 0x1 +#define MX93_PAD_GPIO_IO02__LPI2C6_SDA0x0018 0x01C8
[PATCH 17/53] imx: imx9: disable watchdog
From: Ye Li
Disable all 3 wdogs on AIPS2 and unmask SRC reset trigger for WDOG3-5
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/imx-regs.h | 4 ++
arch/arm/mach-imx/imx9/soc.c | 45 ++-
2 files changed, 48 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h
b/arch/arm/include/asm/arch-imx9/imx-regs.h
index 32c76ce9c3b..e4babed40fc 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -15,4 +15,8 @@
#define ANATOP_BASE_ADDR0x4448UL
+#define WDG3_BASE_ADDR 0x4249UL
+#define WDG4_BASE_ADDR 0x424aUL
+#define WDG5_BASE_ADDR 0x424bUL
+
#endif
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 4b8f1ca30d5..8b620832b5d 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -34,6 +34,45 @@ u32 get_cpu_rev(void)
return (MXC_CPU_IMX93 << 12) | CHIP_REV_1_0;
}
+#define UNLOCK_WORD 0xD928C520 /* unlock word */
+#define REFRESH_WORD 0xB480A602 /* refresh word */
+
+static void disable_wdog(void __iomem *wdog_base)
+{
+ u32 val_cs = readl(wdog_base + 0x00);
+
+ if (!(val_cs & 0x80))
+ return;
+
+ /* default is 32bits cmd */
+ writel(REFRESH_WORD, (wdog_base + 0x04)); /* Refresh the CNT */
+
+ if (!(val_cs & 0x800)) {
+ writel(UNLOCK_WORD, (wdog_base + 0x04));
+ while (!(readl(wdog_base + 0x00) & 0x800))
+ ;
+ }
+ writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */
+ writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */
+ writel(0x2120, (wdog_base + 0x00)); /* Disable it and set update */
+
+ while (!(readl(wdog_base + 0x00) & 0x400))
+ ;
+}
+
+void init_wdog(void)
+{
+ u32 src_val;
+
+ disable_wdog((void __iomem *)WDG3_BASE_ADDR);
+ disable_wdog((void __iomem *)WDG4_BASE_ADDR);
+ disable_wdog((void __iomem *)WDG5_BASE_ADDR);
+
+ src_val = readl(0x54460018); /* reset mask */
+ src_val &= ~0x1c;
+ writel(src_val, 0x54460018);
+}
+
static struct mm_region imx93_mem_map[] = {
{
/* ROM */
@@ -123,8 +162,12 @@ int ft_system_setup(void *blob, struct bd_info *bd)
int arch_cpu_init(void)
{
- if (IS_ENABLED(CONFIG_SPL_BUILD))
+ if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+ /* Disable wdog */
+ init_wdog();
+
clock_init();
+ }
return 0;
}
--
2.36.0
[PATCH 20/53] misc: s4mu: Support iMX93 with Sentinel MU
From: Peng Fan
Support iMX93 communicate with Sentinel
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/imx-regs.h | 30 +++
drivers/misc/sentinel/s4mu.c | 1 +
2 files changed, 31 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h
b/arch/arm/include/asm/arch-imx9/imx-regs.h
index e4babed40fc..7b84b970b75 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -19,4 +19,34 @@
#define WDG4_BASE_ADDR 0x424aUL
#define WDG5_BASE_ADDR 0x424bUL
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include
+#include
+
+struct mu_type {
+ u32 ver;
+ u32 par;
+ u32 cr;
+ u32 sr;
+ u32 reserved0[60];
+ u32 fcr;
+ u32 fsr;
+ u32 reserved1[2];
+ u32 gier;
+ u32 gcr;
+ u32 gsr;
+ u32 reserved2;
+ u32 tcr;
+ u32 tsr;
+ u32 rcr;
+ u32 rsr;
+ u32 reserved3[52];
+ u32 tr[16];
+ u32 reserved4[16];
+ u32 rr[16];
+ u32 reserved5[14];
+ u32 mu_attr;
+};
+#endif
+
#endif
diff --git a/drivers/misc/sentinel/s4mu.c b/drivers/misc/sentinel/s4mu.c
index 121a81060a6..18aea27105e 100644
--- a/drivers/misc/sentinel/s4mu.c
+++ b/drivers/misc/sentinel/s4mu.c
@@ -219,6 +219,7 @@ static struct misc_ops imx8ulp_mu_ops = {
static const struct udevice_id imx8ulp_mu_ids[] = {
{ .compatible = "fsl,imx8ulp-mu" },
+ { .compatible = "fsl,imx93-mu-s4" },
{ }
};
--
2.36.0
[PATCH 14/53] mmc: fsl_esdhc_imx: Support i.MX9
From: Peng Fan Support i.MX9 for fsl_esdhc_imx driver Signed-off-by: Peng Fan --- drivers/mmc/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 6ff00a7cbd3..6276593b3e7 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -853,7 +853,7 @@ config FSL_ESDHC_IMX config FSL_USDHC bool "Freescale/NXP i.MX uSDHC controller support" - depends on MX6 || MX7 ||ARCH_MX7ULP || IMX8 || IMX8M || IMX8ULP || IMXRT + depends on MX6 || MX7 ||ARCH_MX7ULP || IMX8 || IMX8M || IMX8ULP || IMX9 || IMXRT select FSL_ESDHC_IMX help This enables the Ultra Secured Digital Host Controller enhancements -- 2.36.0
[PATCH 19/53] misc: imx: S400_API: Move S400 MU and API to a common place
From: Ye Li
Since iMX9 uses S401 which shares the API with iMX8ULP. So move S400
MU driver and API to a common place and selected by CONFIG_IMX_SENTINEL
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/Kconfig | 4 +
arch/arm/include/asm/global_data.h| 2 +-
.../asm/{arch-imx8ulp => mach-imx}/mu_hal.h | 4 +-
.../asm/{arch-imx8ulp => mach-imx}/s400_api.h | 0
arch/arm/mach-imx/imx8ulp/ahab.c | 345 ++
arch/arm/mach-imx/imx8ulp/rdc.c | 4 +-
arch/arm/mach-imx/imx8ulp/soc.c | 4 +-
board/freescale/imx8ulp_evk/spl.c | 2 +-
drivers/misc/Kconfig | 7 +
drivers/misc/Makefile | 2 +
drivers/misc/imx8ulp/Makefile | 1 -
drivers/misc/imx8ulp/fuse.c | 2 +-
drivers/misc/sentinel/Makefile| 3 +
drivers/misc/{imx8ulp => sentinel}/s400_api.c | 6 +-
.../{imx8ulp/imx8ulp_mu.c => sentinel/s4mu.c} | 4 +-
15 files changed, 375 insertions(+), 15 deletions(-)
rename arch/arm/include/asm/{arch-imx8ulp => mach-imx}/mu_hal.h (79%)
rename arch/arm/include/asm/{arch-imx8ulp => mach-imx}/s400_api.h (100%)
create mode 100644 arch/arm/mach-imx/imx8ulp/ahab.c
create mode 100644 drivers/misc/sentinel/Makefile
rename drivers/misc/{imx8ulp => sentinel}/s400_api.c (98%)
rename drivers/misc/{imx8ulp/imx8ulp_mu.c => sentinel/s4mu.c} (98%)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2802b9b3fa5..d290194f900 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -905,6 +905,8 @@ config ARCH_IMX8ULP
select OF_CONTROL
select SUPPORT_SPL
select GPIO_EXTRA_HEADER
+ select MISC
+ select IMX_SENTINEL
imply CMD_DM
imply DM_EVENT
@@ -914,6 +916,8 @@ config ARCH_IMX9
select DM
select MACH_IMX
select SUPPORT_SPL
+ select MISC
+ select IMX_SENTINEL
imply CMD_DM
imply DM_EVENT
diff --git a/arch/arm/include/asm/global_data.h
b/arch/arm/include/asm/global_data.h
index 085e12b5d4d..09f352269e5 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -90,7 +90,7 @@ struct arch_global_data {
struct udevice *scu_dev;
#endif
-#ifdef CONFIG_ARCH_IMX8ULP
+#ifdef CONFIG_IMX_SENTINEL
struct udevice *s400_dev;
#endif
diff --git a/arch/arm/include/asm/arch-imx8ulp/mu_hal.h
b/arch/arm/include/asm/mach-imx/mu_hal.h
similarity index 79%
rename from arch/arm/include/asm/arch-imx8ulp/mu_hal.h
rename to arch/arm/include/asm/mach-imx/mu_hal.h
index 10d966d5d43..5db559c1ac5 100644
--- a/arch/arm/include/asm/arch-imx8ulp/mu_hal.h
+++ b/arch/arm/include/asm/mach-imx/mu_hal.h
@@ -3,8 +3,8 @@
* Copyright 2021 NXP
*/
-#ifndef __IMX8ULP_MU_HAL_H__
-#define __IMX8ULP_MU_HAL_H__
+#ifndef __SNT_MU_HAL_H__
+#define __SNT_MU_HAL_H__
void mu_hal_init(ulong base);
int mu_hal_sendmsg(ulong base, u32 reg_index, u32 msg);
diff --git a/arch/arm/include/asm/arch-imx8ulp/s400_api.h
b/arch/arm/include/asm/mach-imx/s400_api.h
similarity index 100%
rename from arch/arm/include/asm/arch-imx8ulp/s400_api.h
rename to arch/arm/include/asm/mach-imx/s400_api.h
diff --git a/arch/arm/mach-imx/imx8ulp/ahab.c b/arch/arm/mach-imx/imx8ulp/ahab.c
new file mode 100644
index 000..87c4c66a087
--- /dev/null
+++ b/arch/arm/mach-imx/imx8ulp/ahab.c
@@ -0,0 +1,345 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define IMG_CONTAINER_BASE (0x2201UL)
+#define IMG_CONTAINER_END_BASE (IMG_CONTAINER_BASE + 0xUL)
+
+#define AHAB_NO_AUTHENTICATION_IND 0xee
+#define AHAB_BAD_KEY_HASH_IND 0xfa
+#define AHAB_INVALID_KEY_IND 0xf9
+#define AHAB_BAD_SIGNATURE_IND 0xf0
+#define AHAB_BAD_HASH_IND 0xf1
+
+static void display_ahab_auth_ind(u32 event)
+{
+ u8 resp_ind = (event >> 8) & 0xff;
+
+ switch (resp_ind) {
+ case AHAB_NO_AUTHENTICATION_IND:
+ printf("AHAB_NO_AUTHENTICATION_IND (0x%02X)\n\n", resp_ind);
+ break;
+ case AHAB_BAD_KEY_HASH_IND:
+ printf("AHAB_BAD_KEY_HASH_IND (0x%02X)\n\n", resp_ind);
+ break;
+ case AHAB_INVALID_KEY_IND:
+ printf("AHAB_INVALID_KEY_IND (0x%02X)\n\n", resp_ind);
+ break;
+ case AHAB_BAD_SIGNATURE_IND:
+ printf("AHAB_BAD_SIGNATURE_IND (0x%02X)\n\n", resp_ind);
+ break;
+ case AHAB_BAD_HASH_IND:
+ printf("AHAB_BAD_HASH_IND (0x%02X)\n\n", resp_ind);
+ break;
+ default:
+ printf("Unknown Indicator (0x%02X)\n\n", resp_ind);
+ break;
+ }
+}
+
+int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length
[PATCH 21/53] misc: S400_API: Update release RDC API
From: Ye Li
To support more RDC instances on i.MX93, update API to latest
definition.
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/mach-imx/s400_api.h | 2 +-
drivers/misc/sentinel/s400_api.c | 21 +
2 files changed, 18 insertions(+), 5 deletions(-)
diff --git a/arch/arm/include/asm/mach-imx/s400_api.h
b/arch/arm/include/asm/mach-imx/s400_api.h
index b3e6b3fa45d..d09c078df01 100644
--- a/arch/arm/include/asm/mach-imx/s400_api.h
+++ b/arch/arm/include/asm/mach-imx/s400_api.h
@@ -32,7 +32,7 @@ struct imx8ulp_s400_msg {
u32 data[(S400_MAX_MSG - 1U)];
};
-int ahab_release_rdc(u8 core_id, bool xrdc, u32 *response);
+int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response);
int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response);
int ahab_release_container(u32 *response);
int ahab_verify_image(u32 img_id, u32 *response);
diff --git a/drivers/misc/sentinel/s400_api.c b/drivers/misc/sentinel/s400_api.c
index 3d791bc868e..4e90171420f 100644
--- a/drivers/misc/sentinel/s400_api.c
+++ b/drivers/misc/sentinel/s400_api.c
@@ -14,7 +14,7 @@
DECLARE_GLOBAL_DATA_PTR;
-int ahab_release_rdc(u8 core_id, bool xrdc, u32 *response)
+int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response)
{
struct udevice *dev = gd->arch.s400_dev;
int size = sizeof(struct imx8ulp_s400_msg);
@@ -30,10 +30,23 @@ int ahab_release_rdc(u8 core_id, bool xrdc, u32 *response)
msg.tag = AHAB_CMD_TAG;
msg.size = 2;
msg.command = AHAB_RELEASE_RDC_REQ_CID;
- if (xrdc)
- msg.data[0] = (0x78 << 8) | core_id;
- else
+ switch (xrdc) {
+ case 0:
msg.data[0] = (0x74 << 8) | core_id;
+ break;
+ case 1:
+ msg.data[0] = (0x78 << 8) | core_id;
+ break;
+ case 2:
+ msg.data[0] = (0x82 << 8) | core_id;
+ break;
+ case 3:
+ msg.data[0] = (0x86 << 8) | core_id;
+ break;
+ default:
+ printf("Error: wrong xrdc index %u\n", xrdc);
+ return -EINVAL;
+ }
ret = misc_call(dev, false, &msg, size, &msg, size);
if (ret)
--
2.36.0
[PATCH 29/53] misc: fuse: support to access fuse on i.MX93
From: Alice Guo
i.MX93 fuse can be accessed through FSB and s400-api. Add mapping tables
for i.MX93. The offset address of FSB accessing OTP shadow registers is
different between i.MX8ULP and i.MX93, so use macro to define the offset
address instead of hardcode.
Signed-off-by: Alice Guo
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/imx-regs.h | 2 ++
drivers/misc/sentinel/fuse.c | 30 ++-
2 files changed, 31 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h
b/arch/arm/include/asm/arch-imx9/imx-regs.h
index 7b84b970b75..fa6951ebbe8 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -19,6 +19,8 @@
#define WDG4_BASE_ADDR 0x424aUL
#define WDG5_BASE_ADDR 0x424bUL
+#define FSB_BASE_ADDR 0x4751UL
+
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include
#include
diff --git a/drivers/misc/sentinel/fuse.c b/drivers/misc/sentinel/fuse.c
index 83d2c25731f..abb4c072f9b 100644
--- a/drivers/misc/sentinel/fuse.c
+++ b/drivers/misc/sentinel/fuse.c
@@ -31,6 +31,9 @@ struct s400_map_entry {
u32 s400_index;
};
+#if defined(CONFIG_IMX8ULP)
+#define FSB_OTP_SHADOW 0x800
+
struct fsb_map_entry fsb_mapping_table[] = {
{ 3, 8 },
{ 4, 8 },
@@ -65,6 +68,31 @@ struct s400_map_entry s400_api_mapping_table[] = {
{ 23, 1, 4, 2 }, /* OTFAD */
{ 25, 8 }, /* Test config2 */
};
+#elif defined(CONFIG_ARCH_IMX9)
+#define FSB_OTP_SHADOW 0x8000
+
+struct fsb_map_entry fsb_mapping_table[] = {
+ { 0, 8 },
+ { 1, 8 },
+ { 2, 8 },
+ { -1, 8 },
+ { 4, 8 },
+ { 5, 8 },
+ { 6, 8 }, /* UID */
+ { -1, 8 },
+ { 8, 8 },
+ { 9, 8 },
+ { 10, 8 },
+};
+
+struct s400_map_entry s400_api_mapping_table[] = {
+ { 3, 11 }, /* 24 .. 34 */
+ { 7, 8 },
+ { 16, 11 }, /* 128 .. 143 */
+ { 22, 8 },
+ { 23, 8 },
+};
+#endif
static s32 map_fsb_fuse_index(u32 bank, u32 word, bool *redundancy)
{
@@ -128,7 +156,7 @@ int fuse_sense(u32 bank, u32 word, u32 *val)
word_index = map_fsb_fuse_index(bank, word, &redundancy);
if (word_index >= 0) {
- *val = readl((ulong)FSB_BASE_ADDR + 0x800 + (word_index << 2));
+ *val = readl((ulong)FSB_BASE_ADDR + FSB_OTP_SHADOW +
(word_index << 2));
if (redundancy)
*val = (*val >> ((word % 2) * 16)) & 0x;
--
2.36.0
[PATCH 24/53] imx: imx9: Add TRDC driver for TRDC init
From: Ye Li
Add TRDC driver to iMX9. The TRDC init splits to two phases:
1. Early init phase will release TRDC from Sentinel and open write
permission to the memory where SPL image runs. Sentinel will set
the memory to RX only after ROM authentication for the OEM
closed part.
2. Init phase will configure TRDC to allow non-secure master to
access DDR. So the peripherals can work in u-boot.
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/trdc.h | 19 +
arch/arm/mach-imx/imx9/Makefile | 2 +-
arch/arm/mach-imx/imx9/soc.c | 3 +
arch/arm/mach-imx/imx9/trdc.c | 581 ++
4 files changed, 604 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/include/asm/arch-imx9/trdc.h
create mode 100644 arch/arm/mach-imx/imx9/trdc.c
diff --git a/arch/arm/include/asm/arch-imx9/trdc.h
b/arch/arm/include/asm/arch-imx9/trdc.h
new file mode 100644
index 000..1481ee375b7
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx9/trdc.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX9_TRDC_H
+#define __ASM_ARCH_IMX9_TRDC_H
+
+int trdc_mbc_set_control(ulong trdc_reg, u32 mbc_x, u32 glbac_id, u32
glbac_val);
+int trdc_mbc_blk_config(ulong trdc_reg, u32 mbc_x, u32 dom_x, u32 mem_x, u32
blk_x,
+ bool sec_access, u32 glbac_id);
+int trdc_mrc_set_control(ulong trdc_reg, u32 mrc_x, u32 glbac_id, u32
glbac_val);
+int trdc_mrc_region_config(ulong trdc_reg, u32 mrc_x, u32 dom_x, u32
addr_start,
+ u32 addr_end, bool sec_access, u32 glbac_id);
+
+void trdc_early_init(void);
+void trdc_init(void);
+
+#endif
diff --git a/arch/arm/mach-imx/imx9/Makefile b/arch/arm/mach-imx/imx9/Makefile
index 7be0343d52e..0124212f266 100644
--- a/arch/arm/mach-imx/imx9/Makefile
+++ b/arch/arm/mach-imx/imx9/Makefile
@@ -3,4 +3,4 @@
# Copyright 2022 NXP
obj-y += lowlevel_init.o
-obj-y += soc.o clock.o clock_root.o
+obj-y += soc.o clock.o clock_root.o trdc.o
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 9ea2d51495b..7c71cbdd55a 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -14,6 +14,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -204,6 +205,8 @@ int arch_cpu_init(void)
init_wdog();
clock_init();
+
+ trdc_early_init();
}
return 0;
diff --git a/arch/arm/mach-imx/imx9/trdc.c b/arch/arm/mach-imx/imx9/trdc.c
new file mode 100644
index 000..b0881697a10
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/trdc.c
@@ -0,0 +1,581 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define DID_NUM 16
+#define MBC_MAX_NUM 4
+#define MRC_MAX_NUM 2
+#define MBC_NUM(HWCFG) (((HWCFG) >> 16) & 0xF)
+#define MRC_NUM(HWCFG) (((HWCFG) >> 24) & 0x1F)
+
+struct mbc_mem_dom {
+ u32 mem_glbcfg[4];
+ u32 nse_blk_index;
+ u32 nse_blk_set;
+ u32 nse_blk_clr;
+ u32 nsr_blk_clr_all;
+ u32 memn_glbac[8];
+ /* The upper only existed in the beginning of each MBC */
+ u32 mem0_blk_cfg_w[64];
+ u32 mem0_blk_nse_w[16];
+ u32 mem1_blk_cfg_w[8];
+ u32 mem1_blk_nse_w[2];
+ u32 mem2_blk_cfg_w[8];
+ u32 mem2_blk_nse_w[2];
+ u32 mem3_blk_cfg_w[8];
+ u32 mem3_blk_nse_w[2];/*0x1F0, 0x1F4 */
+ u32 reserved[2];
+};
+
+struct mrc_rgn_dom {
+ u32 mrc_glbcfg[4];
+ u32 nse_rgn_indirect;
+ u32 nse_rgn_set;
+ u32 nse_rgn_clr;
+ u32 nse_rgn_clr_all;
+ u32 memn_glbac[8];
+ /* The upper only existed in the beginning of each MRC */
+ u32 rgn_desc_words[16][2]; /* 16 regions at max, 2 words per region */
+ u32 rgn_nse;
+ u32 reserved2[15];
+};
+
+struct mda_inst {
+ u32 mda_w[8];
+};
+
+struct trdc_mgr {
+ u32 trdc_cr;
+ u32 res0[59];
+ u32 trdc_hwcfg0;
+ u32 trdc_hwcfg1;
+ u32 res1[450];
+ struct mda_inst mda[8];
+ u32 res2[15808];
+};
+
+struct trdc_mbc {
+ struct mbc_mem_dom mem_dom[DID_NUM];
+};
+
+struct trdc_mrc {
+ struct mrc_rgn_dom mrc_dom[DID_NUM];
+};
+
+int trdc_mda_set_cpu(ulong trdc_reg, u32 mda_inst, u32 mda_reg, u8 sa, u8 dids,
+u8 did, u8 pe, u8 pidm, u8 pid)
+{
+ struct trdc_mgr *trdc_base = (struct trdc_mgr *)trdc_reg;
+ u32 *mda_w = &trdc_base->mda[mda_inst].mda_w[mda_reg];
+ u32 val = readl(mda_w);
+
+ if (val & BIT(29)) /* non-cpu */
+ return -EINVAL;
+
+ val = BIT(31) | ((pid & 0x3f) << 16) | ((pidm & 0x3f) << 8) |
+ ((pe & 0x3) << 6) | ((sa & 0x3) << 14) | ((dids & 0x3) << 4) |
+ (did & 0xf);
+
+ writel(val, mda_w);
+
+ return 0;
+}
+
+int trdc_mda_set_noncpu(ulo
[PATCH 23/53] misc: s400_api: introduce ahab_release_m33_trout
From: Peng Fan
Introduce Sentinel API ahab_release_m33_trout to make sure sentinel
release M33 trout and make sure M33 could boot.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/mach-imx/s400_api.h | 1 +
drivers/misc/sentinel/s400_api.c | 25
2 files changed, 26 insertions(+)
diff --git a/arch/arm/include/asm/mach-imx/s400_api.h
b/arch/arm/include/asm/mach-imx/s400_api.h
index d95f8227b29..dc176e1f619 100644
--- a/arch/arm/include/asm/mach-imx/s400_api.h
+++ b/arch/arm/include/asm/mach-imx/s400_api.h
@@ -55,5 +55,6 @@ int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32
*response);
int ahab_dump_buffer(u32 *buffer, u32 buffer_length);
int ahab_get_info(struct sentinel_get_info_data *info, u32 *response);
int ahab_get_fw_status(u32 *status, u32 *response);
+int ahab_release_m33_trout(void);
#endif
diff --git a/drivers/misc/sentinel/s400_api.c b/drivers/misc/sentinel/s400_api.c
index ca7903670ed..01a673e5e13 100644
--- a/drivers/misc/sentinel/s400_api.c
+++ b/drivers/misc/sentinel/s400_api.c
@@ -420,3 +420,28 @@ int ahab_get_fw_status(u32 *status, u32 *response)
return ret;
}
+
+int ahab_release_m33_trout(void)
+{
+ struct udevice *dev = gd->arch.s400_dev;
+ int size = sizeof(struct sentinel_msg);
+ struct sentinel_msg msg;
+ int ret;
+
+ if (!dev) {
+ printf("s400 dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ msg.version = AHAB_VERSION;
+ msg.tag = AHAB_CMD_TAG;
+ msg.size = 1;
+ msg.command = 0xd3;
+
+ ret = misc_call(dev, false, &msg, size, &msg, size);
+ if (ret)
+ printf("Error: %s: ret %d, response 0x%x\n",
+ __func__, ret, msg.data[0]);
+
+ return ret;
+}
--
2.36.0
[PATCH 26/53] imx: imx9: Get the chip revision through S400 API
From: Peng Fan
Update the get chip revision methond to use S400 API, also record
other information like lifecycle and UID to global data.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/global_data.h | 3 ++
arch/arm/mach-imx/imx9/soc.c | 49 +-
2 files changed, 51 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/global_data.h
b/arch/arm/include/asm/global_data.h
index 09f352269e5..6ee2a767615 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -92,6 +92,9 @@ struct arch_global_data {
#ifdef CONFIG_IMX_SENTINEL
struct udevice *s400_dev;
+ u32 soc_rev;
+ u32 lifecycle;
+ u32 uid[4];
#endif
};
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 7c71cbdd55a..c71a5a92504 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -27,6 +27,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -67,9 +68,18 @@ int mmc_get_env_dev(void)
}
#endif
+static void set_cpu_info(struct sentinel_get_info_data *info)
+{
+ gd->arch.soc_rev = info->soc;
+ gd->arch.lifecycle = info->lc;
+ memcpy((void *)&gd->arch.uid, &info->uid, 4 * sizeof(u32));
+}
+
u32 get_cpu_rev(void)
{
- return (MXC_CPU_IMX93 << 12) | CHIP_REV_1_0;
+ u32 rev = (gd->arch.soc_rev >> 24) - 0xa0;
+
+ return (MXC_CPU_IMX93 << 12) | (CHIP_REV_1_0 + rev);
}
#define UNLOCK_WORD 0xD928C520 /* unlock word */
@@ -198,6 +208,17 @@ int ft_system_setup(void *blob, struct bd_info *bd)
return 0;
}
+#if defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+ printf("UID: 0x%x 0x%x 0x%x 0x%x\n",
+ gd->arch.uid[0], gd->arch.uid[1], gd->arch.uid[2],
gd->arch.uid[3]);
+
+ serialnr->low = gd->arch.uid[0];
+ serialnr->high = gd->arch.uid[3];
+}
+#endif
+
int arch_cpu_init(void)
{
if (IS_ENABLED(CONFIG_SPL_BUILD)) {
@@ -212,6 +233,32 @@ int arch_cpu_init(void)
return 0;
}
+int imx9_probe_mu(void *ctx, struct event *event)
+{
+ struct udevice *devp;
+ int node, ret;
+ u32 res;
+ struct sentinel_get_info_data info;
+
+ node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
"fsl,imx93-mu-s4");
+
+ ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp);
+ if (ret)
+ return ret;
+
+ if (gd->flags & GD_FLG_RELOC)
+ return 0;
+
+ ret = ahab_get_info(&info, &res);
+ if (ret)
+ return ret;
+
+ set_cpu_info(&info);
+
+ return 0;
+}
+EVENT_SPY(EVT_DM_POST_INIT, imx9_probe_mu);
+
int timer_init(void)
{
#ifdef CONFIG_SPL_BUILD
--
2.36.0
[PATCH 30/53] misc: fuse: update the code for accessing fuse of i.MX93
From: Alice Guo
Sentinel have read access of OTP shadow register 0-511, and fsb have
read access of shadow 0-51/312-511.
Reviewed-by: Ye Li
Signed-off-by: Alice Guo
Signed-off-by: Peng Fan
---
drivers/misc/sentinel/fuse.c | 86 +++-
1 file changed, 74 insertions(+), 12 deletions(-)
diff --git a/drivers/misc/sentinel/fuse.c b/drivers/misc/sentinel/fuse.c
index abb4c072f9b..e2b68757664 100644
--- a/drivers/misc/sentinel/fuse.c
+++ b/drivers/misc/sentinel/fuse.c
@@ -75,22 +75,44 @@ struct fsb_map_entry fsb_mapping_table[] = {
{ 0, 8 },
{ 1, 8 },
{ 2, 8 },
- { -1, 8 },
+ { 3, 8 },
{ 4, 8 },
{ 5, 8 },
- { 6, 8 }, /* UID */
- { -1, 8 },
- { 8, 8 },
- { 9, 8 },
- { 10, 8 },
+ { 6, 4 },
+ { -1, 260 },
+ { 39, 8 },
+ { 40, 8 },
+ { 41, 8 },
+ { 42, 8 },
+ { 43, 8 },
+ { 44, 8 },
+ { 45, 8 },
+ { 46, 8 },
+ { 47, 8 },
+ { 48, 8 },
+ { 49, 8 },
+ { 50, 8 },
+ { 51, 8 },
+ { 52, 8 },
+ { 53, 8 },
+ { 54, 8 },
+ { 55, 8 },
+ { 56, 8 },
+ { 57, 8 },
+ { 58, 8 },
+ { 59, 8 },
+ { 60, 8 },
+ { 61, 8 },
+ { 62, 8 },
+ { 63, 8 },
};
struct s400_map_entry s400_api_mapping_table[] = {
- { 3, 11 }, /* 24 .. 34 */
- { 7, 8 },
- { 16, 11 }, /* 128 .. 143 */
- { 22, 8 },
- { 23, 8 },
+ { 7, 1, 7, 63 },
+ { 16, 8, },
+ { 17, 8, },
+ { 22, 1, 6 },
+ { 23, 1, 4 },
};
#endif
@@ -102,7 +124,8 @@ static s32 map_fsb_fuse_index(u32 bank, u32 word, bool
*redundancy)
/* map the fuse from ocotp fuse map to FSB*/
for (i = 0; i < size; i++) {
if (fsb_mapping_table[i].fuse_bank != -1 &&
- fsb_mapping_table[i].fuse_bank == bank) {
+ fsb_mapping_table[i].fuse_bank == bank &&
+ fsb_mapping_table[i].fuse_words > word) {
break;
}
@@ -146,6 +169,7 @@ static s32 map_s400_fuse_index(u32 bank, u32 word)
return s400_api_mapping_table[i].fuse_bank * 8 + word;
}
+#if defined(CONFIG_IMX8ULP)
int fuse_sense(u32 bank, u32 word, u32 *val)
{
s32 word_index;
@@ -198,6 +222,44 @@ int fuse_sense(u32 bank, u32 word, u32 *val)
return -ENOENT;
}
+#elif defined(CONFIG_ARCH_IMX9)
+int fuse_sense(u32 bank, u32 word, u32 *val)
+{
+ s32 word_index;
+ bool redundancy;
+
+ if (bank >= FUSE_BANKS || word >= WORDS_PER_BANKS || !val)
+ return -EINVAL;
+
+ word_index = map_fsb_fuse_index(bank, word, &redundancy);
+ if (word_index >= 0) {
+ *val = readl((ulong)FSB_BASE_ADDR + FSB_OTP_SHADOW +
(word_index << 2));
+ if (redundancy)
+ *val = (*val >> ((word % 2) * 16)) & 0x;
+
+ return 0;
+ }
+
+ word_index = map_s400_fuse_index(bank, word);
+ if (word_index >= 0) {
+ u32 data;
+ u32 res, size = 1;
+ int ret;
+
+ ret = ahab_read_common_fuse(word_index, &data, size, &res);
+ if (ret) {
+ printf("ahab read fuse failed %d, 0x%x\n", ret, res);
+ return ret;
+ }
+
+ *val = data;
+
+ return 0;
+ }
+
+ return -ENOENT;
+}
+#endif
int fuse_read(u32 bank, u32 word, u32 *val)
{
--
2.36.0
[PATCH 31/53] imx: imx9: Add gpio registers structure
From: Ye Li
Add GPIO registers structure for iMX93, so that we can enable lpgpio
driver
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/Kconfig | 1 +
arch/arm/include/asm/arch-imx9/gpio.h | 20
2 files changed, 21 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index d290194f900..e48054ab385 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -916,6 +916,7 @@ config ARCH_IMX9
select DM
select MACH_IMX
select SUPPORT_SPL
+ select GPIO_EXTRA_HEADER
select MISC
select IMX_SENTINEL
imply CMD_DM
diff --git a/arch/arm/include/asm/arch-imx9/gpio.h
b/arch/arm/include/asm/arch-imx9/gpio.h
index e69de29bb2d..40732022e7e 100644
--- a/arch/arm/include/asm/arch-imx9/gpio.h
+++ b/arch/arm/include/asm/arch-imx9/gpio.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX9_GPIO_H
+#define __ASM_ARCH_IMX9_GPIO_H
+
+struct gpio_regs {
+ u32 gpio_pdor;
+ u32 gpio_psor;
+ u32 gpio_pcor;
+ u32 gpio_ptor;
+ u32 gpio_pdir;
+ u32 gpio_pddr;
+ u32 gpio_pidr;
+ u8 gpio_pxdr[32];
+};
+
+#endif
--
2.36.0
[PATCH 32/53] imx: imx9: Add MIX power init
From: Peng Fan
Add power init of MEDIAMIX, MLMIX and DDRMIX. And clear isolation
of MIPI DSI/CSI, USBPHY after the power up.
SPL should call the power init in its boot sequence before accessing
above three MIX and USB.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/imx-regs.h | 173 +
arch/arm/include/asm/arch-imx9/sys_proto.h | 1 +
arch/arm/mach-imx/imx9/soc.c | 101
3 files changed, 275 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h
b/arch/arm/include/asm/arch-imx9/imx-regs.h
index fa6951ebbe8..049eca4f3a7 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -21,6 +21,24 @@
#define FSB_BASE_ADDR 0x4751UL
+#define ANATOP_BASE_ADDR0x4448UL
+
+#define BLK_CTRL_WAKEUPMIX_BASE_ADDR 0x4242
+#define BLK_CTRL_S_ANOMIX_BASE_ADDR 0x444f
+
+#define SRC_IPS_BASE_ADDR (0x4446)
+#define SRC_GLOBAL_RBASE (SRC_IPS_BASE_ADDR + 0x)
+
+#define SRC_DDR_RBASE (SRC_IPS_BASE_ADDR + 0x1000)
+#define SRC_ML_RBASE (SRC_IPS_BASE_ADDR + 0x1800)
+#define SRC_MEDIA_RBASE(SRC_IPS_BASE_ADDR + 0x2400)
+#define SRC_M33P_RBASE (SRC_IPS_BASE_ADDR + 0x2800)
+
+#define SRC_MIX_SLICE_FUNC_STAT_PSW_STAT BIT(0)
+#define SRC_MIX_SLICE_FUNC_STAT_RST_STAT BIT(2)
+#define SRC_MIX_SLICE_FUNC_STAT_ISO_STAT BIT(4)
+#define SRC_MIX_SLICE_FUNC_STAT_MEM_STAT BIT(12)
+
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include
#include
@@ -49,6 +67,161 @@ struct mu_type {
u32 reserved5[14];
u32 mu_attr;
};
+
+enum mix_power_domain {
+ MIX_PD_MEDIAMIX,
+ MIX_PD_MLMIX,
+ MIX_PD_DDRMIX,
+};
+
+enum src_mix_slice_id {
+ SRC_MIX_EDGELOCK = 0,
+ SRC_MIX_AONMIX = 1,
+ SRC_MIX_WAKEUPMIX = 2,
+ SRC_MIX_DDRMIX = 3,
+ SRC_MIX_DDRPHY = 4,
+ SRC_MIX_ML = 5,
+ SRC_MIX_NIC = 6,
+ SRC_MIX_HSIO = 7,
+ SRC_MIX_MEDIA = 8,
+ SRC_MIX_CM33 = 9,
+ SRC_MIX_CA55C0 = 10,
+ SRC_MIX_CA55C1 = 11,
+ SRC_MIX_CA55CLUSTER = 12,
+};
+
+enum src_mem_slice_id {
+ SRC_MEM_AONMIX = 0,
+ SRC_MEM_WAKEUPMIX = 1,
+ SRC_MEM_DDRMIX = 2,
+ SRC_MEM_DDRPHY = 3,
+ SRC_MEM_ML = 4,
+ SRC_MEM_NIC = 5,
+ SRC_MEM_OCRAM = 6,
+ SRC_MEM_HSIO = 7,
+ SRC_MEM_MEDIA = 8,
+ SRC_MEM_CA55C0 = 9,
+ SRC_MEM_CA55C1 = 10,
+ SRC_MEM_CA55CLUSTER = 11,
+ SRC_MEM_L3 = 12,
+};
+
+struct blk_ctrl_s_aonmix_regs {
+ u32 cm33_irq_mask[7];
+ u32 initnsvtor;
+ u32 reserved1[8];
+ u32 ca55_irq_mask[7];
+ u32 initsvtor;
+ u32 m33_cfg;
+ u32 reserved2[11];
+ u32 axbs_aon_ctrl;
+ u32 reserved3[27];
+ u32 dap_access_stkybit;
+ u32 reserved4[3];
+ u32 lp_handshake[2];
+ u32 ca55_cpuwait;
+ u32 ca55_rvbaraddr0_l;
+ u32 ca55_rvbaraddr0_h;
+ u32 ca55_rvbaraddr1_l;
+ u32 ca55_rvbaraddr1_h;
+ u32 s401_irq_mask;
+ u32 s401_reset_req_mask;
+ u32 s401_halt_st;
+ u32 ca55_mode;
+ u32 nmi_mask;
+ u32 nmi_clr;
+ u32 wdog_any_mask;
+ u32 s4v1_ipi_noclk_ref1;
+};
+
+struct blk_ctrl_wakeupmix_regs {
+ u32 upper_addr;
+ u32 ipg_debug_cm33;
+ u32 reserved[2];
+ u32 qch_dis;
+ u32 ssi;
+ u32 reserved1[1];
+ u32 dexsc_err;
+ u32 mqs_setting;
+ u32 sai_clk_sel;
+ u32 eqos_gpr;
+ u32 enet_clk_sel;
+ u32 reserved2[1];
+ u32 volt_detect;
+ u32 i3c2_wakeup;
+ u32 ipg_debug_ca55c0;
+ u32 ipg_debug_ca55c1;
+ u32 axi_attr_cfg;
+ u32 i3c2_sda_irq;
+};
+
+struct src_general_regs {
+ u32 reserved[1];
+ u32 authen_ctrl;
+ u32 reserved1[2];
+ u32 scr;
+ u32 srtmr;
+ u32 srmask;
+ u32 reserved2[1];
+ u32 srmr[6];
+ u32 reserved3[2];
+ u32 sbmr[2];
+ u32 reserved4[2];
+ u32 srsr;
+ u32 gpr[19];
+ u32 reserved5[24];
+ u32 gpr20;
+ u32 cm_quiesce;
+ u32 cold_reset_ssar_ack_ctrl;
+ u32 sp_iso_ctrl;
+ u32 rom_lp_ctrl;
+ u32 a55_deny_stat;
+};
+
+struct src_mem_slice_regs {
+ u32 reserved[1];
+ u32 mem_ctrl;
+ u32 memlp_ctrl_0;
+ u32 reserved1[1];
+ u32 memlp_ctrl_1;
+ u32 memlp_ctrl_2;
+ u32 mem_stat;
+};
+
+struct src_mix_slice_regs {
+ u32 reserved[1];
+ u32 authen_ctrl;
+ u32 reserved1[2];
+ u32 lpm_setting[3];
+ u32 reserved2[1];
+ u32 slice_sw_ctrl;
+ u32 single_reset_sw_ctrl;
+ u32 reserved3[6];
+ u32 a55_hdsk_ack_ctrl;
+ u32 a55_hdsk_ack_stat;
+ u32 reserved4[2];
+ u32 ssar_ack_ctrl;
+ u32 ssar_ack_stat;
+ u32 reserved5[1];
+ u32 iso_off_dly_por;
+ u32 iso_on_dly;
+ u32 iso_off_dly;
+ u32 psw_off_lf_dly;
+
[PATCH 27/53] misc: S400_API: Rename imx8ulp_s400_msg to sentinel_msg
From: Ye Li
Use more generic name for S40x msg structure
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/mach-imx/s400_api.h | 2 +-
arch/arm/mach-imx/imx8ulp/rdc.c | 2 +-
arch/arm/mach-imx/imx9/trdc.c| 2 +-
drivers/misc/sentinel/s400_api.c | 44
drivers/misc/sentinel/s4mu.c | 6 ++--
5 files changed, 28 insertions(+), 28 deletions(-)
diff --git a/arch/arm/include/asm/mach-imx/s400_api.h
b/arch/arm/include/asm/mach-imx/s400_api.h
index dc176e1f619..89fa373d06f 100644
--- a/arch/arm/include/asm/mach-imx/s400_api.h
+++ b/arch/arm/include/asm/mach-imx/s400_api.h
@@ -26,7 +26,7 @@
#define S400_MAX_MSG 255U
-struct imx8ulp_s400_msg {
+struct sentinel_msg {
u8 version;
u8 size;
u8 command;
diff --git a/arch/arm/mach-imx/imx8ulp/rdc.c b/arch/arm/mach-imx/imx8ulp/rdc.c
index cc47079d8f5..e24eeff8a20 100644
--- a/arch/arm/mach-imx/imx8ulp/rdc.c
+++ b/arch/arm/mach-imx/imx8ulp/rdc.c
@@ -184,7 +184,7 @@ int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32
perm)
int release_rdc(enum rdc_type type)
{
ulong s_mu_base = 0x2702UL;
- struct imx8ulp_s400_msg msg;
+ struct sentinel_msg msg;
int ret;
u32 rdc_id = (type == RDC_XRDC) ? 0x78 : 0x74;
diff --git a/arch/arm/mach-imx/imx9/trdc.c b/arch/arm/mach-imx/imx9/trdc.c
index b0881697a10..3f37ce712c0 100644
--- a/arch/arm/mach-imx/imx9/trdc.c
+++ b/arch/arm/mach-imx/imx9/trdc.c
@@ -315,7 +315,7 @@ bool trdc_mbc_enabled(ulong trdc_base)
int release_rdc(u8 xrdc)
{
ulong s_mu_base = 0x4752UL;
- struct imx8ulp_s400_msg msg;
+ struct sentinel_msg msg;
int ret;
u32 rdc_id;
diff --git a/drivers/misc/sentinel/s400_api.c b/drivers/misc/sentinel/s400_api.c
index 01a673e5e13..65032f77362 100644
--- a/drivers/misc/sentinel/s400_api.c
+++ b/drivers/misc/sentinel/s400_api.c
@@ -17,8 +17,8 @@ DECLARE_GLOBAL_DATA_PTR;
int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response)
{
struct udevice *dev = gd->arch.s400_dev;
- int size = sizeof(struct imx8ulp_s400_msg);
- struct imx8ulp_s400_msg msg;
+ int size = sizeof(struct sentinel_msg);
+ struct sentinel_msg msg;
int ret;
if (!dev) {
@@ -62,8 +62,8 @@ int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response)
int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response)
{
struct udevice *dev = gd->arch.s400_dev;
- int size = sizeof(struct imx8ulp_s400_msg);
- struct imx8ulp_s400_msg msg;
+ int size = sizeof(struct sentinel_msg);
+ struct sentinel_msg msg;
int ret;
if (!dev) {
@@ -92,8 +92,8 @@ int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response)
int ahab_release_container(u32 *response)
{
struct udevice *dev = gd->arch.s400_dev;
- int size = sizeof(struct imx8ulp_s400_msg);
- struct imx8ulp_s400_msg msg;
+ int size = sizeof(struct sentinel_msg);
+ struct sentinel_msg msg;
int ret;
if (!dev) {
@@ -120,8 +120,8 @@ int ahab_release_container(u32 *response)
int ahab_verify_image(u32 img_id, u32 *response)
{
struct udevice *dev = gd->arch.s400_dev;
- int size = sizeof(struct imx8ulp_s400_msg);
- struct imx8ulp_s400_msg msg;
+ int size = sizeof(struct sentinel_msg);
+ struct sentinel_msg msg;
int ret;
if (!dev) {
@@ -149,8 +149,8 @@ int ahab_verify_image(u32 img_id, u32 *response)
int ahab_forward_lifecycle(u16 life_cycle, u32 *response)
{
struct udevice *dev = gd->arch.s400_dev;
- int size = sizeof(struct imx8ulp_s400_msg);
- struct imx8ulp_s400_msg msg;
+ int size = sizeof(struct sentinel_msg);
+ struct sentinel_msg msg;
int ret;
if (!dev) {
@@ -178,8 +178,8 @@ int ahab_forward_lifecycle(u16 life_cycle, u32 *response)
int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32
*response)
{
struct udevice *dev = gd->arch.s400_dev;
- int size = sizeof(struct imx8ulp_s400_msg);
- struct imx8ulp_s400_msg msg;
+ int size = sizeof(struct sentinel_msg);
+ struct sentinel_msg msg;
int ret;
if (!dev) {
@@ -226,8 +226,8 @@ int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32
fuse_num, u32 *respo
int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response)
{
struct udevice *dev = gd->arch.s400_dev;
- int size = sizeof(struct imx8ulp_s400_msg);
- struct imx8ulp_s400_msg msg;
+ int size = sizeof(struct sentinel_msg);
+ struct sentinel_msg msg;
int ret;
if (!dev) {
@@ -259,8 +259,8 @@ int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock,
u32 *response)
int ahab_release_caam(u32 core_did, u32 *response)
{
struct udevice *dev = gd->arch.s400_dev;
- int size = sizeof(struct imx8ulp_s400_msg);
- struct imx8ulp_s400_msg msg;
+
[PATCH 22/53] misc: S400_API: New API for FW status and chip info
From: Peng Fan
Add new API to get sentinel FW status and SoC chip info
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/mach-imx/s400_api.h | 13 +
drivers/misc/sentinel/s400_api.c | 61
2 files changed, 74 insertions(+)
diff --git a/arch/arm/include/asm/mach-imx/s400_api.h
b/arch/arm/include/asm/mach-imx/s400_api.h
index d09c078df01..d95f8227b29 100644
--- a/arch/arm/include/asm/mach-imx/s400_api.h
+++ b/arch/arm/include/asm/mach-imx/s400_api.h
@@ -19,8 +19,10 @@
#define AHAB_READ_FUSE_REQ_CID 0x97
#define AHAB_GET_FW_VERSION_CID0x9D
#define AHAB_RELEASE_RDC_REQ_CID 0xC4
+#define AHAB_GET_FW_STATUS_CID 0xC5
#define AHAB_WRITE_FUSE_REQ_CID0xD6
#define AHAB_CAAM_RELEASE_CID 0xD7
+#define AHAB_GET_INFO_CID 0xDA
#define S400_MAX_MSG 255U
@@ -32,6 +34,15 @@ struct imx8ulp_s400_msg {
u32 data[(S400_MAX_MSG - 1U)];
};
+struct sentinel_get_info_data {
+ u32 hdr;
+ u32 soc;
+ u32 lc;
+ u32 uid[4];
+ u32 sha256_rom_patch[8];
+ u32 sha_fw[8];
+};
+
int ahab_release_rdc(u8 core_id, u8 xrdc, u32 *response);
int ahab_auth_oem_ctnr(ulong ctnr_addr, u32 *response);
int ahab_release_container(u32 *response);
@@ -42,5 +53,7 @@ int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32
fuse_num, u32 *respo
int ahab_release_caam(u32 core_did, u32 *response);
int ahab_get_fw_version(u32 *fw_version, u32 *sha1, u32 *response);
int ahab_dump_buffer(u32 *buffer, u32 buffer_length);
+int ahab_get_info(struct sentinel_get_info_data *info, u32 *response);
+int ahab_get_fw_status(u32 *status, u32 *response);
#endif
diff --git a/drivers/misc/sentinel/s400_api.c b/drivers/misc/sentinel/s400_api.c
index 4e90171420f..ca7903670ed 100644
--- a/drivers/misc/sentinel/s400_api.c
+++ b/drivers/misc/sentinel/s400_api.c
@@ -359,3 +359,64 @@ int ahab_dump_buffer(u32 *buffer, u32 buffer_length)
return i;
}
+
+int ahab_get_info(struct sentinel_get_info_data *info, u32 *response)
+{
+ struct udevice *dev = gd->arch.s400_dev;
+ int size = sizeof(struct imx8ulp_s400_msg);
+ struct imx8ulp_s400_msg msg;
+ int ret;
+
+ if (!dev) {
+ printf("s400 dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ msg.version = AHAB_VERSION;
+ msg.tag = AHAB_CMD_TAG;
+ msg.size = 4;
+ msg.command = AHAB_GET_INFO_CID;
+ msg.data[0] = upper_32_bits((ulong)info);
+ msg.data[1] = lower_32_bits((ulong)info);
+ msg.data[2] = sizeof(struct sentinel_get_info_data);
+
+ ret = misc_call(dev, false, &msg, size, &msg, size);
+ if (ret)
+ printf("Error: %s: ret %d, response 0x%x\n",
+ __func__, ret, msg.data[0]);
+
+ if (response)
+ *response = msg.data[0];
+
+ return ret;
+}
+
+int ahab_get_fw_status(u32 *status, u32 *response)
+{
+ struct udevice *dev = gd->arch.s400_dev;
+ int size = sizeof(struct imx8ulp_s400_msg);
+ struct imx8ulp_s400_msg msg;
+ int ret;
+
+ if (!dev) {
+ printf("s400 dev is not initialized\n");
+ return -ENODEV;
+ }
+
+ msg.version = AHAB_VERSION;
+ msg.tag = AHAB_CMD_TAG;
+ msg.size = 1;
+ msg.command = AHAB_GET_FW_STATUS_CID;
+
+ ret = misc_call(dev, false, &msg, size, &msg, size);
+ if (ret)
+ printf("Error: %s: ret %d, response 0x%x\n",
+ __func__, ret, msg.data[0]);
+
+ if (response)
+ *response = msg.data[0];
+
+ *status = msg.data[1] & 0xF;
+
+ return ret;
+}
--
2.36.0
[PATCH 25/53] imx: imx9: Add AHAB boot support
From: Ye Li
Add AHAB driver for iMX9 to do authentication by calling sentinel API
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/Kconfig | 5 +
arch/arm/mach-imx/imx9/Makefile | 1 +
arch/arm/mach-imx/imx9/ahab.c | 346
3 files changed, 352 insertions(+)
create mode 100644 arch/arm/mach-imx/imx9/ahab.c
diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig
index ce58e41428f..dae9f658e65 100644
--- a/arch/arm/mach-imx/imx9/Kconfig
+++ b/arch/arm/mach-imx/imx9/Kconfig
@@ -1,5 +1,10 @@
if ARCH_IMX9
+config AHAB_BOOT
+bool "Support i.MX9 AHAB features"
+help
+This option enables the support for AHAB secure boot.
+
config IMX9
bool
select HAS_CAAM
diff --git a/arch/arm/mach-imx/imx9/Makefile b/arch/arm/mach-imx/imx9/Makefile
index 0124212f266..41a22500c95 100644
--- a/arch/arm/mach-imx/imx9/Makefile
+++ b/arch/arm/mach-imx/imx9/Makefile
@@ -4,3 +4,4 @@
obj-y += lowlevel_init.o
obj-y += soc.o clock.o clock_root.o trdc.o
+obj-$(CONFIG_AHAB_BOOT) += ahab.o
diff --git a/arch/arm/mach-imx/imx9/ahab.c b/arch/arm/mach-imx/imx9/ahab.c
new file mode 100644
index 000..6aa949619b5
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/ahab.c
@@ -0,0 +1,346 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define IMG_CONTAINER_BASE (0x8000UL)
+#define IMG_CONTAINER_END_BASE (IMG_CONTAINER_BASE + 0xUL)
+
+#define AHAB_NO_AUTHENTICATION_IND 0xee
+#define AHAB_BAD_KEY_HASH_IND 0xfa
+#define AHAB_INVALID_KEY_IND 0xf9
+#define AHAB_BAD_SIGNATURE_IND 0xf0
+#define AHAB_BAD_HASH_IND 0xf1
+
+static void display_ahab_auth_ind(u32 event)
+{
+ u8 resp_ind = (event >> 8) & 0xff;
+
+ switch (resp_ind) {
+ case AHAB_NO_AUTHENTICATION_IND:
+ printf("AHAB_NO_AUTHENTICATION_IND (0x%02X)\n\n", resp_ind);
+ break;
+ case AHAB_BAD_KEY_HASH_IND:
+ printf("AHAB_BAD_KEY_HASH_IND (0x%02X)\n\n", resp_ind);
+ break;
+ case AHAB_INVALID_KEY_IND:
+ printf("AHAB_INVALID_KEY_IND (0x%02X)\n\n", resp_ind);
+ break;
+ case AHAB_BAD_SIGNATURE_IND:
+ printf("AHAB_BAD_SIGNATURE_IND (0x%02X)\n\n", resp_ind);
+ break;
+ case AHAB_BAD_HASH_IND:
+ printf("AHAB_BAD_HASH_IND (0x%02X)\n\n", resp_ind);
+ break;
+ default:
+ printf("Unknown Indicator (0x%02X)\n\n", resp_ind);
+ break;
+ }
+}
+
+int ahab_auth_cntr_hdr(struct container_hdr *container, u16 length)
+{
+ int err;
+ u32 resp;
+
+ memcpy((void *)IMG_CONTAINER_BASE, (const void *)container,
+ ALIGN(length, CONFIG_SYS_CACHELINE_SIZE));
+
+ flush_dcache_range(IMG_CONTAINER_BASE,
+ IMG_CONTAINER_BASE + ALIGN(length,
CONFIG_SYS_CACHELINE_SIZE) - 1);
+
+ err = ahab_auth_oem_ctnr(IMG_CONTAINER_BASE, &resp);
+ if (err) {
+ printf("Authenticate container hdr failed, return %d, resp
0x%x\n",
+ err, resp);
+ display_ahab_auth_ind(resp);
+ }
+
+ return err;
+}
+
+int ahab_auth_release(void)
+{
+ int err;
+ u32 resp;
+
+ err = ahab_release_container(&resp);
+ if (err) {
+ printf("Error: release container failed, resp 0x%x!\n", resp);
+ display_ahab_auth_ind(resp);
+ }
+
+ return err;
+}
+
+int ahab_verify_cntr_image(struct boot_img_t *img, int image_index)
+{
+ int err;
+ u32 resp;
+
+ err = ahab_verify_image(image_index, &resp);
+ if (err) {
+ printf("Authenticate img %d failed, return %d, resp 0x%x\n",
+ image_index, err, resp);
+ display_ahab_auth_ind(resp);
+
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static inline bool check_in_dram(ulong addr)
+{
+ int i;
+ struct bd_info *bd = gd->bd;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
+ if (bd->bi_dram[i].size) {
+ if (addr >= bd->bi_dram[i].start &&
+ addr < (bd->bi_dram[i].start + bd->bi_dram[i].size))
+ return true;
+ }
+ }
+
+ return false;
+}
+
+int authenticate_os_container(ulong addr)
+{
+ struct container_hdr *phdr;
+ int i, ret = 0;
+ int err;
+ u16 length;
+ struct boot_img_t *img;
+ unsigned long s, e;
+
+ if (addr % 4) {
+ puts("Error: Image's address is not 4 byte aligned\n");
+ return -EINVAL;
+ }
+
+ if (!check_in_dram(addr)) {
+ puts("Error: Image's address is inval
[PATCH 28/53] misc: imx8ulp: move fuse.c from imx8ulp to sentinel
From: Alice Guo
The i.MX93 platform wants to reuse drivers/misc/imx8ulp/fuse.c. Moving
fuse.c from the folder imx8ulp to sentinel makes it can be used by other
platforms.
Signed-off-by: Alice Guo
Signed-off-by: Peng Fan
---
drivers/misc/Makefile | 2 --
drivers/misc/imx8ulp/Makefile | 3 ---
drivers/misc/sentinel/Makefile| 1 +
drivers/misc/{imx8ulp => sentinel}/fuse.c | 0
4 files changed, 1 insertion(+), 5 deletions(-)
delete mode 100644 drivers/misc/imx8ulp/Makefile
rename drivers/misc/{imx8ulp => sentinel}/fuse.c (100%)
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 31d639b837c..d494639cd95 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -49,8 +49,6 @@ obj-$(CONFIG_SANDBOX) += irq_sandbox.o irq_sandbox_test.o
obj-$(CONFIG_$(SPL_)I2C_EEPROM) += i2c_eeprom.o
obj-$(CONFIG_IHS_FPGA) += ihs_fpga.o
obj-$(CONFIG_IMX8) += imx8/
-obj-$(CONFIG_IMX8ULP) += imx8ulp/
-obj-$(CONFIG_IMX8ULP) += imx8ulp/
obj-$(CONFIG_IMX_SENTINEL) += sentinel/
obj-$(CONFIG_LED_STATUS) += status_led.o
obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o
diff --git a/drivers/misc/imx8ulp/Makefile b/drivers/misc/imx8ulp/Makefile
deleted file mode 100644
index 450e615e645..000
--- a/drivers/misc/imx8ulp/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-$(CONFIG_CMD_FUSE) += fuse.o
diff --git a/drivers/misc/sentinel/Makefile b/drivers/misc/sentinel/Makefile
index 3e2f623b278..446154cb201 100644
--- a/drivers/misc/sentinel/Makefile
+++ b/drivers/misc/sentinel/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y += s400_api.o s4mu.o
+obj-$(CONFIG_CMD_FUSE) += fuse.o
diff --git a/drivers/misc/imx8ulp/fuse.c b/drivers/misc/sentinel/fuse.c
similarity index 100%
rename from drivers/misc/imx8ulp/fuse.c
rename to drivers/misc/sentinel/fuse.c
--
2.36.0
[PATCH 33/53] imx: imx9: Add M33 release prepare function
From: Peng Fan
To support on-demand booting M33 image from A core. SPL needs
to follow M33 kick up sequence to release M33 firstly,
then set M33 CPUWAIT signal. ATF will clear CPUWAIT to kick
M33 to run.
The prepare function also works around the M33 TCM ECC issue by
clean the TCM. Also enable sentinel handshake and WDOG1 clock
for M33 stop and reset.
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/sys_proto.h | 2 +
arch/arm/mach-imx/imx9/soc.c | 51 ++
2 files changed, 53 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx9/sys_proto.h
b/arch/arm/include/asm/arch-imx9/sys_proto.h
index 5ae7a043398..ba97f92f5ae 100644
--- a/arch/arm/include/asm/arch-imx9/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx9/sys_proto.h
@@ -9,4 +9,6 @@
#include
void soc_power_init(void);
+bool m33_is_rom_kicked(void);
+int m33_prepare(void);
#endif
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 68f3ddd4287..2a29454d1eb 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -13,6 +13,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -378,3 +379,53 @@ void soc_power_init(void)
disable_isolation();
}
+
+static bool m33_is_rom_kicked(void)
+{
+ struct blk_ctrl_s_aonmix_regs *s_regs =
+ (struct blk_ctrl_s_aonmix_regs
*)BLK_CTRL_S_ANOMIX_BASE_ADDR;
+
+ if (!(readl(&s_regs->m33_cfg) & BIT(2)))
+ return true;
+
+ return false;
+}
+
+int m33_prepare(void)
+{
+ struct src_mix_slice_regs *mix_regs =
+ (struct src_mix_slice_regs *)(ulong)(SRC_IPS_BASE_ADDR + 0x400
* (SRC_MIX_CM33 + 1));
+ struct src_general_regs *global_regs =
+ (struct src_general_regs *)(ulong)SRC_GLOBAL_RBASE;
+ struct blk_ctrl_s_aonmix_regs *s_regs =
+ (struct blk_ctrl_s_aonmix_regs
*)BLK_CTRL_S_ANOMIX_BASE_ADDR;
+ u32 val;
+
+ if (m33_is_rom_kicked())
+ return -EPERM;
+
+ /* Release reset of M33 */
+ setbits_le32(&global_regs->scr, BIT(0));
+
+ /* Check the reset released in M33 MIX func stat */
+ val = readl(&mix_regs->func_stat);
+ while (!(val & SRC_MIX_SLICE_FUNC_STAT_RST_STAT))
+ val = readl(&mix_regs->func_stat);
+
+ /* Release Sentinel TROUT */
+ ahab_release_m33_trout();
+
+ /* Mask WDOG1 IRQ from A55, we use it for M33 reset */
+ setbits_le32(&s_regs->ca55_irq_mask[1], BIT(6));
+
+ /* Turn on WDOG1 clock */
+ ccm_lpcg_on(CCGR_WDG1, 1);
+
+ /* Set sentinel LP handshake for M33 reset */
+ setbits_le32(&s_regs->lp_handshake[0], BIT(6));
+
+ /* Clear M33 TCM for ECC */
+ memset((void *)(ulong)0x201e, 0, 0x4);
+
+ return 0;
+}
--
2.36.0
[PATCH 36/53] imx: imx9: clock: Add DDR clock support
From: Ye Li
Implement the DDR driver clock interfaces for set DDR rate and
bypass DDR PLL
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/clock.h | 3 ++
arch/arm/mach-imx/imx9/clock.c | 41 ++
2 files changed, 44 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx9/clock.h
b/arch/arm/include/asm/arch-imx9/clock.h
index fcf04d66f05..d96f126a1d1 100644
--- a/arch/arm/include/asm/arch-imx9/clock.h
+++ b/arch/arm/include/asm/arch-imx9/clock.h
@@ -213,6 +213,9 @@ void init_clk_usdhc(u32 index);
int enable_i2c_clk(unsigned char enable, u32 i2c_num);
u32 imx_get_i2cclk(u32 i2c_num);
u32 mxc_get_clock(enum mxc_clock clk);
+void dram_pll_init(ulong pll_val);
+void dram_enable_bypass(ulong clk_val);
+void dram_disable_bypass(void);
int ccm_clk_src_on(enum ccm_clk_src oscpll, bool enable);
int ccm_clk_src_auto(enum ccm_clk_src oscpll, bool enable);
diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c
index 55cbb40f328..5d2bc0d2f8f 100644
--- a/arch/arm/mach-imx/imx9/clock.c
+++ b/arch/arm/mach-imx/imx9/clock.c
@@ -626,6 +626,47 @@ void enable_usboh3_clk(unsigned char enable)
}
}
+#ifdef CONFIG_SPL_BUILD
+void dram_pll_init(ulong pll_val)
+{
+ configure_fracpll(DRAM_PLL_CLK, pll_val);
+}
+
+void dram_enable_bypass(ulong clk_val)
+{
+ switch (clk_val) {
+ case MHZ(400):
+ ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD1, 2);
+ break;
+ case MHZ(333):
+ ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD0, 3);
+ break;
+ case MHZ(200):
+ ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD1, 4);
+ break;
+ case MHZ(100):
+ ccm_clk_root_cfg(DRAM_ALT_CLK_ROOT, SYS_PLL_PFD1, 8);
+ break;
+ default:
+ printf("No matched freq table %lu\n", clk_val);
+ return;
+ }
+
+ /* Set DRAM APB to 133Mhz */
+ ccm_clk_root_cfg(DRAM_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+ /* Switch from DRAM clock root from PLL to CCM */
+ ccm_shared_gpr_set(SHARED_GPR_DRAM_CLK, SHARED_GPR_DRAM_CLK_SEL_CCM);
+}
+
+void dram_disable_bypass(void)
+{
+ /* Set DRAM APB to 133Mhz */
+ ccm_clk_root_cfg(DRAM_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3);
+ /* Switch from DRAM clock root from CCM to PLL */
+ ccm_shared_gpr_set(SHARED_GPR_DRAM_CLK, SHARED_GPR_DRAM_CLK_SEL_PLL);
+}
+#endif
+
int clock_init(void)
{
int i;
--
2.36.0
[PATCH 37/53] ddr: imx: Add i.MX9 DDR controller driver
From: Ye Li
Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common
directory under imx, then use dedicated ddr controller driver for each
iMX9 and iMX8M.
The DDRPHY registers are space compressed, so it needs conversion to
access the DDRPHY address. Introduce a common PHY address remap function
for both iMX8M and iMX9 for all PHY registers accessing.
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8m/ddr.h | 6 +-
arch/arm/include/asm/arch-imx9/ddr.h | 126 +
drivers/Makefile | 1 +
drivers/ddr/imx/Kconfig | 2 +
drivers/ddr/imx/imx8m/Kconfig | 1 +
drivers/ddr/imx/imx8m/Makefile| 3 +-
drivers/ddr/imx/imx8m/ddr_init.c | 219
drivers/ddr/imx/imx9/Kconfig | 21 +
drivers/ddr/imx/imx9/Makefile | 10 +
drivers/ddr/imx/imx9/ddr_init.c | 485 ++
drivers/ddr/imx/phy/Kconfig | 4 +
drivers/ddr/imx/phy/Makefile | 9 +
drivers/ddr/imx/{imx8m => phy}/ddrphy_csr.c | 0
drivers/ddr/imx/{imx8m => phy}/ddrphy_train.c | 1 -
drivers/ddr/imx/phy/ddrphy_utils.c| 169 ++
drivers/ddr/imx/{imx8m => phy}/helper.c | 45 +-
16 files changed, 1077 insertions(+), 25 deletions(-)
create mode 100644 arch/arm/include/asm/arch-imx9/ddr.h
create mode 100644 drivers/ddr/imx/imx9/Kconfig
create mode 100644 drivers/ddr/imx/imx9/Makefile
create mode 100644 drivers/ddr/imx/imx9/ddr_init.c
create mode 100644 drivers/ddr/imx/phy/Kconfig
create mode 100644 drivers/ddr/imx/phy/Makefile
rename drivers/ddr/imx/{imx8m => phy}/ddrphy_csr.c (100%)
rename drivers/ddr/imx/{imx8m => phy}/ddrphy_train.c (98%)
create mode 100644 drivers/ddr/imx/phy/ddrphy_utils.c
rename drivers/ddr/imx/{imx8m => phy}/helper.c (79%)
diff --git a/arch/arm/include/asm/arch-imx8m/ddr.h
b/arch/arm/include/asm/arch-imx8m/ddr.h
index 2ce8a8f2d41..2f76e7d69b9 100644
--- a/arch/arm/include/asm/arch-imx8m/ddr.h
+++ b/arch/arm/include/asm/arch-imx8m/ddr.h
@@ -725,6 +725,8 @@ void update_umctl2_rank_space_setting(unsigned int
pstat_num);
void get_trained_CDD(unsigned int fsp);
unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr);
+ulong ddrphy_addr_remap(uint32_t paddr_apb_from_ctlr);
+
static inline void reg32_write(unsigned long addr, u32 val)
{
writel(val, addr);
@@ -741,9 +743,9 @@ static inline void reg32setbit(unsigned long addr, u32 bit)
}
#define dwc_ddrphy_apb_wr(addr, data) \
- reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr), data)
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr),
data)
#define dwc_ddrphy_apb_rd(addr) \
- reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr))
+ reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr))
extern struct dram_cfg_param ddrphy_trained_csr[];
extern uint32_t ddrphy_trained_csr_num;
diff --git a/arch/arm/include/asm/arch-imx9/ddr.h
b/arch/arm/include/asm/arch-imx9/ddr.h
new file mode 100644
index 000..62e6f7dda53
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx9/ddr.h
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX8M_DDR_H
+#define __ASM_ARCH_IMX8M_DDR_H
+
+#include
+#include
+
+#define DDR_CTL_BASE 0x4E30
+#define DDR_PHY_BASE 0x4E10
+#define DDRMIX_BLK_CTRL_BASE 0x4E01
+
+#define REG_DDRDSR_2 (DDR_CTL_BASE + 0xB24)
+#define REG_DDR_SDRAM_CFG (DDR_CTL_BASE + 0x110)
+#define REG_DDR_DEBUG_19 (DDR_CTL_BASE + 0xF48)
+
+#define SRC_BASE_ADDR (0x4446)
+#define SRC_DPHY_BASE_ADDR (SRC_BASE_ADDR + 0x1400)
+#define REG_SRC_DPHY_SW_CTRL (SRC_DPHY_BASE_ADDR + 0x20)
+#define REG_SRC_DPHY_SINGLE_RESET_SW_CTRL (SRC_DPHY_BASE_ADDR + 0x24)
+
+#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (DDR_PHY_BASE + ((X) * 0x200))
+#define DDRPHY_MEM(X) (DDR_PHY_BASE + ((X) * 0x200) +
0x5)
+
+/* PHY State */
+enum pstate {
+ PS0,
+ PS1,
+ PS2,
+ PS3,
+};
+
+enum msg_response {
+ TRAIN_SUCCESS = 0x7,
+ TRAIN_STREAM_START = 0x8,
+ TRAIN_FAIL = 0xff,
+};
+
+/* user data type */
+enum fw_type {
+ FW_1D_IMAGE,
+ FW_2D_IMAGE,
+};
+
+struct dram_cfg_param {
+ unsigned int reg;
+ unsigned int val;
+};
+
+struct dram_fsp_msg {
+ unsigned int drate;
+ enum fw_type fw_type;
+ struct dram_cfg_param *fsp_cfg;
+ unsigned int fsp_cfg_num;
+};
+
+struct dram_timing_info {
+ /* umctl2 config */
+ struct dram_cfg_param *ddrc_cfg;
+ unsigned int ddrc_cfg_num;
+ /* ddrphy config */
+ struct dram_cfg_param *ddrphy_cfg;
+ unsigned int ddrphy_cfg_num;
+ /* ddr fsp
[PATCH 34/53] imx: imx9: Support booting m33 from Acore
From: Peng Fan
Add bootaux command to support on-demand booting M33 from u-boot.
It kicks M33 via ATF by "bootaux 0x201e 0"
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/Makefile | 4 +
arch/arm/mach-imx/imx9/imx_bootaux.c | 133 +++
arch/arm/mach-imx/imx9/soc.c | 10 +-
include/imx_sip.h| 1 +
4 files changed, 147 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/mach-imx/imx9/imx_bootaux.c
diff --git a/arch/arm/mach-imx/imx9/Makefile b/arch/arm/mach-imx/imx9/Makefile
index 41a22500c95..6d038a60c67 100644
--- a/arch/arm/mach-imx/imx9/Makefile
+++ b/arch/arm/mach-imx/imx9/Makefile
@@ -5,3 +5,7 @@
obj-y += lowlevel_init.o
obj-y += soc.o clock.o clock_root.o trdc.o
obj-$(CONFIG_AHAB_BOOT) += ahab.o
+
+#ifndef CONFIG_SPL_BUILD
+obj-y += imx_bootaux.o
+#endif
diff --git a/arch/arm/mach-imx/imx9/imx_bootaux.c
b/arch/arm/mach-imx/imx9/imx_bootaux.c
new file mode 100644
index 000..3b6662aeb81
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/imx_bootaux.c
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+int arch_auxiliary_core_check_up(u32 core_id)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0,
+ 0, 0, 0, 0, &res);
+
+ return res.a0;
+}
+
+int arch_auxiliary_core_down(u32 core_id)
+{
+ struct arm_smccc_res res;
+
+ printf("## Stopping auxiliary core\n");
+
+ arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STOP, 0, 0,
+ 0, 0, 0, 0, &res);
+
+ return 0;
+}
+
+int arch_auxiliary_core_up(u32 core_id, ulong addr)
+{
+ struct arm_smccc_res res;
+ u32 stack, pc;
+
+ if (!addr)
+ return -EINVAL;
+
+ stack = *(u32 *)addr;
+ pc = *(u32 *)(addr + 4);
+
+ printf("## Starting auxiliary core stack = 0x%08X, pc = 0x%08X...\n",
stack, pc);
+
+ arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0,
+ 0, 0, 0, 0, &res);
+
+ return 0;
+}
+
+/*
+ * To i.MX6SX and i.MX7D, the image supported by bootaux needs
+ * the reset vector at the head for the image, with SP and PC
+ * as the first two words.
+ *
+ * Per the cortex-M reference manual, the reset vector of M4/M7 needs
+ * to exist at 0x0 (TCMUL/IDTCM). The PC and SP are the first two addresses
+ * of that vector. So to boot M4/M7, the A core must build the M4/M7's reset
+ * vector with getting the PC and SP from image and filling them to
+ * TCMUL/IDTCM. When M4/M7 is kicked, it will load the PC and SP by itself.
+ * The TCMUL/IDTCM is mapped to (MCU_BOOTROM_BASE_ADDR) at A core side for
+ * accessing the M4/M7 TCMUL/IDTCM.
+ */
+static int do_bootaux(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ ulong addr;
+ int ret, up;
+ u32 core = 0;
+ u32 stop = 0;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ if (argc > 2)
+ core = simple_strtoul(argv[2], NULL, 10);
+
+ if (argc > 3)
+ stop = simple_strtoul(argv[3], NULL, 10);
+
+ up = arch_auxiliary_core_check_up(core);
+ if (up) {
+ printf("## Auxiliary core is already up\n");
+ return CMD_RET_SUCCESS;
+ }
+
+ addr = simple_strtoul(argv[1], NULL, 16);
+
+ if (!addr)
+ return CMD_RET_FAILURE;
+
+ ret = arch_auxiliary_core_up(core, addr);
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ return CMD_RET_SUCCESS;
+}
+
+static int do_stopaux(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ int ret, up;
+
+ up = arch_auxiliary_core_check_up(0);
+ if (!up) {
+ printf("## Auxiliary core is already down\n");
+ return CMD_RET_SUCCESS;
+ }
+
+ ret = arch_auxiliary_core_down(0);
+ if (ret)
+ return CMD_RET_FAILURE;
+
+ return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+ stopaux, CONFIG_SYS_MAXARGS, 1, do_stopaux,
+ "Stop auxiliary core",
+ " []\n"
+ " - start auxiliary core [] (default 0),\n"
+ " at address \n"
+);
+
+U_BOOT_CMD(
+ bootaux, CONFIG_SYS_MAXARGS, 1, do_bootaux,
+ "Start auxiliary core",
+ " []\n"
+ " - start auxiliary core [] (default 0),\n"
+ " at address \n"
+);
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 2a29454d1eb..ca88271564c 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -131,6 +131,14 @@ static struct mm_region imx93_mem_map[] = {
.size = 0x10UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE
+ }, {
+ /* TCM */
+ .virt = 0x201cUL,
+ .phys = 0x201
[PATCH 45/53] net: dwc_eth_qos: move i.MX code out
From: Peng Fan
Move i.MX code to a standalone file to make it easy for adding new
platform support
Reviewed-by: Ramon Fried
Signed-off-by: Peng Fan
---
drivers/net/Makefile | 1 +
drivers/net/dwc_eth_qos.c | 92 --
drivers/net/dwc_eth_qos.h | 2 +
drivers/net/dwc_eth_qos_imx.c | 121 ++
4 files changed, 124 insertions(+), 92 deletions(-)
create mode 100644 drivers/net/dwc_eth_qos_imx.c
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 69fb3bbbf7c..9536af11946 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_DM_ETH_PHY) += eth-phy-uclass.o
obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o
obj-$(CONFIG_DSA_SANDBOX) += dsa_sandbox.o
obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
+obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o
obj-$(CONFIG_E1000) += e1000.o
obj-$(CONFIG_E1000_SPI) += e1000_spi.o
obj-$(CONFIG_EEPRO100) += eepro100.o
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index b69a9feb824..1f24f5cb0cf 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -506,20 +506,6 @@ static ulong eqos_get_tick_clk_rate_stm32(struct udevice
*dev)
#endif
}
-__weak u32 imx_get_eqos_csr_clk(void)
-{
- return 100 * 100;
-}
-__weak int imx_eqos_txclk_set_rate(unsigned long rate)
-{
- return 0;
-}
-
-static ulong eqos_get_tick_clk_rate_imx(struct udevice *dev)
-{
- return imx_get_eqos_csr_clk();
-}
-
static int eqos_set_full_duplex(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
@@ -616,38 +602,6 @@ static int eqos_set_tx_clk_speed_tegra186(struct udevice
*dev)
return 0;
}
-static int eqos_set_tx_clk_speed_imx(struct udevice *dev)
-{
- struct eqos_priv *eqos = dev_get_priv(dev);
- ulong rate;
- int ret;
-
- debug("%s(dev=%p):\n", __func__, dev);
-
- switch (eqos->phy->speed) {
- case SPEED_1000:
- rate = 125 * 1000 * 1000;
- break;
- case SPEED_100:
- rate = 25 * 1000 * 1000;
- break;
- case SPEED_10:
- rate = 2.5 * 1000 * 1000;
- break;
- default:
- pr_err("invalid speed %d", eqos->phy->speed);
- return -EINVAL;
- }
-
- ret = imx_eqos_txclk_set_rate(rate);
- if (ret < 0) {
- pr_err("imx (tx_clk, %lu) failed: %d", rate, ret);
- return ret;
- }
-
- return 0;
-}
-
static int eqos_adjust_link(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
@@ -1468,24 +1422,6 @@ static phy_interface_t eqos_get_interface_tegra186(const
struct udevice *dev)
return PHY_INTERFACE_MODE_MII;
}
-static int eqos_probe_resources_imx(struct udevice *dev)
-{
- struct eqos_priv *eqos = dev_get_priv(dev);
- phy_interface_t interface;
-
- debug("%s(dev=%p):\n", __func__, dev);
-
- interface = eqos->config->interface(dev);
-
- if (interface == PHY_INTERFACE_MODE_NA) {
- pr_err("Invalid PHY interface\n");
- return -EINVAL;
- }
-
- debug("%s: OK\n", __func__);
- return 0;
-}
-
static int eqos_remove_resources_tegra186(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
@@ -1695,34 +1631,6 @@ static const struct eqos_config __maybe_unused
eqos_stm32_config = {
.ops = &eqos_stm32_ops
};
-static struct eqos_ops eqos_imx_ops = {
- .eqos_inval_desc = eqos_inval_desc_generic,
- .eqos_flush_desc = eqos_flush_desc_generic,
- .eqos_inval_buffer = eqos_inval_buffer_generic,
- .eqos_flush_buffer = eqos_flush_buffer_generic,
- .eqos_probe_resources = eqos_probe_resources_imx,
- .eqos_remove_resources = eqos_null_ops,
- .eqos_stop_resets = eqos_null_ops,
- .eqos_start_resets = eqos_null_ops,
- .eqos_stop_clks = eqos_null_ops,
- .eqos_start_clks = eqos_null_ops,
- .eqos_calibrate_pads = eqos_null_ops,
- .eqos_disable_calibration = eqos_null_ops,
- .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_imx,
- .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_imx
-};
-
-struct eqos_config __maybe_unused eqos_imx_config = {
- .reg_access_always_ok = false,
- .mdio_wait = 10,
- .swr_wait = 50,
- .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
- .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
- .axi_bus_width = EQOS_AXI_WIDTH_64,
- .interface = dev_read_phy_mode,
- .ops = &eqos_imx_ops
-};
-
static const struct udevice_id eqos_ids[] = {
#if IS_ENABLED(CONFIG_DWC_ETH_QOS_TEGRA186)
{
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index 68b367b068a..ce90e1f1ce1 100644
--- a/drivers/net/dwc_eth_qos.h
+++ b/drivers/net/dwc_eth_qos.h
@@ -278,3 +278,5 @@ void eqos_flush_desc_generic(void *desc);
void eqos_inva
[PATCH 39/53] arm: dts: Add i.MX93 SoC DTSi file
From: Peng Fan
Add the DTSi file and DT header files for i.MX93 SoC
Signed-off-by: Ye Li
Signed-off-by: Alice Guo
Signed-off-by: Peng Fan
---
arch/arm/dts/imx93.dtsi | 688
include/dt-bindings/clock/imx93-clock.h | 203 +++
include/dt-bindings/power/imx93-power.h | 12 +
3 files changed, 903 insertions(+)
create mode 100644 arch/arm/dts/imx93.dtsi
create mode 100644 include/dt-bindings/clock/imx93-clock.h
create mode 100644 include/dt-bindings/power/imx93-power.h
diff --git a/arch/arm/dts/imx93.dtsi b/arch/arm/dts/imx93.dtsi
new file mode 100644
index 000..28026ccecc8
--- /dev/null
+++ b/arch/arm/dts/imx93.dtsi
@@ -0,0 +1,688 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021 NXP
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "imx93-pinfunc.h"
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
+ mmc2 = &usdhc3;
+ ethernet0 = &fec;
+ ethernet1 = &eqos;
+ serial0 = &lpuart1;
+ serial1 = &lpuart2;
+ serial2 = &lpuart3;
+ serial3 = &lpuart4;
+ serial4 = &lpuart5;
+ serial5 = &lpuart6;
+ serial6 = &lpuart7;
+ serial7 = &lpuart8;
+ i2c0 = &lpi2c1;
+ i2c1 = &lpi2c2;
+ i2c2 = &lpi2c3;
+ i2c3 = &lpi2c4;
+ i2c4 = &lpi2c5;
+ i2c5 = &lpi2c6;
+ usb0 = &usbotg1;
+ usb1 = &usbotg2;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ A55_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0>;
+ enable-method = "psci";
+ #cooling-cells = <2>;
+ };
+
+ A55_1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x100>;
+ enable-method = "psci";
+ #cooling-cells = <2>;
+ };
+
+ };
+
+ osc_32k: clock-osc-32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "osc_32k";
+ };
+
+ osc_24m: clock-osc-24m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2400>;
+ clock-output-names = "osc_24m";
+ };
+
+ clk_ext1: clock-ext1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <13300>;
+ clock-output-names = "clk_ext1";
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = ,
+,
+,
+;
+ clock-frequency = <2400>;
+ arm,no-tick-in-suspend;
+ interrupt-parent = <&gic>;
+ };
+
+ gic: interrupt-controller@4800 {
+ compatible = "arm,gic-v3";
+ reg = <0 0x4800 0 0x1>,
+ <0 0x4804 0 0xc>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = ;
+ interrupt-parent = <&gic>;
+ };
+
+ soc@0 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x0 0x8000>,
+<0x2800 0x0 0x2800 0x1000>;
+
+ aips1: bus@4400 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ reg = <0x4400 0x80>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ mu1: mailbox@4423 {
+ compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
+ reg = <0x4423 0x1>;
+ interrupts = ;
+ #mbox-cells = <2>;
+ status = "disabled";
+ };
+
+ anomix_ns_gpr: blk-ctrl-anomix@4242 {
+ compatible = "syscon";
+
[PATCH 38/53] ddr: imx9: enable Performance monitor counter
From: Ye Li
Add Kconfig for enabling reference events counter in DDRC performance
monitor by default
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
drivers/ddr/imx/imx9/Kconfig| 6 ++
drivers/ddr/imx/imx9/ddr_init.c | 4
2 files changed, 10 insertions(+)
diff --git a/drivers/ddr/imx/imx9/Kconfig b/drivers/ddr/imx/imx9/Kconfig
index a16ddc65e01..123ad173cfc 100644
--- a/drivers/ddr/imx/imx9/Kconfig
+++ b/drivers/ddr/imx/imx9/Kconfig
@@ -11,6 +11,12 @@ config IMX9_LPDDR4X
help
Select the i.MX9 LPDDR4/4X driver support on i.MX9 SOC.
+config IMX9_DRAM_PM_COUNTER
+ bool "imx9 DDRC performance monitor counter"
+ default y
+ help
+ Enable DDR controller performance monitor counter for reference
events.
+
config SAVED_DRAM_TIMING_BASE
hex "Define the base address for saved dram timing"
help
diff --git a/drivers/ddr/imx/imx9/ddr_init.c b/drivers/ddr/imx/imx9/ddr_init.c
index 16eac65105f..8b8ec7f8de3 100644
--- a/drivers/ddr/imx/imx9/ddr_init.c
+++ b/drivers/ddr/imx/imx9/ddr_init.c
@@ -112,6 +112,10 @@ int ddr_init(struct dram_timing_info *dram_timing)
ddrc_config(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num);
debug("DDRINFO: ddrc config done\n");
+#ifdef CONFIG_IMX9_DRAM_PM_COUNTER
+ writel(0x20, REG_DDR_DEBUG_19);
+#endif
+
check_dfi_init_complete();
regval = readl(REG_DDR_SDRAM_CFG);
--
2.36.0
[PATCH 48/53] board: freescale: imx93_evk: support ethernet
From: Peng Fan
Add ethernet support
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/imx-regs.h | 7 +
board/freescale/imx93_evk/imx93_evk.c | 32 +++
configs/imx93_11x11_evk_defconfig | 9 +++
3 files changed, 48 insertions(+)
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h
b/arch/arm/include/asm/arch-imx9/imx-regs.h
index 049eca4f3a7..f575805c7da 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -7,6 +7,7 @@
#define __ASM_ARCH_IMX9_REGS_H__
#define ARCH_MXC
+#define FEC_QUIRK_ENET_MAC
#define IOMUXC_BASE_ADDR 0x443CUL
#define CCM_BASE_ADDR 0x4445UL
@@ -39,6 +40,12 @@
#define SRC_MIX_SLICE_FUNC_STAT_ISO_STAT BIT(4)
#define SRC_MIX_SLICE_FUNC_STAT_MEM_STAT BIT(12)
+#define BCTRL_GPR_ENET_QOS_INTF_MODE_MASKGENMASK(3, 1)
+#define BCTRL_GPR_ENET_QOS_INTF_SEL_MII (0x0 << 1)
+#define BCTRL_GPR_ENET_QOS_INTF_SEL_RMII (0x4 << 1)
+#define BCTRL_GPR_ENET_QOS_INTF_SEL_RGMII(0x1 << 1)
+#define BCTRL_GPR_ENET_QOS_CLK_GEN_EN(0x1 << 0)
+
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include
#include
diff --git a/board/freescale/imx93_evk/imx93_evk.c
b/board/freescale/imx93_evk/imx93_evk.c
index 77b92b35db4..f111b99fc2e 100644
--- a/board/freescale/imx93_evk/imx93_evk.c
+++ b/board/freescale/imx93_evk/imx93_evk.c
@@ -38,8 +38,40 @@ int board_early_init_f(void)
return 0;
}
+static int setup_fec(void)
+{
+ return set_clk_enet(ENET_125MHZ);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+static int setup_eqos(void)
+{
+ struct blk_ctrl_wakeupmix_regs *bctrl =
+ (struct blk_ctrl_wakeupmix_regs *)BLK_CTRL_WAKEUPMIX_BASE_ADDR;
+
+ /* set INTF as RGMII, enable RGMII TXC clock */
+ clrsetbits_le32(&bctrl->eqos_gpr,
+ BCTRL_GPR_ENET_QOS_INTF_MODE_MASK,
+ BCTRL_GPR_ENET_QOS_INTF_SEL_RGMII |
BCTRL_GPR_ENET_QOS_CLK_GEN_EN);
+
+ return set_clk_eqos(ENET_125MHZ);
+}
+
int board_init(void)
{
+ if (CONFIG_IS_ENABLED(FEC_MXC))
+ setup_fec();
+
+ if (CONFIG_IS_ENABLED(DWC_ETH_QOS))
+ setup_eqos();
+
return 0;
}
diff --git a/configs/imx93_11x11_evk_defconfig
b/configs/imx93_11x11_evk_defconfig
index 8a396ed1c13..1f59f7e365d 100644
--- a/configs/imx93_11x11_evk_defconfig
+++ b/configs/imx93_11x11_evk_defconfig
@@ -75,6 +75,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
@@ -89,6 +90,14 @@ CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_IMX=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX93=y
--
2.36.0
[PATCH 51/53] ddr: imx8m: helper: load ddr firmware according to binman symbols
From: Peng Fan
By reading binman symbols, we no need hard coded IMEM_LEN/DMEM_LEN after
we update the binman dtsi to drop 0x8000/0x4000 length for the firmware.
And that could save binary size for many KBs.
Tested-by: Tim Harvey #imx8m[m,n,p]-venice
Signed-off-by: Peng Fan
Reviewed-by: Alper Nebi Yasak
[Alper: Check BINMAN_SYMS_OK instead]
Signed-off-by: Alper Nebi Yasak
---
drivers/ddr/imx/phy/helper.c | 47 +++-
1 file changed, 41 insertions(+), 6 deletions(-)
diff --git a/drivers/ddr/imx/phy/helper.c b/drivers/ddr/imx/phy/helper.c
index 60d650e3089..e9e0294f87d 100644
--- a/drivers/ddr/imx/phy/helper.c
+++ b/drivers/ddr/imx/phy/helper.c
@@ -4,6 +4,7 @@
*/
#include
+#include
#include
#include
#include
@@ -24,15 +25,30 @@ DECLARE_GLOBAL_DATA_PTR;
#define DMEM_OFFSET_ADDR 0x00054000
#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0)
+binman_sym_declare(ulong, ddr_1d_imem_fw, image_pos);
+binman_sym_declare(ulong, ddr_1d_imem_fw, size);
+
+binman_sym_declare(ulong, ddr_1d_dmem_fw, image_pos);
+binman_sym_declare(ulong, ddr_1d_dmem_fw, size);
+
+#if !IS_ENABLED(CONFIG_IMX8M_DDR3L)
+binman_sym_declare(ulong, ddr_2d_imem_fw, image_pos);
+binman_sym_declare(ulong, ddr_2d_imem_fw, size);
+
+binman_sym_declare(ulong, ddr_2d_dmem_fw, image_pos);
+binman_sym_declare(ulong, ddr_2d_dmem_fw, size);
+#endif
+
/* We need PHY iMEM PHY is 32KB padded */
void ddr_load_train_firmware(enum fw_type type)
{
u32 tmp32, i;
u32 error = 0;
unsigned long pr_to32, pr_from32;
- unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0;
+ uint32_t fw_offset = type ? IMEM_2D_OFFSET : 0;
unsigned long imem_start = (unsigned long)&_end + fw_offset;
unsigned long dmem_start;
+ unsigned long imem_len = IMEM_LEN, dmem_len = DMEM_LEN;
#ifdef CONFIG_SPL_OF_CONTROL
if (gd->fdt_blob && !fdt_check_header(gd->fdt_blob)) {
@@ -42,11 +58,30 @@ void ddr_load_train_firmware(enum fw_type type)
}
#endif
- dmem_start = imem_start + IMEM_LEN;
+ dmem_start = imem_start + imem_len;
+
+ if (BINMAN_SYMS_OK) {
+ switch (type) {
+ case FW_1D_IMAGE:
+ imem_start = binman_sym(ulong, ddr_1d_imem_fw,
image_pos);
+ imem_len = binman_sym(ulong, ddr_1d_imem_fw, size);
+ dmem_start = binman_sym(ulong, ddr_1d_dmem_fw,
image_pos);
+ dmem_len = binman_sym(ulong, ddr_1d_dmem_fw, size);
+ break;
+ case FW_2D_IMAGE:
+#if !IS_ENABLED(CONFIG_IMX8M_DDR3L)
+ imem_start = binman_sym(ulong, ddr_2d_imem_fw,
image_pos);
+ imem_len = binman_sym(ulong, ddr_2d_imem_fw, size);
+ dmem_start = binman_sym(ulong, ddr_2d_dmem_fw,
image_pos);
+ dmem_len = binman_sym(ulong, ddr_2d_dmem_fw, size);
+#endif
+ break;
+ }
+ }
pr_from32 = imem_start;
pr_to32 = IMEM_OFFSET_ADDR;
- for (i = 0x0; i < IMEM_LEN; ) {
+ for (i = 0x0; i < imem_len; ) {
tmp32 = readl(pr_from32);
writew(tmp32 & 0x, DDR_TRAIN_CODE_BASE_ADDR +
ddrphy_addr_remap(pr_to32));
pr_to32 += 1;
@@ -59,7 +94,7 @@ void ddr_load_train_firmware(enum fw_type type)
pr_from32 = dmem_start;
pr_to32 = DMEM_OFFSET_ADDR;
- for (i = 0x0; i < DMEM_LEN; ) {
+ for (i = 0x0; i < dmem_len; ) {
tmp32 = readl(pr_from32);
writew(tmp32 & 0x, DDR_TRAIN_CODE_BASE_ADDR +
ddrphy_addr_remap(pr_to32));
pr_to32 += 1;
@@ -73,7 +108,7 @@ void ddr_load_train_firmware(enum fw_type type)
debug("check ddr_pmu_train_imem code\n");
pr_from32 = imem_start;
pr_to32 = IMEM_OFFSET_ADDR;
- for (i = 0x0; i < IMEM_LEN; ) {
+ for (i = 0x0; i < imem_len; ) {
tmp32 = (readw(DDR_TRAIN_CODE_BASE_ADDR +
ddrphy_addr_remap(pr_to32)) & 0x);
pr_to32 += 1;
tmp32 += ((readw(DDR_TRAIN_CODE_BASE_ADDR +
@@ -95,7 +130,7 @@ void ddr_load_train_firmware(enum fw_type type)
debug("check ddr4_pmu_train_dmem code\n");
pr_from32 = dmem_start;
pr_to32 = DMEM_OFFSET_ADDR;
- for (i = 0x0; i < DMEM_LEN;) {
+ for (i = 0x0; i < dmem_len;) {
tmp32 = (readw(DDR_TRAIN_CODE_BASE_ADDR +
ddrphy_addr_remap(pr_to32)) & 0x);
pr_to32 += 1;
tmp32 += ((readw(DDR_TRAIN_CODE_BASE_ADDR +
--
2.36.0
[PATCH 35/53] imx: imx9: Support multiple env storages at runtime
From: Ye Li
Select env storages according to boot device at runtime
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/soc.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index ca88271564c..797d7a802ba 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -288,6 +288,40 @@ int timer_init(void)
return 0;
}
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+ enum boot_device dev = get_boot_device();
+ enum env_location env_loc = ENVL_UNKNOWN;
+
+ if (prio)
+ return env_loc;
+
+ switch (dev) {
+#if defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+ case QSPI_BOOT:
+ env_loc = ENVL_SPI_FLASH;
+ break;
+#endif
+#if defined(CONFIG_ENV_IS_IN_MMC)
+ case SD1_BOOT:
+ case SD2_BOOT:
+ case SD3_BOOT:
+ case MMC1_BOOT:
+ case MMC2_BOOT:
+ case MMC3_BOOT:
+ env_loc = ENVL_MMC;
+ break;
+#endif
+ default:
+#if defined(CONFIG_ENV_IS_NOWHERE)
+ env_loc = ENVL_NOWHERE;
+#endif
+ break;
+ }
+
+ return env_loc;
+}
+
static int mix_power_init(enum mix_power_domain pd)
{
enum src_mix_slice_id mix_id;
--
2.36.0
[PATCH 43/53] net: dwc_eth_qos: fix build break when CLK not enabled
From: Peng Fan
When CONFIG_CLK is not enabled, there will be buil break:
"error: ‘eqos’ undeclared (first use in this function)"
Take eqos definition out the CONFIG_CLK ifdef.
Signed-off-by: Peng Fan
---
drivers/net/dwc_eth_qos.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 9d255cf95ff..6048d56ff8c 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1774,11 +1774,11 @@ static int eqos_remove_resources_tegra186(struct
udevice *dev)
static int eqos_remove_resources_stm32(struct udevice *dev)
{
-#ifdef CONFIG_CLK
struct eqos_priv *eqos = dev_get_priv(dev);
debug("%s(dev=%p):\n", __func__, dev);
+#ifdef CONFIG_CLK
clk_free(&eqos->clk_tx);
clk_free(&eqos->clk_rx);
clk_free(&eqos->clk_master_bus);
--
2.36.0
[PATCH 41/53] imx: imx93_evk: Set ARM clock to 1.7Ghz
From: Peng Fan
Set ARM clock to OD frequency 1.7Ghz, since we have set PMIC VDD_SOC
to Overdrive voltage 0.9V
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/clock.h | 4 +++-
arch/arm/mach-imx/imx9/clock.c | 9 +
board/freescale/imx93_evk/spl.c| 3 +++
3 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-imx9/clock.h
b/arch/arm/include/asm/arch-imx9/clock.h
index d96f126a1d1..336d8613181 100644
--- a/arch/arm/include/asm/arch-imx9/clock.h
+++ b/arch/arm/include/asm/arch-imx9/clock.h
@@ -217,6 +217,8 @@ void dram_pll_init(ulong pll_val);
void dram_enable_bypass(ulong clk_val);
void dram_disable_bypass(void);
+int configure_intpll(enum ccm_clk_src pll, u32 freq);
+
int ccm_clk_src_on(enum ccm_clk_src oscpll, bool enable);
int ccm_clk_src_auto(enum ccm_clk_src oscpll, bool enable);
int ccm_clk_src_lpm(enum ccm_clk_src oscpll, bool enable);
@@ -238,5 +240,5 @@ int ccm_shared_gpr_tz_access(u32 gpr, bool non_secure, bool
user_mode, bool lock
void enable_usboh3_clk(unsigned char enable);
int set_clk_enet(enum enet_freq type);
int set_clk_eqos(enum enet_freq type);
-
+void set_arm_clk(ulong freq);
#endif
diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c
index 5d2bc0d2f8f..8240afc6172 100644
--- a/arch/arm/mach-imx/imx9/clock.c
+++ b/arch/arm/mach-imx/imx9/clock.c
@@ -665,6 +665,15 @@ void dram_disable_bypass(void)
/* Switch from DRAM clock root from CCM to PLL */
ccm_shared_gpr_set(SHARED_GPR_DRAM_CLK, SHARED_GPR_DRAM_CLK_SEL_PLL);
}
+
+void set_arm_clk(ulong freq)
+{
+ /* Increase ARM clock to 1.7Ghz */
+ ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_CCM);
+ configure_intpll(ARM_PLL_CLK, 17);
+ ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_PLL);
+}
+
#endif
int clock_init(void)
diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c
index ca33f943424..38cfbac6ea6 100644
--- a/board/freescale/imx93_evk/spl.c
+++ b/board/freescale/imx93_evk/spl.c
@@ -108,6 +108,9 @@ void board_init_f(ulong dummy)
}
power_init_board();
+ /* 1.7GHz */
+ set_arm_clk(17);
+
/* Init power of mix */
soc_power_init();
--
2.36.0
[PATCH 44/53] net: dwc_eth_qos: public some functions
From: Peng Fan
Move macros and structures to header file and make some functions
public, so that could used by other files, this is to
prepare split platform specific config to one file.
Signed-off-by: Peng Fan
---
drivers/net/dwc_eth_qos.c | 280 +-
drivers/net/dwc_eth_qos.h | 280 ++
2 files changed, 287 insertions(+), 273 deletions(-)
create mode 100644 drivers/net/dwc_eth_qos.h
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 6048d56ff8c..b69a9feb824 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -51,275 +51,9 @@
#include
#include
#endif
-#include
#include
-/* Core registers */
-
-#define EQOS_MAC_REGS_BASE 0x000
-struct eqos_mac_regs {
- uint32_t configuration; /* 0x000 */
- uint32_t unused_004[(0x070 - 0x004) / 4]; /* 0x004 */
- uint32_t q0_tx_flow_ctrl; /* 0x070 */
- uint32_t unused_070[(0x090 - 0x074) / 4]; /* 0x074 */
- uint32_t rx_flow_ctrl; /* 0x090 */
- uint32_t unused_094;/* 0x094 */
- uint32_t txq_prty_map0; /* 0x098 */
- uint32_t unused_09c;/* 0x09c */
- uint32_t rxq_ctrl0; /* 0x0a0 */
- uint32_t unused_0a4;/* 0x0a4 */
- uint32_t rxq_ctrl2; /* 0x0a8 */
- uint32_t unused_0ac[(0x0dc - 0x0ac) / 4]; /* 0x0ac */
- uint32_t us_tic_counter;/* 0x0dc */
- uint32_t unused_0e0[(0x11c - 0x0e0) / 4]; /* 0x0e0 */
- uint32_t hw_feature0; /* 0x11c */
- uint32_t hw_feature1; /* 0x120 */
- uint32_t hw_feature2; /* 0x124 */
- uint32_t unused_128[(0x200 - 0x128) / 4]; /* 0x128 */
- uint32_t mdio_address; /* 0x200 */
- uint32_t mdio_data; /* 0x204 */
- uint32_t unused_208[(0x300 - 0x208) / 4]; /* 0x208 */
- uint32_t address0_high; /* 0x300 */
- uint32_t address0_low; /* 0x304 */
-};
-
-#define EQOS_MAC_CONFIGURATION_GPSLCE BIT(23)
-#define EQOS_MAC_CONFIGURATION_CST BIT(21)
-#define EQOS_MAC_CONFIGURATION_ACS BIT(20)
-#define EQOS_MAC_CONFIGURATION_WD BIT(19)
-#define EQOS_MAC_CONFIGURATION_JD BIT(17)
-#define EQOS_MAC_CONFIGURATION_JE BIT(16)
-#define EQOS_MAC_CONFIGURATION_PS BIT(15)
-#define EQOS_MAC_CONFIGURATION_FES BIT(14)
-#define EQOS_MAC_CONFIGURATION_DM BIT(13)
-#define EQOS_MAC_CONFIGURATION_LM BIT(12)
-#define EQOS_MAC_CONFIGURATION_TE BIT(1)
-#define EQOS_MAC_CONFIGURATION_RE BIT(0)
-
-#define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16
-#define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_MASK 0x
-#define EQOS_MAC_Q0_TX_FLOW_CTRL_TFE BIT(1)
-
-#define EQOS_MAC_RX_FLOW_CTRL_RFE BIT(0)
-
-#define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT 0
-#define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK 0xff
-
-#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT0
-#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK 3
-#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED 0
-#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2
-#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV 1
-
-#define EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT 0
-#define EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK 0xff
-
-#define EQOS_MAC_HW_FEATURE0_MMCSEL_SHIFT 8
-#define EQOS_MAC_HW_FEATURE0_HDSEL_SHIFT 2
-#define EQOS_MAC_HW_FEATURE0_GMIISEL_SHIFT 1
-#define EQOS_MAC_HW_FEATURE0_MIISEL_SHIFT 0
-
-#define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT 6
-#define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK 0x1f
-#define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT 0
-#define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK 0x1f
-
-#define EQOS_MAC_HW_FEATURE3_ASP_SHIFT 28
-#define EQOS_MAC_HW_FEATURE3_ASP_MASK 0x3
-
-#define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21
-#define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT16
-#define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8
-#define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2
-#define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5
-#define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4)
-#define EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT2
-#define EQOS_MAC_MDIO_ADDRESS_GOC_READ
[PATCH 49/53] tools: image: support i.MX93
From: Peng Fan
Support build i.MX93 container image with mkimage
Signed-off-by: Peng Fan
---
include/imx8image.h | 15 +++--
tools/imx8image.c | 79 +
2 files changed, 78 insertions(+), 16 deletions(-)
diff --git a/include/imx8image.h b/include/imx8image.h
index 00c614ab6cc..32064bfeeb8 100644
--- a/include/imx8image.h
+++ b/include/imx8image.h
@@ -165,6 +165,7 @@ enum imx8image_core_type {
CFG_M40,
CFG_M41,
CFG_A35,
+ CFG_A55,
CFG_A53,
CFG_A72
};
@@ -180,7 +181,9 @@ enum imx8image_fld_types {
typedef enum SOC_TYPE {
NONE = 0,
QX,
- QM
+ QM,
+ ULP,
+ IMX9
} soc_type_t;
typedef enum option_type {
@@ -201,7 +204,9 @@ typedef enum option_type {
DATA,
PARTITION,
FILEOFF,
- MSG_BLOCK
+ MSG_BLOCK,
+ SENTINEL,
+ UPOWER
} option_type_t;
typedef struct {
@@ -221,6 +226,11 @@ typedef struct {
#define CORE_CA72 5
#define CORE_SECO 6
+#define CORE_ULP_CM33 0x1
+#define CORE_ULP_CA35 0x2
+#define CORE_ULP_UPOWER0x4
+#define CORE_ULP_SENTINEL 0x6
+
#define SC_R_OTP 357U
#define SC_R_DEBUG 354U
#define SC_R_ROM_0 236U
@@ -235,6 +245,7 @@ typedef struct {
#define IMG_TYPE_DATA0x04 /* Data image type */
#define IMG_TYPE_DCD_DDR 0x05 /* DCD/DDR image type */
#define IMG_TYPE_SECO0x06 /* SECO image type */
+#define IMG_TYPE_SENTINEL 0x06 /* SENTINEL image type */
#define IMG_TYPE_PROV0x07 /* Provisioning image type */
#define IMG_TYPE_DEK 0x08 /* DEK validation type */
diff --git a/tools/imx8image.c b/tools/imx8image.c
index fa8f2274876..01e14869114 100644
--- a/tools/imx8image.c
+++ b/tools/imx8image.c
@@ -60,6 +60,7 @@ static table_entry_t imx8image_core_entries[] = {
{CFG_M40, "M40", "M4 core 0",},
{CFG_M41, "M41", "M4 core 1",},
{CFG_A35, "A35", "A35 core", },
+ {CFG_A55, "A55", "A55 core", },
{CFG_A53, "A53", "A53 core", },
{CFG_A72, "A72", "A72 core", },
{-1,"", "", },
@@ -117,6 +118,10 @@ static void parse_cfg_cmd(image_t *param_stack, int32_t
cmd, char *token,
soc = QX;
} else if (!strncmp(token, "IMX8QM", 6)) {
soc = QM;
+ } else if (!strncmp(token, "ULP", 3)) {
+ soc = IMX9;
+ } else if (!strncmp(token, "IMX9", 4)) {
+ soc = IMX9;
} else {
fprintf(stderr, "Unknown CMD_SOC_TYPE");
exit(EXIT_FAILURE);
@@ -187,6 +192,7 @@ static void parse_cfg_fld(image_t *param_stack, int32_t
*cmd, char *token,
param_stack[p_idx].filename = token;
break;
case CFG_A35:
+ case CFG_A55:
param_stack[p_idx].ext = CORE_CA35;
param_stack[p_idx].option =
(*cmd == CMD_DATA) ? DATA : AP;
@@ -219,6 +225,7 @@ static void parse_cfg_fld(image_t *param_stack, int32_t
*cmd, char *token,
case CFG_M41:
case CFG_A35:
case CFG_A53:
+ case CFG_A55:
case CFG_A72:
param_stack[p_idx++].entry =
(uint32_t)strtoll(token, NULL, 0);
@@ -548,6 +555,18 @@ static void set_image_array_entry(flash_header_v3_t
*container,
img->dst = 0x20C0;
img->entry = 0x2000;
break;
+ case SENTINEL:
+ if (container->num_images > 0) {
+ fprintf(stderr, "Error: SENTINEL container only allows
1 image\n");
+ return;
+ }
+
+ img->hab_flags |= IMG_TYPE_SENTINEL;
+ img->hab_flags |= CORE_ULP_SENTINEL <<
BOOT_IMG_FLAGS_CORE_SHIFT;
+ tmp_name = "SENTINEL";
+ img->dst = 0xe400; /* S400 IRAM base */
+ img->entry = 0xe400;
+ break;
case AP:
if (soc == QX && core == CORE_CA35) {
meta = IMAGE_A35_DEFAULT_META(custom_partition);
@@ -555,6 +574,8 @@ static void set_image_array_entry(flash_header_v3_t
*container,
meta = IMAGE_A53_DEFAULT_META(custom_partition);
} else if (soc == QM && core == CORE_CA72) {
meta = IMAGE_A72_DEFAULT_META(custom_partition);
+ } else if (((soc == ULP) || (soc == IMX9)) && core ==
CORE_CA35) {
+ meta = 0;
} else {
fprintf(stderr,
[PATCH 46/53] net: eqos: add function to get phy node and address
From: Ye Li
Since new atheros PHY driver needs to access its PHY node through
phy device, we have to assign the phy node in ethernet controller
driver. Otherwise the PHY driver will fail to get some nodes
and properties.
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
drivers/net/dwc_eth_qos.c | 23 ---
drivers/net/dwc_eth_qos.h | 1 +
2 files changed, 21 insertions(+), 3 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 1f24f5cb0cf..a4380d17d9c 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -719,6 +719,24 @@ static int eqos_read_rom_hwaddr(struct udevice *dev)
return !is_valid_ethaddr(pdata->enetaddr);
}
+static int eqos_get_phy_addr(struct eqos_priv *priv, struct udevice *dev)
+{
+ struct ofnode_phandle_args phandle_args;
+ int reg;
+
+ if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
+ &phandle_args)) {
+ debug("Failed to find phy-handle");
+ return -ENODEV;
+ }
+
+ priv->phy_of_node = phandle_args.node;
+
+ reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
+
+ return reg;
+}
+
static int eqos_start(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
@@ -767,9 +785,7 @@ static int eqos_start(struct udevice *dev)
*/
if (!eqos->phy) {
int addr = -1;
-#ifdef CONFIG_DM_ETH_PHY
- addr = eth_phy_get_addr(dev);
-#endif
+ addr = eqos_get_phy_addr(eqos, dev);
#ifdef DWC_NET_PHYADDR
addr = DWC_NET_PHYADDR;
#endif
@@ -788,6 +804,7 @@ static int eqos_start(struct udevice *dev)
}
}
+ eqos->phy->node = eqos->phy_of_node;
ret = phy_config(eqos->phy);
if (ret < 0) {
pr_err("phy_config() failed: %d", ret);
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index ce90e1f1ce1..f470189e8d4 100644
--- a/drivers/net/dwc_eth_qos.h
+++ b/drivers/net/dwc_eth_qos.h
@@ -261,6 +261,7 @@ struct eqos_priv {
struct clk clk_slave_bus;
struct mii_dev *mii;
struct phy_device *phy;
+ ofnode phy_of_node;
u32 max_speed;
void *descs;
int tx_desc_idx, rx_desc_idx;
--
2.36.0
[PATCH 18/53] imx: imx9: support romapi
From: Peng Fan
i.MX9 shares same ROM API with i.MX8ULP, so make the i.MX8ULP the function
prototype common and usable by i.MX9.
Also include mmc env functions that use ROM API.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8ulp/sys_proto.h | 4 --
arch/arm/include/asm/mach-imx/sys_proto.h | 4 ++
arch/arm/mach-imx/imx9/soc.c | 37 +++
3 files changed, 41 insertions(+), 4 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
index 05859dfc2aa..a7869fbb573 100644
--- a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h
@@ -8,10 +8,6 @@
#include
-extern unsigned long rom_pointer[];
-
-ulong spl_romapi_raw_seekable_read(u32 offset, u32 size, void *buf);
-ulong spl_romapi_get_uboot_base(u32 image_offset, u32 rom_bt_dev);
enum bt_mode get_boot_mode(void);
int xrdc_config_pdac(u32 bridge, u32 index, u32 dom, u32 perm);
int xrdc_config_pdac_openacc(u32 bridge, u32 index);
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h
b/arch/arm/include/asm/mach-imx/sys_proto.h
index 05532ebea89..17c5f44b208 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -180,6 +180,10 @@ enum boot_dev_type_e {
#define ROM_API_OKAY 0xF0
extern struct rom_api *g_rom_api;
+extern unsigned long rom_pointer[];
+
+ulong spl_romapi_raw_seekable_read(u32 offset, u32 size, void *buf);
+ulong spl_romapi_get_uboot_base(u32 image_offset, u32 rom_bt_dev);
/* For i.MX ULP */
#define BT0CFG_LPBOOT_MASK 0x1
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 8b620832b5d..9ea2d51495b 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -29,6 +29,43 @@
DECLARE_GLOBAL_DATA_PTR;
+struct rom_api *g_rom_api = (struct rom_api *)0x1980;
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+__weak int board_mmc_get_env_dev(int devno)
+{
+ return devno; }
+
+int mmc_get_env_dev(void)
+{
+ volatile gd_t *pgd = gd;
+ int ret;
+ u32 boot;
+ u16 boot_type;
+ u8 boot_instance;
+
+ ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
+ ((uintptr_t)&boot) ^ QUERY_BT_DEV);
+ set_gd(pgd);
+
+ if (ret != ROM_API_OKAY) {
+ puts("ROMAPI: failure at query_boot_info\n");
+ return CONFIG_SYS_MMC_ENV_DEV;
+ }
+
+ boot_type = boot >> 16;
+ boot_instance = (boot >> 8) & 0xff;
+
+ debug("boot_type %d, instance %d\n", boot_type, boot_instance);
+
+ /* If not boot from sd/mmc, use default value */
+ if (boot_type != BOOT_TYPE_SD && boot_type != BOOT_TYPE_MMC)
+ return env_get_ulong("mmcdev", 10, CONFIG_SYS_MMC_ENV_DEV);
+
+ return board_mmc_get_env_dev(boot_instance);
+}
+#endif
+
u32 get_cpu_rev(void)
{
return (MXC_CPU_IMX93 << 12) | CHIP_REV_1_0;
--
2.36.0
[PATCH 52/53] arm: dts: imx8m: shrink ddr firmware size to actual file size
From: Peng Fan
After we switch to use BINMAN_SYMBOLS, there is no need to pad
the file size to 0x8000 and 0x4000. After we use BINMAN_SYMBOLS,
the u-boot-spl-ddr.bin shrink about 36KB with i.MX8MP-EVK.
Tested-by: Tim Harvey #imx8m[m,n,p]-venice
Signed-off-by: Peng Fan
Reviewed-by: Alper Nebi Yasak
---
arch/arm/dts/imx8mm-u-boot.dtsi | 8
arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi| 8
arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi | 4 ++--
arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 8
arch/arm/dts/imx8mn-evk-u-boot.dtsi | 8
arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi | 8
arch/arm/dts/imx8mn-venice-u-boot.dtsi| 8
arch/arm/dts/imx8mp-u-boot.dtsi | 8
arch/arm/dts/imx8mq-cm-u-boot.dtsi| 8
arch/arm/dts/imx8mq-u-boot.dtsi | 8
10 files changed, 38 insertions(+), 38 deletions(-)
diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi
index 86f8e1a284b..8c48678625d 100644
--- a/arch/arm/dts/imx8mm-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-u-boot.dtsi
@@ -41,25 +41,25 @@
ddr-1d-imem-fw {
filename = "lpddr4_pmu_train_1d_imem.bin";
- size = <0x8000>;
+ align-end = <4>;
type = "blob-ext";
};
ddr-1d-dmem-fw {
filename = "lpddr4_pmu_train_1d_dmem.bin";
- size = <0x4000>;
+ align-end = <4>;
type = "blob-ext";
};
ddr-2d-imem-fw {
filename = "lpddr4_pmu_train_2d_imem.bin";
- size = <0x8000>;
+ align-end = <4>;
type = "blob-ext";
};
ddr-2d-dmem-fw {
filename = "lpddr4_pmu_train_2d_dmem.bin";
- size = <0x4000>;
+ align-end = <4>;
type = "blob-ext";
};
};
diff --git a/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
b/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
index d28bb2b2ffe..5f839524028 100644
--- a/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi
@@ -149,26 +149,26 @@
ddr-1d-imem-fw {
filename = "lpddr4_pmu_train_1d_imem.bin";
- size = <0x8000>;
type = "blob-ext";
+ align-end = <4>;
};
ddr-1d-dmem-fw {
filename = "lpddr4_pmu_train_1d_dmem.bin";
- size = <0x4000>;
type = "blob-ext";
+ align-end = <4>;
};
ddr-2d-imem-fw {
filename = "lpddr4_pmu_train_2d_imem.bin";
- size = <0x8000>;
type = "blob-ext";
+ align-end = <4>;
};
ddr-2d-dmem-fw {
filename = "lpddr4_pmu_train_2d_dmem.bin";
- size = <0x4000>;
type = "blob-ext";
+ align-end = <4>;
};
};
diff --git a/arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
b/arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
index dc4cec250ef..c4ae7ca4f31 100644
--- a/arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
+++ b/arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi
@@ -113,13 +113,13 @@
ddr-1d-imem-fw {
filename = "ddr3_imem_1d.bin";
- size = <0x8000>;
+ align-end = <4>;
type = "blob-ext";
};
ddr-1d-dmem-fw {
filename = "ddr3_dmem_1d.bin";
- size = <0x4000>;
+ align-end = <4>;
type = "blob-ext";
};
};
diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
index 30ef8bc47d9..78773c198e4 100644
--- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
@@ -157,26 +157,26 @@
ddr-1d-imem-fw {
filename = "ddr4_imem_1d_201810.bin";
- size = <0x8000>;
type = "blob-ext";
+ align-end = <4>;
};
ddr-1d-dmem-fw {
filename = "ddr4_dmem_1d_201810.bin";
- size = <0x4000>;
type = "blob-ext";
+ align-end = <4>;
};
ddr-2d-imem-fw {
[PATCH 13/53] imx: imx9: Add CCM and clock API support
From: Peng Fan Add clock API to support CCM root clock and LPCG setting Set the CCM AUTHEN register to allow non-secure world to set root clock and lpcg. Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-imx9/ccm_regs.h | 266 arch/arm/include/asm/arch-imx9/clock.h| 239 +++ arch/arm/include/asm/arch-imx9/imx-regs.h | 6 +- arch/arm/mach-imx/imx9/Makefile | 2 +- arch/arm/mach-imx/imx9/clock.c| 769 +- arch/arm/mach-imx/imx9/clock_root.c | 438 arch/arm/mach-imx/imx9/soc.c | 3 + 7 files changed, 1720 insertions(+), 3 deletions(-) create mode 100644 arch/arm/include/asm/arch-imx9/ccm_regs.h create mode 100644 arch/arm/mach-imx/imx9/clock_root.c diff --git a/arch/arm/include/asm/arch-imx9/ccm_regs.h b/arch/arm/include/asm/arch-imx9/ccm_regs.h new file mode 100644 index 000..d326a6ea516 --- /dev/null +++ b/arch/arm/include/asm/arch-imx9/ccm_regs.h @@ -0,0 +1,266 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 NXP + */ + +#ifndef __ASM_ARCH_IMX9_CCM_REGS_H__ +#define __ASM_ARCH_IMX9_CCM_REGS_H__ +#define IMX93_CLK_ROOT_MAX 95 +#define IMX93_CLK_CCGR_MAX 127 + +#define ARM_A55_PERIPH_CLK_ROOT0 +#define ARM_A55_MTR_BUS_CLK_ROOT 1 +#define ARM_A55_CLK_ROOT 2 +#define M33_CLK_ROOT 3 +#define SENTINEL_CLK_ROOT 4 +#define BUS_WAKEUP_CLK_ROOT5 +#define BUS_AON_CLK_ROOT 6 +#define WAKEUP_AXI_CLK_ROOT7 +#define SWO_TRACE_CLK_ROOT 8 +#define M33_SYSTICK_CLK_ROOT 9 +#define FLEXIO1_CLK_ROOT 10 +#define FLEXIO2_CLK_ROOT 11 +#define LPIT1_CLK_ROOT 12 +#define LPIT2_CLK_ROOT 13 +#define LPTMR1_CLK_ROOT14 +#define LPTMR2_CLK_ROOT15 +#define TPM1_CLK_ROOT 16 +#define TPM2_CLK_ROOT 17 +#define TPM3_CLK_ROOT 18 +#define TPM4_CLK_ROOT 19 +#define TPM5_CLK_ROOT 20 +#define TPM6_CLK_ROOT 21 +#define FLEXSPI1_CLK_ROOT 22 +#define CAN1_CLK_ROOT 23 +#define CAN2_CLK_ROOT 24 +#define LPUART1_CLK_ROOT 25 +#define LPUART2_CLK_ROOT 26 +#define LPUART3_CLK_ROOT 27 +#define LPUART4_CLK_ROOT 28 +#define LPUART5_CLK_ROOT 29 +#define LPUART6_CLK_ROOT 30 +#define LPUART7_CLK_ROOT 31 +#define LPUART8_CLK_ROOT 32 +#define LPI2C1_CLK_ROOT33 +#define LPI2C2_CLK_ROOT34 +#define LPI2C3_CLK_ROOT35 +#define LPI2C4_CLK_ROOT36 +#define LPI2C5_CLK_ROOT37 +#define LPI2C6_CLK_ROOT38 +#define LPI2C7_CLK_ROOT39 +#define LPI2C8_CLK_ROOT40 +#define LPSPI1_CLK_ROOT41 +#define LPSPI2_CLK_ROOT42 +#define LPSPI3_CLK_ROOT43 +#define LPSPI4_CLK_ROOT44 +#define LPSPI5_CLK_ROOT45 +#define LPSPI6_CLK_ROOT46 +#define LPSPI7_CLK_ROOT47 +#define LPSPI8_CLK_ROOT48 +#define I3C1_CLK_ROOT 49 +#define I3C2_CLK_ROOT 50 +#define USDHC1_CLK_ROOT51 +#define USDHC2_CLK_ROOT52 +#define USDHC3_CLK_ROOT53 +#define SAI1_CLK_ROOT 54 +#define SAI2_CLK_ROOT 55 +#define SAI3_CLK_ROOT 56 +#define CCM_CKO1_CLK_ROOT 57 +#define CCM_CKO2_CLK_ROOT 58 +#define CCM_CKO3_CLK_ROOT 59 +#define CCM_CKO4_CLK_ROOT 60 +#define HSIO_CLK_ROOT 61 +#define HSIO_USB_TEST_60M_CLK_ROOT 62 +#define HSIO_ACSCAN_80M_CLK_ROOT 63 +#define HSIO_ACSCAN_480M_CLK_ROOT 64 +#define NIC_CLK_ROOT 65 +#define NIC_APB_CLK_ROOT 66 +#define ML_APB_CLK_ROOT67 +#define ML_CLK_ROOT68 +#define MEDIA_AXI_CLK_ROOT 69 +#define MEDIA_APB_CLK_ROOT 70 +#define MEDIA_LDB_CLK_ROOT 71 +#define MEDIA_DISP_PIX_CLK_ROOT72 +#define CAM_PIX_CLK_ROOT 73 +#define MIPI_TEST_BYTE_CLK_ROOT74 +#define MIPI_PHY_CFG_CLK_ROOT 75 +#define DRAM_ALT_CLK_ROOT 76 +#define DRAM_APB_CLK_ROOT 77 +#define ADC_CLK_ROOT 78 +#define PDM_CLK_ROOT 79 +#define TSTMR1_CLK_ROOT80 +#define TSTMR2_CLK_ROOT81 +#define MQS1_CLK_ROOT
[PATCH 08/53] imx: add USB2_BOOT type
From: Peng Fan
Add USB2_BOOT type for i.MX8ULP and i.MX9
Signed-off-by: Peng Fan
---
arch/arm/include/asm/mach-imx/boot_mode.h | 1 +
arch/arm/mach-imx/imx_romapi.c| 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/mach-imx/boot_mode.h
b/arch/arm/include/asm/mach-imx/boot_mode.h
index 6dc58559680..a568c443722 100644
--- a/arch/arm/include/asm/mach-imx/boot_mode.h
+++ b/arch/arm/include/asm/mach-imx/boot_mode.h
@@ -29,6 +29,7 @@ enum boot_device {
QSPI_BOOT,
FLEXSPI_BOOT,
USB_BOOT,
+ USB2_BOOT,
UNKNOWN_BOOT,
BOOT_DEV_NUM = UNKNOWN_BOOT,
};
diff --git a/arch/arm/mach-imx/imx_romapi.c b/arch/arm/mach-imx/imx_romapi.c
index 3b2cc6935dc..0f94091fc53 100644
--- a/arch/arm/mach-imx/imx_romapi.c
+++ b/arch/arm/mach-imx/imx_romapi.c
@@ -50,7 +50,7 @@ enum boot_device get_boot_device(void)
boot_dev = QSPI_BOOT;
break;
case BT_DEV_TYPE_USB:
- boot_dev = USB_BOOT;
+ boot_dev = boot_instance + USB_BOOT;
break;
default:
break;
--
2.36.0
[PATCH 53/53] imx: imx8mm-icore: migrate to use BINMAN
From: Peng Fan Use BINMAN instead of imx specific packing method. Signed-off-by: Peng Fan Reviewed-by: Alper Nebi Yasak --- arch/arm/mach-imx/imx8m/Kconfig | 1 + arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg | 10 +- configs/imx8mm-icore-mx8mm-ctouch2_defconfig| 2 +- configs/imx8mm-icore-mx8mm-edimm2.2_defconfig | 2 +- 4 files changed, 4 insertions(+), 11 deletions(-) diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 09b9d5603d0..979b30ae39c 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -69,6 +69,7 @@ config TARGET_IMX8MM_EVK config TARGET_IMX8MM_ICORE_MX8MM bool "Engicam i.Core MX8M Mini SOM" + select BINMAN select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 diff --git a/arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg b/arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg index e06d53ef417..5dcb8ae72f0 100644 --- a/arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg +++ b/arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg @@ -3,13 +3,5 @@ * Copyright 2019 NXP */ - -FIT BOOT_FROM sd -LOADER spl/u-boot-spl-ddr.bin 0x7E1000 -SECOND_LOADER u-boot.itb 0x4020 0x6 - -DDR_FW lpddr4_pmu_train_1d_imem.bin -DDR_FW lpddr4_pmu_train_1d_dmem.bin -DDR_FW lpddr4_pmu_train_2d_imem.bin -DDR_FW lpddr4_pmu_train_2d_dmem.bin +LOADER u-boot-spl-ddr.bin 0x7E1000 diff --git a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig index b9fb3c69cb7..cb1a8d45da5 100644 --- a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig +++ b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig @@ -20,7 +20,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +# CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_SYSTEM_SETUP=y CONFIG_DEFAULT_FDT_FILE="imx8mm-icore-mx8mm-ctouch2.dtb" CONFIG_SPL_HAS_BSS_LINKER_SECTION=y diff --git a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig index 1149bb68c04..a6482b65a6e 100644 --- a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig +++ b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig @@ -20,7 +20,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +# CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_SYSTEM_SETUP=y CONFIG_DEFAULT_FDT_FILE="imx8mm-icore-mx8mm-edimm2.2.dtb" CONFIG_SPL_HAS_BSS_LINKER_SECTION=y -- 2.36.0
[PATCH 40/53] imx: imx93_evk: Add basic board support
From: Peng Fan
Add basic board codes and defconfig for i.MX93 11x11 EVK board.
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/dts/Makefile |3 +
arch/arm/dts/imx93-11x11-evk-u-boot.dtsi | 157 +++
arch/arm/dts/imx93-11x11-evk.dts | 527 +++
arch/arm/mach-imx/imx9/Kconfig | 12 +
board/freescale/common/Makefile|2 +-
board/freescale/imx93_evk/Kconfig | 19 +
board/freescale/imx93_evk/MAINTAINERS |6 +
board/freescale/imx93_evk/Makefile | 12 +
board/freescale/imx93_evk/imx93_evk.c | 58 +
board/freescale/imx93_evk/lpddr4x_timing.c | 1486
board/freescale/imx93_evk/spl.c| 126 ++
configs/imx93_11x11_evk_defconfig | 108 ++
include/configs/imx93_evk.h| 145 ++
13 files changed, 2660 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/imx93-11x11-evk-u-boot.dtsi
create mode 100644 arch/arm/dts/imx93-11x11-evk.dts
create mode 100644 board/freescale/imx93_evk/Kconfig
create mode 100644 board/freescale/imx93_evk/MAINTAINERS
create mode 100644 board/freescale/imx93_evk/Makefile
create mode 100644 board/freescale/imx93_evk/imx93_evk.c
create mode 100644 board/freescale/imx93_evk/lpddr4x_timing.c
create mode 100644 board/freescale/imx93_evk/spl.c
create mode 100644 configs/imx93_11x11_evk_defconfig
create mode 100644 include/configs/imx93_evk.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 66c719908cd..1f0bb221d88 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -971,6 +971,9 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mq-pico-pi.dtb \
imx8mq-kontron-pitx-imx8m.dtb
+dtb-$(CONFIG_ARCH_IMX9) += \
+ imx93-11x11-evk.dtb
+
dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
imxrt1020-evk.dtb
diff --git a/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi
b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi
new file mode 100644
index 000..6f02b389893
--- /dev/null
+++ b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ */
+
+/ {
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog3>;
+ u-boot,dm-spl;
+ };
+
+ aliases {
+ usbgadget0 = &usbg1;
+ usbgadget1 = &usbg2;
+ };
+
+ usbg1: usbg1 {
+ compatible = "fsl,imx27-usb-gadget";
+ dr_mode = "peripheral";
+ chipidea,usb = <&usbotg1>;
+ status = "okay";
+ };
+
+ usbg2: usbg2 {
+ compatible = "fsl,imx27-usb-gadget";
+ dr_mode = "peripheral";
+ chipidea,usb = <&usbotg2>;
+ status = "okay";
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+};
+
+&{/soc@0} {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+&aips1 {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&aips2 {
+ u-boot,dm-spl;
+};
+
+&aips3 {
+ u-boot,dm-spl;
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+};
+
+®_usdhc2_vmmc {
+ u-boot,off-on-delay-us = <2>;
+ u-boot,dm-spl;
+};
+
+&pinctrl_reg_usdhc2_vmmc {
+ u-boot,dm-spl;
+};
+
+&pinctrl_uart1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_gpio {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&lpuart1 {
+ u-boot,dm-spl;
+};
+
+&usdhc1 {
+ u-boot,dm-spl;
+};
+
+&usdhc2 {
+ u-boot,dm-spl;
+ fsl,signal-voltage-switch-extra-delay-ms = <8>;
+};
+
+&lpi2c2 {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@4400/i2c@4435/pmic@25} {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@4400/i2c@4435/pmic@25/regulators} {
+ u-boot,dm-spl;
+};
+
+&pinctrl_lpi2c2 {
+ u-boot,dm-spl;
+};
+
+&fec {
+ phy-reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <15>;
+ phy-reset-post-delay = <100>;
+};
+
+&eqos {
+ compatible = "fsl,imx-eqos";
+};
+
+ðphy1 {
+ reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <15000>;
+ reset-deassert-us = <10>;
+};
+
+&usbotg1 {
+ status = "okay";
+ extcon = <&ptn5110>;
+};
+
+&usbotg2 {
+ status = "okay";
+ extcon = <&ptn5110_2>;
+};
+
+&s4muap {
+ u-boot,dm-spl;
+ status = "okay";
+};
diff --git a/arch/arm/dts/imx93-11x11-evk.dts b/arch/arm/dts/imx93-11x11-evk.dts
new file mode 100644
index 000..b3a5a3d71e2
--- /dev/null
+++ b/arch/arm/dts/imx93-11x11-evk.dts
@@ -0,0 +1,527 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021 NXP
+ */
+
+/dts-v1/;
+
+#include "
Re: [RESEND v9 7/9] bootmenu: add removable media entries
Hi Kojima-san
[...]
> +
> + /* add non-existent boot option */
> + for (i = 0; i < count; i++) {
> + u32 boot_index;
> + u16 var_name[9];
> +
> + if (!opt[i].exist) {
> + ret = eficonfig_get_unused_bootoption(var_name,
> sizeof(var_name),
> + &boot_index);
> + if (ret != EFI_SUCCESS)
> + goto out;
> +
> + ret = efi_set_variable_int(var_name,
> &efi_global_variable_guid,
> + EFI_VARIABLE_NON_VOLATILE |
> +
> EFI_VARIABLE_BOOTSERVICE_ACCESS |
> +
> EFI_VARIABLE_RUNTIME_ACCESS,
> + opt[i].size, opt[i].lo,
> false);
> + if (ret != EFI_SUCCESS)
> + goto out;
> +
> + ret = eficonfig_append_bootorder(boot_index);
> + if (ret != EFI_SUCCESS)
> + goto out;
> + }
Should we got through the trouble on removing the variable we just added?
[...]
>
> diff --git a/cmd/eficonfig.c b/cmd/eficonfig.c
> index 51d4e36a54..564ddd02c1 100644
> --- a/cmd/eficonfig.c
> +++ b/cmd/eficonfig.c
> @@ -1786,6 +1786,131 @@ static efi_status_t
> eficonfig_process_delete_boot_option(void *data)
> return ret;
> }
>
> +efi_status_t eficonfig_enumerate_boot_option(struct
> eficonfig_media_boot_option *opt,
> +efi_handle_t *volume_handles,
> efi_status_t count)
> +{
> + u32 i;
> + struct efi_handler *handler;
> + efi_status_t ret = EFI_SUCCESS;
> +
> + for (i = 0; i < count; i++) {
> + char *optional_data;
> + u16 *dev_name, *p;
> + struct efi_load_option lo;
> + char buf[BOOTMENU_DEVICE_NAME_MAX];
> + struct efi_device_path *device_path;
> +
> + ret = efi_search_protocol(volume_handles[i],
> &efi_guid_device_path, &handler);
> + if (ret != EFI_SUCCESS)
> + continue;
> + ret = efi_protocol_open(handler, (void **)&device_path,
> + efi_root, NULL,
> EFI_OPEN_PROTOCOL_GET_PROTOCOL);
> + if (ret != EFI_SUCCESS)
> + continue;
> +
> + ret = efi_disk_get_device_name(volume_handles[i], buf,
> BOOTMENU_DEVICE_NAME_MAX);
> + if (ret != EFI_SUCCESS)
> + continue;
> +
> + dev_name = calloc(1, (strlen(buf) + 1) * sizeof(u16));
> + if (!dev_name) {
> + ret = EFI_OUT_OF_RESOURCES;
> + goto out;
> + }
Just allocate an array in the stack
> + p = dev_name;
> + utf8_utf16_strncpy(&p, buf, strlen(buf));
> +
> + lo.label = dev_name;
> + lo.attributes = LOAD_OPTION_ACTIVE;
> + lo.file_path = device_path;
> + lo.file_path_length = efi_dp_size(device_path) + sizeof(END);
> + /*
> +* Set the dedicated guid to optional_data, it is used to
> identify
> +* the boot option that automatically generated by the
> bootmenu.
> +* efi_serialize_load_option() expects optional_data is
> null-terminated
> +* utf8 string, so set the "1234567" string to allocate
> enough space
[...]
Thanks
/Ilias
Re: [PATCH v5 19/23] FWU: synquacer: Add FWU Multi bank update support for DeveloperBox
On Wed, Jul 20, 2022 at 2:54 AM Ilias Apalodimas
wrote:
>
> Hi Jassi,
>
> On Tue, 19 Jul 2022 at 18:27, Jassi Brar wrote:
> >
> > On Mon, 18 Jul 2022 at 16:00, Tom Rini wrote:
> > > On Mon, Jul 18, 2022 at 10:31:56AM -0500, Jassi Brar wrote:
> >
> > > > > > > >
> > > > > > > > > > +
> > > > > > > > > > +#define PLAT_METADATA_OFFSET 0x51
> > > > > > > > > > +#define PLAT_METADATA_SIZE (sizeof(struct
> > > > > > > > > > devbox_metadata))
> > > > > > > > > > +
> > > > > > > > > > +struct __packed devbox_metadata {
> > > > > > > > > > + u32 boot_index;
> > > > > > > > > > + u32 boot_count;
> > > > > > > > >
> > > > > > > > > There is the whole bootcount infrastructure for this. I think
> > > > > > > > > it would be much
> > > > > > > > > better to use that framework instead of creating parallel one.
> > > > > > > > >
> > > > > > > > Yes, this goes too.
> > > > > > >
> > > > > > > Is bootcount really suited for this case?
> > > > > > > AFAIK bootcount either requires device specific registers (which
> > > > > > > won't
> > > > > > > reset on reboots), or an environment you can write data to.
> > > > > > > But what if a user wants to disable writing the env variables and
> > > > > > > the
> > > > > > > device doesn't have a set of registers we can use?
> > > > > > >
> > > > > > Maybe it should be moved in 'struct fwu_mdata' ?
> > > > >
> > > > > I was mostly thinking on moving this count as another 'bootcount'
> > > > > method. So in case the user has disabled writing evn variables but he
> > > > > is booting with EFI he can use that.
> > > >
> > > > Sorry, not sure I understand IIUIC there has to be some persistent
> > > > storage.
> > >
> > > No, there just has to be "somewhere" to do the counting. We've got a
> > > DDR backed driver, for example. So yes, I think we should try and use
> > > the bootcount framework here.
> > >
> > OK, for platforms that can preserve ram across reboot, using
> > non-persistent storage can work.
> > My platform neither preserves ram, nor has any warmreset-proof
> > registers. So I have to choose between saving the bootcount in efi-env
> > or in vendor specific structure next to the metadata. I prefer
> > metadata because it is common to all stages of boot. Any corrections
> > to this approach?
>
> The metadata is defined by a spec and they don't have a field for
> bootcounting. Once Sughosh resends his patches he'll include a
> bootcount backend that reuses EFI variables. Can't we just use that?
>
Yes, I am aware metadata spec has no provision of vendor data. But
there is nothing illegal in appending vendor-data to metadata and that
is trivial to implement ... basically use sizeof(struct fwu_mdata) +
sizeof(struct sni_vendor_mdata) while read/write meta-data. That will
also be zero extra-overhead.
fwu-mdata {
compatible = "u-boot,fwu-mdata-mtd";
fwu-mdata-store = <&spi_flash>;
mdata-offsets = <0x50 0x53>;
vendor-data-size = <0x100>; // optional
};
Sure we can use an efi variable, but I see more uses of vendor-data
:- shared among BL1/BL2/BL3x/OS so we can emulate reset-syndrome,
crash-logging, per-image bootcount etc when the h/w doesn't support
these features.
Ofcourse, please feel free to implement efi-variables still.
thanks.
Error: unrecognized opcode on riscv64
Attempting to compile the latest master code for qemu (virt) and the unmatched shows the following error: arch/riscv/cpu/cpu.c: Assembler messages: arch/riscv/cpu/cpu.c:96: Error: unrecognized opcode `csrs sstatus,a5' arch/riscv/cpu/cpu.c:97: Error: unrecognized opcode `csrw 0x003,0' Any ideas on what's going on? Toolchain: riscv64-linux-gnu-gcc - gcc version 12.1.0 (GCC) riscv64-linux-gnu-as - GNU assembler (GNU Binutils) 2.36.1 Compiling on ArchLinux -- Alex
[PATCH v3 0/3] Support various block interfaces for avb and bcb
Hello. Originally bcb and avb utilities implementation relay on mmc block devices. This patch series adds an optional interface parameter to those utilities, which gives the ability to use bcb and avb on various block devices. The patch set was tested using xenguest_arm64 based board and pvblock interface. Changes for v3: - Added RB and ACK - Added patch #3 by the request Changes for v2: - Removed patch #3 as not actual for mainline Andrii Chepurnyi (3): cmd: bcb: introduce optional interface parameter to bcb cmd: avb: introduce optional interface parameter to avb init cmd: avb: remove mmc naming from generic block code cmd/avb.c| 13 +++- cmd/bcb.c| 65 ++--- common/avb_verify.c | 76 doc/android/avb2.rst | 2 +- doc/android/bcb.rst | 33 ++- include/avb_verify.h | 24 +- 6 files changed, 107 insertions(+), 106 deletions(-) -- 2.25.1
[PATCH v3 1/3] cmd: bcb: introduce optional interface parameter to bcb
From: Andrii Chepurnyi
From: Andrii Chepurnyi
Originally, bcb implementation relay on mmc block devices.
The interface parameter will give the ability to use bcb with
various block devices by choosing the exact interface type.
By default (if no interface parameter is provided) mmc interface
will be used.
Reviewed-by: Igor Opaniuk
Signed-off-by: Andrii Chepurnyi
---
cmd/bcb.c | 65 +++--
doc/android/bcb.rst | 33 ---
2 files changed, 51 insertions(+), 47 deletions(-)
diff --git a/cmd/bcb.c b/cmd/bcb.c
index 92f4d27990..bfe395558e 100644
--- a/cmd/bcb.c
+++ b/cmd/bcb.c
@@ -26,6 +26,7 @@ enum bcb_cmd {
static int bcb_dev = -1;
static int bcb_part = -1;
static struct bootloader_message bcb __aligned(ARCH_DMA_MINALIGN) = { { 0 } };
+static struct blk_desc *bcb_blk_desc;
static int bcb_cmd_get(char *cmd)
{
@@ -51,6 +52,9 @@ static int bcb_is_misused(int argc, char *const argv[])
switch (cmd) {
case BCB_CMD_LOAD:
+ if (argc != 3 && argc != 4)
+ goto err;
+ break;
case BCB_CMD_FIELD_SET:
if (argc != 3)
goto err;
@@ -115,25 +119,23 @@ static int bcb_field_get(char *name, char **fieldp, int
*sizep)
static int __bcb_load(int devnum, const char *partp)
{
- struct blk_desc *desc;
struct disk_partition info;
u64 cnt;
char *endp;
int part, ret;
- desc = blk_get_devnum_by_type(IF_TYPE_MMC, devnum);
- if (!desc) {
+ if (!bcb_blk_desc) {
ret = -ENODEV;
goto err_read_fail;
}
part = simple_strtoul(partp, &endp, 0);
if (*endp == '\0') {
- ret = part_get_info(desc, part, &info);
+ ret = part_get_info(bcb_blk_desc, part, &info);
if (ret)
goto err_read_fail;
} else {
- part = part_get_info_by_name(desc, partp, &info);
+ part = part_get_info_by_name(bcb_blk_desc, partp, &info);
if (part < 0) {
ret = part;
goto err_read_fail;
@@ -144,12 +146,12 @@ static int __bcb_load(int devnum, const char *partp)
if (cnt > info.size)
goto err_too_small;
- if (blk_dread(desc, info.start, cnt, &bcb) != cnt) {
+ if (blk_dread(bcb_blk_desc, info.start, cnt, &bcb) != cnt) {
ret = -EIO;
goto err_read_fail;
}
- bcb_dev = desc->devnum;
+ bcb_dev = bcb_blk_desc->devnum;
bcb_part = part;
debug("%s: Loaded from mmc %d:%d\n", __func__, bcb_dev, bcb_part);
@@ -170,15 +172,15 @@ err:
static int do_bcb_load(struct cmd_tbl *cmdtp, int flag, int argc,
char * const argv[])
{
- char *endp;
- int devnum = simple_strtoul(argv[1], &endp, 0);
+ int ret = blk_get_device_by_str((argv[3]) ? argv[3] : "mmc", argv[1],
&bcb_blk_desc);
- if (*endp != '\0') {
- printf("Error: Device id '%s' not a number\n", argv[1]);
+ if (ret < 0) {
+ printf("Error: Device id '%s' or interface '%s' is not
valid\n", argv[1],
+ (argv[3]) ? argv[3] : "mmc");
return CMD_RET_FAILURE;
}
- return __bcb_load(devnum, argv[2]);
+ return __bcb_load(bcb_blk_desc->devnum, argv[2]);
}
static int __bcb_set(char *fieldp, const char *valp)
@@ -281,24 +283,22 @@ static int do_bcb_dump(struct cmd_tbl *cmdtp, int flag,
int argc,
static int __bcb_store(void)
{
- struct blk_desc *desc;
struct disk_partition info;
u64 cnt;
int ret;
- desc = blk_get_devnum_by_type(IF_TYPE_MMC, bcb_dev);
- if (!desc) {
+ if (!bcb_blk_desc) {
ret = -ENODEV;
goto err;
}
- ret = part_get_info(desc, bcb_part, &info);
+ ret = part_get_info(bcb_blk_desc, bcb_part, &info);
if (ret)
goto err;
cnt = DIV_ROUND_UP(sizeof(struct bootloader_message), info.blksz);
- if (blk_dwrite(desc, info.start, cnt, &bcb) != cnt) {
+ if (blk_dwrite(bcb_blk_desc, info.start, cnt, &bcb) != cnt) {
ret = -EIO;
goto err;
}
@@ -373,21 +373,22 @@ static int do_bcb(struct cmd_tbl *cmdtp, int flag, int
argc, char *const argv[])
U_BOOT_CMD(
bcb, CONFIG_SYS_MAXARGS, 1, do_bcb,
"Load/set/clear/test/dump/store Android BCB fields",
- "load - load BCB from mmc :\n"
- "bcb set - set BCB to \n"
- "bcb clear [] - clear BCB or all fields\n"
- "bcb test - test BCB against \n"
- "bcb dump - dump BCB \n"
- "bcb store- store BCB back to mmc\n"
+ "load[] - load BCB from
:[]\n"
+ "bcb set- set
[PATCH v2] Improve Windows build documentation
I have recently build the u-boot tools on Windows and ran into difficulties. This patch to the documentation would have avoided those difficulties. Contentious points: * While I have run the document through a rst previewer, I haven't run the full test suite. I know, I know, everyone thinks _they_ don't need to run the tests because reasons, but I think it's true this time. * I have removed the version numbers from the list of packages. I don't think they are helpful, and are just maintenance overhead. (I don't think I got those versions for example). I'd be grateful if @Bin Meng could review this, because `git blame` says the file I am changing is all his. No actual changes, but hopefully closer to the required formalities: Signed-off-by: Martin Bonner commit e3615603d919ab19fddbee4a68e8a37b91a75f3e (HEAD -> better-windows-build-doc) Author: Martin Bonner Date: Tue Jul 5 09:10:59 2022 +0100 Tweak docs for building tools on Windows * Add three more modules that are required. * Remove the version numbers (because they are hard to keep in sync) * Add a pacman command line to install everything. diff --git a/doc/build/tools.rst b/doc/build/tools.rst index c06f915274..95f1246617 100644 --- a/doc/build/tools.rst +++ b/doc/build/tools.rst @@ -24,14 +24,20 @@ you can use MSYS2, a software distro and building platform for Windows. Download the MSYS2 installer from https://www.msys2.org. Make sure you have installed all required packages below in order to build these host tools:: - * gcc (9.1.0) - * make (4.2.1) - * bison (3.4.2) - * diffutils (3.7) - * openssl-devel (1.1.1.d) - -Note the version numbers in these parentheses above are the package versions -at the time being when writing this document. The MSYS2 installer tested is + * gcc + * make + * bison + * diffutils + * openssl-devel + * flex + * libgnutls-devel + * libuuid-devel + +You probably want ``git`` as well. You can install all these with:: + +$ pacman -S gcc make bison diffutils openssl=devel flex libgnutls-devel libuuid-devel git + +The MSYS2 installer tested is http://repo.msys2.org/distrib/x86_64/msys2-x86_64-20190524.exe. There are 3 MSYS subsystems installed: MSYS2, MinGW32 and MinGW64. Each -- Martin
[PATCH v3 2/3] cmd: avb: introduce optional interface parameter to avb init
From: Andrii Chepurnyi
From: Andrii Chepurnyi
Originally, avb implementation relay on mmc block devices.
The interface parameter will give the ability to use avb with
various block devices by choosing the exact interface type.
By default (if no interface parameter is provided) mmc interface
will be used.
Acked-by: Igor Opaniuk
Signed-off-by: Andrii Chepurnyi
---
cmd/avb.c| 13 +
common/avb_verify.c | 28 ++--
doc/android/avb2.rst | 2 +-
include/avb_verify.h | 11 ++-
4 files changed, 26 insertions(+), 28 deletions(-)
diff --git a/cmd/avb.c b/cmd/avb.c
index 783f51b816..6fdbdc708f 100644
--- a/cmd/avb.c
+++ b/cmd/avb.c
@@ -17,17 +17,14 @@ static struct AvbOps *avb_ops;
int do_avb_init(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
- unsigned long mmc_dev;
-
- if (argc != 2)
+ if (argc != 2 && argc != 3)
return CMD_RET_USAGE;
- mmc_dev = hextoul(argv[1], NULL);
-
if (avb_ops)
avb_ops_free(avb_ops);
- avb_ops = avb_ops_alloc(mmc_dev);
+ avb_ops = avb_ops_alloc(argv[1], (argc == 3) ? argv[2] : "mmc");
+
if (avb_ops)
return CMD_RET_SUCCESS;
@@ -419,7 +416,7 @@ int do_avb_write_pvalue(struct cmd_tbl *cmdtp, int flag,
int argc,
}
static struct cmd_tbl cmd_avb[] = {
- U_BOOT_CMD_MKENT(init, 2, 0, do_avb_init, "", ""),
+ U_BOOT_CMD_MKENT(init, 3, 0, do_avb_init, "", ""),
U_BOOT_CMD_MKENT(read_rb, 2, 0, do_avb_read_rb, "", ""),
U_BOOT_CMD_MKENT(write_rb, 3, 0, do_avb_write_rb, "", ""),
U_BOOT_CMD_MKENT(is_unlocked, 1, 0, do_avb_is_unlocked, "", ""),
@@ -455,7 +452,7 @@ static int do_avb(struct cmd_tbl *cmdtp, int flag, int
argc, char *const argv[])
U_BOOT_CMD(
avb, 29, 0, do_avb,
"Provides commands for testing Android Verified Boot 2.0 functionality",
- "init - initialize avb2 for \n"
+ "init [] - initialize avb2 for []\n"
"avb read_rb - read rollback index at location \n"
"avb write_rb - write rollback index to \n"
"avb is_unlocked - returns unlock status of the device\n"
diff --git a/common/avb_verify.c b/common/avb_verify.c
index 0520a71455..e086dc6760 100644
--- a/common/avb_verify.c
+++ b/common/avb_verify.c
@@ -338,7 +338,6 @@ static struct mmc_part *get_partition(AvbOps *ops, const
char *partition)
{
int ret;
u8 dev_num;
- int part_num = 0;
struct mmc_part *part;
struct blk_desc *mmc_blk;
@@ -347,22 +346,8 @@ static struct mmc_part *get_partition(AvbOps *ops, const
char *partition)
return NULL;
dev_num = get_boot_device(ops);
- part->mmc = find_mmc_device(dev_num);
- if (!part->mmc) {
- printf("No MMC device at slot %x\n", dev_num);
- goto err;
- }
-
- if (mmc_init(part->mmc)) {
- printf("MMC initialization failed\n");
- goto err;
- }
+ mmc_blk = get_blk(ops);
- ret = mmc_switch_part(part->mmc, part_num);
- if (ret)
- goto err;
-
- mmc_blk = mmc_get_blk_desc(part->mmc);
if (!mmc_blk) {
printf("Error - failed to obtain block descriptor\n");
goto err;
@@ -976,7 +961,8 @@ free_name:
* AVB2.0 AvbOps alloc/initialisation/free
*
*/
-AvbOps *avb_ops_alloc(int boot_device)
+
+AvbOps *avb_ops_alloc(const char *boot_device, const char *interface)
{
struct AvbOpsData *ops_data;
@@ -999,7 +985,13 @@ AvbOps *avb_ops_alloc(int boot_device)
ops_data->ops.read_persistent_value = read_persistent_value;
#endif
ops_data->ops.get_size_of_partition = get_size_of_partition;
- ops_data->mmc_dev = boot_device;
+ ops_data->mmc_dev = simple_strtoul(boot_device, NULL, 16);
+ ops_data->blk = NULL;
+ if (interface && (blk_get_device_by_str(interface, boot_device,
&ops_data->blk) < 0)) {
+ printf("Error - failed to obtain block descriptor for devce=%s
if=%s\n",
+ boot_device, interface);
+ return NULL;
+ }
return &ops_data->ops;
}
diff --git a/doc/android/avb2.rst b/doc/android/avb2.rst
index a072119574..8fa54338fd 100644
--- a/doc/android/avb2.rst
+++ b/doc/android/avb2.rst
@@ -38,7 +38,7 @@ AVB 2.0 U-Boot shell commands
Provides CLI interface to invoke AVB 2.0 verification + misc. commands for
different testing purposes::
-avb init - initialize avb 2.0 for
+avb init [] - initialize avb2 for []
avb verify - run verification process using hash data from vbmeta structure
avb read_rb - read rollback index at location
avb write_rb - write rollback index to
diff --git a/include/avb_verify.h b/include/avb_verify.h
index 1e787ba666..ff70cb26f8 100644
--- a/include/avb_verify.h
+++ b/inc
[PATCH v3 3/3] cmd: avb: remove mmc naming from generic block code
From: Andrii Chepurnyi
From: Andrii Chepurnyi
Part of avb code uses mmc notation, but in fact
it uses generic block functions.
Signed-off-by: Andrii Chepurnyi
---
common/avb_verify.c | 52 ++--
include/avb_verify.h | 13 +--
2 files changed, 32 insertions(+), 33 deletions(-)
diff --git a/common/avb_verify.c b/common/avb_verify.c
index e086dc6760..3c9594d6d7 100644
--- a/common/avb_verify.c
+++ b/common/avb_verify.c
@@ -253,10 +253,10 @@ char *avb_set_enforce_verity(const char *cmdline)
/**
*
- * IO(mmc) auxiliary functions
+ * IO auxiliary functions
*
*/
-static unsigned long mmc_read_and_flush(struct mmc_part *part,
+static unsigned long blk_read_and_flush(struct blk_part *part,
lbaint_t start,
lbaint_t sectors,
void *buffer)
@@ -291,7 +291,7 @@ static unsigned long mmc_read_and_flush(struct mmc_part
*part,
tmp_buf = buffer;
}
- blks = blk_dread(part->mmc_blk,
+ blks = blk_dread(part->blk,
start, sectors, tmp_buf);
/* flush cache after read */
flush_cache((ulong)tmp_buf, sectors * part->info.blksz);
@@ -302,7 +302,7 @@ static unsigned long mmc_read_and_flush(struct mmc_part
*part,
return blks;
}
-static unsigned long mmc_write(struct mmc_part *part, lbaint_t start,
+static unsigned long blk_write(struct blk_part *part, lbaint_t start,
lbaint_t sectors, void *buffer)
{
void *tmp_buf;
@@ -330,37 +330,37 @@ static unsigned long mmc_write(struct mmc_part *part,
lbaint_t start,
tmp_buf = buffer;
}
- return blk_dwrite(part->mmc_blk,
+ return blk_dwrite(part->blk,
start, sectors, tmp_buf);
}
-static struct mmc_part *get_partition(AvbOps *ops, const char *partition)
+static struct blk_part *get_partition(AvbOps *ops, const char *partition)
{
int ret;
u8 dev_num;
- struct mmc_part *part;
- struct blk_desc *mmc_blk;
+ struct blk_part *part;
+ struct blk_desc *blk;
- part = malloc(sizeof(struct mmc_part));
+ part = malloc(sizeof(struct blk_part));
if (!part)
return NULL;
dev_num = get_boot_device(ops);
- mmc_blk = get_blk(ops);
+ blk = get_blk(ops);
- if (!mmc_blk) {
+ if (!blk) {
printf("Error - failed to obtain block descriptor\n");
goto err;
}
- ret = part_get_info_by_name(mmc_blk, partition, &part->info);
+ ret = part_get_info_by_name(blk, partition, &part->info);
if (ret < 0) {
printf("Can't find partition '%s'\n", partition);
goto err;
}
part->dev_num = dev_num;
- part->mmc_blk = mmc_blk;
+ part->blk = blk;
return part;
err:
@@ -368,16 +368,16 @@ err:
return NULL;
}
-static AvbIOResult mmc_byte_io(AvbOps *ops,
+static AvbIOResult blk_byte_io(AvbOps *ops,
const char *partition,
s64 offset,
size_t num_bytes,
void *buffer,
size_t *out_num_read,
- enum mmc_io_type io_type)
+ enum io_type io_type)
{
ulong ret;
- struct mmc_part *part;
+ struct blk_part *part;
u64 start_offset, start_sector, sectors, residue;
u8 *tmp_buf;
size_t io_cnt = 0;
@@ -410,7 +410,7 @@ static AvbIOResult mmc_byte_io(AvbOps *ops,
}
if (io_type == IO_READ) {
- ret = mmc_read_and_flush(part,
+ ret = blk_read_and_flush(part,
part->info.start +
start_sector,
1, tmp_buf);
@@ -427,7 +427,7 @@ static AvbIOResult mmc_byte_io(AvbOps *ops,
tmp_buf += (start_offset % part->info.blksz);
memcpy(buffer, (void *)tmp_buf, residue);
} else {
- ret = mmc_read_and_flush(part,
+ ret = blk_read_and_flush(part,
part->info.start +
start_sector,
1, tmp_buf);
@@ -441,7 +441,7 @@ static AvbIOResult mmc_byte_io(AvbOps *ops,
Re: Reading GPIOs with DM_GPIO before device tree is loaded
Hi Hugo,
On Wed, 20 Jul 2022 at 04:54, Hugo Villeneuve wrote:
>
> Hi,
> in board_early_init_f(), i call a custom function get_som_revision() to read
> some GPIOs that are used to determine the SOM revision. This function
> basically sets the iomux, and then uses
> gpio_request/gpio_direction_input/gpio_get_value functions to read the GPIOs.
> Then, this SOM revision information is used in board_fit_config_name_match()
> to decide which device tree to load.
>
> This works perfectly fine without CONFIG_DM_GPIO. However, if I enable
> CONFIG_DM_GPIO, it doesn't work anymore. There is an error when calling
> gpio_request().
>
> What is the correct way to read GPIOs BEFORE any device tree is loaded?
>
> My board uses an MX6Q SOM.
>
> Here is part of the code I am using:
>
>
> static iomux_v3_cfg_t const boardcfg_pads[] = {
> MX6_PAD_DISP0_DAT15__GPIO5_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
> MX6_PAD_DISP0_DAT8__GPIO4_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
> MX6_PAD_DISP0_DAT0__GPIO4_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
> MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
> MX6_PAD_ENET_RXD1__GPIO1_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL),
> };
>
> static int som_revision = -1;
>
> static const int boardcfg_gpio[] = {
> IMX_GPIO_NR(5, 9),
> IMX_GPIO_NR(4, 29),
> IMX_GPIO_NR(4, 21),
> IMX_GPIO_NR(1, 27),
> IMX_GPIO_NR(1, 26),
> };
>
> static void get_som_revision(void)
> {
> int i;
> int rc;
>
> som_revision = 0;
>
> SETUP_IOMUX_PADS(boardcfg_pads);
>
> for (i = 0; i < ARRAY_SIZE(boardcfg_gpio); ++i) {
> int v;
>
> rc = gpio_request(boardcfg_gpio[i], "som-revision-gpio");
> if (rc) {
> printf("%s(): gpio request %d failed\n", __func__, i);
> som_revision = -1;
> return;
> }
>
> gpio_direction_input(boardcfg_gpio[i]);
> v = gpio_get_value(boardcfg_gpio[i]);
>
> if ((v == 0) || (v == 1))
> som_revision |= v << i;
> else {
> som_revision = -1;
> return;
> }
> }
> }
>
> int board_early_init_f(void)
> {
> setup_iomux_uart();
> get_som_revision();
>
> return 0;
> }
>
>
Well driver model needs the device tree to init, for example DM_GPIO
cannot operate without one unless you are hacking around with
platdata, which is a bit of a pain.
One option you might have is to use a general DT before relocation,
then figure out which one you really want to use and select that for
post relocation. That works better with driver model.
Regards,
Simon
Re: [PATCH] Provide more details of exactly how configuration signatures are calculated
Hi Martin,
On Wed, 20 Jul 2022 at 02:46, Martin Bonner wrote:
>
> OK. I've just realized there is an important warning missing from
> this (if you verify a configuration signature outside u-boot, you
> _must_ verify the hashes for the kernel, fdt, and ramdisk images match
> too). What is the protocol for handling that? Submit a new patch
> with title "[Patch v2] ..."?
Yes when the images are loaded, the hash for each is verified. If that
is not done then you can change the images.
Yes you can do a v2 patch. See patman.
>
> I will hold off submitting that in case there are other comments that
> need to be addressed.
>
> Martin
>
> On Wed, 20 Jul 2022 at 08:23, Martin Bonner wrote:
> >
> > There are a couple of uncertainties still remaining:
> > - The "hashed-nodes" property is created by mkimage in image order.
> > What happens if somebody manipulates a signed image to change the
> > order? Does it make any difference? Do u-boot and fit_check_sign
If the wrong nodes are hashed then the signature will not match. If
you change it deliberately, then you still need to get the signature
right, which you cannot do without the private key.
For the order, it should not matter as I believe the fdt_region code
works through the DT in sequential order.
> > handle it in the same way? (My preference would be that both fail the
> > signature on the grounds that there is no good reason for the nodes to
> > be out of order, and it suggests an attacker is trying to be clever.)
You could perhaps get the offsets of the paths and check that they are
in increasing order of offset.
> > - What happens if the image contains a DTB_NOP tag? Is it included or
> > not? (Again, I would fail the signature if it does.)
It should be included if the properties of that node are included by default.
> >
> > Martin
> >
> > On Wed, 20 Jul 2022 at 08:14, Martin Bonner
> > wrote:
> > >
> > > I have just spent a week reverse-engineering this, so I thought I'd
> > > contribute the work back to the community
> > >
> > > diff --git a/doc/uImage.FIT/signature.txt b/doc/uImage.FIT/signature.txt
> > > index 61a72db3c7..61cdd55e40 100644
> > > --- a/doc/uImage.FIT/signature.txt
> > > +++ b/doc/uImage.FIT/signature.txt
> > > @@ -382,6 +382,25 @@ verified later even if the FIT has been signed
> > > with other keys in the
> > > meantime.
> > >
> > >
> > > +Details
> > > +---
> > > +The signature node contains a property ('hashed-nodes') which lists all
> > > the
> > > +nodes that the signature was made over. The image is walked in order
> > > and each
> > > +tag processed as follows:
> > > +- DTB_BEGIN_NODE: The tag and the following name are added to the
> > > signature if
> > > + the node or its parent are present in 'hashed-nodes'
> > > +- DTB_END_NODE: The tag is added to the signature if the node or its
> > > parent are
> > > + present in 'hashed-nodes'
> > > +- DTB_PROPERTY: The tag, the length word, the offset in the string
> > > table, and
> > > + the data are all included if the node is present in 'hashed-nodes' and
> > > the
> > > + property name is not 'data'.
> > > +- DTB_END: The tag is always included.
> > > +
> > > +In addition, the signature contains a property 'hashed-strings' which
> > > contains
> > > +the offset and length in the string table of the strings that are to be
> > > added
> > > +to the signature (this is always done at the end).
There is an fdtgrep tool which actually shows you what is going on.
You can use the -A and -a options, for example, along with the same
settings that the signature code is using.
See also here:
https://static.googleusercontent.com/media/research.google.com/en//pubs/archive/42038.pdf
(the slide on signing configurations, there is a video too)
> > > +
> > > +
> > > Verification
> > >
> > > FITs are verified when loaded. After the configuration is selected a list
> > >
Regards,
Simon
Re: [PATCH] console: Add option to keep it silent until env is loaded
Hi Harald, On Mon, 18 Jul 2022 at 09:08, Harald Seiler wrote: > > Hi Simon, > > On Wed, 2022-07-13 at 09:28 -0600, Simon Glass wrote: > > Hi Harald, > > > > On Tue, 12 Jul 2022 at 05:58, Harald Seiler wrote: > > > > > > Hi Simon, > > > > > > On Tue, 2022-07-12 at 04:58 -0600, Simon Glass wrote: > > > > Hi Harald, > > > > > > > > On Wed, 6 Jul 2022 at 05:19, Harald Seiler wrote: > > > > > > > > > > Add a config-option which forces the console to stay silent until the > > > > > proper environment is loaded from flash. > > > > > > > > > > This is important when the default environment does not silence the > > > > > console but no output must be printed when 'silent' is set in the > > > > > flash > > > > > environment. > > > > > > > > > > After the environment from flash is loaded, the console will be > > > > > silenced/unsilenced depending on it. If PRE_CONSOLE_BUFFER is also > > > > > used, the buffer will now be flushed if the console should not be > > > > > silenced. > > > > > > > > > > Signed-off-by: Harald Seiler > > > > > --- > > > > > common/Kconfig | 10 ++ > > > > > common/console.c | 5 + > > > > > 2 files changed, 15 insertions(+) > > > > > > > > This seems OK to me. You might want to implement the silent-console > > > > device tree property in console_update_silent() too, which was dropped > > > > in the conversion to driver model. > > > > > > This looks interesting, I'll have to look into it. > > > > > > Do you know if there's any effort towards supporting such a flag in the > > > kernel as well? I had to remove the serial console property from my DT > > > and instead pass console info via cmdline to make the silent console > > > work. A "pure DT" solution of any sort would have been nicer of > > > course... > > > > The console's 'silent' flag is propagated to Linux by dropping the > > 'console=' text from the bootargs. See fixup_silent_linux(). > > Right, this is what I am relying on right now. The problem is that this > does not have any effect when `console=` is not used and the console is > instead passed using the `/chosen/stdout-path` DT property. OK. > > I was wondering whether U-Boot should maybe delete this property from > the DT passed to Linux when going silent... Yes it probably should! > > (But of course this is unrelated to the original patch here) Regards, Simon
