Re: [PATCH 01/11] virtio_ring: Merge identical variables
On 3/31/22 12:09, Andrew Scull wrote:
The variables `total_sg` and `descs_used` have the same value. Replace
the few uses of `total_sg` with `descs_used` to simplify the situation.
Signed-off-by: Andrew Scull
Reviewed-by: Heinrich Schuchardt
---
drivers/virtio/virtio_ring.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c
index 7f1cbc5932..a6922ce1b8 100644
--- a/drivers/virtio/virtio_ring.c
+++ b/drivers/virtio/virtio_ring.c
@@ -20,17 +20,16 @@ int virtqueue_add(struct virtqueue *vq, struct virtio_sg
*sgs[],
unsigned int out_sgs, unsigned int in_sgs)
{
struct vring_desc *desc;
- unsigned int total_sg = out_sgs + in_sgs;
- unsigned int i, n, avail, descs_used, uninitialized_var(prev);
+ unsigned int descs_used = out_sgs + in_sgs;
+ unsigned int i, n, avail, uninitialized_var(prev);
int head;
- WARN_ON(total_sg == 0);
+ WARN_ON(descs_used == 0);
head = vq->free_head;
desc = vq->vring.desc;
i = head;
- descs_used = total_sg;
if (vq->num_free < descs_used) {
debug("Can't add buf len %i - avail = %i\n",
[PATCH v2 04/52] mips: octeon: Add cvmx-lbk-defs.h header file
From: Aaron Williams
Import cvmx-lbk-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support networking on the MIPS Octeon II /
III platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
.../mach-octeon/include/mach/cvmx-lbk-defs.h | 157 ++
1 file changed, 157 insertions(+)
create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-lbk-defs.h
diff --git a/arch/mips/mach-octeon/include/mach/cvmx-lbk-defs.h
b/arch/mips/mach-octeon/include/mach/cvmx-lbk-defs.h
new file mode 100644
index ..1068a19ad80b
--- /dev/null
+++ b/arch/mips/mach-octeon/include/mach/cvmx-lbk-defs.h
@@ -0,0 +1,157 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018-2022 Marvell International Ltd.
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon lbk.
+ */
+
+#ifndef __CVMX_LBK_DEFS_H__
+#define __CVMX_LBK_DEFS_H__
+
+#define CVMX_LBK_BIST_RESULT (0x000118001220ull)
+#define CVMX_LBK_CHX_PKIND(offset) (0x0001180012000200ull + ((offset) & 63) *
8)
+#define CVMX_LBK_CLK_GATE_CTL (0x000118001208ull)
+#define CVMX_LBK_DAT_ERR_INFO (0x000118001250ull)
+#define CVMX_LBK_ECC_CFG (0x000118001260ull)
+#define CVMX_LBK_INT (0x000118001240ull)
+#define CVMX_LBK_SFT_RST (0x000118001200ull)
+
+/**
+ * cvmx_lbk_bist_result
+ *
+ * This register provides access to the internal BIST results. Each bit is the
+ * BIST result of an individual memory (per bit, 0 = pass and 1 = fail).
+ */
+union cvmx_lbk_bist_result {
+ u64 u64;
+ struct cvmx_lbk_bist_result_s {
+ u64 reserved_1_63 : 63;
+ u64 dat : 1;
+ } s;
+ struct cvmx_lbk_bist_result_s cn73xx;
+ struct cvmx_lbk_bist_result_s cn78xx;
+ struct cvmx_lbk_bist_result_s cn78xxp1;
+ struct cvmx_lbk_bist_result_s cnf75xx;
+};
+
+typedef union cvmx_lbk_bist_result cvmx_lbk_bist_result_t;
+
+/**
+ * cvmx_lbk_ch#_pkind
+ */
+union cvmx_lbk_chx_pkind {
+ u64 u64;
+ struct cvmx_lbk_chx_pkind_s {
+ u64 reserved_6_63 : 58;
+ u64 pkind : 6;
+ } s;
+ struct cvmx_lbk_chx_pkind_s cn73xx;
+ struct cvmx_lbk_chx_pkind_s cn78xx;
+ struct cvmx_lbk_chx_pkind_s cn78xxp1;
+ struct cvmx_lbk_chx_pkind_s cnf75xx;
+};
+
+typedef union cvmx_lbk_chx_pkind cvmx_lbk_chx_pkind_t;
+
+/**
+ * cvmx_lbk_clk_gate_ctl
+ *
+ * This register is for diagnostic use only.
+ *
+ */
+union cvmx_lbk_clk_gate_ctl {
+ u64 u64;
+ struct cvmx_lbk_clk_gate_ctl_s {
+ u64 reserved_1_63 : 63;
+ u64 dis : 1;
+ } s;
+ struct cvmx_lbk_clk_gate_ctl_s cn73xx;
+ struct cvmx_lbk_clk_gate_ctl_s cn78xx;
+ struct cvmx_lbk_clk_gate_ctl_s cn78xxp1;
+ struct cvmx_lbk_clk_gate_ctl_s cnf75xx;
+};
+
+typedef union cvmx_lbk_clk_gate_ctl cvmx_lbk_clk_gate_ctl_t;
+
+/**
+ * cvmx_lbk_dat_err_info
+ */
+union cvmx_lbk_dat_err_info {
+ u64 u64;
+ struct cvmx_lbk_dat_err_info_s {
+ u64 reserved_58_63 : 6;
+ u64 dbe_ecc_out : 9;
+ u64 dbe_synd : 9;
+ u64 dbe_addr : 8;
+ u64 reserved_26_31 : 6;
+ u64 sbe_ecc_out : 9;
+ u64 sbe_synd : 9;
+ u64 sbe_addr : 8;
+ } s;
+ struct cvmx_lbk_dat_err_info_s cn73xx;
+ struct cvmx_lbk_dat_err_info_s cn78xx;
+ struct cvmx_lbk_dat_err_info_s cn78xxp1;
+ struct cvmx_lbk_dat_err_info_s cnf75xx;
+};
+
+typedef union cvmx_lbk_dat_err_info cvmx_lbk_dat_err_info_t;
+
+/**
+ * cvmx_lbk_ecc_cfg
+ */
+union cvmx_lbk_ecc_cfg {
+ u64 u64;
+ struct cvmx_lbk_ecc_cfg_s {
+ u64 reserved_3_63 : 61;
+ u64 dat_flip : 2;
+ u64 dat_cdis : 1;
+ } s;
+ struct cvmx_lbk_ecc_cfg_s cn73xx;
+ struct cvmx_lbk_ecc_cfg_s cn78xx;
+ struct cvmx_lbk_ecc_cfg_s cn78xxp1;
+ struct cvmx_lbk_ecc_cfg_s cnf75xx;
+};
+
+typedef union cvmx_lbk_ecc_cfg cvmx_lbk_ecc_cfg_t;
+
+/**
+ * cvmx_lbk_int
+ */
+union cvmx_lbk_int {
+ u64 u64;
+ struct cvmx_lbk_int_s {
+ u64 reserved_6_63 : 58;
+ u64 chan_oflow : 1;
+ u64 chan_uflow : 1;
+ u64 dat_oflow : 1;
+ u64 dat_uflow : 1;
+ u64 dat_dbe : 1;
+ u64 dat_sbe : 1;
+ } s;
+ struct cvmx_lbk_int_s cn73xx;
+ struct cvmx_lbk_int_s cn78xx;
+ struct cvmx_lbk_int_s cn78xxp1;
+ struct cvmx_lbk_int_s cnf75xx;
+};
+
+typedef union cvmx_lbk_int cvmx_lbk_int_t;
+
+/**
+ * cvmx_lbk_sft_rst
+ */
+union cvmx_lbk_sft_rst {
+ u64 u64;
+ struct cvmx_lbk_sft_rst_s {
+ u64 reserved_1_63 : 63;
+ u64 reset : 1;
+ } s;
+ struct cvmx_lbk_sft_rst_s cn73xx;
+ struct cvmx_lbk_sft_rst_s cn78xx;
+ struct cvmx_lbk_sft_rst_s cn78xxp1;
+
[PATCH v2 00/52] mips: octeon: Add ethernet support
This patchset adds the networking files and drivers including device helper headers and C files. Please excuse the massive amount of files in this patch series. Also the sometimes huge files (mostly headers with register definitions) that I needed to include. The infrastructure code with all the headers is ported mistly without any intended functional changes from the 2013 Cavium / Marvell U-Boot version. It has undergone many hours of extensive code cleanup and reformatting. Some of it done by using tools (checkpatch, Lindent, clang format etc) and also some of it done manually, as I couldn't find some tools that could do the needed work in a reliable and functional way. The result is that checkpatch now only throws a "few" warnings that are left. Some of those can't be removed without an even more extensive cleanup / rewrite of the code, like the addition of typedefs. The added header, helper and infrastructure files in the first part of the patch-series (patches 1-43) are the foundation, that is used by the main Octeon U-Boot ethernet driver (patch 50/52). Patches 47-49 add the DT nodes and properties to the corresponding dtsi / dts files. Patches 51 & 52 finally enable the ethernet support both MIPS Octeon boards, EBB7304 & NIC23. All this is tested on the 2 Cavium / Marvell MIPS Octeon boards: EBB7304 & NIC23 This patchset including the small Marvell PHY patches is available in this gitlab branch: https://source.denx.de/u-boot/custodians/u-boot-marvell/-/tree/mips-octeon-ethernet-v2-2022-04-07 Changes in v2: - As suggested by Daniel, remove all unreferenced functions from the source code by manually inspecting u-boot.map [1] - Rebased on latest TOT [1] Here the diffstat comarison between v1 and v2: v1: 77 files changed, 42315 insertions(+), 586 deletions(-) v2: 78 files changed, 33672 insertions(+), 2524 deletions(-) Thanks, Stefan Aaron Williams (40): mips: octeon: Add misc cvmx-* header files mips: octeon: Add cvmx-ilk-defs.h header file mips: octeon: Add cvmx-iob-defs.h header file mips: octeon: Add cvmx-lbk-defs.h header file mips: octeon: Add cvmx-npei-defs.h header file mips: octeon: Add cvmx-pcsxx-defs.h header file mips: octeon: Add cvmx-xcv-defs.h header file mips: octeon: Add cvmx-helper-agl.c mips: octeon: Add cvmx-helper-bgx.c mips: octeon: Add cvmx-helper-board.c mips: octeon: Add cvmx-helper-fpa.c mips: octeon: Add cvmx-helper-ilk.c mips: octeon: Add cvmx-helper-ipd.c mips: octeon: Add cvmx-helper-loop.c mips: octeon: Add cvmx-helper-npi.c mips: octeon: Add cvmx-helper-pki.c mips: octeon: Add cvmx-helper-pko.c mips: octeon: Add cvmx-helper-pko3.c mips: octeon: Add cvmx-helper-rgmii.c mips: octeon: Add cvmx-helper-sgmii.c mips: octeon: Add cvmx-helper-sfp.c mips: octeon: Add cvmx-helper-xaui.c mips: octeon: Add cvmx-agl.c mips: octeon: Add cvmx-cmd-queue.c mips: octeon: Add cvmx-fau-compat.c mips: octeon: Add cvmx-fpa.c mips: octeon: Add cvmx-fpa-resource.c mips: octeon: Add cvmx-global-resource.c mips: octeon: Add cvmx-ilk.c mips: octeon: Add cvmx-ipd.c mips: octeon: Add cvmx-pki.c mips: octeon: Add cvmx-pki-resources.c mips: octeon: Add cvmx-pko.c mips: octeon: Add cvmx-pko3.c mips: octeon: Add cvmx-pko3-queue.c mips: octeon: Add cvmx-pko3-compat.c mips: octeon: Add cvmx-pko3-resources.c mips: octeon: Add cvmx-pko-internal-ports-range.c mips: octeon: Add cvmx-qlm-tables.c mips: octeon: Add cvmx-range.c Stefan Roese (12): mips: octeon: Misc changes to existing headers for upcoming eth support mips: octeon: Misc changes to existing C files for upcoming eth support mips: octeon: Makefile: Enable building of the newly added C files mips: octeon: cpu.c: Move bootmem init to arch_early_init_r() mips: octeon: cpu.c: Implement configure_lmtdma_window() mips: octeon: octeon_common.h: Move init SP because of increased image size mips: octeon: mrvl,cn73xx.dtsi: Add ethernet (BGX) and SMI DT nodes mips: octeon: mrvl,octeon-ebb7304.dts: Add ethernet DT support mips: octeon: mrvl,octeon-nic23.dts: Add ethernet DT support net: Add ethernet support for MIPS Octeon mips: octeon: ebb7304: Enable ethernet support mips: octeon: nic23: Enable ethernet support arch/mips/Kconfig |1 + arch/mips/dts/mrvl,cn73xx.dtsi| 35 + arch/mips/dts/mrvl,octeon-ebb7304.dts | 45 + arch/mips/dts/mrvl,octeon-nic23.dts | 238 ++ arch/mips/mach-octeon/Makefile| 35 +- arch/mips/mach-octeon/cpu.c | 47 +- arch/mips/mach-octeon/cvmx-agl.c | 216 + arch/mips/mach-octeon/cvmx-bootmem.c |3 +- arch/mips/mach-octeon/cvmx-cmd-queue.c| 355 ++ arch/mips/mach-octeon/cvmx-fau-compat.c | 53 + arch/mips/mach-octeon/cvmx-fpa-resource.c | 219 + arch/mips/mach-octeon/cvmx-fpa.c | 1127 ++ arch/mips/mach-octeon/cvmx-global-resources.c | 5
[PATCH v2 07/52] mips: octeon: Add cvmx-xcv-defs.h header file
From: Aaron Williams
Import cvmx-xcv-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support networking on the MIPS Octeon II /
III platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
.../mach-octeon/include/mach/cvmx-xcv-defs.h | 226 ++
1 file changed, 226 insertions(+)
create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-xcv-defs.h
diff --git a/arch/mips/mach-octeon/include/mach/cvmx-xcv-defs.h
b/arch/mips/mach-octeon/include/mach/cvmx-xcv-defs.h
new file mode 100644
index ..4fd4d163eae1
--- /dev/null
+++ b/arch/mips/mach-octeon/include/mach/cvmx-xcv-defs.h
@@ -0,0 +1,226 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018-2022 Marvell International Ltd.
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon xcv.
+ */
+
+#ifndef __CVMX_XCV_DEFS_H__
+#define __CVMX_XCV_DEFS_H__
+
+#define CVMX_XCV_BATCH_CRD_RET (0x00011800DB000100ull)
+#define CVMX_XCV_COMP_CTL (0x00011800DB20ull)
+#define CVMX_XCV_CTL (0x00011800DB30ull)
+#define CVMX_XCV_DLL_CTL (0x00011800DB10ull)
+#define CVMX_XCV_ECO (0x00011800DB000200ull)
+#define CVMX_XCV_INBND_STATUS (0x00011800DB80ull)
+#define CVMX_XCV_INT (0x00011800DB40ull)
+#define CVMX_XCV_RESET(0x00011800DB00ull)
+
+/**
+ * cvmx_xcv_batch_crd_ret
+ */
+union cvmx_xcv_batch_crd_ret {
+ u64 u64;
+ struct cvmx_xcv_batch_crd_ret_s {
+ u64 reserved_1_63 : 63;
+ u64 crd_ret : 1;
+ } s;
+ struct cvmx_xcv_batch_crd_ret_s cn73xx;
+};
+
+typedef union cvmx_xcv_batch_crd_ret cvmx_xcv_batch_crd_ret_t;
+
+/**
+ * cvmx_xcv_comp_ctl
+ *
+ * This register controls programmable compensation.
+ *
+ */
+union cvmx_xcv_comp_ctl {
+ u64 u64;
+ struct cvmx_xcv_comp_ctl_s {
+ u64 drv_byp : 1;
+ u64 reserved_61_62 : 2;
+ u64 cmp_pctl : 5;
+ u64 reserved_53_55 : 3;
+ u64 cmp_nctl : 5;
+ u64 reserved_45_47 : 3;
+ u64 drv_pctl : 5;
+ u64 reserved_37_39 : 3;
+ u64 drv_nctl : 5;
+ u64 reserved_31_31 : 1;
+ u64 pctl_lock : 1;
+ u64 pctl_sat : 1;
+ u64 reserved_28_28 : 1;
+ u64 nctl_lock : 1;
+ u64 reserved_1_26 : 26;
+ u64 nctl_sat : 1;
+ } s;
+ struct cvmx_xcv_comp_ctl_s cn73xx;
+};
+
+typedef union cvmx_xcv_comp_ctl cvmx_xcv_comp_ctl_t;
+
+/**
+ * cvmx_xcv_ctl
+ *
+ * This register contains the status control bits.
+ *
+ */
+union cvmx_xcv_ctl {
+ u64 u64;
+ struct cvmx_xcv_ctl_s {
+ u64 reserved_4_63 : 60;
+ u64 lpbk_ext : 1;
+ u64 lpbk_int : 1;
+ u64 speed : 2;
+ } s;
+ struct cvmx_xcv_ctl_s cn73xx;
+};
+
+typedef union cvmx_xcv_ctl cvmx_xcv_ctl_t;
+
+/**
+ * cvmx_xcv_dll_ctl
+ *
+ * The RGMII timing specification requires that devices transmit clock and
+ * data synchronously. The specification requires external sources (namely
+ * the PC board trace routes) to introduce the appropriate 1.5 to 2.0 ns of
+ * delay.
+ *
+ * To eliminate the need for the PC board delays, the RGMII interface has
optional
+ * on-board DLLs for both transmit and receive. For correct operation, at most
one
+ * of the transmitter, board, or receiver involved in an RGMII link should
+ * introduce delay. By default/reset, the RGMII receivers delay the received
clock,
+ * and the RGMII transmitters do not delay the transmitted clock. Whether this
+ * default works as-is with a given link partner depends on the behavior of the
+ * link partner and the PC board.
+ *
+ * These are the possible modes of RGMII receive operation:
+ *
+ * * XCV_DLL_CTL[CLKRX_BYP] = 0 (reset value) - The RGMII
+ * receive interface introduces clock delay using its internal DLL.
+ * This mode is appropriate if neither the remote
+ * transmitter nor the PC board delays the clock.
+ *
+ * * XCV_DLL_CTL[CLKRX_BYP] = 1, [CLKRX_SET] = 0x0 - The
+ * RGMII receive interface introduces no clock delay. This mode
+ * is appropriate if either the remote transmitter or the PC board
+ * delays the clock.
+ *
+ * These are the possible modes of RGMII transmit operation:
+ *
+ * * XCV_DLL_CTL[CLKTX_BYP] = 1, [CLKTX_SET] = 0x0 (reset value) -
+ * The RGMII transmit interface introduces no clock
+ * delay. This mode is appropriate is either the remote receiver
+ * or the PC board delays the clock.
+ *
+ * * XCV_DLL_CTL[CLKTX_BYP] = 0 - The RGMII transmit
+ * interface introduces clock delay using its internal DLL.
+ * This mode is appropriate if neither the remote receiver
+ * nor the PC board delays the clock.
+ */
+union cvmx_xcv_dll_ctl {
+ u64 u64;
+ struct cvmx_xcv_dll_ctl_s {
+ u64 reserved_32_63 : 32;
+ u64 lock : 1;
+ u
[PATCH v2 08/52] mips: octeon: Misc changes to existing headers for upcoming eth support
This patch includes misc changes to already present Octeon MIPS header
files, which are necessary for the upcoming ethernet support.
The changes are mostly:
- DM GPIO & I2C infrastructure
- Coding style cleanup while reworking the headers
Signed-off-by: Stefan Roese
---
.../mach-octeon/include/mach/cvmx-bootmem.h | 3 +-
arch/mips/mach-octeon/include/mach/cvmx-fpa.h | 3 +-
.../mips/mach-octeon/include/mach/cvmx-fpa3.h | 37 ---
.../include/mach/cvmx-helper-board.h | 6 +-
.../include/mach/cvmx-helper-fdt.h| 40 +++
.../include/mach/cvmx-helper-pko.h| 2 +-
.../mach-octeon/include/mach/cvmx-helper.h| 20
.../mips/mach-octeon/include/mach/cvmx-regs.h | 100 --
.../mach-octeon/include/mach/octeon_eth.h | 54 +-
9 files changed, 166 insertions(+), 99 deletions(-)
diff --git a/arch/mips/mach-octeon/include/mach/cvmx-bootmem.h
b/arch/mips/mach-octeon/include/mach/cvmx-bootmem.h
index 283ac5c6bb56..d5c004d017ef 100644
--- a/arch/mips/mach-octeon/include/mach/cvmx-bootmem.h
+++ b/arch/mips/mach-octeon/include/mach/cvmx-bootmem.h
@@ -26,7 +26,8 @@
/* Real physical addresses of memory regions */
#define OCTEON_DDR0_BASE(0x0ULL)
-#define OCTEON_DDR0_SIZE(0x01000ULL)
+/* Use 16MiB here, as 256 leads to overwriting U-Boot reloc space */
+#define OCTEON_DDR0_SIZE(0x00100ULL)
#define OCTEON_DDR1_BASE((OCTEON_IS_OCTEON2() || OCTEON_IS_OCTEON3()) \
? 0x2000ULL : 0x41000ULL)
#define OCTEON_DDR1_SIZE(0x01000ULL)
diff --git a/arch/mips/mach-octeon/include/mach/cvmx-fpa.h
b/arch/mips/mach-octeon/include/mach/cvmx-fpa.h
index aa238a885072..0660c31b4f59 100644
--- a/arch/mips/mach-octeon/include/mach/cvmx-fpa.h
+++ b/arch/mips/mach-octeon/include/mach/cvmx-fpa.h
@@ -104,8 +104,9 @@ static inline void *cvmx_fpa_alloc(u64 pool)
/* FPA3 is handled differently */
if ((octeon_has_feature(OCTEON_FEATURE_FPA3))) {
return cvmx_fpa3_alloc(cvmx_fpa1_pool_to_fpa3_aura(pool));
- } else
+ } else {
return cvmx_fpa1_alloc(pool);
+ }
}
/**
diff --git a/arch/mips/mach-octeon/include/mach/cvmx-fpa3.h
b/arch/mips/mach-octeon/include/mach/cvmx-fpa3.h
index b3e04d7f02a1..9bab03f59a09 100644
--- a/arch/mips/mach-octeon/include/mach/cvmx-fpa3.h
+++ b/arch/mips/mach-octeon/include/mach/cvmx-fpa3.h
@@ -526,41 +526,4 @@ const char *cvmx_fpa3_get_pool_name(cvmx_fpa3_pool_t pool);
int cvmx_fpa3_get_pool_buf_size(cvmx_fpa3_pool_t pool);
const char *cvmx_fpa3_get_aura_name(cvmx_fpa3_gaura_t aura);
-/* FIXME: Need a different macro for stage2 of u-boot */
-
-static inline void cvmx_fpa3_stage2_init(int aura, int pool, u64 stack_paddr,
int stacklen,
-int buffer_sz, int buf_cnt)
-{
- cvmx_fpa_poolx_cfg_t pool_cfg;
-
- /* Configure pool stack */
- cvmx_write_csr_node(0, CVMX_FPA_POOLX_STACK_BASE(pool), stack_paddr);
- cvmx_write_csr_node(0, CVMX_FPA_POOLX_STACK_ADDR(pool), stack_paddr);
- cvmx_write_csr_node(0, CVMX_FPA_POOLX_STACK_END(pool), stack_paddr +
stacklen);
-
- /* Configure pool with buffer size */
- pool_cfg.u64 = 0;
- pool_cfg.cn78xx.nat_align = 1;
- pool_cfg.cn78xx.buf_size = buffer_sz >> 7;
- pool_cfg.cn78xx.l_type = 0x2;
- pool_cfg.cn78xx.ena = 0;
- cvmx_write_csr_node(0, CVMX_FPA_POOLX_CFG(pool), pool_cfg.u64);
- /* Reset pool before starting */
- pool_cfg.cn78xx.ena = 1;
- cvmx_write_csr_node(0, CVMX_FPA_POOLX_CFG(pool), pool_cfg.u64);
-
- cvmx_write_csr_node(0, CVMX_FPA_AURAX_CFG(aura), 0);
- cvmx_write_csr_node(0, CVMX_FPA_AURAX_CNT_ADD(aura), buf_cnt);
- cvmx_write_csr_node(0, CVMX_FPA_AURAX_POOL(aura), (u64)pool);
-}
-
-static inline void cvmx_fpa3_stage2_disable(int aura, int pool)
-{
- cvmx_write_csr_node(0, CVMX_FPA_AURAX_POOL(aura), 0);
- cvmx_write_csr_node(0, CVMX_FPA_POOLX_CFG(pool), 0);
- cvmx_write_csr_node(0, CVMX_FPA_POOLX_STACK_BASE(pool), 0);
- cvmx_write_csr_node(0, CVMX_FPA_POOLX_STACK_ADDR(pool), 0);
- cvmx_write_csr_node(0, CVMX_FPA_POOLX_STACK_END(pool), 0);
-}
-
#endif /* __CVMX_FPA3_H__ */
diff --git a/arch/mips/mach-octeon/include/mach/cvmx-helper-board.h
b/arch/mips/mach-octeon/include/mach/cvmx-helper-board.h
index 5837592d21aa..9cc61b1a350e 100644
--- a/arch/mips/mach-octeon/include/mach/cvmx-helper-board.h
+++ b/arch/mips/mach-octeon/include/mach/cvmx-helper-board.h
@@ -9,6 +9,8 @@
#ifndef __CVMX_HELPER_BOARD_H__
#define __CVMX_HELPER_BOARD_H__
+#include
+
#define CVMX_VSC7224_NAME_LEN 16
typedef enum {
@@ -185,8 +187,8 @@ struct cvmx_vsc7224 {
struct cvmx_fdt_i2c_bus_info *i2c_bus;
/** Address of VSC7224 on i2c bus */
int i2c_addr;
- struct cvmx_fdt_gpio_info *los_gpio; /** LoS GPIO pin */
- struct cvmx_fdt_gpio_info *reset_gpio; /** Reset GPIO p
[PATCH v2 12/52] mips: octeon: Add cvmx-helper-fpa.c
From: Aaron Williams
Import cvmx-helper-fpa.c from 2013 U-Boot. It will be used by the later
added drivers to support networking on the MIPS Octeon II / III
platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
arch/mips/mach-octeon/cvmx-helper-fpa.c | 76 +
1 file changed, 76 insertions(+)
create mode 100644 arch/mips/mach-octeon/cvmx-helper-fpa.c
diff --git a/arch/mips/mach-octeon/cvmx-helper-fpa.c
b/arch/mips/mach-octeon/cvmx-helper-fpa.c
new file mode 100644
index ..e87082934739
--- /dev/null
+++ b/arch/mips/mach-octeon/cvmx-helper-fpa.c
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018-2022 Marvell International Ltd.
+ *
+ * Helper functions for FPA setup.
+ */
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+/**
+ * @INTERNAL
+ * OBSOLETE
+ *
+ * Allocate memory for and initialize a single FPA pool.
+ *
+ * @param poolPool to initialize
+ * @param buffer_size Size of buffers to allocate in bytes
+ * @param buffers Number of buffers to put in the pool. Zero is allowed
+ * @param nameString name of the pool for debugging purposes
+ * @return Zero on success, non-zero on failure
+ *
+ * This function is only for transition, will be removed.
+ */
+int __cvmx_helper_initialize_fpa_pool(int pool, u64 buffer_size, u64 buffers,
+ const char *name)
+{
+ return cvmx_fpa_setup_pool(pool, name, NULL, buffer_size, buffers);
+}
--
2.35.1
[PATCH v2 06/52] mips: octeon: Add cvmx-pcsxx-defs.h header file
From: Aaron Williams
Import cvmx-pcsxxx-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support networking on the MIPS Octeon II /
III platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
.../include/mach/cvmx-pcsxx-defs.h| 787 ++
1 file changed, 787 insertions(+)
create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-pcsxx-defs.h
diff --git a/arch/mips/mach-octeon/include/mach/cvmx-pcsxx-defs.h
b/arch/mips/mach-octeon/include/mach/cvmx-pcsxx-defs.h
new file mode 100644
index ..e16a4c404f63
--- /dev/null
+++ b/arch/mips/mach-octeon/include/mach/cvmx-pcsxx-defs.h
@@ -0,0 +1,787 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018-2022 Marvell International Ltd.
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon pcsxx.
+ */
+
+#ifndef __CVMX_PCSXX_DEFS_H__
+#define __CVMX_PCSXX_DEFS_H__
+
+static inline u64 CVMX_PCSXX_10GBX_STATUS_REG(unsigned long offset)
+{
+ switch (cvmx_get_octeon_family()) {
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ return 0x00011800B828ull + (offset) * 0x800ull;
+ case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ return 0x00011800B828ull + (offset) * 0x800ull;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ return 0x00011800B828ull + (offset) * 0x100ull;
+ }
+ return 0x00011800B828ull + (offset) * 0x800ull;
+}
+
+static inline u64 CVMX_PCSXX_BIST_STATUS_REG(unsigned long offset)
+{
+ switch (cvmx_get_octeon_family()) {
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ return 0x00011800B870ull + (offset) * 0x800ull;
+ case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ return 0x00011800B870ull + (offset) * 0x800ull;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ return 0x00011800B870ull + (offset) * 0x100ull;
+ }
+ return 0x00011800B870ull + (offset) * 0x800ull;
+}
+
+static inline u64 CVMX_PCSXX_BIT_LOCK_STATUS_REG(unsigned long offset)
+{
+ switch (cvmx_get_octeon_family()) {
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ return 0x00011800B850ull + (offset) * 0x800ull;
+ case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ return 0x00011800B850ull + (offset) * 0x800ull;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ return 0x00011800B850ull + (offset) * 0x100ull;
+ }
+ return 0x00011800B850ull + (offset) * 0x800ull;
+}
+
+static inline u64 CVMX_PCSXX_CONTROL1_REG(unsigned long offset)
+{
+ switch (cvmx_get_octeon_family()) {
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ return 0x00011800B800ull + (offset) * 0x800ull;
+ case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ return 0x00011800B800ull + (offset) * 0x800ull;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ return 0x00011800B800ull + (offset) * 0x100ull;
+ }
+ return 0x00011800B800ull + (offset) * 0x800ull;
+}
+
+static inline u64 CVMX_PCSXX_CONTROL2_REG(unsigned long offset)
+{
+ switch (cvmx_get_octeon_family()) {
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ return 0x00011800B818ull + (offset) * 0x800ull;
+ case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ return 0x00011800B818ull + (offset) * 0x800ull;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ return 0x00011800B818ull + (offset) * 0x100ull;
+ }
+ return 0x00011800B818ull + (offset) * 0x800ull;
+}
+
+static inline u64 CVMX_PCSXX_INT_EN_REG(unsigned long offset)
+{
+ switch (cvmx_get_octeon_family()) {
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ return 0x00011800B860ull + (offset) * 0x800ull;
+ case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ return 0x00011800B860ull + (offset) * 0x800ull;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ return 0x00011800B860ull + (offset) * 0x100ull;
+ }
+ return 0x00011800B860ull + (offset) * 0x800ull;
+}
+
+static inline u64 CVMX_PCSXX_INT_REG(unsigned long offset)
+{
+ switch (cvmx_get_octeon_family()) {
+ case OC
[PATCH v2 16/52] mips: octeon: Add cvmx-helper-npi.c
From: Aaron Williams
Import cvmx-helper-npi.c from 2013 U-Boot. It will be used by the later
added drivers to support networking on the MIPS Octeon II / III
platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
arch/mips/mach-octeon/cvmx-helper-npi.c | 137
1 file changed, 137 insertions(+)
create mode 100644 arch/mips/mach-octeon/cvmx-helper-npi.c
diff --git a/arch/mips/mach-octeon/cvmx-helper-npi.c
b/arch/mips/mach-octeon/cvmx-helper-npi.c
new file mode 100644
index ..92ee1a80215a
--- /dev/null
+++ b/arch/mips/mach-octeon/cvmx-helper-npi.c
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018-2022 Marvell International Ltd.
+ *
+ * Functions for NPI initialization, configuration,
+ * and monitoring.
+ */
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+static int cvmx_npi_num_pipes = -1;
+
+/**
+ * @INTERNAL
+ * Probe a NPI interface and determine the number of ports
+ * connected to it. The NPI interface should still be down
+ * after this call.
+ *
+ * @param interface to probe
+ *
+ * @return Number of ports on the interface. Zero to disable.
+ */
+int __cvmx_helper_npi_probe(int interface)
+{
+ if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+ return 32;
+ else if (OCTEON_IS_MODEL(OCTEON_CN73XX))
+ return 128;
+ else if (OCTEON_IS_MODEL(OCTEON_CN78XX))
+ return 64;
+
+ return 0;
+}
+
+/**
+ * @INTERNAL
+ * Bringup and enable a NPI interface. After this call packet
+ * I/O should be fully functional. This is called with IPD
+ * enabled but PKO disabled.
+ *
+ * @param xiface Interface to bring up
+ *
+ * @return Zero on success, negative on failure
+ */
+int __cvmx_helper_npi_enable(int xiface)
+{
+ struct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);
+ int interface = xi.interface;
+ int port;
+ int num_ports = cvmx_helper_ports_on_interface(interface);
+
+ /*
+* On CN50XX, CN52XX, and CN56XX we need to disable length
+* checking so packet < 64 bytes and jumbo frames don't get
+* errors.
+*/
+ for (port = 0; port < num_ports; port++) {
+ union cvmx_pip_prt_cfgx port_cfg;
+ int ipd_port =
+ (octeon_has_feature(OCTEON_FEATURE_PKND)) ?
+ cvmx_helper_get_pknd(interface, port) :
+ cvmx_helper_get_ipd_port(interface, port);
+ if (octeon_has_feature(OCTEON_FEATURE_PKI)) {
+ unsigned int node = cvmx_get_node_num();
+
+ cvmx_pki_endis_l2_errs(node, ipd_port, 0, 0, 0);
+
+ } else {
+ port_cfg.u64 = csr_rd(CVMX_PIP_PRT_CFGX(ipd_port));
+ port_cfg.s.lenerr_en = 0;
+ port_cfg.s.maxerr_en = 0;
+ port_cfg.s.minerr_en = 0;
+ csr_wr(CVMX_PIP_PRT_CFGX(ipd_port), port_cfg.u64);
+ }
+ if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
+ /* Set up pknd and bpid */
+ union cvmx_sli_portx_pkind config;
+
+ config.u64 = csr_rd(CVMX_PEXP_SLI_PORTX_PKIND(port));
+ config.s.bpkind = cvmx_helper_get_bpid(interface, port);
+ config.s.pkind = cvmx_helper_get_pknd(interface, port);
+ csr_wr(CVMX_PEXP_SLI_PORTX_PKIND(port), config.u64);
+ }
+ }
+
+ if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
+ /*
+* Set up pko pipes.
+*/
+ union cvmx_sli_tx_pipe config;
+
+ config.u64 = csr_rd(CVMX_PEXP_SLI_TX_PIPE);
+ config.s.base = __cvmx_pko_get_pipe(interface, 0);
+ config.s.nump =
+ cvmx_npi_num_pipes < 0 ? num_ports : cvmx_npi_num_pipes;
+ csr_wr(CVMX_PEXP_SLI_TX_PIPE, config.u64);
+ }
+
+ /* Enables are controlled by the remote host, so nothing to do here */
+ return 0;
+}
--
2.35.1
[PATCH v2 14/52] mips: octeon: Add cvmx-helper-ipd.c
From: Aaron Williams
Import cvmx-helper-ipd.c from 2013 U-Boot. It will be used by the later
added drivers to support networking on the MIPS Octeon II / III
platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
arch/mips/mach-octeon/cvmx-helper-ipd.c | 286
1 file changed, 286 insertions(+)
create mode 100644 arch/mips/mach-octeon/cvmx-helper-ipd.c
diff --git a/arch/mips/mach-octeon/cvmx-helper-ipd.c
b/arch/mips/mach-octeon/cvmx-helper-ipd.c
new file mode 100644
index ..cb04b63b9b07
--- /dev/null
+++ b/arch/mips/mach-octeon/cvmx-helper-ipd.c
@@ -0,0 +1,286 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018-2022 Marvell International Ltd.
+ *
+ * IPD helper functions.
+ */
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+/** It allocate pools for packet and wqe pools
+ * and sets up the FPA hardware
+ */
+int __cvmx_helper_ipd_setup_fpa_pools(void)
+{
+ cvmx_fpa_global_initialize();
+ if (cvmx_ipd_cfg.packet_pool.buffer_count == 0)
+ return 0;
+ __cvmx_helper_initialize_fpa_pool(cvmx_ipd_cfg.packet_pool.pool_num,
+ cvmx_ipd_cfg.packet_pool.buffer_size,
+ cvmx_ipd_cfg.packet_pool.buffer_count,
+ "Packet Buffers");
+ if (cvmx_ipd_cfg.wqe_pool.buffer_count == 0)
+ return 0;
+ __cvmx_helper_initialize_fpa_pool(cvmx_ipd_cfg.wqe_pool.pool_num,
+ cvmx_ipd_cfg.wqe_pool.buffer_size,
+ cvmx_ipd_cfg.wqe_pool.buffer_count,
+ "WQE Buffers");
+ return 0;
+}
+
+/**
+ * @INTERNAL
+ * Setup global setting for IPD/PIP not related to a specific
+ * interface or port. This must be called before IPD is enabled.
+ *
+ * @return Zero on success, negative on failure.
+ */
+int __cvmx_helper_ipd_global_setup(void)
+{
+ /* Setup the packet and wqe pools*/
+ __cvmx_helper_ipd_setup_fpa_pools();
+ /* Setup the global packet input options */
+ cvmx_ipd_config(cvmx_ipd_cfg.packet_pool.buffer_size / 8,
+ cvmx_ipd_cfg.first_mbuf_skip / 8,
+ cvmx_ipd_cfg.not_first_mbuf_skip / 8,
+ /* The +8 is to account for the next ptr */
+ (cvmx_ipd_cfg.first_mbuf_skip + 8) / 128,
+ /* The +8 is to account for the next ptr */
+ (cvmx_ipd_cfg.not_first_mbuf_skip + 8) / 128,
+ cvmx_ipd_cfg.wqe_pool.pool_num,
+ (cvmx_ipd_mode_t)(cvmx_ipd_cfg.cache_mode), 1);
+ return 0;
+}
+
+/**
+ * Enable or disable FCS stripping for all the ports on an interface.
+ *
+ * @param xiface
+ * @param nports number of ports
+ * @param has_fcs 0 for disable and !0 for enable
+ */
+static int cvmx_helper_fcs_op(int xiface, int nports, int has_fcs)
+{
+ u64 port_bit;
+ int index;
+ int pknd;
+ union cvmx_pip_sub_pkind_fcsx pkind_fcsx;
+ union cvmx_pip_prt_cfgx port_cfg;
+ struct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);
+
+ if (!octeon_has_feature(OCTEON_FEATURE_PKND))
+ return 0;
+ if (octeon_has_feature(OCTEON_FEATURE_PKI)) {
+ cvmx_helper_pki_set_fcs_op(xi.node, xi.interface, nports,
+ has_fcs);
+ return 0;
+ }
+
+ port_bit = 0;
+ for (index = 0; index < nports; index++)
+ port_bit |= ((u64)1 << cvmx_helper_get_pknd(xiface, index));
+
+ pkind_fcsx.u64 = csr_rd(CVMX_PIP_SUB_PKIND_FCSX(0));
+ if (has_fcs)
+ pkind_fcsx.s.port_bit |= port_bit;
+ else
+ pkind_fcsx.s.port_bit &= ~port_bit;
+ csr_wr(CVMX_PIP_SUB_PKIND_FCSX(0), pkind_fcsx.u64);
+
+ for (pknd = 0; pknd < 64; pknd++) {
+ if ((1ull << pknd) & port_bit) {
+ port_cfg.u64 = csr_rd(CVMX_PIP_PRT_CFGX(pknd));
+ port_cfg.s.crc_en = (has_fcs) ? 1 : 0;
+ csr_wr(CVMX_PIP_PRT_CFGX(pknd), port_cfg.u64);
+ }
+ }
+
+ return 0;
+}
+
+/**
+ * @INTERNAL
+ * Configure the IPD/PIP tagging and QoS options for a specific
+ * port. This function determines the POW work queue entry
+ * contents for a port. The setup performed here is controlled by
+ * the defines in executive-config.h.
+ *
+
[PATCH v2 11/52] mips: octeon: Add cvmx-helper-board.c
From: Aaron Williams
Import cvmx-helper-board.c from 2013 U-Boot. It will be used by the later
added drivers to support networking on the MIPS Octeon II / III
platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
arch/mips/mach-octeon/cvmx-helper-board.c | 1824 +
1 file changed, 1824 insertions(+)
create mode 100644 arch/mips/mach-octeon/cvmx-helper-board.c
diff --git a/arch/mips/mach-octeon/cvmx-helper-board.c
b/arch/mips/mach-octeon/cvmx-helper-board.c
new file mode 100644
index ..6dcc4e557e12
--- /dev/null
+++ b/arch/mips/mach-octeon/cvmx-helper-board.c
@@ -0,0 +1,1824 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018-2022 Marvell International Ltd.
+ *
+ * Helper functions to abstract board specific data about
+ * network ports from the rest of the cvmx-helper files.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static bool sfp_parsed;
+
+static int __cvmx_helper_78xx_parse_phy(struct cvmx_phy_info *phy_info,
+ int ipd_port);
+static int __get_phy_info_from_dt(cvmx_phy_info_t *phy_info, int ipd_port);
+
+/**
+ * Writes to a Microsemi VSC7224 16-bit register
+ *
+ * @param[in] i2c_bus i2c bus data structure (must be enabled)
+ * @param addrAddress of VSC7224 on the i2c bus
+ * @param reg 8-bit register number to write to
+ * @param val 16-bit value to write
+ *
+ * @return 0 for success
+ */
+static int cvmx_write_vsc7224_reg(const struct cvmx_fdt_i2c_bus_info *i2c_bus,
+ u8 addr, u8 reg, u16 val)
+{
+ struct udevice *dev;
+ u8 buffer[2];
+ int ret;
+
+ ret = i2c_get_chip(i2c_bus->i2c_bus, addr, 1, &dev);
+ if (ret) {
+ debug("Cannot find I2C device: %d\n", ret);
+ return -1;
+ }
+
+ ret = dm_i2c_write(dev, reg, buffer, 2);
+ if (ret) {
+ debug("Cannot write I2C device: %d\n", ret);
+ return -1;
+ }
+
+ return 0;
+}
+
+/**
+ * Writes to a Microsemi VSC7224 16-bit register
+ *
+ * @param[in] i2c_bus i2c bus data structure (must be enabled)
+ * @param addrAddress of VSC7224 on the i2c bus
+ * @param reg 8-bit register number to write to
+ *
+ * @return 16-bit value or error if < 0
+ */
+static int cvmx_read_vsc7224_reg(const struct cvmx_fdt_i2c_bus_info *i2c_bus,
+u8 addr, u8 reg)
+{
+ struct udevice *dev;
+ u8 buffer[2];
+ int ret;
+
+ ret = i2c_get_chip(i2c_bus->i2c_bus, addr, 1, &dev);
+ if (ret) {
+ debug("Cannot find I2C device: %d\n", ret);
+ return -1;
+ }
+
+ ret = dm_i2c_read(dev, reg, buffer, 2);
+ if (ret) {
+ debug("Cannot read I2C device: %d\n", ret);
+ return -1;
+ }
+
+ return (buffer[0] << 8) | buffer[1];
+}
+
+/**
+ * Function called whenever mod_abs/mod_prs has changed for Microsemi VSC7224
+ *
+ * @param sfp pointer to SFP data structure
+ * @param val 1 if absent, 0 if present, otherwise not set
+ * @param datauser-defined data
+ *
+ * @return 0 for success, -1 on error
+ */
+int cvmx_sfp_vsc7224_mod_abs_changed(struct cvmx_fdt_sfp_info *sfp, int val,
+void *data)
+{
+ int err;
+ struct cvmx_sfp_mod_info *mod_info;
+ int length;
+ struct cvmx_vsc7224 *vsc7224;
+ struct cvmx_vsc7224_chan *vsc7224_chan;
+ struct cvmx_vsc7224_tap *taps, *match = NULL;
+ int i;
+
+ debug("%s(%s, %d, %p): Module %s\n", __func__, sfp->name, val, data,
+ val ? "absent" : "present");
+ if (val)
+ return 0;
+
+ /* We're here if we detect that the module is now present */
+ err = cvmx_sfp_read_i2c_eeprom(sfp);
+ if (err) {
+ debug("%s: Error reading the SFP module eeprom for %s\n",
+ __func__, sfp->name);
+ return err;
+ }
+ mod_info = &sfp->sfp_info;
+
+ if (!mod_info->valid || !sfp->valid) {
+ debug("%s: Module data is invalid\n", __func__);
+ return -1;
+ }
+
+ vsc7224_chan = sfp->vsc7224_chan;
+ while (vsc7224_chan) {
+ /* We don't do any rx tuning */
+ if (!vsc7224_chan->is_tx) {
+ vsc7224_chan = vsc7224_chan->next;
+ continue;
+ }
+
+ /* Walk through all the channels */
+ taps = vsc7224_chan->taps;
+ if (mod_info->limiting)
+ length = 0;
+ else
+ length = mod_info->max_copper_cable_len;
+ d
[PATCH v2 17/52] mips: octeon: Add cvmx-helper-pki.c
From: Aaron Williams
Import cvmx-helper-pki.c from 2013 U-Boot. It will be used by the later
added drivers to support networking on the MIPS Octeon II / III
platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
arch/mips/mach-octeon/cvmx-helper-pki.c | 549
1 file changed, 549 insertions(+)
create mode 100644 arch/mips/mach-octeon/cvmx-helper-pki.c
diff --git a/arch/mips/mach-octeon/cvmx-helper-pki.c
b/arch/mips/mach-octeon/cvmx-helper-pki.c
new file mode 100644
index ..51fa4fb5f054
--- /dev/null
+++ b/arch/mips/mach-octeon/cvmx-helper-pki.c
@@ -0,0 +1,549 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018-2022 Marvell International Ltd.
+ *
+ * PKI helper functions.
+ */
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+static int pki_helper_debug;
+
+bool cvmx_pki_dflt_init[CVMX_MAX_NODES] = { [0 ... CVMX_MAX_NODES - 1] = 1 };
+
+static bool cvmx_pki_dflt_bp_en[CVMX_MAX_NODES] = { [0 ... CVMX_MAX_NODES - 1]
=
+ true };
+static struct cvmx_pki_cluster_grp_config pki_dflt_clgrp[CVMX_MAX_NODES] = {
+ { 0, 0xf },
+ { 0, 0xf }
+};
+
+struct cvmx_pki_pool_config pki_dflt_pool[CVMX_MAX_NODES] = {
+ [0 ... CVMX_MAX_NODES -
+1] = { .pool_num = -1, .buffer_size = 2048, .buffer_count = 0 }
+};
+
+struct cvmx_pki_aura_config pki_dflt_aura[CVMX_MAX_NODES] = {
+ [0 ... CVMX_MAX_NODES -
+1] = { .aura_num = 0, .pool_num = -1, .buffer_count = 0 }
+};
+
+struct cvmx_pki_style_config pki_dflt_style[CVMX_MAX_NODES] = {
+ [0 ... CVMX_MAX_NODES - 1] = { .parm_cfg = { .lenerr_en = 1,
+.maxerr_en = 1,
+.minerr_en = 1,
+.fcs_strip = 1,
+.fcs_chk = 1,
+.first_skip = 40,
+.mbuff_size = 2048 } }
+};
+
+struct cvmx_pki_sso_grp_config pki_dflt_sso_grp[CVMX_MAX_NODES];
+struct cvmx_pki_qpg_config pki_dflt_qpg[CVMX_MAX_NODES];
+struct cvmx_pki_pkind_config pki_dflt_pkind[CVMX_MAX_NODES];
+u64 pkind_style_map[CVMX_MAX_NODES][CVMX_PKI_NUM_PKIND] = {
+ [0 ... CVMX_MAX_NODES -
+1] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
+ 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
+ 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }
+};
+
+/* To store the qos watcher values before they are written to pcam when watcher
+ * is enabled. There is no cvmx-pip.c file exist so it ended up here
+ */
+struct cvmx_pki_legacy_qos_watcher qos_watcher[8];
+
+/** @INTERNAL
+ * This function setsup default ltype map
+ * @param nodenode number
+ */
+void __cvmx_helper_pki_set_dflt_ltype_map(int node)
+{
+ cvmx_pki_write_ltype_map(node, CVMX_PKI_LTYPE_E_NONE,
+CVMX_PKI_BELTYPE_NONE);
+ cvmx_pki_write_ltype_map(node, CVMX_PKI_LTYPE_E_ENET,
+CVMX_PKI_BELTYPE_MISC);
+ cvmx_pki_write_ltype_map(node, CVMX_PKI_LTYPE_E_VLAN,
+CVMX_PKI_BELTYPE_MISC);
+ cvmx_pki_write_ltype_map(node, CVMX_PKI_LTYPE_E_SNAP_PAYLD,
+CVMX_PKI_BELTYPE_MISC);
+ cvmx_pki_write_ltype_map(node, CVMX_PKI_LTYPE_E_ARP,
+CVMX_PKI_BELTYPE_MISC);
+ cvmx_pki_write_ltype_map(node, CVMX_PKI_LTYPE_E_RARP,
+CVMX_PKI_BELTYPE_MISC);
+ cvmx_pki_write_ltype_map(node, CVMX_PKI_LTYPE_E_IP4,
+CVMX_PKI_BELTYPE_IP4);
+ cvmx_pki_write_ltype_map(node, CVMX_PKI_LTYPE_E_IP4_OPT,
+CVMX_PKI_BELTYPE_IP4);
+ cvmx_pki_write_ltype_map(node, CVMX_PKI_LTYPE_E_IP6,
+CVMX_PKI_BELTYPE_IP6);
+ cvmx_pki_write_ltype_map(node, CVMX_PKI_LTYPE_E_IP6_OPT,
+CVMX_PKI_BELTYPE_IP6);
+ cvmx_pki_write_ltype_map(node, CVMX_PKI_LTYPE_E_IPSEC_ESP,
+CVMX_PKI_BELTYPE_MISC);
+ cvmx_pki_write_ltype_map(node, CVMX_PKI_LTYPE_E_IPFRAG,
+CVMX_PKI_BELTYPE_MISC);
+ cvmx_pki_write_ltype_map(node, CVMX_PKI_LTYPE_E_IPCOMP,
+CVMX_PKI_BEL
[PATCH v2 09/52] mips: octeon: Add cvmx-helper-agl.c
From: Aaron Williams
Import cvmx-helper-agl.c from 2013 U-Boot. It will be used by the later
added drivers to support networking on the MIPS Octeon II / III
platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
arch/mips/mach-octeon/cvmx-helper-agl.c | 231
1 file changed, 231 insertions(+)
create mode 100644 arch/mips/mach-octeon/cvmx-helper-agl.c
diff --git a/arch/mips/mach-octeon/cvmx-helper-agl.c
b/arch/mips/mach-octeon/cvmx-helper-agl.c
new file mode 100644
index ..7eb99ac7c22b
--- /dev/null
+++ b/arch/mips/mach-octeon/cvmx-helper-agl.c
@@ -0,0 +1,231 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018-2022 Marvell International Ltd.
+ *
+ * Functions for AGL (RGMII) initialization, configuration,
+ * and monitoring.
+ */
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include
+#include
+
+#include
+#include
+
+int __cvmx_helper_agl_enumerate(int xiface)
+{
+ if (OCTEON_IS_MODEL(OCTEON_CN70XX)) {
+ union cvmx_agl_prtx_ctl agl_prtx_ctl;
+
+ agl_prtx_ctl.u64 = csr_rd(CVMX_AGL_PRTX_CTL(0));
+ if (agl_prtx_ctl.s.mode == 0) /* RGMII */
+ return 1;
+ }
+ return 0;
+}
+
+/**
+ * @INTERNAL
+ * Convert interface to port to assess CSRs.
+ *
+ * @param xiface Interface to probe
+ * @return The port corresponding to the interface
+ */
+int cvmx_helper_agl_get_port(int xiface)
+{
+ struct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);
+
+ if (OCTEON_IS_MODEL(OCTEON_CN70XX))
+ return xi.interface - 4;
+ return -1;
+}
+
+/**
+ * @INTERNAL
+ * Probe a RGMII interface and determine the number of ports
+ * connected to it. The RGMII interface should still be down
+ * after this call.
+ *
+ * @param interface to probe
+ *
+ * @return Number of ports on the interface. Zero to disable.
+ */
+int __cvmx_helper_agl_probe(int interface)
+{
+ int port = cvmx_helper_agl_get_port(interface);
+ union cvmx_agl_gmx_bist gmx_bist;
+ union cvmx_agl_gmx_prtx_cfg gmx_prtx_cfg;
+ union cvmx_agl_prtx_ctl agl_prtx_ctl;
+ int result;
+
+ result = __cvmx_helper_agl_enumerate(interface);
+ if (result == 0)
+ return 0;
+
+ /* Check BIST status */
+ gmx_bist.u64 = csr_rd(CVMX_AGL_GMX_BIST);
+ if (gmx_bist.u64)
+ printf("Management port AGL failed BIST (0x%016llx) on AGL%d\n",
+ CAST64(gmx_bist.u64), port);
+
+ /* Disable the external input/output */
+ gmx_prtx_cfg.u64 = csr_rd(CVMX_AGL_GMX_PRTX_CFG(port));
+ gmx_prtx_cfg.s.en = 0;
+ csr_wr(CVMX_AGL_GMX_PRTX_CFG(port), gmx_prtx_cfg.u64);
+
+ /* Set the rgx_ref_clk MUX with AGL_PRTx_CTL[REFCLK_SEL]. Default value
+* is 0 (RGMII REFCLK). Recommended to use RGMII RXC(1) or sclk/4 (2)
+* to save cost.
+*/
+
+ agl_prtx_ctl.u64 = csr_rd(CVMX_AGL_PRTX_CTL(port));
+ agl_prtx_ctl.s.clkrst = 0;
+ agl_prtx_ctl.s.dllrst = 0;
+ agl_prtx_ctl.s.clktx_byp = 0;
+
+ if (OCTEON_IS_MODEL(OCTEON_CN70XX)) {
+ bool tx_enable_bypass;
+ int tx_delay;
+
+ agl_prtx_ctl.s.refclk_sel =
+ cvmx_helper_get_agl_refclk_sel(interface, port);
+ agl_prtx_ctl.s.clkrx_set =
+ cvmx_helper_get_agl_rx_clock_skew(interface, port);
+ agl_prtx_ctl.s.clkrx_byp =
+ cvmx_helper_get_agl_rx_clock_delay_bypass(interface,
+ port);
+ cvmx_helper_cfg_get_rgmii_tx_clk_delay(
+ interface, port, &tx_enable_bypass, &tx_delay);
+ agl_prtx_ctl.s.clktx_byp = tx_enable_bypass;
+ agl_prtx_ctl.s.clktx_set = tx_delay;
+ }
+ csr_wr(CVMX_AGL_PRTX_CTL(port), agl_prtx_ctl.u64);
+ /* Force write out before wait */
+ csr_rd(CVMX_AGL_PRTX_CTL(port));
+ udelay(500);
+
+ /* Enable the componsation controller */
+ agl_prtx_ctl.u64 = csr_rd(CVMX_AGL_PRTX_CTL(port));
+ agl_prtx_ctl.s.drv_byp = 0;
+ csr_wr(CVMX_AGL_PRTX_CTL(port), agl_prtx_ctl.u64);
+ /* Force write out before wait */
+ csr_rd(CVMX_AGL_PRTX_CTL(port));
+
+ if (!OCTEON_IS_OCTEON3()) {
+ /* Enable the interface */
+ agl_prtx_ctl.u64 = csr_rd(CVMX_AGL_PRTX_CTL(port));
+ agl_prtx_ctl.s.enable = 1;
+ csr_wr(CVMX_AGL_PRTX_CTL(port), agl_prtx_ctl.u64);
+ /* Read the value back to force the previous write */
+ agl_prtx_ctl.u64 = csr_rd(CVMX_AGL_PRTX_CTL(port));
+ }
+
+ /* Enable the compensation controller */
+ agl_prtx_ctl.u64 = csr_rd(CVMX_AGL_PRTX_CTL(p
[PATCH v2 18/52] mips: octeon: Add cvmx-helper-pko.c
From: Aaron Williams
Import cvmx-helper-pko.c from 2013 U-Boot. It will be used by the later
added drivers to support networking on the MIPS Octeon II / III
platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
arch/mips/mach-octeon/cvmx-helper-pko.c | 203
1 file changed, 203 insertions(+)
create mode 100644 arch/mips/mach-octeon/cvmx-helper-pko.c
diff --git a/arch/mips/mach-octeon/cvmx-helper-pko.c
b/arch/mips/mach-octeon/cvmx-helper-pko.c
new file mode 100644
index ..b9ac22cf0081
--- /dev/null
+++ b/arch/mips/mach-octeon/cvmx-helper-pko.c
@@ -0,0 +1,203 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018-2022 Marvell International Ltd.
+ *
+ * Helper Functions for the PKO
+ */
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+static s64 pko_fpa_config_pool = -1;
+static u64 pko_fpa_config_size = 1024;
+
+/**
+ * cvmx_override_pko_queue_priority(int pko_port, u64
+ * priorities[16]) is a function pointer. It is meant to allow
+ * customization of the PKO queue priorities based on the port
+ * number. Users should set this pointer to a function before
+ * calling any cvmx-helper operations.
+ */
+void (*cvmx_override_pko_queue_priority)(int ipd_port,
+uint8_t *priorities) = NULL;
+
+int64_t cvmx_fpa_get_pko_pool(void)
+{
+ return pko_fpa_config_pool;
+}
+
+/**
+ * Gets the buffer size of pko pool
+ */
+u64 cvmx_fpa_get_pko_pool_block_size(void)
+{
+ return pko_fpa_config_size;
+}
+
+/**
+ * Initialize PKO command queue buffer pool
+ */
+static int cvmx_helper_pko_pool_init(void)
+{
+ u8 pool;
+ unsigned int buf_count;
+ unsigned int pkt_buf_count;
+ int rc;
+
+ /* Reserve pool */
+ pool = cvmx_fpa_get_pko_pool();
+
+ /* Avoid redundant pool creation */
+ if (cvmx_fpa_get_block_size(pool) > 0) {
+#ifdef DEBUG
+ debug("WARNING: %s: pool %d already initialized\n", __func__,
+ pool);
+#endif
+ /* It is up to the app to have sufficient buffer count */
+ return pool;
+ }
+
+ /* Calculate buffer count: one per queue + 3-word-cmds * max_pkts */
+ pkt_buf_count = cvmx_fpa_get_packet_pool_buffer_count();
+ buf_count = CVMX_PKO_MAX_OUTPUT_QUEUES + (pkt_buf_count * 3) / 8;
+
+ /* Allocate pools for pko command queues */
+ rc = __cvmx_helper_initialize_fpa_pool(pool,
+
cvmx_fpa_get_pko_pool_block_size(),
+ buf_count, "PKO Cmd-bufs");
+
+ if (rc < 0)
+ debug("%s: ERROR: in PKO buffer pool\n", __func__);
+
+ pool = rc;
+ return pool;
+}
+
+/**
+ * Initialize the PKO
+ *
+ */
+int cvmx_helper_pko_init(void)
+{
+ int rc;
+
+ rc = cvmx_helper_pko_pool_init();
+ if (rc < 0)
+ return rc;
+
+ __cvmx_helper_init_port_config_data(0);
+
+ cvmx_pko_hw_init(cvmx_fpa_get_pko_pool(),
+cvmx_fpa_get_pko_pool_block_size());
+ return 0;
+}
+
+/**
+ * @INTERNAL
+ * Setup the PKO for the ports on an interface. The number of
+ * queues per port and the priority of each PKO output queue
+ * is set here. PKO must be disabled when this function is called.
+ *
+ * @param interface to setup PKO for
+ *
+ * @return Zero on success, negative on failure
+ *
+ * @note This is for PKO1/PKO2, and is not used for PKO3.
+ */
+int __cvmx_helper_interface_setup_pko(int interface)
+{
+ /*
+* Each packet output queue has an associated priority. The
+* higher the priority, the more often it can send a packet. A
+* priority of 8 means it can send in all 8 rounds of
+* contention. We're going to make each queue one less than
+* the last. The vector of priorities has been extended to
+* support CN5xxx CPUs, where up to 16 queues can be
+* associated to a port. To keep backward compatibility we
+* don't change the initial 8 priorities and replicate them in
+* the second half. With per-core PKO queues (PKO lockless
+* operation) all queues have the same priority.
+*/
+ /* uint8_t priorities[16] = {8,7,6,5,4,3,2,1,8,7,6,5,4,3,2,1}; */
+ u8 priorities[16] = { [0 ... 15] = 8 };
+
+ /*
+* Setup the IPD/PIP and PKO for the ports discovered
+* above. Here packet classification, tagging and output
+* priorities are set.
+*/
+ int num_
[PATCH v2 02/52] mips: octeon: Add cvmx-ilk-defs.h header file
From: Aaron Williams Import cvmx-igl-defs.h header file from 2013 U-Boot. It will be used by the later added drivers to support networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams Signed-off-by: Stefan Roese --- .../mach-octeon/include/mach/cvmx-ilk-defs.h | 2269 + 1 file changed, 2269 insertions(+) create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-ilk-defs.h diff --git a/arch/mips/mach-octeon/include/mach/cvmx-ilk-defs.h b/arch/mips/mach-octeon/include/mach/cvmx-ilk-defs.h new file mode 100644 index ..d54f9ca792f5 --- /dev/null +++ b/arch/mips/mach-octeon/include/mach/cvmx-ilk-defs.h @@ -0,0 +1,2269 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018-2022 Marvell International Ltd. + * + * Configuration and status register (CSR) type definitions for + * Octeon ilk. + */ + +#ifndef __CVMX_ILK_DEFS_H__ +#define __CVMX_ILK_DEFS_H__ + +#define CVMX_ILK_BIST_SUM(0x000118001438ull) +#define CVMX_ILK_GBL_CFG (0x000118001400ull) +#define CVMX_ILK_GBL_ERR_CFG (0x000118001458ull) +#define CVMX_ILK_GBL_INT (0x000118001408ull) +#define CVMX_ILK_GBL_INT_EN (0x000118001410ull) +#define CVMX_ILK_INT_SUM (0x000118001430ull) +#define CVMX_ILK_LNEX_TRN_CTL(offset) \ + (0x00011800140380F0ull + ((offset) & 15) * 1024) +#define CVMX_ILK_LNEX_TRN_LD(offset) \ + (0x00011800140380E0ull + ((offset) & 15) * 1024) +#define CVMX_ILK_LNEX_TRN_LP(offset) \ + (0x00011800140380E8ull + ((offset) & 15) * 1024) +#define CVMX_ILK_LNE_DBG (0x0001180014030008ull) +#define CVMX_ILK_LNE_STS_MSG (0x000118001403ull) +#define CVMX_ILK_RID_CFG (0x000118001450ull) +#define CVMX_ILK_RXF_IDX_PMAP (0x000118001420ull) +#define CVMX_ILK_RXF_MEM_PMAP (0x000118001428ull) +#define CVMX_ILK_RXX_BYTE_CNTX(offset, block_id) \ + (0x0001180014023000ull + \ +(((offset) & 255) + ((block_id) & 1) * 0x800ull) * 8) +#define CVMX_ILK_RXX_CAL_ENTRYX(offset, block_id) \ + (0x0001180014021000ull + \ +(((offset) & 511) + ((block_id) & 1) * 0x800ull) * 8) +#define CVMX_ILK_RXX_CFG0(offset) (0x000118001402ull + ((offset) & 1) * 16384) +#define CVMX_ILK_RXX_CFG1(offset) (0x0001180014020008ull + ((offset) & 1) * 16384) +#define CVMX_ILK_RXX_CHAX(offset, block_id) \ + (0x0001180014002000ull + \ +(((offset) & 255) + ((block_id) & 1) * 0x200ull) * 8) +#define CVMX_ILK_RXX_CHA_XONX(offset, block_id) \ + (0x0001180014020400ull + (((offset) & 3) + ((block_id) & 1) * 0x800ull) * 8) +#define CVMX_ILK_RXX_ERR_CFG(offset) \ + (0x00011800140200E0ull + ((offset) & 1) * 16384) +#define CVMX_ILK_RXX_FLOW_CTL0(offset) \ + (0x0001180014020090ull + ((offset) & 1) * 16384) +#define CVMX_ILK_RXX_FLOW_CTL1(offset) \ + (0x0001180014020098ull + ((offset) & 1) * 16384) +#define CVMX_ILK_RXX_IDX_CAL(offset) \ + (0x00011800140200A0ull + ((offset) & 1) * 16384) +#define CVMX_ILK_RXX_IDX_STAT0(offset) \ + (0x0001180014020070ull + ((offset) & 1) * 16384) +#define CVMX_ILK_RXX_IDX_STAT1(offset) \ + (0x0001180014020078ull + ((offset) & 1) * 16384) +#define CVMX_ILK_RXX_INT(offset) (0x0001180014020010ull + ((offset) & 1) * 16384) +#define CVMX_ILK_RXX_INT_EN(offset) \ + (0x0001180014020018ull + ((offset) & 1) * 16384) +#define CVMX_ILK_RXX_JABBER(offset) \ + (0x00011800140200B8ull + ((offset) & 1) * 16384) +#define CVMX_ILK_RXX_MEM_CAL0(offset) \ + (0x00011800140200A8ull + ((offset) & 1) * 16384) +#define CVMX_ILK_RXX_MEM_CAL1(offset) \ + (0x00011800140200B0ull + ((offset) & 1) * 16384) +#define CVMX_ILK_RXX_MEM_STAT0(offset) \ + (0x0001180014020080ull + ((offset) & 1) * 16384) +#define CVMX_ILK_RXX_MEM_STAT1(offset) \ + (0x0001180014020088ull + ((offset) & 1) * 16384) +#define CVMX_ILK_RXX_PKT_CNTX(offset, block_id) \ + (0x0001180014022000ull + \ +(((offset) & 255) + ((block_id) & 1) * 0x800ull) * 8) +#define CVMX_ILK_RXX_RID(offse
[PATCH v2 10/52] mips: octeon: Add cvmx-helper-bgx.c
From: Aaron Williams
Import cvmx-helper-bgx.c from 2013 U-Boot. It will be used by the later
added drivers to support networking on the MIPS Octeon II / III
platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
arch/mips/mach-octeon/cvmx-helper-bgx.c | 2737 +++
1 file changed, 2737 insertions(+)
create mode 100644 arch/mips/mach-octeon/cvmx-helper-bgx.c
diff --git a/arch/mips/mach-octeon/cvmx-helper-bgx.c
b/arch/mips/mach-octeon/cvmx-helper-bgx.c
new file mode 100644
index ..7d6e178a447a
--- /dev/null
+++ b/arch/mips/mach-octeon/cvmx-helper-bgx.c
@@ -0,0 +1,2737 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018-2022 Marvell International Ltd.
+ *
+ * Functions to configure the BGX MAC.
+ */
+
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+/* Enable this define to see BGX error messages */
+/*#define DEBUG_BGX */
+
+/* Enable this variable to trace functions called for initializing BGX */
+static const int debug;
+
+/**
+ * cvmx_helper_bgx_override_autoneg(int xiface, int index) is a function
pointer
+ * to override enabling/disabling of autonegotiation for SGMII, 10G-KR or
40G-KR4
+ * interfaces. This function is called when interface is initialized.
+ */
+int (*cvmx_helper_bgx_override_autoneg)(int xiface, int index) = NULL;
+
+/*
+ * cvmx_helper_bgx_override_fec(int xiface) is a function pointer
+ * to override enabling/disabling of FEC for 10G interfaces. This function
+ * is called when interface is initialized.
+ */
+int (*cvmx_helper_bgx_override_fec)(int xiface, int index) = NULL;
+
+/**
+ * Delay after enabling an interface based on the mode. Different modes take
+ * different amounts of time.
+ */
+static void
+__cvmx_helper_bgx_interface_enable_delay(cvmx_helper_interface_mode_t mode)
+{
+ switch (mode) {
+ case CVMX_HELPER_INTERFACE_MODE_10G_KR:
+ case CVMX_HELPER_INTERFACE_MODE_40G_KR4:
+ case CVMX_HELPER_INTERFACE_MODE_XLAUI:
+ case CVMX_HELPER_INTERFACE_MODE_XFI:
+ mdelay(250);
+ break;
+ case CVMX_HELPER_INTERFACE_MODE_RXAUI:
+ case CVMX_HELPER_INTERFACE_MODE_XAUI:
+ mdelay(100);
+ break;
+ case CVMX_HELPER_INTERFACE_MODE_SGMII:
+ mdelay(50);
+ break;
+ default:
+ mdelay(50);
+ break;
+ }
+}
+
+/**
+ * @INTERNAL
+ *
+ * Returns number of ports based on interface
+ * @param xiface Which xiface
+ * @return Number of ports based on xiface
+ */
+int __cvmx_helper_bgx_enumerate(int xiface)
+{
+ cvmx_bgxx_cmr_tx_lmacs_t lmacs;
+ struct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);
+
+ lmacs.u64 = csr_rd_node(xi.node, CVMX_BGXX_CMR_TX_LMACS(xi.interface));
+ return lmacs.s.lmacs;
+}
+
+/**
+ * @INTERNAL
+ *
+ * Returns mode of each BGX LMAC (port).
+ * This is different than 'cvmx_helper_interface_get_mode()' which
+ * provides mode of an entire interface, but when BGX is in "mixed"
+ * mode this function should be called instead to get the protocol
+ * for each port (BGX LMAC) individually.
+ * Both function return the same enumerated mode.
+ *
+ * @param xiface is the global interface identifier
+ * @param index is the interface port index
+ * @returns mode of the individual port
+ */
+cvmx_helper_interface_mode_t cvmx_helper_bgx_get_mode(int xiface, int index)
+{
+ struct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);
+ cvmx_bgxx_cmrx_config_t cmr_config;
+ cvmx_bgxx_spux_br_pmd_control_t pmd_control;
+
+ cmr_config.u64 = csr_rd_node(
+ xi.node, CVMX_BGXX_CMRX_CONFIG(index, xi.interface));
+
+ switch (cmr_config.s.lmac_type) {
+ case 0:
+ return CVMX_HELPER_INTERFACE_MODE_SGMII;
+ case 1:
+ return CVMX_HELPER_INTERFACE_MODE_XAUI;
+ case 2:
+ return CVMX_HELPER_INTERFACE_MODE_RXAUI;
+ case 3:
+ if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
+ return cvmx_helper_interface_get_mode(xiface);
+ pmd_control.u64 = csr_rd_node(
+ xi.node,
+ CVMX_BGXX_SPUX_BR_PMD_CONTROL(index, xi.interface));
+ if (pmd_control.s.train_en)
+ return CVMX_HELPER_INTERFACE_MODE_10G_KR;
+ else
+ return CVMX_HELPER_INTERFACE_MODE_XFI;
+ break;
+ case 4:
+ if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
+ return cvmx_helper_interface_get_mode(xiface);
+ pmd_control.u64 = csr_rd_node(
+ xi.no
[PATCH v2 05/52] mips: octeon: Add cvmx-npei-defs.h header file
From: Aaron Williams Import cvmx-npei-defs.h header file from 2013 U-Boot. It will be used by the later added drivers to support networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams Signed-off-by: Stefan Roese --- .../mach-octeon/include/mach/cvmx-npei-defs.h | 3550 + 1 file changed, 3550 insertions(+) create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-npei-defs.h diff --git a/arch/mips/mach-octeon/include/mach/cvmx-npei-defs.h b/arch/mips/mach-octeon/include/mach/cvmx-npei-defs.h new file mode 100644 index ..2e2c24819445 --- /dev/null +++ b/arch/mips/mach-octeon/include/mach/cvmx-npei-defs.h @@ -0,0 +1,3550 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018-2022 Marvell International Ltd. + * + * Configuration and status register (CSR) type definitions for + * Octeon npei. + */ + +#ifndef __CVMX_NPEI_DEFS_H__ +#define __CVMX_NPEI_DEFS_H__ + +#define CVMX_NPEI_BAR1_INDEXX(offset) \ + (0xull + ((offset) & 31) * 16) +#define CVMX_NPEI_BIST_STATUS (0x0580ull) +#define CVMX_NPEI_BIST_STATUS2 (0x0680ull) +#define CVMX_NPEI_CTL_PORT0 (0x0250ull) +#define CVMX_NPEI_CTL_PORT1 (0x0260ull) +#define CVMX_NPEI_CTL_STATUS(0x0570ull) +#define CVMX_NPEI_CTL_STATUS2 (0x3C00ull) +#define CVMX_NPEI_DATA_OUT_CNT (0x05F0ull) +#define CVMX_NPEI_DBG_DATA (0x0510ull) +#define CVMX_NPEI_DBG_SELECT(0x0500ull) +#define CVMX_NPEI_DMA0_INT_LEVEL (0x05C0ull) +#define CVMX_NPEI_DMA1_INT_LEVEL (0x05D0ull) +#define CVMX_NPEI_DMAX_COUNTS(offset) \ + (0x0450ull + ((offset) & 7) * 16) +#define CVMX_NPEI_DMAX_DBELL(offset) (0x03B0ull + ((offset) & 7) * 16) +#define CVMX_NPEI_DMAX_IBUFF_SADDR(offset) \ + (0x0400ull + ((offset) & 7) * 16) +#define CVMX_NPEI_DMAX_NADDR(offset) (0x04A0ull + ((offset) & 7) * 16) +#define CVMX_NPEI_DMA_CNTS (0x05E0ull) +#define CVMX_NPEI_DMA_CONTROL (0x03A0ull) +#define CVMX_NPEI_DMA_PCIE_REQ_NUM (0x05B0ull) +#define CVMX_NPEI_DMA_STATE1(0x06C0ull) +#define CVMX_NPEI_DMA_STATE1_P1 (0x0680ull) +#define CVMX_NPEI_DMA_STATE2(0x06D0ull) +#define CVMX_NPEI_DMA_STATE2_P1 (0x0690ull) +#define CVMX_NPEI_DMA_STATE3_P1 (0x06A0ull) +#define CVMX_NPEI_DMA_STATE4_P1 (0x06B0ull) +#define CVMX_NPEI_DMA_STATE5_P1 (0x06C0ull) +#define CVMX_NPEI_INT_A_ENB (0x0560ull) +#define CVMX_NPEI_INT_A_ENB2(0x3CE0ull) +#define CVMX_NPEI_INT_A_SUM (0x0550ull) +#define CVMX_NPEI_INT_ENB (0x0540ull) +#define CVMX_NPEI_INT_ENB2 (0x3CD0ull) +#define CVMX_NPEI_INT_INFO (0x0590ull) +#define CVMX_NPEI_INT_SUM (0x0530ull) +#define CVMX_NPEI_INT_SUM2 (0x3CC0ull) +#define CVMX_NPEI_LAST_WIN_RDATA0(0x0600ull) +#define CVMX_NPEI_LAST_WIN_RDATA1(0x0610ull) +#define CVMX_NPEI_MEM_ACCESS_CTL (0x04F0ull) +#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) \ + (0x0280ull + ((offset) & 31) * 16 - 16 * 12) +#define CVMX_NPEI_MSI_ENB0 (0x3C50ull) +#define CVMX_NPEI_MSI_ENB1 (0x3C60ull) +#define CVMX_NPEI_MSI_ENB2 (0x3C70ull) +#define CVMX_NPEI_MSI_ENB3 (0x3C80ull) +#define CVMX_NPEI_MSI_RCV0 (0x3C10ull) +#define CVMX_NPEI_MSI_RCV1 (0x3C20ull) +#define CVMX_NPEI_MSI_RCV2 (0x3C30ull) +#define CVMX_NPEI_MSI_RCV3 (0x3C40ull) +#define CVMX_NPEI_MSI_RD_MAP (0x3CA0ull) +#define CVMX_NPEI_MSI_W1C_ENB0 (0x3CF0ull) +#define CVMX_NPEI_MSI_W1C_ENB1 (0x3D00ull) +#define CVMX_NPEI_MSI_W1C_ENB2 (0x3D10ull) +#define CVMX_NPEI_MSI_W1C_ENB3 (0x3D20ull) +#define CVMX_NPEI_MSI_W1S_ENB0 (0x3D30ull) +#define CVMX_NPEI_MSI_W1S_ENB1 (0x3D40ull) +#define CVMX_NPEI_MSI_W1S_ENB2 (0x3D50ull) +#define CVMX_NPEI_MSI_W1S_ENB3 (0x3D60ull) +#define CVMX_NPEI_MSI_WR_MAP (0x3C90ull) +#define CVMX_NPEI_PCIE_CREDIT_CNT (0x3D70ull) +#define CVMX_NPEI_PCIE_MSI_RCV (0x3CB0ull) +#define CVMX_NPEI_PCIE_MSI_RCV_B1 (0x0650ull) +#define CVMX_NPEI_PCIE_MSI_RCV_B2 (0x0660ull) +#define CVMX_NPEI_PCIE_MSI_RCV_B3 (0x00
[PATCH v2 23/52] mips: octeon: Add cvmx-helper-xaui.c
From: Aaron Williams
Import cvmx-helper-xaui.c from 2013 U-Boot. It will be used by the later
added drivers to support networking on the MIPS Octeon II / III
platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
arch/mips/mach-octeon/cvmx-helper-xaui.c | 518 +++
1 file changed, 518 insertions(+)
create mode 100644 arch/mips/mach-octeon/cvmx-helper-xaui.c
diff --git a/arch/mips/mach-octeon/cvmx-helper-xaui.c
b/arch/mips/mach-octeon/cvmx-helper-xaui.c
new file mode 100644
index ..2eb3b7d9c462
--- /dev/null
+++ b/arch/mips/mach-octeon/cvmx-helper-xaui.c
@@ -0,0 +1,518 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018-2022 Marvell International Ltd.
+ *
+ * Functions for XAUI initialization, configuration,
+ * and monitoring.
+ */
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+int __cvmx_helper_xaui_enumerate(int xiface)
+{
+ struct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);
+ int interface = xi.interface;
+ union cvmx_gmxx_hg2_control gmx_hg2_control;
+
+ if (OCTEON_IS_MODEL(OCTEON_CN70XX)) {
+ enum cvmx_qlm_mode qlm_mode =
+ cvmx_qlm_get_dlm_mode(0, interface);
+
+ if (qlm_mode == CVMX_QLM_MODE_RXAUI)
+ return 1;
+ return 0;
+ }
+ /* If HiGig2 is enabled return 16 ports, otherwise return 1 port */
+ gmx_hg2_control.u64 = csr_rd(CVMX_GMXX_HG2_CONTROL(interface));
+ if (gmx_hg2_control.s.hg2tx_en)
+ return 16;
+ else
+ return 1;
+}
+
+/**
+ * @INTERNAL
+ * Probe a XAUI interface and determine the number of ports
+ * connected to it. The XAUI interface should still be down
+ * after this call.
+ *
+ * @param xiface Interface to probe
+ *
+ * @return Number of ports on the interface. Zero to disable.
+ */
+int __cvmx_helper_xaui_probe(int xiface)
+{
+ int i, ports;
+ struct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);
+ int interface = xi.interface;
+ union cvmx_gmxx_inf_mode mode;
+
+ /*
+* CN63XX Pass 1.0 errata G-14395 requires the QLM De-emphasis
+* be programmed.
+*/
+ if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_0)) {
+ union cvmx_ciu_qlm2 ciu_qlm;
+
+ ciu_qlm.u64 = csr_rd(CVMX_CIU_QLM2);
+ ciu_qlm.s.txbypass = 1;
+ ciu_qlm.s.txdeemph = 0x5;
+ ciu_qlm.s.txmargin = 0x1a;
+ csr_wr(CVMX_CIU_QLM2, ciu_qlm.u64);
+ }
+
+ /*
+* CN63XX Pass 2.x errata G-15273 requires the QLM De-emphasis
+* be programmed when using a 156.25Mhz ref clock.
+*/
+ if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_X)) {
+ /* Read the QLM speed pins */
+ union cvmx_mio_rst_boot mio_rst_boot;
+
+ mio_rst_boot.u64 = csr_rd(CVMX_MIO_RST_BOOT);
+
+ if (mio_rst_boot.cn63xx.qlm2_spd == 0xb) {
+ union cvmx_ciu_qlm2 ciu_qlm;
+
+ ciu_qlm.u64 = csr_rd(CVMX_CIU_QLM2);
+ ciu_qlm.s.txbypass = 1;
+ ciu_qlm.s.txdeemph = 0xa;
+ ciu_qlm.s.txmargin = 0x1f;
+ csr_wr(CVMX_CIU_QLM2, ciu_qlm.u64);
+ }
+ }
+
+ /*
+* Check if QLM is configured correct for XAUI/RXAUI, verify
+* the speed as well as mode.
+*/
+ if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
+ int qlm = cvmx_qlm_interface(xiface);
+ enum cvmx_qlm_mode mode = cvmx_qlm_get_mode(qlm);
+
+ if (mode != CVMX_QLM_MODE_XAUI && mode != CVMX_QLM_MODE_RXAUI)
+ return 0;
+ }
+
+ ports = __cvmx_helper_xaui_enumerate(xiface);
+
+ if (ports <= 0)
+ return 0;
+
+ /*
+* Due to errata GMX-700 on CN56XXp1.x and CN52XXp1.x, the
+* interface needs to be enabled before IPD otherwise per port
+* backpressure may not work properly.
+*/
+ mode.u64 = csr_rd(CVMX_GMXX_INF_MODE(interface));
+ mode.s.en = 1;
+ csr_wr(CVMX_GMXX_INF_MODE(interface), mode.u64);
+
+ if (!OCTEON_IS_MODEL(OCTEON_CN68XX) &&
+ !OCTEON_IS_MODEL(OCTEON_CN70XX)) {
+ /*
+* Setup PKO to support 16 ports for HiGig2 virtual
+* ports. We're pointing all of the PKO packet ports
+* for this interface to the XAUI. This allows us to
+* use HiGig2 backpressure per port.
+*/
+ for (i = 0; i < 16; i++) {
+ union cvmx_pko_mem_port_ptrs pko_mem_port_pt
[PATCH v2 26/52] mips: octeon: Add cvmx-fau-compat.c
From: Aaron Williams
Import cvmx-fau-compat.c from 2013 U-Boot. It will be used by the later
added drivers to support networking on the MIPS Octeon II / III
platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
arch/mips/mach-octeon/cvmx-fau-compat.c | 53 +
1 file changed, 53 insertions(+)
create mode 100644 arch/mips/mach-octeon/cvmx-fau-compat.c
diff --git a/arch/mips/mach-octeon/cvmx-fau-compat.c
b/arch/mips/mach-octeon/cvmx-fau-compat.c
new file mode 100644
index ..9c2ff763ad53
--- /dev/null
+++ b/arch/mips/mach-octeon/cvmx-fau-compat.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018-2022 Marvell International Ltd.
+ */
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include
+#include
+#include
+#include
+
+#include
+
+u8 *cvmx_fau_regs_ptr;
+
+void cvmx_fau_bootmem_init(void *bootmem)
+{
+ memset(bootmem, 0, CVMX_FAU_MAX_REGISTERS_8);
+}
+
+/**
+ * Initializes FAU region for devices without FAU unit.
+ * @return 0 on success -1 on failure
+ */
+int cvmx_fau_init(void)
+{
+ cvmx_fau_regs_ptr = (u8 *)cvmx_bootmem_alloc_named_range_once(
+ CVMX_FAU_MAX_REGISTERS_8, 0, 1ull << 31, 128,
+ "cvmx_fau_registers", cvmx_fau_bootmem_init);
+
+ if (cvmx_fau_regs_ptr == 0ull) {
+ debug("ERROR: Failed to alloc named block for software FAU.\n");
+ return -1;
+ }
+
+ return 0;
+}
--
2.35.1
[PATCH v2 24/52] mips: octeon: Add cvmx-agl.c
From: Aaron Williams
Import cvmx-agl.c from 2013 U-Boot. It will be used by the later
added drivers to support networking on the MIPS Octeon II / III
platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
arch/mips/mach-octeon/cvmx-agl.c | 216 +++
1 file changed, 216 insertions(+)
create mode 100644 arch/mips/mach-octeon/cvmx-agl.c
diff --git a/arch/mips/mach-octeon/cvmx-agl.c b/arch/mips/mach-octeon/cvmx-agl.c
new file mode 100644
index ..9eea857e47c7
--- /dev/null
+++ b/arch/mips/mach-octeon/cvmx-agl.c
@@ -0,0 +1,216 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018-2022 Marvell International Ltd.
+ *
+ * Functions for RGMII (MGMT) initialization, configuration,
+ * and monitoring.
+ */
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+/*
+ * @param port to enable
+ *
+ * @return Zero on success, negative on failure
+ */
+int cvmx_agl_enable(int port)
+{
+ cvmx_agl_gmx_rxx_frm_ctl_t rxx_frm_ctl;
+
+ rxx_frm_ctl.u64 = 0;
+ rxx_frm_ctl.s.pre_align = 1;
+ /* When set, disables the length check for non-min sized pkts with
+* padding in the client data
+*/
+ rxx_frm_ctl.s.pad_len = 1;
+ /* When set, disables the length check for VLAN pkts */
+ rxx_frm_ctl.s.vlan_len = 1;
+ /* When set, PREAMBLE checking is less strict */
+ rxx_frm_ctl.s.pre_free = 1;
+ /* Control Pause Frames can match station SMAC */
+ rxx_frm_ctl.s.ctl_smac = 0;
+ /* Control Pause Frames can match globally assign Multicast address */
+ rxx_frm_ctl.s.ctl_mcst = 1;
+ rxx_frm_ctl.s.ctl_bck = 1; /* Forward pause information to TX block */
+ rxx_frm_ctl.s.ctl_drp = 1; /* Drop Control Pause Frames */
+ rxx_frm_ctl.s.pre_strp = 1; /* Strip off the preamble */
+ /* This port is configured to send PREAMBLE+SFD to begin every frame.
+* GMX checks that the PREAMBLE is sent correctly
+*/
+ rxx_frm_ctl.s.pre_chk = 1;
+ csr_wr(CVMX_AGL_GMX_RXX_FRM_CTL(port), rxx_frm_ctl.u64);
+
+ return 0;
+}
+
+cvmx_helper_link_info_t cvmx_agl_link_get(int port)
+{
+ cvmx_helper_link_info_t result;
+ int interface, port_index;
+
+ /* Fake IPD port is used on some older models. */
+ if (port < 0)
+ return __cvmx_helper_board_link_get(port);
+
+ /* Simulator does not have PHY, use some defaults. */
+ interface = cvmx_helper_get_interface_num(port);
+ port_index = cvmx_helper_get_interface_index_num(port);
+ if (cvmx_helper_get_port_force_link_up(interface, port_index)) {
+ result.u64 = 0;
+ result.s.full_duplex = 1;
+ result.s.link_up = 1;
+ result.s.speed = 1000;
+ return result;
+ }
+
+ return __cvmx_helper_board_link_get(port);
+}
+
+/*
+ * Set MII/RGMII link based on mode.
+ *
+ * @param port interface port to set the link.
+ * @param link_info Link status
+ *
+ * @return 0 on success and 1 on failure
+ */
+int cvmx_agl_link_set(int port, cvmx_helper_link_info_t link_info)
+{
+ cvmx_agl_gmx_prtx_cfg_t agl_gmx_prtx;
+
+ /* Disable GMX before we make any changes. */
+ agl_gmx_prtx.u64 = csr_rd(CVMX_AGL_GMX_PRTX_CFG(port));
+ agl_gmx_prtx.s.en = 0;
+ agl_gmx_prtx.s.tx_en = 0;
+ agl_gmx_prtx.s.rx_en = 0;
+ csr_wr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64);
+
+ if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_OCTEON3()) {
+ u64 one_second = 0x100; /* todo: this needs checking */
+
+ /* Wait for GMX to be idle */
+ if (CVMX_WAIT_FOR_FIELD64(CVMX_AGL_GMX_PRTX_CFG(port),
+ cvmx_agl_gmx_prtx_cfg_t, rx_idle, ==,
+ 1, one_second) ||
+ CVMX_WAIT_FOR_FIELD64(CVMX_AGL_GMX_PRTX_CFG(port),
+ cvmx_agl_gmx_prtx_cfg_t, tx_idle, ==,
+ 1, one_second)) {
+ debug("AGL%d: Timeout waiting for GMX to be idle\n",
+ port);
+ return -1;
+ }
+ }
+
+ agl_gmx_prtx.u64 = csr_rd(CVMX_AGL_GMX_PRTX_CFG(port));
+
+ /* Set duplex mode */
+ if (!link_info.s.link_up)
+ agl_gmx_prtx.s.duplex = 1; /* Force full duplex on down links */
+ else
+ agl_gmx_prtx.s.duplex = link_info.s.full_duplex;
+
+ switch (link_info.s.speed) {
+ case 10:
+ agl_gmx_prtx.s.speed = 0;
+ agl_gmx_prtx.s.slottime = 0;
+ if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_OCTEON3()) {
+ agl_gmx_prtx.s.s
[PATCH v2 19/52] mips: octeon: Add cvmx-helper-pko3.c
From: Aaron Williams
Import cvmx-helper-pko3.c from 2013 U-Boot. It will be used by the later
added drivers to support networking on the MIPS Octeon II / III
platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
arch/mips/mach-octeon/cvmx-helper-pko3.c | 1088 ++
1 file changed, 1088 insertions(+)
create mode 100644 arch/mips/mach-octeon/cvmx-helper-pko3.c
diff --git a/arch/mips/mach-octeon/cvmx-helper-pko3.c
b/arch/mips/mach-octeon/cvmx-helper-pko3.c
new file mode 100644
index ..37fe45d71f4b
--- /dev/null
+++ b/arch/mips/mach-octeon/cvmx-helper-pko3.c
@@ -0,0 +1,1088 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018-2022 Marvell International Ltd.
+ *
+ * PKOv3 helper file
+ */
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+/* channels are present at L2 queue level by default */
+static const enum cvmx_pko3_level_e cvmx_pko_default_channel_level =
+ CVMX_PKO_L2_QUEUES;
+
+static const int debug;
+
+static int __pko_pkt_budget, __pko_pkt_quota;
+
+/* These global variables are relevant for boot CPU only */
+static cvmx_fpa3_gaura_t __cvmx_pko3_aura[CVMX_MAX_NODES];
+
+/* This constant can not be modified, defined here for clarity only */
+#define CVMX_PKO3_POOL_BUFFER_SIZE 4096 /* 78XX PKO requires 4KB */
+
+/**
+ * @INTERNAL
+ *
+ * Build an owner tag based on interface/port
+ */
+static int __cvmx_helper_pko3_res_owner(int ipd_port)
+{
+ int res_owner;
+ const int res_owner_pfix = 0x19d0 << 14;
+
+ ipd_port &= 0x3fff; /* 12-bit for local CHAN_E value + node */
+
+ res_owner = res_owner_pfix | ipd_port;
+
+ return res_owner;
+}
+
+/**
+ * Configure an AURA/POOL designated for PKO internal use.
+ *
+ * This pool is used for (a) memory buffers that store PKO descriptor queues,
+ * (b) buffers for use with PKO_SEND_JUMP_S sub-header.
+ *
+ * The buffers of type (a) are never accessed by software, and their number
+ * should be at least equal to 4 times the number of descriptor queues
+ * in use.
+ *
+ * Type (b) buffers are consumed by PKO3 command-composition code,
+ * and are released by the hardware upon completion of transmission.
+ *
+ * @returns -1 if the pool could not be established or 12-bit AURA
+ * that includes the node number for use in PKO3 initialization call.
+ *
+ * NOTE: Linux kernel should pass its own aura to PKO3 initialization
+ * function so that the buffers can be mapped into kernel space
+ * for when software needs to adccess their contents.
+ *
+ */
+static int __cvmx_pko3_config_memory(unsigned int node)
+{
+ cvmx_fpa3_gaura_t aura;
+ int aura_num;
+ unsigned int buf_count;
+ bool small_mem;
+ int i, num_intf = 0;
+ const unsigned int pkt_per_buf =
+ (CVMX_PKO3_POOL_BUFFER_SIZE / sizeof(u64) / 16);
+ const unsigned int base_buf_count = 1024 * 4;
+
+ /* Simulator has limited memory, but uses one interface at a time */
+ // small_mem = cvmx_sysinfo_get()->board_type ==
CVMX_BOARD_TYPE_SIM;
+ small_mem = false;
+
+ /* Count the number of live interfaces */
+ for (i = 0; i < cvmx_helper_get_number_of_interfaces(); i++) {
+ int xiface = cvmx_helper_node_interface_to_xiface(node, i);
+
+ if (CVMX_HELPER_INTERFACE_MODE_DISABLED !=
+ cvmx_helper_interface_get_mode(xiface))
+ num_intf++;
+ }
+
+ buf_count = 1024;
+ __pko_pkt_quota = buf_count * pkt_per_buf;
+ __pko_pkt_budget = __pko_pkt_quota * num_intf;
+ (void)small_mem;
+ (void)base_buf_count;
+
+ if (debug)
+ debug("%s: Creating AURA with %u buffers for up to %d total
packets, %d packets per interface\n",
+ __func__, buf_count, __pko_pkt_budget, __pko_pkt_quota);
+
+ aura = cvmx_fpa3_setup_aura_and_pool(node, -1, "PKO3 AURA", NULL,
+CVMX_PKO3_POOL_BUFFER_SIZE,
+buf_count);
+
+ if (!__cvmx_fpa3_aura_valid(aura)) {
+ printf("ERROR: %s AURA create failed\n", __func__);
+ return -1;
+ }
+
+ aura_num = aura.node << 10 | aura.laura;
+
+ /* Store handle for destruction */
+ __cvmx_pko3_aura[node] = aura;
+
+ return aura_num;
+}
+
+/** Initialize a channelized port
+ * This is intended for LOOP, ILK and NPI interfaces which have one MAC
+ * per interface and need a channel per subinterface (e.g. ring).
+ * Each channel then
[PATCH v2 15/52] mips: octeon: Add cvmx-helper-loop.c
From: Aaron Williams
Import cvmx-helper-loop.c from 2013 U-Boot. It will be used by the later
added drivers to support networking on the MIPS Octeon II / III
platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
arch/mips/mach-octeon/cvmx-helper-loop.c | 178 +++
1 file changed, 178 insertions(+)
create mode 100644 arch/mips/mach-octeon/cvmx-helper-loop.c
diff --git a/arch/mips/mach-octeon/cvmx-helper-loop.c
b/arch/mips/mach-octeon/cvmx-helper-loop.c
new file mode 100644
index ..8eaeac387df4
--- /dev/null
+++ b/arch/mips/mach-octeon/cvmx-helper-loop.c
@@ -0,0 +1,178 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018-2022 Marvell International Ltd.
+ *
+ * Functions for LOOP initialization, configuration,
+ * and monitoring.
+ */
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+int __cvmx_helper_loop_enumerate(int xiface)
+{
+ return OCTEON_IS_MODEL(OCTEON_CN68XX) ?
+ 8 : (OCTEON_IS_MODEL(OCTEON_CNF71XX) ? 2 : 4);
+}
+
+/**
+ * @INTERNAL
+ * Probe a LOOP interface and determine the number of ports
+ * connected to it. The LOOP interface should still be down
+ * after this call.
+ *
+ * @param xiface Interface to probe
+ *
+ * @return Number of ports on the interface. Zero to disable.
+ */
+int __cvmx_helper_loop_probe(int xiface)
+{
+ return __cvmx_helper_loop_enumerate(xiface);
+}
+
+/**
+ * @INTERNAL
+ * Bringup and enable a LOOP interface. After this call packet
+ * I/O should be fully functional. This is called with IPD
+ * enabled but PKO disabled.
+ *
+ * @param interface to bring up
+ *
+ * @return Zero on success, negative on failure
+ */
+int __cvmx_helper_loop_enable(int xiface)
+{
+ cvmx_pip_prt_cfgx_t port_cfg;
+ int num_ports, index;
+ unsigned long offset;
+ struct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);
+
+ num_ports = __cvmx_helper_get_num_ipd_ports(xiface);
+ /*
+* We need to disable length checking so packet < 64 bytes and jumbo
+* frames don't get errors
+*/
+ for (index = 0; index < num_ports; index++) {
+ offset = ((octeon_has_feature(OCTEON_FEATURE_PKND)) ?
+ cvmx_helper_get_pknd(xiface, index) :
+ cvmx_helper_get_ipd_port(xiface,
index));
+
+ if (octeon_has_feature(OCTEON_FEATURE_PKI)) {
+ cvmx_pki_endis_l2_errs(xi.node, offset, 1, 0, 0);
+ cvmx_pki_endis_fcs_check(xi.node, offset, 0, 0);
+ } else {
+ port_cfg.u64 = csr_rd(CVMX_PIP_PRT_CFGX(offset));
+ port_cfg.s.maxerr_en = 0;
+ port_cfg.s.minerr_en = 0;
+ csr_wr(CVMX_PIP_PRT_CFGX(offset), port_cfg.u64);
+ }
+ }
+
+ /*
+* Disable FCS stripping for loopback ports
+*/
+ if (!octeon_has_feature(OCTEON_FEATURE_PKND)) {
+ cvmx_ipd_sub_port_fcs_t ipd_sub_port_fcs;
+
+ ipd_sub_port_fcs.u64 = csr_rd(CVMX_IPD_SUB_PORT_FCS);
+ ipd_sub_port_fcs.s.port_bit2 = 0;
+ csr_wr(CVMX_IPD_SUB_PORT_FCS, ipd_sub_port_fcs.u64);
+ }
+ /*
+* Set PKND and BPID for loopback ports.
+*/
+ if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
+ cvmx_pko_reg_loopback_pkind_t lp_pknd;
+ cvmx_pko_reg_loopback_bpid_t lp_bpid;
+
+ for (index = 0; index < num_ports; index++) {
+ int pknd = cvmx_helper_get_pknd(xiface, index);
+ int bpid = cvmx_helper_get_bpid(xiface, index);
+
+ lp_pknd.u64 = csr_rd(CVMX_PKO_REG_LOOPBACK_PKIND);
+ lp_bpid.u64 = csr_rd(CVMX_PKO_REG_LOOPBACK_BPID);
+
+ if (index == 0)
+ lp_pknd.s.num_ports = num_ports;
+
+ switch (index) {
+ case 0:
+ lp_pknd.s.pkind0 = pknd;
+ lp_bpid.s.bpid0 = bpid;
+ break;
+ case 1:
+ lp_pknd.s.pkind1 = pknd;
+ lp_bpid.s.bpid1 = bpid;
+ break;
+ case 2:
+ lp_pknd.s.pkind2 = pknd;
+ lp_bpid.s.bpid2 = bpid;
+ break;
+ case 3:
+ lp_pknd.s.pkind3 = pknd;
+ lp_bpid.s.bpid3
[PATCH v2 21/52] mips: octeon: Add cvmx-helper-sgmii.c
From: Aaron Williams
Import cvmx-helper-sgmii.c from 2013 U-Boot. It will be used by the later
added drivers to support networking on the MIPS Octeon II / III
platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
arch/mips/mach-octeon/cvmx-helper-sgmii.c | 781 ++
1 file changed, 781 insertions(+)
create mode 100644 arch/mips/mach-octeon/cvmx-helper-sgmii.c
diff --git a/arch/mips/mach-octeon/cvmx-helper-sgmii.c
b/arch/mips/mach-octeon/cvmx-helper-sgmii.c
new file mode 100644
index ..b789ad5d1913
--- /dev/null
+++ b/arch/mips/mach-octeon/cvmx-helper-sgmii.c
@@ -0,0 +1,781 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018-2022 Marvell International Ltd.
+ *
+ * Functions for SGMII initialization, configuration,
+ * and monitoring.
+ */
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+/**
+ * @INTERNAL
+ * Perform initialization required only once for an SGMII port.
+ *
+ * @param interface to init
+ * @param index Index of prot on the interface
+ *
+ * @return Zero on success, negative on failure
+ */
+static int __cvmx_helper_sgmii_hardware_init_one_time(int interface, int index)
+{
+ const u64 clock_mhz = 1200; /* todo: fixme */
+ union cvmx_pcsx_miscx_ctl_reg pcsx_miscx_ctl_reg;
+ union cvmx_pcsx_linkx_timer_count_reg pcsx_linkx_timer_count_reg;
+ union cvmx_gmxx_prtx_cfg gmxx_prtx_cfg;
+
+ if (!cvmx_helper_is_port_valid(interface, index))
+ return 0;
+
+ /* Disable GMX */
+ gmxx_prtx_cfg.u64 = csr_rd(CVMX_GMXX_PRTX_CFG(index, interface));
+ gmxx_prtx_cfg.s.en = 0;
+ csr_wr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64);
+
+ /*
+* Write PCS*_LINK*_TIMER_COUNT_REG[COUNT] with the
+* appropriate value. 1000BASE-X specifies a 10ms
+* interval. SGMII specifies a 1.6ms interval.
+*/
+ pcsx_miscx_ctl_reg.u64 =
+ csr_rd(CVMX_PCSX_MISCX_CTL_REG(index, interface));
+ /* Adjust the MAC mode if requested by device tree */
+ pcsx_miscx_ctl_reg.s.mac_phy =
+ cvmx_helper_get_mac_phy_mode(interface, index);
+ pcsx_miscx_ctl_reg.s.mode =
+ cvmx_helper_get_1000x_mode(interface, index);
+ csr_wr(CVMX_PCSX_MISCX_CTL_REG(index, interface),
+ pcsx_miscx_ctl_reg.u64);
+
+ pcsx_linkx_timer_count_reg.u64 =
+ csr_rd(CVMX_PCSX_LINKX_TIMER_COUNT_REG(index, interface));
+ if (pcsx_miscx_ctl_reg.s.mode)
+ /* 1000BASE-X */
+ pcsx_linkx_timer_count_reg.s.count =
+ (1ull * clock_mhz) >> 10;
+ else
+ /* SGMII */
+ pcsx_linkx_timer_count_reg.s.count =
+ (1600ull * clock_mhz) >> 10;
+
+ csr_wr(CVMX_PCSX_LINKX_TIMER_COUNT_REG(index, interface),
+ pcsx_linkx_timer_count_reg.u64);
+
+ /*
+* Write the advertisement register to be used as the
+* tx_Config_Reg of the autonegotiation. In
+* 1000BASE-X mode, tx_Config_Reg is PCS*_AN*_ADV_REG.
+* In SGMII PHY mode, tx_Config_Reg is
+* PCS*_SGM*_AN_ADV_REG. In SGMII MAC mode,
+* tx_Config_Reg is the fixed value 0x4001, so this
+* step can be skipped.
+*/
+ if (pcsx_miscx_ctl_reg.s.mode) {
+ /* 1000BASE-X */
+ union cvmx_pcsx_anx_adv_reg pcsx_anx_adv_reg;
+
+ pcsx_anx_adv_reg.u64 =
+ csr_rd(CVMX_PCSX_ANX_ADV_REG(index, interface));
+ pcsx_anx_adv_reg.s.rem_flt = 0;
+ pcsx_anx_adv_reg.s.pause = 3;
+ pcsx_anx_adv_reg.s.hfd = 1;
+ pcsx_anx_adv_reg.s.fd = 1;
+ csr_wr(CVMX_PCSX_ANX_ADV_REG(index, interface),
+ pcsx_anx_adv_reg.u64);
+ } else {
+ if (pcsx_miscx_ctl_reg.s.mac_phy) {
+ /* PHY Mode */
+ union cvmx_pcsx_sgmx_an_adv_reg pcsx_sgmx_an_adv_reg;
+
+ pcsx_sgmx_an_adv_reg.u64 = csr_rd(
+ CVMX_PCSX_SGMX_AN_ADV_REG(index, interface));
+ pcsx_sgmx_an_adv_reg.s.dup = 1;
+ pcsx_sgmx_an_adv_reg.s.speed = 2;
+ csr_wr(CVMX_PCSX_SGMX_AN_ADV_REG(index, interface),
+ pcsx_sgmx_an_adv_reg.u64);
+ } else {
+ /* MAC Mode - Nothing to do */
+ }
+ }
+ return 0;
+}
+
+static int __cvmx_helper_need_g15618(void)
+{
+ if (OCTEON_IS_MODEL(OCTEON_CN63XX) ||
+ OCTEON_IS_MODEL(OCTEON_CN66XX_PASS1_X) ||
+ OCTEON_IS_MODEL(OCTEON_CN68XX))
+
[PATCH v2 13/52] mips: octeon: Add cvmx-helper-ilk.c
From: Aaron Williams
Import cvmx-helper-ilk.c from 2013 U-Boot. It will be used by the later
added drivers to support networking on the MIPS Octeon II / III
platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
arch/mips/mach-octeon/cvmx-helper-ilk.c | 902
1 file changed, 902 insertions(+)
create mode 100644 arch/mips/mach-octeon/cvmx-helper-ilk.c
diff --git a/arch/mips/mach-octeon/cvmx-helper-ilk.c
b/arch/mips/mach-octeon/cvmx-helper-ilk.c
new file mode 100644
index ..9e882f133323
--- /dev/null
+++ b/arch/mips/mach-octeon/cvmx-helper-ilk.c
@@ -0,0 +1,902 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018-2022 Marvell International Ltd.
+ *
+ * Functions for ILK initialization, configuration,
+ * and monitoring.
+ */
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+int __cvmx_helper_ilk_enumerate(int xiface)
+{
+ struct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);
+
+ xi.interface -= CVMX_ILK_GBL_BASE();
+ return cvmx_ilk_chans[xi.node][xi.interface];
+}
+
+/**
+ * @INTERNAL
+ * Initialize all tx calendar entries to the xoff state.
+ * Initialize all rx calendar entries to the xon state. The rx calendar entries
+ * must be in the xon state to allow new pko pipe assignments. If a calendar
+ * entry is assigned a different pko pipe while in the xoff state, the old pko
+ * pipe will stay in the xoff state even when no longer used by ilk.
+ *
+ * @param intf Interface whose calendar are to be initialized.
+ */
+static void __cvmx_ilk_clear_cal_cn78xx(int intf)
+{
+ cvmx_ilk_txx_cal_entryx_t tx_entry;
+ cvmx_ilk_rxx_cal_entryx_t rx_entry;
+ int i;
+ int node = (intf >> 4) & 0xf;
+ int interface = (intf & 0xf);
+
+ /* Initialize all tx calendar entries to off */
+ tx_entry.u64 = 0;
+ tx_entry.s.ctl = XOFF;
+ for (i = 0; i < CVMX_ILK_MAX_CAL; i++) {
+ csr_wr_node(node, CVMX_ILK_TXX_CAL_ENTRYX(i, interface),
+ tx_entry.u64);
+ }
+
+ /* Initialize all rx calendar entries to on */
+ rx_entry.u64 = 0;
+ rx_entry.s.ctl = XOFF;
+ for (i = 0; i < CVMX_ILK_MAX_CAL; i++) {
+ csr_wr_node(node, CVMX_ILK_RXX_CAL_ENTRYX(i, interface),
+ rx_entry.u64);
+ }
+}
+
+/**
+ * @INTERNAL
+ * Initialize all tx calendar entries to the xoff state.
+ * Initialize all rx calendar entries to the xon state. The rx calendar entries
+ * must be in the xon state to allow new pko pipe assignments. If a calendar
+ * entry is assigned a different pko pipe while in the xoff state, the old pko
+ * pipe will stay in the xoff state even when no longer used by ilk.
+ *
+ * @param interface whose calendar are to be initialized.
+ */
+static void __cvmx_ilk_clear_cal_cn68xx(int interface)
+{
+ cvmx_ilk_txx_idx_cal_t tx_idx;
+ cvmx_ilk_txx_mem_cal0_t tx_cal0;
+ cvmx_ilk_txx_mem_cal1_t tx_cal1;
+ cvmx_ilk_rxx_idx_cal_t rx_idx;
+ cvmx_ilk_rxx_mem_cal0_t rx_cal0;
+ cvmx_ilk_rxx_mem_cal1_t rx_cal1;
+ int i;
+
+ /*
+* First we initialize the tx calendar starting from entry 0,
+* incrementing the entry with every write.
+*/
+ tx_idx.u64 = 0;
+ tx_idx.s.inc = 1;
+ csr_wr(CVMX_ILK_TXX_IDX_CAL(interface), tx_idx.u64);
+
+ /* Set state to xoff for all entries */
+ tx_cal0.u64 = 0;
+ tx_cal0.s.entry_ctl0 = XOFF;
+ tx_cal0.s.entry_ctl1 = XOFF;
+ tx_cal0.s.entry_ctl2 = XOFF;
+ tx_cal0.s.entry_ctl3 = XOFF;
+
+ tx_cal1.u64 = 0;
+ tx_cal1.s.entry_ctl4 = XOFF;
+ tx_cal1.s.entry_ctl5 = XOFF;
+ tx_cal1.s.entry_ctl6 = XOFF;
+ tx_cal1.s.entry_ctl7 = XOFF;
+
+ /* Write all 288 entries */
+ for (i = 0; i < CVMX_ILK_MAX_CAL_IDX; i++) {
+ csr_wr(CVMX_ILK_TXX_MEM_CAL0(interface), tx_cal0.u64);
+ csr_wr(CVMX_ILK_TXX_MEM_CAL1(interface), tx_cal1.u64);
+ }
+
+ /*
+* Next we initialize the rx calendar starting from entry 0,
+* incrementing the entry with every write.
+*/
+ rx_idx.u64 = 0;
+ rx_idx.s.inc = 1;
+ csr_wr(CVMX_ILK_RXX_IDX_CAL(interface), rx_idx.u64);
+
+ /* Set state to xon for all entries */
+ rx_cal0.u64 = 0;
+ rx_cal0.s.entry_ctl0 = XON;
+ rx_cal0.s.entry_ctl1 = XON;
+ rx_cal0.s.entry_ctl2 = XON;
+ rx_cal0.s.entry_ctl3 = XON;
+
+ rx_cal1.u64 = 0;
+ rx_cal1.s.entry_ctl4 = XON;
+ rx_cal1.s.entry_ctl5 = XON;
+ rx_cal1.s.entry_ctl6 = XON;
+ rx_cal1.s.entry_ctl7 = XON;
+
+ /* Write all 28
[PATCH v2 03/52] mips: octeon: Add cvmx-iob-defs.h header file
From: Aaron Williams
Import cvmx-iob-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support networking on the MIPS Octeon II /
III platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
.../mach-octeon/include/mach/cvmx-iob-defs.h | 1328 +
1 file changed, 1328 insertions(+)
create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-iob-defs.h
diff --git a/arch/mips/mach-octeon/include/mach/cvmx-iob-defs.h
b/arch/mips/mach-octeon/include/mach/cvmx-iob-defs.h
new file mode 100644
index ..0af444daf418
--- /dev/null
+++ b/arch/mips/mach-octeon/include/mach/cvmx-iob-defs.h
@@ -0,0 +1,1328 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018-2022 Marvell International Ltd.
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon iob.
+ */
+
+#ifndef __CVMX_IOB_DEFS_H__
+#define __CVMX_IOB_DEFS_H__
+
+#define CVMX_IOB_BIST_STATUS (0x00011800F7F8ull)
+#define CVMX_IOB_CHIP_CUR_PWR (0x00011800F828ull)
+#define CVMX_IOB_CHIP_GLB_PWR_THROTTLE (0x00011800F808ull)
+#define CVMX_IOB_CHIP_PWR_OUT (0x00011800F818ull)
+#define CVMX_IOB_CTL_STATUS(0x00011800F050ull)
+#define CVMX_IOB_DWB_PRI_CNT (0x00011800F028ull)
+#define CVMX_IOB_FAU_TIMEOUT (0x00011800F000ull)
+#define CVMX_IOB_I2C_PRI_CNT (0x00011800F010ull)
+#define CVMX_IOB_INB_CONTROL_MATCH (0x00011800F078ull)
+#define CVMX_IOB_INB_CONTROL_MATCH_ENB (0x00011800F088ull)
+#define CVMX_IOB_INB_DATA_MATCH(0x00011800F070ull)
+#define CVMX_IOB_INB_DATA_MATCH_ENB(0x00011800F080ull)
+#define CVMX_IOB_INT_ENB (0x00011800F060ull)
+#define CVMX_IOB_INT_SUM (0x00011800F058ull)
+#define CVMX_IOB_N2C_L2C_PRI_CNT (0x00011800F020ull)
+#define CVMX_IOB_N2C_RSP_PRI_CNT (0x00011800F008ull)
+#define CVMX_IOB_OUTB_COM_PRI_CNT (0x00011800F040ull)
+#define CVMX_IOB_OUTB_CONTROL_MATCH(0x00011800F098ull)
+#define CVMX_IOB_OUTB_CONTROL_MATCH_ENB (0x00011800F0A8ull)
+#define CVMX_IOB_OUTB_DATA_MATCH (0x00011800F090ull)
+#define CVMX_IOB_OUTB_DATA_MATCH_ENB (0x00011800F0A0ull)
+#define CVMX_IOB_OUTB_FPA_PRI_CNT (0x00011800F048ull)
+#define CVMX_IOB_OUTB_REQ_PRI_CNT (0x00011800F038ull)
+#define CVMX_IOB_P2C_REQ_PRI_CNT (0x00011800F018ull)
+#define CVMX_IOB_PKT_ERR (0x00011800F068ull)
+#define CVMX_IOB_PP_BIST_STATUS(0x00011800F700ull)
+#define CVMX_IOB_TO_CMB_CREDITS(0x00011800F0B0ull)
+#define CVMX_IOB_TO_NCB_DID_00_CREDITS (0x00011800F800ull)
+#define CVMX_IOB_TO_NCB_DID_111_CREDITS (0x00011800FB78ull)
+#define CVMX_IOB_TO_NCB_DID_223_CREDITS (0x00011800FEF8ull)
+#define CVMX_IOB_TO_NCB_DID_24_CREDITS (0x00011800F8C0ull)
+#define CVMX_IOB_TO_NCB_DID_32_CREDITS (0x00011800F900ull)
+#define CVMX_IOB_TO_NCB_DID_40_CREDITS (0x00011800F940ull)
+#define CVMX_IOB_TO_NCB_DID_55_CREDITS (0x00011800F9B8ull)
+#define CVMX_IOB_TO_NCB_DID_64_CREDITS (0x00011800FA00ull)
+#define CVMX_IOB_TO_NCB_DID_79_CREDITS (0x00011800FA78ull)
+#define CVMX_IOB_TO_NCB_DID_96_CREDITS (0x00011800FB00ull)
+#define CVMX_IOB_TO_NCB_DID_98_CREDITS (0x00011800FB10ull)
+
+/**
+ * cvmx_iob_bist_status
+ *
+ * The result of the BIST run on the IOB memories.
+ *
+ */
+union cvmx_iob_bist_status {
+ u64 u64;
+ struct cvmx_iob_bist_status_s {
+ u64 reserved_2_63 : 62;
+ u64 ibd : 1;
+ u64 icd : 1;
+ } s;
+ struct cvmx_iob_bist_status_cn30xx {
+ u64 reserved_18_63 : 46;
+ u64 icnrcb : 1;
+ u64 icr0 : 1;
+ u64 icr1 : 1;
+ u64 icnr1 : 1;
+ u64 icnr0 : 1;
+ u64 ibdr0 : 1;
+ u64 ibdr1 : 1;
+ u64 ibr0 : 1;
+ u64 ibr1 : 1;
+ u64 icnrt : 1;
+ u64 ibrq0 : 1;
+ u64 ibrq1 : 1;
+ u64 icrn0 : 1;
+ u64 icrn1 : 1;
+ u64 icrp0 : 1;
+ u64 icrp1 : 1;
+ u64 ibd : 1;
+ u64 icd : 1;
+ } cn30xx;
+ struct cvmx_iob_bist_status_cn30xx cn31xx;
+ struct cvmx_iob_bist_status_cn30xx cn38xx;
+ struct cvmx_iob_bist_status_cn30xx cn38xxp2;
+ struct cvmx_iob_bist_status_cn30xx cn50xx;
+ struct cvmx_iob_bist_status_cn30xx cn52xx;
+ struct cvmx_iob_bist_status_cn30xx cn52xxp1;
+ struct cvmx_iob_bist_status_cn30xx cn56xx;
+ struct cvmx_iob_bist_status_cn30xx cn56xxp1;
+ struct cvmx_iob_bist_status_cn30xx cn58xx;
+ struct cvmx_iob_bist_status_cn30xx cn58xxp1;
+ struct cvmx_iob_bist_status_cn61xx {
+ u64 reserved_23_63 : 41;
+ u64 xmdfif : 1;
+
[PATCH 0/6] imx8mp: misc update
From: Peng Fan Support i.MX8MP UL part Disable fused IP drop legacy property when booting kernel Relocate U-Boot to higher address for System-Ready IR Peng Fan (5): imx: imx8mp: Add iMX8MP UltraLite Part cpu type imx: imx8mp: detect i.MX8MP UltraLite when get cpu rev imx: imx8mp: disable fused IP for UltraLite imx: imx8m: soc: runtime drop extcon property from usbotg node imx8m: soc: drop phy-reset-gpios for fec Ye Li (1): imx8m: soc: Relocate u-boot to the top DDR in 4GB space arch/arm/include/asm/arch-imx/cpu.h | 1 + arch/arm/include/asm/mach-imx/sys_proto.h | 3 +- arch/arm/mach-imx/cpu.c | 2 + arch/arm/mach-imx/imx8m/soc.c | 320 ++ 4 files changed, 266 insertions(+), 60 deletions(-) -- 2.35.1
[PATCH 2/6] imx: imx8mp: detect i.MX8MP UltraLite when get cpu rev
From: Peng Fan
Detect i.MX8MP UltraLite in get_cpu_variant_type
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx8m/soc.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 7397b99a1ee..f88296f7311 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -408,13 +408,27 @@ static u32 get_cpu_variant_type(u32 type)
/* npu disabled*/
if ((value & 0x8) == 0x8)
- flag |= (1 << 1);
+ flag |= BIT(1);
/* isp disabled */
if ((value & 0x3) == 0x3)
- flag |= (1 << 2);
+ flag |= BIT(2);
+
+ /* gpu disabled */
+ if ((value & 0xc0) == 0xc0)
+ flag |= BIT(3);
+
+ /* lvds disabled */
+ if ((value & 0x18) == 0x18)
+ flag |= BIT(4);
+
+ /* mipi dsi disabled */
+ if ((value & 0x6) == 0x6)
+ flag |= BIT(5);
switch (flag) {
+ case 0x3f:
+ return MXC_CPU_IMX8MPUL;
case 7:
return MXC_CPU_IMX8MPL;
case 2:
--
2.35.1
[PATCH 1/6] imx: imx8mp: Add iMX8MP UltraLite Part cpu type
From: Peng Fan Add i.MX8MP UltraLite Part CPU type Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-imx/cpu.h | 1 + arch/arm/include/asm/mach-imx/sys_proto.h | 3 ++- arch/arm/mach-imx/cpu.c | 2 ++ 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index fe963789710..4f63803765e 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -47,6 +47,7 @@ #define MXC_CPU_IMX8MP60x186 /* dummy ID */ #define MXC_CPU_IMX8MPL0x187 /* dummy ID */ #define MXC_CPU_IMX8MPD0x188 /* dummy ID */ +#define MXC_CPU_IMX8MPUL 0x189 /* dummy ID */ #define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */ #define MXC_CPU_IMX8QM 0x91 /* dummy ID */ #define MXC_CPU_IMX8QXP0x92 /* dummy ID */ diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index 37fd427cc00..940864aaeb7 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -73,10 +73,11 @@ struct bd_info; #define is_imx8mnud() (is_cpu_type(MXC_CPU_IMX8MNUD)) #define is_imx8mnus() (is_cpu_type(MXC_CPU_IMX8MNUS)) #define is_imx8mp() (is_cpu_type(MXC_CPU_IMX8MP) || is_cpu_type(MXC_CPU_IMX8MPD) || \ - is_cpu_type(MXC_CPU_IMX8MPL) || is_cpu_type(MXC_CPU_IMX8MP6)) + is_cpu_type(MXC_CPU_IMX8MPL) || is_cpu_type(MXC_CPU_IMX8MP6) || is_cpu_type(MXC_CPU_IMX8MPUL)) #define is_imx8mpd() (is_cpu_type(MXC_CPU_IMX8MPD)) #define is_imx8mpl() (is_cpu_type(MXC_CPU_IMX8MPL)) #define is_imx8mp6() (is_cpu_type(MXC_CPU_IMX8MP6)) +#define is_imx8mpul() (is_cpu_type(MXC_CPU_IMX8MPUL)) #define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP)) diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index 8eb05c8dd67..ba386c24b4a 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -106,6 +106,8 @@ const char *get_imx_type(u32 imxtype) return "8MP Lite[4]"; /* Quad-core Lite version of the imx8mp */ case MXC_CPU_IMX8MP6: return "8MP[6]";/* Quad-core version of the imx8mp, NPU fused */ + case MXC_CPU_IMX8MPUL: + return "8MP UltraLite"; /* Quad-core UltraLite version of the imx8mp */ case MXC_CPU_IMX8MN: return "8MNano Quad"; /* Quad-core version */ case MXC_CPU_IMX8MND: -- 2.35.1
[PATCH 3/6] imx: imx8mp: disable fused IP for UltraLite
From: Peng Fan
Beside the fused modules on iMX8MP Lite, this part has also fused
GPU3D/2D, LVDS and MIPI DSI.
So we have to disable them for kernel and also disable MIPI DSI
in u-boot DTS for splash screen at runtime.
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx8m/soc.c | 147 --
1 file changed, 142 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index f88296f7311..0ab55765c7c 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -907,6 +907,90 @@ static int low_drive_gpu_freq(void *blob)
}
#endif
+static bool check_remote_endpoint(void *blob, const char *ep1, const char *ep2)
+{
+ int lookup_node;
+ int nodeoff;
+
+ nodeoff = fdt_path_offset(blob, ep1);
+ if (nodeoff) {
+ lookup_node = fdtdec_lookup_phandle(blob, nodeoff,
"remote-endpoint");
+ nodeoff = fdt_path_offset(blob, ep2);
+
+ if (nodeoff > 0 && nodeoff == lookup_node)
+ return true;
+ }
+
+ return false;
+}
+
+int disable_dsi_lcdif_nodes(void *blob)
+{
+ int ret;
+
+ static const char * const dsi_path_8mp[] = {
+ "/soc@0/bus@32c0/mipi_dsi@32e6"
+ };
+
+ static const char * const lcdif_path_8mp[] = {
+ "/soc@0/bus@32c0/lcd-controller@32e8"
+ };
+
+ static const char * const lcdif_ep_path_8mp[] = {
+ "/soc@0/bus@32c0/lcd-controller@32e8/port@0/endpoint"
+ };
+ static const char * const dsi_ep_path_8mp[] = {
+ "/soc@0/bus@32c0/mipi_dsi@32e6/port@0/endpoint"
+ };
+
+ ret = disable_fdt_nodes(blob, dsi_path_8mp, ARRAY_SIZE(dsi_path_8mp));
+ if (ret)
+ return ret;
+
+ if (check_remote_endpoint(blob, dsi_ep_path_8mp[0],
lcdif_ep_path_8mp[0])) {
+ /* Disable lcdif node */
+ return disable_fdt_nodes(blob, lcdif_path_8mp,
ARRAY_SIZE(lcdif_path_8mp));
+ }
+
+ return 0;
+}
+
+int disable_lvds_lcdif_nodes(void *blob)
+{
+ int ret, i;
+
+ static const char * const ldb_path_8mp[] = {
+ "/soc@0/bus@32c0/ldb@32ec005c",
+ "/soc@0/bus@32c0/phy@32ec0128"
+ };
+
+ static const char * const lcdif_path_8mp[] = {
+ "/soc@0/bus@32c0/lcd-controller@32e9"
+ };
+
+ static const char * const lcdif_ep_path_8mp[] = {
+ "/soc@0/bus@32c0/lcd-controller@32e9/port@0/endpoint@0",
+ "/soc@0/bus@32c0/lcd-controller@32e9/port@0/endpoint@1"
+ };
+ static const char * const ldb_ep_path_8mp[] = {
+
"/soc@0/bus@32c0/ldb@32ec005c/lvds-channel@0/port@0/endpoint",
+
"/soc@0/bus@32c0/ldb@32ec005c/lvds-channel@1/port@0/endpoint"
+ };
+
+ ret = disable_fdt_nodes(blob, ldb_path_8mp, ARRAY_SIZE(ldb_path_8mp));
+ if (ret)
+ return ret;
+
+ for (i = 0; i < ARRAY_SIZE(ldb_ep_path_8mp); i++) {
+ if (check_remote_endpoint(blob, ldb_ep_path_8mp[i],
lcdif_ep_path_8mp[i])) {
+ /* Disable lcdif node */
+ return disable_fdt_nodes(blob, lcdif_path_8mp,
ARRAY_SIZE(lcdif_path_8mp));
+ }
+ }
+
+ return 0;
+}
+
int disable_gpu_nodes(void *blob)
{
static const char * const nodes_path_8mn[] = {
@@ -914,7 +998,15 @@ int disable_gpu_nodes(void *blob)
"/soc@/gpu@3800"
};
- return disable_fdt_nodes(blob, nodes_path_8mn,
ARRAY_SIZE(nodes_path_8mn));
+ static const char * const nodes_path_8mp[] = {
+ "/gpu3d@3800",
+ "/gpu2d@38008000"
+ };
+
+ if (is_imx8mp())
+ return disable_fdt_nodes(blob, nodes_path_8mp,
ARRAY_SIZE(nodes_path_8mp));
+ else
+ return disable_fdt_nodes(blob, nodes_path_8mn,
ARRAY_SIZE(nodes_path_8mn));
}
int disable_npu_nodes(void *blob)
@@ -1170,16 +1262,27 @@ usb_modify_speed:
disable_cpu_nodes(blob, 3);
#elif defined(CONFIG_IMX8MP)
- if (is_imx8mpl())
+ if (is_imx8mpul()) {
+ /* Disable GPU */
+ disable_gpu_nodes(blob);
+
+ /* Disable DSI */
+ disable_dsi_lcdif_nodes(blob);
+
+ /* Disable LVDS */
+ disable_lvds_lcdif_nodes(blob);
+ }
+
+ if (is_imx8mpul() || is_imx8mpl())
disable_vpu_nodes(blob);
- if (is_imx8mpl() || is_imx8mp6())
+ if (is_imx8mpul() || is_imx8mpl() || is_imx8mp6())
disable_npu_nodes(blob);
- if (is_imx8mpl())
+ if (is_imx8mpul() || is_imx8mpl())
disable_isp_nodes(blob);
- if (is_imx8mpl() || is_imx8mp6())
+ if (is_imx8mpul() || is_imx8mpl() || is_imx8mp6())
[PATCH 4/6] imx: imx8m: soc: runtime drop extcon property from usbotg node
From: Peng Fan
The extcon is an decrepted property and not used by upstream Linux and
NXP 5.10 kernel, so we remove it before kicking linux in case it is in
dts. Otherwise distro kernel will not able to have usb function.
Reviewed-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx8m/soc.c | 33 +
1 file changed, 33 insertions(+)
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 0ab55765c7c..e76d75269d7 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -1148,6 +1148,37 @@ static int disable_cpu_nodes(void *blob, u32
disabled_cores)
return 0;
}
+#if defined(CONFIG_IMX8MM)
+static int cleanup_nodes_for_efi(void *blob)
+{
+ static const char * const usbotg_path[] = {
+ "/soc@0/bus@32c0/usb@32e4",
+ "/soc@0/bus@32c0/usb@32e5"
+ };
+ int nodeoff, i, rc;
+
+ for (i = 0; i < ARRAY_SIZE(usbotg_path); i++) {
+ nodeoff = fdt_path_offset(blob, usbotg_path[i]);
+ if (nodeoff < 0)
+ continue; /* Not found, skip it */
+ debug("Found %s node\n", usbotg_path[i]);
+
+ rc = fdt_delprop(blob, nodeoff, "extcon");
+ if (rc == -FDT_ERR_NOTFOUND)
+ continue;
+ if (rc) {
+ printf("Unable to update property %s:%s, err=%s\n",
+ usbotg_path[i], "extcon", fdt_strerror(rc));
+ return rc;
+ }
+
+ printf("Remove %s:%s\n", usbotg_path[i], "extcon");
+ }
+
+ return 0;
+}
+#endif
+
int ft_system_setup(void *blob, struct bd_info *bd)
{
#ifdef CONFIG_IMX8MQ
@@ -1242,6 +1273,8 @@ usb_modify_speed:
else if (is_imx8mms() || is_imx8mmsl())
disable_cpu_nodes(blob, 3);
+ cleanup_nodes_for_efi(blob);
+
#elif defined(CONFIG_IMX8MN)
if (is_imx8mnl() || is_imx8mndl() || is_imx8mnsl())
disable_gpu_nodes(blob);
--
2.35.1
[PATCH 6/6] imx8m: soc: Relocate u-boot to the top DDR in 4GB space
From: Ye Li
The EFI memory init uses gd->ram_top for conventional memory. In
current implementation, the ram_top is below optee address. This cause
grub failed to allocation memory for initrd.
The change updates DDR bank setup functions to place the u-boot at top
DDR in 4GB space.
Reviewed-by: Peng Fan
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx8m/soc.c | 123 --
1 file changed, 71 insertions(+), 52 deletions(-)
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 5a6872dda61..c83651d43d1 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -188,32 +188,29 @@ static unsigned int imx8m_find_dram_entry_in_mem_map(void)
void enable_caches(void)
{
- /* If OPTEE runs, remove OPTEE memory from MMU table to avoid
speculative prefetch */
- if (rom_pointer[1]) {
- /*
-* TEE are loaded, So the ddr bank structures
-* have been modified update mmu table accordingly
-*/
- int i = 0;
- /*
-* please make sure that entry initial value matches
-* imx8m_mem_map for DRAM1
-*/
- int entry = imx8m_find_dram_entry_in_mem_map();
- u64 attrs = imx8m_mem_map[entry].attrs;
-
- while (i < CONFIG_NR_DRAM_BANKS &&
- entry < ARRAY_SIZE(imx8m_mem_map)) {
- if (gd->bd->bi_dram[i].start == 0)
- break;
- imx8m_mem_map[entry].phys = gd->bd->bi_dram[i].start;
- imx8m_mem_map[entry].virt = gd->bd->bi_dram[i].start;
- imx8m_mem_map[entry].size = gd->bd->bi_dram[i].size;
- imx8m_mem_map[entry].attrs = attrs;
- debug("Added memory mapping (%d): %llx %llx\n", entry,
- imx8m_mem_map[entry].phys,
imx8m_mem_map[entry].size);
- i++; entry++;
- }
+ /* If OPTEE runs, remove OPTEE memory from MMU table to avoid
speculative prefetch
+* If OPTEE does not run, still update the MMU table according to dram
banks structure
+* to set correct dram size from board_phys_sdram_size
+*/
+ int i = 0;
+ /*
+* please make sure that entry initial value matches
+* imx8m_mem_map for DRAM1
+*/
+ int entry = imx8m_find_dram_entry_in_mem_map();
+ u64 attrs = imx8m_mem_map[entry].attrs;
+
+ while (i < CONFIG_NR_DRAM_BANKS &&
+ entry < ARRAY_SIZE(imx8m_mem_map)) {
+ if (gd->bd->bi_dram[i].start == 0)
+ break;
+ imx8m_mem_map[entry].phys = gd->bd->bi_dram[i].start;
+ imx8m_mem_map[entry].virt = gd->bd->bi_dram[i].start;
+ imx8m_mem_map[entry].size = gd->bd->bi_dram[i].size;
+ imx8m_mem_map[entry].attrs = attrs;
+ debug("Added memory mapping (%d): %llx %llx\n", entry,
+ imx8m_mem_map[entry].phys, imx8m_mem_map[entry].size);
+ i++; entry++;
}
icache_enable();
@@ -226,12 +223,15 @@ __weak int board_phys_sdram_size(phys_size_t *size)
return -EINVAL;
*size = PHYS_SDRAM_SIZE;
+
+#ifdef PHYS_SDRAM_2_SIZE
+ *size += PHYS_SDRAM_2_SIZE;
+#endif
return 0;
}
int dram_init(void)
{
- unsigned int entry = imx8m_find_dram_entry_in_mem_map();
phys_size_t sdram_size;
int ret;
@@ -245,13 +245,6 @@ int dram_init(void)
else
gd->ram_size = sdram_size;
- /* also update the SDRAM size in the mem_map used externally */
- imx8m_mem_map[entry].size = sdram_size;
-
-#ifdef PHYS_SDRAM_2_SIZE
- gd->ram_size += PHYS_SDRAM_2_SIZE;
-#endif
-
return 0;
}
@@ -260,18 +253,28 @@ int dram_init_banksize(void)
int bank = 0;
int ret;
phys_size_t sdram_size;
+ phys_size_t sdram_b1_size, sdram_b2_size;
ret = board_phys_sdram_size(&sdram_size);
if (ret)
return ret;
+ /* Bank 1 can't cross over 4GB space */
+ if (sdram_size > 0xc000) {
+ sdram_b1_size = 0xc000;
+ sdram_b2_size = sdram_size - 0xc000;
+ } else {
+ sdram_b1_size = sdram_size;
+ sdram_b2_size = 0;
+ }
+
gd->bd->bi_dram[bank].start = PHYS_SDRAM;
if (rom_pointer[1]) {
phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
phys_size_t optee_size = (size_t)rom_pointer[1];
gd->bd->bi_dram[bank].size = optee_start -
gd->bd->bi_dram[bank].start;
- if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_size)) {
+ if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) {
[PATCH 5/6] imx8m: soc: drop phy-reset-gpios for fec
From: Peng Fan
Need to drop phy-reset-gpios before booting linux, this property
is legacy property and replaced with reset-gpios.
If provide both, kernel would failed to request the same gpio twice
and cause fec not work.
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx8m/soc.c | 27 +--
1 file changed, 13 insertions(+), 14 deletions(-)
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index e76d75269d7..5a6872dda61 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -1148,36 +1148,36 @@ static int disable_cpu_nodes(void *blob, u32
disabled_cores)
return 0;
}
-#if defined(CONFIG_IMX8MM)
static int cleanup_nodes_for_efi(void *blob)
{
- static const char * const usbotg_path[] = {
- "/soc@0/bus@32c0/usb@32e4",
- "/soc@0/bus@32c0/usb@32e5"
- };
+ static const char * const path[][2] = {
+ { "/soc@0/bus@32c0/usb@32e4", "extcon" },
+ { "/soc@0/bus@32c0/usb@32e5", "extcon" },
+ { "/soc@0/bus@3080/ethernet@30be", "phy-reset-gpios" },
+ { "/soc@0/bus@3080/ethernet@30bf", "phy-reset-gpios" }
+ };
int nodeoff, i, rc;
- for (i = 0; i < ARRAY_SIZE(usbotg_path); i++) {
- nodeoff = fdt_path_offset(blob, usbotg_path[i]);
+ for (i = 0; i < ARRAY_SIZE(path); i++) {
+ nodeoff = fdt_path_offset(blob, path[i][0]);
if (nodeoff < 0)
continue; /* Not found, skip it */
- debug("Found %s node\n", usbotg_path[i]);
+ debug("Found %s node\n", path[i][0]);
- rc = fdt_delprop(blob, nodeoff, "extcon");
+ rc = fdt_delprop(blob, nodeoff, path[i][1]);
if (rc == -FDT_ERR_NOTFOUND)
continue;
if (rc) {
printf("Unable to update property %s:%s, err=%s\n",
- usbotg_path[i], "extcon", fdt_strerror(rc));
+ path[i][0], path[i][1], fdt_strerror(rc));
return rc;
}
- printf("Remove %s:%s\n", usbotg_path[i], "extcon");
+ printf("Remove %s:%s\n", path[i][0], path[i][1]);
}
return 0;
}
-#endif
int ft_system_setup(void *blob, struct bd_info *bd)
{
@@ -1273,8 +1273,6 @@ usb_modify_speed:
else if (is_imx8mms() || is_imx8mmsl())
disable_cpu_nodes(blob, 3);
- cleanup_nodes_for_efi(blob);
-
#elif defined(CONFIG_IMX8MN)
if (is_imx8mnl() || is_imx8mndl() || is_imx8mnsl())
disable_gpu_nodes(blob);
@@ -1322,6 +1320,7 @@ usb_modify_speed:
disable_cpu_nodes(blob, 2);
#endif
+ cleanup_nodes_for_efi(blob);
return 0;
}
#endif
--
2.35.1
Re: [PATCH 08/11] virtio: sandbox: Bind RNG rather than block device
On 3/31/22 12:09, Andrew Scull wrote:
The virtio-rng driver is extremely simple, making it suitable for
testing more of the virtio uclass logic. Have the sandbox driver bind
the virtio-rng driver rather than the virtio-blk driver so it can be
used in tests.
test/dm/rng.c assumes that drivers/rng/sandbox_rng.c is providing the
only RNG device.
Does test/dm/virtio.c guarantee that no virtio-rng device is bound after
the test is run?
Best regards
Heinrich
Signed-off-by: Andrew Scull
---
drivers/virtio/virtio_sandbox.c | 2 +-
test/dm/virtio.c| 8
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/virtio/virtio_sandbox.c b/drivers/virtio/virtio_sandbox.c
index a73b123454..5484ae3a1a 100644
--- a/drivers/virtio/virtio_sandbox.c
+++ b/drivers/virtio/virtio_sandbox.c
@@ -161,7 +161,7 @@ static int virtio_sandbox_probe(struct udevice *udev)
/* fake some information for testing */
priv->device_features = BIT_ULL(VIRTIO_F_VERSION_1);
- uc_priv->device = VIRTIO_ID_BLOCK;
+ uc_priv->device = VIRTIO_ID_RNG;
uc_priv->vendor = ('u' << 24) | ('b' << 16) | ('o' << 8) | 't';
return 0;
diff --git a/test/dm/virtio.c b/test/dm/virtio.c
index d054ccfaa4..769945a0d8 100644
--- a/test/dm/virtio.c
+++ b/test/dm/virtio.c
@@ -25,10 +25,10 @@ static int dm_test_virtio_base(struct unit_test_state *uts)
ut_assertok(uclass_first_device(UCLASS_VIRTIO, &bus));
ut_assertnonnull(bus);
- /* check the child virtio-blk device is bound */
+ /* check the child virtio-rng device is bound */
ut_assertok(device_find_first_child(bus, &dev));
ut_assertnonnull(dev);
- ut_assertok(strcmp(dev->name, "virtio-blk#0"));
+ ut_asserteq_str("virtio-rng#0", dev->name);
/* check driver status */
ut_assertok(virtio_get_status(dev, &status));
@@ -54,7 +54,7 @@ static int dm_test_virtio_all_ops(struct unit_test_state *uts)
ut_assertok(uclass_first_device(UCLASS_VIRTIO, &bus));
ut_assertnonnull(bus);
- /* check the child virtio-blk device is bound */
+ /* check the child virtio-rng device is bound */
ut_assertok(device_find_first_child(bus, &dev));
ut_assertnonnull(dev);
@@ -114,7 +114,7 @@ static int dm_test_virtio_remove(struct unit_test_state
*uts)
ut_assertok(uclass_first_device(UCLASS_VIRTIO, &bus));
ut_assertnonnull(bus);
- /* check the child virtio-blk device is bound */
+ /* check the child virtio-rng device is bound */
ut_assertok(device_find_first_child(bus, &dev));
ut_assertnonnull(dev);
[PATCH v2 39/52] mips: octeon: Add cvmx-pko-internal-ports-range.c
From: Aaron Williams
Import cvmx-pko-internal-ports-range.c from 2013 U-Boot. It will be used
by the later added drivers to support networking on the MIPS Octeon II / III
platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
.../cvmx-pko-internal-ports-range.c | 99 +++
1 file changed, 99 insertions(+)
create mode 100644 arch/mips/mach-octeon/cvmx-pko-internal-ports-range.c
diff --git a/arch/mips/mach-octeon/cvmx-pko-internal-ports-range.c
b/arch/mips/mach-octeon/cvmx-pko-internal-ports-range.c
new file mode 100644
index ..694b4e3d9c55
--- /dev/null
+++ b/arch/mips/mach-octeon/cvmx-pko-internal-ports-range.c
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018-2022 Marvell International Ltd.
+ */
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+union interface_port {
+ struct {
+ int port;
+ int interface;
+ } s;
+ u64 u64;
+};
+
+static int dbg;
+
+static int port_range_init;
+
+int __cvmx_pko_internal_ports_range_init(void)
+{
+ int rv = 0;
+
+ if (port_range_init)
+ return 0;
+ port_range_init = 1;
+ rv = cvmx_create_global_resource_range(CVMX_GR_TAG_PKO_IPORTS,
+ CVMX_HELPER_CFG_MAX_PKO_QUEUES);
+ if (rv != 0)
+ debug("ERROR : Failed to initialize pko internal port range\n");
+ return rv;
+}
+
+int cvmx_pko_internal_ports_alloc(int xiface, int port, u64 count)
+{
+ int ret_val = -1;
+ union interface_port inf_port;
+ struct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);
+
+ __cvmx_pko_internal_ports_range_init();
+ inf_port.s.interface = xi.interface;
+ inf_port.s.port = port;
+ ret_val = cvmx_allocate_global_resource_range(CVMX_GR_TAG_PKO_IPORTS,
+ inf_port.u64, count, 1);
+ if (dbg)
+ debug("internal port alloc : port=%02d base=%02d count=%02d\n",
+ (int)port, ret_val, (int)count);
+ if (ret_val == -1)
+ return ret_val;
+ cvmx_cfg_port[xi.node][xi.interface][port].ccpp_pko_port_base = ret_val;
+ cvmx_cfg_port[xi.node][xi.interface][port].ccpp_pko_num_ports = count;
+ return 0;
+}
--
2.35.1
[PATCH v2 44/52] mips: octeon: cpu.c: Move bootmem init to arch_early_init_r()
Call octeon_bootmem_init() earlier in the boot process, so that this
bootmemory infrastructure is already initialized when e.g. the
networking support gets probed.
Signed-off-by: Stefan Roese
---
arch/mips/Kconfig | 1 +
arch/mips/mach-octeon/cpu.c | 13 -
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 06cae68ee576..9b62764f4fe6 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -101,6 +101,7 @@ config ARCH_JZ47XX
config ARCH_OCTEON
bool "Support Marvell Octeon CN7xxx platforms"
+ select ARCH_EARLY_INIT_R
select CPU_CAVIUM_OCTEON
select DISPLAY_CPUINFO
select DMA_ADDR_T_64BIT
diff --git a/arch/mips/mach-octeon/cpu.c b/arch/mips/mach-octeon/cpu.c
index 6cfcc3eae04e..fffd9dfb8580 100644
--- a/arch/mips/mach-octeon/cpu.c
+++ b/arch/mips/mach-octeon/cpu.c
@@ -393,14 +393,25 @@ static int init_bootcmd_console(void)
return ret;
}
-int arch_misc_init(void)
+int arch_early_init_r(void)
{
int ret;
+ /*
+* Needs to be called pretty early, so that e.g. networking etc
+* can access the bootmem infrastructure
+*/
ret = octeon_bootmem_init();
if (ret)
return ret;
+ return 0;
+}
+
+int arch_misc_init(void)
+{
+ int ret;
+
ret = octeon_configure_load_memory();
if (ret)
return ret;
--
2.35.1
[PATCH v2 35/52] mips: octeon: Add cvmx-pko3.c
From: Aaron Williams
Import cvmx-pko3.c from 2013 U-Boot. It will be used by the later
added drivers to support networking on the MIPS Octeon II / III
platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
arch/mips/mach-octeon/cvmx-pko3.c | 786 ++
1 file changed, 786 insertions(+)
create mode 100644 arch/mips/mach-octeon/cvmx-pko3.c
diff --git a/arch/mips/mach-octeon/cvmx-pko3.c
b/arch/mips/mach-octeon/cvmx-pko3.c
new file mode 100644
index ..d8ce02a2717a
--- /dev/null
+++ b/arch/mips/mach-octeon/cvmx-pko3.c
@@ -0,0 +1,786 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018-2022 Marvell International Ltd.
+ */
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+static const int debug;
+
+#define CVMX_DUMP_REGX(reg)\
+ if (debug) \
+ debug("%s=%#llx\n", #reg, (long long)csr_rd_node(node, reg))
+
+static int cvmx_pko_setup_macs(int node);
+
+/*
+ * PKO descriptor queue operation error string
+ *
+ * @param dqstatus is the enumeration returned from hardware,
+ * PKO_QUERY_RTN_S[DQSTATUS].
+ *
+ * @return static constant string error description
+ */
+const char *pko_dqstatus_error(pko_query_dqstatus_t dqstatus)
+{
+ char *str = "PKO Undefined error";
+
+ switch (dqstatus) {
+ case PKO_DQSTATUS_PASS:
+ str = "No error";
+ break;
+ case PKO_DQSTATUS_BADSTATE:
+ str = "PKO queue not ready";
+ break;
+ case PKO_DQSTATUS_NOFPABUF:
+ str = "PKO failed to allocate buffer from FPA";
+ break;
+ case PKO_DQSTATUS_NOPKOBUF:
+ str = "PKO out of buffers";
+ break;
+ case PKO_DQSTATUS_FAILRTNPTR:
+ str = "PKO failed to return buffer to FPA";
+ break;
+ case PKO_DQSTATUS_ALREADY:
+ str = "PKO queue already opened";
+ break;
+ case PKO_DQSTATUS_NOTCREATED:
+ str = "PKO queue has not been created";
+ break;
+ case PKO_DQSTATUS_NOTEMPTY:
+ str = "PKO queue is not empty";
+ break;
+ case PKO_DQSTATUS_SENDPKTDROP:
+ str = "Illegal PKO command construct";
+ break;
+ }
+ return str;
+}
+
+/*
+ * PKO global initialization for 78XX.
+ *
+ * @param node is the node on which PKO block is initialized.
+ * @return none.
+ */
+int cvmx_pko3_hw_init_global(int node, uint16_t aura)
+{
+ cvmx_pko_dpfi_flush_t pko_flush;
+ cvmx_pko_dpfi_fpa_aura_t pko_aura;
+ cvmx_pko_dpfi_ena_t dpfi_enable;
+ cvmx_pko_ptf_iobp_cfg_t ptf_iobp_cfg;
+ cvmx_pko_pdm_cfg_t pko_pdm_cfg;
+ cvmx_pko_enable_t pko_enable;
+ cvmx_pko_dpfi_status_t dpfi_status;
+ cvmx_pko_status_t pko_status;
+ cvmx_pko_shaper_cfg_t shaper_cfg;
+ u64 cycles;
+ const unsigned int timeout = 100; /* 100 milliseconds */
+
+ if (node != (aura >> 10))
+ cvmx_printf("WARNING: AURA vs PKO node mismatch\n");
+
+ pko_enable.u64 = csr_rd_node(node, CVMX_PKO_ENABLE);
+ if (pko_enable.s.enable) {
+ cvmx_printf("WARNING: %s: PKO already enabled on node %u\n",
+ __func__, node);
+ return 0;
+ }
+ /* Enable color awareness. */
+ shaper_cfg.u64 = csr_rd_node(node, CVMX_PKO_SHAPER_CFG);
+ shaper_cfg.s.color_aware = 1;
+ csr_wr_node(node, CVMX_PKO_SHAPER_CFG, shaper_cfg.u64);
+
+ /* Clear FLUSH command to be sure */
+ pko_flush.u64 = 0;
+ pko_flush.s.flush_en = 0;
+ csr_wr_node(node, CVMX_PKO_DPFI_FLUSH, pko_flush.u64);
+
+ /* set the aura number in pko, use aura node from parameter */
+ pko_aura.u64 = 0;
+ pko_aura.s.node = aura >> 10;
+ pko_aura.s.laura = aura;
+ csr_wr_node(node, CVMX_PKO_DPFI_FPA_AURA, pko_aura.u64);
+
+ CVMX_DUMP_REGX(CVMX_PKO_DPFI_FPA_AURA);
+
+ dpfi_enable.u64 = 0;
+ dpfi_enable.s.enable = 1;
+ csr_wr_node(node, CVMX_PKO_DPFI_ENA, dpfi_enable.u64);
+
+ /* Prepare timeout */
+ cycles = get_timer(0);
+
+ /* Wait until all pointers have been returned */
+ do {
+ pko_status.u64 = csr_rd_node(node, CVMX_PKO_STATUS);
+ if (get_timer(cycles) > timeout)
+ break;
+ } while (!pko_status.s.pko_rdy);
+
+ if (!pko_status.s.pko_rdy) {
+
[PATCH v2 30/52] mips: octeon: Add cvmx-ilk.c
From: Aaron Williams
Import cvmx-ilk.c from 2013 U-Boot. It will be used by the later
added drivers to support networking on the MIPS Octeon II / III
platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
arch/mips/mach-octeon/cvmx-ilk.c | 1199 ++
1 file changed, 1199 insertions(+)
create mode 100644 arch/mips/mach-octeon/cvmx-ilk.c
diff --git a/arch/mips/mach-octeon/cvmx-ilk.c b/arch/mips/mach-octeon/cvmx-ilk.c
new file mode 100644
index ..6223ff2c84b2
--- /dev/null
+++ b/arch/mips/mach-octeon/cvmx-ilk.c
@@ -0,0 +1,1199 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018-2022 Marvell International Ltd.
+ *
+ * Support library for the ILK
+ */
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+/*
+ * global configurations.
+ *
+ * for cn68, the default is {0xf, 0xf0}. to disable the 2nd ILK, set
+ * cvmx_ilk_lane_mask[CVMX_NUM_ILK_INTF] = {0xff, 0x0} and
+ * cvmx_ilk_chans[CVMX_NUM_ILK_INTF] = {8, 0}
+ */
+unsigned short cvmx_ilk_lane_mask[CVMX_MAX_NODES][CVMX_NUM_ILK_INTF] = {
+ [0 ... CVMX_MAX_NODES - 1] = { 0x000f, 0x00f0 }
+};
+
+int cvmx_ilk_chans[CVMX_MAX_NODES][CVMX_NUM_ILK_INTF] = {
+ [0 ... CVMX_MAX_NODES - 1] = { 8, 8 }
+};
+
+static cvmx_ilk_intf_t cvmx_ilk_intf_cfg[CVMX_MAX_NODES][CVMX_NUM_ILK_INTF];
+
+cvmx_ilk_LA_mode_t cvmx_ilk_LA_mode[CVMX_NUM_ILK_INTF] = { { 0, 0 }, { 0, 0 }
};
+/**
+ * User-overrideable callback function that returns whether or not an interface
+ * should use look-aside mode.
+ *
+ * @param interface - interface being checked
+ * @param channel - channel number, can be 0 or 1 or -1 to see if LA mode
+ * should be enabled for the interface.
+ * @return 0 to not use LA-mode, 1 to use LA-mode.
+ */
+int cvmx_ilk_use_la_mode(int interface, int channel)
+{
+ if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1_0))
+ return 0;
+
+ if (interface >= CVMX_NUM_ILK_INTF) {
+ debug("ERROR: invalid interface=%d in %s\n",
+ interface, __func__);
+ return -1;
+ }
+ return cvmx_ilk_LA_mode[interface].ilk_LA_mode;
+}
+
+/**
+ * User-overrideable callback function that returns whether or not an interface
+ * in look-aside mode should enable the RX calendar.
+ *
+ * @param interface - interface to check
+ * @return 1 to enable RX calendar, 0 to disable RX calendar.
+ *
+ * NOTE: For the CN68XX pass 2.0 this will enable the RX calendar for interface
+ * 0 and not interface 1. It is up to the customer to override this behavior.
+ */
+int cvmx_ilk_la_mode_enable_rx_calendar(int interface)
+{
+ /* There is an errata in the CN68XX pass 2.0 where if connected
+* in a loopback configuration or back to back then only one interface
+* can have the RX calendar enabled.
+*/
+ if (interface >= CVMX_NUM_ILK_INTF) {
+ debug("ERROR: invalid interface=%d in %s\n",
+ interface, __func__);
+ return -1;
+ }
+ return cvmx_ilk_LA_mode[interface].ilk_LA_mode_cal_ena;
+}
+
+/**
+ * Initialize and start the ILK interface.
+ *
+ * @param interface The identifier of the packet interface to configure and
+ * use as a ILK interface. cn68xx has 2 interfaces: ilk0 and
+ * ilk1.
+ *
+ * @param lane_mask the lane group for this interface
+ *
+ * @return Zero on success, negative on failure.
+ */
+int cvmx_ilk_start_interface(int interface, unsigned short lane_mask)
+{
+ int res = -1;
+ int other_intf, this_qlm, other_qlm;
+ unsigned short uni_mask;
+ cvmx_ilk_txx_cfg0_t ilk_txx_cfg0;
+ cvmx_ilk_rxx_cfg0_t ilk_rxx_cfg0;
+ cvmx_ilk_ser_cfg_t ilk_ser_cfg;
+ int node = (interface >> 4) & 0xf;
+
+ interface &= 0xf;
+
+ if (!octeon_has_feature(OCTEON_FEATURE_ILK))
+ return res;
+
+ if (interface >= CVMX_NUM_ILK_INTF)
+ return res;
+
+ if (lane_mask == 0)
+ return res;
+
+ /* check conflicts between 2 ilk interfaces. 1 lane can be assigned to 1
+* interface only
+*/
+ other_intf = !interface;
+ if (cvmx_ilk_lane_mask[node][other_intf] & lane_mask) {
+ debug("ILK%d:%d: %s: lane assignment conflict\n", node,
+ interface, __func__);
+ return res;
+ }
+
+ /* check the legality of the lane mask. interface 0 can have 8 lanes,
+* while interface 1 can have 4 lanes at most
+*/
+ uni_mask = lane_mask >> (interface * 4);
+ if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
+ cvmx_mio_qlmx_cfg_t mio_qlmx_c
[PATCH v2 50/52] net: Add ethernet support for MIPS Octeon
This patchs adds the ethernet & MDIO driver for the MIPS Octeon II / III
SoC platform. Please note that these drivers are based on the 2013
U-Boot version from Marvell and make use of the platform supported
helper functions for the ethernet functionality, including stuff like
SFP handling.
Signed-off-by: Stefan Roese
Cc: Ramon Fried
Cc: Joe Hershberger
---
drivers/net/Kconfig |7 +
drivers/net/Makefile |1 +
drivers/net/octeon/Makefile |6 +
drivers/net/octeon/octeon_eth.c | 1060 ++
drivers/net/octeon/octeon_mdio.c | 226 +++
5 files changed, 1300 insertions(+)
create mode 100644 drivers/net/octeon/Makefile
create mode 100644 drivers/net/octeon/octeon_eth.c
create mode 100644 drivers/net/octeon/octeon_mdio.c
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index a6171a7c7ffd..e17892898453 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -490,6 +490,13 @@ config MT7628_ETH
The MediaTek MT7628 ethernet interface is used on MT7628 and
MT7688 based boards.
+config NET_OCTEON
+ bool "MIPS Octeon ethernet support"
+ depends on ARCH_OCTEON
+ help
+ You must select Y to enable network device support for
+ MIPS Octeon SoCs. If unsure, say n
+
config NET_OCTEONTX
bool "OcteonTX Ethernet support"
depends on ARCH_OCTEONTX
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index a6d0c23f02d3..63144b27bf02 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -72,6 +72,7 @@ obj-$(CONFIG_MVNETA) += mvneta.o
obj-$(CONFIG_MVPP2) += mvpp2.o
obj-$(CONFIG_NATSEMI) += natsemi.o
obj-$(CONFIG_NETCONSOLE) += netconsole.o
+obj-$(CONFIG_NET_OCTEON) += octeon/
obj-$(CONFIG_NET_OCTEONTX) += octeontx/
obj-$(CONFIG_NET_OCTEONTX2) += octeontx2/
obj-$(CONFIG_NS8382X) += ns8382x.o
diff --git a/drivers/net/octeon/Makefile b/drivers/net/octeon/Makefile
new file mode 100644
index ..c573411a6293
--- /dev/null
+++ b/drivers/net/octeon/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier:GPL-2.0+
+#
+# Copyright (C) 2018-2022 Marvell International Ltd.
+#
+
+obj-$(CONFIG_NET_OCTEON) += octeon_eth.o octeon_mdio.o
diff --git a/drivers/net/octeon/octeon_eth.c b/drivers/net/octeon/octeon_eth.c
new file mode 100644
index ..fbb1afc08abc
--- /dev/null
+++ b/drivers/net/octeon/octeon_eth.c
@@ -0,0 +1,1060 @@
+// SPDX-License-Identifier:GPL-2.0
+/*
+ * Copyright (C) 2018-2022 Marvell International Ltd.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+/** Maximum receive packet size (hardware default is 1536) */
+#define CONFIG_OCTEON_NETWORK_MRU 1536
+
+#define OCTEON_BOOTLOADER_NAMED_BLOCK_TMP_PREFIX "__tmp"
+
+/**
+ * Enables RX packet debugging if octeon_debug_rx_packets is set in the
+ * environment.
+ */
+#define DEBUG_RX_PACKET
+
+/**
+ * Enables TX packet debugging if octeon_debug_tx_packets is set in the
+ * environment.
+ */
+#define DEBUG_TX_PACKET
+
+/* Global flag indicating common hw has been set up */
+static int octeon_global_hw_inited;
+
+#if defined(DEBUG_RX_PACKET) || defined(DEBUG_TX_PACKET)
+static int packet_rx_debug;
+static int packet_tx_debug;
+#endif
+
+/* Make sure that we have enough buffers to keep prefetching blocks happy.
+ * Absolute minimum is probably about 200.
+ */
+#define NUM_PACKET_BUFFERS 1000
+
+#define PKO_SHUTDOWN_TIMEOUT_VAL 100
+
+/* Define the offsets from the base CSR */
+#define GMX_PRT_CFG 0x10
+
+#define GMX_RX_FRM_MAX 0x30
+#define GMX_RX_JABBER 0x38
+
+#define GMX_RX_ADR_CTL 0x100
+#define GMX_RX_ADR_CAM_EN 0x108
+#define GMX_RX_ADR_CAM0 0x180
+#define GMX_RX_ADR_CAM1 0x188
+#define GMX_RX_ADR_CAM2 0x190
+#define GMX_RX_ADR_CAM3 0x198
+#define GMX_RX_ADR_CAM4 0x1a0
+#define GMX_RX_ADR_CAM5 0x1a8
+#define GMX_TX_OVR_BP0x4c8
+
+/**
+ * Set the hardware MAC address for a device
+ *
+ * @param interfaceinterface of port to set
+ * @param indexindex of port to set MAC address for
+ * @param addr Address structure to change it too.
+ * @return Zero on success
+ */
+static int cvm_oct_set_mac_address(struct udevice *dev)
+{
+ struct octeon_eth_info *priv = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ cvmx_gmxx_prtx_cfg_t gmx_cfg;
+ cvmx_helper_interface_mode_t mode;
+ cvmx_gmxx_rxx_adr_ctl_t control;
+ u8 *ptr = (uint8_t *)pdata->enetaddr;
+ int interf
[PATCH v2 52/52] mips: octeon: nic23: Enable ethernet support
This patch enables the Kconfig symbols needed for full ethernet support
on the NIC23. Additionally board specific setup is done, mostly GPIOs
related to SFP / GPIO configuration. With this, ethernet can be used on
this board. Here an example of a tftp load:
=> tftp 8100 big
Using ethernet-mac-nexus@11800e200 device
TFTP from server 192.168.1.5; our IP address is 192.168.1.247
Filename 'big'.
Load address: 0x8100
Loading: ## 10 MiB
9.7 MiB/s
done
Bytes transferred = 10485760 (a0 hex)
Signed-off-by: Stefan Roese
---
board/Marvell/octeon_nic23/board.c | 87 +-
configs/octeon_nic23_defconfig | 10 +++-
2 files changed, 95 insertions(+), 2 deletions(-)
diff --git a/board/Marvell/octeon_nic23/board.c
b/board/Marvell/octeon_nic23/board.c
index 9f5eb2e2a182..3e2c5397 100644
--- a/board/Marvell/octeon_nic23/board.c
+++ b/board/Marvell/octeon_nic23/board.c
@@ -1,10 +1,11 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2021 Stefan Roese
+ * Copyright (C) 2021-2022 Stefan Roese
*/
#include
#include
+#include
#include
#include
@@ -84,6 +85,52 @@ int board_fix_fdt(void *fdt)
return rc;
}
+int board_early_init_f(void)
+{
+ struct gpio_desc gpio = {};
+ ofnode node;
+
+ /* Initial GPIO configuration */
+
+ /* GPIO 7: Vitesse reset */
+ node = ofnode_by_compatible(ofnode_null(), "vitesse,vsc7224");
+ if (ofnode_valid(node)) {
+ gpio_request_by_name_nodev(node, "los", 0, &gpio, GPIOD_IS_IN);
+ dm_gpio_free(gpio.dev, &gpio);
+ gpio_request_by_name_nodev(node, "reset", 0, &gpio,
+ GPIOD_IS_OUT);
+ if (dm_gpio_is_valid(&gpio)) {
+ /* Vitesse reset */
+ debug("%s: Setting GPIO 7 to 1\n", __func__);
+ dm_gpio_set_value(&gpio, 1);
+ }
+ dm_gpio_free(gpio.dev, &gpio);
+ }
+
+ /* SFP+ transmitters */
+ ofnode_for_each_compatible_node(node, "ethernet,sfp-slot") {
+ gpio_request_by_name_nodev(node, "tx_disable", 0,
+ &gpio, GPIOD_IS_OUT);
+ if (dm_gpio_is_valid(&gpio)) {
+ debug("%s: Setting GPIO %d to 1\n", __func__,
+ gpio.offset);
+ dm_gpio_set_value(&gpio, 1);
+ }
+ dm_gpio_free(gpio.dev, &gpio);
+ gpio_request_by_name_nodev(node, "mod_abs", 0, &gpio,
+ GPIOD_IS_IN);
+ dm_gpio_free(gpio.dev, &gpio);
+ gpio_request_by_name_nodev(node, "tx_error", 0, &gpio,
+ GPIOD_IS_IN);
+ dm_gpio_free(gpio.dev, &gpio);
+ gpio_request_by_name_nodev(node, "rx_los", 0, &gpio,
+ GPIOD_IS_IN);
+ dm_gpio_free(gpio.dev, &gpio);
+ }
+
+ return 0;
+}
+
void board_configure_qlms(void)
{
octeon_configure_qlm(4, 3000, CVMX_QLM_MODE_SATA_2X1, 0, 0, 0, 0);
@@ -100,7 +147,45 @@ void board_configure_qlms(void)
int board_late_init(void)
{
+ struct gpio_desc gpio = {};
+ ofnode node;
+
+ /* Turn on SFP+ transmitters */
+ ofnode_for_each_compatible_node(node, "ethernet,sfp-slot") {
+ gpio_request_by_name_nodev(node, "tx_disable", 0,
+ &gpio, GPIOD_IS_OUT);
+ if (dm_gpio_is_valid(&gpio)) {
+ debug("%s: Setting GPIO %d to 0\n", __func__,
+ gpio.offset);
+ dm_gpio_set_value(&gpio, 0);
+ }
+ dm_gpio_free(gpio.dev, &gpio);
+ }
+
board_configure_qlms();
return 0;
}
+
+int last_stage_init(void)
+{
+ struct gpio_desc gpio = {};
+ ofnode node;
+
+ node = ofnode_by_compatible(ofnode_null(), "vitesse,vsc7224");
+ if (!ofnode_valid(node)) {
+ printf("Vitesse SPF DT node not found!");
+ return 0;
+ }
+
+ gpio_request_by_name_nodev(node, "reset", 0, &gpio, GPIOD_IS_OUT);
+ if (dm_gpio_is_valid(&gpio)) {
+ /* Take Vitesse retimer out of reset */
+ debug("%s: Setting GPIO 7 to 0\n", __func__);
+ dm_gpio_set_value(&gpio, 0);
+ mdelay(50);
+ }
+ dm_gpio_free(gpio.dev, &gpio);
+
+ return 0;
+}
diff --git a/configs/octeon_nic23_defconfig b/configs/octeon_nic23_defconfig
index 5427a9970a71..d44c650cef3c 100644
--- a/configs/octeon_nic23_defconfig
+++ b/configs/octeon_nic23_defconfig
@@ -12,6 +12,7 @@ CONFIG_ARCH_OCTEON=y
CONFIG_TARGET_OCTEON_NIC23=y
# CONFIG_MIPS_CACHE_SETUP is not set
# CONFIG_MIPS_CACHE_DISABLE is not
[PATCH v2 43/52] mips: octeon: Makefile: Enable building of the newly added C files
This patch adds the newly added C files to the Makefile to enable compilation. This is done in a separate step, to not introduce build breakage while adding the single files with potentially missing externals. Signed-off-by: Stefan Roese --- arch/mips/mach-octeon/Makefile | 35 +- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/arch/mips/mach-octeon/Makefile b/arch/mips/mach-octeon/Makefile index 40ddab27eacd..6aa7b367416f 100644 --- a/arch/mips/mach-octeon/Makefile +++ b/arch/mips/mach-octeon/Makefile @@ -12,13 +12,46 @@ obj-y += cvmx-coremask.o obj-y += cvmx-bootmem.o obj-y += bootoctlinux.o -# QLM related code +# Misc Octeon C files, mostly for QLM & ethernet support +obj-y += cvmx-agl.o +obj-y += cvmx-fpa.o +obj-y += cvmx-fpa-resource.o +obj-y += cvmx-fau-compat.o +obj-y += cvmx-global-resources.o +obj-y += cvmx-cmd-queue.o +obj-y += cvmx-helper-agl.o +obj-y += cvmx-helper-bgx.o +obj-y += cvmx-helper-board.o obj-y += cvmx-helper-cfg.o obj-y += cvmx-helper-fdt.o +obj-y += cvmx-helper-fpa.o +obj-y += cvmx-helper-ilk.o +obj-y += cvmx-helper-ipd.o obj-y += cvmx-helper-jtag.o +obj-y += cvmx-helper-loop.o +obj-y += cvmx-helper-npi.o +obj-y += cvmx-helper-pki.o +obj-y += cvmx-helper-pko.o +obj-y += cvmx-helper-pko3.o +obj-y += cvmx-helper-rgmii.o +obj-y += cvmx-helper-sfp.o +obj-y += cvmx-helper-sgmii.o obj-y += cvmx-helper-util.o +obj-y += cvmx-helper-xaui.o obj-y += cvmx-helper.o +obj-y += cvmx-ilk.o +obj-y += cvmx-ipd.o obj-y += cvmx-pcie.o +obj-y += cvmx-pki.o +obj-y += cvmx-pki-resources.o +obj-y += cvmx-pko.o +obj-y += cvmx-pko-internal-ports-range.o +obj-y += cvmx-pko3.o +obj-y += cvmx-pko3-compat.o +obj-y += cvmx-pko3-resources.o +obj-y += cvmx-pko3-queue.o +obj-y += cvmx-range.o obj-y += cvmx-qlm.o +obj-y += cvmx-qlm-tables.o obj-y += octeon_fdt.o obj-y += octeon_qlm.o -- 2.35.1
[PATCH v2 47/52] mips: octeon: mrvl, cn73xx.dtsi: Add ethernet (BGX) and SMI DT nodes
Add the Octeon ethernet (BGX) and SMI DT node to the dtsi file.
Signed-off-by: Stefan Roese
---
arch/mips/dts/mrvl,cn73xx.dtsi | 35 ++
1 file changed, 35 insertions(+)
diff --git a/arch/mips/dts/mrvl,cn73xx.dtsi b/arch/mips/dts/mrvl,cn73xx.dtsi
index 2a17f7a6a63e..77f3548a326a 100644
--- a/arch/mips/dts/mrvl,cn73xx.dtsi
+++ b/arch/mips/dts/mrvl,cn73xx.dtsi
@@ -267,5 +267,40 @@
interrupts = <0x6c010 4>;
};
};
+
+ /* SMI1 */
+ smi1: mdio@118003880 {
+ compatible = "cavium,octeon-3860-mdio";
+ reg = <0x11800 0x3880 0x0 0x40>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ /* BGX 0 */
+ bgx0: ethernet-mac-nexus@11800e000 {
+ compatible = "cavium,octeon-7890-bgx";
+ reg = <0x11800 0xe000 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ /* BGX 1 */
+ bgx1: ethernet-mac-nexus@11800e100 {
+ compatible = "cavium,octeon-7890-bgx";
+ reg = <0x11800 0xe100 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ /* BGX 2*/
+ bgx2: ethernet-mac-nexus@11800e200 {
+ compatible = "cavium,octeon-7890-bgx";
+ reg = <0x11800 0xe200 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
};
--
2.35.1
[PATCH v2 20/52] mips: octeon: Add cvmx-helper-rgmii.c
From: Aaron Williams
Import cvmx-helper-rgmii.c from 2013 U-Boot. It will be used by the later
added drivers to support networking on the MIPS Octeon II / III
platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
arch/mips/mach-octeon/cvmx-helper-rgmii.c | 398 ++
1 file changed, 398 insertions(+)
create mode 100644 arch/mips/mach-octeon/cvmx-helper-rgmii.c
diff --git a/arch/mips/mach-octeon/cvmx-helper-rgmii.c
b/arch/mips/mach-octeon/cvmx-helper-rgmii.c
new file mode 100644
index ..dc19c3bc1d9b
--- /dev/null
+++ b/arch/mips/mach-octeon/cvmx-helper-rgmii.c
@@ -0,0 +1,398 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018-2022 Marvell International Ltd.
+ *
+ * Functions for RGMII/GMII/MII initialization, configuration,
+ * and monitoring.
+ */
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+/**
+ * @INTERNAL
+ * Probe RGMII ports and determine the number present
+ *
+ * @param xiface Interface to probe
+ *
+ * @return Number of RGMII/GMII/MII ports (0-4).
+ */
+int __cvmx_helper_rgmii_probe(int xiface)
+{
+ struct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);
+ int num_ports = 0;
+ union cvmx_gmxx_inf_mode mode;
+
+ mode.u64 = csr_rd(CVMX_GMXX_INF_MODE(xi.interface));
+
+ if (mode.s.type)
+ debug("ERROR: Unsupported Octeon model in %s\n", __func__);
+ else
+ debug("ERROR: Unsupported Octeon model in %s\n", __func__);
+ return num_ports;
+}
+
+/**
+ * @INTERNAL
+ * Configure all of the ASX, GMX, and PKO regsiters required
+ * to get RGMII to function on the supplied interface.
+ *
+ * @param xiface PKO Interface to configure (0 or 1)
+ *
+ * @return Zero on success
+ */
+int __cvmx_helper_rgmii_enable(int xiface)
+{
+ struct cvmx_xiface xi = cvmx_helper_xiface_to_node_interface(xiface);
+ int interface = xi.interface;
+ int num_ports = cvmx_helper_ports_on_interface(interface);
+ int port;
+ union cvmx_gmxx_inf_mode mode;
+ union cvmx_asxx_tx_prt_en asx_tx;
+ union cvmx_asxx_rx_prt_en asx_rx;
+
+ mode.u64 = csr_rd(CVMX_GMXX_INF_MODE(interface));
+
+ if (num_ports == -1)
+ return -1;
+ if (mode.s.en == 0)
+ return -1;
+
+ /* Configure the ASX registers needed to use the RGMII ports */
+ asx_tx.u64 = 0;
+ asx_tx.s.prt_en = cvmx_build_mask(num_ports);
+ csr_wr(CVMX_ASXX_TX_PRT_EN(interface), asx_tx.u64);
+
+ asx_rx.u64 = 0;
+ asx_rx.s.prt_en = cvmx_build_mask(num_ports);
+ csr_wr(CVMX_ASXX_RX_PRT_EN(interface), asx_rx.u64);
+
+ /* Configure the GMX registers needed to use the RGMII ports */
+ for (port = 0; port < num_ports; port++) {
+ /*
+* Configure more flexible RGMII preamble
+* checking. Pass 1 doesn't support this feature.
+*/
+ union cvmx_gmxx_rxx_frm_ctl frm_ctl;
+
+ frm_ctl.u64 = csr_rd(CVMX_GMXX_RXX_FRM_CTL(port, interface));
+ /* New field, so must be compile time */
+ frm_ctl.s.pre_free = 1;
+ csr_wr(CVMX_GMXX_RXX_FRM_CTL(port, interface), frm_ctl.u64);
+
+ /*
+* Each pause frame transmitted will ask for about 10M
+* bit times before resume. If buffer space comes
+* available before that time has expired, an XON
+* pause frame (0 time) will be transmitted to restart
+* the flow.
+*/
+ csr_wr(CVMX_GMXX_TXX_PAUSE_PKT_TIME(port, interface), 2);
+ csr_wr(CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(port, interface),
+ 19000);
+
+ csr_wr(CVMX_ASXX_TX_CLK_SETX(port, interface), 24);
+ csr_wr(CVMX_ASXX_RX_CLK_SETX(port, interface), 24);
+ }
+
+ __cvmx_helper_setup_gmx(interface, num_ports);
+
+ /* enable the ports now */
+ for (port = 0; port < num_ports; port++) {
+ union cvmx_gmxx_prtx_cfg gmx_cfg;
+
+ cvmx_helper_link_autoconf(
+ cvmx_helper_get_ipd_port(interface, port));
+ gmx_cfg.u64 = csr_rd(CVMX_GMXX_PRTX_CFG(port, interface));
+ gmx_cfg.s.en = 1;
+ csr_wr(CVMX_GMXX_PRTX_CFG(port, interface), gmx_cfg.u64);
+ }
+ return 0;
+}
+
+/**
+ * @INTERNAL
+ * Return the link state of an IPD/PKO port as returned by
+ * auto negotiation. The result of this function may not match
+ * Octeon's link config if auto negotiation has changed since
+ * the last call to cvmx_helper_link_set().
+ *
+ * @param ipd_port IPD/PKO port to query
+ *
+ * @return Link state
+ */
+cvmx_helper_link_info_t _
[PATCH v2 37/52] mips: octeon: Add cvmx-pko3-compat.c
From: Aaron Williams
Import cvmx-pko3-compat.c from 2013 U-Boot. It will be used by the later
added drivers to support networking on the MIPS Octeon II / III
platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
arch/mips/mach-octeon/cvmx-pko3-compat.c | 656 +++
1 file changed, 656 insertions(+)
create mode 100644 arch/mips/mach-octeon/cvmx-pko3-compat.c
diff --git a/arch/mips/mach-octeon/cvmx-pko3-compat.c
b/arch/mips/mach-octeon/cvmx-pko3-compat.c
new file mode 100644
index ..3e142322dbfb
--- /dev/null
+++ b/arch/mips/mach-octeon/cvmx-pko3-compat.c
@@ -0,0 +1,656 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018-2022 Marvell International Ltd.
+ *
+ */
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+/* #undef CVMX_ENABLE_PARAMETER_CHECKING */
+/* #define CVMX_ENABLE_PARAMETER_CHECKING 1 */
+/* #define __PKO3_NATIVE_PTR */
+
+static inline u64 cvmx_pko3_legacy_paddr(unsigned int node, u64 addr)
+{
+ u64 paddr;
+
+ paddr = node;
+ paddr = (addr & ((1ull << 40) - 1)) | (paddr << 40);
+ return paddr;
+}
+
+#if CVMX_ENABLE_PARAMETER_CHECKING
+/**
+ * @INTERNAL
+ *
+ * Verify the integrity of a legacy buffer link pointer,
+ *
+ * Note that the IPD/PIP/PKO hardware would sometimes
+ * round-up the buf_ptr->size field of the last buffer in a chain to the next
+ * cache line size, so the sum of buf_ptr->size
+ * fields for a packet may exceed total_bytes by up to 127 bytes.
+ *
+ * @returns 0 on success, a negative number on error.
+ */
+static int cvmx_pko3_legacy_bufptr_validate(cvmx_buf_ptr_t buf_ptr,
+ unsigned int gather,
+ unsigned int buffers,
+ unsigned int total_bytes)
+{
+ unsigned int node = cvmx_get_node_num();
+ unsigned int segs = 0, bytes = 0;
+ unsigned int phys_addr;
+ cvmx_buf_ptr_t ptr;
+ int delta;
+
+ if (buffers == 0) {
+ return -1;
+ } else if (buffers == 1) {
+ delta = buf_ptr.s.size - total_bytes;
+ if (delta < 0 || delta > 127)
+ return -2;
+ } else if (gather) {
+ cvmx_buf_ptr_t *vptr;
+ /* Validate gather list */
+ if (buf_ptr.s.size < buffers)
+ return -3;
+ phys_addr = cvmx_pko3_legacy_paddr(node, buf_ptr.s.addr);
+ vptr = cvmx_phys_to_ptr(phys_addr);
+ for (segs = 0; segs < buffers; segs++)
+ bytes += vptr[segs].s.size;
+ delta = bytes - total_bytes;
+ if (delta < 0 || delta > 127)
+ return -4;
+ } else {
+ void *vptr;
+ /* Validate linked buffers */
+ ptr = buf_ptr;
+ for (segs = 0; segs < buffers; segs++) {
+ bytes += ptr.s.size;
+ phys_addr = cvmx_pko3_legacy_paddr(node, ptr.s.addr);
+ vptr = cvmx_phys_to_ptr(phys_addr);
+ memcpy(&ptr, vptr - sizeof(u64), sizeof(u64));
+ }
+ delta = bytes - total_bytes;
+ if (delta < 0 || delta > 127)
+ return -5;
+ }
+ return 0;
+}
+#endif /* CVMX_ENABLE_PARAMETER_CHECKING */
+
+/*
+ * @INTERNAL
+ *
+ * Implementation note:
+ * When the packet is sure to not need a jump_buf,
+ * it will be written directly into cvmseg.
+ * When the packet might not fit into cvmseg with all
+ * of its descriptors, a jump_buf is allocated a priori,
+ * and only header is first placed into cvmseg, all other
+ * descriptors are placed into jump_buf, and finally
+ * the PKO_SEND_JUMP_S is written to cvmseg.
+ * This is because if there are no EXT or TSO descriptors,
+ * then HDR must be first, and JMP second and that is all
+ * that should go into cvmseg.
+ */
+struct __cvmx_pko3_legacy_desc {
+ u64 *cmd_words;
+ u64 *jump_buf_base_ptr;
+ unsigned short word_count;
+ short last_pool;
+ u8 port_node;
+ u8 aura_node;
+ u8 jump_buf_size;
+};
+
+/**
+ * @INTERNAL
+ *
+ * Add a subdescriptor into a command buffer,
+ * and handle command-buffer overflow by allocating a JUMP_s buffer
+ * from PKO3 internal AURA.
+ */
+static int __cvmx_pko3_cmd_subdc_add(struct __cvmx_pko3_legacy_desc *desc,
+u64 subdc)
+{
+ /* SEND_JUMP_S missing on
[PATCH v2 38/52] mips: octeon: Add cvmx-pko3-resources.c
From: Aaron Williams
Import cvmx-pko3-resources.c from 2013 U-Boot. It will be used by the later
added drivers to support networking on the MIPS Octeon II / III
platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
arch/mips/mach-octeon/cvmx-pko3-resources.c | 213
1 file changed, 213 insertions(+)
create mode 100644 arch/mips/mach-octeon/cvmx-pko3-resources.c
diff --git a/arch/mips/mach-octeon/cvmx-pko3-resources.c
b/arch/mips/mach-octeon/cvmx-pko3-resources.c
new file mode 100644
index ..ab04e9acb558
--- /dev/null
+++ b/arch/mips/mach-octeon/cvmx-pko3-resources.c
@@ -0,0 +1,213 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018-2022 Marvell International Ltd.
+ *
+ * PKO resources.
+ */
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+#define CVMX_GR_TAG_PKO_PORT_QUEUES(x)
\
+ cvmx_get_gr_tag('c', 'v', 'm', '_', 'p', 'k', 'o', 'p', 'o', 'q', '_', \
+ ((x) + '0'), '.', '.', '.', '.')
+#define CVMX_GR_TAG_PKO_L2_QUEUES(x)
\
+ cvmx_get_gr_tag('c', 'v', 'm', '_', 'p', 'k', 'o', 'l', '2', 'q', '_', \
+ ((x) + '0'), '.', '.', '.', '.')
+#define CVMX_GR_TAG_PKO_L3_QUEUES(x)
\
+ cvmx_get_gr_tag('c', 'v', 'm', '_', 'p', 'k', 'o', 'l', '3', 'q', '_', \
+ ((x) + '0'), '.', '.', '.', '.')
+#define CVMX_GR_TAG_PKO_L4_QUEUES(x)
\
+ cvmx_get_gr_tag('c', 'v', 'm', '_', 'p', 'k', 'o', 'l', '4', 'q', '_', \
+ ((x) + '0'), '.', '.', '.', '.')
+#define CVMX_GR_TAG_PKO_L5_QUEUES(x)
\
+ cvmx_get_gr_tag('c', 'v', 'm', '_', 'p', 'k', 'o', 'l', '5', 'q', '_', \
+ ((x) + '0'), '.', '.', '.', '.')
+#define CVMX_GR_TAG_PKO_DESCR_QUEUES(x)
\
+ cvmx_get_gr_tag('c', 'v', 'm', '_', 'p', 'k', 'o', 'd', 'e', 'q', '_', \
+ ((x) + '0'), '.', '.', '.', '.')
+#define CVMX_GR_TAG_PKO_PORT_INDEX(x)
\
+ cvmx_get_gr_tag('c', 'v', 'm', '_', 'p', 'k', 'o', 'p', 'i', 'd', '_', \
+ ((x) + '0'), '.', '.', '.', '.')
+
+/*
+ * @INRWENAL
+ * Per-DQ parameters, current and maximum queue depth counters
+ */
+cvmx_pko3_dq_params_t *__cvmx_pko3_dq_params[CVMX_MAX_NODES];
+
+static const short cvmx_pko_num_queues_78XX[256] = {
+ [CVMX_PKO_PORT_QUEUES] = 32, [CVMX_PKO_L2_QUEUES] = 512,
+ [CVMX_PKO_L3_QUEUES] = 512, [CVMX_PKO_L4_QUEUES] = 1024,
+ [CVMX_PKO_L5_QUEUES] = 1024, [CVMX_PKO_DESCR_QUEUES] = 1024
+};
+
+static const short cvmx_pko_num_queues_73XX[256] = {
+ [CVMX_PKO_PORT_QUEUES] = 16, [CVMX_PKO_L2_QUEUES] = 256,
+ [CVMX_PKO_L3_QUEUES] = 256, [CVMX_PKO_L4_QUEUES] = 0,
+ [CVMX_PKO_L5_QUEUES] = 0,[CVMX_PKO_DESCR_QUEUES] = 256
+};
+
+int cvmx_pko3_num_level_queues(enum cvmx_pko3_level_e level)
+{
+ unsigned int nq = 0, ne = 0;
+
+ if (OCTEON_IS_MODEL(OCTEON_CN78XX)) {
+ ne = NUM_ELEMENTS(cvmx_pko_num_queues_78XX);
+ nq = cvmx_pko_num_queues_78XX[level];
+ }
+ if (OCTEON_IS_MODEL(OCTEON_CN73XX) || OCTEON_IS_MODEL(OCTEON_CNF75XX)) {
+ ne = NUM_ELEMENTS(cvmx_pko_num_queues_73XX);
+ nq = cvmx_pko_num_queues_73XX[level];
+ }
+
+ if (nq == 0 || level >= ne) {
+ printf("ERROR: %s: queue level %#x invalid\n", __func__, level);
+ return -1;
+ }
+
+ return nq;
+}
+
+static inline struct global_resource_tag
+__cvmx_pko_get_queues_resource_tag(int node, enum cvmx_pko3_level_e
queue_level)
+{
+ if (cvmx_pko3_num_level_queues(queue_level) == 0) {
+ printf("ERROR: %s: queue level %#x invalid\n", __func__,
+ queue_level);
+ return CVMX_GR_TAG_INVALID;
+ }
+
+ switch (queue_level) {
+ case CVMX_PKO_PORT_QUEUES:
+ return CVMX_GR_TAG_PKO_PORT_QUEUES(node);
+ case CVMX_PKO_L2_QUEUES:
+ return CVMX_GR_TAG_PKO_L2_QUEUES(node);
+ case CVMX_PKO_L3_QUEUES:
+ return CVMX_GR_TAG_PKO_L3_QUEUES(node);
+ case CVMX_PKO_L4_QUEUES:
+ return CVMX_GR_TAG_PKO_L4_QUEUES(node);
+ case CVMX_PKO_L5_QUEUES:
+ return CVMX_GR_TAG_PKO_L5_QUEUES(node);
+ case CVMX_PKO_DESCR_QUEUES:
+
[PATCH v2 51/52] mips: octeon: ebb7304: Enable ethernet support
This patch enables the Kconfig symbols needed for full ethernet support on the EBB7304. Also the PHY autonegotiation timeout is increased, as the default 5 seconds are sometime a bit short. With this, ethernet can be used on this board. Here an example of a tftp load: => tftp 8100 big ethernet-mac-nexus@11800e000 Waiting for PHY auto negotiation to complete... done Using ethernet-mac-nexus@11800e000 device TFTP from server 192.168.1.5; our IP address is 192.168.1.243 Filename 'big'. Load address: 0x8100 Loading: ## 10 MiB 13.2 MiB/s done Bytes transferred = 10485760 (a0 hex) Signed-off-by: Stefan Roese --- configs/octeon_ebb7304_defconfig | 7 +++ include/configs/octeon_ebb7304.h | 2 ++ 2 files changed, 9 insertions(+) diff --git a/configs/octeon_ebb7304_defconfig b/configs/octeon_ebb7304_defconfig index 9824f8b97ae5..3d9bbaaab4df 100644 --- a/configs/octeon_ebb7304_defconfig +++ b/configs/octeon_ebb7304_defconfig @@ -25,6 +25,7 @@ CONFIG_CMD_PART=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_RTC=y CONFIG_CMD_TIME=y @@ -36,6 +37,7 @@ CONFIG_EFI_PARTITION=y CONFIG_PARTITION_TYPE_GUID=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0x80001FBFE000 +CONFIG_TFTP_TSIZE=y CONFIG_CLK=y # CONFIG_INPUT is not set CONFIG_MISC=y @@ -53,7 +55,12 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_MARVELL=y +CONFIG_DM_MDIO=y +CONFIG_DM_ETH_PHY=y CONFIG_E1000=y +CONFIG_NET_OCTEON=y CONFIG_PCI=y CONFIG_PCIE_OCTEON=y CONFIG_DM_REGULATOR=y diff --git a/include/configs/octeon_ebb7304.h b/include/configs/octeon_ebb7304.h index 358db69a05b3..8c6c57bd546a 100644 --- a/include/configs/octeon_ebb7304.h +++ b/include/configs/octeon_ebb7304.h @@ -16,4 +16,6 @@ #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT #define CONFIG_SYS_FLASH_EMPTY_INFO/* flinfo indicates empty blocks */ +#define PHY_ANEG_TIMEOUT 8000/* PHY needs a longer aneg time */ + #endif /* __CONFIG_H__ */ -- 2.35.1
[PATCH v2 46/52] mips: octeon: octeon_common.h: Move init SP because of increased image size
This patch moves CONFIG_SYS_INIT_SP_OFFSET to a higher address so that it does not interfere with larger U-Boot images. This was noticed, while adding network support to the EBB7304 board. Signed-off-by: Stefan Roese --- include/configs/octeon_common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/octeon_common.h b/include/configs/octeon_common.h index 2e4bfd035162..7e71c83887f3 100644 --- a/include/configs/octeon_common.h +++ b/include/configs/octeon_common.h @@ -8,7 +8,7 @@ #define __OCTEON_COMMON_H__ #if defined(CONFIG_RAM_OCTEON) -#define CONFIG_SYS_INIT_SP_OFFSET 0x2010 +#define CONFIG_SYS_INIT_SP_OFFSET 0x2018 #else /* No DDR init -> run in L2 cache with limited resources */ #define CONFIG_SYS_INIT_SP_OFFSET 0x0018 -- 2.35.1
[PATCH v2 33/52] mips: octeon: Add cvmx-pki-resources.c
From: Aaron Williams
Import cvmx-pki-resources.c from 2013 U-Boot. It will be used by the later
added drivers to support networking on the MIPS Octeon II / III
platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
arch/mips/mach-octeon/cvmx-pki-resources.c | 285 +
1 file changed, 285 insertions(+)
create mode 100644 arch/mips/mach-octeon/cvmx-pki-resources.c
diff --git a/arch/mips/mach-octeon/cvmx-pki-resources.c
b/arch/mips/mach-octeon/cvmx-pki-resources.c
new file mode 100644
index ..ab8417216241
--- /dev/null
+++ b/arch/mips/mach-octeon/cvmx-pki-resources.c
@@ -0,0 +1,285 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018-2022 Marvell International Ltd.
+ *
+ * PKI Support.
+ */
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+static s32 cvmx_pki_style_refcnt[CVMX_MAX_NODES][CVMX_PKI_NUM_INTERNAL_STYLE];
+
+/**
+ * This function allocates/reserves a style from pool of global styles per
node.
+ * @param node node to allocate style from.
+ * @param stylestyle to allocate, if -1 it will be allocated
+ * first available style from style resource. If index is positive
+ * number and in range, it will try to allocate specified style.
+ * @return style number on success,
+ * -1 on alloc failure.
+ * -2 on resource already reserved.
+ */
+int cvmx_pki_style_alloc(int node, int style)
+{
+ int rs;
+
+ if (cvmx_create_global_resource_range(CVMX_GR_TAG_STYLE(node),
+ CVMX_PKI_NUM_INTERNAL_STYLE)) {
+ printf("ERROR: Failed to create styles global resource\n");
+ return -1;
+ }
+ if (style >= 0) {
+ /* Reserving specific style, use refcnt for sharing */
+ rs = cvmx_atomic_fetch_and_add32(
+ &cvmx_pki_style_refcnt[node][style], 1);
+ if (rs > 0)
+ return CVMX_RESOURCE_ALREADY_RESERVED;
+
+ rs = cvmx_reserve_global_resource_range(CVMX_GR_TAG_STYLE(node),
+ style, style, 1);
+ if (rs == -1) {
+ /* This means the style is taken by another app */
+ printf("ERROR: style %d is reserved by another app\n",
+ style);
+ cvmx_atomic_fetch_and_add32(
+ &cvmx_pki_style_refcnt[node][style], -1);
+ return CVMX_RESOURCE_ALLOC_FAILED;
+ }
+ } else {
+ /* Allocate first available style */
+ rs = cvmx_allocate_global_resource_range(
+ CVMX_GR_TAG_STYLE(node), style, 1, 1);
+ if (rs < 0) {
+ printf("ERROR: Failed to allocate style, none
available\n");
+ return CVMX_RESOURCE_ALLOC_FAILED;
+ }
+ style = rs;
+ /* Increment refcnt for newly created style */
+ cvmx_atomic_fetch_and_add32(&cvmx_pki_style_refcnt[node][style],
+ 1);
+ }
+ return style;
+}
+
+/**
+ * This function frees a style from pool of global styles per node.
+ * @param node node to free style from.
+ * @param style style to free
+ * @return 0 on success, -1 on failure or
+ * if the style is shared a positive count of remaining users for this style.
+ */
+int cvmx_pki_style_free(int node, int style)
+{
+ int rs;
+
+ rs = cvmx_atomic_fetch_and_add32(&cvmx_pki_style_refcnt[node][style],
+-1);
+ if (rs > 1)
+ return rs - 1;
+
+ if (cvmx_free_global_resource_range_with_base(CVMX_GR_TAG_STYLE(node),
+ style, 1) == -1) {
+ printf("ERROR Failed to release style %d\n", (int)style);
+ return -1;
+ }
+ return 0;
+}
+
+/**
+ * This function allocates/reserves a cluster group from per node
+ cluster group resources.
+ * @param node node to allocate cluster group from.
+ @param cl_grp cluster group to allocate/reserve, if -1 ,
+ * allocate any available cluster group.
+ * @return cluster group number
+ * -1 on alloc failure.
+ * -2 on resource already reserved.
+ */
+int cvmx_pki_cluster_grp_alloc(int node, int cl_grp)
+{
+ int rs;
+
+ if (node >= CVMX_MAX_NODES) {
+ printf("ERROR: Invalid node number %d\n", node);
+ return -1;
+ }
+ if (cvmx_create_global_resource_range(CVMX_GR_TAG_CLUSTER_GRP(node),
+
[PATCH v2 48/52] mips: octeon: mrvl, octeon-ebb7304.dts: Add ethernet DT support
Add the Octeon ethernet (BGX), SMI and PHY DT nodes to the EBB7304 dts
file to enable ethernet support on this board.
Signed-off-by: Stefan Roese
---
arch/mips/dts/mrvl,octeon-ebb7304.dts | 45 +++
1 file changed, 45 insertions(+)
diff --git a/arch/mips/dts/mrvl,octeon-ebb7304.dts
b/arch/mips/dts/mrvl,octeon-ebb7304.dts
index fda559d8629d..08247eb4e0ee 100644
--- a/arch/mips/dts/mrvl,octeon-ebb7304.dts
+++ b/arch/mips/dts/mrvl,octeon-ebb7304.dts
@@ -201,3 +201,48 @@
cd-gpios = <&gpio 25 1>; /* active low */
};
};
+
+/* SMI_1 -- Available on rev 2 and later boards */
+&smi1 {
+ /**
+* The phy names are broken down as follows:
+* (m)phyxxyzzs
+* where:
+* xx = 01 for SGMII, 10 for DXAUI, 20 for RXAUI
+* and 40 for XFI/LXAUI
+* y = QLM/DLM number
+* zz = PHY address (decimal)
+* s = sub-phy number in the case of the Cortina
+* PHY
+* a mphy is a nexus phy that contains one or more
+* sub-phys, for example the Cortina CS4223.
+*/
+
+ /* QLM 2 */
+ phy01208: ethernet-phy@01208 {
+ reg = <8>;
+ compatible = "marvell,88e1240", "ethernet-phy-ieee802.3-c22";
+
+ marvell,reg-init = <3 0x10 0 0x8665>,
+ <3 0x11 0 0x00aa>,
+ <3 0x12 0 0x4105>,
+ <3 0x13 0 0x8a08>;
+
+ interrupt-parent = <&gpio>;
+ interrupts = <12 8>; /* Pin 12, active low */
+ };
+};
+
+/* BGX 0 */
+&bgx0 {
+ status = "okay";
+ phy-handle = <&phy01208>; /* put phy-handle in BGX node and MAC node */
+
+ /* SerDes 0, may differ from PCS Lane/LMAC */
+ eth0: ethernet-mac@D {
+ compatible = "cavium,octeon-7890-bgx-port";
+ reg = <0>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ phy-handle = <&phy01208>;
+ };
+};
--
2.35.1
[PATCH v2 34/52] mips: octeon: Add cvmx-pko.c
From: Aaron Williams
Import cvmx-pko.c from 2013 U-Boot. It will be used by the later
added drivers to support networking on the MIPS Octeon II / III
platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
arch/mips/mach-octeon/cvmx-pko.c | 788 +++
1 file changed, 788 insertions(+)
create mode 100644 arch/mips/mach-octeon/cvmx-pko.c
diff --git a/arch/mips/mach-octeon/cvmx-pko.c b/arch/mips/mach-octeon/cvmx-pko.c
new file mode 100644
index ..8a9181362bda
--- /dev/null
+++ b/arch/mips/mach-octeon/cvmx-pko.c
@@ -0,0 +1,788 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018-2022 Marvell International Ltd.
+ *
+ * Support library for the hardware Packet Output unit.
+ */
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CVMX_PKO_NQ_PER_PORT_MAX 32
+
+static cvmx_pko_return_value_t cvmx_pko2_config_port(short ipd_port,
+int base_queue,
+int num_queues,
+const u8 priority[]);
+
+static const int debug;
+
+/**
+ * Internal state of packet output
+ */
+
+/*
+ * PKO port iterator
+ * XXX this macro only works for 68XX
+ */
+
+#define pko_for_each_port(__p)
\
+ for (__p = 0; __p < CVMX_HELPER_CFG_MAX_PKO_PORT; __p++) \
+ if (__cvmx_helper_cfg_pko_queue_base(__p) != \
+ CVMX_HELPER_CFG_INVALID_VALUE)
+
+/*
+ * @INTERNAL
+ *
+ * Get INT for a port
+ *
+ * @param interface
+ * @param index
+ * @return the INT value on success and -1 on error
+ *
+ * This function is only for CN68XX.
+ */
+static int __cvmx_pko_int(int interface, int index)
+{
+ cvmx_helper_cfg_assert(interface < CVMX_HELPER_MAX_IFACE);
+ cvmx_helper_cfg_assert(index >= 0);
+
+ switch (interface) {
+ case 0:
+ cvmx_helper_cfg_assert(index < 4);
+ return index;
+ case 1:
+ cvmx_helper_cfg_assert(index == 0);
+ return 4;
+ case 2:
+ cvmx_helper_cfg_assert(index < 4);
+ return index + 8;
+ case 3:
+ cvmx_helper_cfg_assert(index < 4);
+ return index + 0xC;
+ case 4:
+ cvmx_helper_cfg_assert(index < 4);
+ return index + 0x10;
+ case 5:
+ cvmx_helper_cfg_assert(index < 256);
+ return 0x1C;
+ case 6:
+ cvmx_helper_cfg_assert(index < 256);
+ return 0x1D;
+ case 7:
+ cvmx_helper_cfg_assert(index < 32);
+ return 0x1E;
+ case 8:
+ cvmx_helper_cfg_assert(index < 8);
+ return 0x1F;
+ }
+
+ return -1;
+}
+
+int cvmx_pko_get_base_pko_port(int interface, int index)
+{
+ if (octeon_has_feature(OCTEON_FEATURE_CN78XX_WQE))
+ return cvmx_helper_get_ipd_port(interface, index);
+ else if (octeon_has_feature(OCTEON_FEATURE_PKND))
+ return __cvmx_helper_cfg_pko_port_base(interface, index);
+ else
+ return cvmx_helper_get_ipd_port(interface, index);
+}
+
+int cvmx_pko_get_base_queue(int port)
+{
+ if (octeon_has_feature(OCTEON_FEATURE_CN78XX_WQE)) {
+ return cvmx_pko3_get_queue_base(port);
+ } else if (octeon_has_feature(OCTEON_FEATURE_PKND)) {
+ return __cvmx_helper_cfg_pko_queue_base(
+ cvmx_helper_cfg_ipd2pko_port_base(port));
+ } else {
+ if (port < 48)
+ return cvmx_pko_queue_table[port].ccppp_queue_base;
+ else
+ return CVMX_PKO_ILLEGAL_QUEUE;
+ }
+}
+
+int cvmx_pko_get_num_queues(int port)
+{
+ if (octeon_has_feature(OCTEON_FEATURE_CN78XX_WQE)) {
+ return cvmx_pko3_get_queue_num(port);
+ } else if (octeon_has_feature(OCTEON_FEATURE_PKND)) {
+ return __cvmx_helper_cfg_pko_queue_num(
+ cvmx_helper_cfg_ipd2pko_port_base(port));
+ } else {
+ if (port < 48)
+ return cvmx_pko_queue_table[port].ccppp_num_queues;
+ }
+ return 0;
+}
+
+/*
+ * Allocate memory for PKO engines.
+ *
+ * @param engine is the PKO engine ID.
+ * @return # of 2KB-chunks allocated to this PKO engine.
+ */
+static int __cvmx_pko_memory_per_engine_o68(int engine)
+{
+
[PATCH v2 49/52] mips: octeon: mrvl, octeon-nic23.dts: Add ethernet DT support
Add the Octeon ethernet (BGX) and SFP DT nodes to the NIC23 dts file to
enable ethernet support on this board.
Signed-off-by: Stefan Roese
---
arch/mips/dts/mrvl,octeon-nic23.dts | 238
1 file changed, 238 insertions(+)
diff --git a/arch/mips/dts/mrvl,octeon-nic23.dts
b/arch/mips/dts/mrvl,octeon-nic23.dts
index 72ef56d834e4..dfbd51c92468 100644
--- a/arch/mips/dts/mrvl,octeon-nic23.dts
+++ b/arch/mips/dts/mrvl,octeon-nic23.dts
@@ -118,11 +118,208 @@
&i2c0 {
u-boot,dm-pre-reloc;/* Needed early for DDR SPD EEPROM */
clock-frequency = <10>;
+
+ sfp0eeprom: eeprom@50 {
+ compatible = "atmel,24c01";
+ reg = <0x50>;
+ };
+
+ sfp0alerts: eeprom@51 {
+ compatible = "atmel,24c01";
+ reg = <0x51>;
+ };
};
&i2c1 {
u-boot,dm-pre-reloc;/* Needed early for DDR SPD EEPROM */
clock-frequency = <10>;
+
+ vitesse@10 {
+ compatible = "vitesse,vsc7224";
+ reg = <0x10>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* Note that reset is active high with this device */
+ reset = <&gpio 7 0>;
+
+ /* LoS pin can be pulled low when there is a loss of signal */
+ los = <&gpio 6 0>;
+
+ vitesse,reg-init =
+ /* Clear all masks */
+ /* Page select FSYNC0 (0x30) */
+ <0x7f 0x0030>,
+ /* Set FSYNC0 for 10.3125Gbps */
+ <0x80 0x2841>, /* See Table 3. */
+ <0x81 0x0008>,
+ <0x82 0xc000>,
+ <0x83 0x0010>,
+ <0x84 0x1d00>,
+
+ /* All channels Rx settings set equally */
+ <0x7f 0x0050>,
+ /* Shrink EQ_BUFF */
+ <0x82 0x0014>,
+ /* Set EQVGA_ADAP = 1 (enable EQVGA circuitry),
+* USE_UNIT_GAIN = 1 (EQVGA is in unity gain),
+* USE_LPF = 0 (VGA adapt not using LPF),
+* USE_EQVGA = 1
+ <0x89 0x7f13>,
+ /* Select min DFE Delay (DFE_DELAY) */
+ <0x90 0x5785>,
+ /* Set DFE 1-3 limit (DXMAX) = 32dec,
+* AP Max limit = 127 decimal
+*/
+ <0x92 0x207f>,
+ /* Set AP Min limit = 32 decimal */
+ <0x93 0x2000>,
+ /* Set DFE Averaging to the slowest (DFE_AVG) */
+ <0x94 0x0031>,
+ /* Set Inductor Bypass OD_IND_BYP = 0 & fastest
Rise/Fall */
+ <0x9c 0x>,
+ /* Setting DFE Boost = none. Must set for
+* rev C (if DFE in adapt mode)
+*/
+ <0xaa 0x0888>,
+ /* Setting EQ Min = 8 & Max limit = 72 dec.
+* Must set for rev C, otherwise EQ is 0
+* (if EQ is in adaptive mode)
+*/
+ <0xa8 0x2408>,
+ /* Setting EQVGA = 96, when in EQVGA manual mode */
+ <0xa9 0x0060>,
+ /* Setting SW_BFOCM, bits 15:14 to 01 */
+ <0x87 0x4021>,
+ /* Turn off adaptive input equalization
+* and VGA adaptive algorithm control.
+ */
+ <0x89 0x7313>,
+ /* Turn on adaptive input equalization
+* and VGA adaptive algorithm control.
+ */
+ <0x89 0x7f13>;
+
+ vitesse-channel@0 {
+ compatible = "vitesse,vsc7224-channel";
+ reg = <0>;
+ direction-tx;
+ sfp-mac = <ð0>;
+
+ /* TAP settings. The format of this is as
+* follows:
+* - cable length in meters, 0 = active or
+* optical module
+* - maintap value
+* - pretap value
+* - posttap value
+*
+* For the cable length, the value will apply
+* for that cable length and greater until the
+* next largest cable length specified. These
+* values must be ordered first by channel mask
+* then by cable length. These are typically
+* set for the transmit channels, not the
+* recei
[PATCH v2 45/52] mips: octeon: cpu.c: Implement configure_lmtdma_window()
Import configure_lmtdma_window from Marvell 2013 U-Boot as it's needed
for network functionality.
Signed-off-by: Stefan Roese
---
arch/mips/mach-octeon/cpu.c | 34 +-
1 file changed, 33 insertions(+), 1 deletion(-)
diff --git a/arch/mips/mach-octeon/cpu.c b/arch/mips/mach-octeon/cpu.c
index fffd9dfb8580..1bdc6cd72903 100644
--- a/arch/mips/mach-octeon/cpu.c
+++ b/arch/mips/mach-octeon/cpu.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2020 Marvell International Ltd.
+ * Copyright (C) 2020-2022 Marvell International Ltd.
*/
#include
@@ -17,6 +17,8 @@
#include
#include
#include
+#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -393,6 +395,33 @@ static int init_bootcmd_console(void)
return ret;
}
+static void configure_lmtdma_window(void)
+{
+ u64 tmp;
+ u64 addr;
+ u64 end_addr;
+
+ CVMX_MF_CVM_MEM_CTL(tmp);
+ tmp &= ~0x1ffull;
+ tmp |= 0x104ull;
+
+ /* enable LMTDMA */
+ tmp |= (1ull << 51);
+ /* configure scratch line 2 for LMT */
+ /* TODO: reserve this scratch line, so that others will not use it */
+ /* TODO: store LMTLINE in global var */
+ tmp |= (CVMX_PKO_LMTLINE << 45);
+ /* clear LMTLINE in scratch */
+ addr = CVMX_PKO_LMTLINE * CVMX_CACHE_LINE_SIZE;
+ end_addr = addr + CVMX_CACHE_LINE_SIZE;
+
+ while (addr < end_addr) {
+ *CASTPTR(volatile u64, addr + CVMX_SCRATCH_BASE) = (u64)0;
+ addr += 8;
+ }
+ CVMX_MT_CVM_MEM_CTL(tmp);
+}
+
int arch_early_init_r(void)
{
int ret;
@@ -405,6 +434,9 @@ int arch_early_init_r(void)
if (ret)
return ret;
+ if (octeon_has_feature(OCTEON_FEATURE_PKO3))
+ configure_lmtdma_window();
+
return 0;
}
--
2.35.1
[PATCH v2 40/52] mips: octeon: Add cvmx-qlm-tables.c
From: Aaron Williams
Import cvmx-qlm-tables.c from 2013 U-Boot. It will be used by the later
added drivers to support networking on the MIPS Octeon II / III
platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
arch/mips/mach-octeon/cvmx-qlm-tables.c | 292
1 file changed, 292 insertions(+)
create mode 100644 arch/mips/mach-octeon/cvmx-qlm-tables.c
diff --git a/arch/mips/mach-octeon/cvmx-qlm-tables.c
b/arch/mips/mach-octeon/cvmx-qlm-tables.c
new file mode 100644
index ..ca2289225d37
--- /dev/null
+++ b/arch/mips/mach-octeon/cvmx-qlm-tables.c
@@ -0,0 +1,292 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018-2022 Marvell International Ltd.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+const __cvmx_qlm_jtag_field_t __cvmx_qlm_jtag_field_cn63xx[] = {
+ { "prbs_err_cnt", 299, 252 }, // prbs_err_cnt[47..0]
+ { "prbs_lock", 251, 251 }, // prbs_lock
+ { "jtg_prbs_rst_n", 250, 250 },// jtg_prbs_rst_n
+ { "jtg_run_prbs31", 249, 249 },// jtg_run_prbs31
+ { "jtg_run_prbs7", 248, 248 }, // jtg_run_prbs7
+ { "Unused1", 247, 245 }, // 0
+ { "cfg_pwrup_set", 244, 244 }, // cfg_pwrup_set
+ { "cfg_pwrup_clr", 243, 243 }, // cfg_pwrup_clr
+ { "cfg_rst_n_set", 242, 242 }, // cfg_rst_n_set
+ { "cfg_rst_n_clr", 241, 241 }, // cfg_rst_n_clr
+ { "cfg_tx_idle_set", 240, 240 }, // cfg_tx_idle_set
+ { "cfg_tx_idle_clr", 239, 239 }, // cfg_tx_idle_clr
+ { "cfg_tx_byp", 238, 238 },// cfg_tx_byp
+ { "cfg_tx_byp_inv", 237, 237 },// cfg_tx_byp_inv
+ { "cfg_tx_byp_val", 236, 227 },// cfg_tx_byp_val[9..0]
+ { "cfg_loopback", 226, 226 }, // cfg_loopback
+ { "shlpbck", 225, 224 }, // shlpbck[1..0]
+ { "sl_enable", 223, 223 }, // sl_enable
+ { "sl_posedge_sample", 222, 222 }, // sl_posedge_sample
+ { "trimen", 221, 220 },// trimen[1..0]
+ { "serdes_tx_byp", 219, 219 }, // serdes_tx_byp
+ { "serdes_pll_byp", 218, 218 },// serdes_pll_byp
+ { "lowf_byp", 217, 217 }, // lowf_byp
+ { "spdsel_byp", 216, 216 },// spdsel_byp
+ { "div4_byp", 215, 215 }, // div4_byp
+ { "clkf_byp", 214, 208 }, // clkf_byp[6..0]
+ { "Unused2", 207, 206 }, // 0
+ { "biasdrv_hs_ls_byp", 205, 201 }, // biasdrv_hs_ls_byp[4..0]
+ { "tcoeff_hf_ls_byp", 200, 197 }, // tcoeff_hf_ls_byp[3..0]
+ { "biasdrv_hf_byp", 196, 192 },// biasdrv_hf_byp[4..0]
+ { "tcoeff_hf_byp", 191, 188 }, // tcoeff_hf_byp[3..0]
+ { "Unused3", 187, 186 }, // 0
+ { "biasdrv_lf_ls_byp", 185, 181 }, // biasdrv_lf_ls_byp[4..0]
+ { "tcoeff_lf_ls_byp", 180, 177 }, // tcoeff_lf_ls_byp[3..0]
+ { "biasdrv_lf_byp", 176, 172 },// biasdrv_lf_byp[4..0]
+ { "tcoeff_lf_byp", 171, 168 }, // tcoeff_lf_byp[3..0]
+ { "Unused4", 167, 167 }, // 0
+ { "interpbw", 166, 162 }, // interpbw[4..0]
+ { "pll_cpb", 161, 159 }, // pll_cpb[2..0]
+ { "pll_cps", 158, 156 }, // pll_cps[2..0]
+ { "pll_diffamp", 155, 152 }, // pll_diffamp[3..0]
+ { "Unused5", 151, 150 }, // 0
+ { "cfg_rx_idle_set", 149, 149 }, // cfg_rx_idle_set
+ { "cfg_rx_idle_clr", 148, 148 }, // cfg_rx_idle_clr
+ { "cfg_rx_idle_thr", 147, 144 }, // cfg_rx_idle_thr[3..0]
+ { "cfg_com_thr", 143, 140 }, // cfg_com_thr[3..0]
+ { "cfg_rx_offset", 139, 136 }, // cfg_rx_offset[3..0]
+ { "cfg_skp_max", 135, 132 }, // cfg_skp_max[3..0]
+ { "cfg_skp_min", 131, 128 }, // cfg_skp_min[3..0]
+ { "cfg_fast_pwrup", 127, 127 },// cfg_fast_pwrup
+ { "Unused6", 126, 100 }, // 0
+ { "detected_n", 99, 99 }, // detected_n
+ { "detected_p", 98, 98 }, // detected_p
+ { "dbg_res_rx", 97, 94 }, // dbg_res_rx[3..0]
+ { "dbg_res_tx", 93, 90 }, // dbg_res_tx[3..0]
+ { "cfg_tx_pol_set", 89, 89 }, // cfg_tx_pol_set
+ { "cfg_tx_pol_clr", 88, 88 }, // cfg_tx_pol_clr
+ { "cfg_rx_pol_set", 87, 87 }, // cfg_rx_pol_set
+ { "cfg_rx_pol_clr", 86, 86 }, // cfg_rx_pol_clr
+ { "cfg_rxd_set", 85, 85 }, // cfg_rxd_set
+ { "cfg_rxd_clr", 84, 84 }, // cfg_rxd_clr
+ { "cfg_rxd_wait", 83, 80 },// cfg_rxd_wait[3..0]
+ { "cfg_cdr_limit", 79, 79 }, // cfg_cdr_limit
+ { "cfg_cdr_rotate", 78, 78 }, // cfg_cdr_rotate
+ { "cfg_cdr_bw_ctl", 77, 76 }, // cfg_cdr_bw_ctl[1..0]
+ { "cfg_cdr_trunc", 75, 74 }, // cfg_cdr_trunc[1..0]
+ { "cfg_cdr_rqoffs", 73, 64 }, // cfg_cdr_rqoffs[9..0]
+ { "cfg_cdr_inc2", 63, 58 },// cfg_cdr_inc
[PATCH v2 27/52] mips: octeon: Add cvmx-fpa.c
From: Aaron Williams
Import cvmx-fpa.c from 2013 U-Boot. It will be used by the later
added drivers to support networking on the MIPS Octeon II / III
platforms.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
arch/mips/mach-octeon/cvmx-fpa.c | 1127 ++
1 file changed, 1127 insertions(+)
create mode 100644 arch/mips/mach-octeon/cvmx-fpa.c
diff --git a/arch/mips/mach-octeon/cvmx-fpa.c b/arch/mips/mach-octeon/cvmx-fpa.c
new file mode 100644
index ..14fe87c739c9
--- /dev/null
+++ b/arch/mips/mach-octeon/cvmx-fpa.c
@@ -0,0 +1,1127 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018-2022 Marvell International Ltd.
+ *
+ * Support library for the hardware Free Pool Allocator.
+ */
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+static const int debug;
+
+/* Due to suspected errata, we may not be able to let the FPA_AURAX_CNT
+ * get too close to 0, to avoid a spurious wrap-around error
+ */
+const unsigned int __cvmx_fpa3_cnt_offset = 32;
+
+/* For advanced checks, a guard-band is created around the internal
+ * stack, to make sure the stack is not overwritten.
+ */
+const u64 magic_pattern = 0xbab4faced095f00d;
+const unsigned int guard_band_size = 0 << 10; /* 1KiB default*/
+
+#define CVMX_CACHE_LINE_SHIFT (7)
+
+#define CVMX_FPA3_NAME_LEN (16)
+
+typedef struct {
+ char name[CVMX_FPA3_NAME_LEN];
+ u64 stack_paddr; /* Internal stack storage */
+ u64 bufs_paddr; /* Buffer pool base address */
+ u64 stack_psize; /* Internal stack storage size */
+ u64 bufs_psize; /* Buffer pool raw size */
+ u64 buf_count; /* Number of buffer filled */
+ u64 buf_size;/* Buffer size */
+} cvmx_fpa3_poolx_info_t;
+
+typedef struct {
+ char name[CVMX_FPA3_NAME_LEN];
+ unsigned int buf_size; /* Buffer size */
+} cvmx_fpa3_aurax_info_t;
+
+typedef struct {
+ char name[CVMX_FPA1_NAME_SIZE];
+ u64 size; /* Block size of pool buffers */
+ u64 buffer_count;
+ u64 base_paddr; /* Base physical addr */
+ /* if buffer is allocated at initialization */
+} cvmx_fpa1_pool_info_t;
+
+/**
+ * FPA1/FPA3 info structure is stored in a named block
+ * that is allocated once and shared among applications.
+ */
+static cvmx_fpa1_pool_info_t *cvmx_fpa1_pool_info;
+static cvmx_fpa3_poolx_info_t *cvmx_fpa3_pool_info[CVMX_MAX_NODES];
+static cvmx_fpa3_aurax_info_t *cvmx_fpa3_aura_info[CVMX_MAX_NODES];
+
+/**
+ * Return the size of buffers held in a POOL
+ *
+ * @param pool is the POOL handle
+ * @return buffer size in bytes
+ *
+ */
+int cvmx_fpa3_get_pool_buf_size(cvmx_fpa3_pool_t pool)
+{
+ cvmx_fpa_poolx_cfg_t pool_cfg;
+
+ if (!__cvmx_fpa3_pool_valid(pool))
+ return -1;
+
+ pool_cfg.u64 = csr_rd_node(pool.node, CVMX_FPA_POOLX_CFG(pool.lpool));
+ return pool_cfg.cn78xx.buf_size << CVMX_CACHE_LINE_SHIFT;
+}
+
+/**
+ * Return the size of buffers held in a buffer pool
+ *
+ * @param pool is the pool number
+ *
+ * This function will work with CN78XX models in backward-compatible mode
+ */
+unsigned int cvmx_fpa_get_block_size(int pool)
+{
+ if (octeon_has_feature(OCTEON_FEATURE_FPA3)) {
+ return cvmx_fpa3_get_pool_buf_size(cvmx_fpa3_aura_to_pool(
+ cvmx_fpa1_pool_to_fpa3_aura(pool)));
+ } else {
+ if ((unsigned int)pool >= CVMX_FPA1_NUM_POOLS)
+ return 0;
+ if (!cvmx_fpa1_pool_info)
+ cvmx_fpa_global_init_node(0);
+ return cvmx_fpa1_pool_info[pool].size;
+ }
+}
+
+static void cvmx_fpa3_set_aura_name(cvmx_fpa3_gaura_t aura, const char *name)
+{
+ cvmx_fpa3_aurax_info_t *pinfo;
+
+ pinfo = cvmx_fpa3_aura_info[aura.node];
+ if (!pinfo)
+ return;
+ pinfo += aura.laura;
+ memset(pinfo->name, 0, sizeof(pinfo->name));
+ if (name)
+ strlcpy(pinfo->name, name, sizeof(pinfo->name));
+}
+
+static void cvmx_fpa3_set_pool_name(cvmx_fpa3_pool_t pool, const char *name)
+{
+ cvmx_fpa3_poolx_info_t *pinfo;
+
+ pinfo = cvmx_fpa3_pool_info[pool.node];
+ if (!pinfo)
+ return;
+ pinfo += pool.lpool;
+ memset(pinfo->name, 0, sizeof(pinfo->name));
+ if (name)
+ strlcpy(pinfo->name, name, sizeof(pinfo->name));
+}
+
+static void cvmx_fpa_set_name(int pool_num, const char *name)
+{
+ if (octeon_has_feature(OCTEON_FEATURE_FPA3)) {
+ cvmx_fpa3_set_aura_name(cvmx_fpa1_pool_t
[PATCH] drivers: usb: dwc3: Add support for AM62 USB wrapper driver
Add support for AM62 USB wrapper for DWC3 Controller in AM62 SoC.
Signed-off-by: Aswath Govindraju
---
Link to corresponding kernel dt-bindings and driver patches,
- https://patchwork.kernel.org/project/linux-usb/list/?series=629613
drivers/usb/dwc3/Kconfig | 7 +
drivers/usb/dwc3/Makefile| 1 +
drivers/usb/dwc3/dwc3-am62.c | 284 +++
3 files changed, 292 insertions(+)
create mode 100644 drivers/usb/dwc3/dwc3-am62.c
diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
index 62aa65bf0cd2..87e19720ab84 100644
--- a/drivers/usb/dwc3/Kconfig
+++ b/drivers/usb/dwc3/Kconfig
@@ -63,6 +63,13 @@ config USB_DWC3_LAYERSCAPE
Host and Peripheral operation modes are supported. OTG is not
supported.
+config USB_DWC3_AM62
+ tristate "Texas Instruments AM62 Platforms"
+ depends on ARCH_K3 || COMPILE_TEST
+ default USB_DWC3
+ help
+ Support of USB2 functionality in TI's AM62 platforms
+
menu "PHY Subsystem"
config USB_DWC3_PHY_OMAP
diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
index 0dd1ba87cd94..26bc3a7379b7 100644
--- a/drivers/usb/dwc3/Makefile
+++ b/drivers/usb/dwc3/Makefile
@@ -7,6 +7,7 @@ dwc3-y := core.o
obj-$(CONFIG_USB_DWC3_GADGET) += gadget.o ep0.o
obj-$(CONFIG_USB_DWC3_OMAP)+= dwc3-omap.o
+obj-$(CONFIG_USB_DWC3_AM62)+= dwc3-am62.o
obj-$(CONFIG_USB_DWC3_MESON_G12A) += dwc3-meson-g12a.o
obj-$(CONFIG_USB_DWC3_MESON_GXL) += dwc3-meson-gxl.o
obj-$(CONFIG_USB_DWC3_GENERIC) += dwc3-generic.o
diff --git a/drivers/usb/dwc3/dwc3-am62.c b/drivers/usb/dwc3/dwc3-am62.c
new file mode 100644
index ..a3ad609036e2
--- /dev/null
+++ b/drivers/usb/dwc3/dwc3-am62.c
@@ -0,0 +1,284 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dwc3-am62.c - TI specific Glue layer for AM62 DWC3 USB Controller
+ *
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* USB WRAPPER register offsets */
+#define USBSS_PID 0x0
+#define USBSS_OVERCURRENT_CTRL 0x4
+#define USBSS_PHY_CONFIG 0x8
+#define USBSS_PHY_TEST 0xc
+#define USBSS_CORE_STAT0x14
+#define USBSS_HOST_VBUS_CTRL 0x18
+#define USBSS_MODE_CONTROL 0x1c
+#define USBSS_WAKEUP_CONFIG0x30
+#define USBSS_WAKEUP_STAT 0x34
+#define USBSS_OVERRIDE_CONFIG 0x38
+#define USBSS_IRQ_MISC_STATUS_RAW 0x430
+#define USBSS_IRQ_MISC_STATUS 0x434
+#define USBSS_IRQ_MISC_ENABLE_SET 0x438
+#define USBSS_IRQ_MISC_ENABLE_CLR 0x43c
+#define USBSS_IRQ_MISC_EOI 0x440
+#define USBSS_INTR_TEST0x490
+#define USBSS_VBUS_FILTER 0x614
+#define USBSS_VBUS_STAT0x618
+#define USBSS_DEBUG_CFG0x708
+#define USBSS_DEBUG_DATA 0x70c
+#define USBSS_HOST_HUB_CTRL0x714
+
+/* PHY CONFIG register bits */
+#define USBSS_PHY_VBUS_SEL_MASKGENMASK(2, 1)
+#define USBSS_PHY_VBUS_SEL_SHIFT 1
+#define USBSS_PHY_LANE_REVERSE BIT(0)
+
+/* MODE CONTROL register bits */
+#define USBSS_MODE_VALID BIT(0)
+
+/* IRQ_MISC_STATUS_RAW register bits */
+#define USBSS_IRQ_MISC_RAW_VBUSVALID BIT(22)
+#define USBSS_IRQ_MISC_RAW_SESSVALID BIT(20)
+
+/* IRQ_MISC_STATUS register bits */
+#define USBSS_IRQ_MISC_VBUSVALID BIT(22)
+#define USBSS_IRQ_MISC_SESSVALID BIT(20)
+
+/* IRQ_MISC_ENABLE_SET register bits */
+#define USBSS_IRQ_MISC_ENABLE_SET_VBUSVALIDBIT(22)
+#define USBSS_IRQ_MISC_ENABLE_SET_SESSVALIDBIT(20)
+
+/* IRQ_MISC_ENABLE_CLR register bits */
+#define USBSS_IRQ_MISC_ENABLE_CLR_VBUSVALIDBIT(22)
+#define USBSS_IRQ_MISC_ENABLE_CLR_SESSVALIDBIT(20)
+
+/* VBUS_STAT register bits */
+#define USBSS_VBUS_STAT_SESSVALID BIT(2)
+#define USBSS_VBUS_STAT_VBUSVALID BIT(0)
+
+/* Mask for PHY PLL REFCLK */
+#define PHY_PLL_REFCLK_MASKGENMASK(3, 0)
+
+struct dwc3_data {
+ struct udevice *dev;
+ void __iomem *usbss;
+ struct regmap *syscon;
+ unsigned int offset;
+ unsigned int vbus_divider;
+};
+
+static inline u32 dwc3_ti_readl(struct dwc3_data *data, u32 offset)
+{
+ return readl(data->usbss + offset);
+}
+
+static inline void dwc3_ti_writel(struct dwc3_data *data, u32 offset, u32
value)
+{
+ writel(value, data->usbss + offset);
+}
+
+static const int dwc3_ti_rate_table[] = { /* in KHZ */
+ 9600,
+ 1,
+ 12000,
+ 19200,
+ 2,
+ 24000,
+ 25000,
+ 26000,
+ 38400,
+ 4,
+ 58000,
+ 5,
+ 52000,
+};
+
+static int phy_syscon_pll
Re: [PATCH] squashfs: Fix compilation on big endian systems
Hi Pali, p...@kernel.org wrote on Wed, 6 Apr 2022 23:31:53 +0200: Would you mind explaining a little bit how this change fixes it? It does not look straightforward to me. > Signed-off-by: Pali Rohár > --- > fs/squashfs/sqfs.c | 3 +-- > fs/squashfs/sqfs_dir.c | 3 +-- > 2 files changed, 2 insertions(+), 4 deletions(-) > > diff --git a/fs/squashfs/sqfs.c b/fs/squashfs/sqfs.c > index 5d9c52af80ba..41cb811c1b32 100644 > --- a/fs/squashfs/sqfs.c > +++ b/fs/squashfs/sqfs.c > @@ -11,8 +11,7 @@ > #include > #include > #include > -#include > -#include > +#include > #include > #include > #include > diff --git a/fs/squashfs/sqfs_dir.c b/fs/squashfs/sqfs_dir.c > index a265b98fe685..ed83c90682ff 100644 > --- a/fs/squashfs/sqfs_dir.c > +++ b/fs/squashfs/sqfs_dir.c > @@ -7,8 +7,7 @@ > > #include > #include > -#include > -#include > +#include > #include > #include > #include Cheers, Miquèl
Re: [PATCH v6 7/7] fpga: zynqmp: support loading encrypted bitfiles
On 2/7/22 12:18, Adrian Fiergolski wrote:
Add supporting new compatible string "u-boot,zynqmp-fpga-enc" to handle
loading encrypted bitfiles.
This feature requires encrypted FSBL,as according to UG1085:
"The CSU automatically locks out the AES key, stored in either BBRAM or eFUSEs,
as a key source to the AES engine if the FSBL is not encrypted. This prevents
using the BBRAM or eFUSE as the key source to the AES engine during run-time
applications."
Signed-off-and-tested-by: Adrian Fiergolski
---
doc/uImage.FIT/source_file_format.txt | 2 ++
drivers/fpga/zynqmppl.c | 16
2 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/doc/uImage.FIT/source_file_format.txt
b/doc/uImage.FIT/source_file_format.txt
index 461e2af2a8..2cf77ba3e9 100644
--- a/doc/uImage.FIT/source_file_format.txt
+++ b/doc/uImage.FIT/source_file_format.txt
@@ -188,6 +188,8 @@ the '/images' node should have the following layout:
"u-boot,fpga-legacy" - the generic fpga loading routine.
"u-boot,zynqmp-fpga-ddrauth" - signed non-encrypted FPGA bitstream for
Xilinx Zynq UltraScale+ (ZymqMP) device.
+"u-boot,zynqmp-fpga-enc" - encrypted FPGA bitstream for Xilinx Zynq
+UltraScale+ (ZymqMP) device.
ZynqMP
Optional nodes:
- hash-1 : Each hash sub-node represents separate hash or checksum
diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c
index bf6f56e1c4..5fcca8d1b8 100644
--- a/drivers/fpga/zynqmppl.c
+++ b/drivers/fpga/zynqmppl.c
@@ -214,7 +214,9 @@ static int zynqmp_load(xilinx_desc **desc_ptr, const void
*buf, size_t bsize,
fpga_desc *fdesc = container_of((void *)desc_ptr, fpga_desc, devdesc);
if (fdesc && fdesc->compatible &&
- !strcmp(fdesc->compatible, "u-boot,zynqmp-fpga-ddrauth")) {
+ ( !strcmp(fdesc->compatible, "u-boot,zynqmp-fpga-ddrauth") ||
+ !strcmp(fdesc->compatible, "u-boot,zynqmp-fpga-enc") )
+ ) {
coding style and I think you should revert the logic here. You should check
u-boot-fpga-legacy and use inverted logic if possible which should save some bytes.
And strncmp
if (CONFIG_IS_ENABLED(FPGA_LOAD_SECURE)) {
struct fpga_secure_info info = { 0 };
@@ -222,9 +224,15 @@ static int zynqmp_load(xilinx_desc **desc_ptr, const void *buf, size_t bsize,
printf("%s: Missing load operation\n",
__func__);
return FPGA_FAIL;
}
- /* DDR authentication */
- info.authflag = 1;
- info.encflag = 2;
+ if(!strcmp(fdesc->compatible+19, "enc")){
coding style issues and use strncmp.
+ /* Encryption using device key*/
coding style issues.
+ info.authflag = 2;
+ info.encflag = 0;
You should use macros for it.
+ } else {
+ /* DDR authentication */
+ info.authflag = 1;
+ info.encflag = 2;
ditto.
+ }
return desc->operations->loads(desc, buf, bsize, &info);
} else {
printf("No support for %s\n", fdesc->compatible);
M
Re: [PATCH v6 6/7] fpga: zynqmp: support loading authenticated images
On 2/7/22 12:18, Adrian Fiergolski wrote:
From: Oleksandr Suvorov
Add supporting new compatible string "u-boot,zynqmp-fpga-ddrauth" to
handle loading authenticated images (DDR).
Based on solution by Jorge Ramirez-Ortiz
Signed-off-by: Oleksandr Suvorov
Co-developed-by: Ricardo Salveti
Signed-off-by: Ricardo Salveti
Tested-by: Ricardo Salveti
---
boot/Kconfig | 4 ++--
doc/uImage.FIT/source_file_format.txt | 5 -
drivers/fpga/zynqmppl.c | 21 +
3 files changed, 27 insertions(+), 3 deletions(-)
diff --git a/boot/Kconfig b/boot/Kconfig
index b83a4e8400..f7faafb29f 100644
--- a/boot/Kconfig
+++ b/boot/Kconfig
@@ -209,8 +209,8 @@ config SPL_LOAD_FIT
1. "loadables" images, other than FDTs, which do not have a "load"
property will not be loaded. This limitation also applies to FPGA
images with the correct "compatible" string.
- 2. For FPGA images, only the "compatible" = "u-boot,fpga-legacy"
-loading method is supported.
+ 2. For FPGA images, the supported "compatible" list is in the
+doc/uImage.FIT/source_file_format.txt.
3. FDTs are only loaded for images with an "os" property of "u-boot".
"linux" images are also supported with Falcon boot mode.
diff --git a/doc/uImage.FIT/source_file_format.txt b/doc/uImage.FIT/source_file_format.txt
index f93ac6d1c7..461e2af2a8 100644
--- a/doc/uImage.FIT/source_file_format.txt
+++ b/doc/uImage.FIT/source_file_format.txt
@@ -184,7 +184,10 @@ the '/images' node should have the following layout:
Mandatory for types: "firmware", and "kernel".
- compatible : compatible method for loading image.
Mandatory for types: "fpga", and images that do not specify a load
address.
-To use the generic fpga loading routine, use "u-boot,fpga-legacy".
+Supported compatible methods:
+"u-boot,fpga-legacy" - the generic fpga loading routine.
+"u-boot,zynqmp-fpga-ddrauth" - signed non-encrypted FPGA bitstream for
+Xilinx Zynq UltraScale+ (ZymqMP) device.
Optional nodes:
- hash-1 : Each hash sub-node represents separate hash or checksum
diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c
index c7f9f4ae84..bf6f56e1c4 100644
--- a/drivers/fpga/zynqmppl.c
+++ b/drivers/fpga/zynqmppl.c
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -210,6 +211,26 @@ static int zynqmp_load(xilinx_desc **desc_ptr, const void
*buf, size_t bsize,
u32 ret_payload[PAYLOAD_ARG_CNT];
bool xilfpga_old = false;
xilinx_desc *desc = *desc_ptr;
+ fpga_desc *fdesc = container_of((void *)desc_ptr, fpga_desc, devdesc);
+
+ if (fdesc && fdesc->compatible &&
+ !strcmp(fdesc->compatible, "u-boot,zynqmp-fpga-ddrauth")) {
+ if (CONFIG_IS_ENABLED(FPGA_LOAD_SECURE)) {
+ struct fpga_secure_info info = { 0 };
+
+ if (!desc->operations->loads) {
+ printf("%s: Missing load operation\n",
__func__);
+ return FPGA_FAIL;
+ }
+ /* DDR authentication */
+ info.authflag = 1;
+ info.encflag = 2;
+ return desc->operations->loads(desc, buf, bsize, &info);
+ } else {
Please run checkpatch on every patch. Then you would see this error.
WARNING: else is not generally useful after a break or return
#89: FILE: drivers/fpga/zynqmppl.c:229:
+ return desc->operations->loads(desc, buf, bsize, &info);
+ } else {
M
+ printf("No support for %s\n", fdesc->compatible);
+ return FPGA_FAIL;
+ }
+ }
if (zynqmp_firmware_version() <= PMUFW_V1_0) {
puts("WARN: PMUFW v1.0 or less is detected\n");
Re: [PATCH v6 3/7] fpga: xilinx: pass an address of xilinx_desc in fpga_desc
On 2/7/22 12:18, Adrian Fiergolski wrote: From: Oleksandr Suvorov Pass an address of xilinx_desc pointer in an fpga_desc to use parent double space here. M
Re: [PATCH v6 1/7] fpga: add option for loading FPGA secure bitstreams
On 2/7/22 12:18, Adrian Fiergolski wrote: From: Oleksandr Suvorov It allows using this feature without enabling the "fpga loads" command. Signed-off-by: Oleksandr Suvorov Tested-by: Ricardo Salveti --- cmd/Kconfig | 3 ++- drivers/fpga/Kconfig| 14 ++ drivers/fpga/fpga.c | 2 +- drivers/fpga/xilinx.c | 2 +- drivers/fpga/zynqmppl.c | 4 ++-- 5 files changed, 20 insertions(+), 5 deletions(-) diff --git a/cmd/Kconfig b/cmd/Kconfig index 5e25e45fd2..604ab37f3b 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -949,8 +949,9 @@ config CMD_FPGA_LOADP a partial bitstream. config CMD_FPGA_LOAD_SECURE - bool "fpga loads - loads secure bitstreams (Xilinx only)" + bool "fpga loads - loads secure bitstreams" depends on CMD_FPGA + select FPGA_LOAD_SECURE help Enables the fpga loads command which is used to load secure (authenticated or encrypted or both) bitstreams on to FPGA. diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index dc0b3dd31b..262f95a252 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -85,4 +85,18 @@ config FPGA_ZYNQPL Enable FPGA driver for loading bitstream in BIT and BIN format on Xilinx Zynq devices. +config FPGA_LOAD_SECURE + bool "Enable loading secure bitstreams" + depends on FPGA + help + Enables the fpga loads() functions that are used to load secure + (authenticated or encrypted or both) bitstreams on to FPGA. + +config SPL_FPGA_LOAD_SECURE + bool "Enable loading secure bitstreams for SPL" + depends on FPGA This should be SPL_FPGA M
Re: [PATCH] misc: atsha204a: Fix big endian support
On Monday 04 April 2022 09:43:21 Stefan Roese wrote: > On 4/3/22 00:36, Pali Rohár wrote: > > Callers of function atsha204a_crc16() expect to return value in host cpu > > endianity. So remove cpu_to_le16() conversion. > > > > Signed-off-by: Pali Rohár > > Reviewed-by: Stefan Roese Hello Stefan! Would you or somebody else take this patch? Because I have some other u-boot generic patches which touches this driver and I'm waiting until this simple change would be merged first. > Thanks, > Stefan > > > --- > > drivers/misc/atsha204a-i2c.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/misc/atsha204a-i2c.c b/drivers/misc/atsha204a-i2c.c > > index b89463babb56..63fe541dade3 100644 > > --- a/drivers/misc/atsha204a-i2c.c > > +++ b/drivers/misc/atsha204a-i2c.c > > @@ -146,7 +146,7 @@ static u16 atsha204a_crc16(const u8 *buffer, size_t len) > > while (len--) > > crc = crc16_byte(crc, *buffer++); > > - return cpu_to_le16(crc); > > + return crc; > > } > > static int atsha204a_send(struct udevice *dev, const u8 *buf, u8 len) > > Viele Grüße, > Stefan Roese > > -- > DENX Software Engineering GmbH, Managing Director: Wolfgang Denk > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany > Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH] imx: power-domain: Add i.MX8MP support
On 4/7/22 06:01, Peng Fan (OSS) wrote: On 2022/4/1 9:12, Marek Vasut wrote: Add i.MX8MP power domain handling into the driver. This is based on the Linux GPCv2 driver state which is soon to be in Linux next. Do we really need this in U-Boot? You will also port the blk-ctrl part? That would be lots code! I already did sent HSIOMIX driver too, that's all we need to get USB and PCIe going in U-Boot, and get U-Boot working without running ATF, which makes new platform bring up far easier. The "lots of code" that's in Linux is for graphics pipeline and we don't need that in U-Boot, so we conveniently avoid it here.
Re: [PATCH v6 2/7] fpga: add fit_fpga_load function
On 2/7/22 12:18, Adrian Fiergolski wrote:
From: Oleksandr Suvorov
Introduce a function which passes an fpga compatible string from
FIT images to FPGA drivers. This lets the different implementations
decide how to handle it.
Some code of Jorge Ramirez-Ortiz is reused.
Signed-off-by: Oleksandr Suvorov
Tested-by: Ricardo Salveti
---
common/spl/spl_fit.c | 6 ++
drivers/fpga/fpga.c | 35 ---
include/fpga.h | 4
3 files changed, 34 insertions(+), 11 deletions(-)
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 1bbf824684..0e3c2a94b6 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -588,11 +588,9 @@ static int spl_fit_upload_fpga(struct spl_fit_info *ctx,
int node,
compatible = fdt_getprop(ctx->fit, node, "compatible", NULL);
if (!compatible)
warn_deprecated("'fpga' image without 'compatible' property");
- else if (strcmp(compatible, "u-boot,fpga-legacy"))
- printf("Ignoring compatible = %s property\n", compatible);
- ret = fpga_load(0, (void *)fpga_image->load_addr, fpga_image->size,
- BIT_FULL);
+ ret = fit_fpga_load(0, (void *)fpga_image->load_addr, fpga_image->size,
+ BIT_FULL, compatible);
if (ret) {
printf("%s: Cannot load the image to the FPGA\n", __func__);
return ret;
diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c
index 3b0a44b242..2266c7d83a 100644
--- a/drivers/fpga/fpga.c
+++ b/drivers/fpga/fpga.c
@@ -197,9 +197,9 @@ int fpga_fsload(int devnum, const void *buf, size_t size,
fpga_fs_info *fpga_fsinfo)
{
int ret_val = FPGA_FAIL; /* assume failure */
- const fpga_desc *desc = fpga_validate(devnum, buf, size,
- (char *)__func__);
+ const fpga_desc *desc;
+ desc = fpga_validate(devnum, buf, size, (char *)__func__);
this is unrelated to core change.
if (desc) {
switch (desc->devtype) {
case fpga_xilinx:
@@ -225,10 +225,9 @@ int fpga_loads(int devnum, const void *buf, size_t size,
struct fpga_secure_info *fpga_sec_info)
{
int ret_val = FPGA_FAIL;
+ const fpga_desc *desc;
- const fpga_desc *desc = fpga_validate(devnum, buf, size,
- (char *)__func__);
-
+ desc = fpga_validate(devnum, buf, size, (char *)__func__);
the same here.
if (desc) {
switch (desc->devtype) {
case fpga_xilinx:
@@ -249,15 +248,31 @@ int fpga_loads(int devnum, const void *buf, size_t size,
}
#endif
+int fit_fpga_load(int devnum, const void *buf, size_t bsize,
+ bitstream_type bstype, const char *compatible)
+{
+ fpga_desc *desc = (fpga_desc *)fpga_validate(devnum, buf, bsize,
+ (char *)__func__);
This is the first fpga_validate() call
+
+ if (!desc)
+ return FPGA_FAIL;
+ /*
+* Store the compatible string to proceed it in underlying
+* functions
+*/
+ desc->compatible = (char *)compatible;
+
+ return fpga_load(devnum, buf, bsize, bstype);
and inside fpga_load there is another fpga_validate call again.
+}
missing newline
/*
- * Generic multiplexing code
+ * Generic multiplexing code:
+ * Each architecture must handle the mandatory FPGA DT compatible property.
*/
int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type
bstype)
{
int ret_val = FPGA_FAIL; /* assume failure */
const fpga_desc *desc = fpga_validate(devnum, buf, bsize,
(char *)__func__);
-
unrelated.
if (desc) {
switch (desc->devtype) {
case fpga_xilinx:
@@ -270,6 +285,9 @@ int fpga_load(int devnum, const void *buf, size_t bsize,
bitstream_type bstype)
break;
case fpga_altera:
#if defined(CONFIG_FPGA_ALTERA)
+ if (strncmp(desc->compatible, "u-boot,fpga-legacy", 18))
+ printf("Ignoring compatible = %s property\n",
+ desc->compatible);
ret_val = altera_load(desc->devdesc, buf, bsize);
#else
fpga_no_sup((char *)__func__, "Altera devices");
@@ -277,6 +295,9 @@ int fpga_load(int devnum, const void *buf, size_t bsize,
bitstream_type bstype)
break;
case fpga_lattice:
#if defined(CONFIG_FPGA_LATTICE)
+ if (strncmp(desc->compatible, "u-boot,fpga-legacy", 18))
+ printf("Ignoring compatible = %s property\n",
+ desc->compatible);
ret_val = lattice_load(desc->dev
Re: [PATCH v6 0/7] fpga: zynqmp: Adding support of loading authenticated images
Hi, On 2/7/22 12:18, Adrian Fiergolski wrote: This patchset introduces support for the authenticated FPGA images on ZynqMP boards, besides that introducing common way to pass the compatible property to any fpga driver. It bases on the initial work by Jorge Ramirez-Ortiz https://patchwork.ozlabs.org/project/uboot/patch/20211015091506.2602-1-jo...@foundries.io/ https://patchwork.ozlabs.org/project/uboot/patch/20211005111324.19749-3-jo...@foundries.io/ Changed in v6: - add support for the encrypted bitfiles Changes in v5: - replace ifdef with if() where it's possible Changes in v4: - change interface to xilinx_desc->operations->open() callback. - fix a bug from previous version of the patchset in dereferencing of a parent fpga_desc structure. Changes in v3: - remove the patch which introduced CMD_SPL_FPGA_LOAD_SECURE. - fix mixing definitions/declarations. - replace strcmp() calls with more secure strncmp(). - document the "u-boot,zynqmp-fpga-ddrauth" compatible string. - fix code style by check-patch recommendations. Changes in v2: - add function fit_fpga_load() to simplify calls of fpga_load() from contexts without a compatible attribute. - move all ZynqMP-specific logic to drivers/fpga/zynqmppl.c - prepare for passing a "compatible" FDT property to any fpga driver. Oleksandr Suvorov (6): fpga: add option for loading FPGA secure bitstreams fpga: add fit_fpga_load function fpga: xilinx: pass an address of xilinx_desc in fpga_desc fpga: xilinx: add missed identifier names fpga: xilinx: pass xilinx_desc pointer address into load() ops fpga: zynqmp: support loading authenticated images Adrian Fiergolski (1): fpga: zynqmp: support loading encrypted bitfiles sorry for delay. My biggest problem with this series is that if SPL_FPGA_LOAD_SECURE is not enabled when this series is applied I see what we are adding 216 Bytes without any benefit when this option is disabled. Please use buildman and make sure that there is only reasonable number of bytes added when this option is not enabled. Thanks, Michal
Re: [PATCH] riscv: Fix build against binutils 2.38
Hi Alex, On Thu, Mar 10, 2022 at 09:03:08AM +0100, Alexandre Ghiti wrote: > Hi Leo, > > On Wed, Mar 9, 2022 at 7:31 AM Leo Liang wrote: > > > > Hi Alex, > > On Thu, Mar 03, 2022 at 11:06:18AM +, Leo Liang wrote: > > > Hi Alex, > > > On Tue, Mar 01, 2022 at 03:21:56AM +, Leo Liang wrote: > > > > Hi Alex, > > > > On Mon, Feb 21, 2022 at 05:42:41PM +0100, Alexandre Ghiti wrote: > > > > > On Sat, Feb 19, 2022 at 9:52 AM Leo Liang > > > > > wrote: > > > > > > > > > > > > Hi Alex, > > > > > > On Thu, Feb 17, 2022 at 11:28:46AM +0100, Alexandre Ghiti wrote: > > > > > > > Hi Leo, > > > > > > > > > > > > > > On Thu, Feb 17, 2022 at 10:25 AM Leo Liang > > > > > > > wrote: > > > > > > > > > > > > > > > > Hi Alexandre, > > > > > > > > On Fri, Jan 28, 2022 at 02:47:13PM +0100, Alexandre Ghiti wrote: > > > > > > > > > The following description is copied from the equivalent patch > > > > > > > > > for the > > > > > > > > > Linux Kernel proposed by Aurelien Jarno: > > > > > > > > > > > > > > > > > > From version 2.38, binutils default to ISA spec version > > > > > > > > > 20191213. This > > > > > > > > > means that the csr read/write (csrr*/csrw*) instructions and > > > > > > > > > fence.i > > > > > > > > > instruction has separated from the `I` extension, become two > > > > > > > > > standalone > > > > > > > > > extensions: Zicsr and Zifencei. As the kernel uses those > > > > > > > > > instruction, > > > > > > > > > this causes the following build failure: > > > > > > > > > > > > > > > > > > arch/riscv/cpu/mtrap.S: Assembler messages: > > > > > > > > > arch/riscv/cpu/mtrap.S:65: Error: unrecognized opcode `csrr > > > > > > > > > a0,scause' > > > > > > > > > arch/riscv/cpu/mtrap.S:66: Error: unrecognized opcode `csrr > > > > > > > > > a1,sepc' > > > > > > > > > arch/riscv/cpu/mtrap.S:67: Error: unrecognized opcode `csrr > > > > > > > > > a2,stval' > > > > > > > > > arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw > > > > > > > > > sepc,a0' > > > > > > > > > > > > > > > > > > Signed-off-by: Alexandre Ghiti > > > > > > > > > --- > > > > > > > > > arch/riscv/Makefile | 11 ++- > > > > > > > > > 1 file changed, 10 insertions(+), 1 deletion(-) > > > > > > > > > > > > > > > > This patch seems to fail CI somehow. > > > > > > > > (https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/11004) > > > > > > > > > > > > > > > > Could you take a look at it ? > > > > > > > > > > > > > > I have just tried on master (commit ab8903a24db1) and it failed > > > > > > > for > > > > > > > the same reason, so this is not related to this patch. > > > > > > > Nevertheless, > > > > > > > I'll try to bisect the problem :) > > > > > > > > > > > > > > Thanks, > > > > > > > > > > > > > > Alex > > > > > > > > > > > > > > > > > > > Thanks for putting the effort into it! > > > > > > > > > > > > AFAIK, this patch does nothing related to the error message > > > > > > "undefined reference to `__ashldi3'" from the failed CI. > > > > > > > > > > > > Nonetheless, I have tried a few times myself, > > > > > > and found that CI could pass with ab8903a24db1 but cannot pass with > > > > > > this patch on my side. > > > > > > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/commits/staging > > > > > > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines > > > > > > > > > > > > > > > > To me it is an issue with the toolchain: libgcc is missing those > > > > > symbols. If I use an Ubuntu toolchain, it fails no matter which commit > > > > > I am on (I tested as far as v2021.10). But if I use a toolchain from > > > > > https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/, > > > > > it works fine. > > > > > > > > > > What I don't understand is how you manage to have different build > > > > > results with the same docker image: can you confirm that you use the > > > > > same toolchains in the following builds? > > > > > > > > > > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/jobs/393701 > > > > > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/jobs/393783 > > > > > > > > > > > > > Sorry for the late reply. > > > > I have checked the toolchain version of these two builds, > > > > they are using the same toolchain[1] from Tom's docker image on docker > > > > hub[2]. > > > > > > > > Also the fail is reproducible using this docker image with the > > > > following commands: > > > > > > > > leo@host sudo docker run -it --name leo-test > > > > trini/u-boot-gitlab-ci-runner:focal-20220113-03Feb2022 /bin/bash > > > > uboot@356268d27bf0:~$ git clone > > > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git && cd > > > > u-boot-riscv > > > > uboot@356268d27bf0:~/u-boot-riscv$ git checkout staging > > > > uboot@356268d27bf0:~/u-boot-riscv$ export > > > > PATH=/opt/gcc-11.1.0-nolibc/riscv64-linux/bin:$PATH > > > > uboot@356268d27bf0:~/u-boot-riscv$ export CROSS_COMPILE=riscv64-linux- > > > > uboot@356268d27bf0:~/u-boot-riscv$ make qemu-riscv32_spl_defconfig >
[PATCH] arm: mvebu: a37xx: Add support for writing Security OTP values
Implement write support for Security OTP values via mailbox API commands
MBOX_CMD_OTP_WRITE_32B and MBOX_CMD_OTP_WRITE.
Write support for North and South Bridge OTPs are not implemented as these
OTPs are already burned in factory with some data.
Signed-off-by: Pali Rohár
---
This patch depends on series which implements read support for A3720 OTP:
https://patchwork.ozlabs.org/project/uboot/list/?series=287578&state=*
Stefan, what do you think, should be enable write support by default. Or
should it be hidden under some other CONFIG option? Becaue currently
CONFIG_CMD_FUSE enable both read and write support (or what driver
implements).
---
arch/arm/mach-mvebu/armada3700/efuse.c | 50 --
1 file changed, 48 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-mvebu/armada3700/efuse.c
b/arch/arm/mach-mvebu/armada3700/efuse.c
index 50c73f36c565..07d5f394354c 100644
--- a/arch/arm/mach-mvebu/armada3700/efuse.c
+++ b/arch/arm/mach-mvebu/armada3700/efuse.c
@@ -113,6 +113,41 @@ static int rwtm_otp_read(u8 row, u32 word, u32 *data)
return res;
}
+static int rwtm_otp_write(u8 row, u32 word, u32 data)
+{
+ u32 in[4];
+ int res = -EINVAL;
+
+ if (word < 2) {
+ /*
+* MBOX_CMD_OTP_WRITE_32B command is supported by Marvell
+* fuse.bin firmware and also by new CZ.NIC wtmi firmware.
+* This command writes only selected bits to OTP and does
+* not calculate ECC bits. It does not allow to write the
+* lock bit.
+*/
+ in[0] = row;
+ in[1] = word * 32;
+ in[2] = data;
+ res = mbox_do_cmd(MBOX_CMD_OTP_WRITE_32B, in, 3, NULL, 0);
+ } else if (word == 2 && !(data & ~0x1)) {
+ /*
+* MBOX_CMD_OTP_WRITE command is supported only by new CZ.NIC
+* wtmi firmware and allows to write any bit to OTP, including
+* the lock bit. It does not calculate or write ECC bits too.
+* For compatibility with Marvell fuse.bin firmware, use this
+* command only for writing the lock bit.
+*/
+ in[0] = row;
+ in[1] = 0;
+ in[2] = 0;
+ in[3] = data;
+ res = mbox_do_cmd(MBOX_CMD_OTP_WRITE, in, 4, NULL, 0);
+ }
+
+ return res;
+}
+
/*
* Banks 0-43 are used for accessing Security OTP (44 rows with 67 bits via 44
banks and words 0-2)
* Bank 44 is used for accessing North Bridge OTP (69 bits via words 0-2)
@@ -154,8 +189,19 @@ int fuse_read(u32 bank, u32 word, u32 *val)
int fuse_prog(u32 bank, u32 word, u32 val)
{
- /* TODO: not implemented yet */
- return -ENOSYS;
+ if (bank <= RWTM_MAX_BANK) {
+ if (word >= RWTM_ROW_WORDS)
+ return -EINVAL;
+ return rwtm_otp_write(bank, word, val);
+ } else if (bank == OTP_NB_BANK) {
+ /* TODO: not implemented yet */
+ return -ENOSYS;
+ } else if (bank == OTP_SB_BANK) {
+ /* TODO: not implemented yet */
+ return -ENOSYS;
+ } else {
+ return -EINVAL;
+ }
}
int fuse_sense(u32 bank, u32 word, u32 *val)
--
2.20.1
[PATCH] tools: add boot/ to .gitignore
/tools/boot/ is a build product. Add it to .gitignore Signed-off-by: Du Huanpeng --- tools/.gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/.gitignore b/tools/.gitignore index a88453f64d..d3a93ff294 100644 --- a/tools/.gitignore +++ b/tools/.gitignore @@ -36,3 +36,4 @@ /update_octeon_header /version.h /xway-swap-bytes +/boot -- 2.25.1
[PATCH 01/11] sandbox: Set the EFI symbols in linker script
The sandbox doesn't populate the EFI lists so explicitly set the list
start and end symbols to indicate that the lists are empty. This
simplifies the linker scripts, removed references to non-existant
sections and removes '.' prefixed sections that conflicted with clang's
ASAN.
Signed-off-by: Andrew Scull
---
arch/sandbox/cpu/u-boot.lds | 32 +---
arch/sandbox/lib/Makefile | 2 +-
arch/sandbox/lib/sections.c | 13 -
3 files changed, 6 insertions(+), 41 deletions(-)
delete mode 100644 arch/sandbox/lib/sections.c
diff --git a/arch/sandbox/cpu/u-boot.lds b/arch/sandbox/cpu/u-boot.lds
index 6d710618f5..dd675cc3d2 100644
--- a/arch/sandbox/cpu/u-boot.lds
+++ b/arch/sandbox/cpu/u-boot.lds
@@ -19,33 +19,11 @@ SECTIONS
*(.u_boot_sandbox_getopt_end)
}
- .__efi_runtime_start : {
- *(.__efi_runtime_start)
- }
-
- .efi_runtime : {
- *(efi_runtime_text)
- *(efi_runtime_data)
- }
-
- .__efi_runtime_stop : {
- *(.__efi_runtime_stop)
- }
-
- .efi_runtime_rel_start :
- {
- *(.__efi_runtime_rel_start)
- }
-
- .efi_runtime_rel : {
- *(.relefi_runtime_text)
- *(.relefi_runtime_data)
- }
-
- .efi_runtime_rel_stop :
- {
- *(.__efi_runtime_rel_stop)
- }
+ /* Sandbox has empty EFI runtime lists. */
+ __efi_runtime_start = .;
+ __efi_runtime_stop = __efi_runtime_start;
+ __efi_runtime_rel_start = .;
+ __efi_runtime_rel_stop = __efi_runtime_rel_start;
.dynsym :
{
diff --git a/arch/sandbox/lib/Makefile b/arch/sandbox/lib/Makefile
index a2bc5a7ee6..05f06180f8 100644
--- a/arch/sandbox/lib/Makefile
+++ b/arch/sandbox/lib/Makefile
@@ -5,7 +5,7 @@
# (C) Copyright 2002-2006
# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
-obj-y += fdt_fixup.o interrupts.o sections.o
+obj-y += fdt_fixup.o interrupts.o
obj-$(CONFIG_PCI) += pci_io.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-$(CONFIG_CMD_BOOTZ) += bootm.o
diff --git a/arch/sandbox/lib/sections.c b/arch/sandbox/lib/sections.c
deleted file mode 100644
index 2559eeea38..00
--- a/arch/sandbox/lib/sections.c
+++ /dev/null
@@ -1,13 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Albert ARIBAUD
- *
- */
-#include
-
-char __efi_runtime_start[0] __section(".__efi_runtime_start");
-char __efi_runtime_stop[0] __section(".__efi_runtime_stop");
-char __efi_runtime_rel_start[0]
- __section(".__efi_runtime_rel_start");
-char __efi_runtime_rel_stop[0]
- __section(".__efi_runtime_rel_stop");
--
2.35.1.1094.g7c7d902a7c-goog
[PATCH 02/11] sandbox: Migrate getopt section to linker list
Use the common infrastructure to create a linker list of the sandbox
command line flags rather than using a custom method.
The list is changed from containing pointers to containing structs and
the uses are updated accordingly.
Signed-off-by: Andrew Scull
---
arch/sandbox/cpu/os.c | 21 ++---
arch/sandbox/cpu/start.c| 10 +-
arch/sandbox/cpu/u-boot-spl.lds | 6 --
arch/sandbox/cpu/u-boot.lds | 6 --
arch/sandbox/include/asm/getopt.h | 19 ---
arch/sandbox/include/asm/sections.h | 25 -
6 files changed, 27 insertions(+), 60 deletions(-)
diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c
index d83c862182..72a72029f2 100644
--- a/arch/sandbox/cpu/os.c
+++ b/arch/sandbox/cpu/os.c
@@ -424,9 +424,8 @@ static struct option *long_opts;
int os_parse_args(struct sandbox_state *state, int argc, char *argv[])
{
- struct sandbox_cmdline_option **sb_opt =
- __u_boot_sandbox_option_start();
- size_t num_options = __u_boot_sandbox_option_count();
+ struct sandbox_cmdline_option *sb_opt = SANDBOX_CMDLINE_OPT_START();
+ size_t num_options = SANDBOX_CMDLINE_OPT_COUNT();
size_t i;
int hidden_short_opt;
@@ -455,17 +454,17 @@ int os_parse_args(struct sandbox_state *state, int argc,
char *argv[])
hidden_short_opt = 0x100;
si = 0;
for (i = 0; i < num_options; ++i) {
- long_opts[i].name = sb_opt[i]->flag;
- long_opts[i].has_arg = sb_opt[i]->has_arg ?
+ long_opts[i].name = sb_opt[i].flag;
+ long_opts[i].has_arg = sb_opt[i].has_arg ?
required_argument : no_argument;
long_opts[i].flag = NULL;
- if (sb_opt[i]->flag_short) {
- short_opts[si++] = long_opts[i].val =
sb_opt[i]->flag_short;
+ if (sb_opt[i].flag_short) {
+ short_opts[si++] = long_opts[i].val =
sb_opt[i].flag_short;
if (long_opts[i].has_arg == required_argument)
short_opts[si++] = ':';
} else
- long_opts[i].val = sb_opt[i]->flag_short =
hidden_short_opt++;
+ long_opts[i].val = sb_opt[i].flag_short =
hidden_short_opt++;
}
short_opts[si] = '\0';
@@ -480,9 +479,9 @@ int os_parse_args(struct sandbox_state *state, int argc,
char *argv[])
*/
while ((c = getopt_long(argc, argv, short_opts, long_opts, NULL)) !=
-1) {
for (i = 0; i < num_options; ++i) {
- if (sb_opt[i]->flag_short == c) {
- if (sb_opt[i]->callback(state, optarg)) {
- state->parse_err = sb_opt[i]->flag;
+ if (sb_opt[i].flag_short == c) {
+ if (sb_opt[i].callback(state, optarg)) {
+ state->parse_err = sb_opt[i].flag;
return 0;
}
break;
diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c
index 13b0731ec3..5cb47e1156 100644
--- a/arch/sandbox/cpu/start.c
+++ b/arch/sandbox/cpu/start.c
@@ -58,9 +58,8 @@ static int h_compare_opt(const void *p1, const void *p2)
int sandbox_early_getopt_check(void)
{
struct sandbox_state *state = state_get_current();
- struct sandbox_cmdline_option **sb_opt =
- __u_boot_sandbox_option_start();
- size_t num_options = __u_boot_sandbox_option_count();
+ struct sandbox_cmdline_option *sb_opt = SANDBOX_CMDLINE_OPT_START();
+ size_t num_options = SANDBOX_CMDLINE_OPT_COUNT();
size_t i;
int max_arg_len, max_noarg_len;
struct sandbox_cmdline_option **sorted_opt;
@@ -84,7 +83,7 @@ int sandbox_early_getopt_check(void)
max_arg_len = 0;
for (i = 0; i < num_options; ++i)
- max_arg_len = max((int)strlen(sb_opt[i]->flag), max_arg_len);
+ max_arg_len = max((int)strlen(sb_opt[i].flag), max_arg_len);
max_noarg_len = max_arg_len + 7;
/* Sort the options */
@@ -94,7 +93,8 @@ int sandbox_early_getopt_check(void)
printf("No memory to sort options\n");
os_exit(1);
}
- memcpy(sorted_opt, sb_opt, size);
+ for (i = 0; i < num_options; ++i)
+ sorted_opt[i] = &sb_opt[i];
qsort(sorted_opt, num_options, sizeof(*sorted_opt), h_compare_opt);
for (i = 0; i < num_options; ++i) {
diff --git a/arch/sandbox/cpu/u-boot-spl.lds b/arch/sandbox/cpu/u-boot-spl.lds
index 6754f4ef6c..5c19d090cb 100644
--- a/arch/sandbox/cpu/u-boot-spl.lds
+++ b/arch/sandbox/cpu/u-boot-spl.lds
@@ -20,12 +20,6 @@ SECTIONS
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.priv_data*)))
__
[PATCH 05/11] fuzzing_engine: Add fuzzing engine uclass
This new class of device will provide fuzzing inputs from a fuzzing
engine.
Signed-off-by: Andrew Scull
---
drivers/Kconfig | 2 +
drivers/Makefile | 1 +
drivers/fuzzing_engine/Kconfig| 6 +++
drivers/fuzzing_engine/Makefile | 7 +++
.../fuzzing_engine/fuzzing_engine-uclass.c| 28 ++
include/dm/uclass-id.h| 1 +
include/fuzzing_engine.h | 51 +++
7 files changed, 96 insertions(+)
create mode 100644 drivers/fuzzing_engine/Kconfig
create mode 100644 drivers/fuzzing_engine/Makefile
create mode 100644 drivers/fuzzing_engine/fuzzing_engine-uclass.c
create mode 100644 include/fuzzing_engine.h
diff --git a/drivers/Kconfig b/drivers/Kconfig
index b26ca8cf70..54ad7f82fa 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -40,6 +40,8 @@ source "drivers/fastboot/Kconfig"
source "drivers/firmware/Kconfig"
+source "drivers/fuzzing_engine/Kconfig"
+
source "drivers/fpga/Kconfig"
source "drivers/gpio/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index 4e7cf28440..10a4a317c9 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -113,6 +113,7 @@ obj-$(CONFIG_W1) += w1/
obj-$(CONFIG_W1_EEPROM) += w1-eeprom/
obj-$(CONFIG_MACH_PIC32) += ddr/microchip/
+obj-$(CONFIG_FUZZ) += fuzzing_engine/
obj-$(CONFIG_DM_HWSPINLOCK) += hwspinlock/
obj-$(CONFIG_DM_RNG) += rng/
endif
diff --git a/drivers/fuzzing_engine/Kconfig b/drivers/fuzzing_engine/Kconfig
new file mode 100644
index 00..f405fc75e8
--- /dev/null
+++ b/drivers/fuzzing_engine/Kconfig
@@ -0,0 +1,6 @@
+config DM_FUZZING_ENGINE
+ bool "Driver support for fuzzing engine devices"
+ depends on DM
+ help
+ Enable driver model for fuzzing engine devices. This interface is
+ used to get fuzzing inputs from a fuzzing engine.
diff --git a/drivers/fuzzing_engine/Makefile b/drivers/fuzzing_engine/Makefile
new file mode 100644
index 00..acd894999c
--- /dev/null
+++ b/drivers/fuzzing_engine/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2022 Google, Inc.
+# Written by Andrew Scull
+#
+
+obj-$(CONFIG_DM_FUZZING_ENGINE) += fuzzing_engine-uclass.o
diff --git a/drivers/fuzzing_engine/fuzzing_engine-uclass.c
b/drivers/fuzzing_engine/fuzzing_engine-uclass.c
new file mode 100644
index 00..b16f1c4cfb
--- /dev/null
+++ b/drivers/fuzzing_engine/fuzzing_engine-uclass.c
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2022 Google, Inc.
+ * Written by Andrew Scull
+ */
+
+#define LOG_CATEGORY UCLASS_FUZZING_ENGINE
+
+#include
+#include
+#include
+
+int dm_fuzzing_engine_get_input(struct udevice *dev,
+ const uint8_t **data,
+ size_t *size)
+{
+ const struct dm_fuzzing_engine_ops *ops = device_get_ops(dev);
+
+ if (!ops->get_input)
+ return -ENOSYS;
+
+ return ops->get_input(dev, data, size);
+}
+
+UCLASS_DRIVER(fuzzing_engine) = {
+ .name = "fuzzing_engine",
+ .id = UCLASS_FUZZING_ENGINE,
+};
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 0e26e1d138..b9411f1d59 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -53,6 +53,7 @@ enum uclass_id {
UCLASS_ETH, /* Ethernet device */
UCLASS_ETH_PHY, /* Ethernet PHY device */
UCLASS_FIRMWARE,/* Firmware */
+ UCLASS_FUZZING_ENGINE, /* Fuzzing engine */
UCLASS_FS_FIRMWARE_LOADER, /* Generic loader */
UCLASS_GPIO,/* Bank of general-purpose I/O pins */
UCLASS_HASH,/* Hash device */
diff --git a/include/fuzzing_engine.h b/include/fuzzing_engine.h
new file mode 100644
index 00..357346e93d
--- /dev/null
+++ b/include/fuzzing_engine.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2022 Google, Inc.
+ * Written by Andrew Scull
+ */
+
+#ifndef __FUZZING_ENGINE_H
+#define __FUZZING_ENGINE_H
+
+struct udevice;
+
+/**
+ * dm_fuzzing_engine_get_input() - get an input from the fuzzing engine device
+ *
+ * The function will return a pointer to the input data and the size of the
+ * data pointed to. The pointer will remain valid until the next invocation of
+ * this function.
+ *
+ * @dev: fuzzing engine device
+ * @data: output pointer to input data
+ * @size output size of input data
+ * Return: 0 if OK, -ve on error
+ */
+int dm_fuzzing_engine_get_input(struct udevice *dev,
+ const uint8_t **data,
+ size_t *size);
+
+/**
+ * struct dm_fuzzing_engine_ops - operations for the fuzzing engine uclass
+ *
+ * This contains the functions implemented by a fuzzing engine device.
+ */
+struct dm_fuzzing_engine_ops {
+ /**
+* @get_input() - get an input
+*
[PATCH 04/11] sandbox: Add support for Address Sanitizer
Add CONFIG_ASAN to build with the Address Sanitizer. This only works
with the sandbox so the config is likewise dependent. The resulting
executable will have ASAN instrumentation, including the leak detector
that can be disabled with the ASAN_OPTIONS environment variable:
ASAN_OPTIONS=detect_leaks=0 ./u-boot
Since u-boot uses its own dlmalloc, dynamic allocations aren't
automatically instrumented, but stack variables and globals are.
Instrumentation could be added to dlmalloc to poison and unpoison memory
as it is allocated and deallocated, and to introduce redzones between
allocations. Alternatively, the sandbox may be able to play games with
the system allocator and somehow still keep the required memory
abstraction. No effort to address dynamic allocation is made by this
patch.
Signed-off-by: Andrew Scull
---
Kconfig | 7 +++
arch/sandbox/config.mk| 8
configs/sandbox_defconfig | 1 +
3 files changed, 16 insertions(+)
diff --git a/Kconfig b/Kconfig
index 9dd9ec7f6d..ae7e92611d 100644
--- a/Kconfig
+++ b/Kconfig
@@ -137,6 +137,13 @@ config CC_COVERAGE
Enabling this option will pass "--coverage" to gcc to compile
and link code instrumented for coverage analysis.
+config ASAN
+ bool "Enable AddressSanitizer"
+ depends on SANDBOX
+ help
+ Enables AddressSanitizer to discover out-of-bounds accesses,
+ use-after-free, double-free and memory leaks.
+
config CC_HAS_ASM_INLINE
def_bool $(success,echo 'void foo(void) { asm inline (""); }' | $(CC)
-x c - -c -o /dev/null)
diff --git a/arch/sandbox/config.mk b/arch/sandbox/config.mk
index c42de2ff27..d7ce66fb6c 100644
--- a/arch/sandbox/config.mk
+++ b/arch/sandbox/config.mk
@@ -15,7 +15,14 @@ PLATFORM_LIBS += $(shell $(SDL_CONFIG) --libs)
PLATFORM_CPPFLAGS += $(shell $(SDL_CONFIG) --cflags)
endif
+SANITIZERS :=
+ifdef CONFIG_ASAN
+SANITIZERS += -fsanitize=address
+endif
+KBUILD_CFLAGS += $(SANITIZERS)
+
cmd_u-boot__ = $(CC) -o $@ -Wl,-T u-boot.lds $(u-boot-init) \
+ $(SANITIZERS) \
$(LTO_FINAL_LDFLAGS) \
-Wl,--whole-archive \
$(u-boot-main) \
@@ -24,6 +31,7 @@ cmd_u-boot__ = $(CC) -o $@ -Wl,-T u-boot.lds $(u-boot-init) \
$(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map
cmd_u-boot-spl = (cd $(obj) && $(CC) -o $(SPL_BIN) -Wl,-T u-boot-spl.lds \
+ $(SANITIZERS) \
$(LTO_FINAL_LDFLAGS) \
$(patsubst $(obj)/%,%,$(u-boot-spl-init)) \
-Wl,--whole-archive \
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 7ebeb89264..4862af07cd 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -1,3 +1,4 @@
+CONFIG_ASAN=y
CONFIG_SYS_TEXT_BASE=0
CONFIG_SYS_MALLOC_LEN=0x200
CONFIG_NR_DRAM_BANKS=1
--
2.35.1.1094.g7c7d902a7c-goog
[PATCH 06/11] test: fuzz: Add framework for fuzzing
Add the basic infrastructure for declaring fuzz tests and a command to
invoke them.
Signed-off-by: Andrew Scull
---
Kconfig | 8 +
include/test/fuzz.h | 51 +++
test/Makefile| 1 +
test/fuzz/Makefile | 7
test/fuzz/cmd_fuzz.c | 82
5 files changed, 149 insertions(+)
create mode 100644 include/test/fuzz.h
create mode 100644 test/fuzz/Makefile
create mode 100644 test/fuzz/cmd_fuzz.c
diff --git a/Kconfig b/Kconfig
index ae7e92611d..ce0a69d6aa 100644
--- a/Kconfig
+++ b/Kconfig
@@ -144,6 +144,14 @@ config ASAN
Enables AddressSanitizer to discover out-of-bounds accesses,
use-after-free, double-free and memory leaks.
+config FUZZ
+ bool "Enable fuzzing"
+ depends on DM_FUZZING_ENGINE
+ select ASAN
+ help
+ Enables the fuzzing infrastructure to generate fuzzing data and run
+ fuzz tests.
+
config CC_HAS_ASM_INLINE
def_bool $(success,echo 'void foo(void) { asm inline (""); }' | $(CC)
-x c - -c -o /dev/null)
diff --git a/include/test/fuzz.h b/include/test/fuzz.h
new file mode 100644
index 00..d4c57540eb
--- /dev/null
+++ b/include/test/fuzz.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2022 Google, Inc.
+ * Written by Andrew Scull
+ */
+
+#ifndef __TEST_FUZZ_H
+#define __TEST_FUZZ_H
+
+#include
+#include
+
+/**
+ * struct fuzz_test - Information about a fuzz test
+ *
+ * @name: Name of fuzz test
+ * @func: Function to call to perform fuzz test on an input
+ * @flags: Flags indicate pre-conditions for fuzz test
+ */
+struct fuzz_test {
+ const char *name;
+ int (*func)(const uint8_t * data, size_t size);
+ int flags;
+};
+
+/**
+ * FUZZ_TEST() - register a fuzz test
+ *
+ * The fuzz test function must return 0 as other values are reserved for future
+ * use.
+ *
+ * @_name: the name of the fuzz test function
+ * @_flags:an integer field that can be evaluated by the fuzzer
+ * implementation
+ */
+#define FUZZ_TEST(_name, _flags) \
+ ll_entry_declare(struct fuzz_test, _name, fuzz_tests) = { \
+ .name = #_name, \
+ .func = _name, \
+ .flags = _flags,\
+ }
+
+/** Get the start of the list of fuzz tests */
+#define FUZZ_TEST_START() \
+ ll_entry_start(struct fuzz_test, fuzz_tests)
+
+/** Get the number of elements in the list of fuzz tests */
+#define FUZZ_TEST_COUNT() \
+ ll_entry_count(struct fuzz_test, fuzz_tests)
+
+#endif /* __TEST_FUZZ_H */
diff --git a/test/Makefile b/test/Makefile
index b3b2902e2e..bb2b0b5c73 100644
--- a/test/Makefile
+++ b/test/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_$(SPL_)CMDLINE) += cmd_ut.o
obj-$(CONFIG_$(SPL_)CMDLINE) += command_ut.o
obj-$(CONFIG_$(SPL_)UT_COMPRESSION) += compression.o
obj-y += dm/
+obj-$(CONFIG_FUZZ) += fuzz/
obj-$(CONFIG_$(SPL_)CMDLINE) += print_ut.o
obj-$(CONFIG_$(SPL_)CMDLINE) += str_ut.o
obj-$(CONFIG_UT_TIME) += time_ut.o
diff --git a/test/fuzz/Makefile b/test/fuzz/Makefile
new file mode 100644
index 00..03b497
--- /dev/null
+++ b/test/fuzz/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2022 Google, Inc.
+# Written by Andrew Scull
+#
+
+obj-$(CONFIG_$(SPL_)CMDLINE) += cmd_fuzz.o
diff --git a/test/fuzz/cmd_fuzz.c b/test/fuzz/cmd_fuzz.c
new file mode 100644
index 00..0cc01dc199
--- /dev/null
+++ b/test/fuzz/cmd_fuzz.c
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2022 Google, Inc.
+ * Written by Andrew Scull
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+static struct fuzz_test *find_fuzz_test(const char *name)
+{
+ struct fuzz_test *fuzzer = FUZZ_TEST_START();
+ size_t count = FUZZ_TEST_COUNT();
+ size_t i;
+
+ for (i = 0; i < count; ++i) {
+ if (strcmp(name, fuzzer->name) == 0)
+ return fuzzer;
+ ++fuzzer;
+ }
+
+ return NULL;
+}
+
+static struct udevice *find_fuzzing_engine(void)
+{
+ struct udevice *dev;
+
+ if (uclass_first_device(UCLASS_FUZZING_ENGINE, &dev))
+ return NULL;
+
+ return dev;
+}
+
+static int do_fuzz(struct cmd_tbl *cmdtp, int flag, int argc, char *const
argv[])
+{
+ struct fuzz_test *fuzzer;
+ struct udevice *dev;
+
+ if (argc != 2)
+ return CMD_RET_USAGE;
+
+ fuzzer = find_fuzz_test(argv[1]);
+ if (!fuzzer) {
+ printf("Could not find fuzzer: %s\n", argv[1]);
+ return 1;
+ }
+
+ dev = find_fuzzing_engine();
+ if (!dev) {
+ puts("No fuzzing engine available\n");
+ return 1;
+ }
+
+ while (1) {
+
[PATCH 08/11] sandbox: Add libfuzzer integration
Add an implementation of LLVMFuzzerTestOneInput() that starts the
sandbox on a secondary thread and exposes a function to synchronize the
generation of fuzzing inputs with their consumption by the sandbox.
Signed-off-by: Andrew Scull
---
arch/sandbox/config.mk| 3 +
arch/sandbox/cpu/os.c | 70 +++
arch/sandbox/include/asm/fuzzing_engine.h | 25
3 files changed, 98 insertions(+)
create mode 100644 arch/sandbox/include/asm/fuzzing_engine.h
diff --git a/arch/sandbox/config.mk b/arch/sandbox/config.mk
index d7ce66fb6c..5fbe1f50e3 100644
--- a/arch/sandbox/config.mk
+++ b/arch/sandbox/config.mk
@@ -19,6 +19,9 @@ SANITIZERS :=
ifdef CONFIG_ASAN
SANITIZERS += -fsanitize=address
endif
+ifdef CONFIG_FUZZ
+SANITIZERS += -fsanitize=fuzzer
+endif
KBUILD_CFLAGS += $(SANITIZERS)
cmd_u-boot__ = $(CC) -o $@ -Wl,-T u-boot.lds $(u-boot-init) \
diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c
index 5ea4135741..cd45d7b6b6 100644
--- a/arch/sandbox/cpu/os.c
+++ b/arch/sandbox/cpu/os.c
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -26,6 +27,7 @@
#include
#include
+#include
#include
#include
#include
@@ -1002,7 +1004,75 @@ void os_relaunch(char *argv[])
os_exit(1);
}
+
+#ifdef CONFIG_FUZZ
+static void *fuzzer_thread(void * ptr)
+{
+ char cmd[64];
+ char *argv[5] = {"./u-boot", "-T", "-c", cmd, NULL};
+ const char *fuzz_test;
+
+ /* Find which test to run from an environment variable. */
+ fuzz_test = getenv("UBOOT_SB_FUZZ_TEST");
+ if (!fuzz_test)
+ os_abort();
+
+ snprintf(cmd, sizeof(cmd), "fuzz %s", fuzz_test);
+
+ sandbox_main(4, argv);
+ os_abort();
+ return NULL;
+}
+
+static bool fuzzer_initialized = false;
+static pthread_mutex_t fuzzer_mutex = PTHREAD_MUTEX_INITIALIZER;
+static pthread_cond_t fuzzer_cond = PTHREAD_COND_INITIALIZER;
+static const uint8_t *fuzzer_data;
+static size_t fuzzer_size;
+
+int sandbox_fuzzing_engine_get_input(const uint8_t **data, size_t *size)
+{
+ if (!fuzzer_initialized)
+ return -ENOSYS;
+
+ /* Tell the main thread we need new inputs then wait for them. */
+ pthread_mutex_lock(&fuzzer_mutex);
+ pthread_cond_signal(&fuzzer_cond);
+ pthread_cond_wait(&fuzzer_cond, &fuzzer_mutex);
+ *data = fuzzer_data;
+ *size = fuzzer_size;
+ pthread_mutex_unlock(&fuzzer_mutex);
+ return 0;
+}
+
+int LLVMFuzzerTestOneInput(const uint8_t *data, size_t size)
+{
+ static pthread_t tid;
+
+ pthread_mutex_lock(&fuzzer_mutex);
+
+ /* Initialize the sandbox on another thread. */
+ if (!fuzzer_initialized) {
+ fuzzer_initialized = true;
+ if (pthread_create(&tid, NULL, fuzzer_thread, NULL))
+ os_abort();
+ pthread_cond_wait(&fuzzer_cond, &fuzzer_mutex);
+ }
+
+ /* Hand over the input. */
+ fuzzer_data = data;
+ fuzzer_size = size;
+ pthread_cond_signal(&fuzzer_cond);
+
+ /* Wait for the inputs to be finished with. */
+ pthread_cond_wait(&fuzzer_cond, &fuzzer_mutex);
+ pthread_mutex_unlock(&fuzzer_mutex);
+
+ return 0;
+}
+#else
int main(int argc, char *argv[])
{
return sandbox_main(argc, argv);
}
+#endif
diff --git a/arch/sandbox/include/asm/fuzzing_engine.h
b/arch/sandbox/include/asm/fuzzing_engine.h
new file mode 100644
index 00..cf6396363b
--- /dev/null
+++ b/arch/sandbox/include/asm/fuzzing_engine.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2022 Google, Inc.
+ * Written by Andrew Scull
+ */
+
+#ifndef __ASM_FUZZING_ENGINE_H
+#define __ASM_FUZZING_ENGINE_H
+
+/** Function to get fuzzing engine input data. */
+/**
+ * sandbox_fuzzing_engine_get_input() - get an input from the sandbox fuzzing
+ * engine
+ *
+ * The function will return a pointer to the input data and the size of the
+ * data pointed to. The pointer will remain valid until the next invocation of
+ * this function.
+ *
+ * @data: output pointer to input data
+ * @size output size of input data
+ * Return: 0 if OK, -ve on error
+ */
+int sandbox_fuzzing_engine_get_input(const uint8_t **data, size_t *size);
+
+#endif /* __ASM_FUZZING_ENGINE_H */
--
2.35.1.1094.g7c7d902a7c-goog
[PATCH 03/11] linker_lists: Rename sections to remove . prefix
Rename the sections used to implement linker lists so they begin with
'__u_boot_list' rather than '.u_boot_list'. The double underscore at the
start is still distinct from the single underscore used by the symbol
names.
Having a '.' in the section names conflicts with clang's ASAN
instrumentation which tries to add redzones between the linker list
elements, causing expected accesses to fail. However, clang doesn't try
to add redzones to user sections, which are names with all alphanumeric
and underscore characters.
Signed-off-by: Andrew Scull
---
arch/arc/cpu/u-boot.lds | 4 ++--
arch/arm/config.mk| 4 ++--
arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds | 4 ++--
arch/arm/cpu/armv7/sunxi/u-boot-spl.lds | 4 ++--
arch/arm/cpu/armv8/u-boot-spl.lds | 4 ++--
arch/arm/cpu/armv8/u-boot.lds | 4 ++--
arch/arm/cpu/u-boot-spl.lds | 4 ++--
arch/arm/cpu/u-boot.lds | 6 ++---
arch/arm/mach-at91/arm926ejs/u-boot-spl.lds | 2 +-
arch/arm/mach-at91/armv7/u-boot-spl.lds | 2 +-
arch/arm/mach-omap2/u-boot-spl.lds| 4 ++--
arch/arm/mach-orion5x/u-boot-spl.lds | 4 ++--
arch/arm/mach-rockchip/u-boot-tpl-v8.lds | 4 ++--
arch/arm/mach-zynq/u-boot-spl.lds | 4 ++--
arch/arm/mach-zynq/u-boot.lds | 4 ++--
arch/m68k/cpu/u-boot.lds | 4 ++--
arch/microblaze/cpu/u-boot-spl.lds| 4 ++--
arch/microblaze/cpu/u-boot.lds| 4 ++--
arch/mips/config.mk | 2 +-
arch/mips/cpu/u-boot-spl.lds | 4 ++--
arch/mips/cpu/u-boot.lds | 4 ++--
arch/nds32/cpu/n1213/u-boot.lds | 4 ++--
arch/nios2/cpu/u-boot.lds | 4 ++--
arch/powerpc/cpu/mpc83xx/u-boot.lds | 4 ++--
arch/powerpc/cpu/mpc85xx/u-boot-nand.lds | 4 ++--
arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds | 4 ++--
arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 4 ++--
arch/powerpc/cpu/mpc85xx/u-boot.lds | 4 ++--
arch/riscv/cpu/u-boot-spl.lds | 4 ++--
arch/riscv/cpu/u-boot.lds | 4 ++--
arch/sandbox/config.mk| 4 ++--
arch/sandbox/cpu/u-boot-spl.lds | 4 ++--
arch/sandbox/cpu/u-boot.lds | 4 ++--
arch/sh/cpu/u-boot.lds| 4 ++--
arch/x86/cpu/u-boot-64.lds| 6 ++---
arch/x86/cpu/u-boot-spl.lds | 6 ++---
arch/x86/cpu/u-boot.lds | 6 ++---
arch/x86/lib/elf_ia32_efi.lds | 4 ++--
arch/x86/lib/elf_x86_64_efi.lds | 4 ++--
arch/xtensa/cpu/u-boot.lds| 2 +-
arch/xtensa/include/asm/ldscript.h| 4 ++--
board/compulab/cm_t335/u-boot.lds | 4 ++--
board/cssi/MCR3000/u-boot.lds | 4 ++--
.../davinci/da8xxevm/u-boot-spl-da850evm.lds | 2 +-
board/qualcomm/dragonboard820c/u-boot.lds | 4 ++--
board/samsung/common/exynos-uboot-spl.lds | 4 ++--
board/synopsys/iot_devkit/u-boot.lds | 4 ++--
board/ti/am335x/u-boot.lds| 4 ++--
board/vscom/baltos/u-boot.lds | 4 ++--
doc/api/linker_lists.rst | 22 +--
doc/develop/commands.rst | 4 ++--
doc/develop/driver-model/of-plat.rst | 4 ++--
include/linker_lists.h| 18 +++
53 files changed, 121 insertions(+), 121 deletions(-)
diff --git a/arch/arc/cpu/u-boot.lds b/arch/arc/cpu/u-boot.lds
index e12145c768..9f2973da65 100644
--- a/arch/arc/cpu/u-boot.lds
+++ b/arch/arc/cpu/u-boot.lds
@@ -39,8 +39,8 @@ SECTIONS
}
. = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
+ __u_boot_list : {
+ KEEP(*(SORT(__u_boot_list*)));
}
. = ALIGN(4);
diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index b107b1af27..b3548ce243 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -141,11 +141,11 @@ endif
# limit ourselves to the sections we want in the .bin.
ifdef CONFIG_ARM64
OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .data \
- -j .u_boot_list -j .rela.dyn -j .got -j .got.plt \
+ -j __u_boot_list -j .rela.dyn -j .got -j .got.plt \
-j .binman_sym_table -j .text_rest
else
OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .hash \
- -j .data -j .got -j .got.plt -j .u_boot_list -j .rel.dyn \
+ -j .data -j .got -j .got.plt -j __u_boot_list -j .rel.dyn \
-j .binman_sym_table -j .text_rest
endif
diff --git a/arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds
b/arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds
index 9a000ac5d3..c108736811 100644
--
[PATCH 09/11] sandbox: Implement fuzzing engine driver
Add a fuzzing engine driver for the sandbox to take inputs from
libfuzzer and expose them to the fuzz tests.
Signed-off-by: Andrew Scull
---
arch/Kconfig | 2 ++
arch/sandbox/dts/test.dts | 4 +++
drivers/fuzzing_engine/Kconfig| 11 ++
drivers/fuzzing_engine/Makefile | 1 +
.../fuzzing_engine/sandbox_fuzzing_engine.c | 35 +++
5 files changed, 53 insertions(+)
create mode 100644 drivers/fuzzing_engine/sandbox_fuzzing_engine.c
diff --git a/arch/Kconfig b/arch/Kconfig
index e6191446a3..6320a98db6 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -135,6 +135,7 @@ config SANDBOX
select BZIP2
select CMD_POWEROFF
select DM
+ select DM_FUZZING_ENGINE
select DM_GPIO
select DM_I2C
select DM_KEYBOARD
@@ -170,6 +171,7 @@ config SANDBOX
imply CRC32_VERIFY
imply FAT_WRITE
imply FIRMWARE
+ imply FUZZING_ENGINE_SANDBOX
imply HASH_VERIFY
imply LZMA
imply TEE
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 48ca3e1e47..848329fda5 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -71,6 +71,10 @@
};
};
+ fuzzing-engine {
+ compatible = "sandbox,sandbox-fuzzing-engine";
+ };
+
reboot-mode0 {
compatible = "reboot-mode-gpio";
gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1
GPIO_ACTIVE_HIGH>;
diff --git a/drivers/fuzzing_engine/Kconfig b/drivers/fuzzing_engine/Kconfig
index f405fc75e8..6311385222 100644
--- a/drivers/fuzzing_engine/Kconfig
+++ b/drivers/fuzzing_engine/Kconfig
@@ -4,3 +4,14 @@ config DM_FUZZING_ENGINE
help
Enable driver model for fuzzing engine devices. This interface is
used to get fuzzing inputs from a fuzzing engine.
+
+if DM_FUZZING_ENGINE
+
+config FUZZING_ENGINE_SANDBOX
+ bool "Sanbox fuzzing engine"
+ depends on SANDBOX
+ default y
+ help
+ Enable fuzzing engine for sandbox.
+
+endif
diff --git a/drivers/fuzzing_engine/Makefile b/drivers/fuzzing_engine/Makefile
index acd894999c..073743ba94 100644
--- a/drivers/fuzzing_engine/Makefile
+++ b/drivers/fuzzing_engine/Makefile
@@ -5,3 +5,4 @@
#
obj-$(CONFIG_DM_FUZZING_ENGINE) += fuzzing_engine-uclass.o
+obj-$(CONFIG_FUZZING_ENGINE_SANDBOX) += sandbox_fuzzing_engine.o
diff --git a/drivers/fuzzing_engine/sandbox_fuzzing_engine.c
b/drivers/fuzzing_engine/sandbox_fuzzing_engine.c
new file mode 100644
index 00..4d187deaa4
--- /dev/null
+++ b/drivers/fuzzing_engine/sandbox_fuzzing_engine.c
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2022 Google, Inc.
+ * Written by Andrew Scull
+ */
+
+#include
+#include
+#include
+#include
+
+static int get_input(struct udevice *dev,
+const uint8_t **data,
+size_t *size)
+{
+ return sandbox_fuzzing_engine_get_input(data, size);
+}
+
+static const struct dm_fuzzing_engine_ops sandbox_fuzzing_engine_ops = {
+ .get_input = get_input,
+};
+
+static const struct udevice_id sandbox_fuzzing_engine_match[] = {
+ {
+ .compatible = "sandbox,sandbox-fuzzing-engine",
+ },
+ {},
+};
+
+U_BOOT_DRIVER(sandbox_fuzzing_engine) = {
+ .name = "sandbox-fuzzing-engine",
+ .id = UCLASS_FUZZING_ENGINE,
+ .of_match = sandbox_fuzzing_engine_match,
+ .ops = &sandbox_fuzzing_engine_ops,
+};
--
2.35.1.1094.g7c7d902a7c-goog
[PATCH 07/11] sandbox: Decouple program entry from sandbox init
Move the program's entry point to os.c, in preparation for a separate
fuzzing entry point to be added.
Signed-off-by: Andrew Scull
---
arch/sandbox/cpu/os.c | 6 ++
arch/sandbox/cpu/start.c| 2 +-
arch/sandbox/include/asm/main.h | 18 ++
3 files changed, 25 insertions(+), 1 deletion(-)
create mode 100644 arch/sandbox/include/asm/main.h
diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c
index 72a72029f2..5ea4135741 100644
--- a/arch/sandbox/cpu/os.c
+++ b/arch/sandbox/cpu/os.c
@@ -27,6 +27,7 @@
#include
#include
+#include
#include
#include
#include
@@ -1000,3 +1001,8 @@ void os_relaunch(char *argv[])
execv(argv[0], argv);
os_exit(1);
}
+
+int main(int argc, char *argv[])
+{
+ return sandbox_main(argc, argv);
+}
diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c
index 5cb47e1156..ba67f4fbd7 100644
--- a/arch/sandbox/cpu/start.c
+++ b/arch/sandbox/cpu/start.c
@@ -451,7 +451,7 @@ void sandbox_reset(void)
os_relaunch(os_argv);
}
-int main(int argc, char *argv[])
+int sandbox_main(int argc, char *argv[])
{
struct sandbox_state *state;
void * text_base;
diff --git a/arch/sandbox/include/asm/main.h b/arch/sandbox/include/asm/main.h
new file mode 100644
index 00..7a2f0d3a8d
--- /dev/null
+++ b/arch/sandbox/include/asm/main.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2022 Google, Inc.
+ * Written by Andrew Scull
+ */
+
+#ifndef __ASM_SANDBOX_MAIN_H
+#define __ASM_SANDBOX_MAIN_H
+
+/**
+ * sandbox_main() - main entrypoint for sandbox
+ *
+ * @argc: the number of arguments passed to the program
+ * @argv: array of argc+1 pointers, of which the last one is null
+ */
+int sandbox_main(int argc, char *argv[]);
+
+#endif /* __ASM_SANDBOX_MAIN_H */
--
2.35.1.1094.g7c7d902a7c-goog
Re: [PATCH] squashfs: Fix compilation on big endian systems
On Thursday 07 April 2022 09:54:21 Miquel Raynal wrote: > Hi Pali, > > p...@kernel.org wrote on Wed, 6 Apr 2022 23:31:53 +0200: > > Would you mind explaining a little bit how this change fixes it? It > does not look straightforward to me. Yes! I though that it is straightforward this change... byteorder/little_endian.h defines cpu_to_le* macros for Little Endian systems and byteorder/big_endian.h for Big Endian systems. File asm/byteorder.h is then ARCH-specific and implements macros for the current architecture (by including the correct header file). So currently if you try to compile squashfs for big endian systems you get compile error: In file included from ./arch/powerpc/include/asm/byteorder.h:82, from include/linux/unaligned/access_ok.h:4, from ./arch/powerpc/include/asm/unaligned.h:9, from fs/squashfs/sqfs_filesystem.h:11, from fs/squashfs/sqfs_dir.c:16: include/linux/byteorder/big_endian.h:34: warning: "__cpu_to_le32" redefined #define __cpu_to_le32(x) ((__force __le32)__swab32((x))) In file included from fs/squashfs/sqfs_dir.c:10: include/linux/byteorder/little_endian.h:34: note: this is the location of the previous definition #define __cpu_to_le32(x) ((__force __le32)(__u32)(x)) Or: In file included from fs/squashfs/sqfs.c:14: include/linux/byteorder/little_endian.h:89:21: error: redefinition of ‘__be16_to_cpup’ static inline __u16 __be16_to_cpup(const __be16 *p) ^~ In file included from ./arch/powerpc/include/asm/byteorder.h:82, from include/linux/unaligned/access_ok.h:4, from ./arch/powerpc/include/asm/unaligned.h:9, from fs/squashfs/sqfs.c:10: include/linux/byteorder/big_endian.h:89:21: note: previous definition of ‘__be16_to_cpup’ was here static inline __u16 __be16_to_cpup(const __be16 *p) ^~ As some header files include correct asm/byteorder.h file and this squashfs includes additional little_endian.h. > > Signed-off-by: Pali Rohár > > --- > > fs/squashfs/sqfs.c | 3 +-- > > fs/squashfs/sqfs_dir.c | 3 +-- > > 2 files changed, 2 insertions(+), 4 deletions(-) > > > > diff --git a/fs/squashfs/sqfs.c b/fs/squashfs/sqfs.c > > index 5d9c52af80ba..41cb811c1b32 100644 > > --- a/fs/squashfs/sqfs.c > > +++ b/fs/squashfs/sqfs.c > > @@ -11,8 +11,7 @@ > > #include > > #include > > #include > > -#include > > -#include > > +#include > > #include > > #include > > #include > > diff --git a/fs/squashfs/sqfs_dir.c b/fs/squashfs/sqfs_dir.c > > index a265b98fe685..ed83c90682ff 100644 > > --- a/fs/squashfs/sqfs_dir.c > > +++ b/fs/squashfs/sqfs_dir.c > > @@ -7,8 +7,7 @@ > > > > #include > > #include > > -#include > > -#include > > +#include > > #include > > #include > > #include > > Cheers, > Miquèl
[PATCH 11/11] RFC: Hack dlmalloc to poison memory
This is a hugely ugly hack to poison and unpoison memory allocated by
dlmalloc. It wraps every access dlmalloc makes to the metadata breifly
allow it access, taking care not to then poison the parts of the record
which overlap.
The result is very small redzones between the allocations, which has
limted value but has able to spot immediate buffer overruns.
The instrumentation is extremely intrusive and would be benefited by
more intrusions to increase redzone sizes etc.
Signed-off-by: Andrew Scull
---
common/dlmalloc.c | 284 --
include/compiler.h| 1 +
include/linux/types.h | 1 +
3 files changed, 245 insertions(+), 41 deletions(-)
diff --git a/common/dlmalloc.c b/common/dlmalloc.c
index 11729e8c85..614f004579 100644
--- a/common/dlmalloc.c
+++ b/common/dlmalloc.c
@@ -8,6 +8,8 @@
* as file malloc-2.6.6.c.
*/
+#define DEBUG
+
#include
#include
#include
@@ -16,6 +18,8 @@
#define DEBUG
#endif
+#include
+
#include
#include
@@ -31,6 +35,17 @@ void malloc_stats();
DECLARE_GLOBAL_DATA_PTR;
+/*
+#undef ASAN_POISON_MEMORY_REGION
+#define ASAN_POISON_MEMORY_REGION(p, s) do { \
+if ((uintptr_t)p == 0x150200c0) { \
+printf("size %lx\n", s); \
+*(int*)NULL = 9; \
+} \
+__asan_poison_memory_region(p, s); \
+} while (0)
+*/
+
/*
Emulation of sbrk for WIN32
All code within the ifdef WIN32 is untested by me.
@@ -409,12 +424,26 @@ nextchunk->
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
/* Ptr to next physical malloc_chunk. */
-#define next_chunk(p) ((mchunkptr)( ((char*)(p)) + ((p)->size & ~PREV_INUSE) ))
+#define _next_chunk(p) ((mchunkptr)( ((char*)(p)) + ((p)->size & ~PREV_INUSE)
))
+#define next_chunk(p) ({ \
+mchunkptr _ptr = (p); \
+ASAN_UNPOISON_MEMORY_REGION(((char*)_ptr) + SIZE_SZ, SIZE_SZ); \
+mchunkptr _ret = _next_chunk(_ptr); \
+ASAN_POISON_MEMORY_REGION(((char*)_ptr) + SIZE_SZ, SIZE_SZ); \
+_ret; \
+})
/* Ptr to previous physical malloc_chunk */
-#define prev_chunk(p)\
+#define _prev_chunk(p)\
((mchunkptr)( ((char*)(p)) - ((p)->prev_size) ))
+#define prev_chunk(p) ({ \
+mchunkptr _ptr = (p); \
+ASAN_UNPOISON_MEMORY_REGION(_ptr, SIZE_SZ); \
+mchunkptr _ret = _prev_chunk(_ptr); \
+ASAN_POISON_MEMORY_REGION(_ptr, SIZE_SZ); \
+_ret; \
+})
/* Treat space at ptr + offset as a chunk */
@@ -430,35 +459,102 @@ nextchunk->
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
/* extract p's inuse bit */
-#define inuse(p)\
+#define _inuse(p)\
mchunkptr)(((char*)(p))+((p)->size & ~PREV_INUSE)))->size) & PREV_INUSE)
+#define inuse(p) ({ \
+mchunkptr _p = (p); \
+ASAN_UNPOISON_MEMORY_REGION(((char*)_p) + SIZE_SZ, SIZE_SZ); \
+mchunkptr _ptr = ((mchunkptr)(((char*)_p)+(_p->size & ~PREV_INUSE))); \
+ASAN_UNPOISON_MEMORY_REGION(((char*)_ptr) + SIZE_SZ, SIZE_SZ); \
+INTERNAL_SIZE_T _ret = _inuse(_p); \
+ASAN_POISON_MEMORY_REGION(((char*)_ptr) + SIZE_SZ, SIZE_SZ); \
+ASAN_POISON_MEMORY_REGION(((char*)_p) + SIZE_SZ, SIZE_SZ); \
+_ret; \
+})
/* extract inuse bit of previous chunk */
-#define prev_inuse(p) ((p)->size & PREV_INUSE)
+#define _prev_inuse(p) ((p)->size & PREV_INUSE)
+#define prev_inuse(p) ({ \
+mchunkptr _ptr = (p); \
+ASAN_UNPOISON_MEMORY_REGION(((char*)_ptr) + SIZE_SZ, SIZE_SZ); \
+INTERNAL_SIZE_T _ret = _prev_inuse(_ptr); \
+ASAN_POISON_MEMORY_REGION(((char*)_ptr) + SIZE_SZ, SIZE_SZ); \
+_ret; \
+})
/* check for mmap()'ed chunk */
-#define chunk_is_mmapped(p) ((p)->size & IS_MMAPPED)
+#define _chunk_is_mmapped(p) ((p)->size & IS_MMAPPED)
+#define chunk_is_mmapped(p) ({ \
+mchunkptr _ptr = (p); \
+ASAN_UNPOISON_MEMORY_REGION(((char*)_ptr) + SIZE_SZ, SIZE_SZ); \
+INTERNAL_SIZE_T _ret = _chunk_is_mmapped(_ptr); \
+ASAN_POISON_MEMORY_REGION(((char*)_ptr) + SIZE_SZ, SIZE_SZ); \
+_ret; \
+})
/* set/clear chunk as in use without otherwise disturbing */
-#define set_inuse(p)\
+#define _set_inuse(p)\
((mchunkptr)(((char*)(p)) + ((p)->size & ~PREV_INUSE)))->size |= PREV_INUSE
-
-#define clear_inuse(p)\
+#define set_inuse(p, s) ({ \
+mchunkptr _p = (p); \
+ASAN_UNPOISON_MEMORY_REGION(((char*)_p) + SIZE_SZ, SIZE_SZ); \
+mchunkptr _ptr = ((mchunkptr)(((char*)_p)+(_p->size & ~PREV_INUSE))); \
+ASAN_UNPOISON_MEMORY_REGION(((char*)_ptr) + SIZE_SZ, SIZE_SZ); \
+_set_inuse(_p, (s)); \
+ASAN_POISON_MEMORY_REGION(((char*)_ptr) + SIZE_SZ, SIZE_SZ); \
+ASAN_POISON_MEMORY_REGION(((char*)_p) + SIZE_SZ, SIZE_SZ); \
+})
+
+#define _clear_inuse(p)\
((mchunkptr)(((char*)(p)) + ((p)->size & ~PREV_INUSE)))->size &= ~(PREV_INUSE)
+#define clear_inuse(p, s) ({ \
+__typeof__(p) _p = (p); \
+ASAN_UNPOISON_
Re: [PATCH] squashfs: Fix compilation on big endian systems
Hi Pali, p...@kernel.org wrote on Thu, 7 Apr 2022 11:41:59 +0200: > On Thursday 07 April 2022 09:54:21 Miquel Raynal wrote: > > Hi Pali, > > > > p...@kernel.org wrote on Wed, 6 Apr 2022 23:31:53 +0200: > > > > Would you mind explaining a little bit how this change fixes it? It > > does not look straightforward to me. > > Yes! I though that it is straightforward this change... > byteorder/little_endian.h defines cpu_to_le* macros for Little Endian > systems and byteorder/big_endian.h for Big Endian systems. > > File asm/byteorder.h is then ARCH-specific and implements macros for the > current architecture (by including the correct header file). > > So currently if you try to compile squashfs for big endian systems you > get compile error: > > In file included from ./arch/powerpc/include/asm/byteorder.h:82, >from include/linux/unaligned/access_ok.h:4, >from ./arch/powerpc/include/asm/unaligned.h:9, >from fs/squashfs/sqfs_filesystem.h:11, >from fs/squashfs/sqfs_dir.c:16: > include/linux/byteorder/big_endian.h:34: warning: "__cpu_to_le32" redefined >#define __cpu_to_le32(x) ((__force __le32)__swab32((x))) > > In file included from fs/squashfs/sqfs_dir.c:10: > include/linux/byteorder/little_endian.h:34: note: this is the location of > the previous definition >#define __cpu_to_le32(x) ((__force __le32)(__u32)(x)) > > Or: > > In file included from fs/squashfs/sqfs.c:14: > include/linux/byteorder/little_endian.h:89:21: error: redefinition of > ‘__be16_to_cpup’ >static inline __u16 __be16_to_cpup(const __be16 *p) >^~ > In file included from ./arch/powerpc/include/asm/byteorder.h:82, >from include/linux/unaligned/access_ok.h:4, >from ./arch/powerpc/include/asm/unaligned.h:9, >from fs/squashfs/sqfs.c:10: > include/linux/byteorder/big_endian.h:89:21: note: previous definition of > ‘__be16_to_cpup’ was here >static inline __u16 __be16_to_cpup(const __be16 *p) >^~ > > As some header files include correct asm/byteorder.h file and this > squashfs includes additional little_endian.h. Great, thanks for the thorough explanation. Based on what you said, wouldn't it be cleaner to just get rid of the little_endian.h include rather than also use the ARCH specific byteorder.h header? > > > > Signed-off-by: Pali Rohár > > > --- > > > fs/squashfs/sqfs.c | 3 +-- > > > fs/squashfs/sqfs_dir.c | 3 +-- > > > 2 files changed, 2 insertions(+), 4 deletions(-) > > > > > > diff --git a/fs/squashfs/sqfs.c b/fs/squashfs/sqfs.c > > > index 5d9c52af80ba..41cb811c1b32 100644 > > > --- a/fs/squashfs/sqfs.c > > > +++ b/fs/squashfs/sqfs.c > > > @@ -11,8 +11,7 @@ > > > #include > > > #include > > > #include > > > -#include > > > -#include > > > +#include > > > #include > > > #include > > > #include > > > diff --git a/fs/squashfs/sqfs_dir.c b/fs/squashfs/sqfs_dir.c > > > index a265b98fe685..ed83c90682ff 100644 > > > --- a/fs/squashfs/sqfs_dir.c > > > +++ b/fs/squashfs/sqfs_dir.c > > > @@ -7,8 +7,7 @@ > > > > > > #include > > > #include > > > -#include > > > -#include > > > +#include > > > #include > > > #include > > > #include > > > > Cheers, > > Miquèl Thanks, Miquèl
Re: [PATCH] squashfs: Fix compilation on big endian systems
On Thursday 07 April 2022 11:54:55 Miquel Raynal wrote: > Hi Pali, > > p...@kernel.org wrote on Thu, 7 Apr 2022 11:41:59 +0200: > > > On Thursday 07 April 2022 09:54:21 Miquel Raynal wrote: > > > Hi Pali, > > > > > > p...@kernel.org wrote on Wed, 6 Apr 2022 23:31:53 +0200: > > > > > > Would you mind explaining a little bit how this change fixes it? It > > > does not look straightforward to me. > > > > Yes! I though that it is straightforward this change... > > byteorder/little_endian.h defines cpu_to_le* macros for Little Endian > > systems and byteorder/big_endian.h for Big Endian systems. > > > > File asm/byteorder.h is then ARCH-specific and implements macros for the > > current architecture (by including the correct header file). > > > > So currently if you try to compile squashfs for big endian systems you > > get compile error: > > > > In file included from ./arch/powerpc/include/asm/byteorder.h:82, > >from include/linux/unaligned/access_ok.h:4, > >from ./arch/powerpc/include/asm/unaligned.h:9, > >from fs/squashfs/sqfs_filesystem.h:11, > >from fs/squashfs/sqfs_dir.c:16: > > include/linux/byteorder/big_endian.h:34: warning: "__cpu_to_le32" > > redefined > >#define __cpu_to_le32(x) ((__force __le32)__swab32((x))) > > > > In file included from fs/squashfs/sqfs_dir.c:10: > > include/linux/byteorder/little_endian.h:34: note: this is the location of > > the previous definition > >#define __cpu_to_le32(x) ((__force __le32)(__u32)(x)) > > > > Or: > > > > In file included from fs/squashfs/sqfs.c:14: > > include/linux/byteorder/little_endian.h:89:21: error: redefinition of > > ‘__be16_to_cpup’ > >static inline __u16 __be16_to_cpup(const __be16 *p) > >^~ > > In file included from ./arch/powerpc/include/asm/byteorder.h:82, > >from include/linux/unaligned/access_ok.h:4, > >from ./arch/powerpc/include/asm/unaligned.h:9, > >from fs/squashfs/sqfs.c:10: > > include/linux/byteorder/big_endian.h:89:21: note: previous definition of > > ‘__be16_to_cpup’ was here > >static inline __u16 __be16_to_cpup(const __be16 *p) > >^~ > > > > As some header files include correct asm/byteorder.h file and this > > squashfs includes additional little_endian.h. > > Great, thanks for the thorough explanation. Based on what you said, > wouldn't it be cleaner to just get rid of the little_endian.h include > rather than also use the ARCH specific byteorder.h header? I think that this is not possible. squashfs code uses le16_to_cpu() macro and its correct definition is provided only by arch specific asm/byteorder.h. > > > > > > Signed-off-by: Pali Rohár > > > > --- > > > > fs/squashfs/sqfs.c | 3 +-- > > > > fs/squashfs/sqfs_dir.c | 3 +-- > > > > 2 files changed, 2 insertions(+), 4 deletions(-) > > > > > > > > diff --git a/fs/squashfs/sqfs.c b/fs/squashfs/sqfs.c > > > > index 5d9c52af80ba..41cb811c1b32 100644 > > > > --- a/fs/squashfs/sqfs.c > > > > +++ b/fs/squashfs/sqfs.c > > > > @@ -11,8 +11,7 @@ > > > > #include > > > > #include > > > > #include > > > > -#include > > > > -#include > > > > +#include > > > > #include > > > > #include > > > > #include > > > > diff --git a/fs/squashfs/sqfs_dir.c b/fs/squashfs/sqfs_dir.c > > > > index a265b98fe685..ed83c90682ff 100644 > > > > --- a/fs/squashfs/sqfs_dir.c > > > > +++ b/fs/squashfs/sqfs_dir.c > > > > @@ -7,8 +7,7 @@ > > > > > > > > #include > > > > #include > > > > -#include > > > > -#include > > > > +#include > > > > #include > > > > #include > > > > #include > > > > > > Cheers, > > > Miquèl > > > Thanks, > Miquèl
Re: [PATCH 10/11] virtio: rng: Check length before copying
On Wed, 6 Apr 2022 at 15:18, Pierre-Clément Tosi wrote:
>
> Hi,
>
> On Thu, Mar 31, 2022 at 10:09:48AM +, Andrew Scull wrote:
> > Check the length of data written by the device is consistent with the
> > size of the buffers to avoid out-of-bounds memory accesses in case
> > values aren't consistent.
> >
> > Signed-off-by: Andrew Scull
> > Cc: Sughosh Ganu
> > ---
> > drivers/virtio/virtio_rng.c | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/virtio/virtio_rng.c b/drivers/virtio/virtio_rng.c
> > index 9314c0a03e..b85545c2ee 100644
> > --- a/drivers/virtio/virtio_rng.c
> > +++ b/drivers/virtio/virtio_rng.c
> > @@ -41,6 +41,9 @@ static int virtio_rng_read(struct udevice *dev, void
> > *data, size_t len)
> > while (!virtqueue_get_buf(priv->rng_vq, &rsize))
> > ;
> >
> > + if (rsize > sg.length)
> > + return -EIO;
> > +
>
> Although this patch addresses a legitimate concern, could we instead aim for
> strengthening the lower-level virtio building blocks (e.g.
> virtqueue_get_buf())
> so that higher-level virtio device drivers such as
> virtio-{rng,console,net,...}
> don't have to be littered with checks of this nature? Could this be achieved
> by
> using the shadow copy introduced in [PATCH 03/11]?
There could certainly be _a_ bounds check in the vring driver, to
check that the total size written doesn't exceed the cumulative size
of the writable buffers in the descriptor chain. That would be
satisfactory for this rng driver, since there is only one buffer being
used, but if there is more than one buffer then the device driver will
still need to do checks as it accesses each of them. So it still feels
like the device driver's responsibility to do the checking, given the
current API.
> > memcpy(ptr, buf, rsize);
> > len -= rsize;
> > ptr += rsize;
> > --
> > 2.35.1.1094.g7c7d902a7c-goog
> >
>
> Thanks,
>
> --
> Pierre
Re: [PATCH 08/11] virtio: sandbox: Bind RNG rather than block device
On Thu, 7 Apr 2022 at 08:20, Heinrich Schuchardt wrote:
>
> On 3/31/22 12:09, Andrew Scull wrote:
> > The virtio-rng driver is extremely simple, making it suitable for
> > testing more of the virtio uclass logic. Have the sandbox driver bind
> > the virtio-rng driver rather than the virtio-blk driver so it can be
> > used in tests.
>
> test/dm/rng.c assumes that drivers/rng/sandbox_rng.c is providing the
> only RNG device.
>
> Does test/dm/virtio.c guarantee that no virtio-rng device is bound after
> the test is run?
My understanding was that dm_test_pre_run() in test/test-main.c reset
the driver model for each dm test, which would imply that nothing is
bound at the start of the test. Have I understood this correctly?
> Best regards
>
> Heinrich
>
> >
> > Signed-off-by: Andrew Scull
> > ---
> > drivers/virtio/virtio_sandbox.c | 2 +-
> > test/dm/virtio.c| 8
> > 2 files changed, 5 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/virtio/virtio_sandbox.c
> > b/drivers/virtio/virtio_sandbox.c
> > index a73b123454..5484ae3a1a 100644
> > --- a/drivers/virtio/virtio_sandbox.c
> > +++ b/drivers/virtio/virtio_sandbox.c
> > @@ -161,7 +161,7 @@ static int virtio_sandbox_probe(struct udevice *udev)
> >
> > /* fake some information for testing */
> > priv->device_features = BIT_ULL(VIRTIO_F_VERSION_1);
> > - uc_priv->device = VIRTIO_ID_BLOCK;
> > + uc_priv->device = VIRTIO_ID_RNG;
> > uc_priv->vendor = ('u' << 24) | ('b' << 16) | ('o' << 8) | 't';
> >
> > return 0;
> > diff --git a/test/dm/virtio.c b/test/dm/virtio.c
> > index d054ccfaa4..769945a0d8 100644
> > --- a/test/dm/virtio.c
> > +++ b/test/dm/virtio.c
> > @@ -25,10 +25,10 @@ static int dm_test_virtio_base(struct unit_test_state
> > *uts)
> > ut_assertok(uclass_first_device(UCLASS_VIRTIO, &bus));
> > ut_assertnonnull(bus);
> >
> > - /* check the child virtio-blk device is bound */
> > + /* check the child virtio-rng device is bound */
> > ut_assertok(device_find_first_child(bus, &dev));
> > ut_assertnonnull(dev);
> > - ut_assertok(strcmp(dev->name, "virtio-blk#0"));
> > + ut_asserteq_str("virtio-rng#0", dev->name);
> >
> > /* check driver status */
> > ut_assertok(virtio_get_status(dev, &status));
> > @@ -54,7 +54,7 @@ static int dm_test_virtio_all_ops(struct unit_test_state
> > *uts)
> > ut_assertok(uclass_first_device(UCLASS_VIRTIO, &bus));
> > ut_assertnonnull(bus);
> >
> > - /* check the child virtio-blk device is bound */
> > + /* check the child virtio-rng device is bound */
> > ut_assertok(device_find_first_child(bus, &dev));
> > ut_assertnonnull(dev);
> >
> > @@ -114,7 +114,7 @@ static int dm_test_virtio_remove(struct unit_test_state
> > *uts)
> > ut_assertok(uclass_first_device(UCLASS_VIRTIO, &bus));
> > ut_assertnonnull(bus);
> >
> > - /* check the child virtio-blk device is bound */
> > + /* check the child virtio-rng device is bound */
> > ut_assertok(device_find_first_child(bus, &dev));
> > ut_assertnonnull(dev);
> >
>
[PATCH 00/11] board: freescale: p1_p2_rdb_pc: Various cleanups and fixes
This patch series contains various cleanups and fixes for shared P1*/P2* board code and preparation for introducing support for another P2020 board. Pali Rohár (11): board: freescale: p1_p2_rdb_pc: Do not hang in checkboard() board: freescale: p1_p2_rdb_pc: Detect both P2020 SD switch configurations board: freescale: p1_p2_rdb_pc: Fix parsing negated upper 4 bits from boot input data board: freescale: p1_p2_rdb_pc: Do not set MPC85xx_PMUXCR_SDHC_WP bit when SDHC_WP is used as GPIO board: freescale: p1_p2_rdb_pc: Fix page attributes for second 1G SDRAM map board: freescale: p1_p2_rdb_pc: Move ifdef for USB/eLBC check to correct place board: freescale: p1_p2_rdb_pc: Fix env $vscfw_addr board: freescale: p1_p2_rdb_pc: Use named macros for i2c bus num and address board: freescale: p1_p2_rdb_pc: Define SW macros for lower and upper NOR banks board: freescale: p1_p2_rdb_pc: Move BootROM change source macros to p1_p2_bootrom.h board: freescale: p1_p2_rdb_pc: Add env commands norlowerboot, norupperboot, sd2boot and defboot board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 20 ++- board/freescale/p1_p2_rdb_pc/tlb.c | 6 +- include/configs/p1_p2_bootrom.h | 46 +++ include/configs/p1_p2_rdb_pc.h | 130 +++- 4 files changed, 164 insertions(+), 38 deletions(-) create mode 100644 include/configs/p1_p2_bootrom.h -- 2.20.1
[PATCH 01/11] board: freescale: p1_p2_rdb_pc: Do not hang in checkboard()
Like in all other checks in checkboard() function, do not hang on error.
Signed-off-by: Pali Rohár
---
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 19ece1229631..186887336354 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -182,7 +182,7 @@ int checkboard(void)
if (ret) {
printf("%s: Cannot find udev for a bus %d\n", __func__,
bus_num);
- return -ENXIO;
+ return 0; /* Don't want to hang() on this error */
}
if (dm_i2c_read(dev, 0, &in, 1) < 0 ||
--
2.20.1
[PATCH 07/11] board: freescale: p1_p2_rdb_pc: Fix env $vscfw_addr
Do not stringify env $vscfw_addr two times (once implicitly via string operator "" and second time explicitly via __stringify() macro) and allow to compile U-Boot without CONFIG_VSC7385_ENET (when __VSCFW_ADDR was not defined and so macro name was stringified into CONFIG_EXTRA_ENV_SETTINGS). Signed-off-by: Pali Rohár --- include/configs/p1_p2_rdb_pc.h | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index ecc6e0c644bf..7b5a8dd9e509 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -351,7 +351,7 @@ /* Vsc7385 switch */ #ifdef CONFIG_VSC7385_ENET -#define __VSCFW_ADDR "vscfw_addr=ef00" +#define __VSCFW_ADDR "vscfw_addr=ef00\0" #define CONFIG_SYS_VSC7385_BASE0xffb0 #ifdef CONFIG_PHYS_64BIT @@ -370,6 +370,10 @@ #define CONFIG_VSC7385_IMAGE_SIZE 8192 #endif +#ifndef __VSCFW_ADDR +#define __VSCFW_ADDR "" +#endif + /* * Config the L2 Cache as L2 SRAM */ @@ -614,7 +618,7 @@ i2c mw 18 3 __SW_BOOT_MASK 1; reset "ramdisk_size=12\0"\ "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ -__stringify(__VSCFW_ADDR)"\0" \ +__VSCFW_ADDR \ __stringify(__NOR_RST_CMD)"\0" \ __stringify(__SPI_RST_CMD)"\0" \ __stringify(__SD_RST_CMD)"\0" \ -- 2.20.1
[PATCH 02/11] board: freescale: p1_p2_rdb_pc: Detect both P2020 SD switch configurations
As written in comment, P2020 has two possible SD switch configurations.
Extend code to detect both of them.
Signed-off-by: Pali Rohár
---
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 4
include/configs/p1_p2_rdb_pc.h | 3 ++-
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 186887336354..29502a5c05c2 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -207,6 +207,10 @@ int checkboard(void)
puts("rom_loc: ");
if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) {
puts("sd");
+#ifdef __SW_BOOT_SD2
+ } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD2) {
+ puts("sd");
+#endif
#ifdef __SW_BOOT_SPI
} else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SPI) {
puts("spi");
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 370772053e63..ecc6e0c644bf 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -60,7 +60,8 @@
#define __SW_BOOT_MASK 0x03
#define __SW_BOOT_NOR 0xc8
#define __SW_BOOT_SPI 0x28
-#define __SW_BOOT_SD 0x68 /* or 0x18 */
+#define __SW_BOOT_SD 0x68
+#define __SW_BOOT_SD2 0x18
#define __SW_BOOT_NAND 0xe8
#define __SW_BOOT_PCIE 0xa8
#define CONFIG_SYS_L2_SIZE (512 << 10)
--
2.20.1
[PATCH 04/11] board: freescale: p1_p2_rdb_pc: Do not set MPC85xx_PMUXCR_SDHC_WP bit when SDHC_WP is used as GPIO
When MPC85xx_PMUXCR_SDHC_WP is set then SDHC controller automatically makes
inserted SD card readonly if GPIO[9] is active.
In some design GPIO[9] pin does not have to be connected to SD card
write-protect pin and can be used as GPIO.
So do not set MPC85xx_PMUXCR_SDHC_WP bit when GPIO[9] is not used for
SDHC_WP functionality.
Signed-off-by: Pali Rohár
---
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 766a82386079..fc581bdb2a40 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -147,8 +147,10 @@ int board_early_init_f(void)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- setbits_be32(&gur->pmuxcr,
- (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
+ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SDHC_CD);
+#ifndef SDHC_WP_IS_GPIO
+ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SDHC_WP);
+#endif
clrbits_be32(&gur->sdhcdcr, SDHCDCR_CD_INV);
clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
--
2.20.1
[PATCH 10/11] board: freescale: p1_p2_rdb_pc: Move BootROM change source macros to p1_p2_bootrom.h
Code for changing BootROM source is platform generic and can be used by any P1* and P2* compatible board. Not only by RDB boards which use config header file p1_p2_rdb_pc.h. So move this code from p1_p2_rdb_pc.h to p1_p2_bootrom.h and cleanup macros for generating boot source env variables in CONFIG_EXTRA_ENV_SETTINGS. This allows to use code for changing BootROM source also by other boards in future. Signed-off-by: Pali Rohár --- include/configs/p1_p2_bootrom.h | 32 +++ include/configs/p1_p2_rdb_pc.h | 73 + 2 files changed, 78 insertions(+), 27 deletions(-) create mode 100644 include/configs/p1_p2_bootrom.h diff --git a/include/configs/p1_p2_bootrom.h b/include/configs/p1_p2_bootrom.h new file mode 100644 index ..a1f61b788cf7 --- /dev/null +++ b/include/configs/p1_p2_bootrom.h @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ +// (C) 2022 Pali Rohár + +#define CHANGE_BOOTROM_SOURCE_CMD(SOURCE, MASK) i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 SOURCE 1; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 MASK 1 + +#ifdef __SW_NOR_BANK_LO +#define CHANGE_BOOTROM_LOWER_NOR_BANK_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_NOR_BANK_LO, __SW_NOR_BANK_MASK) +#endif + +#ifdef __SW_NOR_BANK_UP +#define CHANGE_BOOTROM_UPPER_NOR_BANK_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_NOR_BANK_UP, __SW_NOR_BANK_MASK) +#endif + +#ifdef __SW_BOOT_NOR +#define CHANGE_BOOTROM_SOURCE_DEF_NOR_BANK_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_NOR, __SW_BOOT_MASK) +#endif + +#ifdef __SW_BOOT_SPI +#define CHANGE_BOOTROM_SOURCE_SPI_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_SPI, __SW_BOOT_MASK) +#endif + +#ifdef __SW_BOOT_SD +#define CHANGE_BOOTROM_SOURCE_SD_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_SD, __SW_BOOT_MASK) +#endif + +#ifdef __SW_BOOT_NAND +#define CHANGE_BOOTROM_SOURCE_NAND_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_NAND, __SW_BOOT_MASK) +#endif + +#ifdef __SW_BOOT_PCIE +#define CHANGE_BOOTROM_SOURCE_PCIE_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_PCIE, __SW_BOOT_MASK) +#endif diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 995bd983cef1..d41b31081017 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -79,6 +79,8 @@ */ #endif +#include "p1_p2_bootrom.h" + #ifdef CONFIG_SDCARD #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" @@ -575,30 +577,46 @@ #define CONFIG_BOOTFILE"uImage" #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ -#ifdef __SW_BOOT_NOR -#define __NOR_RST_CMD \ -norboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NOR 1; \ -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset +#ifdef CHANGE_BOOTROM_LOWER_NOR_BANK_CMD +#define __MAP_NOR_LOWER_CMD "map_lowernorbank="__stringify(CHANGE_BOOTROM_LOWER_NOR_BANK_CMD)"\0" +#else +#define __MAP_NOR_LOWER_CMD "" +#endif + +#ifdef CHANGE_BOOTROM_UPPER_NOR_BANK_CMD +#define __MAP_NOR_UPPER_CMD "map_uppernorbank="__stringify(CHANGE_BOOTROM_UPPER_NOR_BANK_CMD)"\0" +#else +#define __MAP_NOR_UPPER_CMD "" +#endif + +#ifdef CHANGE_BOOTROM_SOURCE_DEF_NOR_BANK_CMD +#define __NOR_RST_CMD "norboot="__stringify(CHANGE_BOOTROM_SOURCE_DEF_NOR_BANK_CMD)"; reset\0" +#else +#define __NOR_RST_CMD "" #endif -#ifdef __SW_BOOT_SPI -#define __SPI_RST_CMD \ -spiboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SPI 1; \ -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset + +#ifdef CHANGE_BOOTROM_SOURCE_SPI_CMD +#define __SPI_RST_CMD "spiboot="__stringify(CHANGE_BOOTROM_SOURCE_SPI_CMD)"; reset\0" +#else +#define __SPI_RST_CMD "" #endif -#ifdef __SW_BOOT_SD -#define __SD_RST_CMD \ -sdboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SD 1; \ -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset + +#ifdef CHANGE_BOOTROM_SOURCE_SD_CMD +#define __SD_RST_CMD "sdboot="__stringify(CHANGE_BOOTROM_SOURCE_SD_CMD)"; reset\0" +#else +#define __SD_RST_CMD "" #endif -#ifdef __SW_BOOT_NAND -#define __NAND_RST_CMD \ -nandboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NAND 1; \ -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset + +#ifdef CHANGE_BOOTROM_SOURCE_NAND_CMD +#define __NAND_RST_CMD "nandboot="__stringify(CHANGE_BOOTROM_SOURCE_NAND_CMD)"; reset\0" +#else +#define __NAND_RST_CMD "" #endif -#ifdef __SW_BOOT_PCIE -#define __PCIE_RST_CMD \ -pciboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_PCIE 1; \ -i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset + +#ifdef CHANGE_BOOTROM_SOURCE_PCIE_CMD +#define __PCIE_RST_CMD "pciboot="__stringify(CHANGE_BOOTROM_SOURCE_PCIE_CMD)"; reset\0" +#else +#define __PCIE_RST_CMD "" #endif #defineCONFIG_EXTRA_ENV_SETTINGS \ @@ -626,13 +644,14 @@ i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset
[PATCH 03/11] board: freescale: p1_p2_rdb_pc: Fix parsing negated upper 4 bits from boot input data
On some boards upper 4 bits of i2c boot input data (register 0) are
negated. So negate read input data back prior processing them.
Fixes printing correct rom_loc: value.
Signed-off-by: Pali Rohár
---
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 4
1 file changed, 4 insertions(+)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 29502a5c05c2..766a82386079 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -202,6 +202,10 @@ int checkboard(void)
}
#endif
+#ifdef __SW_BOOT_IN_NEG_UPPER4
+ in = (~in & 0xf0) | (in & 0x0f);
+#endif
+
val = (in & io_config) | (out & (~io_config));
puts("rom_loc: ");
--
2.20.1
[PATCH 05/11] board: freescale: p1_p2_rdb_pc: Fix page attributes for second 1G SDRAM map
Like for first 1G SDRAM map, do not enable Caching-inhibited nor Guarded
attribute for second 1G SDRAM mapping. Whole 2G SDRAM should use caches and
also allow speculative loading (by not setting Guarded attribute).
Also enable Memory Coherency attribute for second 1G SDRAM map. In commit
316f0d0f8f3c ("powerpc: mpc85xx: Fix static TLB table for SDRAM") it was
enabled for all SDRAM maps on all other boards, just missed this one case.
As a last thing, first 1G SDRAM map has wrong comment, so adjust it.
Signed-off-by: Pali Rohár
---
board/freescale/p1_p2_rdb_pc/tlb.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c
b/board/freescale/p1_p2_rdb_pc/tlb.c
index fcd7a55199f0..5931ec650bd8 100644
--- a/board/freescale/p1_p2_rdb_pc/tlb.c
+++ b/board/freescale/p1_p2_rdb_pc/tlb.c
@@ -79,16 +79,16 @@ struct fsl_e_tlb_entry tlb_table[] = {
#if defined(CONFIG_SYS_RAMBOOT) || \
(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
- /* *I*G - eSDHC/eSPI/NAND boot */
+ /* **M** - 1G DDR for eSDHC/eSPI/NAND boot */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 8, BOOKE_PAGESZ_1G, 1),
#if defined(CONFIG_TARGET_P1020RDB_PD)
- /* 2G DDR on P1020MBG, map the second 1G */
+ /* **M** - 2G DDR on P1020MBG, map the second 1G */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000,
CONFIG_SYS_DDR_SDRAM_BASE + 0x4000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 9, BOOKE_PAGESZ_1G, 1),
#endif
#endif /* RAMBOOT/SPL */
--
2.20.1
[PATCH 09/11] board: freescale: p1_p2_rdb_pc: Define SW macros for lower and upper NOR banks
Replace hardcoded i2c hex values for NOR banks by named SW macros in map_lowernorbank/map_uppernorbank env commands. Signed-off-by: Pali Rohár --- include/configs/p1_p2_rdb_pc.h | 13 +++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index cb3b1a1da05d..995bd983cef1 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -22,6 +22,9 @@ #define __SW_BOOT_SD 0x9c #define __SW_BOOT_NAND 0xec #define __SW_BOOT_PCIE 0x6c +#define __SW_NOR_BANK_MASK 0xfd +#define __SW_NOR_BANK_UP 0x00 +#define __SW_NOR_BANK_LO 0x02 #define CONFIG_SYS_L2_SIZE (256 << 10) #endif @@ -48,6 +51,9 @@ #define __SW_BOOT_SD 0x24 #define __SW_BOOT_NAND 0x44 #define __SW_BOOT_PCIE 0x74 +#define __SW_NOR_BANK_MASK 0xfd +#define __SW_NOR_BANK_UP 0x00 +#define __SW_NOR_BANK_LO 0x02 #define CONFIG_SYS_L2_SIZE (256 << 10) /* * Dynamic MTD Partition support with mtdparts @@ -64,6 +70,9 @@ #define __SW_BOOT_SD2 0x18 #define __SW_BOOT_NAND 0xe8 #define __SW_BOOT_PCIE 0xa8 +#define __SW_NOR_BANK_MASK 0xfd +#define __SW_NOR_BANK_UP 0x00 +#define __SW_NOR_BANK_LO 0x02 #define CONFIG_SYS_L2_SIZE (512 << 10) /* * Dynamic MTD Partition support with mtdparts @@ -617,8 +626,8 @@ i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset "nandfdtaddr=8\0" \ "ramdisk_size=12\0"\ __VSCFW_ADDR \ -"map_lowernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 02 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 fd 1\0" \ -"map_uppernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 00 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 fd 1\0" \ +"map_lowernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_LO)" 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 "__stringify(__SW_NOR_BANK_MASK)" 1\0" \ +"map_uppernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_UP)" 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 "__stringify(__SW_NOR_BANK_MASK)" 1\0" \ __stringify(__NOR_RST_CMD)"\0" \ __stringify(__SPI_RST_CMD)"\0" \ __stringify(__SD_RST_CMD)"\0" \ -- 2.20.1
[PATCH 06/11] board: freescale: p1_p2_rdb_pc: Move ifdef for USB/eLBC check to correct place
Whole section about USB/eLBC configuration seems to be P1020 specific. So
add ifdefs to not compile it on other platforms (e.g. P2020).
Signed-off-by: Pali Rohár
---
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index fc581bdb2a40..1b28f1bbc776 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -354,9 +354,9 @@ int ft_board_setup(void *blob, struct bd_info *bd)
#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
const char *soc_usb_compat = "fsl-usb2-dr";
int usb_err, usb1_off, usb2_off;
-#endif
#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
int err;
+#endif
#endif
ft_cpu_setup(blob, bd);
@@ -375,6 +375,7 @@ int ft_board_setup(void *blob, struct bd_info *bd)
fsl_fdt_fixup_dr_usb(blob, bd);
#endif
+#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
/* Delete eLBC node as it is muxed with USB2 controller */
if (hwconfig("usb2")) {
@@ -396,7 +397,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
}
#endif
-#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
/* Delete USB2 node as it is muxed with eLBC */
usb1_off = fdt_node_offset_by_compatible(blob, -1,
soc_usb_compat);
--
2.20.1
[PATCH 11/11] board: freescale: p1_p2_rdb_pc: Add env commands norlowerboot, norupperboot, sd2boot and defboot
All *boot env commands overrides default BootROM boot location via i2c. BootROM then starts booting U-Boot from this specified location instead of the default one. Add new env command defboot which reverts BootROM boot location to the default value, which in most cases is configurable by HW DIP switches. And add new env commands norlowerboot, norupperboot, sd2boot to boot from other locations. norlowerboot would instruct BootROM to boot from lower NOR bank, norupperboot from upper NOR bank and sd2boot from SD card with alternative configuration. Signed-off-by: Pali Rohár --- include/configs/p1_p2_bootrom.h | 14 + include/configs/p1_p2_rdb_pc.h | 37 + 2 files changed, 51 insertions(+) diff --git a/include/configs/p1_p2_bootrom.h b/include/configs/p1_p2_bootrom.h index a1f61b788cf7..d1e91049606b 100644 --- a/include/configs/p1_p2_bootrom.h +++ b/include/configs/p1_p2_bootrom.h @@ -15,6 +15,14 @@ #define CHANGE_BOOTROM_SOURCE_DEF_NOR_BANK_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_NOR, __SW_BOOT_MASK) #endif +#ifdef __SW_BOOT_NOR_BANK_LO +#define CHANGE_BOOTROM_SOURCE_LOWER_NOR_BANK_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_NOR_BANK_LO, __SW_BOOT_NOR_BANK_MASK) +#endif + +#ifdef __SW_BOOT_NOR_BANK_UP +#define CHANGE_BOOTROM_SOURCE_UPPER_NOR_BANK_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_NOR_BANK_UP, __SW_BOOT_NOR_BANK_MASK) +#endif + #ifdef __SW_BOOT_SPI #define CHANGE_BOOTROM_SOURCE_SPI_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_SPI, __SW_BOOT_MASK) #endif @@ -23,6 +31,10 @@ #define CHANGE_BOOTROM_SOURCE_SD_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_SD, __SW_BOOT_MASK) #endif +#ifdef __SW_BOOT_SD2 +#define CHANGE_BOOTROM_SOURCE_SD2_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_SD2, __SW_BOOT_MASK) +#endif + #ifdef __SW_BOOT_NAND #define CHANGE_BOOTROM_SOURCE_NAND_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_NAND, __SW_BOOT_MASK) #endif @@ -30,3 +42,5 @@ #ifdef __SW_BOOT_PCIE #define CHANGE_BOOTROM_SOURCE_PCIE_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_PCIE, __SW_BOOT_MASK) #endif + +#define CHANGE_BOOTROM_SOURCE_DEF_CMD CHANGE_BOOTROM_SOURCE_CMD(0x00, 0xff) diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index d41b31081017..ac8199a88aa0 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -25,6 +25,9 @@ #define __SW_NOR_BANK_MASK 0xfd #define __SW_NOR_BANK_UP 0x00 #define __SW_NOR_BANK_LO 0x02 +#define __SW_BOOT_NOR_BANK_UP 0x5c /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */ +#define __SW_BOOT_NOR_BANK_LO 0x5e /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */ +#define __SW_BOOT_NOR_BANK_MASK0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */ #define CONFIG_SYS_L2_SIZE (256 << 10) #endif @@ -54,6 +57,9 @@ #define __SW_NOR_BANK_MASK 0xfd #define __SW_NOR_BANK_UP 0x00 #define __SW_NOR_BANK_LO 0x02 +#define __SW_BOOT_NOR_BANK_UP 0x64 /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */ +#define __SW_BOOT_NOR_BANK_LO 0x66 /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */ +#define __SW_BOOT_NOR_BANK_MASK0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */ #define CONFIG_SYS_L2_SIZE (256 << 10) /* * Dynamic MTD Partition support with mtdparts @@ -73,6 +79,9 @@ #define __SW_NOR_BANK_MASK 0xfd #define __SW_NOR_BANK_UP 0x00 #define __SW_NOR_BANK_LO 0x02 +#define __SW_BOOT_NOR_BANK_UP 0xc8 /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */ +#define __SW_BOOT_NOR_BANK_LO 0xca /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */ +#define __SW_BOOT_NOR_BANK_MASK0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */ #define CONFIG_SYS_L2_SIZE (512 << 10) /* * Dynamic MTD Partition support with mtdparts @@ -595,6 +604,18 @@ #define __NOR_RST_CMD "" #endif +#ifdef CHANGE_BOOTROM_SOURCE_LOWER_NOR_BANK_CMD +#define __NOR_LOWER_RST_CMD "norlowerboot="__stringify(CHANGE_BOOTROM_SOURCE_LOWER_NOR_BANK_CMD)"; reset\0" +#else +#define __NOR_LOWER_RST_CMD "" +#endif + +#ifdef CHANGE_BOOTROM_SOURCE_UPPER_NOR_BANK_CMD +#define __NOR_UPPER_RST_CMD "norupperboot="__stringify(CHANGE_BOOTROM_SOURCE_UPPER_NOR_BANK_CMD)"; reset\0" +#else +#define __NOR_UPPER_RST_CMD "" +#endif + #ifdef CHANGE_BOOTROM_SOURCE_SPI_CMD #define __SPI_RST_CMD "spiboot="__stringify(CHANGE_BOOTROM_SOURCE_SPI_CMD)"; reset\0" #else @@ -607,6 +628,12 @@ #define __SD_RST_CMD "" #endif +#ifdef CHANGE_BOOTROM_SOURCE_SD2_CMD +#define __SD2_RST_CMD "sd2boot="__stringify(CHANGE_BOOTROM_SOURCE_SD2_CMD)"; reset\0" +#else +#define __SD2_RST_CMD "" +#endif + #ifdef CHANGE_BOOTROM_SOURCE_NAND_CMD #define __NAND_RST_CMD "nandboot="__stringify(CHANGE_BOOTROM_SOURCE_NAND_CMD)"; reset\0" #else @@ -619,6 +646,12 @@ #define __PCIE_RST_CMD "" #endif +#ifdef CHANGE_BOOTROM_SOURCE_DEF_CMD +#define __DEF_RST_CMD "defboot="__stringify(CHANGE_BOOTROM_SOURCE_DEF_CMD)"; reset\0" +#else +#define __DEF_RST_CMD "" +#endif + #defineCONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0"\ "uboot=" __stringify(C
[PATCH 08/11] board: freescale: p1_p2_rdb_pc: Use named macros for i2c bus num and address
Replace hardcoded boot i2c bus num and address by existing macros when generating env for CONFIG_EXTRA_ENV_SETTINGS. Same macros are used in U-Boot board code when reading information from boot i2c data. Signed-off-by: Pali Rohár --- include/configs/p1_p2_rdb_pc.h | 24 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 7b5a8dd9e509..cb3b1a1da05d 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -568,28 +568,28 @@ #ifdef __SW_BOOT_NOR #define __NOR_RST_CMD \ -norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \ -i2c mw 18 3 __SW_BOOT_MASK 1; reset +norboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NOR 1; \ +i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset #endif #ifdef __SW_BOOT_SPI #define __SPI_RST_CMD \ -spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \ -i2c mw 18 3 __SW_BOOT_MASK 1; reset +spiboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SPI 1; \ +i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset #endif #ifdef __SW_BOOT_SD #define __SD_RST_CMD \ -sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \ -i2c mw 18 3 __SW_BOOT_MASK 1; reset +sdboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SD 1; \ +i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset #endif #ifdef __SW_BOOT_NAND #define __NAND_RST_CMD \ -nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \ -i2c mw 18 3 __SW_BOOT_MASK 1; reset +nandboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NAND 1; \ +i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset #endif #ifdef __SW_BOOT_PCIE #define __PCIE_RST_CMD \ -pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \ -i2c mw 18 3 __SW_BOOT_MASK 1; reset +pciboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_PCIE 1; \ +i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset #endif #defineCONFIG_EXTRA_ENV_SETTINGS \ @@ -616,9 +616,9 @@ i2c mw 18 3 __SW_BOOT_MASK 1; reset "nandbootaddr=10\0"\ "nandfdtaddr=8\0" \ "ramdisk_size=12\0"\ -"map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ -"map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ __VSCFW_ADDR \ +"map_lowernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 02 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 fd 1\0" \ +"map_uppernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 00 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 fd 1\0" \ __stringify(__NOR_RST_CMD)"\0" \ __stringify(__SPI_RST_CMD)"\0" \ __stringify(__SD_RST_CMD)"\0" \ -- 2.20.1
Re: [PATCH v2] IOMUX: Fix access past end of console_devices
On Wed, Apr 06, 2022 at 02:36:35PM -0400, Sean Anderson wrote:
> We should only access console_devices[file][i] once we have checked that i
> < cd_count[file]. Otherwise, we will access uninitialized memory at the end
> of the loop. console_devices[file][i] should not be NULL, but putting the
> assignment in the loop condition allows us to ensure that i is checked
> beforehand. This isn't a bug, but it does make valgrind stop complaining.
Acked-by: Andy Shevchenko
> Fixes: 400797cad3 ("IOMUX: Split out for_each_console_dev() helper macro")
> Signed-off-by: Sean Anderson
> Reviewed-by: Andrew Scull
> ---
>
> Changes in v2:
> - Put each clause of the for loop on its own line
>
> include/iomux.h | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/include/iomux.h b/include/iomux.h
> index 37f5f6dee6..35caa697eb 100644
> --- a/include/iomux.h
> +++ b/include/iomux.h
> @@ -24,10 +24,10 @@ extern struct stdio_dev **console_devices[MAX_FILES];
> */
> extern int cd_count[MAX_FILES];
>
> -#define for_each_console_dev(i, file, dev) \
> - for (i = 0, dev = console_devices[file][i]; \
> - i < cd_count[file];\
> - i++, dev = console_devices[file][i])
> +#define for_each_console_dev(i, file, dev) \
> + for (i = 0; \
> + i < cd_count[file] && (dev = console_devices[file][i]);\
> + i++)
>
> int iomux_match_device(struct stdio_dev **, const int, struct stdio_dev *);
> int iomux_doenv(const int, const char *);
> --
> 2.35.1
>
--
With Best Regards,
Andy Shevchenko
Re: [PATCH] arm: mvebu: Add support for reading LD0 and LD1 eFuse
On Wednesday 06 April 2022 21:21:59 Marek Behún wrote: > On Wed, 6 Apr 2022 14:18:18 +0200 > Pali Rohár wrote: > > > Armada 385 contains 64 lines of HD eFuse and 2 lines of LD eFuse. HD eFuse > > is used for secure boot and each line is 64 bits long + 1 lock bit. LD > > eFuse lines are 256 bits long + 1 lock bit. LD 0 line is reserved for > > Marvell Internal Use and LD 1 line is for General Purpose Data. U-Boot > > already contains HD eFuse reading and programming support. > > > > This patch implements LD eFuse reading support. LD 0 line is mapped to > > U-Boot fuse bank 64 and LD 1 line to fuse bank 65. > > > > LD 0 Marvell Internal Use line seems that was burned in factory with some > > data and can be read by U-Boot fuse command: > > > > => fuse read 64 0 9 > > > > LD 1 General Purpose Data line is by default empty and can be read by > > U-Boot fuse command: > > > > => fuse read 65 0 9 > > > > Signed-off-by: Pali Rohár > > I am not sure whether this can be used safely on Turris Omnia - there > was some issue with voltage or something, I know for sure that burning > does not work on Omnia, but I am not sure if the issue also prevents > stable reading. On A385 there is errata only for programming OTP bits. > Are the values you read always the same? Even across power cycles? > > Marek Reading is working fine and is stable also after power cycles. Marvell Internal Use contains data which are same after more reads.
Re: [PATCH] arm: mvebu: Add support for reading LD0 and LD1 eFuse
On Thu, 7 Apr 2022 13:53:23 +0200 Pali Rohár wrote: > On Wednesday 06 April 2022 21:21:59 Marek Behún wrote: > > On Wed, 6 Apr 2022 14:18:18 +0200 > > Pali Rohár wrote: > > > > > Armada 385 contains 64 lines of HD eFuse and 2 lines of LD eFuse. HD eFuse > > > is used for secure boot and each line is 64 bits long + 1 lock bit. LD > > > eFuse lines are 256 bits long + 1 lock bit. LD 0 line is reserved for > > > Marvell Internal Use and LD 1 line is for General Purpose Data. U-Boot > > > already contains HD eFuse reading and programming support. > > > > > > This patch implements LD eFuse reading support. LD 0 line is mapped to > > > U-Boot fuse bank 64 and LD 1 line to fuse bank 65. > > > > > > LD 0 Marvell Internal Use line seems that was burned in factory with some > > > data and can be read by U-Boot fuse command: > > > > > > => fuse read 64 0 9 > > > > > > LD 1 General Purpose Data line is by default empty and can be read by > > > U-Boot fuse command: > > > > > > => fuse read 65 0 9 > > > > > > Signed-off-by: Pali Rohár > > > > I am not sure whether this can be used safely on Turris Omnia - there > > was some issue with voltage or something, I know for sure that burning > > does not work on Omnia, but I am not sure if the issue also prevents > > stable reading. > > On A385 there is errata only for programming OTP bits. > > > Are the values you read always the same? Even across power cycles? > > > > Marek > > Reading is working fine and is stable also after power cycles. Marvell > Internal Use contains data which are same after more reads. In that case Reviewed-by: Marek Behún
Re: [PATCH] arm: mvebu: a37xx: Add support for writing Security OTP values
On Thu, 7 Apr 2022 11:32:10 +0200
Pali Rohár wrote:
> Implement write support for Security OTP values via mailbox API commands
> MBOX_CMD_OTP_WRITE_32B and MBOX_CMD_OTP_WRITE.
>
> Write support for North and South Bridge OTPs are not implemented as these
> OTPs are already burned in factory with some data.
>
> Signed-off-by: Pali Rohár
> ---
> This patch depends on series which implements read support for A3720 OTP:
> https://patchwork.ozlabs.org/project/uboot/list/?series=287578&state=*
>
> Stefan, what do you think, should be enable write support by default. Or
> should it be hidden under some other CONFIG option? Becaue currently
> CONFIG_CMD_FUSE enable both read and write support (or what driver
> implements).
> ---
> arch/arm/mach-mvebu/armada3700/efuse.c | 50 --
> 1 file changed, 48 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-mvebu/armada3700/efuse.c
> b/arch/arm/mach-mvebu/armada3700/efuse.c
> index 50c73f36c565..07d5f394354c 100644
> --- a/arch/arm/mach-mvebu/armada3700/efuse.c
> +++ b/arch/arm/mach-mvebu/armada3700/efuse.c
> @@ -113,6 +113,41 @@ static int rwtm_otp_read(u8 row, u32 word, u32 *data)
> return res;
> }
>
> +static int rwtm_otp_write(u8 row, u32 word, u32 data)
> +{
> + u32 in[4];
> + int res = -EINVAL;
> +
> + if (word < 2) {
> + /*
> + * MBOX_CMD_OTP_WRITE_32B command is supported by Marvell
> + * fuse.bin firmware and also by new CZ.NIC wtmi firmware.
> + * This command writes only selected bits to OTP and does
> + * not calculate ECC bits. It does not allow to write the
> + * lock bit.
> + */
> + in[0] = row;
> + in[1] = word * 32;
> + in[2] = data;
> + res = mbox_do_cmd(MBOX_CMD_OTP_WRITE_32B, in, 3, NULL, 0);
> + } else if (word == 2 && !(data & ~0x1)) {
> + /*
> + * MBOX_CMD_OTP_WRITE command is supported only by new CZ.NIC
> + * wtmi firmware and allows to write any bit to OTP, including
> + * the lock bit. It does not calculate or write ECC bits too.
> + * For compatibility with Marvell fuse.bin firmware, use this
> + * command only for writing the lock bit.
> + */
> + in[0] = row;
> + in[1] = 0;
> + in[2] = 0;
> + in[3] = data;
> + res = mbox_do_cmd(MBOX_CMD_OTP_WRITE, in, 4, NULL, 0);
> + }
> +
> + return res;
> +}
> +
> /*
> * Banks 0-43 are used for accessing Security OTP (44 rows with 67 bits via
> 44 banks and words 0-2)
> * Bank 44 is used for accessing North Bridge OTP (69 bits via words 0-2)
> @@ -154,8 +189,19 @@ int fuse_read(u32 bank, u32 word, u32 *val)
>
> int fuse_prog(u32 bank, u32 word, u32 val)
> {
> - /* TODO: not implemented yet */
> - return -ENOSYS;
> + if (bank <= RWTM_MAX_BANK) {
> + if (word >= RWTM_ROW_WORDS)
> + return -EINVAL;
> + return rwtm_otp_write(bank, word, val);
> + } else if (bank == OTP_NB_BANK) {
> + /* TODO: not implemented yet */
> + return -ENOSYS;
> + } else if (bank == OTP_SB_BANK) {
> + /* TODO: not implemented yet */
> + return -ENOSYS;
> + } else {
> + return -EINVAL;
> + }
> }
>
> int fuse_sense(u32 bank, u32 word, u32 *val)
Reviewed-by: Marek Behún
[PATCH v2 42/52] mips: octeon: Misc changes to existing C files for upcoming eth support
This patch includes misc changes to already present Octeon MIPS C files
files, which are necessary for the upcoming ethernet support.
The changes are mostly:
- DM GPIO & I2C infrastructure
- Coding style cleanup while reworking of the code
Signed-off-by: Stefan Roese
---
arch/mips/mach-octeon/cvmx-bootmem.c | 3 +-
arch/mips/mach-octeon/cvmx-helper-cfg.c | 655 +
arch/mips/mach-octeon/cvmx-helper-fdt.c | 898 ++-
arch/mips/mach-octeon/cvmx-helper-util.c | 248 ---
arch/mips/mach-octeon/cvmx-helper.c | 845 +
5 files changed, 230 insertions(+), 2419 deletions(-)
diff --git a/arch/mips/mach-octeon/cvmx-bootmem.c
b/arch/mips/mach-octeon/cvmx-bootmem.c
index 9bd644d68bd8..52e58b4c1761 100644
--- a/arch/mips/mach-octeon/cvmx-bootmem.c
+++ b/arch/mips/mach-octeon/cvmx-bootmem.c
@@ -1189,7 +1189,7 @@ s64 cvmx_bootmem_phy_mem_list_init(u64 mem_size,
if (mem_size > OCTEON_DDR1_SIZE) {
__cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, OCTEON_DDR1_SIZE, 0);
__cvmx_bootmem_phy_free(OCTEON_DDR2_BASE,
- mem_size - OCTEON_DDR1_SIZE, 0);
+ mem_size - OCTEON_DDR2_BASE, 0);
} else {
__cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, mem_size, 0);
}
@@ -1349,7 +1349,6 @@ s64 cvmx_bootmem_phy_mem_list_init_multi(u8 node_mask,
addr += sizeof(struct cvmx_bootmem_named_block_desc);
}
- // test-only: DEBUG ifdef???
cvmx_bootmem_phy_list_print();
return 1;
diff --git a/arch/mips/mach-octeon/cvmx-helper-cfg.c
b/arch/mips/mach-octeon/cvmx-helper-cfg.c
index 494108f0cdb7..a3f4ff0eeb5f 100644
--- a/arch/mips/mach-octeon/cvmx-helper-cfg.c
+++ b/arch/mips/mach-octeon/cvmx-helper-cfg.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2020 Marvell International Ltd.
+ * Copyright (C) 2020-2022 Marvell International Ltd.
*
* Helper Functions for the Configuration Framework
*/
@@ -100,7 +100,6 @@ static u64 cvmx_cfg_opts[CVMX_HELPER_CFG_OPT_MAX] = {
static int cvmx_cfg_max_pko_engines; /* # of PKO DMA engines allocated */
static int cvmx_pko_queue_alloc(u64 port, int count);
static void cvmx_init_port_cfg(void);
-static const int dbg;
int __cvmx_helper_cfg_pknd(int xiface, int index)
{
@@ -184,16 +183,6 @@ int __cvmx_helper_cfg_pko_max_engine(void)
return cvmx_cfg_max_pko_engines;
}
-int cvmx_helper_cfg_opt_set(cvmx_helper_cfg_option_t opt, uint64_t val)
-{
- if (opt >= CVMX_HELPER_CFG_OPT_MAX)
- return -1;
-
- cvmx_cfg_opts[opt] = val;
-
- return 0;
-}
-
uint64_t cvmx_helper_cfg_opt_get(cvmx_helper_cfg_option_t opt)
{
if (opt >= CVMX_HELPER_CFG_OPT_MAX)
@@ -298,18 +287,6 @@ int cvmx_pko_queue_init_from_cvmx_config_non_pknd(void)
return 0;
}
-int cvmx_helper_pko_queue_config_get(int node,
cvmx_user_static_pko_queue_config_t *cfg)
-{
- *cfg = __cvmx_pko_queue_static_config[node];
- return 0;
-}
-
-int cvmx_helper_pko_queue_config_set(int node,
cvmx_user_static_pko_queue_config_t *cfg)
-{
- __cvmx_pko_queue_static_config[node] = *cfg;
- return 0;
-}
-
static int queue_range_init;
int init_cvmx_pko_que_range(void)
@@ -376,91 +353,6 @@ static int cvmx_pko_queue_alloc(u64 port, int count)
return 0;
}
-/*
- * return the queues for "port"
- *
- * @param port the port for which the queues are returned
- *
- * Return: 0 on success
- * -1 on failure
- */
-int cvmx_pko_queue_free(uint64_t port)
-{
- int ret_val = -1;
-
- init_cvmx_pko_que_range();
- if (port >= CVMX_HELPER_CFG_MAX_PKO_QUEUES) {
- debug("ERROR: %s port=%d > %d", __func__, (int)port,
- CVMX_HELPER_CFG_MAX_PKO_QUEUES);
- return -1;
- }
-
- ret_val = cvmx_free_global_resource_range_with_base(
- CVMX_GR_TAG_PKO_QUEUES,
cvmx_pko_queue_table[port].ccppp_queue_base,
- cvmx_pko_queue_table[port].ccppp_num_queues);
- if (ret_val != 0)
- return ret_val;
-
- cvmx_pko_queue_table[port].ccppp_num_queues = 0;
- cvmx_pko_queue_table[port].ccppp_queue_base =
CVMX_HELPER_CFG_INVALID_VALUE;
- ret_val = 0;
- return ret_val;
-}
-
-void cvmx_pko_queue_free_all(void)
-{
- int i;
-
- for (i = 0; i < CVMX_HELPER_CFG_MAX_PKO_PORT; i++)
- if (cvmx_pko_queue_table[i].ccppp_queue_base !=
- CVMX_HELPER_CFG_INVALID_VALUE)
- cvmx_pko_queue_free(i);
-}
-
-void cvmx_pko_queue_show(void)
-{
- int i;
-
- cvmx_show_global_resource_range(CVMX_GR_TAG_PKO_QUEUES);
- for (i = 0; i < CVMX_HELPER_CFG_MAX_PKO_PORT; i++)
- if (cvmx_pko_queue_table[i].ccppp_queue_base !=
- CVMX_HELPER_CFG_INVALID_VALUE)
- debug("port=%d que_base=%d que_
[PATCH v2 01/52] mips: octeon: Add misc cvmx-* header files
From: Aaron Williams Import misc cvmx-helper header files from 2013 U-Boot. They will be used by the later added drivers to support networking on the MIPS Octeon II / III platforms. Signed-off-by: Aaron Williams Signed-off-by: Stefan Roese --- arch/mips/mach-octeon/include/mach/cvmx-agl.h | 45 + .../mach-octeon/include/mach/cvmx-config.h| 128 ++ arch/mips/mach-octeon/include/mach/cvmx-fau.h | 581 + .../mips/mach-octeon/include/mach/cvmx-mdio.h | 516 .../include/mach/cvmx-pki-cluster.h | 343 ++ arch/mips/mach-octeon/include/mach/cvmx-pko.h | 213 .../include/mach/cvmx-pko3-resources.h| 36 + .../mips/mach-octeon/include/mach/cvmx-pko3.h | 1052 + .../mach-octeon/include/mach/cvmx-range.h | 23 + 9 files changed, 2937 insertions(+) create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-agl.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-config.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-fau.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-mdio.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-pki-cluster.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-pko.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-pko3-resources.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-pko3.h create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-range.h diff --git a/arch/mips/mach-octeon/include/mach/cvmx-agl.h b/arch/mips/mach-octeon/include/mach/cvmx-agl.h new file mode 100644 index ..4afb3a48bfdc --- /dev/null +++ b/arch/mips/mach-octeon/include/mach/cvmx-agl.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018-2022 Marvell International Ltd. + * + * Functions for AGL (RGMII) commong initialization, configuration. + */ + +#ifndef __CVMX_AGL_H__ +#define __CVMX_AGL_H__ + +/* + * @param port to enable + * + * @return Zero on success, negative on failure + */ +int cvmx_agl_enable(int port); + +cvmx_helper_link_info_t cvmx_agl_link_get(int port); + +/* + * Set MII/RGMII link based on mode. + * + * @param port interface port to set the link. + * @param link_info Link status + * + * @return 0 on success and 1 on failure + */ +int cvmx_agl_link_set(int port, cvmx_helper_link_info_t link_info); + +/** + * Disables the sending of flow control (pause) frames on the specified + * AGL (RGMII) port(s). + * + * @param interface Which interface (0 or 1) + * @param port_mask Mask (4bits) of which ports on the interface to disable + * backpressure on. + * 1 => disable backpressure + * 0 => enable backpressure + * + * @return 0 on success + * -1 on error + */ +int cvmx_agl_set_backpressure_override(u32 interface, uint32_t port_mask); + +#endif /* __CVMX_AGL_H__ */ diff --git a/arch/mips/mach-octeon/include/mach/cvmx-config.h b/arch/mips/mach-octeon/include/mach/cvmx-config.h new file mode 100644 index ..4f66a3cce524 --- /dev/null +++ b/arch/mips/mach-octeon/include/mach/cvmx-config.h @@ -0,0 +1,128 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018-2022 Marvell International Ltd. + */ + +#ifndef __CVMX_CONFIG_H__ +#define __CVMX_CONFIG_H__ + +/* Config Specific Defines / +#define CVMX_LLM_NUM_PORTS 1 + +/**< PKO queues per port for interface 0 (ports 0-15) */ +#define CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 1 + +/**< PKO queues per port for interface 1 (ports 16-31) */ +#define CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 1 + +/**< PKO queues per port for interface 4 (AGL) */ +#define CVMX_PKO_QUEUES_PER_PORT_INTERFACE4 1 + +/**< Limit on the number of PKO ports enabled for interface 0 */ +#define CVMX_PKO_MAX_PORTS_INTERFACE0 CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0 + +/**< Limit on the number of PKO ports enabled for interface 1 */ +#define CVMX_PKO_MAX_PORTS_INTERFACE1 CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1 + +/**< PKO queues per port for PCI (ports 32-35) */ +#define CVMX_PKO_QUEUES_PER_PORT_PCI 1 + +/**< PKO queues per port for Loop devices (ports 36-39) */ +#define CVMX_PKO_QUEUES_PER_PORT_LOOP 1 + +/**< PKO queues per port for SRIO0 devices (ports 40-41) */ +#define CVMX_PKO_QUEUES_PER_PORT_SRIO0 1 + +/**< PKO queues per port for SRIO1 devices (ports 42-43) */ +#define CVMX_PKO_QUEUES_PER_PORT_SRIO1 1 + +/* FPA allocation */ +/* Pool sizes in bytes, must be multiple of a cache line */ +#define CVMX_FPA_POOL_0_SIZE (16 * CVMX_CACHE_LINE_SIZE) +#define CVMX_FPA_POOL_1_SIZE (1 * CVMX_CACHE_LINE_SIZE) +#define CVMX_FPA_POOL_2_SIZE (8 * CVMX_CACHE_LINE_SIZE) +#define CVMX_FPA_POOL_3_SIZE (2 * CVMX_CACHE_LINE_SIZE) +#define CVMX_FPA_POOL_4_SIZE (0 * CVMX_CACHE_LINE_SIZE) +#define CVMX_FPA_POOL_5_SIZE (0 * CVMX_CACHE_LINE_SIZE) +#define CVMX_FPA_POOL_6_SIZE (8 * CVMX_CACHE_LINE_SIZE) +#define CVMX_FPA_POOL_7_SIZE (0 * CV
[PATCH] LS1043ARDB, LS1046ARDB, LS1088ARDB: Enable SPL_OF_CONTROL in SECURE Boot defconfig
If enable SPL_DM without SPL_OF_CONTROL, build errors "undefined reference to fdt_get_resource", is coming in function `caam_jr_probe'. Added SPL_OF_CONTROL to remove the error. Signed-off-by: Kshitiz Varshney --- configs/ls1043ardb_nand_SECURE_BOOT_defconfig| 1 + configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig | 1 + configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig | 1 + configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 1 + 4 files changed, 4 insertions(+) diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig index 3ca7dac9e8..e7d7a43351 100644 --- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig @@ -45,6 +45,7 @@ CONFIG_MP=y CONFIG_MTDPARTS_DEFAULT="mtdparts=6000.nor:2m@0x10(nor_bank0_uboot),40m@0x110(nor_bank0_fit),7m(nor_bank0_user),2m@0x410(nor_bank4_uboot),40m@0x510(nor_bank4_fit),-(nor_bank4_user);7e80.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig index 06c1ce5053..c83492c814 100644 --- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig @@ -45,6 +45,7 @@ CONFIG_MP=y CONFIG_MTDPARTS_DEFAULT="mtdparts=6000.nor:2m@0x10(nor_bank0_uboot),40m@0x110(nor_bank0_fit),7m(nor_bank0_user),2m@0x410(nor_bank4_uboot),40m@0x510(nor_bank4_fit),-(nor_bank4_user);7e80.flash:1m(nand_uboot),1m(nand_uboot_env),20m(nand_fit);spi0.0:1m(uboot),5m(kernel),1m(dtb),9m(file_system)" # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig index 5caf24f800..7f2285424a 100644 --- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig @@ -45,6 +45,7 @@ CONFIG_MP=y CONFIG_MTDPARTS_DEFAULT="mtdparts=155.spi-0:1m(rcw),15m(u-boot),48m(kernel.itb);7e80.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)" # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig index 24e4ba7229..0598160fcb 100644 --- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig @@ -50,6 +50,7 @@ CONFIG_CMD_USB=y CONFIG_CMD_CACHE=y CONFIG_MP=y CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y -- 2.25.1
Re: [PATCH 1/9] net: gmac_rockchip: Fix misuse of GENMASK macro
Hi Pierre-Clément,
Thanks for your correction, there was wrong mask here.
Reviewed-by: David Wu
在 2022/4/6 23:08, Kever Yang 写道:
Add David,
Hi David,
Could you help to check this patch?
Thanks,
- Kever
On 2022/3/16 23:39, Pierre-Clément Tosi wrote:
Swap the arguments as that seems to have been the author's intention.
Note: This fix wasn't tested on hardware and will result in more bits
being set by the underlying writel() in rk_clrsetreg(), which
might bring unexpected behavioural changes.
Fixes: b07911840025 ("net: gmac_rockchip: add support for px30")
Signed-off-by: Pierre-Clément Tosi
Cc: Joe Hershberger
Cc: Heiko Stuebner
Cc: Kever Yang
Cc: Tom Rini
---
drivers/net/gmac_rockchip.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index 04008d2b19..0ecbcdf641 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -350,7 +350,7 @@ static void px30_gmac_set_to_rmii(struct
gmac_rockchip_plat *pdata)
struct px30_grf *grf;
enum {
PX30_GMAC_PHY_INTF_SEL_SHIFT = 4,
- PX30_GMAC_PHY_INTF_SEL_MASK = GENMASK(4, 6),
+ PX30_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4),
PX30_GMAC_PHY_INTF_SEL_RMII = BIT(6),
};
