[PATCH] cmd:Update HELP text of ’askenv’

[opensource . kab]

From: Adarsh Babu Kalepalli 

Help text of ‘askenv’ cmd is updated

Signed-off-by: Adarsh Babu Kalepalli 
---

 cmd/nvedit.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/cmd/nvedit.c b/cmd/nvedit.c
index d14ba10cef..910cf16aaf 100644
--- a/cmd/nvedit.c
+++ b/cmd/nvedit.c
@@ -1569,7 +1569,7 @@ U_BOOT_CMD(
askenv, CONFIG_SYS_MAXARGS, 1,  do_env_ask,
"get environment variables from stdin",
"name [message] [size]\n"
-   "- get environment variable 'name' from stdin (max 'size' chars)"
+   "- display 'message' and get environment variable 'name' from stdin 
(max 'size' chars)"
 );
 #endif
 
-- 
2.17.1

Re: [PATCHv2] drivers: tpm2: update reset gpio semantics

[Jorge Ramirez-Ortiz, Foundries]

On 01/06/21, Michal Simek wrote:
> 
> 
> On 6/1/21 8:09 AM, Jorge Ramirez-Ortiz wrote:
> > Use the more generic reset-gpios propery name.
> > 
> > Signed-off-by: Jorge Ramirez-Ortiz 
> > ---
> >   v2: kept gpio-reset as legacy
> > 
> >  .../tpm2/tis-tpm2-spi.txt |  2 +-
> >  drivers/tpm/tpm2_tis_spi.c| 21 ---
> >  2 files changed, 14 insertions(+), 9 deletions(-)
> > 
> > diff --git a/doc/device-tree-bindings/tpm2/tis-tpm2-spi.txt 
> > b/doc/device-tree-bindings/tpm2/tis-tpm2-spi.txt
> > index 3a2ee4bd17..bbcd12950f 100644
> > --- a/doc/device-tree-bindings/tpm2/tis-tpm2-spi.txt
> > +++ b/doc/device-tree-bindings/tpm2/tis-tpm2-spi.txt
> > @@ -6,7 +6,7 @@ Required properties:
> >  - reg  : SPI Chip select
> >  
> >  Optional properties:
> > -- gpio-reset   : Reset GPIO (if not connected to the SoC reset 
> > line)
> 
> As I said you shouldn't remove this. Just extend description that it is
> deprecated and reset-gpios should be used instead.

I dont really agree with that. IMO we should remove the documentation
since it is obsolete after this commit and anyone reading it should
not care about the gpio-reset property.

> 
> > +- reset-gpios  : Reset GPIO (if not connected to the SoC reset 
> > line)
> >  - spi-max-frequency: See spi-bus.txt
> >  
> >  Example:
> > diff --git a/drivers/tpm/tpm2_tis_spi.c b/drivers/tpm/tpm2_tis_spi.c
> > index 4b33ac8fd3..1f9f89f68f 100644
> > --- a/drivers/tpm/tpm2_tis_spi.c
> > +++ b/drivers/tpm/tpm2_tis_spi.c
> > @@ -589,18 +589,23 @@ static int tpm_tis_spi_probe(struct udevice *dev)
> > if (CONFIG_IS_ENABLED(DM_GPIO)) {
> > struct gpio_desc reset_gpio;
> >  
> > -   ret = gpio_request_by_name(dev, "gpio-reset", 0,
> > +   ret = gpio_request_by_name(dev, "reset-gpios", 0,
> >&reset_gpio, GPIOD_IS_OUT);
> > if (ret) {
> > -   log(LOGC_NONE, LOGL_NOTICE, "%s: missing reset GPIO\n",
> > -   __func__);
> > -   } else {
> > -   dm_gpio_set_value(&reset_gpio, 1);
> > -   mdelay(1);
> > -   dm_gpio_set_value(&reset_gpio, 0);
> > +   /* legacy reset */
> > +   ret = gpio_request_by_name(dev, "gpio-reset", 0,
> > +  &reset_gpio, GPIOD_IS_OUT);
> > +   if (ret) {
> > +   log(LOGC_NONE, LOGL_NOTICE,
> > +   "%s: missing reset GPIO\n",  __func__);
> > +   goto init;
> > +   }
> 
> And here it is clear that gpio-reset is used which should deprecated
> that's why you should print message about it here.

yes, I can do that. makes sense

> 
> 
> > }
> > +   dm_gpio_set_value(&reset_gpio, 1);
> > +   mdelay(1);
> > +   dm_gpio_set_value(&reset_gpio, 0);
> > }
> 
> What about this to remove that goto?

um, what is the problem with the goto (IMO tidier than yet another
conditional); it is not as if this goto is making the code obscure.

with the change below you just removed previous functionality
(ie indicating that there is no GPIO reset provided, hence why at
first sight might look cleaner than a goto)

> 
> ret = gpio_request_by_name(dev, "reset-gpios", 0,
>  &reset_gpio, GPIOD_IS_OUT);
> if (ret) {
>   /* trying legacy reset */
>   ret = gpio_request_by_name(dev, "gpio-reset", 0,
>  &reset_gpio, GPIOD_IS_OUT);
>   if (!ret)
>   log(LOGC_NONE, LOGL_NOTICE,
>   "%s: Using deprecated gpio-reset switch to reset-gpios\n",  
> __func__);
> }
> 
> if (!ret) {
>   dm_gpio_set_value(&reset_gpio, 1);
>   mdelay(1);
>   dm_gpio_set_value(&reset_gpio, 0);
> }
> 
> > -
> > +init:
> > /* Ensure a minimum amount of time elapsed since reset of the TPM */
> > mdelay(drv_data->time_before_first_cmd_ms);
> >  
> > 
> 
> M

Re: [PATCHv2] drivers: tpm2: update reset gpio semantics

[Michal Simek]

On 6/1/21 9:35 AM, Jorge Ramirez-Ortiz, Foundries wrote:
> On 01/06/21, Michal Simek wrote:
>>
>>
>> On 6/1/21 8:09 AM, Jorge Ramirez-Ortiz wrote:
>>> Use the more generic reset-gpios propery name.
>>>
>>> Signed-off-by: Jorge Ramirez-Ortiz 
>>> ---
>>>   v2: kept gpio-reset as legacy
>>>
>>>  .../tpm2/tis-tpm2-spi.txt |  2 +-
>>>  drivers/tpm/tpm2_tis_spi.c| 21 ---
>>>  2 files changed, 14 insertions(+), 9 deletions(-)
>>>
>>> diff --git a/doc/device-tree-bindings/tpm2/tis-tpm2-spi.txt 
>>> b/doc/device-tree-bindings/tpm2/tis-tpm2-spi.txt
>>> index 3a2ee4bd17..bbcd12950f 100644
>>> --- a/doc/device-tree-bindings/tpm2/tis-tpm2-spi.txt
>>> +++ b/doc/device-tree-bindings/tpm2/tis-tpm2-spi.txt
>>> @@ -6,7 +6,7 @@ Required properties:
>>>  - reg  : SPI Chip select
>>>  
>>>  Optional properties:
>>> -- gpio-reset   : Reset GPIO (if not connected to the SoC reset 
>>> line)
>>
>> As I said you shouldn't remove this. Just extend description that it is
>> deprecated and reset-gpios should be used instead.
> 
> I dont really agree with that. IMO we should remove the documentation
> since it is obsolete after this commit and anyone reading it should
> not care about the gpio-reset property.

Run this on linux kernel and you will see that normal style is to keep
it there.
git grep deprecated Documentation/devicetree/bindings

> 
>>
>>> +- reset-gpios  : Reset GPIO (if not connected to the SoC reset 
>>> line)
>>>  - spi-max-frequency: See spi-bus.txt
>>>  
>>>  Example:
>>> diff --git a/drivers/tpm/tpm2_tis_spi.c b/drivers/tpm/tpm2_tis_spi.c
>>> index 4b33ac8fd3..1f9f89f68f 100644
>>> --- a/drivers/tpm/tpm2_tis_spi.c
>>> +++ b/drivers/tpm/tpm2_tis_spi.c
>>> @@ -589,18 +589,23 @@ static int tpm_tis_spi_probe(struct udevice *dev)
>>> if (CONFIG_IS_ENABLED(DM_GPIO)) {
>>> struct gpio_desc reset_gpio;
>>>  
>>> -   ret = gpio_request_by_name(dev, "gpio-reset", 0,
>>> +   ret = gpio_request_by_name(dev, "reset-gpios", 0,
>>>&reset_gpio, GPIOD_IS_OUT);
>>> if (ret) {
>>> -   log(LOGC_NONE, LOGL_NOTICE, "%s: missing reset GPIO\n",
>>> -   __func__);
>>> -   } else {
>>> -   dm_gpio_set_value(&reset_gpio, 1);
>>> -   mdelay(1);
>>> -   dm_gpio_set_value(&reset_gpio, 0);
>>> +   /* legacy reset */
>>> +   ret = gpio_request_by_name(dev, "gpio-reset", 0,
>>> +  &reset_gpio, GPIOD_IS_OUT);
>>> +   if (ret) {
>>> +   log(LOGC_NONE, LOGL_NOTICE,
>>> +   "%s: missing reset GPIO\n",  __func__);
>>> +   goto init;
>>> +   }
>>
>> And here it is clear that gpio-reset is used which should deprecated
>> that's why you should print message about it here.
> 
> yes, I can do that. makes sense
> 
>>
>>
>>> }
>>> +   dm_gpio_set_value(&reset_gpio, 1);
>>> +   mdelay(1);
>>> +   dm_gpio_set_value(&reset_gpio, 0);
>>> }
>>
>> What about this to remove that goto?
> 
> um, what is the problem with the goto (IMO tidier than yet another
> conditional); it is not as if this goto is making the code obscure.
> 
> with the change below you just removed previous functionality
> (ie indicating that there is no GPIO reset provided, hence why at
> first sight might look cleaner than a goto)

I tend to use goto unless there is no way around. But up2you.

M

[PATCH] usb: cdns3: cdns3-ti: Fix clk_get_by_name() to get the correct name

[Aswath Govindraju]

From: Kishon Vijay Abraham I 

Kernel device tree got updated to use clock name as "ref" instead of
"usb2_refclk". Fix cdns3-ti.c to use the correct name.

Fixes: 70e167495ab2 ("arm: dts: k3-j721e: Sync Linux v5.11-rc6 dts into U-Boot")
Fixes: 6239cc8c4e84 ("arm: dts: k3-j7200: Sync Linux v5.11-rc6 dts into U-Boot")
Signed-off-by: Kishon Vijay Abraham I 
Signed-off-by: Aswath Govindraju 
---
 drivers/usb/cdns3/cdns3-ti.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/usb/cdns3/cdns3-ti.c b/drivers/usb/cdns3/cdns3-ti.c
index 7b205c565674..43171678ee17 100644
--- a/drivers/usb/cdns3/cdns3-ti.c
+++ b/drivers/usb/cdns3/cdns3-ti.c
@@ -101,7 +101,7 @@ static int cdns_ti_probe(struct udevice *dev)
if (!data->usbss)
return -EINVAL;
 
-   ret = clk_get_by_name(dev, "usb2_refclk", &usb2_refclk);
+   ret = clk_get_by_name(dev, "ref", &usb2_refclk);
if (ret) {
dev_err(dev, "Failed to get usb2_refclk\n");
return ret;
-- 
2.17.1

Re: [PATCH] usb: cdns3: cdns3-ti: Fix clk_get_by_name() to get the correct name

[Marek Vasut]

On 6/1/21 12:56 PM, Aswath Govindraju wrote:

From: Kishon Vijay Abraham I 

Kernel device tree got updated to use clock name as "ref" instead of
"usb2_refclk". Fix cdns3-ti.c to use the correct name.


Applied, thanks

Re: [RESEND PATCH v2 1/2] rockchip: rk3568: add device tree file

[Kever Yang]

On 2021/5/26 下午5:01, Elaine Zhang wrote:

From: Elaine Zhang 

Add dts binding header for rk3568, files origin from kernel.

Signed-off-by: Elaine Zhang 


Reviewed-by: Kever Yang 

Thanks,
- Kever

---
  include/dt-bindings/clock/rk3568-cru.h | 925 +
  1 file changed, 925 insertions(+)
  create mode 100644 include/dt-bindings/clock/rk3568-cru.h

diff --git a/include/dt-bindings/clock/rk3568-cru.h 
b/include/dt-bindings/clock/rk3568-cru.h
new file mode 100644
index ..c1942422a438
--- /dev/null
+++ b/include/dt-bindings/clock/rk3568-cru.h
@@ -0,0 +1,925 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
+ * Author: Elaine Zhang 
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H
+
+/* pmucru-clocks indices */
+
+/* pmucru plls */
+#define PLL_PPLL   1
+#define PLL_HPLL   2
+
+/* pmucru clocks */
+#define XIN_OSC0_DIV   4
+#define CLK_RTC_32K5
+#define CLK_PMU6
+#define CLK_I2C0   7
+#define CLK_RTC32K_FRAC8
+#define CLK_UART0_DIV  9
+#define CLK_UART0_FRAC 10
+#define SCLK_UART0 11
+#define DBCLK_GPIO012
+#define CLK_PWM0   13
+#define CLK_CAPTURE_PWM0_NDFT  14
+#define CLK_PMUPVTM15
+#define CLK_CORE_PMUPVTM   16
+#define CLK_REF24M 17
+#define XIN_OSC0_USBPHY0_G 18
+#define CLK_USBPHY0_REF19
+#define XIN_OSC0_USBPHY1_G 20
+#define CLK_USBPHY1_REF21
+#define XIN_OSC0_MIPIDSIPHY0_G 22
+#define CLK_MIPIDSIPHY0_REF23
+#define XIN_OSC0_MIPIDSIPHY1_G 24
+#define CLK_MIPIDSIPHY1_REF25
+#define CLK_WIFI_DIV   26
+#define CLK_WIFI_OSC0  27
+#define CLK_WIFI   28
+#define CLK_PCIEPHY0_DIV   29
+#define CLK_PCIEPHY0_OSC0  30
+#define CLK_PCIEPHY0_REF   31
+#define CLK_PCIEPHY1_DIV   32
+#define CLK_PCIEPHY1_OSC0  33
+#define CLK_PCIEPHY1_REF   34
+#define CLK_PCIEPHY2_DIV   35
+#define CLK_PCIEPHY2_OSC0  36
+#define CLK_PCIEPHY2_REF   37
+#define CLK_PCIE30PHY_REF_M38
+#define CLK_PCIE30PHY_REF_N39
+#define CLK_HDMI_REF   40
+#define XIN_OSC0_EDPPHY_G  41
+#define PCLK_PDPMU 42
+#define PCLK_PMU   43
+#define PCLK_UART0 44
+#define PCLK_I2C0  45
+#define PCLK_GPIO0 46
+#define PCLK_PMUPVTM   47
+#define PCLK_PWM0  48
+#define CLK_PDPMU  49
+#define SCLK_32K_IOE   50
+
+#define CLKPMU_NR_CLKS (SCLK_32K_IOE + 1)
+
+/* cru-clocks indices */
+
+/* cru plls */
+#define PLL_APLL   1
+#define PLL_DPLL   2
+#define PLL_CPLL   3
+#define PLL_GPLL   4
+#define PLL_VPLL   5
+#define PLL_NPLL   6
+
+/* cru clocks */
+#define CPLL_333M  9
+#define ARMCLK 10
+#define USB480M11
+#define ACLK_CORE_NIU2BUS  18
+#define CLK_CORE_PVTM  19
+#define CLK_CORE_PVTM_CORE 20
+#define CLK_CORE_PVTPLL21
+#define CLK_GPU_SRC22
+#define CLK_GPU_PRE_NDFT   23
+#define CLK_GPU_PRE_MUX24
+#define ACLK_GPU_PRE   25
+#define PCLK_GPU_PRE   26
+#define CLK_GPU27
+#define CLK_GPU_NP528
+#define PCLK_GPU_PVTM  29
+#define CLK_GPU_PVTM   30
+#define CLK_GPU_PVTM_CORE  31
+#define CLK_GPU_PVTPLL 32
+#define CLK_NPU_SRC33
+#define CLK_NPU_PRE_NDFT   34
+#define CLK_NPU35
+#define CLK_NPU_NP536
+#define HCLK_NPU_PRE   37
+#define PCLK_NPU_PRE   38
+#define ACLK_NPU_PRE   39
+#define ACLK_NPU   40
+#define HCLK_NPU   41
+#define PCLK_NPU_PVTM  42
+#define CLK_NPU_PVTM   43
+#define CLK_NPU_PVTM_CORE  44
+#define CLK_NPU_PVTPLL 45
+#define CLK_DDRPHY1X_SRC   46
+#define CLK_DDRPHY1X_HWFFC_SRC 47
+#define CLK_DDR1X  48
+#define CLK_MSCH   49
+#define CLK24_DDRMON   50
+#define ACLK_GIC_AUDIO 51
+#define HCLK_GIC_AUDIO 52
+#define HCLK_SDMMC_BUFFER  53
+#define DCLK_SDMMC_BUFFER  54
+#define ACLK_GIC60055
+#define ACLK_SPINLOCK  56
+#define HCLK_I2S0_8CH  57
+#define HCLK_I2S1_8CH  58
+#define HCLK_I2S2_2CH  59
+#define HCLK_I2S3_2CH  60
+#define CLK_I2S0_8CH_TX_SRC61
+#define CLK_I2S0_8CH_TX_FRAC   62
+#define MCLK_I2S0_8CH_TX   63
+#define I2S0_MCLKOUT_TX64
+#define CLK_I2S0_8CH_RX_SRC65
+#define CLK_I2S0_8CH_RX_FRAC   66
+#define MCLK_I2S0_8CH_RX   67
+#define I2S0_MCLKOUT_RX68
+#define CLK_I2S1_8CH_TX_SRC69
+#define CLK_I2S1_8CH_TX_FRAC   70
+#define MCLK_I2S1_8CH_TX   

Re: [RESEND PATCH v2 2/2] rockchip: rk3568: add clock driver

[Kever Yang]

On 2021/5/26 下午5:01, Elaine Zhang wrote:

From: Elaine Zhang 

Add rk3568 clock driver and cru structure definition.

Signed-off-by: Elaine Zhang 


Reviewed-by: Kever Yang 

Thanks,
- Kever

---
  .../include/asm/arch-rockchip/cru_rk3568.h|  504 +++
  drivers/clk/rockchip/Makefile |1 +
  drivers/clk/rockchip/clk_rk3568.c | 2959 +
  3 files changed, 3464 insertions(+)
  create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3568.h
  create mode 100644 drivers/clk/rockchip/clk_rk3568.c

diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3568.h 
b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h
new file mode 100644
index ..6c59033f03a6
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h
@@ -0,0 +1,504 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
+ * Author: Elaine Zhang 
+ */
+
+#ifndef _ASM_ARCH_CRU_RK3568_H
+#define _ASM_ARCH_CRU_RK3568_H
+
+#define MHz100
+#define KHz1000
+#define OSC_HZ (24 * MHz)
+
+#define APLL_HZ(816 * MHz)
+#define GPLL_HZ(1188 * MHz)
+#define CPLL_HZ(1000 * MHz)
+#define PPLL_HZ(100 * MHz)
+
+/* RK3568 pll id */
+enum rk3568_pll_id {
+   APLL,
+   DPLL,
+   CPLL,
+   GPLL,
+   NPLL,
+   VPLL,
+   PPLL,
+   HPLL,
+   PLL_COUNT,
+};
+
+struct rk3568_clk_info {
+   unsigned long id;
+   char *name;
+   bool is_cru;
+};
+
+/* Private data for the clock driver - used by rockchip_get_cru() */
+struct rk3568_pmuclk_priv {
+   struct rk3568_pmucru *pmucru;
+   ulong ppll_hz;
+   ulong hpll_hz;
+};
+
+struct rk3568_clk_priv {
+   struct rk3568_cru *cru;
+   struct rk3568_grf *grf;
+   ulong ppll_hz;
+   ulong hpll_hz;
+   ulong gpll_hz;
+   ulong cpll_hz;
+   ulong npll_hz;
+   ulong vpll_hz;
+   ulong armclk_hz;
+   ulong armclk_enter_hz;
+   ulong armclk_init_hz;
+   bool sync_kernel;
+   bool set_armclk_rate;
+};
+
+struct rk3568_pll {
+   unsigned int con0;
+   unsigned int con1;
+   unsigned int con2;
+   unsigned int con3;
+   unsigned int con4;
+   unsigned int reserved0[3];
+};
+
+struct rk3568_pmucru {
+   struct rk3568_pll pll[2];/* Address Offset: 0x */
+   unsigned int reserved0[16];/* Address Offset: 0x0040 */
+   unsigned int mode_con00;/* Address Offset: 0x0080 */
+   unsigned int reserved1[31];/* Address Offset: 0x0084 */
+   unsigned int pmu_clksel_con[10];/* Address Offset: 0x0100 */
+   unsigned int reserved2[22];/* Address Offset: 0x0128 */
+   unsigned int pmu_clkgate_con[3];/* Address Offset: 0x0180 */
+   unsigned int reserved3[29];/* Address Offset: 0x018C */
+   unsigned int pmu_softrst_con[1];/* Address Offset: 0x0200 */
+};
+
+check_member(rk3568_pmucru, mode_con00, 0x80);
+check_member(rk3568_pmucru, pmu_softrst_con[0], 0x200);
+
+struct rk3568_cru {
+   struct rk3568_pll pll[6];
+   unsigned int mode_con00;/* Address Offset: 0x00C0 */
+   unsigned int misc_con[3];/* Address Offset: 0x00C4 */
+   unsigned int glb_cnt_th;/* Address Offset: 0x00D0 */
+   unsigned int glb_srst_fst;/* Address Offset: 0x00D4 */
+   unsigned int glb_srsr_snd; /* Address Offset: 0x00D8 */
+   unsigned int glb_rst_con;/* Address Offset: 0x00DC */
+   unsigned int glb_rst_st;/* Address Offset: 0x00E0 */
+   unsigned int reserved0[7];/* Address Offset: 0x00E4 */
+   unsigned int clksel_con[85]; /* Address Offset: 0x0100 */
+   unsigned int reserved1[43];/* Address Offset: 0x0254 */
+   unsigned int clkgate_con[36];/* Address Offset: 0x0300 */
+   unsigned int reserved2[28]; /* Address Offset: 0x0390 */
+   unsigned int softrst_con[30];/* Address Offset: 0x0400 */
+   unsigned int reserved3[2];/* Address Offset: 0x0478 */
+   unsigned int ssgtbl[32];/* Address Offset: 0x0480 */
+   unsigned int reserved4[32];/* Address Offset: 0x0500 */
+   unsigned int sdmmc0_con[2];/* Address Offset: 0x0580 */
+   unsigned int sdmmc1_con[2];/* Address Offset: 0x058C */
+   unsigned int sdmmc2_con[2];/* Address Offset: 0x0590 */
+   unsigned int emmc_con[2];/* Address Offset: 0x0598 */
+};
+
+check_member(rk3568_cru, mode_con00, 0xc0);
+check_member(rk3568_cru, softrst_con[0], 0x400);
+
+struct pll_rate_table {
+   unsigned long rate;
+   unsigned int fbdiv;
+   unsigned int postdiv1;
+   unsigned int refdiv;
+   unsigned int postdiv2;
+   unsigned int dsmpd;
+   unsigned int frac;
+};
+
+#define RK3568_PMU_MODE0x80
+#define RK3568_PMU_PLL_CON(x)  ((x) * 0x4)
+#define RK3568_PLL_CON(x)  ((x) * 0x4)
+#define RK3568_MODE_CON0xc0
+
+enum {
+   /* CRU_PMU_CLK_SEL0_CON */
+   RTC32K_SEL_SHIFT= 6,
+

Re: [PATCH] rk3399: boot_devices fix spinor node name

[Kever Yang]

Hi Artem,

On 2021/5/26 下午5:32, Artem Lapkin wrote:

Problem: board_spl_was_booted_from return wrong boot_devices[3] value
/spi@ff1d and same-as-spl dont work properly for SPINOR flash
because arch/arm/mach-rockchip/spl-boot-order.c spl_node_to_boot_device
need parse SPINOR flash node as UCLASS_SPI_FLASH

spl-boot-order: same-as-spl > *** BOOT_SOURCE_ID 3 (2:emmc 3:spi 5:sd ...
/spi@ff1d > board_boot_order: could not map node @618 to a boot-device
/sdhci@fe33 > /mmc@fe32

Solution: just change it to /spi@ff1d/flash@0


I don't understand why the solution is add "/flash@0" and why 
"/spi@ff1d " is not work, this drivers should be work for other 
boards before.



Thanks,

- Kever



spl-boot-order: same-as-spl > *** BOOT_SOURCE_ID 3 (2:emmc 3:spi 5:sd ...
/spi@ff1d/flash@0 > /sdhci@fe33 > /mmc@fe32

Signed-off-by: Artem Lapkin 
---
  arch/arm/mach-rockchip/rk3399/rk3399.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c 
b/arch/arm/mach-rockchip/rk3399/rk3399.c
index 869d2159..69e0c8c2 100644
--- a/arch/arm/mach-rockchip/rk3399/rk3399.c
+++ b/arch/arm/mach-rockchip/rk3399/rk3399.c
@@ -28,7 +28,7 @@ DECLARE_GLOBAL_DATA_PTR;
  
  const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {

[BROM_BOOTSOURCE_EMMC] = "/sdhci@fe33",
-   [BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d",
+   [BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d/flash@0",
[BROM_BOOTSOURCE_SD] = "/mmc@fe32",
  };
  

Re: [PATCH] evb_rk3399: add usb ohci definations

[Kever Yang]

Hi Artem,

On 2021/5/26 下午5:33, Artem Lapkin wrote:

Problem: not possible to use CONFIG_USB_OHCI_HCD=y and
CONFIG_USB_OHCI_GENERIC=y options without CONFIG_USB_OHCI_NEW and
CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS definations

Add missed definations.


But , evb_rk3399 board does not enable CONFIG_USB_OHCI_HCD and 
CONFIG_USB_OHCI_GENERIC.



Thanks,

- Kever



Signed-off-by: Artem Lapkin 
---
  include/configs/evb_rk3399.h | 3 +++
  1 file changed, 3 insertions(+)

diff --git a/include/configs/evb_rk3399.h b/include/configs/evb_rk3399.h
index b7e85037..492b7b4d 100644
--- a/include/configs/evb_rk3399.h
+++ b/include/configs/evb_rk3399.h
@@ -15,4 +15,7 @@
  
  #define SDRAM_BANK_SIZE			(2UL << 30)
  
+#define CONFIG_USB_OHCI_NEW

+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+
  #endif

Re: [PATCH] rk3399_common: setup fdtoverlay_addr_r value

[Kever Yang]

On 2021/5/26 下午5:34, Artem Lapkin wrote:

fdtoverlay (pxe_utils) require define fdtoverlay_addr_r env variable
for example sunxi-common.h meson64.h already have it.

Signed-off-by: Artem Lapkin 



Reviewed-by: Kever Yang 

Thanks,
- Kever

---
  include/configs/rk3399_common.h | 1 +
  1 file changed, 1 insertion(+)

diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
index f0be3830..13d15b1f 100644
--- a/include/configs/rk3399_common.h
+++ b/include/configs/rk3399_common.h
@@ -51,6 +51,7 @@
"script_size_f=0x2000\0" \
"pxefile_addr_r=0x0060\0" \
"fdt_addr_r=0x01f0\0" \
+   "fdtoverlay_addr_r=0x0200\0" \
"kernel_addr_r=0x0208\0" \
"ramdisk_addr_r=0x0600\0" \
"kernel_comp_addr_r=0x0800\0" \

Re: [RFC 0/5] rockchip_sfc: add support for Rockchip SFC

[Kever Yang]

Add Yifeng from rockchip.

Hi Chris,

    First of all, I think you should remain the origin author info in 
the signed-off.



Hi Yifeng,

    Please help to review this driver.


Thanks,

- Kever

On 2021/5/26 上午5:49, Chris Morgan wrote:

From: Chris Morgan 

Requesting comments for a proposed patchset for adding the Rockchip
serial flash controller to u-boot. The goal of these patches is to
enable it for the Odroid Go Advance so that it may eventually boot
exclusively from the SFC on mainline U-boot (I have tested this and
it works).

The specific help I need with this patch is:

1) I don't know the best way to upstream the XTX25F128B flash chip.
This chip uses a continuation code for the manufacturer ID, however I
cannot seem to find any way to actually read the continuation code.
There is a risk of this driver, used as-is, to collide with another
chip which has the same manufacturer ID with a different continuation
code.

2) The Rockchip SFC driver itself (as it is mostly as-is from the BSP
U-Boot sources) supports SPI NAND and chips of varying sizes, but my
implementation only permits me to test with a single 128Mb flash chip.
The driver itself does some checking on the bitlen in the routine
rockchip_sfc_xfer() which is what is called for the dm_spi_ops.xfer.
I'm not sure if there is a better way to do this. Additionally, I have
to bit-shift the address written to the SFC as I suspect the value is
meant to be left justified, but I never tested it further.

Additionally, it might be worth mentioning but I noticed the Rockchip
BROM will only boot the TPL/SPL off of the SFC if I write it to address
0x1. This is not documented and different than the address looked
at for SD card booting (512 * 64 = 0x8000 for SD Card booting). Also,
like the SD card driver I can confirm that if DMA is enabled at the SPL
stage A-TF seems to fail silently, then when Linux loads it hangs.
There is an ifdef to force FIFO mode only in the SPL stage.

Tested: Read (works)
Write (works if you write to an erased sector)
Erase (works)
SPL Read (works if you edit the u-boot,spl-boot-order)

Chris Morgan (5):
   spi: rockchip_sfc: add support for Rockchip SFC
   rockchip: px30: Add support for using SFC
   rockchip: px30: add the serial flash controller
   mtd: spi-nor-ids: Add XTX XT25F128B
   rockchip: px30: add support for SFC for Odroid Go Advance

  arch/arm/dts/px30.dtsi |  38 ++
  arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi |  10 +-
  arch/arm/dts/rk3326-odroid-go2.dts |  22 +
  arch/arm/mach-rockchip/px30/px30.c |  64 ++
  drivers/mtd/spi/Kconfig|   6 +
  drivers/mtd/spi/spi-nor-ids.c  |   8 +
  drivers/spi/Kconfig|   8 +
  drivers/spi/Makefile   |   1 +
  drivers/spi/rockchip_sfc.c | 652 +
  9 files changed, 926 insertions(+), 1 deletion(-)
  create mode 100644 drivers/spi/rockchip_sfc.c

Re: [PATCH v2 1/7] arm: a37xx: pci: Don't put link into LTSSM Recovery state during probe

[Pali Rohár]

On Thursday 27 May 2021 08:19:32 Stefan Roese wrote:
> On 26.05.21 17:59, Pali Rohár wrote:
> > During our debugging of the Aardvark driver in Linux we have discovered
> > that the PCIE_CORE_LINK_CTRL_STAT_REG register in fact controls standard
> > PCIe Link Control Register for PCIe Root Bridge. This led us to discover
> > that the name of the PCIE_CORE_LINK_TRAINING macro and the corresponding
> > comment by this macro's usage is misleading; this bit in fact controls
> > Retrain Link, which, according to PCIe base spec is defined as:
> > 
> >A write of 1b to this bit initiates Link retraining by directing the
> >Physical Layer LTSSM to the Recovery state. If the LTSSM is already in
> >Recovery or Configuration, re-entering Recovery is permitted but not
> >required.
> > 
> > Entering Recovery state is normally done from LTSSM L0, L0s and L1 states.
> > But since the pci-aardvark.c driver enables Link Training just a few lines
> > above, the controller is not in L0 ready state yet. So setting aardvark bit
> > PCIE_CORE_LINK_TRAINING does not actually enter Recovery state at this
> > place.
> > 
> > Moreover, trying to enter LTSSM Recovery state without other configuration
> > is causing issues for some cards (e.g. Atheros AR9xxx and QCA9xxx). Since
> > Recovery state is not entered, these issues are not triggered.
> > 
> > Remove code which tries to enter LTSSM Recovery state completely.
> > 
> > Signed-off-by: Pali Rohár 
> > Reviewed-by: Marek Behún 
> 
> Reviewed-by: Stefan Roese 
> 
> Thanks,
> Stefan

Hello Stefan! Thank you for review. Would you be sending these A3720
patches to 2021.07 version?

> > ---
> >   drivers/pci/pci-aardvark.c | 5 -
> >   1 file changed, 5 deletions(-)
> > 
> > diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
> > index c43d4f309b19..06c567e236f9 100644
> > --- a/drivers/pci/pci-aardvark.c
> > +++ b/drivers/pci/pci-aardvark.c
> > @@ -613,11 +613,6 @@ static int pcie_advk_setup_hw(struct pcie_advk *pcie)
> > reg |= PIO_CTRL_ADDR_WIN_DISABLE;
> > advk_writel(pcie, reg, PIO_CTRL);
> > -   /* Start link training */
> > -   reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG);
> > -   reg |= PCIE_CORE_LINK_TRAINING;
> > -   advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
> > -
> > /* Wait for PCIe link up */
> > if (pcie_advk_wait_for_link(pcie))
> > return -ENXIO;
> > 
> 
> 
> Viele Grüße,
> Stefan
> 
> -- 
> DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de

Re: [PATCH u-boot v4 00/36] U-Boot LTO (Sandbox + Some ARM boards)

[Patrick DELAUNAY]

Hi Marek,

On 5/20/21 1:23 PM, Marek Behún wrote:

Hello,

this is version 4 of patches adding support for LTO to U-Boot.

This series is being tested by Github/Azure CI at
   https://github.com/u-boot/u-boot/pull/57

There is a problem with sandbox_clang test scenario, which I was
unable to resolve yet, or even determine correctly whether the
problem is with my patches or was there before. (One of the
problems is with testing stack protector test_stackprotector.py,
but for some reason I could not make this work even with GCC on
my local machine.)
Nevertheless I am sending these patches now so that at least you
can review them. In the meantime I will try to resolve the issue
with sandbox_clang test scenario.

Changes since v3:
- for some reason the mvneta driver does not work correctly when
   U-Boot is compiled with LTO. I have not debugged this issue yet, so
   for now I have removed Turris Omnia and Turris MOX from devices with
   enabled LTO
- linker list entry symbols are now forced to emit by using the
   __ADDRESSABLE macro in a generated C file (keep-syms-lto.c).
   Previously this was done in the ll_entry_declare() macro, but this
   was not flexible, since, for example, trying to declare an entry as
   extern could not work that way. This came to attention now after
   Simon's patches for dtoc were merged, and ll_entry_declare() is
   being used with the extern keyword in include/generated/dt-decl.h
- when compiling LTO with Clang, use llvm-ar and llvm-nm for AR and NM
- several patches rebased
- removed patch "api: fix a potential serious bug caused by undef
   CONFIG_SYS_64BIT_LBA"
- updated patch converting __attribute__((section(...))) to
   __section(...)

Changes sinve v2:
- now linking with --build-id=none in order to avoid link failures with
   some toolchains (thanks Herald Seiler)
- we don't use -flto=jobserver anymore, since it causes build errors for
   some people. Instead we link with -flto=NPROC
- removed LTO exception for arch/arm/mach-omap2/omap3/clock.o, Adam Ford
   says it is not needed
- added some Reviewed-by tags

Changes since v1:
- remove patches applied into u-boot-marvell
- added Reviewed-by tags
- addressed some issues discovered by Bin Meng, Marek Vasut,
   Heinrich Schuchardt
- added more ARM boards (thanks to Adam Ford, Tim Harvey and Bin Meng)
- removed --gc-sections for ARM if internal libgcc is used
- remove -fwhole-program in final LTO LDFLAGS
- declared all 4 functions (memcpy, memset, memcmp, memmove) __used,
   (these are mentioned in GCC man page for option -nodefaultlibs that
the compiler may generate; this seems to be a bug in GCC that linking
fails with LTO even if these functions are present, because the
symbols can be renamed on some targets by optimization)

Marek

Marek Behún (36):
   regmap: fix a serious pointer casting bug
   checkpatch: require quotes around section name in the __section()
 macro
   treewide: Convert macro and uses of __section(foo) to __section("foo")
   compiler.h: align the __ADDRESSABLE macro with Linux' version
   test/py: improve regular expression for ut subtest symbol matcher
   string: make memcpy(), memset(), memcmp() and memmove() visible for
 LTO
   efi_loader: fix warning when linking with LTO
   efi_loader: add Sphinx doc for __efi_runtime and __efi_runtime_data
   efi_loader: add macro for const EFI runtime data
   efi_selftest: compiler flags for efi_selftest_miniapp_exception.o
   lib: crc32: put the crc_table variable into efi_runtime_rodata section
   Makefile, Makefile.spl: cosmetic change
   build: use thin archives instead of incremental linking
   build: support building with Link Time Optimizations
   build: link with --build-id=none
   sandbox: errno: avoid conflict with libc's errno
   sandbox: use sections instead of symbols for getopt array boundaries
   sandbox: make LTO available
   sandbox: enable LTO by default
   ARM: global_data: make set_gd() work for armv5 and armv6
   ARM: make gd a function call for LTO and set via set_gd()
   ARM: fix LTO build for some thumb-interwork cases
   ARM: fix LTO for imx28_xea
   ARM: fix LTO for apf27
   ARM: fix LTO for keystone
   ARM: kona: fix clk_bsc_enable() type mismatch for LTO
   ARM: imx8m: fix imx_eqos_txclk_set_rate() type mismatch for LTO
   ARM: fix LTO for seaboard
   ARM: fix LTO for rockchip and samsung
   ARM: omap3: fix LTO for DM3730 (and possibly other omap3 boards)
   armv8: SPL: discard relocation information
   ata: ahci: fix ahci_link_up() type mismatch for LTO
   ARM: make LTO available
   ARM: don't use -ffunction-sections/-fdata-sections with LTO build
   ARM: don't use --gc-sections with LTO when using private libgcc
   ARM: enable LTO for some boards

  Kbuild |  2 +
  Kconfig| 24 +++
  Makefile   | 81 --
  arch/Kconfig   |  3 +
  arch/arm/config.mk

Re: [PATCH v4 5/5] ARM: dts: stm32mp: Add OP-TEE reserved memory to SPL dtb

[Patrick DELAUNAY]

Hi,

On 5/31/21 7:43 PM, Alexandru Gagniuc wrote:

Add the "/reserved-memory/optee" node to the SPL devicetree. The
purpose is to allow configuring TZC regions when booting OP-TEE.

Signed-off-by: Alexandru Gagniuc 
Reviewed-by: Simon Glass 
---
  arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 3 +++
  1 file changed, 3 insertions(+)

diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi 
b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
index 67876192900..55d634f7db2 100644
--- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
+++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi
@@ -30,9 +30,12 @@
};
  
  	reserved-memory {

+   u-boot,dm-spl;
+
optee@de00 {
reg = <0xde00 0x0200>;
no-map;
+   u-boot,dm-spl;
};
};
  


Reviewed-by: Patrick Delaunay 

Thanks
Patrick

Re: [PATCH u-boot v4 00/36] U-Boot LTO (Sandbox + Some ARM boards)

[Tom Rini]

On Tue, Jun 01, 2021 at 04:59:52PM +0200, Patrick DELAUNAY wrote:
> Hi Marek,
> 
> On 5/20/21 1:23 PM, Marek Behún wrote:
> > Hello,
> > 
> > this is version 4 of patches adding support for LTO to U-Boot.
> > 
> > This series is being tested by Github/Azure CI at
> >https://github.com/u-boot/u-boot/pull/57
> > 
> > There is a problem with sandbox_clang test scenario, which I was
> > unable to resolve yet, or even determine correctly whether the
> > problem is with my patches or was there before. (One of the
> > problems is with testing stack protector test_stackprotector.py,
> > but for some reason I could not make this work even with GCC on
> > my local machine.)
> > Nevertheless I am sending these patches now so that at least you
> > can review them. In the meantime I will try to resolve the issue
> > with sandbox_clang test scenario.
> > 
> > Changes since v3:
> > - for some reason the mvneta driver does not work correctly when
> >U-Boot is compiled with LTO. I have not debugged this issue yet, so
> >for now I have removed Turris Omnia and Turris MOX from devices with
> >enabled LTO
> > - linker list entry symbols are now forced to emit by using the
> >__ADDRESSABLE macro in a generated C file (keep-syms-lto.c).
> >Previously this was done in the ll_entry_declare() macro, but this
> >was not flexible, since, for example, trying to declare an entry as
> >extern could not work that way. This came to attention now after
> >Simon's patches for dtoc were merged, and ll_entry_declare() is
> >being used with the extern keyword in include/generated/dt-decl.h
> > - when compiling LTO with Clang, use llvm-ar and llvm-nm for AR and NM
> > - several patches rebased
> > - removed patch "api: fix a potential serious bug caused by undef
> >CONFIG_SYS_64BIT_LBA"
> > - updated patch converting __attribute__((section(...))) to
> >__section(...)
> > 
> > Changes sinve v2:
> > - now linking with --build-id=none in order to avoid link failures with
> >some toolchains (thanks Herald Seiler)
> > - we don't use -flto=jobserver anymore, since it causes build errors for
> >some people. Instead we link with -flto=NPROC
> > - removed LTO exception for arch/arm/mach-omap2/omap3/clock.o, Adam Ford
> >says it is not needed
> > - added some Reviewed-by tags
> > 
> > Changes since v1:
> > - remove patches applied into u-boot-marvell
> > - added Reviewed-by tags
> > - addressed some issues discovered by Bin Meng, Marek Vasut,
> >Heinrich Schuchardt
> > - added more ARM boards (thanks to Adam Ford, Tim Harvey and Bin Meng)
> > - removed --gc-sections for ARM if internal libgcc is used
> > - remove -fwhole-program in final LTO LDFLAGS
> > - declared all 4 functions (memcpy, memset, memcmp, memmove) __used,
> >(these are mentioned in GCC man page for option -nodefaultlibs that
> > the compiler may generate; this seems to be a bug in GCC that linking
> > fails with LTO even if these functions are present, because the
> > symbols can be renamed on some targets by optimization)
> > 
> > Marek
> > 
> > Marek Behún (36):
> >regmap: fix a serious pointer casting bug
> >checkpatch: require quotes around section name in the __section()
> >  macro
> >treewide: Convert macro and uses of __section(foo) to __section("foo")
> >compiler.h: align the __ADDRESSABLE macro with Linux' version
> >test/py: improve regular expression for ut subtest symbol matcher
> >string: make memcpy(), memset(), memcmp() and memmove() visible for
> >  LTO
> >efi_loader: fix warning when linking with LTO
> >efi_loader: add Sphinx doc for __efi_runtime and __efi_runtime_data
> >efi_loader: add macro for const EFI runtime data
> >efi_selftest: compiler flags for efi_selftest_miniapp_exception.o
> >lib: crc32: put the crc_table variable into efi_runtime_rodata section
> >Makefile, Makefile.spl: cosmetic change
> >build: use thin archives instead of incremental linking
> >build: support building with Link Time Optimizations
> >build: link with --build-id=none
> >sandbox: errno: avoid conflict with libc's errno
> >sandbox: use sections instead of symbols for getopt array boundaries
> >sandbox: make LTO available
> >sandbox: enable LTO by default
> >ARM: global_data: make set_gd() work for armv5 and armv6
> >ARM: make gd a function call for LTO and set via set_gd()
> >ARM: fix LTO build for some thumb-interwork cases
> >ARM: fix LTO for imx28_xea
> >ARM: fix LTO for apf27
> >ARM: fix LTO for keystone
> >ARM: kona: fix clk_bsc_enable() type mismatch for LTO
> >ARM: imx8m: fix imx_eqos_txclk_set_rate() type mismatch for LTO
> >ARM: fix LTO for seaboard
> >ARM: fix LTO for rockchip and samsung
> >ARM: omap3: fix LTO for DM3730 (and possibly other omap3 boards)
> >armv8: SPL: discard relocation information
> >ata: ahci: fix ahci_link_up() type mismatch for LTO
> >ARM: 

[PATCH 00/10] AM642-EVM: Add USB support

[Aswath Govindraju]

The following series of patches add support for the following
- Kconfig symbol for giving the load address for ATF
- USB Mass storrage boot mode in AM642-EVM
- DFU boot mode in AM642-EVM
- Host and peripheral modes for AM642-EVM in U-Boot
- Set the USB PHY core voltage to 0.85V

Aswath Govindraju (10):
  tools: k3_fit_atf: Add support for providing ATF load address using a
Kconfig symbol
  arm: mach-k3: am642_init: Add support for USB boot mode
  arm: mach-k3: am642_init: Do USB fixups to facilitate host and device
boot modes
  board: ti: am64x: Set the core voltage of USB PHY to 0.85V
  arm: dts: k3-am64-main: Add USB DT nodes
  arm: dts: k3-am642-*-evm: Add USB support
  arm: dts: k3-am642-evm-u-boot: Add U-Boot tags and fix the dr_mode to
peripheral for USB subsystem
  configs: am64x_evm_*_defconfig: Move the SPL Load address to
0x7000, move the ATF to a latter location and rearrange EEPROM
and BSS data
  arm: dts: k3-am64-main: Update the location of ATF in SRAM
  configs: am64: Enable configs to support USB host and device modes

 arch/arm/dts/k3-am64-main.dtsi| 32 -
 arch/arm/dts/k3-am642-evm-u-boot.dtsi | 13 ++
 arch/arm/dts/k3-am642-evm.dts | 18 
 arch/arm/dts/k3-am642-r5-evm.dts  | 18 
 arch/arm/mach-k3/Kconfig  |  7 +++
 arch/arm/mach-k3/am642_init.c | 46 ++-
 arch/arm/mach-k3/config.mk|  1 +
 arch/arm/mach-k3/include/mach/am64_hardware.h | 11 +++--
 arch/arm/mach-k3/include/mach/am64_spl.h  |  6 ++-
 board/ti/am64x/evm.c  | 14 ++
 configs/am64x_evm_a53_defconfig   | 40 
 configs/am64x_evm_r5_defconfig| 38 +--
 include/configs/am64x_evm.h   | 15 +-
 tools/k3_fit_atf.sh   |  9 ++--
 14 files changed, 251 insertions(+), 17 deletions(-)

-- 
2.17.1

[PATCH 01/10] tools: k3_fit_atf: Add support for providing ATF load address using a Kconfig symbol

[Aswath Govindraju]

Add support for providing ATF load address with a Kconfig symbol.

Signed-off-by: Aswath Govindraju 
---
 arch/arm/mach-k3/Kconfig   | 7 +++
 arch/arm/mach-k3/config.mk | 1 +
 tools/k3_fit_atf.sh| 9 ++---
 3 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index bfbce44bfa59..2c46d7a3a798 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -147,6 +147,13 @@ config SYS_K3_SPL_ATF
  Enabling this will try to start Cortex-A (typically with ATF)
  after SPL from R5.
 
+config K3_ATF_LOAD_ADDR
+   hex "Load address of ATF image"
+   default 0x700
+   help
+ The load address for the ATF image. This value defaults to 0x7000
+ if not provided in the board defconfig file.
+
 source "board/ti/am65x/Kconfig"
 source "board/ti/am64x/Kconfig"
 source "board/ti/j721e/Kconfig"
diff --git a/arch/arm/mach-k3/config.mk b/arch/arm/mach-k3/config.mk
index 41fee2b5a172..674489068204 100644
--- a/arch/arm/mach-k3/config.mk
+++ b/arch/arm/mach-k3/config.mk
@@ -67,6 +67,7 @@ endif
 quiet_cmd_k3_mkits = MKITS   $@
 cmd_k3_mkits = \
$(srctree)/tools/k3_fit_atf.sh \
+   $(CONFIG_K3_ATF_LOAD_ADDR) \
$(patsubst %,$(obj)/dts/%.dtb,$(subst ",,$(LIST_OF_DTB))) > $@
 
 $(SPL_ITS): FORCE
diff --git a/tools/k3_fit_atf.sh b/tools/k3_fit_atf.sh
index 4e9f69c08789..2c0287a63394 100755
--- a/tools/k3_fit_atf.sh
+++ b/tools/k3_fit_atf.sh
@@ -5,7 +5,7 @@
 # ATF, OPTEE, SPL and multiple device trees (given on the command line).
 # Inspired from board/sunxi/mksunxi_fit_atf.sh
 #
-# usage: $0  [ [  [ [;
-   entry = <0x7000>;
+   load = <$1>;
+   entry = <$1>;
};
tee {
description = "OPTEE";
@@ -65,6 +65,9 @@ cat << __HEADER_EOF
};
 __HEADER_EOF
 
+# shift through ATF load address in the command line arguments
+shift
+
 for dtname in $*
 do
cat << __FDT_IMAGE_EOF
-- 
2.17.1

[PATCH 02/10] arm: mach-k3: am642_init: Add support for USB boot mode

[Aswath Govindraju]

Add support for identifying USB host and device boot modes

Signed-off-by: Aswath Govindraju 
---
 arch/arm/mach-k3/am642_init.c | 13 +++--
 arch/arm/mach-k3/include/mach/am64_hardware.h |  5 +
 arch/arm/mach-k3/include/mach/am64_spl.h  |  6 --
 3 files changed, 20 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c
index a433702b4e30..1a2bc4bb9048 100644
--- a/arch/arm/mach-k3/am642_init.c
+++ b/arch/arm/mach-k3/am642_init.c
@@ -192,8 +192,11 @@ static u32 __get_backup_bootmedia(u32 main_devstat)
case BACKUP_BOOT_DEVICE_UART:
return BOOT_DEVICE_UART;
 
-   case BACKUP_BOOT_DEVICE_USB:
-   return BOOT_DEVICE_USB;
+   case BACKUP_BOOT_DEVICE_DFU:
+   if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE_MASK)
+   return BOOT_DEVICE_USB;
+   return BOOT_DEVICE_DFU;
+
 
case BACKUP_BOOT_DEVICE_ETHERNET:
return BOOT_DEVICE_ETHERNET;
@@ -245,6 +248,12 @@ static u32 __get_primary_bootmedia(u32 main_devstat)
return BOOT_DEVICE_MMC2;
return BOOT_DEVICE_MMC1;
 
+   case BOOT_DEVICE_DFU:
+   if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK) >>
+   MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT)
+   return BOOT_DEVICE_USB;
+   return BOOT_DEVICE_DFU;
+
case BOOT_DEVICE_NOBOOT:
return BOOT_DEVICE_RAM;
}
diff --git a/arch/arm/mach-k3/include/mach/am64_hardware.h 
b/arch/arm/mach-k3/include/mach/am64_hardware.h
index c368aa7e6bf1..4ee41ad762ba 100644
--- a/arch/arm/mach-k3/include/mach/am64_hardware.h
+++ b/arch/arm/mach-k3/include/mach/am64_hardware.h
@@ -30,6 +30,11 @@
 #define MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT2
 #define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK 0x04
 
+#define MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT1
+#define MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK 0x02
+
+#define MAIN_DEVSTAT_BACKUP_USB_MODE_MASK  0x01
+
 /*
  * The CTRL_MMR and PADCFG_MMR memory space is divided into several
  * equally-spaced partitions, so defining the partition size allows us to
diff --git a/arch/arm/mach-k3/include/mach/am64_spl.h 
b/arch/arm/mach-k3/include/mach/am64_spl.h
index 36826cfc4ed0..607b09c2e5dc 100644
--- a/arch/arm/mach-k3/include/mach/am64_spl.h
+++ b/arch/arm/mach-k3/include/mach/am64_spl.h
@@ -19,7 +19,8 @@
 #define BOOT_DEVICE_MMC0x08
 #define BOOT_DEVICE_EMMC   0x09
 
-#define BOOT_DEVICE_USB0x0A
+#define BOOT_DEVICE_USB0x2A
+#define BOOT_DEVICE_DFU0x0A
 #define BOOT_DEVICE_GPMC_NOR   0x0C
 #define BOOT_DEVICE_PCIE   0x0D
 #define BOOT_DEVICE_XSPI   0x0E
@@ -32,12 +33,13 @@
 #define BOOT_DEVICE_MMC2_2 0x1F
 
 /* Backup BootMode devices */
-#define BACKUP_BOOT_DEVICE_USB 0x01
+#define BACKUP_BOOT_DEVICE_DFU 0x01
 #define BACKUP_BOOT_DEVICE_UART0x03
 #define BACKUP_BOOT_DEVICE_ETHERNET0x04
 #define BACKUP_BOOT_DEVICE_MMC 0x05
 #define BACKUP_BOOT_DEVICE_SPI 0x06
 #define BACKUP_BOOT_DEVICE_I2C 0x07
+#define BACKUP_BOOT_DEVICE_USB 0x09
 
 #define K3_PRIMARY_BOOTMODE0x0
 
-- 
2.17.1

[PATCH 03/10] arm: mach-k3: am642_init: Do USB fixups to facilitate host and device boot modes

[Aswath Govindraju]

U-Boot either supports USB host or device mode for a node at a time in the
device tree nodes. To support both host and dfu bootmodes, dr_mode is set
to "peripheral" by default and then fixed based on the mode selected by
the boot mode config dip switches on the board.

This needs to happen before the cdns3 generic layer binds the usb device
to a host or a device driver. Therefore, use fdtdec_setup_board()
implementation to fixup the device tree property.

Signed-off-by: Aswath Govindraju 
---
 arch/arm/mach-k3/am642_init.c | 33 +
 1 file changed, 33 insertions(+)

diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c
index 1a2bc4bb9048..579dbacb7e48 100644
--- a/arch/arm/mach-k3/am642_init.c
+++ b/arch/arm/mach-k3/am642_init.c
@@ -8,6 +8,7 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -106,6 +107,38 @@ void do_dt_magic(void)
 }
 #endif
 
+#if CONFIG_IS_ENABLED(USB_STORAGE)
+static int fixup_usb_boot(const void *fdt_blob)
+{
+   int ret = 0;
+
+   switch (spl_boot_device()) {
+   case BOOT_DEVICE_USB:
+   /*
+* If the boot mode is host, fixup the dr_mode to host
+* before cdns3 bind takes place
+*/
+   ret = fdt_find_and_setprop((void *)fdt_blob,
+  
"/bus@f4000/cdns-usb@f90/usb@f40",
+  "dr_mode", "host", 5, 0);
+   if (ret)
+   printf("%s: fdt_find_and_setprop() failed:%d\n",
+  __func__, ret);
+   fallthrough;
+   default:
+   break;
+   }
+
+   return ret;
+}
+
+int fdtdec_board_setup(const void *fdt_blob)
+{
+   /* Can use the pointer from the function parameters */
+   return fixup_usb_boot(fdt_blob);
+}
+#endif
+
 void board_init_f(ulong dummy)
 {
 #if defined(CONFIG_K3_LOAD_SYSFW)
-- 
2.17.1

[PATCH 04/10] board: ti: am64x: Set the core voltage of USB PHY to 0.85V

[Aswath Govindraju]

Set the core voltage of USB PHY in AM64x to 0.85V in spl_board_init().

Signed-off-by: Aswath Govindraju 
---
 board/ti/am64x/evm.c | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/board/ti/am64x/evm.c b/board/ti/am64x/evm.c
index 35cd9e027c04..cdbb9a87bc44 100644
--- a/board/ti/am64x/evm.c
+++ b/board/ti/am64x/evm.c
@@ -152,3 +152,17 @@ int board_late_init(void)
return 0;
 }
 #endif
+
+#define CTRLMMR_USB0_PHY_CTRL  0x43004008
+#define CORE_VOLTAGE   0x8000
+
+#ifdef CONFIG_SPL_BOARD_INIT
+void spl_board_init(void)
+{
+   u32 val;
+   /* Set USB PHY core voltage to 0.85V */
+   val = readl(CTRLMMR_USB0_PHY_CTRL);
+   val &= ~(CORE_VOLTAGE);
+   writel(val, CTRLMMR_USB0_PHY_CTRL);
+}
+#endif
-- 
2.17.1

[PATCH 05/10] arm: dts: k3-am64-main: Add USB DT nodes

[Aswath Govindraju]

Add DT node for the single USB subsystem in main dtsi file.

Signed-off-by: Aswath Govindraju 
---
 arch/arm/dts/k3-am64-main.dtsi | 30 ++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm/dts/k3-am64-main.dtsi b/arch/arm/dts/k3-am64-main.dtsi
index a65011b396cc..5a58337c1ca7 100644
--- a/arch/arm/dts/k3-am64-main.dtsi
+++ b/arch/arm/dts/k3-am64-main.dtsi
@@ -499,6 +499,36 @@
clock-names = "gpio";
};
 
+   usbss0: cdns-usb@f90{
+   compatible = "ti,am64-usb", "ti,j721e-usb";
+   reg = <0x00 0xf90 0x00 0x100>;
+   power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
+   clocks = <&k3_clks 161 9>, <&k3_clks 161 1>;
+   clock-names = "ref", "lpm";
+   assigned-clocks = <&k3_clks 161 9>; /* USB2_REFCLK */
+   assigned-clock-parents = <&k3_clks 161 10>; /* HF0SC0 */
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges;
+   usb0: usb@f40{
+   compatible = "cdns,usb3";
+   reg = <0x00 0xf40 0x00 0x1>,
+ <0x00 0xf41 0x00 0x1>,
+ <0x00 0xf42 0x00 0x1>;
+   reg-names = "otg",
+   "xhci",
+   "dev";
+   interrupts = , /* 
irq.0 */
+, /* 
irq.6 */
+; /* 
otgirq */
+   interrupt-names = "host",
+ "peripheral",
+ "otg";
+   maximum-speed = "super-speed";
+   dr_mode = "otg";
+   };
+   };
+
main_gpio1: gpio@601000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x00 0x00601000 0x00 0x100>;
-- 
2.17.1

[PATCH 06/10] arm: dts: k3-am642-*-evm: Add USB support

[Aswath Govindraju]

AM64 EVM board has a micro USB 2.0 AB connector and the USB0_VBUS is
connected with a resistor divider in between. USB0_DRVVBUS pin is muxed
between USB0_DRVVBUS and GPIO1_79 signals.

Add the corresponding properties and set the pinmux mode for USB subsystem
in the evm dts file.

Signed-off-by: Aswath Govindraju 
---
 arch/arm/dts/k3-am642-evm.dts| 18 ++
 arch/arm/dts/k3-am642-r5-evm.dts | 18 ++
 2 files changed, 36 insertions(+)

diff --git a/arch/arm/dts/k3-am642-evm.dts b/arch/arm/dts/k3-am642-evm.dts
index dc3482bea433..3a505d22c635 100644
--- a/arch/arm/dts/k3-am642-evm.dts
+++ b/arch/arm/dts/k3-am642-evm.dts
@@ -201,6 +201,12 @@
AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) 
PRG1_PRU1_GPO15.RGMII2_TX_CTL */
>;
};
+
+   main_usb0_pins_default: main-usb0-pins-default {
+   pinctrl-single,pins = <
+   AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) 
USB0_DRVVBUS */
+   >;
+   };
 };
 
 &main_uart0 {
@@ -337,3 +343,15 @@
ti,driver-strength-ohm = <50>;
disable-wp;
 };
+
+&usbss0 {
+   ti,vbus-divider;
+   ti,usb2-only;
+};
+
+&usb0 {
+   dr_mode = "otg";
+   maximum-speed = "high-speed";
+   pinctrl-names = "default";
+   pinctrl-0 = <&main_usb0_pins_default>;
+};
diff --git a/arch/arm/dts/k3-am642-r5-evm.dts b/arch/arm/dts/k3-am642-r5-evm.dts
index 1fbf6d2c23a5..cc48fd4cb607 100644
--- a/arch/arm/dts/k3-am642-r5-evm.dts
+++ b/arch/arm/dts/k3-am642-r5-evm.dts
@@ -141,6 +141,12 @@
AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7)   /* 
(L18) OSPI0_CSN1.GPIO0_12 */
>;
};
+
+   main_usb0_pins_default: main-usb0-pins-default {
+   pinctrl-single,pins = <
+   AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) 
USB0_DRVVBUS */
+   >;
+   };
 };
 
 &dmsc {
@@ -201,4 +207,16 @@
/delete-property/ power-domains;
 };
 
+&usbss0 {
+   ti,vbus-divider;
+   ti,usb2-only;
+};
+
+&usb0 {
+   dr_mode = "otg";
+   maximum-speed = "high-speed";
+   pinctrl-names = "default";
+   pinctrl-0 = <&main_usb0_pins_default>;
+};
+
 #include "k3-am642-evm-u-boot.dtsi"
-- 
2.17.1

[PATCH 07/10] arm: dts: k3-am642-evm-u-boot: Add U-Boot tags and fix the dr_mode to peripheral for USB subsystem

[Aswath Govindraju]

Add U-Boot tags and fix the dr_mode as peripheral in U-Boot to support DFU
by default.

Signed-off-by: Aswath Govindraju 
---
 arch/arm/dts/k3-am642-evm-u-boot.dtsi | 13 +
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/dts/k3-am642-evm-u-boot.dtsi 
b/arch/arm/dts/k3-am642-evm-u-boot.dtsi
index 10dea7a1cc46..ed38b7269ee5 100644
--- a/arch/arm/dts/k3-am642-evm-u-boot.dtsi
+++ b/arch/arm/dts/k3-am642-evm-u-boot.dtsi
@@ -50,6 +50,19 @@
u-boot,dm-spl;
 };
 
+&usb0 {
+   dr_mode="peripheral";
+   u-boot,dm-spl;
+};
+
+&usbss0 {
+   u-boot,dm-spl;
+};
+
+&main_usb0_pins_default {
+   u-boot,dm-spl;
+};
+
 &dmss {
u-boot,dm-spl;
 };
-- 
2.17.1

[PATCH 08/10] configs: am64x_evm_*_defconfig: Move the SPL Load address to 0x70000000, move the ATF to a latter location and rearrange EEPROM and BSS data

[Aswath Govindraju]

For USB DFU boot mode there is a limitation on the load address of boot
images that they have to be less than 0x70001000. Therefore, move the
SPL_TEXT_BASE address to 0x7000.

Currently ATF is being loaded at 0x7000, if the SPL is being loaded at
0x7000 then ATF would overwrite SPL image when loaded. Therefore, move
the location of ATF to a latter location in SRAM, past the SPL image. Also
rearrange the EEPROM and BSS data on top of ATF.

Given below is the placement of various data sections in SRAM

 ┌──┐0x7000
 │  │
 │  │
 │  │
 │SPL IMAGE (Max size 1.5 MB)   │
 │  │
 │  │
 │  │
 ├──┤0x7017
 │  │
 │   SPL STACK  │
 │  │
 ├──┤0x70192727
 │  GLOBAL DATA(216 B)  │
 ├──┤0x701927FF
 │  │
 │   INITIAL HEAP (32 KB)   │
 │  │
 ├──┤0x7019A7FF
 │  │
 │  BSS  (20 KB)│
 ├──┤0x7019F7FF
 │ EEPROM DATA (2 KB)   │
 ├──┤0x7019
 │  │
 │  │
 │ATF (123 KB)  │
 │  │
 │  │
 ├──┤0x701BEBFB
 │   BOOT PARAMETER INDEX TABLE (5124 B)│
 ├──┤0x701B
 │  │
 │SYSFW FIREWALLED DUE TO A BUG (128 KB)│
 │  │
 ├──┤0x701D
 │  │
 │  DMSC CODE AREA (128 KB) │
 │  │
 └──┘0x701F

Signed-off-by: Aswath Govindraju 
---
 arch/arm/mach-k3/include/mach/am64_hardware.h | 6 ++
 configs/am64x_evm_a53_defconfig   | 1 +
 configs/am64x_evm_r5_defconfig| 2 +-
 include/configs/am64x_evm.h   | 3 ++-
 4 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-k3/include/mach/am64_hardware.h 
b/arch/arm/mach-k3/include/mach/am64_hardware.h
index 4ee41ad762ba..96383437d5b1 100644
--- a/arch/arm/mach-k3/include/mach/am64_hardware.h
+++ b/arch/arm/mach-k3/include/mach/am64_hardware.h
@@ -7,8 +7,6 @@
 #ifndef __ASM_ARCH_AM64_HARDWARE_H
 #define __ASM_ARCH_AM64_HARDWARE_H
 
-#include 
-
 #define CTRL_MMR0_BASE 0x4300
 #define CTRLMMR_MAIN_DEVSTAT   (CTRL_MMR0_BASE + 0x30)
 
@@ -54,7 +52,7 @@
 
 #define ROM_ENTENDED_BOOT_DATA_INFO0x701beb00
 
-/* Use Last 1K as Scratch pad */
-#define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x701bfc00
+/* Use Last 2K as Scratch pad */
+#define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x7019f800
 
 #endif /* __ASM_ARCH_DRA8_HARDWARE_H */
diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig
index 304f5b41a3ae..3b8b7474f845 100644
--- a/configs/am64x_evm_a53_defconfig
+++ b/configs/am64x_evm_a53_defconfig
@@ -5,6 +5,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_SOC_K3_AM642=y
+CONFIG_K3_ATF_LOAD_ADDR=0x701a
 CONFIG_TARGET_AM642_A53_EVM=y
 CONFIG_ENV_SIZE=0x2
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x28
diff --git a/configs/am64x_evm_r5_defconfig b/configs/am64x_evm_r5_defconfig
index 2810fa1fc57d..de0c814222c0 100644
--- a/configs/am64x_evm_r5_defconfig
+++ b/configs/am64x_evm_r5_defconfig
@@ -10,7 +10,7 @@ CONFIG_ENV_SIZE=0x2
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x8
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
-CONFIG_SPL_TEXT_BASE=0x7002
+CONFIG_SPL_TEXT_BASE=0x7000
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h
index 7c30e50c5f1e..7c9bdc2d7d3a 100644
--- a/include/configs/am64x_evm.h
+++ b/include/configs/am64x_evm.h
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 
 /* DDR Configuration */
 #define CONFIG_SYS_SDRAM_BASE1 0x88000
@@ -43,7 +44,7 @@
  * location filled in by the boot ROM that we want to read out without any
  * interference from the C context.
  */
-#define CON

[PATCH 09/10] arm: dts: k3-am64-main: Update the location of ATF in SRAM

[Aswath Govindraju]

For USB DFU boot mode there is a limitation on the load address of boot
images that they have to be less than 0x70001000. So, the load address of
SPL has been moved to 0x7000 and ATF has been moved to a latter
location, 0x701a.

Therefore, update its location accordingly in the device tree file.

Signed-off-by: Aswath Govindraju 
---
 arch/arm/dts/k3-am64-main.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/k3-am64-main.dtsi b/arch/arm/dts/k3-am64-main.dtsi
index 5a58337c1ca7..fccf0d2fcfb0 100644
--- a/arch/arm/dts/k3-am64-main.dtsi
+++ b/arch/arm/dts/k3-am64-main.dtsi
@@ -14,7 +14,7 @@
ranges = <0x0 0x00 0x7000 0x20>;
 
atf-sram@0 {
-   reg = <0x0 0x1a000>;
+   reg = <0x1a 0x1a000>;
};
};
 
-- 
2.17.1

[PATCH 10/10] configs: am64: Enable configs to support USB host and device modes

[Aswath Govindraju]

Enable config options required to add support for USB Mass storage boot,
USB DFU boot, host and device modes in U-Boot.

Signed-off-by: Aswath Govindraju 
---
 configs/am64x_evm_a53_defconfig | 39 +
 configs/am64x_evm_r5_defconfig  | 36 --
 include/configs/am64x_evm.h | 12 +-
 3 files changed, 84 insertions(+), 3 deletions(-)

diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig
index 3b8b7474f845..a3aab807c6e7 100644
--- a/configs/am64x_evm_a53_defconfig
+++ b/configs/am64x_evm_a53_defconfig
@@ -23,6 +23,7 @@ CONFIG_DEFAULT_DEVICE_TREE="k3-am642-evm"
 CONFIG_DISTRO_DEFAULTS=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x8100
 CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run 
get_kern_${boot}; run get_fdt_${boot}; run run_kern"
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
@@ -30,12 +31,17 @@ CONFIG_SPL_STACK_R=y
 CONFIG_SPL_SEPARATE_BSS=y
 CONFIG_SPL_DMA=y
 CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_DM_MAILBOX=y
 CONFIG_SPL_DM_SPI_FLASH=y
 CONFIG_SPL_POWER_DOMAIN=y
 CONFIG_SPL_RAM_SUPPORT=y
 CONFIG_SPL_RAM_DEVICE=y
 CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_STORAGE=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_DFU=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
@@ -103,3 +109,36 @@ CONFIG_TIMER=y
 CONFIG_SPL_TIMER=y
 CONFIG_OMAP_TIMER=y
 CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
+CONFIG_CMD_DFU=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_USB=y
+CONFIG_DFU=y
+CONFIG_DFU_OVER_USB=y
+# CONFIG_DFU_TFTP is not set
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+# CONFIG_DFU_VIRT is not set
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x4
+CONFIG_SYS_DFU_MAX_FILE_SIZE=0x80
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB_HOST=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_SPL_USB_CDNS3_GADGET=y
+CONFIG_USB_CDNS3_HOST=y
+CONFIG_SPL_USB_CDNS3_HOST=y
+CONFIG_USB_CDNS3_TI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0451
+CONFIG_USB_GADGET_PRODUCT_NUM=0x6165
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_MASS_STORAGE=y
diff --git a/configs/am64x_evm_r5_defconfig b/configs/am64x_evm_r5_defconfig
index de0c814222c0..3e9b5650c60d 100644
--- a/configs/am64x_evm_r5_defconfig
+++ b/configs/am64x_evm_r5_defconfig
@@ -23,6 +23,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_DEFAULT_DEVICE_TREE="k3-am642-r5-evm"
 CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x8008
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
 CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
@@ -31,19 +32,30 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_SEPARATE_BSS=y
 CONFIG_SPL_EARLY_BSS=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_DM_MAILBOX=y
 CONFIG_SPL_DM_SPI_FLASH=y
 CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_POWER_SUPPORT=y
 CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
 CONFIG_SPL_REMOTEPROC=y
 CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_STORAGE=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_DFU=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
+CONFIG_CMD_DFU=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_REMOTEPROC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TIME=y
 CONFIG_CMD_FAT=y
@@ -52,8 +64,6 @@ CONFIG_SPL_OF_CONTROL=y
 CONFIG_SPL_MULTI_DTB_FIT=y
 CONFIG_SPL_OF_LIST="k3-am642-r5-evm k3-am642-r5-sk"
 CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
-CONFIG_ENV_IS_IN_FAT=y
-CONFIG_ENV_FAT_DEVICE_AND_PART="1:1"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_DM=y
 CONFIG_SPL_DM=y
@@ -64,6 +74,10 @@ CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
 CONFIG_CLK_TI_SCI=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x5000
 CONFIG_TI_SCI_PROTOCOL=y
 CONFIG_DA8XX_GPIO=y
 CONFIG_DM_I2C=y
@@ -101,4 +115,22 @@ CONFIG_CADENCE_QSPI=y
 CONFIG_TIMER=y
 CONFIG_SPL_TIMER=y
 CONFIG_OMAP_TIMER=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_SPL_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_SPL_USB_CDNS3_GADGET=y
+CONFIG_USB_CDNS3_HOST=y
+CONFIG_SPL_USB_CDNS3_HOST=y
+CONFIG_USB_CDNS3_TI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0451
+CONFIG_USB_GADGET_PRODUCT_NUM=0x6165
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h
index 7c9bdc2d7d3a..c2c2bf06777c 100644
--- a/include/configs/am64x_evm.h
+++ b/include/configs/

Re: [PATCH] net: dwc_eth_qos: Fix needless phy auto-negotiation restarts

[Patrick DELAUNAY]

Hi,

On 5/24/21 12:24 AM, Daniil Stas wrote:

Disabling clk_ck clock leads to link up status loss in phy, which
leads to auto-negotiation restart before each network command
execution.

This issue is especially big for PXE boot protocol because of
auto-negotiation restarts before each configuration filename trial.

To avoid this issue don't disable clk_ck clock after it was enabled.

Signed-off-by: Daniil Stas 
Cc: Ramon Fried 
Cc: Joe Hershberger 
Cc: Patrick Delaunay 
Cc: Patrice Chotard 
---
  drivers/net/dwc_eth_qos.c | 6 +++---
  1 file changed, 3 insertions(+), 3 deletions(-)


Reviewed-by: Patrick Delaunay 

Thanks
Patrick

Re: [PATCH] spi: stm32_qspi: Fix short data write operation

[Patrick DELAUNAY]

Hi,

On 5/24/21 12:24 AM, Daniil Stas wrote:

TCF flag only means that all data was sent to FIFO. To check if the
data was sent out of FIFO we should also wait for the BUSY flag to be
cleared. Otherwise there is a race condition which can lead to
inability to write short (one byte long) data.

Signed-off-by: Daniil Stas 
Cc: Patrick Delaunay 
Cc: Patrice Chotard 
---
  drivers/spi/stm32_qspi.c | 29 +++--
  1 file changed, 15 insertions(+), 14 deletions(-)



Reviewed-by: Patrick Delaunay 

Thanks
Patrick

[PATCH v3] usb: dfu: Migrate CONFIG_SYS_DFU_DATA_BUF_SIZE and CONFIG_SYS_DFU_MAX_FILE_SIZE to Kconfig

[Aswath Govindraju]

Currently the config options CONFIG_SYS_DFU_DATA_BUF_SIZE and
CONFIG_SYS_DFU_MAX_FILE_SIZE are being set in include/configs/.h
files and also in _defconfig files without a Kconfig option. It
is easier for users to set these configs in defconfig files than in config
header files as they are a part of the source code.

Add Kconfig symbols, and update the defconfigs by using tools/moveconfig.py
script.

Suggested-by: Pratyush Yadav 
Signed-off-by: Aswath Govindraju 
Acked-by: Oleksandr Suvorov 
---

Changes since v2:
- Rebased the patch on top of current HEAD
- Picked up Oleksandr Suvorov's Acked-by

Link to v2 patch,
https://patchwork.ozlabs.org/project/uboot/patch/20210226071849.29070-1-a-govindr...@ti.com/

Changes since v1:
- Removed CONFIG_SYS_DFU_MAX_FILE_SIZE in defconfig files, where it was
  not defined previously. The list of files in which this change is made
  are listed below,
  configs/colibri-imx6ull_defconfig
  configs/colibri_vf_defconfig
  configs/corvus_defconfig
  configs/dh_imx6_defconfig
  configs/draco_defconfig
  configs/etamin_defconfig 
  configs/odroid-xu3_defconfig
  configs/odroid_defconfig
  configs/origen_defconfig
  configs/pico-dwarf-imx6ul_defconfig
  configs/pico-hobbit-imx6ul_defconfig
  configs/pico-imx6_defconfig
  configs/pico-imx6ul_defconfig
  configs/pico-pi-imx6ul_defconfig
  configs/pxm2_defconfig
  configs/rastaban_defconfig 
  configs/rut_defconfig
  configs/s5p_goni_defconfig
  configs/s5pc210_universal_defconfig
  configs/smartweb_defconfig  
  configs/socfpga_arria5_defconfig
  configs/socfpga_cyclone5_defconfig
  configs/socfpga_dbm_soc1_defconfig
  configs/socfpga_de0_nano_soc_defconfig
  configs/socfpga_de10_nano_defconfig 
  configs/socfpga_mcvevk_defconfig
  configs/socfpga_sockit_defconfig
  configs/socfpga_socrates_defconfig
  configs/socfpga_vining_fpga_defconfig
  configs/taurus_defconfig
  configs/thuban_defconfig
  configs/topic_miami_defconfig
  configs/topic_miamilite_defconfig
  configs/topic_miamiplus_defconfig 
  configs/trats2_defconfig 
  configs/trats_defconfig
  configs/warp7_bl33_defconfig
  configs/warp7_defconfig
  configs/warp_defconfig
  configs/xilinx_versal_virt_defconfig
  configs/xilinx_zynq_virt_defconfig
  configs/xilinx_zynqmp_virt_defconfig

Link to v1,
https://patchwork.ozlabs.org/project/uboot/patch/20210223061427.20742-1-a-govindr...@ti.com/
 

 configs/am65x_evm_a53_defconfig   |  2 ++
 configs/am65x_evm_r5_usbdfu_defconfig |  2 ++
 configs/am65x_hs_evm_a53_defconfig|  2 ++
 configs/beaver_defconfig  |  2 ++
 configs/cei-tk1-som_defconfig |  2 ++
 configs/colibri-imx6ull_defconfig |  1 +
 configs/colibri_vf_defconfig  |  1 +
 configs/corvus_defconfig  |  1 +
 configs/dalmore_defconfig |  2 ++
 configs/dh_imx6_defconfig |  1 +
 configs/draco_defconfig   |  1 +
 configs/etamin_defconfig  |  1 +
 configs/jetson-tk1_defconfig  |  2 ++
 configs/nyan-big_defconfig|  2 ++
 configs/odroid-xu3_defconfig  |  1 +
 configs/odroid_defconfig  |  1 +
 configs/origen_defconfig  |  1 +
 configs/p2371-_defconfig  |  2 ++
 configs/p2371-2180_defconfig  |  2 ++
 configs/p2571_defconfig   |  2 ++
 configs/p3450-_defconfig  |  2 ++
 configs/pico-dwarf-imx6ul_defconfig   |  1 +
 configs/pico-hobbit-imx6ul_defconfig  |  1 +
 configs/pico-imx6_defconfig   |  1 +
 configs/pico-imx6ul_defconfig |  1 +
 configs/pico-pi-imx6ul_defconfig  |  1 +
 configs/pxm2_defconfig|  1 +
 configs/rastaban_defconfig|  1 +
 configs/rpi_4_32b_defconfig   |  2 ++
 configs/rpi_4_defconfig   |  2 ++
 configs/rut_defconfig |  1 +
 configs/s5p_goni_defconfig|  1 +
 configs/s5pc210_universal_defconfig   |  1 +
 configs/smartweb_defconfig|  1 +
 configs/socfpga_arria5_defconfig  |  1 +
 configs/socfpga_cyclone5_defconfig|  1 +
 configs/socfpga_dbm_soc1_defconfig|  1 +
 configs/socfpga_de0_nano_soc_defconfig|  1 +
 configs/socfpga_de10_nano_defconfig   |  1 +
 configs/socfpga_mcvevk_defconfig  |  1 +
 configs/socfpga_sockit_defconfig  |  1 +
 configs/socfpga_socrates_defconfig|  1 +
 configs/socfpga_vining_fpga_defconfig |  1 +
 configs/taurus_defconfig  |  1 +
 configs/thuban_defconfig  |  1 +
 configs/topic_miami_defconfig |  1 +
 configs/topic_miamilite_defconfig |  1 +
 configs/topic_miamiplus_defconfig |  1 +
 configs/trats2_defconfig  |  1 +
 configs/trats_defconfig   |  1 +
 configs/venice2_defconfig |  2 ++
 configs/warp7_bl33_defconfig  |  1 +
 configs/warp7_de

Re: [[PATCH] colibri_imx6: add board_fit_config_name_match to support FIT in SPL

[Ming Liu]

Hi, Sean:

Thanks for the comments, please see my answers as follows:

> Please use an errno.

Seems all other board are using '0' and '-1' as return value of
board_fit_config_name_match, shouldn't we keep consistent with them?

> Do you need to match "imx6-colibri", or could you use the default config?

I think so since imx6-colibri.its is the only present DTS file for this
board.

//Ming Liu




Sean Anderson  於 2021年5月31日 週一 下午4:36寫道：

> On 5/31/21 3:06 AM, liu.min...@gmail.com wrote:
> > From: Ming Liu 
> >
> > Only one dtb is currently supported, so match with imx6-colibri.
> >
> > Signed-off-by: Ming Liu 
> > ---
> >   board/toradex/colibri_imx6/colibri_imx6.c | 10 ++
> >   1 file changed, 10 insertions(+)
> >
> > diff --git a/board/toradex/colibri_imx6/colibri_imx6.c
> b/board/toradex/colibri_imx6/colibri_imx6.c
> > index c0e7754469..587d92a8e9 100644
> > --- a/board/toradex/colibri_imx6/colibri_imx6.c
> > +++ b/board/toradex/colibri_imx6/colibri_imx6.c
> > @@ -1081,6 +1081,16 @@ void board_init_f(ulong dummy)
> >   board_init_r(NULL, 0);
> >   }
> >
> > +#ifdef CONFIG_SPL_LOAD_FIT
> > +int board_fit_config_name_match(const char *name)
> > +{
> > + if (!strcmp(name, "imx6-colibri"))
> > + return 0;
> > +
> > + return -1;
>
> Please use an errno.
>
> > +}
> > +#endif
> > +
> >   void reset_cpu(void)
> >   {
> >   }
> >
>
> Do you need to match "imx6-colibri", or could you use the default config?
>
> --Sean
>

Re: [[PATCH] colibri_imx6: add board_fit_config_name_match to support FIT in SPL

[Ming Liu]

Hi, Marcel:

Thanks for the comment, I usually dont send twice for a same PR, but I was
not a member when I sent the first one so I was afraid it's not on the mail
list.

//Ming Liu

Sean Anderson  於 2021年5月31日 週一 下午4:36寫道：

> On 5/31/21 3:06 AM, liu.min...@gmail.com wrote:
> > From: Ming Liu 
> >
> > Only one dtb is currently supported, so match with imx6-colibri.
> >
> > Signed-off-by: Ming Liu 
> > ---
> >   board/toradex/colibri_imx6/colibri_imx6.c | 10 ++
> >   1 file changed, 10 insertions(+)
> >
> > diff --git a/board/toradex/colibri_imx6/colibri_imx6.c
> b/board/toradex/colibri_imx6/colibri_imx6.c
> > index c0e7754469..587d92a8e9 100644
> > --- a/board/toradex/colibri_imx6/colibri_imx6.c
> > +++ b/board/toradex/colibri_imx6/colibri_imx6.c
> > @@ -1081,6 +1081,16 @@ void board_init_f(ulong dummy)
> >   board_init_r(NULL, 0);
> >   }
> >
> > +#ifdef CONFIG_SPL_LOAD_FIT
> > +int board_fit_config_name_match(const char *name)
> > +{
> > + if (!strcmp(name, "imx6-colibri"))
> > + return 0;
> > +
> > + return -1;
>
> Please use an errno.
>
> > +}
> > +#endif
> > +
> >   void reset_cpu(void)
> >   {
> >   }
> >
>
> Do you need to match "imx6-colibri", or could you use the default config?
>
> --Sean
>

Re: [PATCH 00/10] AM642-EVM: Add USB support

[Aswath Govindraju]

Hi all,

On 01/06/21 8:43 pm, Aswath Govindraju wrote:
> The following series of patches add support for the following
> - Kconfig symbol for giving the load address for ATF
> - USB Mass storrage boot mode in AM642-EVM
> - DFU boot mode in AM642-EVM
> - Host and peripheral modes for AM642-EVM in U-Boot
> - Set the USB PHY core voltage to 0.85V
> 

Patch 9 is dependent on,
https://patchwork.ozlabs.org/project/uboot/patch/20210601112147.10253-1-a-govindr...@ti.com/

Thanks,
Aswath

> Aswath Govindraju (10):
>   tools: k3_fit_atf: Add support for providing ATF load address using a
> Kconfig symbol
>   arm: mach-k3: am642_init: Add support for USB boot mode
>   arm: mach-k3: am642_init: Do USB fixups to facilitate host and device
> boot modes
>   board: ti: am64x: Set the core voltage of USB PHY to 0.85V
>   arm: dts: k3-am64-main: Add USB DT nodes
>   arm: dts: k3-am642-*-evm: Add USB support
>   arm: dts: k3-am642-evm-u-boot: Add U-Boot tags and fix the dr_mode to
> peripheral for USB subsystem
>   configs: am64x_evm_*_defconfig: Move the SPL Load address to
> 0x7000, move the ATF to a latter location and rearrange EEPROM
> and BSS data
>   arm: dts: k3-am64-main: Update the location of ATF in SRAM
>   configs: am64: Enable configs to support USB host and device modes
> 
>  arch/arm/dts/k3-am64-main.dtsi| 32 -
>  arch/arm/dts/k3-am642-evm-u-boot.dtsi | 13 ++
>  arch/arm/dts/k3-am642-evm.dts | 18 
>  arch/arm/dts/k3-am642-r5-evm.dts  | 18 
>  arch/arm/mach-k3/Kconfig  |  7 +++
>  arch/arm/mach-k3/am642_init.c | 46 ++-
>  arch/arm/mach-k3/config.mk|  1 +
>  arch/arm/mach-k3/include/mach/am64_hardware.h | 11 +++--
>  arch/arm/mach-k3/include/mach/am64_spl.h  |  6 ++-
>  board/ti/am64x/evm.c  | 14 ++
>  configs/am64x_evm_a53_defconfig   | 40 
>  configs/am64x_evm_r5_defconfig| 38 +--
>  include/configs/am64x_evm.h   | 15 +-
>  tools/k3_fit_atf.sh   |  9 ++--
>  14 files changed, 251 insertions(+), 17 deletions(-)
> 

Re: [PATCH u-boot v4 00/36] U-Boot LTO (Sandbox + Some ARM boards)

[Marek Behún]

On Tue, 1 Jun 2021 16:59:52 +0200
Patrick DELAUNAY  wrote:

> Hi Marek,
> 
> I am trying to activate CONFIG_LTO for STMicroelectronics stm32mp15 
> platform
> 
> (stm32mp15_trusted_defconfig and stm32mp15_basic_defconfig).
> 
> 
> The config stm32mp15_basic_defconfig, with SPL supported failed to
> boot
> 
> with gcc-arm-9.2-2019.12.
> 
> because a weak function is not correctly handle between
> 
> 1/ ./arch/arm/lib/cache-cp15.c: 96
> 
>      __weak void dram_bank_mmu_setup(int bank);
> 
> 2/ the stm32mp implementation in
> 
>     arch/arm/mach-stm32mp/cpu.c:62
> 
>     void dram_bank_mmu_setup(int bank)
> 
> => The used function in SPL is the cache library, not the stm32mp
> function.  
> 
>    and SPL boot it OK when I remove the function in the cache
> library...
> 
> 
> And the issue is also solved with I use a more recent version
> 
> gcc-arm-10.2-2020.11 on my PC.
> 
> 
> Do you see the same kind of issue for old version of gcc ?
> 
> 
> Do you think CONFIG_LTO require a more recent version of gcc that
> 
> the minimal version required by U-Boot  because I don't see this 
> information
> 
> in the serie?

I only tried compiling with older versions in the CI.

On the devices for which I tested it I only compiled with newer gcc
(10.2.0) since it is the stable version on my system.

But yeah, I suggest to use newer GCC for LTO.

Marek

Re: [PATCH] cmd:Update HELP text of ’askenv’

[Heinrich Schuchardt]

On 6/1/21 9:09 AM, opensource@gmail.com wrote:

From: Adarsh Babu Kalepalli 

Help text of ‘askenv’ cmd is updated

Signed-off-by: Adarsh Babu Kalepalli 
---

  cmd/nvedit.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/cmd/nvedit.c b/cmd/nvedit.c
index d14ba10cef..910cf16aaf 100644
--- a/cmd/nvedit.c
+++ b/cmd/nvedit.c
@@ -1569,7 +1569,7 @@ U_BOOT_CMD(
askenv, CONFIG_SYS_MAXARGS, 1,  do_env_ask,
"get environment variables from stdin",
"name [message] [size]\n"
-   "- get environment variable 'name' from stdin (max 'size' chars)"
+   "- display 'message' and get environment variable 'name' from stdin (max 
'size' chars)"



Hello Ardash,

thanks for looking for a better description.

This online help does not correctly describe the command syntax yet
which is:

askenv name [message ...] [size]

=> askenv foo
Please enter 'foo': abcdefgh
=> echo $foo
abcdefgh
=>

=> askenv foo 4
Please enter 'foo': abcdefgh
=> echo $foo
abcd
=>

=> askenv foo msg1 msg2 msg3 3
msg1 msg2 msg3 abcdefgh
=> echo $foo
abc
=>

=> askenv foo msg1 msg2 msg3
msg1 msg2 msg3 abcdefgh
=> echo $foo
abcdefgh
=>

The logic needs some explanation. The last parameter is used as size if
it can be converted to a decimal number. In most other commands we
expect a hexadecimal number.

We started adding man-pages for all commands to doc/usage/. Do you want
to give it a try?

Best regards

Heinrich


  );
  #endif

Re: [PATCH u-boot v4 00/36] U-Boot LTO (Sandbox + Some ARM boards)

[Heinrich Schuchardt]

On 6/1/21 6:22 PM, Marek Behún wrote:

On Tue, 1 Jun 2021 16:59:52 +0200
Patrick DELAUNAY  wrote:


Hi Marek,

I am trying to activate CONFIG_LTO for STMicroelectronics stm32mp15
platform

(stm32mp15_trusted_defconfig and stm32mp15_basic_defconfig).


The config stm32mp15_basic_defconfig, with SPL supported failed to
boot

with gcc-arm-9.2-2019.12.

because a weak function is not correctly handle between

1/ ./arch/arm/lib/cache-cp15.c: 96

      __weak void dram_bank_mmu_setup(int bank);

2/ the stm32mp implementation in

     arch/arm/mach-stm32mp/cpu.c:62

     void dram_bank_mmu_setup(int bank)

=> The used function in SPL is the cache library, not the stm32mp
function.

    and SPL boot it OK when I remove the function in the cache
library...


And the issue is also solved with I use a more recent version

gcc-arm-10.2-2020.11 on my PC.


Do you see the same kind of issue for old version of gcc ?


Do you think CONFIG_LTO require a more recent version of gcc that

the minimal version required by U-Boot  because I don't see this
information

in the serie?


I only tried compiling with older versions in the CI.

On the devices for which I tested it I only compiled with newer gcc
(10.2.0) since it is the stable version on my system.

But yeah, I suggest to use newer GCC for LTO.

Marek



gcc (Debian 11-20210327-1) 11.0.1 compiles stm32mp15_basic_defconfig
with CONFIG_LTO=y.

Best regards

Heinrich

Re: [PATCH u-boot v4 00/36] U-Boot LTO (Sandbox + Some ARM boards)

[Tom Rini]

On Tue, Jun 01, 2021 at 06:55:52PM +0200, Heinrich Schuchardt wrote:
> On 6/1/21 6:22 PM, Marek Behún wrote:
> > On Tue, 1 Jun 2021 16:59:52 +0200
> > Patrick DELAUNAY  wrote:
> > 
> > > Hi Marek,
> > > 
> > > I am trying to activate CONFIG_LTO for STMicroelectronics stm32mp15
> > > platform
> > > 
> > > (stm32mp15_trusted_defconfig and stm32mp15_basic_defconfig).
> > > 
> > > 
> > > The config stm32mp15_basic_defconfig, with SPL supported failed to
> > > boot
> > > 
> > > with gcc-arm-9.2-2019.12.
> > > 
> > > because a weak function is not correctly handle between
> > > 
> > > 1/ ./arch/arm/lib/cache-cp15.c: 96
> > > 
> > >       __weak void dram_bank_mmu_setup(int bank);
> > > 
> > > 2/ the stm32mp implementation in
> > > 
> > >      arch/arm/mach-stm32mp/cpu.c:62
> > > 
> > >      void dram_bank_mmu_setup(int bank)
> > > 
> > > => The used function in SPL is the cache library, not the stm32mp
> > > function.
> > > 
> > >     and SPL boot it OK when I remove the function in the cache
> > > library...
> > > 
> > > 
> > > And the issue is also solved with I use a more recent version
> > > 
> > > gcc-arm-10.2-2020.11 on my PC.
> > > 
> > > 
> > > Do you see the same kind of issue for old version of gcc ?
> > > 
> > > 
> > > Do you think CONFIG_LTO require a more recent version of gcc that
> > > 
> > > the minimal version required by U-Boot  because I don't see this
> > > information
> > > 
> > > in the serie?
> > 
> > I only tried compiling with older versions in the CI.
> > 
> > On the devices for which I tested it I only compiled with newer gcc
> > (10.2.0) since it is the stable version on my system.
> > 
> > But yeah, I suggest to use newer GCC for LTO.
> > 
> > Marek
> > 
> 
> gcc (Debian 11-20210327-1) 11.0.1 compiles stm32mp15_basic_defconfig
> with CONFIG_LTO=y.

It's run-time not compile time that shows the problem however as gcc-9.x
sounds like it has a problem with LTO and weak functions.

-- 
Tom


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Re: [PATCH] cmd:Update HELP text of ’askenv’

[Adarsh Babu Kalepalli]

Hi Heinrich,

> thanks for looking for a better description.

> This online help does not correctly describe the command syntax yet
> which is:
Was trying to keep the command HELP text(on the shell ) simple and mention
the available parameters.


> The logic needs some explanation. The last parameter is used as size if
> it can be converted to a decimal number. In most other commands we
> expect a hexadecimal number.

> We started adding man-pages for all commands to doc/usage/. Do you want
> to give it a try?
Sure.

I am trying to review the HELP text of the shell commands and improve them
(if need be).
In this process, do you recommend following any specific approach ??

Regards,
Adarsh

On Tue, 1 Jun 2021 at 22:12, Heinrich Schuchardt  wrote:

> On 6/1/21 9:09 AM, opensource@gmail.com wrote:
> > From: Adarsh Babu Kalepalli 
> >
> > Help text of ‘askenv’ cmd is updated
> >
> > Signed-off-by: Adarsh Babu Kalepalli 
> > ---
> >
> >   cmd/nvedit.c | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/cmd/nvedit.c b/cmd/nvedit.c
> > index d14ba10cef..910cf16aaf 100644
> > --- a/cmd/nvedit.c
> > +++ b/cmd/nvedit.c
> > @@ -1569,7 +1569,7 @@ U_BOOT_CMD(
> >   askenv, CONFIG_SYS_MAXARGS, 1,  do_env_ask,
> >   "get environment variables from stdin",
> >   "name [message] [size]\n"
> > - "- get environment variable 'name' from stdin (max 'size'
> chars)"
> > + "- display 'message' and get environment variable 'name' from
> stdin (max 'size' chars)"
>
>
> Hello Ardash,
>
> thanks for looking for a better description.
>
> This online help does not correctly describe the command syntax yet
> which is:
>
> askenv name [message ...] [size]
>
> => askenv foo
> Please enter 'foo': abcdefgh
> => echo $foo
> abcdefgh
> =>
>
> => askenv foo 4
> Please enter 'foo': abcdefgh
> => echo $foo
> abcd
> =>
>
> => askenv foo msg1 msg2 msg3 3
> msg1 msg2 msg3 abcdefgh
> => echo $foo
> abc
> =>
>
> => askenv foo msg1 msg2 msg3
> msg1 msg2 msg3 abcdefgh
> => echo $foo
> abcdefgh
> =>
>
> The logic needs some explanation. The last parameter is used as size if
> it can be converted to a decimal number. In most other commands we
> expect a hexadecimal number.
>
> We started adding man-pages for all commands to doc/usage/. Do you want
> to give it a try?
>
> Best regards
>
> Heinrich
>
> >   );
> >   #endif
> >
> >
>

Re: [PATCH v2] fastboot: Fix overflow when calculating chunk size

[Tom Rini]

On Thu, May 27, 2021 at 12:02:34PM -0400, Sean Anderson wrote:

> If a chunk was larger than 4GiB, then chunk_data_sz would overflow and
> blkcnt would not be calculated correctly. Upgrade it to a u64 and cast
> its multiplicands as well. Also fix bytes_written while we're at it.
> 
> Signed-off-by: Sean Anderson 
> Reviewed-by: Heiko Schocher 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [PATCH v3] usb: dfu: Migrate CONFIG_SYS_DFU_DATA_BUF_SIZE and CONFIG_SYS_DFU_MAX_FILE_SIZE to Kconfig

[Matthias Brugger]

On 01/06/2021 13:21, Aswath Govindraju wrote:
> Currently the config options CONFIG_SYS_DFU_DATA_BUF_SIZE and
> CONFIG_SYS_DFU_MAX_FILE_SIZE are being set in include/configs/.h
> files and also in _defconfig files without a Kconfig option. It
> is easier for users to set these configs in defconfig files than in config
> header files as they are a part of the source code.
> 
> Add Kconfig symbols, and update the defconfigs by using tools/moveconfig.py
> script.
> 
> Suggested-by: Pratyush Yadav 
> Signed-off-by: Aswath Govindraju 
> Acked-by: Oleksandr Suvorov 

For Raspberry Pi parts:
Acked-by: Matthias Brugger 

> ---
> 
> Changes since v2:
> - Rebased the patch on top of current HEAD
> - Picked up Oleksandr Suvorov's Acked-by
> 
> Link to v2 patch,
> https://patchwork.ozlabs.org/project/uboot/patch/20210226071849.29070-1-a-govindr...@ti.com/
> 
> Changes since v1:
> - Removed CONFIG_SYS_DFU_MAX_FILE_SIZE in defconfig files, where it was
>   not defined previously. The list of files in which this change is made
>   are listed below,
>   configs/colibri-imx6ull_defconfig
>   configs/colibri_vf_defconfig
>   configs/corvus_defconfig
>   configs/dh_imx6_defconfig
>   configs/draco_defconfig
>   configs/etamin_defconfig 
>   configs/odroid-xu3_defconfig
>   configs/odroid_defconfig
>   configs/origen_defconfig
>   configs/pico-dwarf-imx6ul_defconfig
>   configs/pico-hobbit-imx6ul_defconfig
>   configs/pico-imx6_defconfig
>   configs/pico-imx6ul_defconfig
>   configs/pico-pi-imx6ul_defconfig
>   configs/pxm2_defconfig
>   configs/rastaban_defconfig 
>   configs/rut_defconfig
>   configs/s5p_goni_defconfig
>   configs/s5pc210_universal_defconfig
>   configs/smartweb_defconfig  
>   configs/socfpga_arria5_defconfig
>   configs/socfpga_cyclone5_defconfig
>   configs/socfpga_dbm_soc1_defconfig
>   configs/socfpga_de0_nano_soc_defconfig
>   configs/socfpga_de10_nano_defconfig 
>   configs/socfpga_mcvevk_defconfig
>   configs/socfpga_sockit_defconfig
>   configs/socfpga_socrates_defconfig
>   configs/socfpga_vining_fpga_defconfig
>   configs/taurus_defconfig
>   configs/thuban_defconfig
>   configs/topic_miami_defconfig
>   configs/topic_miamilite_defconfig
>   configs/topic_miamiplus_defconfig 
>   configs/trats2_defconfig 
>   configs/trats_defconfig
>   configs/warp7_bl33_defconfig
>   configs/warp7_defconfig
>   configs/warp_defconfig
>   configs/xilinx_versal_virt_defconfig
>   configs/xilinx_zynq_virt_defconfig
>   configs/xilinx_zynqmp_virt_defconfig
> 
> Link to v1,
> https://patchwork.ozlabs.org/project/uboot/patch/20210223061427.20742-1-a-govindr...@ti.com/
>  
> 
>  configs/am65x_evm_a53_defconfig   |  2 ++
>  configs/am65x_evm_r5_usbdfu_defconfig |  2 ++
>  configs/am65x_hs_evm_a53_defconfig|  2 ++
>  configs/beaver_defconfig  |  2 ++
>  configs/cei-tk1-som_defconfig |  2 ++
>  configs/colibri-imx6ull_defconfig |  1 +
>  configs/colibri_vf_defconfig  |  1 +
>  configs/corvus_defconfig  |  1 +
>  configs/dalmore_defconfig |  2 ++
>  configs/dh_imx6_defconfig |  1 +
>  configs/draco_defconfig   |  1 +
>  configs/etamin_defconfig  |  1 +
>  configs/jetson-tk1_defconfig  |  2 ++
>  configs/nyan-big_defconfig|  2 ++
>  configs/odroid-xu3_defconfig  |  1 +
>  configs/odroid_defconfig  |  1 +
>  configs/origen_defconfig  |  1 +
>  configs/p2371-_defconfig  |  2 ++
>  configs/p2371-2180_defconfig  |  2 ++
>  configs/p2571_defconfig   |  2 ++
>  configs/p3450-_defconfig  |  2 ++
>  configs/pico-dwarf-imx6ul_defconfig   |  1 +
>  configs/pico-hobbit-imx6ul_defconfig  |  1 +
>  configs/pico-imx6_defconfig   |  1 +
>  configs/pico-imx6ul_defconfig |  1 +
>  configs/pico-pi-imx6ul_defconfig  |  1 +
>  configs/pxm2_defconfig|  1 +
>  configs/rastaban_defconfig|  1 +
>  configs/rpi_4_32b_defconfig   |  2 ++
>  configs/rpi_4_defconfig   |  2 ++
>  configs/rut_defconfig |  1 +
>  configs/s5p_goni_defconfig|  1 +
>  configs/s5pc210_universal_defconfig   |  1 +
>  configs/smartweb_defconfig|  1 +
>  configs/socfpga_arria5_defconfig  |  1 +
>  configs/socfpga_cyclone5_defconfig|  1 +
>  configs/socfpga_dbm_soc1_defconfig|  1 +
>  configs/socfpga_de0_nano_soc_defconfig|  1 +
>  configs/socfpga_de10_nano_defconfig   |  1 +
>  configs/socfpga_mcvevk_defconfig  |  1 +
>  configs/socfpga_sockit_defconfig  |  1 +
>  configs/socfpga_socrates_defconfig|  1 +
>  configs/socfpga_vining_fpga_defconfig |  1 +
>  configs/taurus_defconfig  |  1 +
>  configs/thuban_defconfig  |  1 +
>  configs/topic_miami_defconfi

Re: [RFC 0/5] rockchip_sfc: add support for Rockchip SFC

[Chris Morgan]

On Tue, Jun 01, 2021 at 08:22:09PM +0800, Kever Yang wrote:
> Add Yifeng from rockchip.
> 
> Hi Chris,
> 
>     First of all, I think you should remain the origin author info in the
> signed-off.

Okay, I can do that. Please note that since I submitted this I was
asked to redo the upstream linux proposed driver to use the spi-mem
framework. I think for now honestly I'd like to abandon this patch
and resubmit a little later with one that is more or less the same
(using the spi-mem framework) as the Linux driver.

https://patchwork.ozlabs.org/project/linux-mtd/patch/20210528170020.26219-2-macroalph...@gmail.com/

> 
> 
> Hi Yifeng,
> 
>     Please help to review this driver.
> 
> 
> Thanks,
> 
> - Kever
> 
> On 2021/5/26 上午5:49, Chris Morgan wrote:
> > From: Chris Morgan 
> > 
> > Requesting comments for a proposed patchset for adding the Rockchip
> > serial flash controller to u-boot. The goal of these patches is to
> > enable it for the Odroid Go Advance so that it may eventually boot
> > exclusively from the SFC on mainline U-boot (I have tested this and
> > it works).
> > 
> > The specific help I need with this patch is:
> > 
> > 1) I don't know the best way to upstream the XTX25F128B flash chip.
> > This chip uses a continuation code for the manufacturer ID, however I
> > cannot seem to find any way to actually read the continuation code.
> > There is a risk of this driver, used as-is, to collide with another
> > chip which has the same manufacturer ID with a different continuation
> > code.
> > 
> > 2) The Rockchip SFC driver itself (as it is mostly as-is from the BSP
> > U-Boot sources) supports SPI NAND and chips of varying sizes, but my
> > implementation only permits me to test with a single 128Mb flash chip.
> > The driver itself does some checking on the bitlen in the routine
> > rockchip_sfc_xfer() which is what is called for the dm_spi_ops.xfer.
> > I'm not sure if there is a better way to do this. Additionally, I have
> > to bit-shift the address written to the SFC as I suspect the value is
> > meant to be left justified, but I never tested it further.
> > 
> > Additionally, it might be worth mentioning but I noticed the Rockchip
> > BROM will only boot the TPL/SPL off of the SFC if I write it to address
> > 0x1. This is not documented and different than the address looked
> > at for SD card booting (512 * 64 = 0x8000 for SD Card booting). Also,
> > like the SD card driver I can confirm that if DMA is enabled at the SPL
> > stage A-TF seems to fail silently, then when Linux loads it hangs.
> > There is an ifdef to force FIFO mode only in the SPL stage.
> > 
> > Tested: Read (works)
> > Write (works if you write to an erased sector)
> > Erase (works)
> > SPL Read (works if you edit the u-boot,spl-boot-order)
> > 
> > Chris Morgan (5):
> >spi: rockchip_sfc: add support for Rockchip SFC
> >rockchip: px30: Add support for using SFC
> >rockchip: px30: add the serial flash controller
> >mtd: spi-nor-ids: Add XTX XT25F128B
> >rockchip: px30: add support for SFC for Odroid Go Advance
> > 
> >   arch/arm/dts/px30.dtsi |  38 ++
> >   arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi |  10 +-
> >   arch/arm/dts/rk3326-odroid-go2.dts |  22 +
> >   arch/arm/mach-rockchip/px30/px30.c |  64 ++
> >   drivers/mtd/spi/Kconfig|   6 +
> >   drivers/mtd/spi/spi-nor-ids.c  |   8 +
> >   drivers/spi/Kconfig|   8 +
> >   drivers/spi/Makefile   |   1 +
> >   drivers/spi/rockchip_sfc.c | 652 +
> >   9 files changed, 926 insertions(+), 1 deletion(-)
> >   create mode 100644 drivers/spi/rockchip_sfc.c
> > 
> 
> 

Re: [RFC 0/5] rockchip_sfc: add support for Rockchip SFC

[Kever Yang]

Hi Chris,

On 2021/6/2 上午12:54, Chris Morgan wrote:

On Tue, Jun 01, 2021 at 08:22:09PM +0800, Kever Yang wrote:

Add Yifeng from rockchip.

Hi Chris,

     First of all, I think you should remain the origin author info in the
signed-off.

Okay, I can do that. Please note that since I submitted this I was
asked to redo the upstream linux proposed driver to use the spi-mem
framework. I think for now honestly I'd like to abandon this patch
and resubmit a little later with one that is more or less the same
(using the spi-mem framework) as the Linux driver.



This sounds better, then we can wait for driver with new framework.

Thanks,

- Kever



https://patchwork.ozlabs.org/project/linux-mtd/patch/20210528170020.26219-2-macroalph...@gmail.com/



Hi Yifeng,

     Please help to review this driver.


Thanks,

- Kever

On 2021/5/26 上午5:49, Chris Morgan wrote:

From: Chris Morgan 

Requesting comments for a proposed patchset for adding the Rockchip
serial flash controller to u-boot. The goal of these patches is to
enable it for the Odroid Go Advance so that it may eventually boot
exclusively from the SFC on mainline U-boot (I have tested this and
it works).

The specific help I need with this patch is:

1) I don't know the best way to upstream the XTX25F128B flash chip.
This chip uses a continuation code for the manufacturer ID, however I
cannot seem to find any way to actually read the continuation code.
There is a risk of this driver, used as-is, to collide with another
chip which has the same manufacturer ID with a different continuation
code.

2) The Rockchip SFC driver itself (as it is mostly as-is from the BSP
U-Boot sources) supports SPI NAND and chips of varying sizes, but my
implementation only permits me to test with a single 128Mb flash chip.
The driver itself does some checking on the bitlen in the routine
rockchip_sfc_xfer() which is what is called for the dm_spi_ops.xfer.
I'm not sure if there is a better way to do this. Additionally, I have
to bit-shift the address written to the SFC as I suspect the value is
meant to be left justified, but I never tested it further.

Additionally, it might be worth mentioning but I noticed the Rockchip
BROM will only boot the TPL/SPL off of the SFC if I write it to address
0x1. This is not documented and different than the address looked
at for SD card booting (512 * 64 = 0x8000 for SD Card booting). Also,
like the SD card driver I can confirm that if DMA is enabled at the SPL
stage A-TF seems to fail silently, then when Linux loads it hangs.
There is an ifdef to force FIFO mode only in the SPL stage.

Tested: Read (works)
Write (works if you write to an erased sector)
Erase (works)
SPL Read (works if you edit the u-boot,spl-boot-order)

Chris Morgan (5):
spi: rockchip_sfc: add support for Rockchip SFC
rockchip: px30: Add support for using SFC
rockchip: px30: add the serial flash controller
mtd: spi-nor-ids: Add XTX XT25F128B
rockchip: px30: add support for SFC for Odroid Go Advance

   arch/arm/dts/px30.dtsi |  38 ++
   arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi |  10 +-
   arch/arm/dts/rk3326-odroid-go2.dts |  22 +
   arch/arm/mach-rockchip/px30/px30.c |  64 ++
   drivers/mtd/spi/Kconfig|   6 +
   drivers/mtd/spi/spi-nor-ids.c  |   8 +
   drivers/spi/Kconfig|   8 +
   drivers/spi/Makefile   |   1 +
   drivers/spi/rockchip_sfc.c | 652 +
   9 files changed, 926 insertions(+), 1 deletion(-)
   create mode 100644 drivers/spi/rockchip_sfc.c

Re: [PATCH] rk3399: boot_devices fix spinor node name

[Art Nikpal]

hi
> why "/spi@ff1d" is not work, this drivers should be work for other boards 
> before.

i`m sure now is not work (maybe nobody test it ) i have test it and
can see its doesn't works properly

because /spi@ff1d just spi bus node - its not SPINOR-Flash node as
was written before

if we check u-boot,spl-boot-order for rk3399 boards is must be
bootable devices list (for example &norflash | &spi_flash | &spliflash
 is alias for  /spi@ff1d/flash@0 )

grep same-as-spl arch/arm/dts/*rk3399* | grep flash
arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi:
u-boot,spl-boot-order = "same-as-spl", &sdhci, &spiflash, &sdmmc;
arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi:"same-as-spl",
&norflash, &sdhci, &sdmmc;
arch/arm/dts/rk3399-rockpro64-u-boot.dtsi:
u-boot,spl-boot-order = "same-as-spl", &spi_flash, &sdmmc, &sdhci;
arch/arm/dts/rk3399-roc-pc-u-boot.dtsi:u-boot,spl-boot-order =
"same-as-spl", &spi_flash, &sdhci, &sdmmc;

"same-as-spl" same must be translated to same devices ( &spi_flash,
&sdhci, &sdmmc  )

grep "same device the SPL was" -A22 arch/arm/mach-rockchip/spl-boot-order.c

/* Handle the case of 'same device the SPL was loaded from' */
if (strncmp(conf, "same-as-spl", 11) == 0) {
conf = board_spl_was_booted_from();
if (!conf)
continue;
}

/* First check if the list element is an alias */
alias = fdt_get_alias(blob, conf);
if (alias)
conf = alias;

/* Try to resolve the config item (or alias) as a path */

node = fdt_path_offset(blob, conf);
if (node < 0) {
debug("%s: could not find %s in FDT\n", __func__, conf);
continue;
}

/* Try to map this back onto SPL boot devices */
boot_device = spl_node_to_boot_device(node);
if (boot_device < 0) {

debug("%s: could not map node @%x to a boot-device\n",

grep "UCLASS_SPI_FLASH"  arch/arm/mach-rockchip/spl-boot-order.c

} else if (!uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node,
if (!uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node, &parent))


grep SPINOR arch/arm/mach-rockchip/rk3399/rk3399.c

[BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d",

but its not SPI_FLASH and spl_node_to_boot_device(/spi@ff1d)
return always -1 and
u-boot,spl-boot-order = "same-as-spl" never works properly for spinorflash

PS: i have test spi@ff1d/flash@0 works properly as expected

On Tue, Jun 1, 2021 at 8:09 PM Kever Yang  wrote:
>
> Hi Artem,
>
> On 2021/5/26 下午5:32, Artem Lapkin wrote:
> > Problem: board_spl_was_booted_from return wrong boot_devices[3] value
> > /spi@ff1d and same-as-spl dont work properly for SPINOR flash
> > because arch/arm/mach-rockchip/spl-boot-order.c spl_node_to_boot_device
> > need parse SPINOR flash node as UCLASS_SPI_FLASH
> >
> > spl-boot-order: same-as-spl > *** BOOT_SOURCE_ID 3 (2:emmc 3:spi 5:sd ...
> > /spi@ff1d > board_boot_order: could not map node @618 to a boot-device
> > /sdhci@fe33 > /mmc@fe32
> >
> > Solution: just change it to /spi@ff1d/flash@0
>
> I don't understand why the solution is add "/flash@0" and why
> "/spi@ff1d " is not work, this drivers should be work for other
> boards before.
>
>
> Thanks,
>
> - Kever
>
> >
> > spl-boot-order: same-as-spl > *** BOOT_SOURCE_ID 3 (2:emmc 3:spi 5:sd ...
> > /spi@ff1d/flash@0 > /sdhci@fe33 > /mmc@fe32
> >
> > Signed-off-by: Artem Lapkin 
> > ---
> >   arch/arm/mach-rockchip/rk3399/rk3399.c | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c 
> > b/arch/arm/mach-rockchip/rk3399/rk3399.c
> > index 869d2159..69e0c8c2 100644
> > --- a/arch/arm/mach-rockchip/rk3399/rk3399.c
> > +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c
> > @@ -28,7 +28,7 @@ DECLARE_GLOBAL_DATA_PTR;
> >
> >   const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
> >   [BROM_BOOTSOURCE_EMMC] = "/sdhci@fe33",
> > - [BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d",
> > + [BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d/flash@0",
> >   [BROM_BOOTSOURCE_SD] = "/mmc@fe32",
> >   };
> >
>
>

Re: [PATCH] evb_rk3399: add usb ohci definations

[Art Nikpal]

> But , evb_rk3399 board does not enable CONFIG_USB_OHCI_HCD and 
> CONFIG_USB_OHCI_GENERIC.

yes i know it !

for example some other rk3399 boards have it because (usb 1.1 didnt
work without ohci on usb2.0 port and not possible to use usb kbd for
this port )

grep CONFIG_USB_OHCI_GENERIC configs/*3399*
configs/pinebook-pro-rk3399_defconfig:CONFIG_USB_OHCI_GENERIC=y
configs/rock960-rk3399_defconfig:CONFIG_USB_OHCI_GENERIC=y
configs/rockpro64-rk3399_defconfig:CONFIG_USB_OHCI_GENERIC=y

many other boards which used TARGET_EVB_RK3399=y must have  same
problem (with usb1.1)

and i think other boards must have possibilities to use
CONFIG_USB_OHCI_HCD and CONFIG_USB_OHCI_GENERIC.

grep EVB configs/*3399*

configs/evb-rk3399_defconfig:CONFIG_TARGET_EVB_RK3399=y
configs/firefly-rk3399_defconfig:CONFIG_TARGET_EVB_RK3399=y
configs/khadas-edge-captain-rk3399_defconfig:CONFIG_TARGET_EVB_RK3399=y
configs/khadas-edge-rk3399_defconfig:CONFIG_TARGET_EVB_RK3399=y
configs/khadas-edge-v-rk3399_defconfig:CONFIG_TARGET_EVB_RK3399=y
configs/leez-rk3399_defconfig:CONFIG_TARGET_EVB_RK3399=y
configs/nanopc-t4-rk3399_defconfig:CONFIG_TARGET_EVB_RK3399=y
configs/nanopi-m4-2gb-rk3399_defconfig:CONFIG_TARGET_EVB_RK3399=y
configs/nanopi-m4b-rk3399_defconfig:CONFIG_TARGET_EVB_RK3399=y
configs/nanopi-m4-rk3399_defconfig:CONFIG_TARGET_EVB_RK3399=y
configs/nanopi-neo4-rk3399_defconfig:CONFIG_TARGET_EVB_RK3399=y
configs/nanopi-r4s-rk3399_defconfig:CONFIG_TARGET_EVB_RK3399=y
configs/orangepi-rk3399_defconfig:CONFIG_TARGET_EVB_RK3399=y
configs/rock-pi-4c-rk3399_defconfig:CONFIG_TARGET_EVB_RK3399=y
configs/rock-pi-4-rk3399_defconfig:CONFIG_TARGET_EVB_RK3399=y
configs/rock-pi-n10-rk3399pro_defconfig:CONFIG_TARGET_EVB_RK3399=y

On Tue, Jun 1, 2021 at 8:15 PM Kever Yang  wrote:
>
> Hi Artem,
>
> On 2021/5/26 下午5:33, Artem Lapkin wrote:
> > Problem: not possible to use CONFIG_USB_OHCI_HCD=y and
> > CONFIG_USB_OHCI_GENERIC=y options without CONFIG_USB_OHCI_NEW and
> > CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS definations
> >
> > Add missed definations.
>
> But , evb_rk3399 board does not enable CONFIG_USB_OHCI_HCD and
> CONFIG_USB_OHCI_GENERIC.
>
>
> Thanks,
>
> - Kever
>
> >
> > Signed-off-by: Artem Lapkin 
> > ---
> >   include/configs/evb_rk3399.h | 3 +++
> >   1 file changed, 3 insertions(+)
> >
> > diff --git a/include/configs/evb_rk3399.h b/include/configs/evb_rk3399.h
> > index b7e85037..492b7b4d 100644
> > --- a/include/configs/evb_rk3399.h
> > +++ b/include/configs/evb_rk3399.h
> > @@ -15,4 +15,7 @@
> >
> >   #define SDRAM_BANK_SIZE (2UL << 30)
> >
> > +#define CONFIG_USB_OHCI_NEW
> > +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
> > +
> >   #endif
>
>

Re: [PATCH] evb_rk3399: add usb ohci definations

[Art Nikpal]

workable example for CONFIG_USB_OHCI_HCD and CONFIG_USB_OHCI_GENERIC
(usb kbd on usb2.0 port)

kedge# usb tree
USB device tree:
  1  Hub (480 Mb/s, 0mA)
 u-boot EHCI Host Controller

  1  Hub (12 Mb/s, 0mA)
  |   U-Boot Root Hub
  |
  +-2  Human Interface (1.5 Mb/s, 100mA)
Dell KB216 Wired Keyboard

  1  Hub (480 Mb/s, 0mA)
 u-boot EHCI Host Controller

  1  Hub (12 Mb/s, 0mA)
  U-Boot Root Hub

  1  Hub (5 Gb/s, 0mA)
 U-Boot XHCI Host Controller


and for usbkbd connected to usb3 port

kedge# usb tree
USB device tree:
  1  Hub (480 Mb/s, 0mA)
 u-boot EHCI Host Controller

  1  Hub (12 Mb/s, 0mA)
  U-Boot Root Hub

  1  Hub (480 Mb/s, 0mA)
 u-boot EHCI Host Controller

  1  Hub (12 Mb/s, 0mA)
  U-Boot Root Hub

  1  Hub (5 Gb/s, 0mA)
  |  U-Boot XHCI Host Controller
  |
  +-2  Human Interface (1.5 Mb/s, 100mA)
Dell KB216 Wired Keyboard

PS: usb2.0 port cant recognize any usb1.1 devices without OHCI

On Wed, Jun 2, 2021 at 10:33 AM Art Nikpal  wrote:
>
> > But , evb_rk3399 board does not enable CONFIG_USB_OHCI_HCD and 
> > CONFIG_USB_OHCI_GENERIC.
>
> yes i know it !
>
> for example some other rk3399 boards have it because (usb 1.1 didnt
> work without ohci on usb2.0 port and not possible to use usb kbd for
> this port )
>
> grep CONFIG_USB_OHCI_GENERIC configs/*3399*
> configs/pinebook-pro-rk3399_defconfig:CONFIG_USB_OHCI_GENERIC=y
> configs/rock960-rk3399_defconfig:CONFIG_USB_OHCI_GENERIC=y
> configs/rockpro64-rk3399_defconfig:CONFIG_USB_OHCI_GENERIC=y
>
> many other boards which used TARGET_EVB_RK3399=y must have  same
> problem (with usb1.1)
>
> and i think other boards must have possibilities to use
> CONFIG_USB_OHCI_HCD and CONFIG_USB_OHCI_GENERIC.
>
> grep EVB configs/*3399*
>
> configs/evb-rk3399_defconfig:CONFIG_TARGET_EVB_RK3399=y
> configs/firefly-rk3399_defconfig:CONFIG_TARGET_EVB_RK3399=y
> configs/khadas-edge-captain-rk3399_defconfig:CONFIG_TARGET_EVB_RK3399=y
> configs/khadas-edge-rk3399_defconfig:CONFIG_TARGET_EVB_RK3399=y
> configs/khadas-edge-v-rk3399_defconfig:CONFIG_TARGET_EVB_RK3399=y
> configs/leez-rk3399_defconfig:CONFIG_TARGET_EVB_RK3399=y
> configs/nanopc-t4-rk3399_defconfig:CONFIG_TARGET_EVB_RK3399=y
> configs/nanopi-m4-2gb-rk3399_defconfig:CONFIG_TARGET_EVB_RK3399=y
> configs/nanopi-m4b-rk3399_defconfig:CONFIG_TARGET_EVB_RK3399=y
> configs/nanopi-m4-rk3399_defconfig:CONFIG_TARGET_EVB_RK3399=y
> configs/nanopi-neo4-rk3399_defconfig:CONFIG_TARGET_EVB_RK3399=y
> configs/nanopi-r4s-rk3399_defconfig:CONFIG_TARGET_EVB_RK3399=y
> configs/orangepi-rk3399_defconfig:CONFIG_TARGET_EVB_RK3399=y
> configs/rock-pi-4c-rk3399_defconfig:CONFIG_TARGET_EVB_RK3399=y
> configs/rock-pi-4-rk3399_defconfig:CONFIG_TARGET_EVB_RK3399=y
> configs/rock-pi-n10-rk3399pro_defconfig:CONFIG_TARGET_EVB_RK3399=y
>
> On Tue, Jun 1, 2021 at 8:15 PM Kever Yang  wrote:
> >
> > Hi Artem,
> >
> > On 2021/5/26 下午5:33, Artem Lapkin wrote:
> > > Problem: not possible to use CONFIG_USB_OHCI_HCD=y and
> > > CONFIG_USB_OHCI_GENERIC=y options without CONFIG_USB_OHCI_NEW and
> > > CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS definations
> > >
> > > Add missed definations.
> >
> > But , evb_rk3399 board does not enable CONFIG_USB_OHCI_HCD and
> > CONFIG_USB_OHCI_GENERIC.
> >
> >
> > Thanks,
> >
> > - Kever
> >
> > >
> > > Signed-off-by: Artem Lapkin 
> > > ---
> > >   include/configs/evb_rk3399.h | 3 +++
> > >   1 file changed, 3 insertions(+)
> > >
> > > diff --git a/include/configs/evb_rk3399.h b/include/configs/evb_rk3399.h
> > > index b7e85037..492b7b4d 100644
> > > --- a/include/configs/evb_rk3399.h
> > > +++ b/include/configs/evb_rk3399.h
> > > @@ -15,4 +15,7 @@
> > >
> > >   #define SDRAM_BANK_SIZE (2UL << 30)
> > >
> > > +#define CONFIG_USB_OHCI_NEW
> > > +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
> > > +
> > >   #endif
> >
> >

Re: [[PATCH] colibri_imx6: add board_fit_config_name_match to support FIT in SPL

[Sean Anderson]

On 6/1/21 11:58 AM, Ming Liu wrote:

Hi, Sean:

Thanks for the comments, please see my answers as follows:

 > Please use an errno.

Seems all other board are using '0' and '-1' as return value of 
board_fit_config_name_match, shouldn't we keep consistent with them?


*shrug*

We return an int, so why not use an error code? Otherwise, we might as
well return bool.



 > Do you need to match "imx6-colibri", or could you use the default config?

I think so since imx6-colibri.its is the only present DTS file for this board.

//Ming Liu



So does this FIT only contain one config? I ask because if you just
need the default config you can use the weak definition in
common/common_fit.c.

--Sean




Sean Anderson mailto:sean...@gmail.com>> 於 2021年5月31日 週一 
下午4:36寫道：

On 5/31/21 3:06 AM, liu.min...@gmail.com  
wrote:
 > From: Ming Liu mailto:liu.min...@gmail.com>>
 >
 > Only one dtb is currently supported, so match with imx6-colibri.
 >
 > Signed-off-by: Ming Liu mailto:liu.min...@gmail.com>>
 > ---
 >   board/toradex/colibri_imx6/colibri_imx6.c | 10 ++
 >   1 file changed, 10 insertions(+)
 >
 > diff --git a/board/toradex/colibri_imx6/colibri_imx6.c 
b/board/toradex/colibri_imx6/colibri_imx6.c
 > index c0e7754469..587d92a8e9 100644
 > --- a/board/toradex/colibri_imx6/colibri_imx6.c
 > +++ b/board/toradex/colibri_imx6/colibri_imx6.c
 > @@ -1081,6 +1081,16 @@ void board_init_f(ulong dummy)
 >   board_init_r(NULL, 0);
 >   }
 >
 > +#ifdef CONFIG_SPL_LOAD_FIT
 > +int board_fit_config_name_match(const char *name)
 > +{
 > + if (!strcmp(name, "imx6-colibri"))
 > + return 0;
 > +
 > + return -1;

Please use an errno.

 > +}
 > +#endif
 > +
 >   void reset_cpu(void)
 >   {
 >   }
 >

Do you need to match "imx6-colibri", or could you use the default config?

--Sean

RE: [PATCH] armv8: layerscape: enable eMMC HS400 workarounds for LX2160A/LX2162A

[Y.b. Lu]

May I know the status of the patch?
Thanks.

> -Original Message-
> From: Y.b. Lu
> Sent: 2021年5月14日 10:25
> To: Priyanka Jain ; Meenakshi Aggarwal
> 
> Cc: u-boot@lists.denx.de
> Subject: RE: [PATCH] armv8: layerscape: enable eMMC HS400 workarounds for
> LX2160A/LX2162A
> 
> Any comments.
> Thanks!
> 
> > -Original Message-
> > From: Yangbo Lu 
> > Sent: 2021年4月27日 16:42
> > To: u-boot@lists.denx.de; Priyanka Jain ;
> > Meenakshi Aggarwal 
> > Cc: Y.b. Lu 
> > Subject: [PATCH] armv8: layerscape: enable eMMC HS400 workarounds for
> > LX2160A/LX2162A
> >
> > Enable eMMC HS400 workarounds for LX2160A/LX2162A.
> >
> > Signed-off-by: Yangbo Lu 
> > ---
> >  arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 4 
> >  1 file changed, 4 insertions(+)
> >
> > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> > b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> > index 9d1ba4c771..395e5ccaad 100644
> > --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> > +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> > @@ -224,6 +224,8 @@ config ARCH_LX2162A
> > select SYS_FSL_EC1
> > select SYS_FSL_EC2
> > select SYS_FSL_ERRATUM_A050106
> > +   select SYS_FSL_ERRATUM_A011334
> > +   select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
> > select SYS_FSL_HAS_RGMII
> > select SYS_FSL_HAS_SEC
> > select SYS_FSL_HAS_CCN508
> > @@ -254,6 +256,8 @@ config ARCH_LX2160A
> > select SYS_FSL_EC1
> > select SYS_FSL_EC2
> > select SYS_FSL_ERRATUM_A050106
> > +   select SYS_FSL_ERRATUM_A011334
> > +   select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
> > select SYS_FSL_HAS_RGMII
> > select SYS_FSL_HAS_SEC
> > select SYS_FSL_HAS_CCN508
> > --
> > 2.25.1

RE: [PATCH] arm: dts: lx2162aqds: support eMMC HS400 mode on esdhc1

[Y.b. Lu]

May I know the status of the patch?
Thanks.

> -Original Message-
> From: Y.b. Lu
> Sent: 2021年5月14日 10:25
> To: Priyanka Jain ; Meenakshi Aggarwal
> 
> Cc: u-boot@lists.denx.de
> Subject: RE: [PATCH] arm: dts: lx2162aqds: support eMMC HS400 mode on
> esdhc1
> 
> Sent out v2 to update copyright.
> Any comments on v2.
> 
> Thank you.
> 
> > -Original Message-
> > From: Yangbo Lu 
> > Sent: 2021年4月27日 16:28
> > To: u-boot@lists.denx.de; Priyanka Jain ;
> > Meenakshi Aggarwal 
> > Cc: Y.b. Lu 
> > Subject: [PATCH] arm: dts: lx2162aqds: support eMMC HS400 mode on
> > esdhc1
> >
> > Add properties related to eMMC HS400 mode for esdhc1.
> >
> > Signed-off-by: Yangbo Lu 
> > ---
> >  arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi | 6 ++
> > arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi | 6 ++
> > arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi | 6 ++
> >  arch/arm/dts/fsl-lx2162a-qds.dts | 6 ++
> >  4 files changed, 24 insertions(+)
> >
> > diff --git a/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi
> > b/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi
> > index 60f5a4ee43..3b6fddba7c 100644
> > --- a/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi
> > +++ b/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi
> > @@ -56,3 +56,9 @@
> > reg = <0x3>;
> > };
> >  };
> > +
> > +&esdhc1 {
> > +   mmc-hs200-1_8v;
> > +   mmc-hs400-1_8v;
> > +   bus-width = <8>;
> > +};
> > diff --git a/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi
> > b/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi
> > index 8e11b0680a..0f4329f587 100644
> > --- a/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi
> > +++ b/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi
> > @@ -59,3 +59,9 @@
> > reg = <0x1>;
> > };
> >  };
> > +
> > +&esdhc1 {
> > +   mmc-hs200-1_8v;
> > +   mmc-hs400-1_8v;
> > +   bus-width = <8>;
> > +};
> > diff --git a/arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi
> > b/arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi
> > index faf4285eab..8c856a19d4 100644
> > --- a/arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi
> > +++ b/arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi
> > @@ -24,3 +24,9 @@
> > reg = <0x0>;
> > };
> >  };
> > +
> > +&esdhc1 {
> > +   mmc-hs200-1_8v;
> > +   mmc-hs400-1_8v;
> > +   bus-width = <8>;
> > +};
> > diff --git a/arch/arm/dts/fsl-lx2162a-qds.dts
> > b/arch/arm/dts/fsl-lx2162a-qds.dts
> > index 341610ccf4..68cb328716 100644
> > --- a/arch/arm/dts/fsl-lx2162a-qds.dts
> > +++ b/arch/arm/dts/fsl-lx2162a-qds.dts
> > @@ -135,3 +135,9 @@
> > reg = <2>;
> > };
> >  };
> > +
> > +&esdhc1 {
> > +   mmc-hs200-1_8v;
> > +   mmc-hs400-1_8v;
> > +   bus-width = <8>;
> > +};
> > --
> > 2.25.1

[RESEND PATCH v2 2/2] rockchip: rk3568: add clock driver

[Elaine Zhang]

Add rk3568 clock driver and cru structure definition.

Signed-off-by: Elaine Zhang 
---
 .../include/asm/arch-rockchip/cru_rk3568.h|  504 +++
 drivers/clk/rockchip/Makefile |1 +
 drivers/clk/rockchip/clk_rk3568.c | 2959 +
 3 files changed, 3464 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3568.h
 create mode 100644 drivers/clk/rockchip/clk_rk3568.c

diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3568.h 
b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h
new file mode 100644
index ..6c59033f03a6
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3568.h
@@ -0,0 +1,504 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
+ * Author: Elaine Zhang 
+ */
+
+#ifndef _ASM_ARCH_CRU_RK3568_H
+#define _ASM_ARCH_CRU_RK3568_H
+
+#define MHz100
+#define KHz1000
+#define OSC_HZ (24 * MHz)
+
+#define APLL_HZ(816 * MHz)
+#define GPLL_HZ(1188 * MHz)
+#define CPLL_HZ(1000 * MHz)
+#define PPLL_HZ(100 * MHz)
+
+/* RK3568 pll id */
+enum rk3568_pll_id {
+   APLL,
+   DPLL,
+   CPLL,
+   GPLL,
+   NPLL,
+   VPLL,
+   PPLL,
+   HPLL,
+   PLL_COUNT,
+};
+
+struct rk3568_clk_info {
+   unsigned long id;
+   char *name;
+   bool is_cru;
+};
+
+/* Private data for the clock driver - used by rockchip_get_cru() */
+struct rk3568_pmuclk_priv {
+   struct rk3568_pmucru *pmucru;
+   ulong ppll_hz;
+   ulong hpll_hz;
+};
+
+struct rk3568_clk_priv {
+   struct rk3568_cru *cru;
+   struct rk3568_grf *grf;
+   ulong ppll_hz;
+   ulong hpll_hz;
+   ulong gpll_hz;
+   ulong cpll_hz;
+   ulong npll_hz;
+   ulong vpll_hz;
+   ulong armclk_hz;
+   ulong armclk_enter_hz;
+   ulong armclk_init_hz;
+   bool sync_kernel;
+   bool set_armclk_rate;
+};
+
+struct rk3568_pll {
+   unsigned int con0;
+   unsigned int con1;
+   unsigned int con2;
+   unsigned int con3;
+   unsigned int con4;
+   unsigned int reserved0[3];
+};
+
+struct rk3568_pmucru {
+   struct rk3568_pll pll[2];/* Address Offset: 0x */
+   unsigned int reserved0[16];/* Address Offset: 0x0040 */
+   unsigned int mode_con00;/* Address Offset: 0x0080 */
+   unsigned int reserved1[31];/* Address Offset: 0x0084 */
+   unsigned int pmu_clksel_con[10];/* Address Offset: 0x0100 */
+   unsigned int reserved2[22];/* Address Offset: 0x0128 */
+   unsigned int pmu_clkgate_con[3];/* Address Offset: 0x0180 */
+   unsigned int reserved3[29];/* Address Offset: 0x018C */
+   unsigned int pmu_softrst_con[1];/* Address Offset: 0x0200 */
+};
+
+check_member(rk3568_pmucru, mode_con00, 0x80);
+check_member(rk3568_pmucru, pmu_softrst_con[0], 0x200);
+
+struct rk3568_cru {
+   struct rk3568_pll pll[6];
+   unsigned int mode_con00;/* Address Offset: 0x00C0 */
+   unsigned int misc_con[3];/* Address Offset: 0x00C4 */
+   unsigned int glb_cnt_th;/* Address Offset: 0x00D0 */
+   unsigned int glb_srst_fst;/* Address Offset: 0x00D4 */
+   unsigned int glb_srsr_snd; /* Address Offset: 0x00D8 */
+   unsigned int glb_rst_con;/* Address Offset: 0x00DC */
+   unsigned int glb_rst_st;/* Address Offset: 0x00E0 */
+   unsigned int reserved0[7];/* Address Offset: 0x00E4 */
+   unsigned int clksel_con[85]; /* Address Offset: 0x0100 */
+   unsigned int reserved1[43];/* Address Offset: 0x0254 */
+   unsigned int clkgate_con[36];/* Address Offset: 0x0300 */
+   unsigned int reserved2[28]; /* Address Offset: 0x0390 */
+   unsigned int softrst_con[30];/* Address Offset: 0x0400 */
+   unsigned int reserved3[2];/* Address Offset: 0x0478 */
+   unsigned int ssgtbl[32];/* Address Offset: 0x0480 */
+   unsigned int reserved4[32];/* Address Offset: 0x0500 */
+   unsigned int sdmmc0_con[2];/* Address Offset: 0x0580 */
+   unsigned int sdmmc1_con[2];/* Address Offset: 0x058C */
+   unsigned int sdmmc2_con[2];/* Address Offset: 0x0590 */
+   unsigned int emmc_con[2];/* Address Offset: 0x0598 */
+};
+
+check_member(rk3568_cru, mode_con00, 0xc0);
+check_member(rk3568_cru, softrst_con[0], 0x400);
+
+struct pll_rate_table {
+   unsigned long rate;
+   unsigned int fbdiv;
+   unsigned int postdiv1;
+   unsigned int refdiv;
+   unsigned int postdiv2;
+   unsigned int dsmpd;
+   unsigned int frac;
+};
+
+#define RK3568_PMU_MODE0x80
+#define RK3568_PMU_PLL_CON(x)  ((x) * 0x4)
+#define RK3568_PLL_CON(x)  ((x) * 0x4)
+#define RK3568_MODE_CON0xc0
+
+enum {
+   /* CRU_PMU_CLK_SEL0_CON */
+   RTC32K_SEL_SHIFT= 6,
+   RTC32K_SEL_MASK = 0x3 << RTC32K_SEL_SHIFT,
+   RTC32K_SEL_PMUPVTM  = 0,
+ 

[PATCH 0/3] Drop CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT

[Yangbo Lu]

For eSDHC, power supply is through peripheral circuit. So, 3.3V
power supply capability from register bit does not reflect the
truth. 3.3V is common for SD/MMC, and is supported for all boards
with eSDHC in current u-boot. So, let's use a Kconfig
CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT making 3.3V is supported in
default.

Then CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 can be dropped. And
i.MX eSDHC driver should drop it too, since it's not used by any
one of i.MX board.

Yangbo Lu (3):
  mmc: fsl_esdhc: convert to CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT
  mmc: fsl_esdhc_imx: drop CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
  armv8: layerscape: drop CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33

 drivers/mmc/Kconfig  | 7 +++
 drivers/mmc/fsl_esdhc.c  | 6 --
 drivers/mmc/fsl_esdhc_imx.c  | 5 -
 include/configs/T208xQDS.h   | 1 -
 include/configs/T208xRDB.h   | 1 -
 include/configs/T4240RDB.h   | 1 -
 include/configs/kontron_sl28.h   | 5 -
 include/configs/ls1012a2g5rdb.h  | 5 -
 include/configs/ls1012afrwy.h| 5 -
 include/configs/ls1012aqds.h | 5 -
 include/configs/ls1012ardb.h | 6 --
 include/configs/ls1028a_common.h | 5 -
 include/configs/ls1043a_common.h | 7 ---
 include/configs/ls1046a_common.h | 7 ---
 include/configs/ls1088aqds.h | 1 -
 include/configs/ls1088ardb.h | 5 -
 include/configs/ls2080aqds.h | 5 -
 include/configs/ls2080ardb.h | 5 -
 include/configs/lx2160a_common.h | 5 -
 scripts/config_whitelist.txt | 1 -
 20 files changed, 11 insertions(+), 77 deletions(-)


base-commit: 89be8e31ccd1c53b010385ed0807eb00f0eec06a
-- 
2.25.1

[PATCH 1/3] mmc: fsl_esdhc: convert to CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT

[Yangbo Lu]

For eSDHC, power supply is through peripheral circuit. So, 3.3V
power supply capability from register bit does not reflect the
truth. 3.3V is common for SD/MMC, and is supported for all boards
with eSDHC in current u-boot. So, let's use a Kconfig
CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT making 3.3V is supported in
default.

This is also a fix-up for one previous patch, which converted to
use IS_ENABLED() for CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 that is
not a Kconfig option.

Fixes: 52faec31827e ("mmc: fsl_esdhc: replace most #ifdefs by IS_ENABLED()")
Signed-off-by: Yangbo Lu 
---
 drivers/mmc/Kconfig | 7 +++
 drivers/mmc/fsl_esdhc.c | 6 --
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 8901456967..0909f502a1 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -798,6 +798,13 @@ config FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND
  This option assumes no hotplug, and u-boot has to make all the way to
  to linux to use 1.8v UHS-I speed mode if has card.
 
+config FSL_ESDHC_VS33_NOT_SUPPORT
+   bool "3.3V power supply not supported"
+   depends on FSL_ESDHC
+   help
+ For eSDHC, power supply is through peripheral circuit. 3.3V support is
+ common. Select this if 3.3V power supply not supported.
+
 config FSL_ESDHC_IMX
bool "Freescale/NXP i.MX eSDHC controller support"
help
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 7501fdb71e..d20f32b530 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -795,10 +795,12 @@ static void fsl_esdhc_get_cfg_common(struct 
fsl_esdhc_priv *priv,
u32 caps;
 
caps = esdhc_read32(®s->hostcapblt);
+
+   if (!IS_ENABLED(CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT))
+   caps |= HOSTCAPBLT_VS33;
+
if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC135))
caps &= ~(HOSTCAPBLT_SRS | HOSTCAPBLT_VS18 | HOSTCAPBLT_VS30);
-   if (IS_ENABLED(CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33))
-   caps |= HOSTCAPBLT_VS33;
if (caps & HOSTCAPBLT_VS18)
cfg->voltages |= MMC_VDD_165_195;
if (caps & HOSTCAPBLT_VS30)
-- 
2.25.1

[PATCH 2/3] mmc: fsl_esdhc_imx: drop CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33

[Yangbo Lu]

There is no i.MX board using such option. Drop it.

Signed-off-by: Yangbo Lu 
---
 drivers/mmc/fsl_esdhc_imx.c | 5 -
 1 file changed, 5 deletions(-)

diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index a4675838e5..d767795b58 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -1234,11 +1234,6 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
 #endif
 
-/* T4240 host controller capabilities register should have VS33 bit */
-#ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-   caps = caps | ESDHC_HOSTCAPBLT_VS33;
-#endif
-
if (caps & ESDHC_HOSTCAPBLT_VS18)
voltage_caps |= MMC_VDD_165_195;
if (caps & ESDHC_HOSTCAPBLT_VS30)
-- 
2.25.1

[PATCH 3/3] armv8: layerscape: drop CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33

[Yangbo Lu]

Drop CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33. CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT
is used instead.

Signed-off-by: Yangbo Lu 
---
 include/configs/T208xQDS.h   | 1 -
 include/configs/T208xRDB.h   | 1 -
 include/configs/T4240RDB.h   | 1 -
 include/configs/kontron_sl28.h   | 5 -
 include/configs/ls1012a2g5rdb.h  | 5 -
 include/configs/ls1012afrwy.h| 5 -
 include/configs/ls1012aqds.h | 5 -
 include/configs/ls1012ardb.h | 6 --
 include/configs/ls1028a_common.h | 5 -
 include/configs/ls1043a_common.h | 7 ---
 include/configs/ls1046a_common.h | 7 ---
 include/configs/ls1088aqds.h | 1 -
 include/configs/ls1088ardb.h | 5 -
 include/configs/ls2080aqds.h | 5 -
 include/configs/ls2080ardb.h | 5 -
 include/configs/lx2160a_common.h | 5 -
 scripts/config_whitelist.txt | 1 -
 17 files changed, 70 deletions(-)

diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index b1acb564c3..c2bc778809 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -618,7 +618,6 @@ unsigned long get_board_ddr_clk(void);
 #ifdef CONFIG_MMC
 #define CONFIG_SYS_FSL_ESDHC_ADDR  CONFIG_SYS_MPC85xx_ESDHC_ADDR
 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 #endif
 
 /*
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index e467ef453d..b12289f703 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -574,7 +574,6 @@ unsigned long get_board_ddr_clk(void);
 #ifdef CONFIG_MMC
 #define CONFIG_SYS_FSL_ESDHC_ADDR  CONFIG_SYS_MPC85xx_ESDHC_ADDR
 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 #endif
 
 /*
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index a04d9137b3..003aa55e6c 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -585,7 +585,6 @@ unsigned long get_board_ddr_clk(void);
 #ifdef CONFIG_MMC
 #define CONFIG_SYS_FSL_ESDHC_ADDR   CONFIG_SYS_MPC85xx_ESDHC_ADDR
 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 #endif
 
 
diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h
index 5f11205802..bfb4e67c8f 100644
--- a/include/configs/kontron_sl28.h
+++ b/include/configs/kontron_sl28.h
@@ -56,11 +56,6 @@
 #define CONFIG_DDR_CLK_FREQ1
 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4)
 
-/* MMC */
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#endif
-
 /* ethernet */
 #define CONFIG_SYS_RX_ETH_BUFFER   8
 
diff --git a/include/configs/ls1012a2g5rdb.h b/include/configs/ls1012a2g5rdb.h
index 9962b9872a..e651e5f90a 100644
--- a/include/configs/ls1012a2g5rdb.h
+++ b/include/configs/ls1012a2g5rdb.h
@@ -13,11 +13,6 @@
 #define CONFIG_CHIP_SELECTS_PER_CTRL   1
 #define CONFIG_SYS_SDRAM_SIZE  0x4000
 
-/*  MMC  */
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#endif
-
 /* SATA */
 #define CONFIG_LIBATA
 #define CONFIG_SCSI_AHCI
diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h
index ba152834d5..c5096101b4 100644
--- a/include/configs/ls1012afrwy.h
+++ b/include/configs/ls1012afrwy.h
@@ -33,11 +33,6 @@
func(DHCP, dhcp, na)
 #endif
 
-/*  MMC  */
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#endif
-
 #define CONFIG_PCIE1   /* PCIE controller 1 */
 
 #define CONFIG_PCI_SCAN_SHOW
diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
index 36be8f42c9..226d42f182 100644
--- a/include/configs/ls1012aqds.h
+++ b/include/configs/ls1012aqds.h
@@ -93,11 +93,6 @@
DSPI_CTAR_DT(0))
 #define CONFIG_SPI_FLASH_EON /* cs3 */
 
-/*  MMC  */
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#endif
-
 #define CONFIG_PCIE1   /* PCIE controller 1 */
 
 #define CONFIG_PCI_SCAN_SHOW
diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
index 582945b2ab..f896d5516f 100644
--- a/include/configs/ls1012ardb.h
+++ b/include/configs/ls1012ardb.h
@@ -38,12 +38,6 @@
 #define __PHY_ETH2_MASK0xFB
 #define __PHY_ETH1_MASK0xFD
 
-/*  MMC  */
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#endif
-
-
 #define CONFIG_PCIE1   /* PCIE controller 1 */
 
 #define CONFIG_PCI_SCAN_SHOW
diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h
index 31fcdae986..09d8f0c707 100644
--- a/include/configs/ls1028a_common.h
+++ b/include/configs/ls1028a_common.h
@@ -93,11 +93,6 @@
 
 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)  /* Increase max gunzip size */
 
-/*  MMC  */
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#endif
-
 #define OCRAM_NONSECURE_SIZE   0x0001
 #define CONFIG_SYS_FSL_QSPI_BASE   0x2000
 
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 29a3

[v2, 0/3] Drop CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT

[Yangbo Lu]

For eSDHC, power supply is through peripheral circuit. So, 3.3V
power supply capability from register bit does not reflect the
truth. 3.3V is common for SD/MMC, and is supported for all boards
with eSDHC in current u-boot. So, let's use a Kconfig
CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT making 3.3V is supported in
default.

Then CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 can be dropped. And
i.MX eSDHC driver should drop it too, since it's not used by any
one of i.MX board.

Changes for v2:
- Updated copyright.

Yangbo Lu (3):
  mmc: fsl_esdhc: convert to CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT
  mmc: fsl_esdhc_imx: drop CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
  armv8: layerscape: drop CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33

 drivers/mmc/Kconfig  | 7 +++
 drivers/mmc/fsl_esdhc.c  | 8 +---
 drivers/mmc/fsl_esdhc_imx.c  | 7 +--
 include/configs/T208xQDS.h   | 3 +--
 include/configs/T208xRDB.h   | 3 +--
 include/configs/T4240RDB.h   | 3 +--
 include/configs/kontron_sl28.h   | 8 +++-
 include/configs/ls1012a2g5rdb.h  | 7 +--
 include/configs/ls1012afrwy.h| 7 +--
 include/configs/ls1012aqds.h | 6 +-
 include/configs/ls1012ardb.h | 8 +---
 include/configs/ls1028a_common.h | 7 +--
 include/configs/ls1043a_common.h | 9 +
 include/configs/ls1046a_common.h | 9 +
 include/configs/ls1088aqds.h | 3 +--
 include/configs/ls1088ardb.h | 7 +--
 include/configs/ls2080aqds.h | 7 +--
 include/configs/ls2080ardb.h | 7 +--
 include/configs/lx2160a_common.h | 7 +--
 scripts/config_whitelist.txt | 1 -
 20 files changed, 31 insertions(+), 93 deletions(-)


base-commit: 89be8e31ccd1c53b010385ed0807eb00f0eec06a
-- 
2.25.1

[v2, 1/3] mmc: fsl_esdhc: convert to CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT

[Yangbo Lu]

For eSDHC, power supply is through peripheral circuit. So, 3.3V
power supply capability from register bit does not reflect the
truth. 3.3V is common for SD/MMC, and is supported for all boards
with eSDHC in current u-boot. So, let's use a Kconfig
CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT making 3.3V is supported in
default.

This is also a fix-up for one previous patch, which converted to
use IS_ENABLED() for CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 that is
not a Kconfig option.

Fixes: 52faec31827e ("mmc: fsl_esdhc: replace most #ifdefs by IS_ENABLED()")
Signed-off-by: Yangbo Lu 
---
Changes for v2:
- Updated copyright.
---
 drivers/mmc/Kconfig | 7 +++
 drivers/mmc/fsl_esdhc.c | 8 +---
 2 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 8901456967..0909f502a1 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -798,6 +798,13 @@ config FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND
  This option assumes no hotplug, and u-boot has to make all the way to
  to linux to use 1.8v UHS-I speed mode if has card.
 
+config FSL_ESDHC_VS33_NOT_SUPPORT
+   bool "3.3V power supply not supported"
+   depends on FSL_ESDHC
+   help
+ For eSDHC, power supply is through peripheral circuit. 3.3V support is
+ common. Select this if 3.3V power supply not supported.
+
 config FSL_ESDHC_IMX
bool "Freescale/NXP i.MX eSDHC controller support"
help
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 7501fdb71e..b3c71c8695 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
- * Copyright 2019-2020 NXP
+ * Copyright 2019-2021 NXP
  * Andy Fleming
  *
  * Based vaguely on the pxa mmc code:
@@ -795,10 +795,12 @@ static void fsl_esdhc_get_cfg_common(struct 
fsl_esdhc_priv *priv,
u32 caps;
 
caps = esdhc_read32(®s->hostcapblt);
+
+   if (!IS_ENABLED(CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT))
+   caps |= HOSTCAPBLT_VS33;
+
if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC135))
caps &= ~(HOSTCAPBLT_SRS | HOSTCAPBLT_VS18 | HOSTCAPBLT_VS30);
-   if (IS_ENABLED(CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33))
-   caps |= HOSTCAPBLT_VS33;
if (caps & HOSTCAPBLT_VS18)
cfg->voltages |= MMC_VDD_165_195;
if (caps & HOSTCAPBLT_VS30)
-- 
2.25.1

[v2, 2/3] mmc: fsl_esdhc_imx: drop CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33

[Yangbo Lu]

There is no i.MX board using such option. Drop it.

Signed-off-by: Yangbo Lu 
---
Changes for v2:
- Updated copyright.
---
 drivers/mmc/fsl_esdhc_imx.c | 7 +--
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
index a4675838e5..566ce046ae 100644
--- a/drivers/mmc/fsl_esdhc_imx.c
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
- * Copyright 2019 NXP Semiconductors
+ * Copyright 2019, 2021 NXP
  * Andy Fleming
  * Yangbo Lu 
  *
@@ -1234,11 +1234,6 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
 #endif
 
-/* T4240 host controller capabilities register should have VS33 bit */
-#ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-   caps = caps | ESDHC_HOSTCAPBLT_VS33;
-#endif
-
if (caps & ESDHC_HOSTCAPBLT_VS18)
voltage_caps |= MMC_VDD_165_195;
if (caps & ESDHC_HOSTCAPBLT_VS30)
-- 
2.25.1

[v2, 3/3] armv8: layerscape: drop CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33

[Yangbo Lu]

Drop CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33. CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT
is used instead.

Signed-off-by: Yangbo Lu 
---
Changes for v2:
- Updated copyright.
---
 include/configs/T208xQDS.h   | 3 +--
 include/configs/T208xRDB.h   | 3 +--
 include/configs/T4240RDB.h   | 3 +--
 include/configs/kontron_sl28.h   | 8 +++-
 include/configs/ls1012a2g5rdb.h  | 7 +--
 include/configs/ls1012afrwy.h| 7 +--
 include/configs/ls1012aqds.h | 6 +-
 include/configs/ls1012ardb.h | 8 +---
 include/configs/ls1028a_common.h | 7 +--
 include/configs/ls1043a_common.h | 9 +
 include/configs/ls1046a_common.h | 9 +
 include/configs/ls1088aqds.h | 3 +--
 include/configs/ls1088ardb.h | 7 +--
 include/configs/ls2080aqds.h | 7 +--
 include/configs/ls2080ardb.h | 7 +--
 include/configs/lx2160a_common.h | 7 +--
 scripts/config_whitelist.txt | 1 -
 17 files changed, 18 insertions(+), 84 deletions(-)

diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index b1acb564c3..7bc792b8d1 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2011-2013 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
  */
 
 /*
@@ -618,7 +618,6 @@ unsigned long get_board_ddr_clk(void);
 #ifdef CONFIG_MMC
 #define CONFIG_SYS_FSL_ESDHC_ADDR  CONFIG_SYS_MPC85xx_ESDHC_ADDR
 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 #endif
 
 /*
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index e467ef453d..b5197b3ed9 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
  */
 
 /*
@@ -574,7 +574,6 @@ unsigned long get_board_ddr_clk(void);
 #ifdef CONFIG_MMC
 #define CONFIG_SYS_FSL_ESDHC_ADDR  CONFIG_SYS_MPC85xx_ESDHC_ADDR
 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 #endif
 
 /*
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index a04d9137b3..139beae08d 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
  */
 
 /*
@@ -585,7 +585,6 @@ unsigned long get_board_ddr_clk(void);
 #ifdef CONFIG_MMC
 #define CONFIG_SYS_FSL_ESDHC_ADDR   CONFIG_SYS_MPC85xx_ESDHC_ADDR
 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 #endif
 
 
diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h
index 5f11205802..4e9ea9d7fe 100644
--- a/include/configs/kontron_sl28.h
+++ b/include/configs/kontron_sl28.h
@@ -1,4 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
 
 #ifndef __SL28_H
 #define __SL28_H
@@ -56,11 +59,6 @@
 #define CONFIG_DDR_CLK_FREQ1
 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4)
 
-/* MMC */
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#endif
-
 /* ethernet */
 #define CONFIG_SYS_RX_ETH_BUFFER   8
 
diff --git a/include/configs/ls1012a2g5rdb.h b/include/configs/ls1012a2g5rdb.h
index 9962b9872a..1c016dee97 100644
--- a/include/configs/ls1012a2g5rdb.h
+++ b/include/configs/ls1012a2g5rdb.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright 2017 NXP
+ * Copyright 2017, 2021 NXP
  */
 
 #ifndef __LS1012A2G5RDB_H__
@@ -13,11 +13,6 @@
 #define CONFIG_CHIP_SELECTS_PER_CTRL   1
 #define CONFIG_SYS_SDRAM_SIZE  0x4000
 
-/*  MMC  */
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#endif
-
 /* SATA */
 #define CONFIG_LIBATA
 #define CONFIG_SCSI_AHCI
diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h
index ba152834d5..9024d5e10f 100644
--- a/include/configs/ls1012afrwy.h
+++ b/include/configs/ls1012afrwy.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
  */
 
 #ifndef __LS1012AFRWY_H__
@@ -33,11 +33,6 @@
func(DHCP, dhcp, na)
 #endif
 
-/*  MMC  */
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#endif
-
 #define CONFIG_PCIE1   /* PCIE controller 1 */
 
 #define CONFIG_PCI_SCAN_SHOW
diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
index 36be8f42c9..e76f5ef23b 100644
--- a/include/configs/ls1012aqds.h
+++ b/include/configs/ls1012aqds.h
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
  */
 
 #ifndef __LS1012AQDS_H__
@@ -93,11 +94,6 @@
DSPI_CTAR_DT(0))
 #define CONFIG_SPI_FLASH_EON /* cs3 */
 
-/*  MMC 

Re: [PATCH v2 1/7] arm: a37xx: pci: Don't put link into LTSSM Recovery state during probe

[Stefan Roese]

Hi Pali,

On 01.06.21 14:57, Pali Rohár wrote:

On Thursday 27 May 2021 08:19:32 Stefan Roese wrote:

On 26.05.21 17:59, Pali Rohár wrote:

During our debugging of the Aardvark driver in Linux we have discovered
that the PCIE_CORE_LINK_CTRL_STAT_REG register in fact controls standard
PCIe Link Control Register for PCIe Root Bridge. This led us to discover
that the name of the PCIE_CORE_LINK_TRAINING macro and the corresponding
comment by this macro's usage is misleading; this bit in fact controls
Retrain Link, which, according to PCIe base spec is defined as:

A write of 1b to this bit initiates Link retraining by directing the
Physical Layer LTSSM to the Recovery state. If the LTSSM is already in
Recovery or Configuration, re-entering Recovery is permitted but not
required.

Entering Recovery state is normally done from LTSSM L0, L0s and L1 states.
But since the pci-aardvark.c driver enables Link Training just a few lines
above, the controller is not in L0 ready state yet. So setting aardvark bit
PCIE_CORE_LINK_TRAINING does not actually enter Recovery state at this
place.

Moreover, trying to enter LTSSM Recovery state without other configuration
is causing issues for some cards (e.g. Atheros AR9xxx and QCA9xxx). Since
Recovery state is not entered, these issues are not triggered.

Remove code which tries to enter LTSSM Recovery state completely.

Signed-off-by: Pali Rohár 
Reviewed-by: Marek Behún 


Reviewed-by: Stefan Roese 

Thanks,
Stefan


Hello Stefan! Thank you for review. Would you be sending these A3720
patches to 2021.07 version?


My plan was to postpone these patches to the next release, as they seem
quite intrusive. But please let me know if you think this is not the
case and they should be added as fixes into this release still.

Thanks,
Stefan


---
   drivers/pci/pci-aardvark.c | 5 -
   1 file changed, 5 deletions(-)

diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
index c43d4f309b19..06c567e236f9 100644
--- a/drivers/pci/pci-aardvark.c
+++ b/drivers/pci/pci-aardvark.c
@@ -613,11 +613,6 @@ static int pcie_advk_setup_hw(struct pcie_advk *pcie)
reg |= PIO_CTRL_ADDR_WIN_DISABLE;
advk_writel(pcie, reg, PIO_CTRL);
-   /* Start link training */
-   reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG);
-   reg |= PCIE_CORE_LINK_TRAINING;
-   advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
-
/* Wait for PCIe link up */
if (pcie_advk_wait_for_link(pcie))
return -ENXIO;




Viele Grüße,
Stefan

--
DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de



Viele Grüße,
Stefan

--
DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de

[PATCH] config_distro_bootcmd: Ability to boot u-boot script from FIT image

[Yau Wai Gan]

When source u-boot script from an FIT image, it is required to provide the
script subimage name. Add an additional environment variable "scriptuname"
when sourcing u-boot script in FIT image during run distro_bootcmd.

Signed-off-by: Yau Wai Gan 
---
 include/config_distro_bootcmd.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h
index 2627c2a6a5..7d7ee99a07 100644
--- a/include/config_distro_bootcmd.h
+++ b/include/config_distro_bootcmd.h
@@ -451,7 +451,9 @@
"boot_a_script="  \
"load ${devtype} ${devnum}:${distro_bootpart} "   \
"${scriptaddr} ${prefix}${script}; "  \
-   "source ${scriptaddr}\0"  \
+   "if test ${script} = \"boot.scr.uimg\"; then "\
+   "source ${scriptaddr}:${scriptuname};"\
+   "else source ${scriptaddr}; fi; \0"   \
\
"scan_dev_for_scripts="   \
"for script in ${boot_scripts}; do "  \
-- 
2.13.0

Re: [PATCHv4,1/1] clk: zynq: Add clock wizard driver

[Zhengxun Li]

Hi Sean,

Thanks for your reply.

>>This clock driver adds support for clock related settings for
>>Zynq platform.
>>
>> +config COMMON_CLK_XLNX_CLKWZRD
>
> Why not just CLK_XILNIX_WIZARD? Do we need "COMMON" in here?

Follow the linux patch "clk: clocking-wizard: Add the clockwizard to
clk directory".

https://patchwork.kernel.org/project/linux-clk/patch/1617886723-27117-3-git-send-email-shubhrajyoti.da...@xilinx.com/

>> +bool "Xilinx Clocking Wizard"
>> +depends on CLK
>> +help
>> +  Support for the Xilinx Clocking Wizard IP core clock generator.
>> +  Adds support for clocking wizard and compatible.
>> +  This driver supports the Xilinx clocking wizard programmable clock
>> +  synthesizer.
>
> This can all be one sentence. Please also add some basic information
> about the clock wizard. What sorts of systems might one find this device
> on? It looks like configuration is determined from registers within the
> clock itself. Perhaps add a note about that.

Okay.

>> +
>>   config CLK_ZYNQMP
>>  bool "Enable clock driver support for ZynqMP"
>>  depends on ARCH_ZYNQMP
>> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
>> index 645709b855..f4ddbe831a 100644
>> --- a/drivers/clk/Makefile
>> +++ b/drivers/clk/Makefile
>> @@ -43,6 +43,7 @@ obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
>>   obj-$(CONFIG_CLK_VEXPRESS_OSC) += clk_vexpress_osc.o
>>   obj-$(CONFIG_CLK_ZYNQ) += clk_zynq.o
>>   obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o
>> +obj-$(CONFIG_COMMON_CLK_XLNX_CLKWZRD) += clk-xlnx-clock-wizard.o
>>   obj-$(CONFIG_ICS8N3QV01) += ics8n3qv01.o
>>   obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
>>   obj-$(CONFIG_SANDBOX) += clk_sandbox.o
>> diff --git a/drivers/clk/clk-xlnx-clock-wizard.c 
>> b/drivers/clk/clk-xlnx-clock-wizard.c
>> new file mode 100644
>> index 00..76c0eb27e6
>> --- /dev/null
>> +++ b/drivers/clk/clk-xlnx-clock-wizard.c
>> @@ -0,0 +1,177 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Xilinx 'Clocking Wizard' driver
>> + *
>> + * Copyright (c) 2021 Macronix Inc.
>> + *
>> + * Author: Zhengxun Li 
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +#define SRR 0x0
>> +
>> +#define SR  0x4
>> +#define SR_LOCKED   BIT(0)
>> +
>> +#define CCR(x)  (0x200 + ((x) * 4))
>> +
>> +#define FBOUT_CFG   CCR(0)
>> +#define FBOUT_DIV(x)(x)
>> +#define FBOUT_GET_DIV(x)((x) & GENMASK(7, 0))
>> +#define FBOUT_MUL(x)((x) << 8)
>> +#define FBOUT_GET_MUL(x)(((x) & GENMASK(15, 8)) >> 8)
>> +#define FBOUT_FRAC(x)   ((x) << 16)
>> +#define FBOUT_GET_FRAC(x)   (((x) & GENMASK(25, 16)) >> 16)
>> +#define FBOUT_FRAC_EN   BIT(26)
>> +
>> +#define FBOUT_PHASE CCR(1)
>> +
>> +#define OUT_CFG(x)  CCR(2 + ((x) * 3))
>> +#define OUT_DIV(x)  (x)
>> +#define OUT_GET_DIV(x)  ((x) & GENMASK(7, 0))
>
> Please use FIELD_PREP and FIELD_GET. And please define the mask
> separately.

Okay.

>> +#define OUT_FRAC(x) ((x) << 8)
>> +#define OUT_GET_FRAC(x) (((x) & GENMASK(17, 8)) >> 8)
>
> ditto
>
>> +#define OUT_FRAC_EN BIT(18)
>> +
>> +#define OUT_PHASE(x)CCR(3 + ((x) * 3))
>> +#define OUT_DUTY(x) CCR(4 + ((x) * 3))
>> +
>> +#define CTRLCCR(23)
>> +#define CTRL_SENBIT(2)
>> +#define CTRL_SADDR  BIT(1)
>> +#define CTRL_LOAD   BIT(0)
>> +
>> +/**
>> + * struct clkwzrd - Clock wizard private data structure
>> + *
>> + * @base:   memory base
>> + * @vco_clk:voltage-controlled oscillator frequency
>> + */
>> +struct clkwzd {
>> +void *base;
>> +u64 vco_clk;
>> +};
>> +
>> +struct clkwzd_plat {
>> +fdt_addr_t addr;
>> +};
>> +
>> +static int clk_wzrd_enable(struct clk *clk)
>> +{
>> +struct clkwzd *priv = dev_get_priv(clk->dev);
>> +int ret;
>> +u32 val;
>> +
>> +ret = readl_poll_sleep_timeout(priv->base + SR, val, val & SR_LOCKED,
>> +   1, 100);
>> +if (!ret) {
>> +writel(CTRL_SEN | CTRL_SADDR | CTRL_LOAD, priv->base + CTRL);
>> +writel(CTRL_SADDR, priv->base + CTRL);
>> +ret = readl_poll_sleep_timeout(priv->base + SR, val,
>> +   val & SR_LOCKED, 1, 100);
>> +}
>> +
>> +return ret;
>> +}
>> +
>> +static unsigned long clk_wzrd_set_rate(struct clk *clk, ulong rate)
>> +{
>> +struct clkwzd *priv = dev_get_priv(clk->dev);
>> +u64 div;
>> +u32 cfg;
>> +
>> +/* Get output clock divide value */
>> +div = DIV_ROUND_DOWN_ULL(priv->vco_clk * 1000, rate);
>> +if (div < 1000 || div > 255999)
>> +return -EINVAL;
>> +
>> +cfg = OUT_DIV((u32)div / 1000);
>> +
>> +writel(cfg, priv->base + OUT_CFG(clk->id));
>> +
>> +return 0;
>> +}
>> +
>> +static struct clk

[PATCH] net: fm: Fix a memory leak issue

[Zhiqiang Hou]

From: Hou Zhiqiang 

Fix a memory leak issue in the RX port initialization.

Signed-off-by: Hou Zhiqiang 
---
 drivers/net/fm/eth.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index 0e89e663f7..7c23ccc1f0 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -288,8 +288,10 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth 
*fm_eth)
 
/* alloc Rx buffer from main memory */
rx_buf_pool = malloc(MAX_RXBUF_LEN * RX_BD_RING_SIZE);
-   if (!rx_buf_pool)
+   if (!rx_buf_pool) {
+   free(rx_bd_ring_base);
return -ENOMEM;
+   }
 
memset(rx_buf_pool, 0, MAX_RXBUF_LEN * RX_BD_RING_SIZE);
debug("%s: rx_buf_pool = %p\n", __func__, rx_buf_pool);
-- 
2.17.1

Re: [v2, 1/3] mmc: fsl_esdhc: convert to CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT

[Jaehoon Chung]

Hi,

On 6/2/21 1:19 PM, Yangbo Lu wrote:
> For eSDHC, power supply is through peripheral circuit. So, 3.3V
> power supply capability from register bit does not reflect the
> truth. 3.3V is common for SD/MMC, and is supported for all boards
> with eSDHC in current u-boot. So, let's use a Kconfig
> CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT making 3.3V is supported in
> default.
> 
> This is also a fix-up for one previous patch, which converted to
> use IS_ENABLED() for CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 that is
> not a Kconfig option.
> 
> Fixes: 52faec31827e ("mmc: fsl_esdhc: replace most #ifdefs by IS_ENABLED()")
> Signed-off-by: Yangbo Lu 
> ---
> Changes for v2:
>   - Updated copyright.
> ---
>  drivers/mmc/Kconfig | 7 +++
>  drivers/mmc/fsl_esdhc.c | 8 +---
>  2 files changed, 12 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
> index 8901456967..0909f502a1 100644
> --- a/drivers/mmc/Kconfig
> +++ b/drivers/mmc/Kconfig
> @@ -798,6 +798,13 @@ config FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND
> This option assumes no hotplug, and u-boot has to make all the way to
> to linux to use 1.8v UHS-I speed mode if has card.
>  
> +config FSL_ESDHC_VS33_NOT_SUPPORT
> + bool "3.3V power supply not supported"
> + depends on FSL_ESDHC
> + help
> +   For eSDHC, power supply is through peripheral circuit. 3.3V support is
> +   common. Select this if 3.3V power supply not supported.
> +
>  config FSL_ESDHC_IMX
>   bool "Freescale/NXP i.MX eSDHC controller support"
>   help
> diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
> index 7501fdb71e..b3c71c8695 100644
> --- a/drivers/mmc/fsl_esdhc.c
> +++ b/drivers/mmc/fsl_esdhc.c
> @@ -1,7 +1,7 @@
>  // SPDX-License-Identifier: GPL-2.0+
>  /*
>   * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
> - * Copyright 2019-2020 NXP
> + * Copyright 2019-2021 NXP
>   * Andy Fleming
>   *
>   * Based vaguely on the pxa mmc code:
> @@ -795,10 +795,12 @@ static void fsl_esdhc_get_cfg_common(struct 
> fsl_esdhc_priv *priv,
>   u32 caps;
>  
>   caps = esdhc_read32(®s->hostcapblt);
> +
> + if (!IS_ENABLED(CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT))
> + caps |= HOSTCAPBLT_VS33;
> +

If 3.3V is supported by default, how about below code?

caps |= HOSTCAPBLT_VS33;
if (IS_ENABLED(CONFIG_xxx_NOT_SUPPORT))
caps &= ~HOSTCAPBLT_VS33;

I don't know exactly about hostcapblt register. 
If possible to read wrong capability value from regsiter, I think that it's 
better.
Just my opinion. 

Best Regards,
Jaehoon Chung

>   if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC135))
>   caps &= ~(HOSTCAPBLT_SRS | HOSTCAPBLT_VS18 | HOSTCAPBLT_VS30);
> - if (IS_ENABLED(CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33))
> - caps |= HOSTCAPBLT_VS33;
>   if (caps & HOSTCAPBLT_VS18)
>   cfg->voltages |= MMC_VDD_165_195;
>   if (caps & HOSTCAPBLT_VS30)
>