Weirdness of ofnode_get_addr_size()

2021-05-02 Thread Jan Kiszka
Hi,

I'm trying to make some sense of ofnode_get_addr_size() in order to fix
[1] properly.

First, the documentation if this functions says "This does no address
translation". But the node-pointer path happily calls
of_translate_address(), as the result of a6a45cd32539. For not
offset-bases path, it calls fdtdec_get_addr_size() which does no
translation.

Related to [1]: The node-pointer path cleanly calls
of_n_addr/size_cells() in order to retrieve the configured number of
cells. But the offset-based path simply calls fdtdec_get_addr_size()
which assumes that the number of cells is derived from the physical
address width of that platform.

So, what is that functions actually supposed to do?

Jan

[1] https://www.mail-archive.com/u-boot@lists.denx.de/msg405446.html


Unable to boot u-boot image from nand storage imx6ull.

2021-05-02 Thread Navin Sankar

Hello all,

Ported uboot to seeed studio based imx6ull 
 
board.


        NAND Part Number - mt29f4g08abaeawp

        NAND Size - 512 MBytes

Both the SPL and U-BOOT image boot successfully from SD card.

While with nand flash, SPL boot's fine. But SPL didn't boot the u-boot 
from nand flash.



=> mtdparts

device nand0 , # parts = 4
 #: name    size    offset  mask_flags
 0: spl 0x0008  0x  0
 1: uboot   0x0010  0x0008  0
 2: uboot-dup   0x0010  0x0018  0
 3: ubi 0x1fd8  0x0028  0

active partition: nand0,0 - (spl) 0x0008 @ 0x

defaults:
mtdids  : nand0=gpmi-nand
mtdparts: gpmi-nand:512k(spl),1m(uboot),1m(uboot-dup),-(ubi)


And I flashed the SPL and u-boot image from SD card.

Here is flashing result,

Initially erased the nand chip


=> nand erase.chip

NAND erase.chip: device 0 whole chip
Skipping bad block at 0x1ff0
Skipping bad block at 0x1ff4
Skipping bad block at 0x1ff8
Skipping bad block at 0x1ffc

OK


Then flashed the SPL

=> ext4load mmc 0:1 $loadaddr SPL
35840 bytes read in 4 ms (8.5 MiB/s)
=> nand erase.part spl

NAND erase.part: device 0 offset 0x0, size 0x8
Erasing at 0x4 -- 100% complete.
OK
=> nandbcb init $loadaddr 0x0 $filesize
device 0 offset 0x0, size 0x8c00
Skipping bad block at 0x1ff0
Skipping bad block at 0x1ff4
Skipping bad block at 0x1ff8
Skipping bad block at 0x1ffc

Write firmware0 @0x20 offset, 0x9000 bytes written: OK
Write firmware1 @0x1010 offset, 0x9000 bytes written: OK
NAND FCB write to 0x400 offset 0x0 written: OK
NAND FCB write to 0x400 offset 0x4 written: OK
NAND FCB write to 0x400 offset 0x8 written: OK
NAND FCB write to 0x400 offset 0xc written: OK
NAND DBBT write to 0x10 offset 0x1000 written: OK
DBBT data write to 0x104000 offset 0x1000 written: OK
NAND DBBT write to 0x14 offset 0x1000 written: OK
DBBT data write to 0x144000 offset 0x1000 written: OK
NAND DBBT write to 0x18 offset 0x1000 written: OK
DBBT data write to 0x184000 offset 0x1000 written: OK
NAND DBBT write to 0x1c offset 0x1000 written: OK
DBBT data write to 0x1c4000 offset 0x1000 written: OK


Afterwards flashed the uboot image,

=> ext4load mmc 0:1 $loadaddr u-boot-dtb.img
624580 bytes read in 29 ms (20.5 MiB/s)
=> nand erase.part uboot

NAND erase.part: device 0 offset 0x8, size 0x10
Erasing at 0x14 -- 100% complete.
OK
=> nand erase.part uboot-dup

NAND erase.part: device 0 offset 0x18, size 0x10
Erasing at 0x24 -- 100% complete.
OK
=> nand write $loadaddr uboot $filesize

NAND write: device 0 offset 0x8, size 0x987c4
 624580 bytes written: OK


Everything work's fine, but it didn't boot the u-boot image from nand 
storage.


U-Boot SPL 2021.07-rc1-02889-gf6058bbb94-dirty (May 01 2021 - 14:12:55 
+0530)

Trying to boot from NAND


Any hint?


--
Thanks and Regards,
Navin Sankar N V,


FEC_MXC_SHARE_MDIO on i.MX6ULL

2021-05-02 Thread Oleh Kravchenko
Hi all,

I'm working on adding u-boot support for boards based on i.MX6ULL SoC.
One board has a shared MDIO (CONFIG_FEC_MXC_SHARE_MDIO=y).

> U-Boot 2021.04-2-gb199ac910c-dirty (May 02 2021 - 01:03:13 +0300)

I've found a weird race condition in phy_find_by_mask() function.
During the cold boot, it's don't initialize properly:

> Net:   
> Warning: ethernet@20b4000 (eth1) using random MAC address - 9e:55:17:69:4a:cb
> eth1: ethernet@20b4000Get shared mii bus on ethernet@2188000
> Could not get PHY for FEC1: addr 0

Everything initializes properly If I perform hot boot:
> Net:   
> Warning: ethernet@20b4000 (eth1) using random MAC address - f6:cc:65:df:9d:99
> eth1: ethernet@20b4000Get shared mii bus on ethernet@2188000
> 
> Warning: ethernet@2188000 (eth0) using random MAC address - 16:1b:89:80:44:8e
> , eth0: ethernet@2188000

After some debugging, I've change phy_find_by_mask():
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 89e3076bfd..5dfc8cba37 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -914,12 +914,11 @@ struct phy_device *phy_find_by_mask(struct mii_dev *bus, 
uint phy_mask,
phy_interface_t interface)
 {
/* Reset the bus */
-   if (bus->reset) {
+   if (bus->reset)
bus->reset(bus);
 
-   /* Wait 15ms to make sure the PHY has come out of hard reset */
-   mdelay(15);
-   }
+   /* Wait 15ms to make sure the PHY has come out of hard reset */
+   mdelay(15);
 
return get_phy_device_by_mask(bus, phy_mask, interface);
 }

Any ideas on how to fix this issue properly?
Or patch above is good enough to be merged into the u-boot source tree?

-- 
Best regards,
Oleh Kravchenko



Re: [PATCH] Makefile: Fix generation of flash.bin u-boot.itb with binman

2021-05-02 Thread Stefano Babic

Hi Marek,

On 30.04.21 20:52, Simon Glass wrote:

Hi Marek,

On Fri, 30 Apr 2021 at 11:47, Marek Vasut  wrote:


On 4/30/21 8:13 PM, Simon Glass wrote:

Hi,


Hello Simon,


On Thu, 29 Apr 2021 at 17:11, Bin Meng  wrote:


On Sat, Apr 24, 2021 at 8:57 PM Marek Vasut  wrote:


On 2/25/21 9:50 PM, Marek Vasut wrote:

In case binman is enabled, the u-boot.itb is generated using this tool
and there is no direct u-boot.itb target, but instead the binman tool
must be invoked. Add support for this case.

Signed-off-by: Marek Vasut 
Cc: Peng Fan 
Cc: Stefano Babic 


This bugfix is still missing from upstream.


It seems to be missing a Fixes tag?


There are way too many commits related to this to identify specific one.


Sure, I was suggesting why it had not been picked up for the release.




I can't really comment on this particular patch as it is up to MX8
what is done here.


In that case, deciding on this bugfix is up to the maintainer, Stefano.


But a much better solution is to move this generation stuff to binman,
instead of all the arch-specific Makefile rules.


Feel free to submit subsequent patch, but this bug should be fixed
first, improvements can go in later.


Yes indeed. It looks like the maintainers are on this thread so they
should be able to pick it up.



Not sure if this was related to i.MX because it changes the main 
Makefile, but I admit I do not remember anymore if I have already merged 
and I found an issue or I have not seen and I ignored. I pick it up and 
I run CI.


Regards,
Stefano

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Re: [PATCH] arm: mach-imx: Fix speculative instruction prefetch issue

2021-05-02 Thread Stefano Babic

Hi Ye,

this patch is quite old and it looks like it was forgotten - I apply it 
and runs CI, but it breaks most arm board. So I have to drop it.


Best regards,
Stefano Babic

On 21.02.21 03:27, Ye Li wrote:

Default ARM32 MMU setting in u-boot sets XN bit to entire 4GB space no
matter which DCACHE option is used, and set domain permission to manager.
This causes MMU ignores the access check and XN bit, so speculative
instruction can fetch from entire space.

This patch sets the DDR, ROM, OCRAM without XN bit, and set domain to client
to enable the XN and access check. So speculative instruction fetch can only
happens on these 3 regions to avoid prefetch from peripherals and invalid
regions.

Signed-off-by: Ye Li 
Reviewed-by: Peng Fan 
---
  arch/arm/mach-imx/cache.c | 49 ---
  1 file changed, 42 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-imx/cache.c b/arch/arm/mach-imx/cache.c
index 4e3b49a..8486c2d 100644
--- a/arch/arm/mach-imx/cache.c
+++ b/arch/arm/mach-imx/cache.c
@@ -10,6 +10,10 @@
  #include 
  #include 
  #include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
  
  static void enable_ca7_smp(void)

  {
@@ -40,13 +44,13 @@ static void enable_ca7_smp(void)
  }
  
  #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)

+
+#define ARMV7_DOMAIN_CLIENT1
+#define ARMV7_DOMAIN_MASK  (0x3 << 0)
+#define IMX_ARMV7_DCACHE_OPTION (DCACHE_DEFAULT_OPTION & ~TTB_SECT_XN_MASK)
+
  void enable_caches(void)
  {
-#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
-   enum dcache_option option = DCACHE_WRITETHROUGH;
-#else
-   enum dcache_option option = DCACHE_WRITEBACK;
-#endif
/* Avoid random hang when download by usb */
invalidate_dcache_all();
  
@@ -59,11 +63,42 @@ void enable_caches(void)

/* Enable caching on OCRAM and ROM */
mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
ROMCP_ARB_END_ADDR,
-   option);
+   IMX_ARMV7_DCACHE_OPTION);
mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
IRAM_SIZE,
-   option);
+   IMX_ARMV7_DCACHE_OPTION);
+}
+
+void dram_bank_mmu_setup(int bank)
+{
+   struct bd_info *bd = gd->bd;
+   int i;
+
+   /* bd->bi_dram is available only after relocation */
+   if ((gd->flags & GD_FLG_RELOC) == 0)
+   return;
+
+   debug("%s: bank: %d\n", __func__, bank);
+   for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
+i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) +
+(bd->bi_dram[bank].size >> MMU_SECTION_SHIFT);
+i++)
+   set_section_dcache(i, IMX_ARMV7_DCACHE_OPTION);
  }
+
+void arm_init_domains(void)
+{
+   u32 reg;
+
+   reg = get_dacr();
+   /*
+   * Set domain to client to do access and XN check
+   */
+   reg &= ~ARMV7_DOMAIN_MASK;
+   reg |= ARMV7_DOMAIN_CLIENT;
+   set_dacr(reg);
+}
+
  #else
  void enable_caches(void)
  {



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Re: [PATCH 3/3] imx: ventana: enable dm support for PCI and FEC ethernet

2021-05-02 Thread Stefano Babic

Hi Tim,

I applied the first two patches of series, but this one has several 
conflicts in the configs file. Could you check and rebase it ? Thanks !


Best regards,
Stefano

On 16.04.21 23:53, Tim Harvey wrote:

Enable driver model support for FEC ethernet which allows us to remove
the iomux and board_eth_init function. Replace the toggling of the ethernet
phy reset with dt configuration.

Enable driver model support for PCI which allows us to remove the
eth1000_initialize() call. Additionally enable PCI_INIT_R to scan for
PCI devices on init such as the e1000 that is present on the GW552x.

Convert board_pci_fixup to use dm callback and remove pcidisable env
variable which is not supported for DM_PCI and thus leave PCI always
enabled during init.

Signed-off-by: Tim Harvey 
---
  arch/arm/dts/imx6qdl-gw51xx.dtsi|  2 +
  arch/arm/dts/imx6qdl-gw52xx.dtsi|  2 +
  arch/arm/dts/imx6qdl-gw53xx.dtsi|  3 +
  arch/arm/dts/imx6qdl-gw54xx.dtsi|  3 +
  arch/arm/dts/imx6qdl-gw560x.dtsi|  2 +
  arch/arm/dts/imx6qdl-gw5903.dtsi|  3 +
  arch/arm/dts/imx6qdl-gw5904.dtsi|  3 +
  arch/arm/dts/imx6qdl-gw5907.dtsi|  2 +
  arch/arm/dts/imx6qdl-gw5910.dtsi|  3 +
  arch/arm/dts/imx6qdl-gw5912.dtsi|  4 +
  arch/arm/dts/imx6qdl-gw5913.dtsi|  3 +
  board/gateworks/gw_ventana/common.h |  1 -
  board/gateworks/gw_ventana/gw_ventana.c | 99 -
  configs/gwventana_emmc_defconfig|  5 ++
  configs/gwventana_gw5904_defconfig  |  5 ++
  configs/gwventana_nand_defconfig|  5 ++
  include/configs/gw_ventana.h| 10 ---
  17 files changed, 61 insertions(+), 94 deletions(-)

diff --git a/arch/arm/dts/imx6qdl-gw51xx.dtsi b/arch/arm/dts/imx6qdl-gw51xx.dtsi
index 2a21c6731e..7e28463084 100644
--- a/arch/arm/dts/imx6qdl-gw51xx.dtsi
+++ b/arch/arm/dts/imx6qdl-gw51xx.dtsi
@@ -129,6 +129,8 @@
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
+   phy-reset-duration = <10>;
+   phy-reset-post-delay = <100>;
status = "okay";
  };
  
diff --git a/arch/arm/dts/imx6qdl-gw52xx.dtsi b/arch/arm/dts/imx6qdl-gw52xx.dtsi

index 6eedf8d40d..f1d9ba1fac 100644
--- a/arch/arm/dts/imx6qdl-gw52xx.dtsi
+++ b/arch/arm/dts/imx6qdl-gw52xx.dtsi
@@ -195,6 +195,8 @@
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
+   phy-reset-duration = <10>;
+   phy-reset-post-delay = <100>;
status = "okay";
  };
  
diff --git a/arch/arm/dts/imx6qdl-gw53xx.dtsi b/arch/arm/dts/imx6qdl-gw53xx.dtsi

index 9deec7e352..172a45ba17 100644
--- a/arch/arm/dts/imx6qdl-gw53xx.dtsi
+++ b/arch/arm/dts/imx6qdl-gw53xx.dtsi
@@ -188,6 +188,8 @@
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
+   phy-reset-duration = <10>;
+   phy-reset-post-delay = <100>;
status = "okay";
  };
  
@@ -597,6 +599,7 @@

MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC   0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK0x4001b0a8
+   MX6QDL_PAD_ENET_TXD0__GPIO1_IO300x1b0b0
>;
};
  
diff --git a/arch/arm/dts/imx6qdl-gw54xx.dtsi b/arch/arm/dts/imx6qdl-gw54xx.dtsi

index a30ba4848e..e09fad6068 100644
--- a/arch/arm/dts/imx6qdl-gw54xx.dtsi
+++ b/arch/arm/dts/imx6qdl-gw54xx.dtsi
@@ -225,6 +225,8 @@
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
+   phy-reset-duration = <10>;
+   phy-reset-post-delay = <100>;
status = "okay";
  };
  
@@ -675,6 +677,7 @@

MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC   0x1b0b0
MX6QDL_PAD_GPIO_16__ENET_REF_CLK0x4001b0a8
+   MX6QDL_PAD_ENET_TXD0__GPIO1_IO300x1b0b0
>;
};
  
diff --git a/arch/arm/dts/imx6qdl-gw560x.dtsi b/arch/arm/dts/imx6qdl-gw560x.dtsi

index 0786b0d546..bfe65fd3c0 100644
--- a/arch/arm/dts/imx6qdl-gw560x.dtsi
+++ b/arch/arm/dts/imx6qdl-gw560x.dtsi
@@ -279,6 +279,8 @@
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
+   phy-reset-duration = <10>;
+   phy-reset-post-delay = <100>;
status = "okay";
  };
  
diff --git a/arch/arm/dts/imx6qdl-gw5903.dtsi b/arch/arm/dts/imx6qdl-gw5903.dtsi

index 78f9ec90b7..6ebf6aef2f 100644
--- a/arch/arm/dts/imx6qdl-gw5903.dtsi
+++ b/arch/arm/dts/imx6qdl-gw5903.dtsi
@@ -223,6 +223,9 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
+   phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
+ 

[PATCH v3 1/4] arm64: dts: imx8mm: Add common -u-boot.dtsi

2021-05-02 Thread stefano . babic
> /soc@0
> aips1
> aips2
> aips3
> clk
> iomuxc
> osc_24m
> are common node enablements across imx8mm platform for dm-spi,
> dm-pre-reloc stages.
> Move them into common dtsi, imx8mm-u-boot.dtsi
> Cc: Tim Harvey 
> Cc: Adam Ford 
> Cc: Peng Fan 
> Cc: Teresa Remmet 
> Cc: Igor Opaniuk 
> Signed-off-by: Jagan Teki 
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

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[PATCH 7/7] include: configs: ge: avoid shell on boot failure

2021-05-02 Thread stefano . babic
> From: Ian Ray 
> Prevent shell access on boot failure by entering an infinite
> loop.
> Signed-off-by: Ian Ray 
> Signed-off-by: Sebastian Reichel 
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

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[PATCH v3 2/4] arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini SoM

2021-05-02 Thread stefano . babic
> i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini
> from Engicam.
> General features:
> - NXP i.MX8M Mini
> - Up to 2GB LDDR4
> - 8/16GB eMMC
> - Gigabit Ethernet
> - USB 2.0 Host/OTG
> - PCIe Gen2 interface
> - I2S
> - MIPI DSI to LVDS
> - rest of i.MX8M Mini features
> i.Core MX8M Mini needs to mount on top of Engicam baseboards
> for creating complete platform solutions.
> Linux dts commit details:
> commit <470d6dad5ddd> ("arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini
> SoM")
> Add support for it.
> Signed-off-by: Matteo Lisi 
> Signed-off-by: Jagan Teki 
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

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[PATCH 1/7] board: ge: bx50v3: fix crystal bit

2021-05-02 Thread stefano . babic
> The DA9063 enables the CRYSTAL bit by default, but there is no
> crystal populated on the BA16 system on module. Without explicitly
> clearing the CRYSTAL bit the system runs unstable and sometimes
> reboots unexpectedly.
> Signed-off-by: Sebastian Reichel 
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

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[PATCH 2/3] pci: pci-uclass: Add board_pci_fixup_dev for DM_PCI

2021-05-02 Thread stefano . babic
> Add a board_pci_fixup_dev weak function to allow PCI device fixups
> during enumeration.
> Signed-off-by: Tim Harvey 
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

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[PATCH] ARM:imx:imx8mq-cm: Add support for Ronetix iMX8MQ-CM

2021-05-02 Thread stefano . babic
> Supported peripherals: Ethernet, eMMC, Serial.
> U-Boot SPL 2021.04-00911-g5fa1e2ffeb-dirty (Apr 23 2021 - 09:11:14
> +0200)
> Normal Boot
> Trying to boot from MMC2
> U-Boot 2021.04-00911-g5fa1e2ffeb-dirty (Apr 23 2021 - 09:11:14 +0200)
> CPU:   Freescale i.MX8MQ rev2.1 at 1000 MHz
> Reset cause: POR
> Model: Ronetix iMX8M-CM SoM
> DRAM:  1 GiB
> WDT:   Started with servicing (60s timeout)
> MMC:   FSL_SDHC: 0, FSL_SDHC: 1
> Loading Environment from MMC... OK
> In:serial
> Out:   serial
> Err:   serial
> Net:
> Warning: ethernet@30be (eth0) using random MAC address -
> 42:0d:e7:78:da:53
> eth0: ethernet@30be
> Hit any key to stop autoboot:  0
> u-boot=>
> Signed-off-by: Ilko Iliev 
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

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Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
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[PATCH 3/7] configs: ge: bx50v3: adjust watchdog period

2021-05-02 Thread stefano . babic
> From: Ian Ray 
> Increase watchdog period, in order to accomodate recent kernel size
> and configuration changes.
> Signed-off-by: Ian Ray 
> Signed-off-by: Sebastian Reichel 
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

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[PATCH 2/2] arm: dts: imx6qdl-gw552x.dtsi: fix VBUS supply

2021-05-02 Thread stefano . babic
> Remove the invalid 'regulator-always-on' property to resolve:
> starting USB...
> Bus usb@2184000: Error enabling VBUS supply (ret=-13)
> probe failed, error -13
> Bus usb@2184200: USB EHCI 1.00
> Signed-off-by: Tim Harvey 
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

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[PATCH v2 1/2] net: fec: Don't use disabled phys

2021-05-02 Thread stefano . babic
> If a phy is disabled, don't use it. This matches Linux's behavior.
> Signed-off-by: Sean Anderson 
> Reviewed-by: Ramon Fried 
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

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[PATCH v2 2/2] net: fec: Only unregister MII bus if we registered it

2021-05-02 Thread stefano . babic
> If we fail to probe for whatever reason, we cannot unregister/free the
> MII bus unless we registered it with fec_get_miibus. This fixes FECs
> sharing an MDIO bus from destroying it, preventing the other FEC from
> using it.
> Fixes: 6a895d039b ("net: Update eQos driver and FEC driver to use eth phy 
> interfaces")
> Signed-off-by: Sean Anderson 
> Reviewed-by: Ramon Fried 
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

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[PATCH v3 4/4] board: imx8mm: Add Engicam i.Core MX8M Mini C.TOUCH 2.0

2021-05-02 Thread stefano . babic
> Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose Carrier
> board.
> Genaral features:
> - Ethernet 10/100
> - Wifi/BT
> - USB Type A/OTG
> - Audio Out
> - CAN
> - LVDS panel connector
> i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam.
> i.Core MX8M Mini needs to mount on top of this Carrier board for
> creating complete i.Core MX8M Mini C.TOUCH 2.0 board.
> Linux dts commit details:
> commit  ("arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini
> C.TOUCH 2.0")
> Add support for it.
> Signed-off-by: Jagan Teki 
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

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[PATCH 4/7] configs: ge: use non-persistent environment

2021-05-02 Thread stefano . babic
> From: Ian Ray 
> Disable the unused persistent environment.
> Signed-off-by: Ian Ray 
> Signed-off-by: Sebastian Reichel 
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

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[PATCH] imx: mkimage_fit_atf: fix file size reporting

2021-05-02 Thread stefano . babic
> instead using ls and awk to determine file size use stat instead.
> This fixes an invalid size reporting for user or group names that have
> spaces in them.
> This adds a dependency on the stat application which is part of
> the coreutils package which also includes ls.
> Signed-off-by: Tim Harvey 
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
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[PATCH 6/7] include: configs: ge: simplify default boot command

2021-05-02 Thread stefano . babic
> From: Ian Ray 
> Minor cosmetic changes to unify `CONFIG_EXTRA_ENV_SETTINGS'
> indentation between Bx50v3 and PPD to make comparison and
> review easier and simplify the default boot command.
> Signed-off-by: Ian Ray Ian Ray 
> Signed-off-by: Sebastian Reichel 
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
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Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
=


[PATCH 5/7] include: configs: ge: bx50v3: drop USB boot

2021-05-02 Thread stefano . babic
> From: Ian Ray 
> Remove unsupported USB boot.
> Signed-off-by: Ian Ray 
> Signed-off-by: Sebastian Reichel 
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
=


[PATCH] imx: imx8: Update README with somewhat correct firmware versions

2021-05-02 Thread stefano . babic
> From: Priit Laes 
> Current setup instructions for i.MX8QM MEK board include somewhat
> conflicting instructions, so here's an attempt to fix it.
> After trying both sets of firmwares, I can conclude that both of
> them fail to work:
> - no boot at all with imx-sc-firmware-0.7 / firmware-imx-7.6
> - partial success with imx-sc-firmware-1.1 / firmware-imx-8.0:
> U-Boot 2021.04-rc3-00135-ge0669a43c8 (Mar 08 2021 - 16:49:08 +0200)
> CPU:   NXP i.MX8QM RevB A53 at 1200 MHz
> Model: Freescale i.MX8QM MEK
> Board: iMX8QM MEK
> mu_hal_receivemsg timeout
> Build: SCFW 65afe5f6, SECO-FW 65afe5f6, ATF a-20190
> mu_hal_receivemsg timeout
> sc_misc_get_boot_dev: res:16
> Boot:  SD0
> DRAM:  mu_hal_sendmsg timeout
> sc_rm_is_memreg_owned: mr:0 res:21
> ...
> Signed-off-by: Priit Laes 
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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[PATCH v8 1/2] arm: dts: add imx8mm-cl-iot-gate dts file

2021-05-02 Thread stefano . babic
> From: "Ying-Chun Liu (PaulLiu)" 
> Add board dts for imx8mm-cl-iot-gate
> Signed-off-by: Kirill Kapranov 
> Signed-off-by: Uri Mashiach 
> Signed-off-by: Valentin Raevsky 
> Signed-off-by: Ying-Chun Liu (PaulLiu) 
> Cc: Peter Robinson 
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
=


[PATCH v3 3/4] board: imx8mm: Add Engicam i.Core MX8M Mini EDIMM2.2 Starter Kit

2021-05-02 Thread stefano . babic
> Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive
> Evaluation Board.
> Genaral features:
> - LCD 7" C.Touch
> - microSD slot
> - Ethernet 1Gb
> - Wifi/BT
> - 2x LVDS Full HD interfaces
> - 3x USB 2.0
> - 1x USB 3.0
> - HDMI Out
> - Mini PCIe
> - MIPI CSI
> - 2x CAN
> - Audio Out
> i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam.
> i.Core MX8M Mini needs to mount on top of this Evaluation board for
> creating complete i.Core MX8M Mini EDIMM2.2 Starter Kit.
> Linux dts commit details:
> commit <051c08eea682> ("arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini
> EDIMM2.2 Starter Kit")
> Add support for it.
> Signed-off-by: Jagan Teki 
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
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DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
=


[PATCH] pci: imx: disable imx6sdl LTSSM upon driver remove

2021-05-02 Thread stefano . babic
> commit 6ecbe1375671 ("drivers: pci: imx: add imx_pcie_remove function")
> attempted to resolve an issue caused by MX6QDL not having a proper
> intneral PCIe core reset and thus hanging during kernel init if the
> bootloader had enabled PCI.
> The issue exists for IMX6Q, IMX6D, IXM6S, and IMX6DL. Fix the case for
> IMX6S and IMX6DL getting missed.
> This fixes IMX6S and IMX6DL with PCI enabled in U-Boot booting for
> Linux v4.11+.
> Signed-off-by: Tim Harvey 
> Reviewed-by: Fabio Estevam 
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
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DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
=


[PATCH] Makefile: Fix generation of flash.bin u-boot.itb with binman

2021-05-02 Thread stefano . babic
> In case binman is enabled, the u-boot.itb is generated using this tool
> and there is no direct u-boot.itb target, but instead the binman tool
> must be invoked. Add support for this case.
> Signed-off-by: Marek Vasut 
> Cc: Peng Fan 
> Cc: Stefano Babic 
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
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DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
=


[PATCH v3] imx: Add support for Ronetix's iMX7-CM board

2021-05-02 Thread stefano . babic
> Console boot log:
> U-Boot SPL 2021.04-00836-ga6232e065d-dirty (Apr 16 2021 - 15:16:35 +0200)
> Trying to boot from MMC1
> U-Boot 2021.04-00836-ga6232e065d-dirty (Apr 16 2021 - 15:16:35 +0200)
> CPU:   Freescale i.MX7D rev1.3 1000 MHz (running at 792 MHz)
> CPU:   Commercial temperature grade (0C to 95C) at 44C
> Reset cause: POR
> Model: Ronetix iMX7-CM Board
> Board: iMX7-CM
> DRAM:  512 MiB
> PMIC:  PFUZE3000 DEV_ID=0x30 REV_ID=0x11
> MMC:   FSL_SDHC: 0, FSL_SDHC: 2
> Loading Environment from MMC... OK
> In:serial
> Out:   serial
> Err:   serial
> Net:
> Warning: ethernet@30be (eth0) using random MAC address - fe:be:37:01:5a:3f
> eth0: ethernet@30be
> Hit any key to stop autoboot:  0
> Signed-off-by: Ilko Iliev 
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
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[PATCH v8 2/2] arm: imx8m: add support for Compulab iot-gate-imx8 (imx8mm-cl-iot-gate)

2021-05-02 Thread stefano . babic
> From: "Ying-Chun Liu (PaulLiu)" 
> Add initial support for Compulab iot-gate-imx8 board (imx8mm-cl-iot-gate).
> The initial support includes:
>  - MMC
>  - eMMC
>  - I2C
>  - FEC
>  - Serial console
> Signed-off-by: Kirill Kapranov 
> Signed-off-by: Uri Mashiach 
> Signed-off-by: Valentin Raevsky 
> Signed-off-by: Ying-Chun Liu (PaulLiu) 
> Cc: Peter Robinson 
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
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[PATCH 1/2] imx: ventana: add delay before reading EEPROM

2021-05-02 Thread stefano . babic
> fixes: d863d054397a ("imx: ventana: convert U-Boot to OF_CONTROL using FIT 
> image")
> Signed-off-by: Tim Harvey 
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
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[PATCH 1/3] pci: Update the highest subordinate bus number for bridge setup

2021-05-02 Thread stefano . babic
> From: Masami Hiramatsu 
> Update the highest subordinate bus number after probing the devices
> under the bus for setting up the bridge correctly.
> The commit 42f3663a3f67 ("pci: Update to use new sequence numbers")
> removed this but it is required if a PCIe bridge is under the bus.
> Fixes: 42f3663a3f67 ("pci: Update to use new sequence numbers")
> Signed-off-by: Masami Hiramatsu 
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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[PATCH 2/7] board: ge: bx50v3: add phy reset GPIO

2021-05-02 Thread stefano . babic
> Add PHY's reset GPIO, so that U-Boot does a PHY hard reset.
> This is needed, since the PHY might become unresponsive if
> watchdog reboots the system while a transaction is ongoing.
> The reset GPIO is added to the U-Boot specific DT files, since
> the kernel does not setup the reserved registers correctly after
> resetting the PHY and thus must not reset it.
> Signed-off-by: Sebastian Reichel 
Applied to u-boot-imx, master, thanks !

Best regards,
Stefano Babic

-- 
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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[PATCH v2] imx8mn: configs: add support for distro boot commands

2021-05-02 Thread Andrey Zhizhikin
Supported boot device types in iMX8MN: MMC, DHCP.

Add DISTRO_DEFAULTS config option and include the distro boot command
header file to enable full support of distro boot on i.MX8M Nano EVK (both
DDR and LPDDR derivatives).

Drop previous environment, which was targeting customized boot commands and
boot order.

Signed-off-by: Andrey Zhizhikin 
Cc: Peng Fan 
---
Changes in v2:
- Correct fdt parameters: "fdt_file" -> "fdtfile", "fdt_addr" -> "fdt_addr_r"
- Set "kernel_addr_r" and "scriptaddr" from config

 configs/imx8mn_ddr4_evk_defconfig |  1 +
 configs/imx8mn_evk_defconfig  |  1 +
 include/configs/imx8mn_evk.h  | 68 +++
 3 files changed, 16 insertions(+), 54 deletions(-)

diff --git a/configs/imx8mn_ddr4_evk_defconfig 
b/configs/imx8mn_ddr4_evk_defconfig
index b10cd13fc3..1686e1a851 100644
--- a/configs/imx8mn_ddr4_evk_defconfig
+++ b/configs/imx8mn_ddr4_evk_defconfig
@@ -19,6 +19,7 @@ CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x4800
 CONFIG_DEFAULT_DEVICE_TREE="imx8mn-ddr4-evk"
+CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_FIT_EXTERNAL_OFFSET=0x3000
 CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/imx8mn_evk_defconfig b/configs/imx8mn_evk_defconfig
index d0e5b58902..14db624e29 100644
--- a/configs/imx8mn_evk_defconfig
+++ b/configs/imx8mn_evk_defconfig
@@ -22,6 +22,7 @@ CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 CONFIG_SPL=y
 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x4800
 CONFIG_DEFAULT_DEVICE_TREE="imx8mn-evk"
+CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_FIT_EXTERNAL_OFFSET=0x3000
 CONFIG_SPL_LOAD_FIT=y
diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h
index 596e255ca6..985bec803a 100644
--- a/include/configs/imx8mn_evk.h
+++ b/include/configs/imx8mn_evk.h
@@ -31,69 +31,29 @@
 
 #endif
 
+#ifndef CONFIG_SPL_BUILD
+#define BOOT_TARGET_DEVICES(func) \
+   func(MMC, mmc, 1) \
+   func(MMC, mmc, 2) \
+   func(DHCP, dhcp, na)
+
+#include 
+#endif
+
 /* Initial environment variables */
 #define CONFIG_EXTRA_ENV_SETTINGS  \
-   "script=boot.scr\0" \
"image=Image\0" \
+   BOOTENV \
+   "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
+   "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
"console=ttymxc1,115200\0" \
-   "fdt_addr=0x4300\0" \
+   "fdt_addr_r=0x4300\0"   \
"boot_fit=no\0" \
-   "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+   "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
"initrd_addr=0x4380\0"  \
"bootm_size=0x1000\0" \
-   "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
-   "mmcautodetect=yes\0" \
-   "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
-   "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} 
${script};\0" \
-   "bootscript=echo Running bootscript from mmc ...; " \
-   "source\0" \
-   "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
-   "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
-   "mmcboot=echo Booting from mmc ...; " \
-   "run mmcargs; " \
-   "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
-   "bootm ${loadaddr}; " \
-   "else " \
-   "if run loadfdt; then " \
-   "booti ${loadaddr} - ${fdt_addr}; " \
-   "else " \
-   "echo WARN: Cannot load the DT; " \
-   "fi; " \
-   "fi;\0" \
-   "netargs=setenv bootargs console=${console} " \
-   "root=/dev/nfs " \
-   "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
-   "netboot=echo Booting from net ...; " \
-   "run netargs;  " \
-   "if test ${ip_dyn} = yes; then " \
-   "setenv get_cmd dhcp; " \
-   "else " \
-   "setenv get_cmd tftp; " \
-   "fi; " \
-   "${get_cmd} ${loadaddr} ${image}; " \
-   "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
-   "bootm ${loadaddr}; " \
-   "else " \
-   "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
-   "booti ${loadaddr} - ${fdt_addr}; " \
-   "else " \
-   "echo WARN: Cannot load the DT; " \
-   "fi; " \
-   "fi;\0"
-
-#define CONFIG_BOOTCOMMAND \
-  "mmc dev ${mmcdev}; if mmc rescan; then " \
-  "if run loadbootscript; then " \
-  "run bootscript; " \
-  "else " \
-  "if run loadimage; then " \
-   

Re: sunxi_nand_spl reading zeros on NextThing C.H.I.P.

2021-05-02 Thread r315
Replying to myself,

I'm using sunxi driver for nand spl, had to remove ECC from "nand_read_page"
function, after that I was able to proceed to second stage of boot.

Not sure of the cause, maybe the u-boot_SPL ECC algorithm is different of
the one on u-boot, which is used to write u-boot on nand as described by
board/sunxi/README.md




--
Sent from: http://u-boot.10912.n7.nabble.com/


Re: [PATCH] arm: imx: imx8mm: correct unrecognized fracpll frequency

2021-05-02 Thread Fabio Estevam
On Sat, May 1, 2021 at 5:13 PM Andrey Zhizhikin
 wrote:
>
> Frequency requested by ddrphy_init_set_dfi_clk from fracpll uses MHZ()
> macro, which expands the value provided to the Hz range without taking into
> account the precise Hz setting. This causes the frequency of 266 MHz not ot
> be found in the imx8mm_fracpll_tbl, since it is entered there with a
> precise Hz value. This in turn causes the boot hang in SPL, as proper DDR
> fracpll frequency cannot be determined.
>
> Correct the value in imx8mm_fracpll_tbl to match the one expanded by
> MHZ(266) macro, rounding it down to MHz range only.
>
> Signed-off-by: Andrey Zhizhikin 
> Cc: Stefano Babic 
> Cc: Fabio Estevam 
> Cc: "NXP i.MX U-Boot Team" 
> Cc: Peng Fan 
> Cc: Simon Glass 
> Cc: Ye Li 
> Fixes: 825ab6b406 ("driver: ddr: Refine the ddr init driver on imx8m")

Reviewed-by: Fabio Estevam 


Re: [PATCH v2] imx8mn: configs: add support for distro boot commands

2021-05-02 Thread Fabio Estevam
Hi Andrey,

On Sun, May 2, 2021 at 11:33 AM Andrey Zhizhikin
 wrote:
>
> Supported boot device types in iMX8MN: MMC, DHCP.
>
> Add DISTRO_DEFAULTS config option and include the distro boot command
> header file to enable full support of distro boot on i.MX8M Nano EVK (both
> DDR and LPDDR derivatives).
>
> Drop previous environment, which was targeting customized boot commands and
> boot order.
>
> Signed-off-by: Andrey Zhizhikin 
> Cc: Peng Fan 
> ---
> Changes in v2:
> - Correct fdt parameters: "fdt_file" -> "fdtfile", "fdt_addr" -> "fdt_addr_r"

Yes, these are the preferred names according to the README file, thanks:

Reviewed-by: Fabio Estevam 


Re: [PATCH] arm: imx: imx8mm: correct unrecognized fracpll frequency

2021-05-02 Thread Fabio Estevam
Hi Andrey,

After re-reading the patch I have some comments:

On Sat, May 1, 2021 at 5:13 PM Andrey Zhizhikin
 wrote:
>
> Frequency requested by ddrphy_init_set_dfi_clk from fracpll uses MHZ()
> macro, which expands the value provided to the Hz range without taking into
> account the precise Hz setting. This causes the frequency of 266 MHz not ot
> be found in the imx8mm_fracpll_tbl, since it is entered there with a
> precise Hz value. This in turn causes the boot hang in SPL, as proper DDR
> fracpll frequency cannot be determined.
>
> Correct the value in imx8mm_fracpll_tbl to match the one expanded by
> MHZ(266) macro, rounding it down to MHz range only.
>
> Signed-off-by: Andrey Zhizhikin 
> Cc: Stefano Babic 
> Cc: Fabio Estevam 
> Cc: "NXP i.MX U-Boot Team" 
> Cc: Peng Fan 
> Cc: Simon Glass 
> Cc: Ye Li 
> Fixes: 825ab6b406 ("driver: ddr: Refine the ddr init driver on imx8m")
> ---
>  arch/arm/mach-imx/imx8m/clock_imx8mm.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c 
> b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> index 029d06f27f..86ff2b9cc9 100644
> --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> @@ -54,7 +54,7 @@ static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = 
> {
> PLL_1443X_RATE(6U, 300, 3, 2, 0),
> PLL_1443X_RATE(59400U, 99, 1, 2, 0),
> PLL_1443X_RATE(4U, 300, 9, 1, 0),
> -   PLL_1443X_RATE(26667U, 400, 9, 2, 0),
> +   PLL_1443X_RATE(26600U, 400, 9, 2, 0),

This change looks good.

> PLL_1443X_RATE(16700U, 334, 3, 4, 0),
> PLL_1443X_RATE(1U, 300, 9, 3, 0),
>  };
> @@ -72,7 +72,7 @@ static int fracpll_configure(enum pll_clocks pll, u32 freq)
> }
>
> if (i == ARRAY_SIZE(imx8mm_fracpll_tbl)) {
> -   printf("No matched freq table %u\n", freq);
> +   printf("%s: No matched freq table %u\n", __func__, freq);
> return -EINVAL;
> }
>
> @@ -148,7 +148,7 @@ void dram_enable_bypass(ulong clk_val)
> }
>
> if (i == ARRAY_SIZE(imx8mm_dram_bypass_tbl)) {
> -   printf("No matched freq table %lu\n", clk_val);
> +   printf("%s: No matched freq table %lu\n", __func__, clk_val);

, but these two I would put them on a separate patch.

Thanks


Re: [PATCH v7 0/8] Add FU740 chip and HiFive Unmatched board support

2021-05-02 Thread Green Wan
Thanks, Bin.

Hi Rick,

Not sure whether you have a chance to pick it up. Or let me know if
any part needs change.

Thanks,
- Green

On Thu, Apr 29, 2021 at 8:27 PM Bin Meng  wrote:
>
> Hi Green,
>
> On Thu, Apr 29, 2021 at 7:11 PM Green Wan  wrote:
> >
> > Hi Bin,
> >
> > How should this patch set be proceeded?
> >
> > To summary the major changes,
> > - I've rebased to mainstream and merged pcie refactoring code which
> > based on pcie_dw_common.c
> > - separate unmatched dts into separated patch.
> >
>
> I don't have specific comments. Rick should pick this up via the riscv
> tree. Thanks!
>
> Regards,
> Bin


Re: [PATCH v7 0/8] Add FU740 chip and HiFive Unmatched board support

2021-05-02 Thread Rick Chen
Hi Green,


I did not sign the Reviewed-by for this patch "board: sifive: add
HiFive Unmatched board support" from v1 to v6.
But it just has been tagged in [v7,7/8] board: sifive: add HiFive
Unmatched board support by yourself.

[v6,6/7] board: sifive: add HiFive Unmatched board support
https://patchwork.ozlabs.org/project/uboot/patch/20210408134020.238658-7-green@sifive.com/

[v7,7/8] board: sifive: add HiFive Unmatched board support
https://patchwork.ozlabs.org/project/uboot/patch/20210422091202.396956-8-green@sifive.com/

Actually I don't like this patch that you mix every things (arch/,
drivers/, common/, doc/)together in this patch.
But it is OK for now.

BTW, in [PATCH v7 1/8] riscv: cpu: fu740: Add support for cpu fu740
I found that arch/riscv/cpu/fu740/cpu.c and arch/riscv/fu540/cpu.c are
100% the same.

And about spl.c, they are only different in the annotation of Copyright
diff fu540/spl.c fu740/spl.c
3c3
<  * Copyright (C) 2020 SiFive, Inc
---
>  * Copyright (C) 2020-201 SiFive, Inc

About the cache.c, they are just different in one character

diff fu540/cache.c fu740/cache.c
3c3
<  * Copyright (C) 2020 SiFive, Inc
---
>  * Copyright (C) 2020-2021 SiFive, Inc
10d9
< #include 
12a12
> #include 
34c34
<"sifive,fu540-c000-ccache");
---
>"sifive,fu740-c000-ccache");


Originally, I am considering to tell you to re-use the same code base
instead of just copy and create.
After a few days of consideration, I feel it's OK for now.

About
[PATCH v7 2/8] drivers: clk: add fu740 support and
[PATCH v7 4/8] drivers: pci: add pcie support for fu740,
there are still not get any Reviewed-by till now.
For me, it will be better if someone can tag a Reviewed-by here.

Principally, it will be suggested to split drivers from RISC-V
relevant, do not mix them together as Palmer said.

Thanks,
Rick

> From: Bin Meng 
> Sent: Thursday, April 29, 2021 8:27 PM
> To: Green Wan 
> Cc: Rick Jian-Zhi Chen(陳建志) ; Paul Walmsley 
> ; Palmer Dabbelt ; Anup Patel 
> ; Atish Patra ; Lukasz Majewski 
> ; Joe Hershberger ; Ramon Fried 
> ; U-Boot Mailing List 
> Subject: Re: [PATCH v7 0/8] Add FU740 chip and HiFive Unmatched board support
>
> Hi Green,
>
> On Thu, Apr 29, 2021 at 7:11 PM Green Wan  wrote:
> >
> > Hi Bin,
> >
> > How should this patch set be proceeded?
> >
> > To summary the major changes,
> > - I've rebased to mainstream and merged pcie refactoring code which
> > based on pcie_dw_common.c
> > - separate unmatched dts into separated patch.
> >
>
> I don't have specific comments. Rick should pick this up via the riscv tree. 
> Thanks!
>
> Regards,
> Bin


[PATCH 0/4] malloc: Enable profiling dlmalloc with valgrind

2021-05-02 Thread Sean Anderson
This series adds support for running valgrind against U-Boot's internal
malloc. This allows for much more useful reports to be generated.


Sean Anderson (4):
  Add valgrind headers to U-Boot
  malloc: Annotate allocator for valgrind
  doc: sandbox: Document how to run sandbox with valgrind
  malloc: Fix sbrk clearing memory after freeing it instead of before

 Kconfig |   14 +
 Licenses/README |1 +
 Licenses/bzip2-1.0.6.txt|   30 +
 common/dlmalloc.c   |   39 +-
 common/malloc_simple.c  |   10 +
 doc/arch/sandbox.rst|   14 +-
 include/malloc.h|4 +
 include/valgrind/memcheck.h |  251 ++
 include/valgrind/valgrind.h | 7106 +++
 scripts/u-boot.supp |   30 +
 10 files changed, 7490 insertions(+), 9 deletions(-)
 create mode 100644 Licenses/bzip2-1.0.6.txt
 create mode 100644 include/valgrind/memcheck.h
 create mode 100644 include/valgrind/valgrind.h
 create mode 100644 scripts/u-boot.supp

-- 
2.31.0



[PATCH 3/4] doc: sandbox: Document how to run sandbox with valgrind

2021-05-02 Thread Sean Anderson
This documents how to get more detailed results from valgrind made possible
by the last two commits.

Signed-off-by: Sean Anderson 
---

 doc/arch/sandbox.rst | 14 ++
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/doc/arch/sandbox.rst b/doc/arch/sandbox.rst
index e052b6bdb0..9bc4fec5fe 100644
--- a/doc/arch/sandbox.rst
+++ b/doc/arch/sandbox.rst
@@ -481,14 +481,20 @@ Using valgrind / memcheck
 
 It is possible to run U-Boot under valgrind to check memory allocations::
 
-   valgrind u-boot
+valgrind ./u-boot
+
+For more detailed results, enable `CONFIG_VALGRIND`. There are many false
+positives due to `malloc` itself. Suppress these with::
+
+valgrind --suppressions=scripts/u-boot.supp ./u-boot
 
 If you are running sandbox SPL or TPL, then valgrind will not by default
 notice when U-Boot jumps from TPL to SPL, or from SPL to U-Boot proper. To
-fix this, use::
-
-   valgrind --trace-children=yes u-boot
+fix this, use `--trace-children=yes`. To show who alloc'd some troublesome
+memory, use `--track-origins=yes`. To uncover possible errors, try running all
+unit tests with::
 
+valgrind --track-origins=yes --suppressions=scripts/u-boot.supp ./u-boot 
-Tc 'ut all'
 
 Testing
 ---
-- 
2.31.0



[PATCH 2/4] malloc: Annotate allocator for valgrind

2021-05-02 Thread Sean Anderson
This annotates malloc and friends so that valgrind can track the heap. To
do this, we need to follow a few rules:

* Call VALGRIND_MALLOCLIKE_BLOCK whenever we malloc something
* Call VALGRIND_FREELIKE_BLOCK whenever we free something (generally after
  we have done our bookkeeping)
* Call VALGRIND_RESIZEINPLACE_BLOCK whenever we change the size of an
  allocation. Generally this just needs to happen in realloc, but only if
  the address stays the same.

In addition to the above, dlmalloc itself tends to make a lot of accesses
which we know are safe, but which would be unsafe outside of dlmalloc. For
this reason, we provide a suppression file which ignores errors ocurring in
dlmalloc.c

Signed-off-by: Sean Anderson 
---

 common/dlmalloc.c  | 29 -
 common/malloc_simple.c | 10 ++
 include/malloc.h   |  4 
 scripts/u-boot.supp| 30 ++
 4 files changed, 72 insertions(+), 1 deletion(-)
 create mode 100644 scripts/u-boot.supp

diff --git a/common/dlmalloc.c b/common/dlmalloc.c
index cf0270a9c1..05c8fd87e7 100644
--- a/common/dlmalloc.c
+++ b/common/dlmalloc.c
@@ -8,6 +8,7 @@
 
 #include 
 #include 
+#include 
 
 #ifdef DEBUG
 #if __STD_C
@@ -1329,6 +1330,7 @@ Void_t* mALLOc(bytes) size_t bytes;
   unlink(victim, bck, fwd);
   set_inuse_bit_at_offset(victim, victim_size);
   check_malloced_chunk(victim, nb);
+  VALGRIND_MALLOCLIKE_BLOCK(chunk2mem(victim), bytes, SIZE_SZ, false);
   return chunk2mem(victim);
 }
 
@@ -1356,6 +1358,7 @@ Void_t* mALLOc(bytes) size_t bytes;
unlink(victim, bck, fwd);
set_inuse_bit_at_offset(victim, victim_size);
check_malloced_chunk(victim, nb);
+VALGRIND_MALLOCLIKE_BLOCK(chunk2mem(victim), bytes, SIZE_SZ, false);
return chunk2mem(victim);
   }
 }
@@ -1379,6 +1382,7 @@ Void_t* mALLOc(bytes) size_t bytes;
   set_head(remainder, remainder_size | PREV_INUSE);
   set_foot(remainder, remainder_size);
   check_malloced_chunk(victim, nb);
+  VALGRIND_MALLOCLIKE_BLOCK(chunk2mem(victim), bytes, SIZE_SZ, false);
   return chunk2mem(victim);
 }
 
@@ -1388,6 +1392,7 @@ Void_t* mALLOc(bytes) size_t bytes;
 {
   set_inuse_bit_at_offset(victim, victim_size);
   check_malloced_chunk(victim, nb);
+  VALGRIND_MALLOCLIKE_BLOCK(chunk2mem(victim), bytes, SIZE_SZ, false);
   return chunk2mem(victim);
 }
 
@@ -1443,6 +1448,7 @@ Void_t* mALLOc(bytes) size_t bytes;
set_head(remainder, remainder_size | PREV_INUSE);
set_foot(remainder, remainder_size);
check_malloced_chunk(victim, nb);
+   VALGRIND_MALLOCLIKE_BLOCK(chunk2mem(victim), bytes, SIZE_SZ, false);
return chunk2mem(victim);
  }
 
@@ -1451,6 +1457,7 @@ Void_t* mALLOc(bytes) size_t bytes;
set_inuse_bit_at_offset(victim, victim_size);
unlink(victim, bck, fwd);
check_malloced_chunk(victim, nb);
+   VALGRIND_MALLOCLIKE_BLOCK(chunk2mem(victim), bytes, SIZE_SZ, false);
return chunk2mem(victim);
  }
 
@@ -1499,6 +1506,7 @@ Void_t* mALLOc(bytes) size_t bytes;
 /* If big and would otherwise need to extend, try to use mmap instead */
 if ((unsigned long)nb >= (unsigned long)mmap_threshold &&
(victim = mmap_chunk(nb)))
+  VALGRIND_MALLOCLIKE_BLOCK(chunk2mem(victim), bytes, SIZE_SZ, false);
   return chunk2mem(victim);
 #endif
 
@@ -1513,6 +1521,7 @@ Void_t* mALLOc(bytes) size_t bytes;
   top = chunk_at_offset(victim, nb);
   set_head(top, remainder_size | PREV_INUSE);
   check_malloced_chunk(victim, nb);
+  VALGRIND_MALLOCLIKE_BLOCK(chunk2mem(victim), bytes, SIZE_SZ, false);
   return chunk2mem(victim);
 
 }
@@ -1561,8 +1570,10 @@ void fREe(mem) Void_t* mem;
 
 #if CONFIG_VAL(SYS_MALLOC_F_LEN)
/* free() is a no-op - all the memory will be freed on relocation */
-   if (!(gd->flags & GD_FLG_FULL_MALLOC_INIT))
+   if (!(gd->flags & GD_FLG_FULL_MALLOC_INIT)) {
+   VALGRIND_FREELIKE_BLOCK(mem, SIZE_SZ);
return;
+   }
 #endif
 
   if (mem == NULL)  /* free(0) has no effect */
@@ -1584,6 +1595,7 @@ void fREe(mem) Void_t* mem;
   sz = hd & ~PREV_INUSE;
   next = chunk_at_offset(p, sz);
   nextsz = chunksize(next);
+  VALGRIND_FREELIKE_BLOCK(mem, SIZE_SZ);
 
   if (next == top)/* merge with top */
   {
@@ -1772,6 +1784,8 @@ Void_t* rEALLOc(oldmem, bytes) Void_t* oldmem; size_t 
bytes;
  top = chunk_at_offset(oldp, nb);
  set_head(top, (newsize - nb) | PREV_INUSE);
  set_head_size(oldp, nb);
+ VALGRIND_RESIZEINPLACE_BLOCK(chunk2mem(oldp), oldsize, bytes,
+  SIZE_SZ);
  return chunk2mem(oldp);
}
   }
@@ -1810,10 +1824,12 @@ Void_t* rEALLOc(oldmem, bytes) Void_t* oldmem; size_t 
bytes;
newp = prev;
newsize += prevsize 

[PATCH 4/4] malloc: Fix sbrk clearing memory after freeing it instead of before

2021-05-02 Thread Sean Anderson
This fixes memory being cleared after releasing it. Instead, clear memory
before releasing it. In addition, suppress valgrind warnings about writing
to free'd memory.

Signed-off-by: Sean Anderson 
---

 common/dlmalloc.c | 10 ++
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/common/dlmalloc.c b/common/dlmalloc.c
index 05c8fd87e7..ea51bdf6a6 100644
--- a/common/dlmalloc.c
+++ b/common/dlmalloc.c
@@ -592,11 +592,13 @@ void *sbrk(ptrdiff_t increment)
ulong new = old + increment;
 
/*
-* if we are giving memory back make sure we clear it out since
-* we set MORECORE_CLEARS to 1
+* if we are allocating memory make sure we clear it out since we set
+* MORECORE_CLEARS to 1
 */
-   if (increment < 0)
-   memset((void *)new, 0, -increment);
+   if (increment > 0) {
+   VALGRIND_MAKE_MEM_UNDEFINED(old, increment);
+   memset((void *)old, 0, increment);
+   }
 
if ((new < mem_malloc_start) || (new > mem_malloc_end))
return (void *)MORECORE_FAILURE;
-- 
2.31.0



Re: [PATCH v7 0/8] Add FU740 chip and HiFive Unmatched board support

2021-05-02 Thread Green Wan
Hi Rick,

Thanks for quick response. See my reply below.

On Mon, May 3, 2021 at 10:34 AM Rick Chen  wrote:
>
> Hi Green,
>
>
> I did not sign the Reviewed-by for this patch "board: sifive: add
> HiFive Unmatched board support" from v1 to v6.
> But it just has been tagged in [v7,7/8] board: sifive: add HiFive
> Unmatched board support by yourself.

Sorry, I might have a quick conclusion when Reviewed-by is on our
previous discussion in [v6 1/7]. We ended up splitting dts into two.
One for fu740 and the other for Unmatched board specifically. And put
them closer. Then, I added the review-by to them.

 Here is the previous discussion. 
"Makefile need the dts file, but it is not exist in this patch. It
doesn't make sense.

Maybe you can combine with the dts relative files in [PATCH v6 6/7]
into one patch and name as :
riscv: dts: ...

LGTM.
Other than that,

Reviewed-by: Rick Chen  "

"It is OK.

You may arrange them nearby as below:
6/x riscv: dts: support fu740
7/x riscv: dst: support HiFive Unmatched board

Thanks,
Rick"

>
> [v6,6/7] board: sifive: add HiFive Unmatched board support
> https://patchwork.ozlabs.org/project/uboot/patch/20210408134020.238658-7-green@sifive.com/
>
> [v7,7/8] board: sifive: add HiFive Unmatched board support
> https://patchwork.ozlabs.org/project/uboot/patch/20210422091202.396956-8-green@sifive.com/
>
> Actually I don't like this patch that you mix every things (arch/,
> drivers/, common/, doc/)together in this patch.
> But it is OK for now.

Noted. Thanks for reminding me.

>
> BTW, in [PATCH v7 1/8] riscv: cpu: fu740: Add support for cpu fu740
> I found that arch/riscv/cpu/fu740/cpu.c and arch/riscv/fu540/cpu.c are
> 100% the same.
>
> And about spl.c, they are only different in the annotation of Copyright
> diff fu540/spl.c fu740/spl.c
> 3c3
> <  * Copyright (C) 2020 SiFive, Inc
> ---
> >  * Copyright (C) 2020-201 SiFive, Inc
>
> About the cache.c, they are just different in one character
>
> diff fu540/cache.c fu740/cache.c
> 3c3
> <  * Copyright (C) 2020 SiFive, Inc
> ---
> >  * Copyright (C) 2020-2021 SiFive, Inc
> 10d9
> < #include 
> 12a12
> > #include 
> 34c34
> <"sifive,fu540-c000-ccache");
> ---
> >"sifive,fu740-c000-ccache");
>
>
> Originally, I am considering to tell you to re-use the same code base
> instead of just copy and create.
> After a few days of consideration, I feel it's OK for now.
>
You're right. As you mentioned, I also considered having common code.
But I conservatively decided to keep separated files to handle
possible differences among chips.

> About
> [PATCH v7 2/8] drivers: clk: add fu740 support and
> [PATCH v7 4/8] drivers: pci: add pcie support for fu740,
> there are still not get any Reviewed-by till now.
> For me, it will be better if someone can tag a Reviewed-by here.
>
> Principally, it will be suggested to split drivers from RISC-V
> relevant, do not mix them together as Palmer said.

Not sure whether we'll have the driver reviewers very quick. What do
you think of moving forward? I can try to ping some driver maintainers
and see if we have someone to review them. =]

Thanks,



>
> Thanks,
> Rick
>
> > From: Bin Meng 
> > Sent: Thursday, April 29, 2021 8:27 PM
> > To: Green Wan 
> > Cc: Rick Jian-Zhi Chen(陳建志) ; Paul Walmsley 
> > ; Palmer Dabbelt ; Anup Patel 
> > ; Atish Patra ; Lukasz Majewski 
> > ; Joe Hershberger ; Ramon Fried 
> > ; U-Boot Mailing List 
> > Subject: Re: [PATCH v7 0/8] Add FU740 chip and HiFive Unmatched board 
> > support
> >
> > Hi Green,
> >
> > On Thu, Apr 29, 2021 at 7:11 PM Green Wan  wrote:
> > >
> > > Hi Bin,
> > >
> > > How should this patch set be proceeded?
> > >
> > > To summary the major changes,
> > > - I've rebased to mainstream and merged pcie refactoring code which
> > > based on pcie_dw_common.c
> > > - separate unmatched dts into separated patch.
> > >
> >
> > I don't have specific comments. Rick should pick this up via the riscv 
> > tree. Thanks!
> >
> > Regards,
> > Bin


Re: [PATCH v7 0/8] Add FU740 chip and HiFive Unmatched board support

2021-05-02 Thread Rick Chen
Hi Green,

> Hi Rick,
>
> Thanks for quick response. See my reply below.
>
> On Mon, May 3, 2021 at 10:34 AM Rick Chen  wrote:
> >
> > Hi Green,
> >
> >
> > I did not sign the Reviewed-by for this patch "board: sifive: add
> > HiFive Unmatched board support" from v1 to v6.
> > But it just has been tagged in [v7,7/8] board: sifive: add HiFive
> > Unmatched board support by yourself.
>
> Sorry, I might have a quick conclusion when Reviewed-by is on our
> previous discussion in [v6 1/7]. We ended up splitting dts into two.
> One for fu740 and the other for Unmatched board specifically. And put
> them closer. Then, I added the review-by to them.
>
>  Here is the previous discussion. 
> "Makefile need the dts file, but it is not exist in this patch. It
> doesn't make sense.
>
> Maybe you can combine with the dts relative files in [PATCH v6 6/7]
> into one patch and name as :
> riscv: dts: ...
>
> LGTM.
> Other than that,
>
> Reviewed-by: Rick Chen  "
>
> "It is OK.
>
> You may arrange them nearby as below:
> 6/x riscv: dts: support fu740
> 7/x riscv: dst: support HiFive Unmatched board
>
> Thanks,
> Rick"
>
> >
> > [v6,6/7] board: sifive: add HiFive Unmatched board support
> > https://patchwork.ozlabs.org/project/uboot/patch/20210408134020.238658-7-green@sifive.com/
> >
> > [v7,7/8] board: sifive: add HiFive Unmatched board support
> > https://patchwork.ozlabs.org/project/uboot/patch/20210422091202.396956-8-green@sifive.com/
> >
> > Actually I don't like this patch that you mix every things (arch/,
> > drivers/, common/, doc/)together in this patch.
> > But it is OK for now.
>
> Noted. Thanks for reminding me.
>
> >
> > BTW, in [PATCH v7 1/8] riscv: cpu: fu740: Add support for cpu fu740
> > I found that arch/riscv/cpu/fu740/cpu.c and arch/riscv/fu540/cpu.c are
> > 100% the same.
> >
> > And about spl.c, they are only different in the annotation of Copyright
> > diff fu540/spl.c fu740/spl.c
> > 3c3
> > <  * Copyright (C) 2020 SiFive, Inc
> > ---
> > >  * Copyright (C) 2020-201 SiFive, Inc
> >
> > About the cache.c, they are just different in one character
> >
> > diff fu540/cache.c fu740/cache.c
> > 3c3
> > <  * Copyright (C) 2020 SiFive, Inc
> > ---
> > >  * Copyright (C) 2020-2021 SiFive, Inc
> > 10d9
> > < #include 
> > 12a12
> > > #include 
> > 34c34
> > <"sifive,fu540-c000-ccache");
> > ---
> > >"sifive,fu740-c000-ccache");
> >
> >
> > Originally, I am considering to tell you to re-use the same code base
> > instead of just copy and create.
> > After a few days of consideration, I feel it's OK for now.
> >
> You're right. As you mentioned, I also considered having common code.
> But I conservatively decided to keep separated files to handle
> possible differences among chips.
>
> > About
> > [PATCH v7 2/8] drivers: clk: add fu740 support and
> > [PATCH v7 4/8] drivers: pci: add pcie support for fu740,
> > there are still not get any Reviewed-by till now.
> > For me, it will be better if someone can tag a Reviewed-by here.
> >
> > Principally, it will be suggested to split drivers from RISC-V
> > relevant, do not mix them together as Palmer said.
>
> Not sure whether we'll have the driver reviewers very quick. What do
> you think of moving forward? I can try to ping some driver maintainers
> and see if we have someone to review them. =]

OK.
Maybe let's just wait for a period of time, if it still no furthermore response.
I can help to pull them via riscv tree.

Thanks,
Rick

>
> Thanks,
>
>
>
> >
> > Thanks,
> > Rick
> >
> > > From: Bin Meng 
> > > Sent: Thursday, April 29, 2021 8:27 PM
> > > To: Green Wan 
> > > Cc: Rick Jian-Zhi Chen(陳建志) ; Paul Walmsley 
> > > ; Palmer Dabbelt ; Anup 
> > > Patel ; Atish Patra ; Lukasz 
> > > Majewski ; Joe Hershberger ; Ramon 
> > > Fried ; U-Boot Mailing List 
> > > Subject: Re: [PATCH v7 0/8] Add FU740 chip and HiFive Unmatched board 
> > > support
> > >
> > > Hi Green,
> > >
> > > On Thu, Apr 29, 2021 at 7:11 PM Green Wan  wrote:
> > > >
> > > > Hi Bin,
> > > >
> > > > How should this patch set be proceeded?
> > > >
> > > > To summary the major changes,
> > > > - I've rebased to mainstream and merged pcie refactoring code which
> > > > based on pcie_dw_common.c
> > > > - separate unmatched dts into separated patch.
> > > >
> > >
> > > I don't have specific comments. Rick should pick this up via the riscv 
> > > tree. Thanks!
> > >
> > > Regards,
> > > Bin


Re: [PATCH v6 2/7] riscv: cpu: fu740: Add support for cpu fu740

2021-05-02 Thread Rick Chen
> From: Green Wan [mailto:green@sifive.com]
> Sent: Thursday, April 08, 2021 9:40 PM
> Cc: bmeng...@gmail.com; Green Wan ; Rick Jian-Zhi 
> Chen(陳建志) ; Paul Walmsley ; 
> Palmer Dabbelt ; Anup Patel ; Atish 
> Patra ; Pragnesh Patel ; 
> Lukasz Majewski ; Joe Hershberger ; 
> Ramon Fried ; u-boot@lists.denx.de
> Subject: [PATCH v6 2/7] riscv: cpu: fu740: Add support for cpu fu740
>
> Add SiFive fu740 cpu to support RISC-V arch
>
> Signed-off-by: Green Wan 
> Reviewed-by: Bin Meng 
> ---
>  arch/riscv/Kconfig|  1 +
>  arch/riscv/cpu/fu740/Kconfig  | 37 +++
>  arch/riscv/cpu/fu740/Makefile | 12 +
>  arch/riscv/cpu/fu740/cache.c  | 55 +++
>  arch/riscv/cpu/fu740/cpu.c| 22 +
>  arch/riscv/cpu/fu740/dram.c   | 38 
>  arch/riscv/cpu/fu740/spl.c| 23 ++
>  arch/riscv/include/asm/arch-fu740/cache.h | 14 ++
>  arch/riscv/include/asm/arch-fu740/clk.h   | 14 ++
>  arch/riscv/include/asm/arch-fu740/gpio.h  | 38   
> arch/riscv/include/asm/arch-fu740/reset.h | 13 ++
>  arch/riscv/include/asm/arch-fu740/spl.h   | 14 ++
>  arch/riscv/lib/sifive_clint.c |  1 -

Refer to comments about [PATCH v7 1/8].
https://www.mail-archive.com/u-boot@lists.denx.de/msg405522.html
Hope same code base can be effective re-use in the future.

Reviewed-by: Rick Chen 


[PATCH v1 2/2] arm: octeontx2: Add Octeon TX2 CN9132 DB support

2021-05-02 Thread Stefan Roese
From: Konstantin Porotchkin 

This patch adds the base support for the Marvell Octeon TX2 CN9132 DB.
Two versions are currently added via different defconfig's, one for
booting via SPI NOR and one for NAND booting. Not all interfaces are
supported fully yet.

Signed-off-by: Konstantin Porotchkin 
Signed-off-by: Stefan Roese 

---

 board/Marvell/octeontx2_cn913x/MAINTAINERS |  2 +
 configs/mvebu_db_cn9132_defconfig  | 88 +
 configs/mvebu_db_cn9132_nand_defconfig | 89 ++
 3 files changed, 179 insertions(+)
 create mode 100644 configs/mvebu_db_cn9132_defconfig
 create mode 100644 configs/mvebu_db_cn9132_nand_defconfig

diff --git a/board/Marvell/octeontx2_cn913x/MAINTAINERS 
b/board/Marvell/octeontx2_cn913x/MAINTAINERS
index d469e16ea753..5ce23c80f6b2 100644
--- a/board/Marvell/octeontx2_cn913x/MAINTAINERS
+++ b/board/Marvell/octeontx2_cn913x/MAINTAINERS
@@ -3,3 +3,5 @@ M:  Kostya Porotchkin 
 S: Maintained
 F: board/Marvell/octeontx2_cn913x/
 F: configs/mvebu_crb_cn9130_defconfig
+F: configs/mvebu_db_cn9132_defconfig
+F: configs/mvebu_db_cn9132_nand_defconfig
diff --git a/configs/mvebu_db_cn9132_defconfig 
b/configs/mvebu_db_cn9132_defconfig
new file mode 100644
index ..7efb690c66a4
--- /dev/null
+++ b/configs/mvebu_db_cn9132_defconfig
@@ -0,0 +1,88 @@
+CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_TEXT_BASE=0x
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_TARGET_OCTEONTX2_CN913x=y
+CONFIG_ENV_SIZE=0x1
+CONFIG_ENV_OFFSET=0x3f
+CONFIG_ENV_SECT_SIZE=0x1
+CONFIG_DM_GPIO=y
+CONFIG_DEBUG_UART_BASE=0xf0512000
+CONFIG_DEBUG_UART_CLOCK=2
+CONFIG_DEFAULT_DEVICE_TREE="cn9132-db-A"
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_ARCH_EARLY_INIT_R=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SYS_PROMPT="Marvell>> "
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_MVEBU_BUBT=y
+CONFIG_MVEBU_MMC_BOOT=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_AHCI_MVEBU=y
+CONFIG_DM_GPIO_LOOKUP_LABEL=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_MISC=y
+CONFIG_MVEBU_SAR=y
+CONFIG_MMC_BROKEN_CD=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_XENON=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_GIGE=y
+CONFIG_MVPP2=y
+CONFIG_NVME=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCIE_DW_MVEBU=y
+CONFIG_MVEBU_COMPHY_SUPPORT=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_ARMADA_8K=y
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_SYS_NS16550=y
+CONFIG_KIRKWOOD_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
diff --git a/configs/mvebu_db_cn9132_nand_defconfig 
b/configs/mvebu_db_cn9132_nand_defconfig
new file mode 100644
index ..ee6e01091404
--- /dev/null
+++ b/configs/mvebu_db_cn9132_nand_defconfig
@@ -0,0 +1,89 @@
+CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_TEXT_BASE=0x
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_TARGET_OCTEONTX2_CN913x=y
+CONFIG_ENV_SIZE=0x4
+CONFIG_ENV_OFFSET=0x3c
+CONFIG_DM_GPIO=y
+CONFIG_DEBUG_UART_BASE=0xf0512000
+CONFIG_DEBUG_UART_CLOCK=2
+CONFIG_DEFAULT_DEVICE_TREE="cn9132-db-B"
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_ARCH_EARLY_INIT_R=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SYS_PROMPT="Marvell>> "
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_MVEBU_BUBT=y
+CONFIG_MVEBU_NAND_BOOT=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_AHCI_MVEBU=y
+CONFIG_DM_GPIO_LOOKUP_LABEL=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CO

[PATCH v1 0/2] arm: octeontx2: Add base support for Marvell OcteonTX2 CN9132 DB

2021-05-02 Thread Stefan Roese


This patchset adds the base support for the Marvell OcteonTX2 CN9132 DB
board and includes required dts/dtsi files and the defconfig files for
this.

Thanks,
Stefan


Stefan Roese (2):
  arm: octeontx2: Add dtsi/dts files for Octeon TX2 CN9132 DB
  arm: octeontx2: Add Octeon TX2 CN9132 DB support

 arch/arm/dts/Makefile  |   6 +
 arch/arm/dts/cn9130-db-A.dts   | 212 
 arch/arm/dts/cn9130-db-B.dts   | 223 +
 arch/arm/dts/cn9130-db-dev-info.dtsi   |  44 
 arch/arm/dts/cn9130-db.dtsi| 133 
 arch/arm/dts/cn9131-db-A.dts   |  54 +
 arch/arm/dts/cn9131-db-B.dts   |  69 +++
 arch/arm/dts/cn9131-db.dtsi| 166 +++
 arch/arm/dts/cn9132-db-A.dts   | 103 ++
 arch/arm/dts/cn9132-db-B.dts   | 103 ++
 arch/arm/dts/cn9132-db.dtsi| 130 
 board/Marvell/octeontx2_cn913x/MAINTAINERS |   2 +
 configs/mvebu_db_cn9132_defconfig  |  88 
 configs/mvebu_db_cn9132_nand_defconfig |  89 
 14 files changed, 1422 insertions(+)
 create mode 100644 arch/arm/dts/cn9130-db-A.dts
 create mode 100644 arch/arm/dts/cn9130-db-B.dts
 create mode 100644 arch/arm/dts/cn9130-db-dev-info.dtsi
 create mode 100644 arch/arm/dts/cn9130-db.dtsi
 create mode 100644 arch/arm/dts/cn9131-db-A.dts
 create mode 100644 arch/arm/dts/cn9131-db-B.dts
 create mode 100644 arch/arm/dts/cn9131-db.dtsi
 create mode 100644 arch/arm/dts/cn9132-db-A.dts
 create mode 100644 arch/arm/dts/cn9132-db-B.dts
 create mode 100644 arch/arm/dts/cn9132-db.dtsi
 create mode 100644 configs/mvebu_db_cn9132_defconfig
 create mode 100644 configs/mvebu_db_cn9132_nand_defconfig

-- 
2.31.1



[PATCH v1 1/2] arm: octeontx2: Add dtsi/dts files for Octeon TX2 CN9132 DB

2021-05-02 Thread Stefan Roese
From: Konstantin Porotchkin 

This patch adds the dtsi/dts files needed to support the Marvell
Octeon TX2 CN9132 DB. This is only the base port with not all
interfaces supported fully.

Signed-off-by: Konstantin Porotchkin 
Signed-off-by: Stefan Roese 
---

 arch/arm/dts/Makefile|   6 +
 arch/arm/dts/cn9130-db-A.dts | 212 +
 arch/arm/dts/cn9130-db-B.dts | 223 +++
 arch/arm/dts/cn9130-db-dev-info.dtsi |  44 ++
 arch/arm/dts/cn9130-db.dtsi  | 133 
 arch/arm/dts/cn9131-db-A.dts |  54 +++
 arch/arm/dts/cn9131-db-B.dts |  69 +
 arch/arm/dts/cn9131-db.dtsi  | 166 
 arch/arm/dts/cn9132-db-A.dts | 103 +
 arch/arm/dts/cn9132-db-B.dts | 103 +
 arch/arm/dts/cn9132-db.dtsi  | 130 
 11 files changed, 1243 insertions(+)
 create mode 100644 arch/arm/dts/cn9130-db-A.dts
 create mode 100644 arch/arm/dts/cn9130-db-B.dts
 create mode 100644 arch/arm/dts/cn9130-db-dev-info.dtsi
 create mode 100644 arch/arm/dts/cn9130-db.dtsi
 create mode 100644 arch/arm/dts/cn9131-db-A.dts
 create mode 100644 arch/arm/dts/cn9131-db-B.dts
 create mode 100644 arch/arm/dts/cn9131-db.dtsi
 create mode 100644 arch/arm/dts/cn9132-db-A.dts
 create mode 100644 arch/arm/dts/cn9132-db-B.dts
 create mode 100644 arch/arm/dts/cn9132-db.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a5cae010c263..92e68ca4361b 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -237,6 +237,12 @@ dtb-$(CONFIG_ARCH_MVEBU) +=\
armada-xp-maxbcm.dtb\
armada-xp-synology-ds414.dtb\
armada-xp-theadorable.dtb   \
+   cn9130-db-A.dtb \
+   cn9130-db-B.dtb \
+   cn9131-db-A.dtb \
+   cn9131-db-B.dtb \
+   cn9132-db-A.dtb \
+   cn9132-db-B.dtb \
cn9130-crb-A.dtb\
cn9130-crb-B.dtb
 
diff --git a/arch/arm/dts/cn9130-db-A.dts b/arch/arm/dts/cn9130-db-A.dts
new file mode 100644
index ..ab61eb97f0a8
--- /dev/null
+++ b/arch/arm/dts/cn9130-db-A.dts
@@ -0,0 +1,212 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ */
+
+#include "cn9130-db.dtsi"
+
+/ {
+   model = "Marvell CN9130 development board (CP NOR) setup(A)";
+   compatible = "marvell,cn9130-db", "marvell,cn91xx", "marvell,cn9030-vd",
+"marvell,cn9030", "marvell,armada-ap806-quad",
+"marvell,armada-ap806";
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   aliases {
+   i2c0 = &cp0_i2c0;
+   spi0 = &cp0_spi1;
+   gpio0 = &ap_gpio0;
+   gpio1 = &cp0_gpio0;
+   gpio2 = &cp0_gpio1;
+   };
+
+   memory@ {
+   device_type = "memory";
+   reg = <0x0 0x0 0x0 0x8000>;
+   };
+};
+
+&uart0 {
+   status = "okay";
+};
+
+/*
+ * AP related configuration
+ */
+&ap_pinctl {
+   /* MPP Bus:
+* SDIO  [0-10, 12]
+* UART0 [11,19]
+*/
+   /*   0 1 2 3 4 5 6 7 8 9 */
+   pin-func = < 1 1 1 1 1 1 1 1 1 1
+1 3 1 0 0 0 0 0 0 3 >;
+};
+
+/*
+ * CP related configuration
+ */
+&cp0_pinctl {
+   /* MPP Bus:
+*  [0-11]  RGMII1
+*  [12]GPIO GE-IN
+*  [13-16] SPI1
+*  [17-27] NAND
+*  [28]MSS_GPIO[5] XXX:(mode nr from a3900)
+*  [29-30] SATA
+*  [31]MSS_GPIO[4] XXX:(mode nr from a3900)
+*  [32,34] SMI
+*  [33]SDIO
+*  [35-36] I2C1
+*  [37-38] I2C0
+*  [39-43] SDIOctrl
+*  [44-55] RGMII2
+*  [56-62] SDIO
+*/
+
+   /*   0   1   2   3   4   5   6   7   8   9 */
+   pin-func = < 3   3   3   3   3   3   3   3   3   3
+3   3   0   3   3   3   3   1   1   1
+1   1   1   1   1   1   1   1   3   9
+9   3   7   6   7   2   2   2   2   1
+1   1   1   1   1   1   1   1   1   1
+1   1   1   1   1   1   0xe 0xe 0xe 0xe
+0xe 0xe 0xe>;
+};
+
+&cp0_i2c0 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&cp0_i2c0_pins>;
+   status = "okay";
+   clock-frequency = <10>;
+};
+
+&cp0_i2c1 {
+   status = "okay";
+};
+
+/* CON 28 */
+&cp0_sdhci0 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&cp0_sdhci_pins>;
+   bus-width = <4>;
+   status = "okay";
+};
+
+/* U54 */
+&cp0_nand {
+   status = "disabled";
+};
+
+/* U55 */
+&cp0_spi1 {
+   pinc

[PATCH v2 01/10] phy: introduce 1000BaseX and 2500BaseX modes

2021-05-02 Thread Stefan Roese
From: Stefan Chulski 

Signed-off-by: Stefan Chulski 
Signed-off-by: Stefan Roese 
---

(no changes since v1)

 include/phy_interface.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/include/phy_interface.h b/include/phy_interface.h
index 841ade311efb..ebb18ecd40c0 100644
--- a/include/phy_interface.h
+++ b/include/phy_interface.h
@@ -25,6 +25,8 @@ typedef enum {
PHY_INTERFACE_MODE_RGMII_RXID,
PHY_INTERFACE_MODE_RGMII_TXID,
PHY_INTERFACE_MODE_RTBI,
+   PHY_INTERFACE_MODE_1000BASEX,
+   PHY_INTERFACE_MODE_2500BASEX,
PHY_INTERFACE_MODE_XGMII,
PHY_INTERFACE_MODE_XAUI,
PHY_INTERFACE_MODE_RXAUI,
@@ -55,6 +57,8 @@ static const char * const phy_interface_strings[] = {
[PHY_INTERFACE_MODE_RGMII_RXID] = "rgmii-rxid",
[PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid",
[PHY_INTERFACE_MODE_RTBI]   = "rtbi",
+   [PHY_INTERFACE_MODE_1000BASEX]  = "1000base-x",
+   [PHY_INTERFACE_MODE_2500BASEX]  = "2500base-x",
[PHY_INTERFACE_MODE_XGMII]  = "xgmii",
[PHY_INTERFACE_MODE_XAUI]   = "xaui",
[PHY_INTERFACE_MODE_RXAUI]  = "rxaui",
-- 
2.31.1



[PATCH v2 00/10] net: mvpp2: Sync Marvell mvpp2 driver with Marvell version

2021-05-02 Thread Stefan Roese


This patchset adds the missing ethernet mvpp2 patches from the Marvell
U-Boot SDK version to support and fix higher connection speeds. This is
done in preparation for the integration of the Octeon TX2 CN913x
support, which uses the updated version of this code.

Please note that I explicitly did not remove the incorrectly used
PHY_INTERFACE_MODE_SGMII_2500 changes from these patches. This makes it
easier to follow the Marvell downstream code. SGMII_2500 will be
removed by the follow-up patch, that I already did send a bit earlier
today. Sorry, I forgot to send this series earlier.

Thanks,
Stefan

Changes in v2:
- Removed all non-personal tags (Jenkins etc)

Ben Peled (3):
  net: mvpp2: AN Bypass in 1000 and 2500 basex mode
  net: mvpp2: remove unused define MVPP22_SMI_PHY_ADDR_REG
  net: mvpp2: fix missing switch case break

Marcin Wojtas (2):
  net: mvpp2: remove redundant SMI address configuration
  net: mvpp2: add explicit sgmii-2500 support

Stefan Chulski (5):
  phy: introduce 1000BaseX and 2500BaseX modes
  net: mvpp2: add CP115 port1 10G/5G SFI support
  net: mvpp2: add 1000BaseX and 2500BaseX ppv2 support
  net: mvpp2: Fix 2.5G GMII_SPEED configurations
  net: mvpp2: allow MDIO registration for fixed links

 drivers/net/mvpp2.c | 257 +---
 include/phy_interface.h |   4 +
 2 files changed, 163 insertions(+), 98 deletions(-)

-- 
2.31.1



[PATCH v2 02/10] net: mvpp2: add CP115 port1 10G/5G SFI support

2021-05-02 Thread Stefan Roese
From: Stefan Chulski 

1. Differ between Port1 RGMII and SFI modes in Netcomplex config.
2. Remove XPCS config from SFI mode.
   Port1 doesn't XPCS domain, XPCS config should be removed.
   Access to Port1 XPCS can cause stall.
3. Add Port1 MPCS configurations.

Signed-off-by: Stefan Chulski 
Signed-off-by: Stefan Roese 
---

(no changes since v1)

 drivers/net/mvpp2.c | 75 ++---
 1 file changed, 17 insertions(+), 58 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 1cf522b8fe57..015f5329de74 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -520,8 +520,9 @@ do {
\
 /* Net Complex */
 enum mv_netc_topology {
MV_NETC_GE_MAC2_SGMII   =   BIT(0),
-   MV_NETC_GE_MAC3_SGMII   =   BIT(1),
-   MV_NETC_GE_MAC3_RGMII   =   BIT(2),
+   MV_NETC_GE_MAC2_RGMII   =   BIT(1),
+   MV_NETC_GE_MAC3_SGMII   =   BIT(2),
+   MV_NETC_GE_MAC3_RGMII   =   BIT(3),
 };
 
 enum mv_netc_phase {
@@ -3208,56 +3209,31 @@ static int gop_gpcs_reset(struct mvpp2_port *port, int 
reset)
return 0;
 }
 
-/* Set the internal mux's to the required PCS in the PI */
-static int gop_xpcs_mode(struct mvpp2_port *port, int num_of_lanes)
-{
-   u32 val;
-   int lane;
-
-   switch (num_of_lanes) {
-   case 1:
-   lane = 0;
-   break;
-   case 2:
-   lane = 1;
-   break;
-   case 4:
-   lane = 2;
-   break;
-   default:
-   return -1;
-   }
-
-   /* configure XG MAC mode */
-   val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
-   val &= ~MVPP22_XPCS_PCSMODE_MASK;
-   val &= ~MVPP22_XPCS_LANEACTIVE_MASK;
-   val |= (2 * lane) << MVPP22_XPCS_LANEACTIVE_OFFS;
-   writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
-
-   return 0;
-}
-
 static int gop_mpcs_mode(struct mvpp2_port *port)
 {
u32 val;
 
/* configure PCS40G COMMON CONTROL */
-   val = readl(port->priv->mpcs_base + PCS40G_COMMON_CONTROL);
+   val = readl(port->priv->mpcs_base + port->gop_id * MVPP22_PORT_OFFSET +
+   PCS40G_COMMON_CONTROL);
val &= ~FORWARD_ERROR_CORRECTION_MASK;
-   writel(val, port->priv->mpcs_base + PCS40G_COMMON_CONTROL);
+   writel(val, port->priv->mpcs_base + port->gop_id * MVPP22_PORT_OFFSET +
+  PCS40G_COMMON_CONTROL);
 
/* configure PCS CLOCK RESET */
-   val = readl(port->priv->mpcs_base + PCS_CLOCK_RESET);
+   val = readl(port->priv->mpcs_base + port->gop_id * MVPP22_PORT_OFFSET +
+   PCS_CLOCK_RESET);
val &= ~CLK_DIVISION_RATIO_MASK;
val |= 1 << CLK_DIVISION_RATIO_OFFS;
-   writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET);
+   writel(val, port->priv->mpcs_base + port->gop_id * MVPP22_PORT_OFFSET +
+  PCS_CLOCK_RESET);
 
val &= ~CLK_DIV_PHASE_SET_MASK;
val |= MAC_CLK_RESET_MASK;
val |= RX_SD_CLK_RESET_MASK;
val |= TX_SD_CLK_RESET_MASK;
-   writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET);
+   writel(val, port->priv->mpcs_base + port->gop_id * MVPP22_PORT_OFFSET +
+  PCS_CLOCK_RESET);
 
return 0;
 }
@@ -3300,22 +3276,6 @@ static int gop_xlg_mac_mode_cfg(struct mvpp2_port *port, 
int num_of_act_lanes)
return 0;
 }
 
-/* Set PCS to reset or exit from reset */
-static int gop_xpcs_reset(struct mvpp2_port *port, int reset)
-{
-   u32 val;
-
-   /* read - modify - write */
-   val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
-   if (reset)
-   val &= ~MVPP22_XPCS_PCSRESET;
-   else
-   val |= MVPP22_XPCS_PCSRESET;
-   writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
-
-   return 0;
-}
-
 /* Set the MAC to reset or exit from reset */
 static int gop_xlg_mac_reset(struct mvpp2_port *port, int reset)
 {
@@ -3387,14 +3347,10 @@ static int gop_port_init(struct mvpp2_port *port)
num_of_act_lanes = 2;
mac_num = 0;
/* configure PCS */
-   gop_xpcs_mode(port, num_of_act_lanes);
gop_mpcs_mode(port);
/* configure MAC */
gop_xlg_mac_mode_cfg(port, num_of_act_lanes);
 
-   /* pcs unreset */
-   gop_xpcs_reset(port, 0);
-
/* mac unreset */
gop_xlg_mac_reset(port, 0);
break;
@@ -3465,6 +3421,9 @@ static u32 mvpp2_netc_cfg_create(int gop_id, 
phy_interface_t phy_type)
if (gop_id == 2) {
if (phy_type == PHY_INTERFACE_MODE_SGMII)
val |= MV_NETC_GE_MAC2_SGMII;
+   else if (phy_type == PHY_INTERFACE_MODE_RGMII ||
+p

[PATCH v2 04/10] net: mvpp2: remove redundant SMI address configuration

2021-05-02 Thread Stefan Roese
From: Marcin Wojtas 

Because the mvpp2 driver now relies on the PHYLIB and
the external MDIO driver, configuring low level
SMI bus settings is redundant.

Signed-off-by: Marcin Wojtas 
Reviewed-by: Kostya Porotchkin 
Reviewed-by: Stefan Chulski 
Signed-off-by: Stefan Roese 
---

(no changes since v1)

 drivers/net/mvpp2.c | 12 
 1 file changed, 12 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 847007d5b487..2043bdf10aa4 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -5292,14 +5292,6 @@ static int mvpp2_write_hwaddr(struct udevice *dev)
return mvpp2_prs_update_mac_da(port, port->dev_addr);
 }
 
-static int mvpp22_smi_phy_addr_cfg(struct mvpp2_port *port)
-{
-   writel(port->phyaddr, port->priv->iface_base +
-  MVPP22_SMI_PHY_ADDR_REG(port->gop_id));
-
-   return 0;
-}
-
 static int mvpp2_base_probe(struct udevice *dev)
 {
struct mvpp2 *priv = dev_get_priv(dev);
@@ -5422,10 +5414,6 @@ static int mvpp2_probe(struct udevice *dev)
port->base = priv->iface_base + MVPP22_PORT_BASE +
port->gop_id * MVPP22_PORT_OFFSET;
 
-   /* Set phy address of the port */
-   if (port->phyaddr < PHY_MAX_ADDR)
-   mvpp22_smi_phy_addr_cfg(port);
-
/* GoP Init */
gop_port_init(port);
}
-- 
2.31.1



[PATCH v2 05/10] net: mvpp2: Fix 2.5G GMII_SPEED configurations

2021-05-02 Thread Stefan Roese
From: Stefan Chulski 

GMII_SPEED should be enabled for 2.5G speed

Signed-off-by: Stefan Chulski 
Reviewed-by: Yan Markman 
Reviewed-by: Kostya Porotchkin 
Signed-off-by: Stefan Roese 
---

(no changes since v1)

 drivers/net/mvpp2.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 2043bdf10aa4..ec7cb89a94c8 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -4445,7 +4445,8 @@ static void mvpp2_link_event(struct mvpp2_port *port)
if (phydev->duplex)
val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
 
-   if (phydev->speed == SPEED_1000)
+   if (phydev->speed == SPEED_1000 ||
+   phydev->speed == 2500)
val |= MVPP2_GMAC_CONFIG_GMII_SPEED;
else if (phydev->speed == SPEED_100)
val |= MVPP2_GMAC_CONFIG_MII_SPEED;
-- 
2.31.1



[PATCH v2 03/10] net: mvpp2: add 1000BaseX and 2500BaseX ppv2 support

2021-05-02 Thread Stefan Roese
From: Stefan Chulski 

Signed-off-by: Stefan Chulski 
Signed-off-by: Stefan Roese 
---

(no changes since v1)

 drivers/net/mvpp2.c | 117 ++--
 1 file changed, 112 insertions(+), 5 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 015f5329de74..847007d5b487 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -2880,6 +2880,10 @@ static void mvpp2_port_mii_set(struct mvpp2_port *port)
case PHY_INTERFACE_MODE_SGMII:
val |= MVPP2_GMAC_INBAND_AN_MASK;
break;
+   case PHY_INTERFACE_MODE_1000BASEX:
+   case PHY_INTERFACE_MODE_2500BASEX:
+   val &= ~MVPP2_GMAC_INBAND_AN_MASK;
+   break;
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_ID:
val |= MVPP2_GMAC_PORT_RGMII_MASK;
@@ -2940,7 +2944,9 @@ static void mvpp2_port_loopback_set(struct mvpp2_port 
*port)
else
val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
 
-   if (port->phy_interface == PHY_INTERFACE_MODE_SGMII)
+   if (port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
+   port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
+   port->phy_interface == PHY_INTERFACE_MODE_2500BASEX)
val |= MVPP2_GMAC_PCS_LB_EN_MASK;
else
val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
@@ -3051,10 +3057,10 @@ static void gop_gmac_sgmii2_5_cfg(struct mvpp2_port 
*port)
 
val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
/*
-* Configure GIG MAC to 1000Base-X mode connected to a fiber
+* Configure GIG MAC to SGMII mode connected to a fiber
 * transceiver
 */
-   val |= MVPP2_GMAC_PORT_TYPE_MASK;
+   val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
 
/* configure AN 0x9268 */
@@ -3106,6 +3112,89 @@ static void gop_gmac_sgmii_cfg(struct mvpp2_port *port)
writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
 }
 
+static void gop_gmac_2500basex_cfg(struct mvpp2_port *port)
+{
+   u32 val, thresh;
+
+   /*
+* Configure minimal level of the Tx FIFO before the lower part
+* starts to read a packet
+*/
+   thresh = MVPP2_SGMII2_5_TX_FIFO_MIN_TH;
+   val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
+   val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
+   val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
+   writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
+
+   /* Disable bypass of sync module */
+   val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
+   val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
+   /* configure DP clock select according to mode */
+   val |= MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
+   /* configure QSGMII bypass according to mode */
+   val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
+   writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
+
+   val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
+   /*
+* Configure GIG MAC to 2500Base-X mode connected to a fiber
+* transceiver
+*/
+   val |= MVPP2_GMAC_PORT_TYPE_MASK;
+   writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
+
+   /* In 2500BaseX mode, we can't negotiate speed
+* and we do not want InBand autoneg
+* bypass enabled (link interrupt storm risk
+* otherwise).
+*/
+   val = MVPP2_GMAC_EN_PCS_AN |
+   MVPP2_GMAC_CONFIG_GMII_SPEED  |
+   MVPP2_GMAC_CONFIG_FULL_DUPLEX |
+   MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
+   writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
+}
+
+static void gop_gmac_1000basex_cfg(struct mvpp2_port *port)
+{
+   u32 val, thresh;
+
+   /*
+* Configure minimal level of the Tx FIFO before the lower part
+* starts to read a packet
+*/
+   thresh = MVPP2_SGMII_TX_FIFO_MIN_TH;
+   val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
+   val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
+   val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
+   writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
+
+   /* Disable bypass of sync module */
+   val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
+   val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
+   /* configure DP clock select according to mode */
+   val &= ~MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
+   /* configure QSGMII bypass according to mode */
+   val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
+   writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
+
+   val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
+   /* configure GIG MAC to 1000BASEX mode */
+   val |= MVPP2_GMAC_PORT_TYPE_MASK;
+   writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
+
+   /* In 1000BaseX mode, we can't negotiate speed (it's
+* only 1000), and we do not want InBand autoneg
+* bypass enabled (link interrupt storm 

[PATCH v2 07/10] net: mvpp2: remove unused define MVPP22_SMI_PHY_ADDR_REG

2021-05-02 Thread Stefan Roese
From: Ben Peled 

Signed-off-by: Ben Peled 
Reviewed-by: Stefan Chulski 
Reviewed-by: Kostya Porotchkin 
Signed-off-by: Stefan Roese 
---

(no changes since v1)

 drivers/net/mvpp2.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 879289452b15..61a0ea0894a7 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -490,9 +490,6 @@ do {
\
 #define MVPP22_SMI_MISC_CFG_REG(MVPP22_SMI + 0x04)
 #define  MVPP22_SMI_POLLING_EN BIT(10)
 
-#define MVPP22_SMI_PHY_ADDR_REG(port)  (MVPP22_SMI + 0x04 + \
-(0x4 * (port)))
-
 #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
 
 /* Descriptor ring Macros */
-- 
2.31.1



[PATCH v2 06/10] net: mvpp2: AN Bypass in 1000 and 2500 basex mode

2021-05-02 Thread Stefan Roese
From: Ben Peled 

Signed-off-by: Ben Peled 
Reviewed-by: Stefan Chulski 
Reviewed-by: Kostya Porotchkin 
Signed-off-by: Stefan Roese 
---

(no changes since v1)

 drivers/net/mvpp2.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index ec7cb89a94c8..879289452b15 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -3148,7 +3148,8 @@ static void gop_gmac_2500basex_cfg(struct mvpp2_port 
*port)
 * bypass enabled (link interrupt storm risk
 * otherwise).
 */
-   val = MVPP2_GMAC_EN_PCS_AN |
+   val = MVPP2_GMAC_AN_BYPASS_EN |
+   MVPP2_GMAC_EN_PCS_AN |
MVPP2_GMAC_CONFIG_GMII_SPEED  |
MVPP2_GMAC_CONFIG_FULL_DUPLEX |
MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
@@ -3188,7 +3189,8 @@ static void gop_gmac_1000basex_cfg(struct mvpp2_port 
*port)
 * bypass enabled (link interrupt storm risk
 * otherwise).
 */
-   val = MVPP2_GMAC_EN_PCS_AN |
+   val = MVPP2_GMAC_AN_BYPASS_EN |
+   MVPP2_GMAC_EN_PCS_AN |
MVPP2_GMAC_CONFIG_GMII_SPEED  |
MVPP2_GMAC_CONFIG_FULL_DUPLEX |
MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
-- 
2.31.1



[PATCH v2 09/10] net: mvpp2: allow MDIO registration for fixed links

2021-05-02 Thread Stefan Roese
From: Stefan Chulski 

Currently, there are 2 valid cases for interface, PHY
and mdio relation:
  - If an interface has PHY handler, it'll call
mdio_mii_bus_get_from_phy(), which will register
MDIO bus.
  - If we want to use fixed-link for an interface,
PHY handle is not defined in the DTS, and no
MDIO is registered.

There is a third case, for some boards (with switch),
the MDIO is used for switch configuration, but the interface
itself uses fixed link. This patch allows this option by
checking if fixed-link subnode is defined, in this case,
MDIO bus is registers, but the PHY address is set to
PHY_MAX_ADDR for this interface, so this interface will
not try to access the PHY later on.

Signed-off-by: Stefan Chulski 
Signed-off-by: Stefan Roese 
---

(no changes since v1)

 drivers/net/mvpp2.c | 17 +
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 3d920e85ffef..c5bfe41281d6 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -4787,16 +4787,25 @@ static int phy_info_parse(struct udevice *dev, struct 
mvpp2_port *port)
u32 id;
u32 phyaddr = 0;
int phy_mode = -1;
+   int fixed_link = 0;
int ret;
 
phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy");
+   fixed_link = fdt_subnode_offset(gd->fdt_blob, port_node, "fixed-link");
 
if (phy_node > 0) {
int parent;
-   phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0);
-   if (phyaddr < 0) {
-   dev_err(dev, "could not find phy address\n");
-   return -1;
+
+   if (fixed_link != -FDT_ERR_NOTFOUND) {
+   /* phy_addr is set to invalid value for fixed links */
+   phyaddr = PHY_MAX_ADDR;
+   } else {
+   phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node,
+"reg", 0);
+   if (phyaddr < 0) {
+   dev_err(dev, "could not find phy address\n");
+   return -1;
+   }
}
parent = fdt_parent_offset(gd->fdt_blob, phy_node);
ret = uclass_get_device_by_of_offset(UCLASS_MDIO, parent,
-- 
2.31.1



[PATCH v2 08/10] net: mvpp2: fix missing switch case break

2021-05-02 Thread Stefan Roese
From: Ben Peled 

Signed-off-by: Ben Peled 
Reviewed-by: Stefan Chulski 
Reviewed-by: Kostya Porotchkin 
Signed-off-by: Stefan Roese 
---

(no changes since v1)

 drivers/net/mvpp2.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 61a0ea0894a7..3d920e85ffef 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -3247,9 +3247,11 @@ static int gop_gmac_mode_cfg(struct mvpp2_port *port)
 
case PHY_INTERFACE_MODE_1000BASEX:
gop_gmac_1000basex_cfg(port);
+   break;
 
case PHY_INTERFACE_MODE_2500BASEX:
gop_gmac_2500basex_cfg(port);
+   break;
 
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_ID:
-- 
2.31.1



[PATCH v2 10/10] net: mvpp2: add explicit sgmii-2500 support

2021-05-02 Thread Stefan Roese
From: Marcin Wojtas 

Until now the mvpp2 driver used an extra 'phy-speed'
DT property in order to differentiate between the
SGMII and SGMII @2.5GHz. As there is a dedicated
PHY_INTERFACE_MODE_SGMII_2500 flag to mark the latter
start using it and drop the custom flag.

Signed-off-by: Marcin Wojtas 
Reviewed-by: Stefan Chulski 
Reviewed-by: Nadav Haklai 
Tested-by: Nadav Haklai 

Signed-off-by: Stefan Roese 
---

Changes in v2:
- Removed all non-personal tags (Jenkins etc)

 drivers/net/mvpp2.c | 28 
 1 file changed, 12 insertions(+), 16 deletions(-)

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index c5bfe41281d6..4c0a7b0a9f5c 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -976,8 +976,6 @@ struct mvpp2_port {
unsigned int duplex;
unsigned int speed;
 
-   unsigned int phy_speed; /* SGMII 1Gbps vs 2.5Gbps */
-
struct mvpp2_bm_pool *pool_long;
struct mvpp2_bm_pool *pool_short;
 
@@ -2875,6 +2873,7 @@ static void mvpp2_port_mii_set(struct mvpp2_port *port)
 
switch (port->phy_interface) {
case PHY_INTERFACE_MODE_SGMII:
+   case PHY_INTERFACE_MODE_SGMII_2500:
val |= MVPP2_GMAC_INBAND_AN_MASK;
break;
case PHY_INTERFACE_MODE_1000BASEX:
@@ -2942,6 +2941,7 @@ static void mvpp2_port_loopback_set(struct mvpp2_port 
*port)
val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
 
if (port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
+   port->phy_interface == PHY_INTERFACE_MODE_SGMII_2500 ||
port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
port->phy_interface == PHY_INTERFACE_MODE_2500BASEX)
val |= MVPP2_GMAC_PCS_LB_EN_MASK;
@@ -3239,12 +3239,11 @@ static int gop_gmac_mode_cfg(struct mvpp2_port *port)
/* Set TX FIFO thresholds */
switch (port->phy_interface) {
case PHY_INTERFACE_MODE_SGMII:
-   if (port->phy_speed == 2500)
-   gop_gmac_sgmii2_5_cfg(port);
-   else
-   gop_gmac_sgmii_cfg(port);
+   gop_gmac_sgmii_cfg(port);
+   break;
+   case PHY_INTERFACE_MODE_SGMII_2500:
+   gop_gmac_sgmii2_5_cfg(port);
break;
-
case PHY_INTERFACE_MODE_1000BASEX:
gop_gmac_1000basex_cfg(port);
break;
@@ -3425,6 +3424,7 @@ static int gop_port_init(struct mvpp2_port *port)
break;
 
case PHY_INTERFACE_MODE_SGMII:
+   case PHY_INTERFACE_MODE_SGMII_2500:
case PHY_INTERFACE_MODE_1000BASEX:
case PHY_INTERFACE_MODE_2500BASEX:
/* configure PCS */
@@ -3484,6 +3484,7 @@ static void gop_port_enable(struct mvpp2_port *port, int 
enable)
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_SGMII:
+   case PHY_INTERFACE_MODE_SGMII_2500:
case PHY_INTERFACE_MODE_1000BASEX:
case PHY_INTERFACE_MODE_2500BASEX:
if (enable)
@@ -3520,6 +3521,7 @@ static u32 mvpp2_netc_cfg_create(int gop_id, 
phy_interface_t phy_type)
 
if (gop_id == 2) {
if (phy_type == PHY_INTERFACE_MODE_SGMII ||
+   phy_type == PHY_INTERFACE_MODE_SGMII_2500 ||
phy_type == PHY_INTERFACE_MODE_1000BASEX ||
phy_type == PHY_INTERFACE_MODE_2500BASEX)
val |= MV_NETC_GE_MAC2_SGMII;
@@ -3530,6 +3532,7 @@ static u32 mvpp2_netc_cfg_create(int gop_id, 
phy_interface_t phy_type)
 
if (gop_id == 3) {
if (phy_type == PHY_INTERFACE_MODE_SGMII ||
+   phy_type == PHY_INTERFACE_MODE_SGMII_2500 ||
phy_type == PHY_INTERFACE_MODE_1000BASEX ||
phy_type == PHY_INTERFACE_MODE_2500BASEX)
val |= MV_NETC_GE_MAC3_SGMII;
@@ -4528,6 +4531,7 @@ static void mvpp2_start_dev(struct mvpp2_port *port)
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_SGMII:
+   case PHY_INTERFACE_MODE_SGMII_2500:
case PHY_INTERFACE_MODE_1000BASEX:
case PHY_INTERFACE_MODE_2500BASEX:
mvpp2_gmac_max_rx_size_set(port);
@@ -4838,15 +4842,6 @@ static int phy_info_parse(struct udevice *dev, struct 
mvpp2_port *port)
 &port->phy_tx_disable_gpio, GPIOD_IS_OUT);
 #endif
 
-   /*
-* ToDo:
-* Not sure if this DT property "phy-speed" will get accepted, so
-* this might change later
-*/
-   /* Get phy-speed for SGMII 2.5Gbps vs 1Gbps setup */
-   port->phy_speed = fdtdec_get_int(gd->fdt_blob, port_node,
-"phy-speed", 1000);
-
port->id = id;
if (port->priv->hw_version == MVPP21)
port->first_rxq = port->id * rxq_number;
@@ -5275,6 +5270,7 @@ static int mvpp2_start(str

Re: [PATCH v1 08/10] net: mvpp2: fix missing switch case break

2021-05-02 Thread Stefan Roese

Hi Ramon,

On 30.04.21 16:18, Ramon Fried wrote:

On Fri, Apr 30, 2021 at 7:40 AM Stefan Roese  wrote:


On 29.04.21 22:24, Ramon Fried wrote:

On Tue, Apr 27, 2021 at 4:28 PM Stefan Roese  wrote:


From: Ben Peled 

Signed-off-by: Ben Peled 
Reviewed-by: Stefan Chulski 
Reviewed-by: Kostya Porotchkin 
Tested-by: sa_ip-sw-jenkins 

Please remove this, Jenkins is not a person.


I've left these lines in because most of these patches are plain
cherry-picked from the Marvell SDK.

Should I resubmit this patch only or the complete patchset? Or could you
perhaps remove this line while collecting the patches for a pull
request?

Please submit the patchset again.


Done. I just now noticed, that I forgot to add your RB tags. Should I
send v3 with the RB tags?

Thanks,
Stefan


[PATCH 1/2] riscv: cpu: Add callback to init each core

2021-05-02 Thread Green Wan
Add a callback harts_early_init() to start.S to allow different riscv
hart perform setup code for each hart as early as possible. Since all
the harts enter the callback, they must be able to run the same
setup.

Signed-off-by: Green Wan 
Reviewed-by: Rick Chen 
Reviewed-by: Bin Meng 
---
 arch/riscv/cpu/cpu.c   | 11 +++
 arch/riscv/cpu/start.S |  4 
 2 files changed, 15 insertions(+)

diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index 85592f5bee..296e458db4 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -140,3 +140,14 @@ int arch_early_init_r(void)
 {
return riscv_cpu_probe();
 }
+
+/**
+ * harts_early_init() - A callback function called by start.S to configure
+ * feature settings of each hart.
+ *
+ * In a multi-core system, memory access shall be careful here, it shall
+ * take care of race conditions.
+ */
+__weak void harts_early_init(void)
+{
+}
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 8589509e01..308b0a97a5 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -117,6 +117,10 @@ call_board_init_f_0:
mv  sp, a0
 #endif
 
+   /* Configure proprietary settings and customized CSRs of harts */
+call_harts_early_init:
+   jal harts_early_init
+
 #ifndef CONFIG_XIP
/*
 * Pick hart to initialize global data and run U-Boot. The other harts
-- 
2.31.0



[PATCH 2/2] riscv: cpu: fu740: clear feature disable CSR

2021-05-02 Thread Green Wan
Clear feature disable CSR to turn on all features of hart. The detail
is specified at section, 'SiFive Feature Disable CSR', in user manual

https://sifive.cdn.prismic.io/sifive/aee0dd4c-d156-496e-a6c4-db0cf54bbe68_sifive_U74MC_rtl_full_20G1.03.00_manual.pdf

Signed-off-by: Green Wan 
Reviewed-by: Sean Anderson 
Reviewed-by: Bin Meng 
Reviewed-by: Rick Chen 
---
 arch/riscv/cpu/fu740/spl.c | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/arch/riscv/cpu/fu740/spl.c b/arch/riscv/cpu/fu740/spl.c
index ea0b2283a2..55e30346ff 100644
--- a/arch/riscv/cpu/fu740/spl.c
+++ b/arch/riscv/cpu/fu740/spl.c
@@ -6,6 +6,9 @@
 
 #include 
 #include 
+#include 
+
+#define CSR_U74_FEATURE_DISABLE0x7c1
 
 int spl_soc_init(void)
 {
@@ -21,3 +24,15 @@ int spl_soc_init(void)
 
return 0;
 }
+
+void harts_early_init(void)
+{
+   /*
+* Feature Disable CSR
+*
+* Clear feature disable CSR to '0' to turn on all features for
+* each core. This operation must be in M-mode.
+*/
+   if (CONFIG_IS_ENABLED(RISCV_MMODE))
+   csr_write(CSR_U74_FEATURE_DISABLE, 0);
+}
-- 
2.31.0