Re: [U-Boot] [PATCH v3 13/22] ram: rk3328: use common sdram driver

2019-11-24 Thread Matwey V. Kornilov
Hi,

I cannot apply this series on top of current master. On top of which
commit it is supposed to be applied?

пт, 15 нояб. 2019 г. в 06:05, Kever Yang :
>
> From: YouMin Chen 
>
> RK3328 has a similar controller and phy with PX30, so we can use the
> common driver for it and remove the duplicate codes.
>
> Signed-off-by: YouMin Chen 
> Signed-off-by: Kever Yang 
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  arch/arm/dts/rk3328-sdram-ddr3-666.dtsi   |   4 +
>  arch/arm/dts/rk3328-sdram-lpddr3-1600.dtsi|   4 +
>  arch/arm/dts/rk3328-sdram-lpddr3-666.dtsi |   4 +
>  .../include/asm/arch-rockchip/sdram_rk3328.h  | 419 +++---
>  arch/arm/mach-rockchip/Kconfig|   1 +
>  configs/evb-rk3328_defconfig  |   2 +-
>  configs/rock64-rk3328_defconfig   |   2 +-
>  drivers/ram/rockchip/Makefile |   2 +-
>  drivers/ram/rockchip/sdram_rk3328.c   | 763 --
>  9 files changed, 295 insertions(+), 906 deletions(-)
>
> diff --git a/arch/arm/dts/rk3328-sdram-ddr3-666.dtsi 
> b/arch/arm/dts/rk3328-sdram-ddr3-666.dtsi
> index d99e7e0352..3e88ed443b 100644
> --- a/arch/arm/dts/rk3328-sdram-ddr3-666.dtsi
> +++ b/arch/arm/dts/rk3328-sdram-ddr3-666.dtsi
> @@ -14,6 +14,8 @@
> 0x0
> 0x10
> 0x10
> +   0x10
> +   0x10
> 0
>
> 0x9028b189
> @@ -26,6 +28,8 @@
>
> 333
> 3
> +   1
> +   0
> 0
>
> 0x
> diff --git a/arch/arm/dts/rk3328-sdram-lpddr3-1600.dtsi 
> b/arch/arm/dts/rk3328-sdram-lpddr3-1600.dtsi
> index cc0011cf7b..d63c761a02 100644
> --- a/arch/arm/dts/rk3328-sdram-lpddr3-1600.dtsi
> +++ b/arch/arm/dts/rk3328-sdram-lpddr3-1600.dtsi
> @@ -14,6 +14,8 @@
> 0x0
> 0x10
> 0x10
> +   0x10
> +   0x10
> 0
>
> 0x98899459
> @@ -27,6 +29,8 @@
> 800
> 6
> 1
> +   0
> +   1
>
> 0x
> 0x43041008
> diff --git a/arch/arm/dts/rk3328-sdram-lpddr3-666.dtsi 
> b/arch/arm/dts/rk3328-sdram-lpddr3-666.dtsi
> index 62d809e833..b9d3b3b948 100644
> --- a/arch/arm/dts/rk3328-sdram-lpddr3-666.dtsi
> +++ b/arch/arm/dts/rk3328-sdram-lpddr3-666.dtsi
> @@ -14,6 +14,8 @@
> 0x0
> 0x10
> 0x10
> +   0x10
> +   0x10
> 0
>
> 0x0c48a18a
> @@ -26,6 +28,8 @@
>
> 333
> 6
> +   1
> +   0
> 0
>
> 0x
> diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h 
> b/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h
> index c747b461a1..10923505d6 100644
> --- a/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h
> +++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h
> @@ -7,197 +7,13 @@
>  #ifndef _ASM_ARCH_SDRAM_RK3328_H
>  #define _ASM_ARCH_SDRAM_RK3328_H
>  #include 
> +#include 
> +#include 
> +#include 
>
>  #define SR_IDLE93
>  #define PD_IDLE13
>  #define SDRAM_ADDR 0x
> -#define PATTERN(0x5aa5f00f)
> -
> -/* ddr pctl registers define */
> -#define DDR_PCTL2_MSTR 0x0
> -#define DDR_PCTL2_STAT 0x4
> -#define DDR_PCTL2_MSTR10x8
> -#define DDR_PCTL2_MRCTRL0  0x10
> -#define DDR_PCTL2_MRCTRL1  0x14
> -#define DDR_PCTL2_MRSTAT   0x18
> -#define DDR_PCTL2_MRCTRL2  0x1c
> -#define DDR_PCTL2_DERATEEN 0x20
> -#define DDR_PCTL2_DERATEINT0x24
> -#define DDR_PCTL2_PWRCTL   0x30
> -#define DDR_PCTL2_PWRTMG   0x34
> -#define DDR_PCTL2_HWLPCTL  0x38
> -#define DDR_PCTL2_RFSHCTL0 0x50
> -#define DDR_PCTL2_RFSHCTL1 0x54
> -#define DDR_PCTL2_RFSHCTL2 0x58
> -#define DDR_PCTL2_RFSHCTL4 0x5c
> -#define DDR_PCTL2_RFSHCTL3 0x60
> -#define DDR_PCTL2_RFSHTMG  0x64
> -#define DDR_PCTL2_RFSHTMG1 0x68
> -#define DDR_PCTL2_RFSHCTL5 0x6c
> -#define DDR_PCTL2_INIT00xd0
> -#define DDR_PCTL2_INIT10xd4
> -#define DDR_PCTL2_INIT20xd8
> -#define DDR_PCTL2_INIT30xdc
> -#define DDR_PCTL2_INIT40xe0
> -#define DDR_PCTL2_INIT50xe4
> -#define DDR_PCTL2_INIT60xe8
> -#define DDR_PCTL2_INIT70xec
> -#define DDR_PCTL2_DIMMCTL  0xf0
> -#define DDR_PCTL2_RANKCTL  0xf4
> -#define DDR_PCTL2_CHCTL0xfc
> -#define DDR_PCTL2_DRAMTMG0 0x100
> -#defin

Re: [U-Boot] [PATCH 1/1] efi_loader: default EFI_LOADER=n on ARM11

2019-11-24 Thread Matthias Brugger


On 20/11/2019 19:04, Heinrich Schuchardt wrote:
> Some of the ARM11 boards have tight limits on the size of U-Boots. Hence
> use EFI_LOADER=n as default on ARM11.
> 
> Set EFI_LOADER=y for the Raspberry Pi and Raspberry Pi Zero as these boards
> have sufficient storage on the SD card.
> 
> Suggested-by: Tom Rini 
> Signed-off-by: Heinrich Schuchardt 

For RPi configs:

Acked-by: Matthias Brugger 

> ---
>  configs/rpi_0_w_defconfig | 1 +
>  configs/rpi_defconfig | 1 +
>  lib/efi_loader/Kconfig| 2 +-
>  3 files changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/configs/rpi_0_w_defconfig b/configs/rpi_0_w_defconfig
> index fe5a7763a6..6614adfc9b 100644
> --- a/configs/rpi_0_w_defconfig
> +++ b/configs/rpi_0_w_defconfig
> @@ -41,3 +41,4 @@ CONFIG_SYS_WHITE_ON_BLACK=y
>  CONFIG_CONSOLE_SCROLL_LINES=10
>  CONFIG_PHYS_TO_BUS=y
>  CONFIG_OF_LIBFDT_OVERLAY=y
> +CONFIG_EFI_LOADER=y
> diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig
> index 2c04b3334e..fa4d9c0b04 100644
> --- a/configs/rpi_defconfig
> +++ b/configs/rpi_defconfig
> @@ -41,3 +41,4 @@ CONFIG_SYS_WHITE_ON_BLACK=y
>  CONFIG_CONSOLE_SCROLL_LINES=10
>  CONFIG_PHYS_TO_BUS=y
>  CONFIG_OF_LIBFDT_OVERLAY=y
> +CONFIG_EFI_LOADER=y
> diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
> index 7984d6f42d..91411ad124 100644
> --- a/lib/efi_loader/Kconfig
> +++ b/lib/efi_loader/Kconfig
> @@ -10,7 +10,7 @@ config EFI_LOADER
>   depends on !EFI_STUB || !X86_64 || EFI_STUB_64BIT
>   # We need EFI_STUB_32BIT to be set on x86_32 with EFI_STUB
>   depends on !EFI_STUB || !X86 || X86_64 || EFI_STUB_32BIT
> - default y
> + default y if !ARM || SYS_CPU = armv7 || SYS_CPU = armv8
>   select LIB_UUID
>   select HAVE_BLOCK_DEVICE
>   select REGEX
> --
> 2.24.0
> 
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Re: [U-Boot] [GIT PULL] Raspberry Pi updates for v2020.01

2019-11-24 Thread Matthias Brugger


On 22/11/2019 14:40, Marek Szyprowski wrote:
> Hi Matthias,
> 
> On 20.11.2019 10:10, Matthias Brugger wrote:
>> Hi Tom,
>>
>> On 20/11/2019 02:57, Tom Rini wrote:
>>> On Tue, Nov 19, 2019 at 05:02:34PM +0100, Matthias Brugger wrote:
>>>
 Hi Tom,

 Please have a look at the below patches.
 Travis-ci can be found here:
 https://travis-ci.org/mbgg/u-boot/builds/614078145

 Apart from this patches, I planning to send another pull request once the 
 single
 binary series is ready to be merged. But for now, we should take this 
 patches as
 it fixes some FAT write errors and the boot banner issue for RPi3 you 
 detected.

 Regards,
 Matthias

>>> NAK, this seems to break FAT in some cases:
>>> https://protect2.fireeye.com/url?k=2537010b-78fbcdae-25368a44-0cc47a30d446-1c9023d2fe8030d3&u=https://gitlab.denx.de/u-boot/u-boot/-/jobs/31682
>>> https://protect2.fireeye.com/url?k=320832ee-6fc4fe4b-3209b9a1-0cc47a30d446-2f8fe5692eb397d4&u=https://gitlab.denx.de/u-boot/u-boot/-/jobs/31683
>>> (and similar in Azure and Travis).
>>>
>> It seems that it does not break in travis, but it also seems that the CI
>> diverged between travis and gitlab:
>> https://travis-ci.org/mbgg/u-boot/jobs/614078209
>> https://travis-ci.org/mbgg/u-boot/jobs/614078210
>>
>> @Tom are you aware of that?
>>
>> @Marek can you have a look into the FAT errors please?
> 
> Yes, I will take care of them. It looks that my fixes revealed bugs in 
> other parts of fat code...
> 

Thanks. I'll postpone your DFU series for now, as they are rahter useless
without a working FAT partition. I can merge it when all the FAT related
problems are fixed. Sounds good?

Regards,
Matthias
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Re: [U-Boot] Pull request for UEFI sub-system for efi-2020-01-rc4 (2)

2019-11-24 Thread Tom Rini
On Sat, Nov 23, 2019 at 03:07:12PM +0100, Heinrich Schuchardt wrote:

> The following changes since commit 2800540d101d7b0dd0629c5177fca48331d2927d:
> 
>   Update MAINTAINERS to include environment files (2019-11-21 08:36:40
> -0500)
> 
> are available in the Git repository at:
> 
>   https://gitlab.denx.de/u-boot/custodians/u-boot-efi.git
> tags/efi-2020-01-rc4-2
> 
> for you to fetch changes up to b7cdecfc196686ffae34b6849fc8b5b7ef62237a:
> 
>   efi_loader: default EFI_LOADER=n on ARM11 (2019-11-23 09:19:31 +0100)
> 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] [PATCHv2] buildman: Fix problem with non-existent output directories

2019-11-24 Thread Tom Rini
On Tue, Nov 19, 2019 at 03:14:33PM -0500, Tom Rini wrote:

> Now that we have buildman telling genboards.cfg to use an output
> directory we need to ensure that it exists.
> 
> Cc: Bin Meng 
> Cc: Simon Glass 
> Fixes: bc750bca1246 ("tools: buildman: Honor output directory when generating 
> boards.cfg")
> Signed-off-by: Tom Rini 
> Reviewed-by: Bin Meng 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH] moveconfig.py: Fix more Python3 UTF issues

2019-11-24 Thread Tom Rini
On Sun, Nov 10, 2019 at 09:19:37PM -0500, Tom Rini wrote:

> With the move to using Python 3 for real, we encounter two different
> issues.  First, the file include/video_font_data.h includes at least one
> UTF-16 character.  Given that it does not include any CONFIG symbols it
> is easiest to just ignore this file.  Next, we encounter similar
> problems with some dts/dtsi files that come from Linux.  In this case
> it's easiest to simply ignore all dts/dtsi files as there will not be
> CONFIG symbols for us to migrate in them.
> 
> Cc: Masahiro Yamada 
> Signed-off-by: Tom Rini 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH v2 1/1] arm: fix -march for ARM11

2019-11-24 Thread Tom Rini
On Sat, Nov 23, 2019 at 09:14:54AM +0100, Heinrich Schuchardt wrote:

> In GCC 9 support for the Armv5 and Armv5E architectures (which have no
> known implementations) has been removed, cf.
> https://gcc.gnu.org/gcc-9/changes.html
> 
> ARM11 is an armv6 implementation. So change the architecture flag for the
> compiler to armv6 for ARM11.
> 
> Suggested-by: Fabio Estevam 
> Signed-off-by: Heinrich Schuchardt 
> Reviewed-by: Fabio Estevam 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH v2] travis: move orangepi to vendor job

2019-11-24 Thread Tom Rini
On Thu, Nov 21, 2019 at 06:50:12AM +0100, Heiko Schocher wrote:

> move orangepi builds into a new job, and exclude
> orangepi builds from sunxi and rockchip jobs.
> 
> Signed-off-by: Heiko Schocher 
> Reviewed-by: Tom Rini 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH v2 1/3] tools: checkpatch: Restore 'debug' and 'printf' to logFunctions list

2019-11-24 Thread Tom Rini
On Thu, Nov 21, 2019 at 02:32:46PM +, James Byrne wrote:

> The 'debug' and 'printf' functions were previously added to the list of
> logFunctions in commit 0cab42110dbf ("checkpatch.pl: Add 'debug' to
> the list of logFunctions") and commit 397bfd4642c1 ("checkpatch.pl:
> Add 'printf' to logFunctions") but these additions were lost when newer
> versions of checkpatch were pulled in from the upstream Linux
> kernel version.
> 
> This restores them so that you don't end up in a situation where
> checkpatch will give a warning for "quoted string split across lines"
> which you cannot fix without getting a warning for "line over 80
> characters" instead.
> 
> Signed-off-by: James Byrne 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] [PATCH v3] travis: rework NXP layerscape jobs

2019-11-24 Thread Tom Rini
On Fri, Nov 22, 2019 at 11:17:29AM +0100, Heiko Schocher wrote:

> remove from NXP arm32 all layerscape boards and
> build them instead in already existing layerscape
> jobs (which now not only build aarch64 boards)
> 
> Signed-off-by: Heiko Schocher 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH] scripts: dtc: ignore files generated generated by python

2019-11-24 Thread Tom Rini
On Wed, Nov 13, 2019 at 02:42:41PM +0100, Bartosz Golaszewski wrote:

> From: Bartosz Golaszewski 
> 
> Add __pycache__ to ignored files and extend the rule for _libfdt to also
> include generated shared objects (e.g. 
> _libfdt.cpython-37m-x86_64-linux-gnu.so).
> 
> Signed-off-by: Bartosz Golaszewski 

Applied to u-boot/master, thanks!

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Re: [U-Boot] Pull request: u-boot-rockchip-20191124

2019-11-24 Thread Tom Rini
On Sun, Nov 24, 2019 at 08:31:44AM +0800, Kever Yang wrote:

> Hi Tom,
> 
> Please pull the rockchip update:
> - Clean vid/pid in Kconfig and add fastboot for rk3399
> - add 'u-boot, spl-fifo-mode' for mmc
> - Use FIT generator for rk3229 optee and rk3368 ATF
> - fan53555: add support for Silergy SYR82X and SYR83X
> 
> Fix the u8 type comparision with '-1'.
> 
> Travis:
> https://travis-ci.org/keveryang/u-boot/builds/616004990
> 
> Thanks,
> - Kever
> 
> The following changes since commit d4a31e8ee5592072d8d5208b3e950cba2d89b6bd:
> 
>   Prepare v2020.01-rc3 (2019-11-18 21:31:49 -0500)
> 
> are available in the Git repository at:
> 
>   https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip.git 
> tags/u-boot-rockchip-20191124
> 
> for you to fetch changes up to 8019d32c4701b95410113541deb7f28d5c2b02a5:
> 
>   rockchip: px30: enable spl-fifo-mode for both emmc and sdmmc on evb 
> (2019-11-23 23:41:44 +0800)
> 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [PATCH v5 17/26] configs: socfpga: mcvevk: Remove useless UBI infos

2019-11-24 Thread Tom Rini
On Thu, Oct 03, 2019 at 07:50:19PM +0200, Miquel Raynal wrote:

> There is no flash on this board, there is no reason to define MTD
> environment variables nor UBI. Drop them from the configuration file.
> 
> Signed-off-by: Miquel Raynal 
> ---
>  configs/socfpga_mcvevk_defconfig | 3 ---
>  1 file changed, 3 deletions(-)
> 
> diff --git a/configs/socfpga_mcvevk_defconfig 
> b/configs/socfpga_mcvevk_defconfig
> index 39cc753888..15c9f7fdb0 100644
> --- a/configs/socfpga_mcvevk_defconfig
> +++ b/configs/socfpga_mcvevk_defconfig
> @@ -28,9 +28,6 @@ CONFIG_CMD_USB=y
>  CONFIG_CMD_USB_MASS_STORAGE=y
>  CONFIG_CMD_CACHE=y
>  CONFIG_CMD_EXT4_WRITE=y
> -CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
> -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
> -CONFIG_CMD_UBI=y
>  # CONFIG_ISO_PARTITION is not set
>  # CONFIG_EFI_PARTITION is not set
>  CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_mcvevk"

This board has SPI flash and so the MTDIDS/PARTS make sense there.  I'm
adding in the board maintainer for further comment about how UBI might
be used, thanks!

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Re: [U-Boot] [PATCH v3 13/22] ram: rk3328: use common sdram driver

2019-11-24 Thread Matwey V. Kornilov
I've found that the series is already applied, sorry :-)
It works fine on rock64 for me.

вс, 24 нояб. 2019 г. в 11:05, Matwey V. Kornilov :
>
> Hi,
>
> I cannot apply this series on top of current master. On top of which
> commit it is supposed to be applied?
>
> пт, 15 нояб. 2019 г. в 06:05, Kever Yang :
> >
> > From: YouMin Chen 
> >
> > RK3328 has a similar controller and phy with PX30, so we can use the
> > common driver for it and remove the duplicate codes.
> >
> > Signed-off-by: YouMin Chen 
> > Signed-off-by: Kever Yang 
> > ---
> >
> > Changes in v3: None
> > Changes in v2: None
> >
> >  arch/arm/dts/rk3328-sdram-ddr3-666.dtsi   |   4 +
> >  arch/arm/dts/rk3328-sdram-lpddr3-1600.dtsi|   4 +
> >  arch/arm/dts/rk3328-sdram-lpddr3-666.dtsi |   4 +
> >  .../include/asm/arch-rockchip/sdram_rk3328.h  | 419 +++---
> >  arch/arm/mach-rockchip/Kconfig|   1 +
> >  configs/evb-rk3328_defconfig  |   2 +-
> >  configs/rock64-rk3328_defconfig   |   2 +-
> >  drivers/ram/rockchip/Makefile |   2 +-
> >  drivers/ram/rockchip/sdram_rk3328.c   | 763 --
> >  9 files changed, 295 insertions(+), 906 deletions(-)
> >
> > diff --git a/arch/arm/dts/rk3328-sdram-ddr3-666.dtsi 
> > b/arch/arm/dts/rk3328-sdram-ddr3-666.dtsi
> > index d99e7e0352..3e88ed443b 100644
> > --- a/arch/arm/dts/rk3328-sdram-ddr3-666.dtsi
> > +++ b/arch/arm/dts/rk3328-sdram-ddr3-666.dtsi
> > @@ -14,6 +14,8 @@
> > 0x0
> > 0x10
> > 0x10
> > +   0x10
> > +   0x10
> > 0
> >
> > 0x9028b189
> > @@ -26,6 +28,8 @@
> >
> > 333
> > 3
> > +   1
> > +   0
> > 0
> >
> > 0x
> > diff --git a/arch/arm/dts/rk3328-sdram-lpddr3-1600.dtsi 
> > b/arch/arm/dts/rk3328-sdram-lpddr3-1600.dtsi
> > index cc0011cf7b..d63c761a02 100644
> > --- a/arch/arm/dts/rk3328-sdram-lpddr3-1600.dtsi
> > +++ b/arch/arm/dts/rk3328-sdram-lpddr3-1600.dtsi
> > @@ -14,6 +14,8 @@
> > 0x0
> > 0x10
> > 0x10
> > +   0x10
> > +   0x10
> > 0
> >
> > 0x98899459
> > @@ -27,6 +29,8 @@
> > 800
> > 6
> > 1
> > +   0
> > +   1
> >
> > 0x
> > 0x43041008
> > diff --git a/arch/arm/dts/rk3328-sdram-lpddr3-666.dtsi 
> > b/arch/arm/dts/rk3328-sdram-lpddr3-666.dtsi
> > index 62d809e833..b9d3b3b948 100644
> > --- a/arch/arm/dts/rk3328-sdram-lpddr3-666.dtsi
> > +++ b/arch/arm/dts/rk3328-sdram-lpddr3-666.dtsi
> > @@ -14,6 +14,8 @@
> > 0x0
> > 0x10
> > 0x10
> > +   0x10
> > +   0x10
> > 0
> >
> > 0x0c48a18a
> > @@ -26,6 +28,8 @@
> >
> > 333
> > 6
> > +   1
> > +   0
> > 0
> >
> > 0x
> > diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h 
> > b/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h
> > index c747b461a1..10923505d6 100644
> > --- a/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h
> > +++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h
> > @@ -7,197 +7,13 @@
> >  #ifndef _ASM_ARCH_SDRAM_RK3328_H
> >  #define _ASM_ARCH_SDRAM_RK3328_H
> >  #include 
> > +#include 
> > +#include 
> > +#include 
> >
> >  #define SR_IDLE93
> >  #define PD_IDLE13
> >  #define SDRAM_ADDR 0x
> > -#define PATTERN(0x5aa5f00f)
> > -
> > -/* ddr pctl registers define */
> > -#define DDR_PCTL2_MSTR 0x0
> > -#define DDR_PCTL2_STAT 0x4
> > -#define DDR_PCTL2_MSTR10x8
> > -#define DDR_PCTL2_MRCTRL0  0x10
> > -#define DDR_PCTL2_MRCTRL1  0x14
> > -#define DDR_PCTL2_MRSTAT   0x18
> > -#define DDR_PCTL2_MRCTRL2  0x1c
> > -#define DDR_PCTL2_DERATEEN 0x20
> > -#define DDR_PCTL2_DERATEINT0x24
> > -#define DDR_PCTL2_PWRCTL   0x30
> > -#define DDR_PCTL2_PWRTMG   0x34
> > -#define DDR_PCTL2_HWLPCTL  0x38
> > -#define DDR_PCTL2_RFSHCTL0 0x50
> > -#define DDR_PCTL2_RFSHCTL1 0x54
> > -#define DDR_PCTL2_RFSHCTL2 0x58
> > -#define DDR_PCTL2_RFSHCTL4 0x5c
> > -#define DDR_PCTL2_RFSHCTL3 0x60
> > -#define DDR_PCTL2_RFSHTMG  0x64
> > -#define DDR_PCTL2_RFSHTMG1 0x68
> > -#define DDR_PCTL2_RFSHCTL5 0x6c
> > -#define DDR_PCTL2_INIT00xd0
> > -#define DDR_PCTL2_INIT10xd4
> > -#define DDR_PCTL2_INIT20xd8
> > -#define DDR_PCTL2_INIT30xdc
>

Re: [U-Boot] [PATCH 2/5] common: add blkcache init

2019-11-24 Thread Eric Nelson

Hi Angelo,

On 11/23/19 3:47 PM, Angelo Dureghello wrote:

From: Angelo Durgehello 

On m68k, block_cache list is relocated, but next and prev list
pointers are not adjusted to the relocated struct list_head address,
so the first iteration over the block_cache list hangs.

This patch initializes the block_cache list after relocation.

Signed-off-by: Angelo Durgehello 
---
  common/board_r.c | 12 
  drivers/block/blkcache.c |  7 ++-
  include/blk.h|  6 ++
  3 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/common/board_r.c b/common/board_r.c
index 65720849cd..13e70a5ffb 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -628,6 +628,15 @@ static int initr_bedbug(void)
  }
  #endif
  
+#ifdef CONFIG_BLOCK_CACHE

+static int initr_blkcache(void)
+{
+   blkcache_init();
+
+   return 0;
+}
+#endif
+


Why the extra level of indirection?


  static int run_main_loop(void)
  {
  #ifdef CONFIG_SANDBOX
@@ -832,6 +841,9 @@ static init_fnc_t init_sequence_r[] = {
  #endif
  #if defined(CONFIG_PRAM)
initr_mem,
+#endif
+#ifdef CONFIG_BLOCK_CACHE


It seems you could call blkcache_init from here directly:


+   initr_blkcache,
  #endif
run_main_loop,
  };
diff --git a/drivers/block/blkcache.c b/drivers/block/blkcache.c
index 1fa64989d3..bf0fa1ea6f 100644
--- a/drivers/block/blkcache.c
+++ b/drivers/block/blkcache.c
@@ -21,13 +21,18 @@ struct block_cache_node {
char *cache;
  };
  
-static LIST_HEAD(block_cache);

+static struct list_head block_cache;
  
  static struct block_cache_stats _stats = {

.max_blocks_per_entry = 8,
.max_entries = 32
  };
  
+void blkcache_init(void)

+{
+   INIT_LIST_HEAD(&block_cache);
+}
+
  static struct block_cache_node *cache_find(int iftype, int devnum,
   lbaint_t start, lbaint_t blkcnt,
   unsigned long blksz)
diff --git a/include/blk.h b/include/blk.h
index d0c033aece..7070fd6af3 100644
--- a/include/blk.h
+++ b/include/blk.h
@@ -113,6 +113,12 @@ struct blk_desc {
(PAD_SIZE(size, blk_desc->blksz))
  
  #if CONFIG_IS_ENABLED(BLOCK_CACHE)

+
+/**
+ * blkcache_init() - initialize the block cache list pointers
+ */
+void blkcache_init(void);
+
  /**
   * blkcache_read() - attempt to read a set of blocks from cache
   *



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Re: [U-Boot] [PATCH] blk: Check if_type in blk_get_devnum_by_typename

2019-11-24 Thread Heinrich Schuchardt

On 11/24/19 7:09 PM, Juha Sarlin wrote:

While searching for a BLK device, this function checks only for a
matching devnum. It should check if_type, too.


Could you, please, describe in which cases you have observed a problem
and how it can be reproduced.

According to the function description the relevant interface type check is
device_get_uclass_id(dev->parent) != uclass_id



Signed-off-by: Juha Sarlin 
---

  drivers/block/blk-uclass.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c
index ca8978f0e1..78f2bcab09 100644
--- a/drivers/block/blk-uclass.c
+++ b/drivers/block/blk-uclass.c
@@ -112,7 +112,7 @@ struct blk_desc *blk_get_devnum_by_typename(const char 
*if_typename, int devnum)


Should the logic need changing, please, update the function description.
Please, use Sphinx style for the function description.

Best regards

Heinrich



debug("%s: if_type=%d, devnum=%d: %s, %d, %d\n", __func__,
  if_type, devnum, dev->name, desc->if_type, desc->devnum);
-   if (desc->devnum != devnum)
+   if (desc->if_type != if_type || desc->devnum != devnum)
continue;

/* Find out the parent device uclass */



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[U-Boot] Pico-imx7d and imx7d sabre Break on 2020.01-rc3

2019-11-24 Thread Joris Offouga

Anatolij, Fabio


I just compiled a fresh U-Boot with U-Boot master and It looks
like commit f0b54d (video: mxsfb: Configure the clock after eLCDIF 
reset") [1]

breaks my Pico-imx7d and imx7d-Sabre.
see logs after:

U-Boot 2020.01-rc3-00489-g47b48fe186 (Nov 24 2019 - 15:18:23 +0100)

CPU:   Freescale i.MX7D rev1.2 1000 MHz (running at 792 MHz)
CPU:   Commercial temperature grade (0C to 95C) at 36C
Reset cause: POR
Model: Freescale i.MX7 SabreSD Board
Board: i.MX7D SABRESD in secure mode
DRAM:  1 GiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... OK
Video: 480x272x24

After revert it  :

U-Boot 2020.01-rc3-00490-g6bebc83c0a (Nov 24 2019 - 15:51:16 +0100)

CPU:   Freescale i.MX7D rev1.2 1000 MHz (running at 792 MHz)
CPU:   Commercial temperature grade (0C to 95C) at 36C
Reset cause: POR
Model: Freescale i.MX7 SabreSD Board
Board: i.MX7D SABRESD in secure mode
DRAM:  1 GiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... OK
Video: 480x272x24
In:    serial
Out:   serial
Err:   serial
Net:   FEC0
Hit any key to stop autoboot:  0

So, can you consider this commit 'not applicable' for next release ?

[1]- 
https://gitlab.denx.de/u-boot/u-boot/commit/ec3dcea7447031463643c33143b3a5f027f0b54d


Best Regards,

Joris

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[U-Boot] [PATCH] armv8: layerscape: fix SPL multi DTB loading

2019-11-24 Thread Michael Walle
Mark board_fit_config_name_match() as weak so a board can overwrite the
empty function.

Signed-off-by: Michael Walle 
---
 arch/arm/cpu/armv8/fsl-layerscape/spl.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c 
b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
index 3f6a5f6a42..0195a2d96c 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
@@ -128,7 +128,7 @@ int spl_start_uboot(void)
 }
 #endif /* CONFIG_SPL_OS_BOOT */
 #ifdef CONFIG_SPL_LOAD_FIT
-int board_fit_config_name_match(const char *name)
+__weak int board_fit_config_name_match(const char *name)
 {
/* Just empty function now - can't decide what to choose */
debug("%s: %s\n", __func__, name);
-- 
2.20.1

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Re: [U-Boot] Pico-imx7d and imx7d sabre Break on 2020.01-rc3

2019-11-24 Thread Fabio Estevam
Hi Joris,

On Sun, Nov 24, 2019 at 5:06 PM Joris Offouga  wrote:
>
> Anatolij, Fabio
>
>
> I just compiled a fresh U-Boot with U-Boot master and It looks
> like commit f0b54d (video: mxsfb: Configure the clock after eLCDIF
> reset") [1]
> breaks my Pico-imx7d and imx7d-Sabre.
> see logs after:
>
> U-Boot 2020.01-rc3-00489-g47b48fe186 (Nov 24 2019 - 15:18:23 +0100)
>
> CPU:   Freescale i.MX7D rev1.2 1000 MHz (running at 792 MHz)
> CPU:   Commercial temperature grade (0C to 95C) at 36C
> Reset cause: POR
> Model: Freescale i.MX7 SabreSD Board
> Board: i.MX7D SABRESD in secure mode
> DRAM:  1 GiB
> MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
> Loading Environment from MMC... OK
> Video: 480x272x24
>
> After revert it  :
>
> U-Boot 2020.01-rc3-00490-g6bebc83c0a (Nov 24 2019 - 15:51:16 +0100)
>
> CPU:   Freescale i.MX7D rev1.2 1000 MHz (running at 792 MHz)
> CPU:   Commercial temperature grade (0C to 95C) at 36C
> Reset cause: POR
> Model: Freescale i.MX7 SabreSD Board
> Board: i.MX7D SABRESD in secure mode
> DRAM:  1 GiB
> MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
> Loading Environment from MMC... OK
> Video: 480x272x24
> In:serial
> Out:   serial
> Err:   serial
> Net:   FEC0
> Hit any key to stop autoboot:  0
>
> So, can you consider this commit 'not applicable' for next release ?

Thanks. Let me send a revert.
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[U-Boot] [PATCH] Revert "video: mxsfb: Configure the clock after eLCDIF reset"

2019-11-24 Thread Fabio Estevam
Commit ec3dcea74470 ("video: mxsfb: Configure the clock after eLCDIF reset")
causes boot regression on  imx7d-pico/imx7d-sdb boards, so revert it
until a better solution is prepared.

This reverts commit ec3dcea7447031463643c33143b3a5f027f0b54d.

Reported-by: Joris Offouga 
Signed-off-by: Fabio Estevam 
---
 drivers/video/mxsfb.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index d73a8bac99..c52981053e 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -57,6 +57,9 @@ static void mxs_lcd_init(u32 fb_addr, struct ctfb_res_modes 
*mode, int bpp)
uint32_t word_len = 0, bus_width = 0;
uint8_t valid_data = 0;
 
+   /* Kick in the LCDIF clock */
+   mxs_set_lcdclk(MXS_LCDIF_BASE, PS2KHZ(mode->pixclock));
+
/* Restart the LCDIF block */
mxs_reset_block(®s->hw_lcdif_ctrl_reg);
 
@@ -127,9 +130,6 @@ static void mxs_lcd_init(u32 fb_addr, struct ctfb_res_modes 
*mode, int bpp)
/* FIFO cleared */
writel(LCDIF_CTRL1_FIFO_CLEAR, ®s->hw_lcdif_ctrl1_clr);
 
-   /* Kick in the LCDIF clock */
-   mxs_set_lcdclk(MXS_LCDIF_BASE, PS2KHZ(mode->pixclock));
-
/* RUN! */
writel(LCDIF_CTRL_RUN, ®s->hw_lcdif_ctrl_set);
 }
-- 
2.17.1

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Re: [U-Boot] [PATCH 5/6] arm: dts: ls1028a: adds Ethernet switch node and its dependencies

2019-11-24 Thread Alexandru Marginean
Hi Michael,

On 11/24/2019 1:11 AM, Michael Walle wrote:
> Am 2019-11-22 02:36, schrieb Alex Marginean:
>> The definition follows the DSA binding in kernel and describes the 
>> switch,
>> its ports and PHYs.
>> ENETC PF6 is the 2nd Eth controller linked to the switch on LS1028, it is
> 
> nitpicking.. LS1028A
> 
> 
>> not used in U-Boot and was disabled.
> 
> it should be checked that the connected enetc port should be enabled. 
> otherwise this driver goes awry.

On LS1028A if mater Eth is disabled (ENETC PF2) there is a crash, I 
assume that's what you bumped into.  From the looks of it that's caused 
by a hardware issue.  For others reading this, the issue is making PCI 
PF5 (the switch) unable to use its internal MDIO registers if PF2 
(master Eth) is disabled.
I don't think I want to have switch driver code check on the ENETC 
functions, this should end up in a SoC erratum with the recommendation 
to have PF2 enabled when using the switch.

On other platforms having a master Eth disabled means traffic through 
the switch won't work, but should not crash U-Boot either, uclass code 
seems to be fine in that regard.

Thanks for the review and for the comments, I'll send a v2 for this series.

Alex


> 
> [snip]
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Re: [U-Boot] [PATCH] Revert "video: mxsfb: Configure the clock after eLCDIF reset"

2019-11-24 Thread Anatolij Gustschin
Hi Fabio,

On Sun, 24 Nov 2019 17:37:52 -0300
Fabio Estevam feste...@gmail.com wrote:

> Commit ec3dcea74470 ("video: mxsfb: Configure the clock after eLCDIF reset")
> causes boot regression on  imx7d-pico/imx7d-sdb boards, so revert it
> until a better solution is prepared.
> 
> This reverts commit ec3dcea7447031463643c33143b3a5f027f0b54d.
> 
> Reported-by: Joris Offouga 
> Signed-off-by: Fabio Estevam 
> ---
>  drivers/video/mxsfb.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)

Applied to u-boot-video/master, thanks!

--
Anatolij
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[U-Boot] Please pull u-boot-video

2019-11-24 Thread Anatolij Gustschin
Hi Tom,

The following changes since commit 9a0cbae22a613dfd55e15565785749b74c19fdf0:

  Merge tag 'u-boot-rockchip-20191124' of 
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip (2019-11-23 20:50:11 
-0500)

are available in the Git repository at:

  https://gitlab.denx.de/u-boot/custodians/u-boot-video.git 
tags/fixes-for-v2020.01

for you to fetch changes up to beeb57f0a66658aacad3f12f1a31e65f5d22e46d:

  Revert "video: mxsfb: Configure the clock after eLCDIF reset" (2019-11-24 
21:50:44 +0100)


- fix mxsfb regression on pico-imx7d and imx7d-sabre


Fabio Estevam (1):
  Revert "video: mxsfb: Configure the clock after eLCDIF reset"

 drivers/video/mxsfb.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

Please pull. Thanks!

Anatolij
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[U-Boot] [GIT PULL resed] Raspberry Pi updates for v2020.01

2019-11-24 Thread Matthias Brugger
Hi Tom,

This is a new pull request for the RPi updates for v2020.01.

After you noticed that the first pull request broke FAT implementation I deleted
the corresponding patch series from the pull request. In the meantime the one
binary support for RPi is ready to be merged, so I added the series.

Please have a look, you can find the travis-ci here:
https://travis-ci.org/mbgg/u-boot/builds/616217762

Regards,
Matthias

---

The following changes since commit d4a31e8ee5592072d8d5208b3e950cba2d89b6bd:

  Prepare v2020.01-rc3 (2019-11-18 21:31:49 -0500)

are available in the Git repository at:

  https://github.com/mbgg/u-boot tags/rpi-next-2020.01

for you to fetch changes up to 5694090670e262b038377bf196188d8089dc90c4:

  ARM: defconfig: add unified config for RPi3 and RPi4 (2019-11-24 10:46:28 
+0100)


- add RPi4 upstream compatible to pinctrl
- fix boot banner on RPi3/4
- add support for one binary on RPi3/4


Matthias Brugger (9):
  pinctrl: bcm283x: Add compatible for RPi4
  fdt: fix bcm283x dm-pre-reloc definitions
  arm: dts: bcm283x: Rename U-Boot file
  drivers: bcm283x: Set pre-location flag for OF_BOARD
  rpi: push fw_dtb_pointer in the .data section
  ARM: bcm283x: Move BCM283x_BASE to a global variable
  ARM: bcm283x: Set rpi_bcm283x_base at run-time
  ARM: bcm283x: Set memory map at run-time
  ARM: defconfig: add unified config for RPi3 and RPi4

 .../{bcm283x-uboot.dtsi => bcm283x-u-boot.dtsi}|   4 -
 arch/arm/mach-bcm283x/Kconfig  |  13 +--
 arch/arm/mach-bcm283x/include/mach/base.h  |  11 ++
 arch/arm/mach-bcm283x/include/mach/mbox.h  |   4 +-
 arch/arm/mach-bcm283x/include/mach/sdhci.h |   5 +-
 arch/arm/mach-bcm283x/include/mach/timer.h |   7 +-
 arch/arm/mach-bcm283x/include/mach/wdog.h  |   5 +-
 arch/arm/mach-bcm283x/init.c   | 116 +
 arch/arm/mach-bcm283x/mbox.c   |   1 +
 arch/arm/mach-bcm283x/reset.c  |  20 +++-
 board/raspberrypi/rpi/lowlevel_init.S  |  12 +--
 board/raspberrypi/rpi/rpi.c|  52 +
 configs/rpi_arm64_defconfig|  45 
 drivers/pinctrl/broadcom/pinctrl-bcm283x.c |   3 +-
 drivers/serial/serial_bcm283x_mu.c |   2 +-
 drivers/serial/serial_bcm283x_pl011.c  |   2 +-
 include/configs/rpi.h  |   4 +
 17 files changed, 227 insertions(+), 79 deletions(-)
 rename arch/arm/dts/{bcm283x-uboot.dtsi => bcm283x-u-boot.dtsi} (90%)
 create mode 100644 arch/arm/mach-bcm283x/include/mach/base.h
 create mode 100644 configs/rpi_arm64_defconfig
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[U-Boot] [PATCH] blk: Check if_type in blk_get_devnum_by_typename

2019-11-24 Thread Juha Sarlin
While searching for a BLK device, this function checks only for a
matching devnum. It should check if_type, too.

Signed-off-by: Juha Sarlin 
---

 drivers/block/blk-uclass.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c
index ca8978f0e1..78f2bcab09 100644
--- a/drivers/block/blk-uclass.c
+++ b/drivers/block/blk-uclass.c
@@ -112,7 +112,7 @@ struct blk_desc *blk_get_devnum_by_typename(const char 
*if_typename, int devnum)
 
debug("%s: if_type=%d, devnum=%d: %s, %d, %d\n", __func__,
  if_type, devnum, dev->name, desc->if_type, desc->devnum);
-   if (desc->devnum != devnum)
+   if (desc->if_type != if_type || desc->devnum != devnum)
continue;
 
/* Find out the parent device uclass */
-- 
2.20.1.98.gecbdaf0899

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[U-Boot] [PATCH 2/2] bootm: Add a bootm command for type IH_OS_EFI

2019-11-24 Thread Cristian Ciocaltea
Add support for booting EFI binaries contained in FIT images.
A typical usage scenario is chain-loading GRUB2 in a verified
boot environment.

Signed-off-by: Cristian Ciocaltea 
---
 cmd/Kconfig   |  9 -
 cmd/bootefi.c |  2 +-
 common/bootm_os.c | 44 
 include/bootm.h   |  2 ++
 4 files changed, 55 insertions(+), 2 deletions(-)

diff --git a/cmd/Kconfig b/cmd/Kconfig
index cf982ff65e..1bec840f5a 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -263,6 +263,13 @@ config CMD_BOOTI
help
  Boot an AArch64 Linux Kernel image from memory.
 
+config BOOTM_EFI
+   bool "Support booting EFI OS images"
+   depends on CMD_BOOTEFI
+   default y
+   help
+ Support booting EFI images via the bootm command.
+
 config BOOTM_LINUX
bool "Support booting Linux OS images"
depends on CMD_BOOTM || CMD_BOOTZ || CMD_BOOTI
@@ -316,7 +323,7 @@ config CMD_BOOTEFI
depends on EFI_LOADER
default y
help
- Boot an EFI image from memory.
+ Boot an EFI binary from memory.
 
 config CMD_BOOTEFI_HELLO_COMPILE
bool "Compile a standard EFI hello world binary for testing"
diff --git a/cmd/bootefi.c b/cmd/bootefi.c
index f613cce7e2..f25d639dfe 100644
--- a/cmd/bootefi.c
+++ b/cmd/bootefi.c
@@ -553,7 +553,7 @@ static int do_efi_selftest(void)
  * @argv:  command line arguments
  * Return: status code
  */
-static int do_bootefi(cmd_tbl_t *cmdtp, int flag, int argc, char * const 
argv[])
+int do_bootefi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
efi_status_t ret;
 
diff --git a/common/bootm_os.c b/common/bootm_os.c
index 6fb7d658da..706151913a 100644
--- a/common/bootm_os.c
+++ b/common/bootm_os.c
@@ -462,6 +462,47 @@ static int do_bootm_tee(int flag, int argc, char * const 
argv[],
 }
 #endif
 
+#ifdef CONFIG_BOOTM_EFI
+static int do_bootm_efi(int flag, int argc, char * const argv[],
+   bootm_headers_t *images)
+{
+   int ret;
+   int local_argc = 2;
+   char *local_args[3];
+   char str_efi_addr[16];
+   char str_fdt_addr[16];
+
+   if (flag != BOOTM_STATE_OS_GO)
+   return 0;
+
+   /* Locate FDT etc */
+   ret = bootm_find_images(flag, argc, argv);
+   if (ret)
+   return ret;
+
+   printf("## Transferring control to EFI (at address %08lx) ...\n",
+  images->ep);
+   bootstage_mark(BOOTSTAGE_ID_RUN_OS);
+
+   local_args[0] = argv[0];
+
+   /* Write efi addr into string */
+   sprintf(str_efi_addr, "%lx", images->ep);
+   /* and provide it via the arguments */
+   local_args[1] = str_efi_addr;
+
+   if (images->ft_len) {
+   /* Write fdt addr into string */
+   sprintf(str_fdt_addr, "%lx", (unsigned long)images->ft_addr);
+   /* and provide it via the arguments */
+   local_args[2] = str_fdt_addr;
+   local_argc = 3;
+   }
+
+   return do_bootefi(NULL, 0, local_argc, local_args);
+}
+#endif
+
 static boot_os_fn *boot_os[] = {
[IH_OS_U_BOOT] = do_bootm_standalone,
 #ifdef CONFIG_BOOTM_LINUX
@@ -498,6 +539,9 @@ static boot_os_fn *boot_os[] = {
 #ifdef CONFIG_BOOTM_OPTEE
[IH_OS_TEE] = do_bootm_tee,
 #endif
+#ifdef CONFIG_BOOTM_EFI
+   [IH_OS_EFI] = do_bootm_efi,
+#endif
 };
 
 /* Allow for arch specific config before we boot */
diff --git a/include/bootm.h b/include/bootm.h
index edeeacb0df..a0da86dc32 100644
--- a/include/bootm.h
+++ b/include/bootm.h
@@ -37,7 +37,9 @@ typedef int boot_os_fn(int flag, int argc, char * const 
argv[],
 extern boot_os_fn do_bootm_linux;
 extern boot_os_fn do_bootm_vxworks;
 
+int do_bootefi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
 int do_bootelf(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+
 void lynxkdi_boot(image_header_t *hdr);
 
 boot_os_fn *bootm_os_get_boot_func(int os);
-- 
2.17.1

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[U-Boot] [PATCH 1/2] image: Add IH_OS_EFI for EFI chain-load boot

2019-11-24 Thread Cristian Ciocaltea
Add a new OS type to be used for chain-loading an EFI compatible
firmware or boot loader like GRUB2, possibly in a verified boot
scenario.

Bellow is sample ITS file that generates a FIT image supporting
secure boot. Please note the presence of 'os = "efi";' line, which
identifies the currently introduced OS type:

/ {
#address-cells = <1>;

images {
efi-grub {
description = "GRUB EFI";
data = /incbin/("EFI/BOOT/bootarm.efi");
type = "kernel_noload";
arch = "arm";
os = "efi";
compression = "none";
load = <0x0>;
entry = <0x0>;
hash-1 {
algo = "sha256";
};
};
};

configurations {
default = "config-grub";
config-grub {
kernel = "efi-grub";
signature-1 {
algo = "sha256,rsa2048";
sign-images = "kernel";
};
};
};
};

Signed-off-by: Cristian Ciocaltea 
---
 common/image-fit.c | 3 ++-
 common/image.c | 1 +
 include/image.h| 1 +
 3 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/common/image-fit.c b/common/image-fit.c
index 5c63c769de..19e313bf41 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -1925,7 +1925,8 @@ int fit_image_load(bootm_headers_t *images, ulong addr,
image_type == IH_TYPE_FPGA ||
fit_image_check_os(fit, noffset, IH_OS_LINUX) ||
fit_image_check_os(fit, noffset, IH_OS_U_BOOT) ||
-   fit_image_check_os(fit, noffset, IH_OS_OPENRTOS);
+   fit_image_check_os(fit, noffset, IH_OS_OPENRTOS) ||
+   fit_image_check_os(fit, noffset, IH_OS_EFI);
 
/*
 * If either of the checks fail, we should report an error, but
diff --git a/common/image.c b/common/image.c
index f17fa40c49..2e0e2b0e7f 100644
--- a/common/image.c
+++ b/common/image.c
@@ -134,6 +134,7 @@ static const table_entry_t uimage_os[] = {
{   IH_OS_OPENRTOS, "openrtos", "OpenRTOS", },
 #endif
{   IH_OS_OPENSBI,  "opensbi",  "RISC-V OpenSBI",   },
+   {   IH_OS_EFI,  "efi",  "EFI Firmware" },
 
{   -1, "", "", },
 };
diff --git a/include/image.h b/include/image.h
index f4d2aaf53e..4a280b78e7 100644
--- a/include/image.h
+++ b/include/image.h
@@ -157,6 +157,7 @@ enum {
IH_OS_ARM_TRUSTED_FIRMWARE, /* ARM Trusted Firmware */
IH_OS_TEE,  /* Trusted Execution Environment */
IH_OS_OPENSBI,  /* RISC-V OpenSBI */
+   IH_OS_EFI,  /* EFI Firmware (e.g. GRUB2) */
 
IH_OS_COUNT,
 };
-- 
2.17.1

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[U-Boot] [PATCH 0/2] Add support for booting EFI FIT images

2019-11-24 Thread Cristian Ciocaltea
Currently the only way to run an EFI binary like GRUB2 is via the
'bootefi' command, which cannot be used in a verified boot scenario.

The obvious solution to this limitation is to add support for
booting FIT images containing those EFI binaries.

The implementation relies on a new image type - IH_OS_EFI - which
can be created by using 'os = "efi"' inside an ITS file:

/ {
#address-cells = <1>;

images {
efi-grub {
description = "GRUB EFI";
data = /incbin/("EFI/BOOT/bootarm.efi");
type = "kernel_noload";
arch = "arm";
os = "efi";
compression = "none";
load = <0x0>;
entry = <0x0>;
hash-1 {
algo = "sha256";
};
};
};

configurations {
default = "config-grub";
config-grub {
kernel = "efi-grub";
signature-1 {
algo = "sha256,rsa2048";
sign-images = "kernel";
};
};
};
};

The bootm command has been extended to handle the IH_OS_EFI images.
To enable this feature, a new configuration option has been added:
BOOTM_EFI

I tested the solution using the 'qemu_arm' board:

=> load scsi 0:1 ${kernel_addr_r} efi-image.fit
=> bootm ${kernel_addr_r}#config-grub


Cristian Ciocaltea (2):
  image: Add IH_OS_EFI for EFI chain-load boot
  bootm: Add a bootm command for type IH_OS_EFI

 cmd/Kconfig|  9 -
 cmd/bootefi.c  |  2 +-
 common/bootm_os.c  | 44 
 common/image-fit.c |  3 ++-
 common/image.c |  1 +
 include/bootm.h|  2 ++
 include/image.h|  1 +
 7 files changed, 59 insertions(+), 3 deletions(-)

-- 
2.17.1

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Re: [U-Boot] [PATCH] blk: Check if_type in blk_get_devnum_by_typename

2019-11-24 Thread Juha Sarlin

> On 24 Nov 2019, at 19:37, Heinrich Schuchardt  wrote:
> 
> On 11/24/19 7:09 PM, Juha Sarlin wrote:
>> While searching for a BLK device, this function checks only for a
>> matching devnum. It should check if_type, too.
> 
> Could you, please, describe in which cases you have observed a problem
> and how it can be reproduced.
> 
> According to the function description the relevant interface type check is
> device_get_uclass_id(dev->parent) != uclass_id

I was wrong, it isn't really a bug. I was misled by all the other blk-finding 
functions that check if_type instead of parent class. I think that checking 
if_type would work here, too.

Or perhaps this case is the first step towards removing the if_type field in 
the future? There seems to be a 1-1 mapping from almost every if_type to 
uclass_id.

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[U-Boot] [PATCH 1/1] buildman: Improve [make-flags] section parser to allow quoted strings

2019-11-24 Thread Cristian Ciocaltea
The parser responsible for the '[make-flags]' section in
the '.buildman' settings file is currently not able to
handle quoted strings, as given in the sample bellow:

[make-flags]
qemu_arm=HOSTCC="cc -isystem /add/include" HOSTLDFLAGS="-L/add/lib"

This patch replaces the simple string splitter based on the 
delimiter with a regex tokenizer that preserves spaces inside double
quoted strings.

Signed-off-by: Cristian Ciocaltea 
---
 tools/buildman/toolchain.py | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/tools/buildman/toolchain.py b/tools/buildman/toolchain.py
index cc26e2ede5..086a4d47cd 100644
--- a/tools/buildman/toolchain.py
+++ b/tools/buildman/toolchain.py
@@ -435,9 +435,10 @@ class Toolchains:
 self._make_flags['target'] = board.target
 arg_str = self.ResolveReferences(self._make_flags,
self._make_flags.get(board.target, ''))
-args = arg_str.split(' ')
+args = re.findall("(?:\".*?\"|\S)+", arg_str)
 i = 0
 while i < len(args):
+args[i] = args[i].replace('"', '')
 if not args[i]:
 del args[i]
 else:
-- 
2.17.1

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[U-Boot] [RFC PATCH 0/1] Update doc/README.drivers.eth

2019-11-24 Thread Andre Przywara
Hi,

during my quest in converting two network drivers to the driver model,
I couldn't find any real documentation in explaining the new network
driver model, or how to address such a port.
After some digging in the code (both in the framework and in some
drivers), I decided to update the existing Ethernet drivers document.

This is my first shot, I surely made many mistakes or misunderstood some
things. Some parts are not very clear to me, for instance to exact
semantic of the recv() function and this ETH_RECV_CHECK_DEVICE flag.
The uclass implementation of eth_rx() seems to diverge in the code
flow.

Also I found drivers implementing send() slightly differently, some
actually wait for the packet to be send, others copy the data and just
queue the packet.

I would be very grateful for a clarification on the intended behaviour
on both functions.

Sending this as an RFC to get some more feedback.
The diff isn't really helpful, different algorithms didn't really make
a difference. I re-used some paragraphs from the old document to describe
the legacy part at the end, and re-used some sentences for the callback
function. But the rest is probably just a rewrite, so a super-clever
diff wouldn't be of any help here anyway.
I recommend to just look at the new document, preferrably with some reST
rendering.

Cheers,
Andre

Andre Przywara (1):
  doc: net: Rewrite network driver documentation

 doc/README.drivers.eth | 438 ++---
 1 file changed, 271 insertions(+), 167 deletions(-)

-- 
2.14.5

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[U-Boot] [RFC PATCH 1/1] doc: net: Rewrite network driver documentation

2019-11-24 Thread Andre Przywara
doc/README.drivers.eth seems like a good source for understanding
U-Boot's network subsystem, but is only talking about legacy network
drivers. This is particularly sad as proper documentation would help in
porting drivers over to the driver model.

Rewrite the document to describe network drivers in the new driver model
world. Most driver callbacks are almost identical in their semantic, but
recv() differs in some important details.

Also keep some parts of the original text at the end, to help
understanding old drivers. Add some hints on how to port drivers over.

This also uses the opportunity to reformat the document in reST.

Signed-off-by: Andre Przywara 
---
 doc/README.drivers.eth | 438 ++---
 1 file changed, 271 insertions(+), 167 deletions(-)

diff --git a/doc/README.drivers.eth b/doc/README.drivers.eth
index 1a9a23b51b..d1920ee47d 100644
--- a/doc/README.drivers.eth
+++ b/doc/README.drivers.eth
@@ -1,9 +1,3 @@
-!!! WARNING !!!
-
-This guide describes to the old way of doing things. No new Ethernet drivers
-should be implemented this way. All new drivers should be written against the
-U-Boot core driver model. See doc/driver-model/README.txt
-
 ---
  Ethernet Driver Guide
 ---
@@ -13,203 +7,313 @@ to be easily added and controlled at runtime.  This guide 
is meant for people
 who wish to review the net driver stack with an eye towards implementing your
 own ethernet device driver.  Here we will describe a new pseudo 'APE' driver.
 
---
- Driver Functions
---
-
-All functions you will be implementing in this document have the return value
-meaning of 0 for success and non-zero for failure.
-
- --
-  Register
- --
-
-When U-Boot initializes, it will call the common function eth_initialize().
-This will in turn call the board-specific board_eth_init() (or if that fails,
-the cpu-specific cpu_eth_init()).  These board-specific functions can do random
-system handling, but ultimately they will call the driver-specific register
-function which in turn takes care of initializing that particular instance.
+Most exisiting drivers do already - and new network driver MUST - use the
+U-Boot core driver model. Generic information about this can be found in
+doc/driver-model/design.rst, this document will thus focus on the network
+specific code parts.
+Some drivers are still using the old Ethernet interface, differences between
+the two and hints about porting will be handled at the end.
+
+==
+ Driver framework
+==
+
+A network driver following the driver model must declare itself using
+the UCLASS_ETH .id field in the U-Boot driver struct:
+
+.. code-block:: c
+
+   U_BOOT_DRIVER(eth_ape) = {
+   .name   = "eth_ape",
+   .id = UCLASS_ETH,
+   .of_match   = eth_ape_ids,
+   .ofdata_to_platdata = eth_ape_ofdata_to_platdata,
+   .probe  = eth_ape_probe,
+   .ops= ð_ape_ops,
+   .priv_auto_alloc_size   = sizeof(struct eth_ape_dev),
+   .platdata_auto_alloc_size = sizeof(struct eth_ape_pdata),
+   .flags  = DM_FLAG_ALLOC_PRIV_DMA,
+   };
+
+struct eth_ape_dev contains runtime per-instance data, like buffers, pointers
+to current descriptors, current speed settings, pointers to PHY related data
+(like struct mii_dev) and so on. Declaring its size in .priv_auto_alloc_size
+will let the driver framework allocate it at the right time.
+It can be retrieved using a dev_get_priv(dev) call.
+
+struct eth_ape_pdata contains static platform data, like the MMIO base address,
+a hardware variant, the MAC address. ``struct eth_pdata eth_pdata``
+as the first member of this struct helps to avoid duplicated code.
+If you don't need any more platform data beside the standard member,
+just use sizeof(struct eth_pdata) for the platdata_auto_alloc_size.
+
+PCI devices add a line pointing to supported vendor/device ID pairs:
+
+.. code-block:: c
+
+   static struct pci_device_id supported[] = {
+   { PCI_DEVICE(PCI_VENDOR_ID_APE, 0x4223) },
+   {}
+   };
+
+   U_BOOT_PCI_DEVICE(eth_ape, supported);
+
+
+Device probing and instantiation will be handled by the driver model framework,
+so follow the guidelines there. The probe() function would initialise the
+platform specific parts of the hardware, like clocks, resets, GPIOs, the MDIO
+bus. Also it would take care of any special PHY setup (power rails, enable
+bits for internal PHYs, etc.).
+
+
+ Callback functions
+
+
+The real work will be done in the callback function the driver provides
+by defining the members of struct eth_ops:
+
+.. code-block:: c
+
+   struct eth_ops {
+   int (*start)(struct udevice *dev);
+

[U-Boot] [PATCH] binman: README: fix default filename of u-boot-with-ucode-ptr

2019-11-24 Thread Masahiro Yamada
The suffix should be ".bin" instead of ".dtb" .

Signed-off-by: Masahiro Yamada 
---

 tools/binman/README.entries | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/binman/README.entries b/tools/binman/README.entries
index 10994335217c..26050da7702f 100644
--- a/tools/binman/README.entries
+++ b/tools/binman/README.entries
@@ -971,7 +971,7 @@ Entry: u-boot-with-ucode-ptr: U-Boot with embedded 
microcode pointer
 
 
 Properties / Entry arguments:
-- filename: Filename of u-boot-nodtb.dtb (default 'u-boot-nodtb.dtb')
+- filename: Filename of u-boot-nodtb.bin (default 'u-boot-nodtb.bin')
 - optional-ucode: boolean property to make microcode optional. If the
 u-boot.bin image does not include microcode, no error will
 be generated.
-- 
2.17.1

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Re: [U-Boot] [PATCH] binman: README: fix default filename of u-boot-with-ucode-ptr

2019-11-24 Thread Bin Meng
On Mon, Nov 25, 2019 at 9:45 AM Masahiro Yamada
 wrote:
>
> The suffix should be ".bin" instead of ".dtb" .
>
> Signed-off-by: Masahiro Yamada 
> ---
>
>  tools/binman/README.entries | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>

Reviewed-by: Bin Meng 
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[U-Boot] [PATCH v2] configs: ls1028ardb: enable usb net r8152_eth

2019-11-24 Thread Yinbo Zhu
Enable ls1028ardb usb net r8152_eth

Signed-off-by: Yinbo Zhu 
---
 configs/ls1028ardb_tfa_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig
index 1fab450..0664014 100644
--- a/configs/ls1028ardb_tfa_defconfig
+++ b/configs/ls1028ardb_tfa_defconfig
@@ -76,4 +76,6 @@ CONFIG_USB_XHCI_DWC3=y
 CONFIG_WDT=y
 CONFIG_WDT_SP805=y
 CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_RTL8152=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
-- 
2.7.4

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Re: [U-Boot] [PATCH v3] arm: add acpi support for the arm

2019-11-24 Thread Steven Hao
Dear Bin:

Firstly:
I know that acpi about x86 is existing. And it is usefull for x86 platfporm. If 
it  is used to arm platform,some modification may have to do. For example,facs 
table is useless for arm.

In adition,The acpi table is writed statically and then modified dynamically in 
my patch. It is a new method.

I want to consult that whether my method is helpful or not.

Secondly:
If i want to reuse the x86-acpi. I will overwrite the write_acpi_tables 
function. But the definition about acpi strcuture is placed in 
arch/x86/include/asm directory. It can not be used to arm plateform. If the 
acpi library need to surport for all platform,i think it should move to 
/include directory.


Thank you
Steven Hao

获取 Outlook for iOS

发件人: Bin Meng 
发送时间: Thursday, November 21, 2019 11:18:24 PM
收件人: Steven Hao 
抄送: xypron.g...@gmx.de ; liu...@phytium.com.cn 
; ag...@csgraf.de ; 
ja...@amarulasolutions.com ; marek.va...@gmail.com 
; s...@denx.de ; patrice.chot...@st.com 
; a...@ti.com ; 
horatiu.vul...@microchip.com ; 
narmstr...@baylibre.com ; ryder@mediatek.com 
; igor.opan...@gmail.com ; 
patrick.delau...@st.com ; eugen.hris...@microchip.com 
; s...@chromium.org ; 
judge.pack...@gmail.com ; 
yamada.masah...@socionext.com ; 
swar...@nvidia.com ; michal.si...@xilinx.com 
; u-boot@lists.denx.de ; Andy 
Shevchenko 
主题: Re: [PATCH v3] arm: add acpi support for the arm

Hi Steven,

On Wed, Nov 20, 2019 at 4:41 PM Steven Hao  wrote:
>
> This adds acpi code for arm and the acpi tables about Phytium Durian Board.
> The acpi table only support rsdp, rsdt, xsdt, fadt, dsdt, ssdt, gtdt, madt,
> mcfg, iort, spcr.
>
> Signed-off-by: Steven Hao 
> ---
> Changes for v3:
>  - modify arch/arm/Kconfig
>  - modify lib/efi_loader/efi_setup.c
>
> Changes for v2:
>  - execute git pull --rebase
> ---
>  MAINTAINERS|   3 +
>  Makefile   |   1 +
>  arch/arm/Kconfig   |  69 ++
>  arch/arm/include/asm/acpi_table.h  |  39 ++
>  arch/arm/include/asm/acpi_table/acpi61.h   | 755 
> +
>  arch/arm/include/asm/acpi_table/acpi_lib.h |  89 +++
>  arch/arm/include/asm/acpi_table/arm_platform.h |  93 +++
>  .../include/asm/acpi_table/io_remapping_table.h| 179 +
>  arch/arm/include/asm/acpi_table/spcr_table.h   | 175 +
>  arch/arm/lib/Makefile  |   1 +
>  arch/arm/lib/acpi_table.c  | 244 +++
>  board/phytium/durian/Makefile  |  18 +
>  board/phytium/durian/acpi_platform.h   |  38 ++
>  board/phytium/durian/acpi_table.c  |  53 ++
>  board/phytium/durian/acpi_table/dsdt.asl   | 305 +
>  board/phytium/durian/acpi_table/fadt.c |  83 +++
>  board/phytium/durian/acpi_table/gtdt.c |  81 +++
>  board/phytium/durian/acpi_table/iort.c | 117 
>  board/phytium/durian/acpi_table/madt.c |  69 ++
>  board/phytium/durian/acpi_table/mcfg.c |  68 ++
>  board/phytium/durian/acpi_table/rsdp.c |  25 +
>  board/phytium/durian/acpi_table/rsdt.c |  28 +
>  board/phytium/durian/acpi_table/spcr.c |  78 +++
>  board/phytium/durian/acpi_table/ssdt.asl   | 190 ++
>  board/phytium/durian/acpi_table/xsdt.c |  31 +
>  cmd/bootefi.c  |   6 +-
>  configs/durian_defconfig   |   9 +
>  include/configs/durian.h   |   8 +-
>  lib/efi_loader/Makefile|   1 +
>  lib/efi_loader/efi_setup.c |   2 +-
>  scripts/Makefile.lib   |   8 +
>  31 files changed, 2860 insertions(+), 6 deletions(-)
>  create mode 100644 arch/arm/include/asm/acpi_table.h
>  create mode 100644 arch/arm/include/asm/acpi_table/acpi61.h
>  create mode 100644 arch/arm/include/asm/acpi_table/acpi_lib.h
>  create mode 100644 arch/arm/include/asm/acpi_table/arm_platform.h
>  create mode 100644 arch/arm/include/asm/acpi_table/io_remapping_table.h
>  create mode 100644 arch/arm/include/asm/acpi_table/spcr_table.h
>  create mode 100644 arch/arm/lib/acpi_table.c
>  create mode 100644 board/phytium/durian/acpi_platform.h
>  create mode 100644 board/phytium/durian/acpi_table.c
>  create mode 100644 board/phytium/durian/acpi_table/dsdt.asl
>  create mode 100644 board/phytium/durian/acpi_table/fadt.c
>  create mode 100644 board/phytium/durian/acpi_table/gtdt.c
>  create mode 100644 board/phytium/durian/acpi_table/iort.c
>  create mode 100644 board/phytium/durian/acpi_table/madt.c
>  create mode 100644 board/phytium/durian/acpi_table/mcfg.c
>  create mode 100644 board/phytium/durian/acpi_table/rsdp.c
>  create mode 100644 board/phytium/durian/acpi_table/rsdt.c
>  create mode 100644 board/phytium

Re: [U-Boot] [PATCH v3] arm: add acpi support for the arm

2019-11-24 Thread Bin Meng
Hi Steven,

On Mon, Nov 25, 2019 at 10:09 AM Steven Hao  wrote:
>
> Dear Bin:
>
> Firstly:
> I know that acpi about x86 is existing. And it is usefull for x86 platfporm. 
> If it  is used to arm platform,some modification may have to do. For 
> example,facs table is useless for arm.
>
> In adition,The acpi table is writed statically and then modified dynamically 
> in my patch. It is a new method.
>
> I want to consult that whether my method is helpful or not.
>
> Secondly:
> If i want to reuse the x86-acpi. I will overwrite the write_acpi_tables 
> function. But the definition about acpi strcuture is placed in 
> arch/x86/include/asm directory. It can not be used to arm plateform. If the 
> acpi library need to surport for all platform,i think it should move to 
> /include directory.
>

Yes, we all are aware that modifications are needed to the existing
x86 ACPI support to support ARM. We don't want to create 2 ACP
implementation in U-Boot.

Regards,
Bin
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Re: [U-Boot] [PATCH v3] arm: add acpi support for the arm

2019-11-24 Thread Steven Hao
Dear Bin:

I have a suggetion that the acpi specification definition such as all acpi 
table structure definition  should be place in /include directory.
and write_acpi_tables function can be placed in platform directory.  Creating 
acpi table mothod  can be diffrent between x86 and arm.

Thank you
Steven Hao

获取 Outlook for iOS

发件人: Bin Meng 
发送时间: Monday, November 25, 2019 10:13:40 AM
收件人: Steven Hao 
抄送: xypron.g...@gmx.de ; liu...@phytium.com.cn 
; ag...@csgraf.de ; 
ja...@amarulasolutions.com ; marek.va...@gmail.com 
; s...@denx.de ; patrice.chot...@st.com 
; a...@ti.com ; 
horatiu.vul...@microchip.com ; 
narmstr...@baylibre.com ; ryder@mediatek.com 
; igor.opan...@gmail.com ; 
patrick.delau...@st.com ; eugen.hris...@microchip.com 
; s...@chromium.org ; 
judge.pack...@gmail.com ; 
yamada.masah...@socionext.com ; 
swar...@nvidia.com ; michal.si...@xilinx.com 
; u-boot@lists.denx.de ; Andy 
Shevchenko 
主题: Re: [PATCH v3] arm: add acpi support for the arm

Hi Steven,

On Mon, Nov 25, 2019 at 10:09 AM Steven Hao  wrote:
>
> Dear Bin:
>
> Firstly:
> I know that acpi about x86 is existing. And it is usefull for x86 platfporm. 
> If it  is used to arm platform,some modification may have to do. For 
> example,facs table is useless for arm.
>
> In adition,The acpi table is writed statically and then modified dynamically 
> in my patch. It is a new method.
>
> I want to consult that whether my method is helpful or not.
>
> Secondly:
> If i want to reuse the x86-acpi. I will overwrite the write_acpi_tables 
> function. But the definition about acpi strcuture is placed in 
> arch/x86/include/asm directory. It can not be used to arm plateform. If the 
> acpi library need to surport for all platform,i think it should move to 
> /include directory.
>

Yes, we all are aware that modifications are needed to the existing
x86 ACPI support to support ARM. We don't want to create 2 ACP
implementation in U-Boot.

Regards,
Bin
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Re: [U-Boot] [PATCH] board: ti: am43xx: remove net platform code

2019-11-24 Thread Lokesh Vutla


On 22/11/19 10:56 PM, Grygorii Strashko wrote:
> The TI AM43xx platform has DM_ETH and OF_CONTROL enabled,
> so remove networking platform code.
> 
> Signed-off-by: Grygorii Strashko 


Reviewed-by: Lokesh Vutla 

Thanks and regards,
Lokesh
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Re: [U-Boot] [PATCH] board: ti: dra7-evm: remove net platform code

2019-11-24 Thread Lokesh Vutla


On 22/11/19 10:56 PM, Grygorii Strashko wrote:
> The DRA7 has DM_ETH and OF_CONTROL enabled, so remove networking platform
> code.
> 
> Signed-off-by: Grygorii Strashko 

Reviewed-by: Lokesh Vutla 

Thanks and regards,
Lokesh
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Re: [U-Boot] [PATCH v3 1/3] spi: nxp_fspi: new driver for the FlexSPI controller

2019-11-24 Thread Priyanka Jain


>-Original Message-
>From: U-Boot  On Behalf Of Michael Walle
>Sent: Thursday, November 21, 2019 6:18 PM
>To: u-boot@lists.denx.de
>Subject: Re: [U-Boot] [PATCH v3 1/3] spi: nxp_fspi: new driver for the FlexSPI
>controller
>
>Am 2019-11-06 00:03, schrieb Michael Walle:
>> This is a port of the kernel's spi-nxp-fspi driver. It uses the new
>> spi-mem interface and does not expose the more generic spi-xfer
>> interface. The source was taken from the v5.3-rc3 tag.
>>
>> The port was straightforward:
>>  - remove the interrupt handling and the completion by busy polling the
>>controller
>>  - remove locks
>>  - move the setup of the memory windows into claim_bus()
>>  - move the setup of the speed into set_speed()
>>  - port the device tree bindings from the original fspi_probe() to
>>ofdata_to_platdata()
>>
>> There were only some style change fixes, no change in any logic. For
>> example, there are busy loops where the return code is not handled
>> correctly, eg. only prints a warning with WARN_ON(). This port
>> intentionally left most functions unchanged to ease future bugfixes.
>>
>> This was tested on a custom LS1028A board. Because the LS1028A doesn't
>> have proper clock framework support, changing the clock speed was not
>> tested. This also means that it is not possible to change the SPI
>> speed on LS1028A for now (neither is it possible in the linux driver).
>>
>> Signed-off-by: Michael Walle 
>> Reviewed-by: Jagan Teki 
>> ---
>> changes since v1:
>>  - fixed typo, thanks Jagan
>> changes since v2:
>>  - none
>
>
>Ping. any news on this?
Will pick this patch in next merge window
>
>-michael
-priyankajain
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Re: [U-Boot] [PATCH v4] armv8: Add workaround for USB erratum A-050106

2019-11-24 Thread Priyanka Jain


>-Original Message-
>From: Ran Wang 
>Sent: Thursday, November 21, 2019 12:26 PM
>To: Priyanka Jain 
>Cc: u-boot@lists.denx.de; Albert Aribaud 
>Subject: RE: [PATCH v4] armv8: Add workaround for USB erratum A-050106
>
>Hi Priyanka,
>
>On Thursday, November 21, 2019 13:26, Priyanka Jain wrote:
>>
>>
>>
>> >-Original Message-
>> >From: Ran Wang 
>> >Sent: Wednesday, November 13, 2019 11:20 AM
>> >To: Priyanka Jain ; Albert Aribaud
>> >
>> >Cc: u-boot@lists.denx.de; Ran Wang 
>> >Subject: [PATCH v4] armv8: Add workaround for USB erratum A-050106
>> >
>> >USB3.0 Receiver needs to enable fixed equalization for each of PHY
>> >instances in an SOC. This is similar to erratum A-009007, but this
>> >one is for LX2160A, and the register value is different.
>> >
>> >Signed-off-by: Ran Wang 
>> >---
>> >Change in v4:
>> >- Include defines of USB_PHY_RX_EQ_VAL_3 and
>> >USB_PHY_RX_EQ_VAL_4 for
>> >  LS1028A to fix compile failure.
>> >
>> >Change in v3:
>> >- Rebase patch for latest U-Boot (v2019.10)
>> >
>> >Change in v2:
>> >- Move function erratum_a050106() under the scope of
>> >  CONFIG_FSL_LSCH3 to avoid compilation warning of
>> >  'defined but not used'.
>> >
>> > arch/arm/cpu/armv8/fsl-layerscape/Kconfig  |  4 
>> > arch/arm/cpu/armv8/fsl-layerscape/soc.c| 12 +++-
>> > arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h |  6 ++
>> > 3 files changed, 21 insertions(+), 1 deletion(-)
>> >
>> >diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
>> >b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
>> >index f1578b1..c7f28b6 100644
>> >--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
>> >+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
>> >@@ -219,6 +219,7 @@ config ARCH_LX2160A
>> >select SYS_FSL_DDR_VER_50
>> >select SYS_FSL_EC1
>> >select SYS_FSL_EC2
>> >+   select SYS_FSL_ERRATUM_A050106
>> >select SYS_FSL_HAS_RGMII
>> >select SYS_FSL_HAS_SEC
>> >select SYS_FSL_HAS_CCN508
>> >@@ -348,6 +349,9 @@ config SYS_FSL_ERRATUM_A009008  config
>> >SYS_FSL_ERRATUM_A009798
>> >bool "Workaround for USB PHY erratum A009798"
>> >
>> >+config SYS_FSL_ERRATUM_A050106
>> >+   bool "Workaround for USB PHY erratum A050106"
>> >+
>> Please fix checkpatch warning
>> WARNING: please write a paragraph that describes the config symbol
>> fully
>> #35: FILE: arch/arm/cpu/armv8/fsl-layerscape/Kconfig:352:
>> +config SYS_FSL_ERRATUM_A050106
>>
>> total: 0 errors, 1 warnings, 0 checks, 60 lines checked
>
>Actually I followed the history erratum workaround patches to do this.
>And it seems to be OK to ignore that warning,
>
>Please check:
>http://patchwork.ozlabs.org/patch/809597/
>http://patchwork.ozlabs.org/patch/809598/
>http://patchwork.ozlabs.org/patch/809603/
>http://patchwork.ozlabs.org/patch/809599/
>http://patchwork.ozlabs.org/patch/809604/
>http://patchwork.ozlabs.org/patch/809600/
>http://patchwork.ozlabs.org/patch/809601/
>http://patchwork.ozlabs.org/patch/809602/
>http://patchwork.ozlabs.org/patch/817358/
>http://patchwork.ozlabs.org/patch/1098612/
>
>Thanks & Regards,
>Ran
Even though in past , this warning might not have exist or we have ignore this,
But such details help in better code readability.
-priyankajain
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[U-Boot] [PATCH v5 000/101] x86: Add initial support for apollolake

2019-11-24 Thread Simon Glass
Apollo Lake is an Intel SoC generation aimed at relatively low-end
embedded systems. It was released in 2016 but has become more popular
recently with some embedded boards using it.

This series adds support for Apollo Lake. As an example it adds an
implementation of chromebook_coral (a large range of Chromebooks released
in 2017).

The series provides enough support to boot to a prompt. with LCD display,
storage, USB, EC and keyboard.

Since this is the first time U-Boot has used FSP2 there is quite a bit of
refactoring needed.

This series is available at u-boot-dm/coral-working

Changes in v5:
- Add ACPI base address and size
- Add L2 cache flush function
- Add L2 cache flush functoin
- Add a new patch to move qemu CPU fixup function into its own file
- Add a way to obtain the port ID for a device
- Add function to obtain ACPI gpio number
- Add gpio-controller to GPIO nodes
- Allocate the FSP-S data instead of using the stack
- Change SPL as well
- Comment out GPIOs in the fsp_s node since we don't use them yet
- Correct CPU ACPI IDs
- Correct build error in chromebook_samus_tpl
- Drop SAFETY_MARGIN
- Enable SMP
- Fix FST typo
- Fix build errors on some PowerPC boards
- Group U-Boot and device tree into a section
- Rename APOLLOLAKE_USB2_PORT_MAX
- Use a define for ACPI base address

Changes in v4:
- Add a LOG_CATEGORY for silicon init
- Add a binding file
- Add a comment about the speed logic in __dw_i2c_set_bus_speed()
- Add a comment for enable_bios_reset_cpl()
- Add a comment in the commit message about why has_max_speed is added
- Add a patch to explain of-platdata and header files
- Add an extra comment to apl_uart_init()
- Add comments about MRC-cache records being the same size
- Add comments for exported functions
- Add comments to functions
- Add more documentation for pci_ofplat_get_devfn()
- Add new patch to allow designware I2C driver to work in SPL
- Add new patch to drop static data in designware i2c driver
- Add new patch to make mrccache_update() static
- Add new patch to move early-timer init later
- Add support for updating power state
- Add u-boot,skip-auto-config-until-reloc property to PCI
- Adjust
- Adjust condition for binding children
- Adjust the comment for struct dw_i2c_speed_config
- Allow pinctrl nodes to have subnodes (i.e. GPIO nodes)
- Avoid needing to know internals of pinctrl in this driver
- Change apollolake to apl
- Change the behaviour to be a device-tree option
- Detect zero mmio address
- Disable SPL_DM_GPIO on omap35_logic to avoid a build error
- Drop 'if (0)' call to deep_magic_nexgen_probe() and use #ifndef instead
- Drop GPIO_NUM_PAD_CFG_REGS
- Drop TCO_BASE_ADDRESS
- Drop change to message about a missing uclass
- Drop duplicate VBT file CONFIG
- Drop duplicate commit 'Create a new sandbox_pci_read_bar() function'
- Drop empty operations struct since p2sb does not need it
- Drop incorrect coreboot reference from header file
- Drop itss uclass change in Makefile (now in previous patch)
- Drop itss uclass in Makefile
- Drop pmic_pm8916 driver name and use a sandbox name instead
- Drop sandbox defconfig change now that p2sb change is correct
- Drop the whole interrupt file for TPL
- Drop unrelated change metioned by Heiko
- Drop unwanted debug printf("bad\n")
- Enable HAVE_VBT for FSP2 also
- Enable HAVE_X86_FIT
- Enable INTEL_GPIO
- Enable IRQ for sandbox64 too to avoid build error
- Enable option for slimbootloader, coreboot, efi
- Expand commit message to better explain the need to checksum functions
- Explain the 'twisty headers' comment
- Explain why FSP-M cannot be shown
- Fix 'enabled' typo
- Fix 'what' typo
- Fix FSP_M reference to refer to FSP_S in commit message
- Fix Makefile copyright message
- Fix alpha order in Kconfig
- Fix comment for exec_sync_hwseq_xfer()
- Fix comment on fsp_silicon_init()
- Fix incorrect mask check in pmc_gpe_init()
- Fix indentation nit
- Fix up license header
- Fix various code-style problems
- Mention that the return value is pci_dev_t
- Move code to pinctrl driver
- Move this to intel_common
- Name this P-Unit instead of power unit, in the commit message
- New GPIO driver binding
- One last desperate attempt to try to explain the purpose of this commit
- Rename arch_fsp_s_preinit() to arch_fsps_preinit()
- Rename get_coreboot_fsp() and add comments
- Rename new file to designware_i2c_pci.c
- Rename option to HAVE_SYS_TEXT_BASE
- Rename pci_x86_ofplat_get_devfn() to pci_ofplat_get_devfn()
- Reverse the sense of the CONFIG option
- Set up LPC pads early
- Split out GPIO code from the pinctrl driver
- Split out into a separate patch
- Split out mmio changes into a separate patch
- Switch over to use pinctrl for pad init/config
- Tidy up header guards
- Tidy up mixed case in FSP code
- Tidy up the header file a little
- Update SPI flash protection only in SPL
- Update commit message to indicate that CPU-identity bug is fixed
- Update documentation with more detailed memory map
- Update the commit message to be clearer, fix 

[U-Boot] [PATCH v5 001/101] binman: Add a library to access binman entries

2019-11-24 Thread Simon Glass
SPL and TPL can access information about binman entries using link-time
symbols but this is not available in U-Boot proper. Of course it could be
made available, but the intention is to just read the device tree.

Add support for this, so that U-Boot can locate entries.

Signed-off-by: Simon Glass 
---

Changes in v5:
- Fix build errors on some PowerPC boards

Changes in v4:
- Add comments to functions

Changes in v3: None
Changes in v2: None

 common/board_r.c | 10 ++
 include/binman.h | 45 +
 lib/Kconfig  | 10 ++
 lib/Makefile |  1 +
 lib/binman.c | 48 
 5 files changed, 114 insertions(+)
 create mode 100644 include/binman.h
 create mode 100644 lib/binman.c

diff --git a/common/board_r.c b/common/board_r.c
index 65720849cd..e385696a6d 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -15,6 +15,7 @@
 #if defined(CONFIG_CMD_BEDBUG)
 #include 
 #endif
+#include 
 #include 
 #include 
 #include 
@@ -342,6 +343,14 @@ static int initr_manual_reloc_cmdtable(void)
 }
 #endif
 
+static int initr_binman(void)
+{
+   if (!CONFIG_IS_ENABLED(BINMAN_FDT))
+   return 0;
+
+   return binman_init();
+}
+
 #if defined(CONFIG_MTD_NOR_FLASH)
 static int initr_flash(void)
 {
@@ -692,6 +701,7 @@ static init_fnc_t init_sequence_r[] = {
 #ifdef CONFIG_EFI_LOADER
efi_memory_init,
 #endif
+   initr_binman,
stdio_init_tables,
initr_serial,
initr_announce,
diff --git a/include/binman.h b/include/binman.h
new file mode 100644
index 00..b462dc8542
--- /dev/null
+++ b/include/binman.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: Intel */
+/*
+ * Access to binman information at runtime
+ *
+ * Copyright 2019 Google LLC
+ * Written by Simon Glass 
+ */
+
+#ifndef _BINMAN_H_
+#define _BINMAN_H_
+
+/**
+ *struct binman_entry - information about a binman entry
+ *
+ * @image_pos: Position of entry in the image
+ * @size: Size of entry
+ */
+struct binman_entry {
+   u32 image_pos;
+   u32 size;
+};
+
+/**
+ * binman_entry_find() - Find a binman symbol
+ *
+ * This searches the binman information in the device tree for a symbol of the
+ * given name
+ *
+ * @name: Path to entry to examine (e.g. "/read-only/u-boot")
+ * @entry: Returns information about the entry
+ * @return 0 if OK, -ENOENT if the path is not found, other -ve value if the
+ * binman information is invalid (missing image-pos or size)
+ */
+int binman_entry_find(const char *name, struct binman_entry *entry);
+
+/**
+ * binman_init() - Set up the binman symbol information
+ *
+ * This locates the binary symbol information in the device tree ready for use
+ *
+ * @return 0 if OK, -ENOMEM if out of memory, -EINVAL if there is no binman 
node
+ */
+int binman_init(void);
+
+#endif
diff --git a/lib/Kconfig b/lib/Kconfig
index b8a8509d72..7e87b7cff3 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -7,6 +7,16 @@ config BCH
  This is used by SoC platforms which do not have built-in ELM
  hardware engine required for BCH ECC correction.
 
+config BINMAN_FDT
+   bool "Allow access to binman information in the device tree"
+   depends on BINMAN && OF_CONTROL
+   default y
+   help
+ This enables U-Boot to access information about binman entries,
+ stored in the device tree in a binman node. Typical uses are to
+ locate entries in the firmware image. See binman.h for the available
+ functionality.
+
 config CC_OPTIMIZE_LIBS_FOR_SPEED
bool "Optimize libraries for speed"
help
diff --git a/lib/Makefile b/lib/Makefile
index d248d8626c..0c89b4896f 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_ARCH_AT91) += at91/
 obj-$(CONFIG_OPTEE) += optee/
 
 obj-$(CONFIG_AES) += aes.o
+obj-$(CONFIG_$(SPL_TPL_)BINMAN_FDT) += binman.o
 
 ifndef API_BUILD
 ifneq ($(CONFIG_UT_UNICODE)$(CONFIG_EFI_LOADER),)
diff --git a/lib/binman.c b/lib/binman.c
new file mode 100644
index 00..1774bdf2e5
--- /dev/null
+++ b/lib/binman.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: Intel
+/*
+ * Access to binman information at runtime
+ *
+ * Copyright 2019 Google LLC
+ * Written by Simon Glass 
+ */
+
+#include 
+#include 
+#include 
+
+struct binman_info {
+   ofnode image;
+};
+
+static struct binman_info *binman;
+
+int binman_entry_find(const char *name, struct binman_entry *entry)
+{
+   ofnode node;
+   int ret;
+
+   node = ofnode_find_subnode(binman->image, name);
+   if (!ofnode_valid(node))
+   return log_msg_ret("no binman node", -ENOENT);
+
+   ret = ofnode_read_u32(node, "image-pos", &entry->image_pos);
+   if (ret)
+   return log_msg_ret("bad binman node1", ret);
+   ret = ofnode_read_u32(node, "size", &entry->size);
+   if (ret)
+   return log_msg_ret("bad binman node2", ret);
+
+   return 0;
+}
+
+int binman_init(void)
+{

[U-Boot] [PATCH v5 003/101] dm: core: Fix offset_to_ofnode() with invalid offset

2019-11-24 Thread Simon Glass
If the offset is -1 this function correctly sets up a null ofnode. But if
the offset is any other negative number (e.g. -FDT_ERR_BADPATH) then it
does the wrong thing.

An offset of -1 in ofnode indicates that the ofnode is not valid. Any
other negative value is not handled by ofnode_valid(). We could of course
change that function, but it seems much better to always use the same
value for an invalid node.

Fix it by setting the offset to -1 if it is invalid for any reason.

Signed-off-by: Simon Glass 
---

Changes in v5: None
Changes in v4:
- Update the commit message to be clearer, fix 'correct' typo

Changes in v3: None
Changes in v2: None

 include/dm/ofnode.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h
index 5c4cbf0998..4282169706 100644
--- a/include/dm/ofnode.h
+++ b/include/dm/ofnode.h
@@ -118,7 +118,7 @@ static inline ofnode offset_to_ofnode(int of_offset)
if (of_live_active())
node.np = NULL;
else
-   node.of_offset = of_offset;
+   node.of_offset = of_offset >= 0 ? of_offset : -1;
 
return node;
 }
-- 
2.24.0.432.g9d3f5f5b63-goog

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[U-Boot] [PATCH v5 002/101] dm: gpio: Allow control of GPIO uclass in SPL

2019-11-24 Thread Simon Glass
At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass
is included in SPL/TPL without any control for boards. Some boards may
want to disable this to reduce code size where GPIOs are not needed in
SPL or TPL.

Add a new Kconfig option to permit this. Default it to 'y' so that
existing boards work correctly.

Change existing uses of CONFIG_DM_GPIO to CONFIG_IS_ENABLED(DM_GPIO) to
preserve the current behaviour. Also update the 74x164 GPIO driver since
it cannot build with SPL.

This allows us to remove the hacks in config_uncmd_spl.h and
Makefile.uncmd_spl (eventually those files should be removed).

Signed-off-by: Simon Glass 

---

Changes in v5: None
Changes in v4:
- Disable SPL_DM_GPIO on omap35_logic to avoid a build error

Changes in v3: None
Changes in v2:
- Fix the Kconfig condition to avoid build errors on snow

 arch/arm/include/asm/omap_gpio.h  |  2 +-
 arch/arm/mach-at91/include/mach/at91sam9260.h |  2 +-
 arch/arm/mach-davinci/include/mach/gpio.h |  2 +-
 arch/arm/mach-omap2/am33xx/board.c|  4 ++--
 arch/arm/mach-omap2/omap3/board.c |  2 +-
 arch/arm/mach-omap2/omap5/hwinit.c|  2 +-
 board/freescale/imx8qm_mek/imx8qm_mek.c   |  2 +-
 board/freescale/imx8qxp_mek/imx8qxp_mek.c |  2 +-
 board/gateworks/gw_ventana/Kconfig|  3 +++
 board/toradex/apalis-imx8/apalis-imx8.c   |  2 +-
 configs/omap35_logic_defconfig|  1 +
 drivers/gpio/Kconfig  | 22 +++
 drivers/gpio/Makefile |  4 +++-
 drivers/gpio/at91_gpio.c  |  6 ++---
 drivers/gpio/atmel_pio4.c |  2 +-
 drivers/gpio/da8xx_gpio.c |  7 +++---
 drivers/gpio/da8xx_gpio.h |  2 +-
 drivers/gpio/mxc_gpio.c   |  4 ++--
 drivers/gpio/mxs_gpio.c   |  4 ++--
 drivers/gpio/omap_gpio.c  |  6 ++---
 drivers/gpio/sunxi_gpio.c |  8 +++
 drivers/i2c/i2c-uclass.c  |  6 ++---
 drivers/i2c/muxes/pca954x.c   |  4 ++--
 drivers/mmc/fsl_esdhc_imx.c   | 13 ++-
 drivers/mmc/omap_hsmmc.c  |  2 +-
 drivers/net/designware.c  | 10 -
 drivers/net/designware.h  |  4 ++--
 drivers/net/fec_mxc.c |  6 ++---
 drivers/net/fec_mxc.h |  2 +-
 drivers/net/mvneta.c  |  4 ++--
 drivers/net/mvpp2.c   |  8 +++
 drivers/net/sun8i_emac.c  | 12 +-
 drivers/pci/pci-aardvark.c|  4 ++--
 drivers/pci/pcie_dw_mvebu.c   |  4 ++--
 drivers/spi/atmel_spi.c   | 10 -
 drivers/spi/designware_spi.c  |  4 ++--
 drivers/tpm/tpm2_tis_spi.c|  2 +-
 include/config_uncmd_spl.h|  1 -
 include/configs/at91-sama5_common.h   |  5 +++--
 include/configs/gw_ventana.h  |  1 -
 include/configs/mx6ul_14x14_evk.h |  1 +
 scripts/Makefile.uncmd_spl|  1 -
 42 files changed, 111 insertions(+), 82 deletions(-)

diff --git a/arch/arm/include/asm/omap_gpio.h b/arch/arm/include/asm/omap_gpio.h
index 20268fa084..151afa8f44 100644
--- a/arch/arm/include/asm/omap_gpio.h
+++ b/arch/arm/include/asm/omap_gpio.h
@@ -22,7 +22,7 @@
 
 #include 
 
-#ifdef CONFIG_DM_GPIO
+#if CONFIG_IS_ENABLED(DM_GPIO)
 
 /* Information about a GPIO bank */
 struct omap_gpio_platdata {
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h 
b/arch/arm/mach-at91/include/mach/at91sam9260.h
index 91faf729ae..2daeb4fef8 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260.h
@@ -133,7 +133,7 @@
 /*
  * Other misc defines
  */
-#ifndef CONFIG_DM_GPIO
+#if !CONFIG_IS_ENABLED(DM_GPIO)
 #define ATMEL_PIO_PORTS3   /* these SoCs have 3 
PIO */
 #define ATMEL_BASE_PIO ATMEL_BASE_PIOA
 #endif
diff --git a/arch/arm/mach-davinci/include/mach/gpio.h 
b/arch/arm/mach-davinci/include/mach/gpio.h
index c150240962..e5a4053414 100644
--- a/arch/arm/mach-davinci/include/mach/gpio.h
+++ b/arch/arm/mach-davinci/include/mach/gpio.h
@@ -18,7 +18,7 @@
 #define davinci_gpio_bank67 ((struct davinci_gpio *)DAVINCI_GPIO_BANK67)
 #define davinci_gpio_bank8 ((struct davinci_gpio *)DAVINCI_GPIO_BANK8)
 
-#ifndef CONFIG_DM_GPIO
+#if !CONFIG_IS_ENABLED(DM_GPIO)
 #define gpio_status()  gpio_info()
 #endif
 #define GPIO_NAME_SIZE 20
diff --git a/arch/arm/mach-omap2/am33xx/board.c 
b/arch/arm/mach-omap2/am33xx/board.c
index 03460c3eb7..e64942b716 100644
--- a/arch/arm/mach-omap2/am33xx/board.c
+++ b/arch/arm/mach-omap2/am33xx/board.c
@@ -116,7 +116,7 @@ U_BOOT_DEVICES(am33xx_i2c) = {
 };
 #endif
 
-#ifdef CONFIG_DM_GPIO
+#if CONFIG

[U-Boot] [PATCH v5 005/101] dm: pci: Move pci_get_devfn() into a common file

2019-11-24 Thread Simon Glass
Early in boot it is necessary to decode the PCI device/function values for
particular peripherals in the device tree or of-platdata. This is needed
in TPL where CONFIG_PCI is not defined.

To handle this, move pci_get_devfn() into a file that is built even when
CONFIG_PCI is not defined.

Also add a function for use by of-platdata, to convert a reg property to
a pci_dev_t.

Signed-off-by: Simon Glass 
---

Changes in v5: None
Changes in v4:
- Add more documentation for pci_ofplat_get_devfn()
- Mention that the return value is pci_dev_t
- Rename pci_x86_ofplat_get_devfn() to pci_ofplat_get_devfn()

Changes in v3:
- Move the function to a common file instead of duplicating it
- Update device type to pci_dev_t

Changes in v2: None

 drivers/core/util.c  | 20 +++
 drivers/pci/pci-uclass.c | 16 ---
 include/dm/pci.h | 43 
 include/pci.h| 12 ++-
 4 files changed, 65 insertions(+), 26 deletions(-)
 create mode 100644 include/dm/pci.h

diff --git a/drivers/core/util.c b/drivers/core/util.c
index 7dc1a2af02..69f83755f0 100644
--- a/drivers/core/util.c
+++ b/drivers/core/util.c
@@ -4,7 +4,9 @@
  */
 
 #include 
+#include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -58,3 +60,21 @@ bool dm_ofnode_pre_reloc(ofnode node)
 #endif
 }
 #endif
+
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+int pci_get_devfn(struct udevice *dev)
+{
+   struct fdt_pci_addr addr;
+   int ret;
+
+   /* Extract the devfn from fdt_pci_addr */
+   ret = ofnode_read_pci_addr(dev_ofnode(dev), FDT_PCI_SPACE_CONFIG,
+  "reg", &addr);
+   if (ret) {
+   if (ret != -ENOENT)
+   return -EINVAL;
+   }
+
+   return addr.phys_hi & 0xff00;
+}
+#endif
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index b09fb4f993..3863262ebe 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -1018,22 +1018,6 @@ static int pci_uclass_post_probe(struct udevice *bus)
return 0;
 }
 
-int pci_get_devfn(struct udevice *dev)
-{
-   struct fdt_pci_addr addr;
-   int ret;
-
-   /* Extract the devfn from fdt_pci_addr */
-   ret = ofnode_read_pci_addr(dev_ofnode(dev), FDT_PCI_SPACE_CONFIG,
-  "reg", &addr);
-   if (ret) {
-   if (ret != -ENOENT)
-   return -EINVAL;
-   }
-
-   return addr.phys_hi & 0xff00;
-}
-
 static int pci_uclass_child_post_bind(struct udevice *dev)
 {
struct pci_child_platdata *pplat;
diff --git a/include/dm/pci.h b/include/dm/pci.h
new file mode 100644
index 00..4faf09f05f
--- /dev/null
+++ b/include/dm/pci.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2019 Google, Inc
+ */
+
+#ifndef __DM_PCI_H
+#define __DM_PCI_H
+
+struct udevice;
+
+/**
+ * pci_get_devfn() - Extract the devfn from fdt_pci_addr of the device
+ *
+ * Get devfn from fdt_pci_addr of the specified device
+ *
+ * This returns an int to avoid a dependency on pci.h
+ *
+ * @dev:   PCI device
+ * @return devfn in bits 15...8 if found (pci_dev_t format), or -ENODEV if not
+ * found
+ */
+int pci_get_devfn(struct udevice *dev);
+
+/**
+ * pci_x86_ofplat_get_devfn() - Get the PCI dev/fn from of-platdata
+ *
+ * This function is used to obtain a PCI device/function from of-platdata
+ * register data. In this case the first cell of the 'reg' property contains
+ * the required information.
+ *
+ * This returns an int to avoid a dependency on pci.h
+ *
+ * @reg: reg value from dt-platdata.c array (first member). This is not a
+ * pointer type, since the caller may use fdt32_t or fdt64_t depending on
+ * the address sizes.
+ * @return device/function for that device (pci_dev_t format)
+ */
+static inline int pci_ofplat_get_devfn(u32 reg)
+{
+   return reg & 0xff00;
+}
+
+#endif
diff --git a/include/pci.h b/include/pci.h
index de17d0ffba..8c761d8da3 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -482,6 +482,8 @@
 
 #ifndef __ASSEMBLY__
 
+#include 
+
 #ifdef CONFIG_SYS_PCI_64BIT
 typedef u64 pci_addr_t;
 typedef u64 pci_size_t;
@@ -1619,16 +1621,6 @@ int sandbox_pci_get_emul(struct udevice *bus, pci_dev_t 
find_devfn,
  */
 int sandbox_pci_get_client(struct udevice *emul, struct udevice **devp);
 
-/**
- * pci_get_devfn() - Extract the devfn from fdt_pci_addr of the device
- *
- * Get devfn from fdt_pci_addr of the specified device
- *
- * @dev:   PCI device
- * @return devfn in bits 15...8 if found, -ENODEV if not found
- */
-int pci_get_devfn(struct udevice *dev);
-
 #endif /* CONFIG_DM_PCI */
 
 /**
-- 
2.24.0.432.g9d3f5f5b63-goog

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[U-Boot] [PATCH v5 010/101] x86: spi: Add helper functions for Intel Fast SPI

2019-11-24 Thread Simon Glass
Most x86 CPUs use a mechanism where the SPI flash is mapped into the very
top of 32-bit address space, so that it can be executed in place and read
simply by copying from memory. For an 8MB ROM the mapping starts at
0xff80.

However some recent Intel CPUs do not use a simple 1:1 memory map. Instead
the map starts at a different address and not all of the SPI flash is
accessible through the map. This 'Fast SPI' feature requires that U-Boot
check the location of the map. It is also possible (optionally) to read
from the SPI flash using a driver.

Add support for booting from Fast SPI. The memory-mapped version is used
by both TPL and SPL on Apollo Lake.

In respect of a SPI flash driver, the actual SPI driver is ich.c - this
just adds a few helper functions and definitions.

This is used by Apollo Lake.

Signed-off-by: Simon Glass 
---

Changes in v5: None
Changes in v4: None
Changes in v3:
- Add support for of-platdata for TPL
- Add the missing header file
- Change Fast-SPI driver into a helper file used by ICH SPI
- Don't include write() and erase() in TPL
- Drop 'a4' comment for register offset
- Merge in patch "x86: Add support for booting from Fast SPI"
- Reorder file so that write() and erase() are together
- Use pci_get_devfn()

Changes in v2: None

 arch/x86/cpu/intel_common/Makefile   |  1 +
 arch/x86/cpu/intel_common/fast_spi.c | 73 
 arch/x86/include/asm/fast_spi.h  | 68 ++
 arch/x86/include/asm/spl.h   |  1 +
 4 files changed, 143 insertions(+)
 create mode 100644 arch/x86/cpu/intel_common/fast_spi.c
 create mode 100644 arch/x86/include/asm/fast_spi.h

diff --git a/arch/x86/cpu/intel_common/Makefile 
b/arch/x86/cpu/intel_common/Makefile
index 07f27c29ec..dfbc29f047 100644
--- a/arch/x86/cpu/intel_common/Makefile
+++ b/arch/x86/cpu/intel_common/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += report_platform.o
 obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += mrc.o
 endif
 obj-y += cpu.o
+obj-y += fast_spi.o
 obj-y += lpc.o
 ifndef CONFIG_TARGET_EFI_APP
 obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += microcode.o
diff --git a/arch/x86/cpu/intel_common/fast_spi.c 
b/arch/x86/cpu/intel_common/fast_spi.c
new file mode 100644
index 00..a6e3d0a5bf
--- /dev/null
+++ b/arch/x86/cpu/intel_common/fast_spi.c
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/*
+ * Returns bios_start and fills in size of the BIOS region.
+ */
+static ulong fast_spi_get_bios_region(struct fast_spi_regs *regs,
+ uint *bios_size)
+{
+   ulong bios_start, bios_end;
+
+   /*
+* BIOS_BFPREG provides info about BIOS-Flash Primary Region Base and
+* Limit. Base and Limit fields are in units of 4K.
+*/
+   u32 val = readl(®s->bfp);
+
+   bios_start = (val & SPIBAR_BFPREG_PRB_MASK) << 12;
+   bios_end = (((val & SPIBAR_BFPREG_PRL_MASK) >>
+SPIBAR_BFPREG_PRL_SHIFT) + 1) << 12;
+   *bios_size = bios_end - bios_start;
+
+   return bios_start;
+}
+
+int fast_spi_get_bios_mmap(pci_dev_t pdev, ulong *map_basep, uint *map_sizep,
+  uint *offsetp)
+{
+   struct fast_spi_regs *regs;
+   ulong bar, base, mmio_base;
+
+   /* Special case to find mapping without probing the device */
+   pci_x86_read_config(pdev, PCI_BASE_ADDRESS_0, &bar, PCI_SIZE_32);
+   mmio_base = bar & PCI_BASE_ADDRESS_MEM_MASK;
+   regs = (struct fast_spi_regs *)mmio_base;
+   base = fast_spi_get_bios_region(regs, map_sizep);
+   *map_basep = (u32)-*map_sizep - base;
+   *offsetp = base;
+
+   return 0;
+}
+
+int fast_spi_early_init(pci_dev_t pdev, ulong mmio_base)
+{
+   /* Program Temporary BAR for SPI */
+   pci_x86_write_config(pdev, PCI_BASE_ADDRESS_0,
+mmio_base | PCI_BASE_ADDRESS_SPACE_MEMORY,
+PCI_SIZE_32);
+
+   /* Enable Bus Master and MMIO Space */
+   pci_x86_clrset_config(pdev, PCI_COMMAND, 0, PCI_COMMAND_MASTER |
+ PCI_COMMAND_MEMORY, PCI_SIZE_8);
+
+   /*
+* Disable the BIOS write protect so write commands are allowed.
+* Enable Prefetching and caching.
+*/
+   pci_x86_clrset_config(pdev, SPIBAR_BIOS_CONTROL,
+ SPIBAR_BIOS_CONTROL_EISS |
+ SPIBAR_BIOS_CONTROL_CACHE_DISABLE,
+ SPIBAR_BIOS_CONTROL_WPD |
+ SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE, PCI_SIZE_8);
+
+   return 0;
+}
diff --git a/arch/x86/include/asm/fast_spi.h b/arch/x86/include/asm/fast_spi.h
new file mode 100644
index 00..6894298526
--- /dev/null
+++ b/arch/x86/include/asm/fast_spi.h
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2017 Intel Corporation.
+ */
+
+#ifnd

[U-Boot] [PATCH v5 009/101] i2c: designware: Support use in SPL

2019-11-24 Thread Simon Glass
Allow this driver to set up an IO address in SPL using an 'early-regs'
property. This allows SPL to use the I2C driver without having to enable
the full PCI stack.

Also split out ofdata_to_platdata in designware driver since this is more
correct, and more convenient for the new logic.

Signed-off-by: Simon Glass 
---

Changes in v5: None
Changes in v4:
- Add new patch to allow designware I2C driver to work in SPL

Changes in v3: None
Changes in v2: None

 drivers/i2c/designware_i2c_pci.c | 46 +---
 1 file changed, 43 insertions(+), 3 deletions(-)

diff --git a/drivers/i2c/designware_i2c_pci.c b/drivers/i2c/designware_i2c_pci.c
index 8d6bb37f5c..2bf90eaa4b 100644
--- a/drivers/i2c/designware_i2c_pci.c
+++ b/drivers/i2c/designware_i2c_pci.c
@@ -7,6 +7,7 @@
 
 #include 
 #include 
+#include 
 #include "designware_i2c.h"
 
 /* BayTrail HCNT/LCNT/SDA hold time */
@@ -18,17 +19,49 @@ static struct dw_scl_sda_cfg byt_config = {
.sda_hold = 0x6,
 };
 
-static int designware_i2c_pci_probe(struct udevice *dev)
+/* Have a weak function for now - possibly should be a new uclass */
+__weak void lpss_reset_release(void *regs);
+
+static int designware_i2c_pci_ofdata_to_platdata(struct udevice *dev)
 {
struct dw_i2c *priv = dev_get_priv(dev);
 
+   if (spl_phase() < PHASE_SPL) {
+   u32 base;
+   int ret;
+
+   ret = dev_read_u32(dev, "early-regs", &base);
+   if (ret)
+   return log_msg_ret("early-regs", ret);
+
+   /* Set i2c base address */
+   dm_pci_write_config32(dev, PCI_BASE_ADDRESS_0, base);
+
+   /* Enable memory access and bus master */
+   dm_pci_write_config32(dev, PCI_COMMAND, PCI_COMMAND_MEMORY |
+ PCI_COMMAND_MASTER);
+   }
+
+   if (spl_phase() < PHASE_BOARD_F) {
+   /* Handle early, fixed mapping into a different address space */
+   priv->regs = (struct i2c_regs *)dm_pci_read_bar32(dev, 0);
+   } else {
+   priv->regs = (struct i2c_regs *)
+   dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
+   }
+   if (!priv->regs)
+   return -EINVAL;
+
/* Save base address from PCI BAR */
-   priv->regs = (struct i2c_regs *)
-   dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
if (IS_ENABLED(CONFIG_INTEL_BAYTRAIL))
/* Use BayTrail specific timing values */
priv->scl_sda_cfg = &byt_config;
 
+   return 0;
+}
+
+static int designware_i2c_pci_probe(struct udevice *dev)
+{
return designware_i2c_probe(dev);
 }
 
@@ -56,10 +89,17 @@ static int designware_i2c_pci_bind(struct udevice *dev)
return 0;
 }
 
+static const struct udevice_id designware_i2c_pci_ids[] = {
+   { .compatible = "snps,designware-i2c-pci" },
+   { }
+};
+
 U_BOOT_DRIVER(i2c_designware_pci) = {
.name   = "i2c_designware_pci",
.id = UCLASS_I2C,
+   .of_match = designware_i2c_pci_ids,
.bind   = designware_i2c_pci_bind,
+   .ofdata_to_platdata = designware_i2c_pci_ofdata_to_platdata,
.probe  = designware_i2c_pci_probe,
.priv_auto_alloc_size = sizeof(struct dw_i2c),
.remove = designware_i2c_remove,
-- 
2.24.0.432.g9d3f5f5b63-goog

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[U-Boot] [PATCH v5 007/101] i2c: designware: Tidy up PCI support

2019-11-24 Thread Simon Glass
This is hacked into the driver at present. It seems better to have it as
a separate driver that uses the base driver. Create a new file and put
the X86 code into it.

Actually the Baytrail settings should really come from the device tree.

Note that 'has_max_speed' is added as well. This is currently always false
but since only Baytrail provides the config, it does not affect operation
for other devices.

Signed-off-by: Simon Glass 
Reviewed-by: Heiko Schocher 
---

Changes in v5: None
Changes in v4:
- Add a comment about the speed logic in __dw_i2c_set_bus_speed()
- Add a comment in the commit message about why has_max_speed is added
- Drop unwanted debug printf("bad\n")
- Fix indentation nit
- Rename new file to designware_i2c_pci.c

Changes in v3: None
Changes in v2: None

 drivers/i2c/Makefile |   3 +
 drivers/i2c/designware_i2c.c | 106 +--
 drivers/i2c/designware_i2c.h |  35 ++
 drivers/i2c/designware_i2c_pci.c |  79 +++
 4 files changed, 134 insertions(+), 89 deletions(-)
 create mode 100644 drivers/i2c/designware_i2c_pci.c

diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index c2f75d8755..f5a471f887 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -14,6 +14,9 @@ obj-$(CONFIG_SYS_I2C_AT91) += at91_i2c.o
 obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o
 obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
 obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o
+ifdef CONFIG_DM_PCI
+obj-$(CONFIG_SYS_I2C_DW) += designware_i2c_pci.o
+endif
 obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
 obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o
 obj-$(CONFIG_SYS_I2C_INTEL) += intel_i2c.o
diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c
index 6daa90e744..99b7d09bb2 100644
--- a/drivers/i2c/designware_i2c.c
+++ b/drivers/i2c/designware_i2c.c
@@ -13,34 +13,6 @@
 #include 
 #include "designware_i2c.h"
 
-struct dw_scl_sda_cfg {
-   u32 ss_hcnt;
-   u32 fs_hcnt;
-   u32 ss_lcnt;
-   u32 fs_lcnt;
-   u32 sda_hold;
-};
-
-#ifdef CONFIG_X86
-/* BayTrail HCNT/LCNT/SDA hold time */
-static struct dw_scl_sda_cfg byt_config = {
-   .ss_hcnt = 0x200,
-   .fs_hcnt = 0x55,
-   .ss_lcnt = 0x200,
-   .fs_lcnt = 0x99,
-   .sda_hold = 0x6,
-};
-#endif
-
-struct dw_i2c {
-   struct i2c_regs *regs;
-   struct dw_scl_sda_cfg *scl_sda_cfg;
-   struct reset_ctl_bulk resets;
-#if CONFIG_IS_ENABLED(CLK)
-   struct clk clk;
-#endif
-};
-
 #ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
 static int  dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
 {
@@ -90,7 +62,9 @@ static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs 
*i2c_base,
unsigned int ena;
int i2c_spd;
 
-   if (speed >= I2C_MAX_SPEED)
+   /* Allow max speed if there is no config , or the config allows it */
+   if (speed >= I2C_MAX_SPEED &&
+   (!scl_sda_cfg || scl_sda_cfg->has_max_speed))
i2c_spd = IC_SPEED_MODE_MAX;
else if (speed >= I2C_FAST_SPEED)
i2c_spd = IC_SPEED_MODE_FAST;
@@ -106,7 +80,6 @@ static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs 
*i2c_base,
cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
 
switch (i2c_spd) {
-#ifndef CONFIG_X86 /* No High-speed for BayTrail yet */
case IC_SPEED_MODE_MAX:
cntl |= IC_CON_SPD_SS;
if (scl_sda_cfg) {
@@ -119,7 +92,6 @@ static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs 
*i2c_base,
writel(hcnt, &i2c_base->ic_hs_scl_hcnt);
writel(lcnt, &i2c_base->ic_hs_scl_lcnt);
break;
-#endif
 
case IC_SPEED_MODE_STANDARD:
cntl |= IC_CON_SPD_SS;
@@ -565,24 +537,19 @@ static int designware_i2c_probe_chip(struct udevice *bus, 
uint chip_addr,
return ret;
 }
 
-static int designware_i2c_probe(struct udevice *bus)
+static int designware_i2c_ofdata_to_platdata(struct udevice *bus)
 {
struct dw_i2c *priv = dev_get_priv(bus);
-   int ret;
 
-   if (device_is_on_pci_bus(bus)) {
-#ifdef CONFIG_DM_PCI
-   /* Save base address from PCI BAR */
-   priv->regs = (struct i2c_regs *)
-   dm_pci_map_bar(bus, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
-#ifdef CONFIG_X86
-   /* Use BayTrail specific timing values */
-   priv->scl_sda_cfg = &byt_config;
-#endif
-#endif
-   } else {
-   priv->regs = (struct i2c_regs *)devfdt_get_addr_ptr(bus);
-   }
+   priv->regs = (struct i2c_regs *)devfdt_get_addr_ptr(bus);
+
+   return 0;
+}
+
+int designware_i2c_probe(struct udevice *bus)
+{
+   struct dw_i2c *priv = dev_get_priv(bus);
+   int ret;
 
ret = reset_get_bulk(bus, &priv->resets);
if (ret)
@@ -606,7 +573,7 @@ static int designware_i2c_probe(struct udevice *bus)
return __dw_i2c_init(priv->regs, 0, 0);
 }
 
-static int designware_i2c_remove(struct udev

[U-Boot] [PATCH v5 004/101] dm: pci: Allow delaying auto-config until after relocation

2019-11-24 Thread Simon Glass
At present PCI auto-configuration happens in U-Boot both before and after
relocation. This is a waste of time and may mess up static addresses used
in board_init_f(). Adjust the code to supporting doing auto-configuration
once, after relocation, under control of a device-tree property.

This is needed for Apollo Lake for debugging the silicon-init code. Once
the UART is moved to a different MMIO address the debug UART does not work
and any debug output in Apollo Lake's arch_fsp_init_r() causes a hang.

Signed-off-by: Simon Glass 
---

Changes in v5: None
Changes in v4:
- Change the behaviour to be a device-tree option
- apollolake -> Apollo Lake

Changes in v3: None
Changes in v2: None

 doc/device-tree-bindings/pci/x86-pci.txt | 24 
 drivers/pci/pci-uclass.c | 15 ++-
 include/pci.h|  9 -
 3 files changed, 42 insertions(+), 6 deletions(-)
 create mode 100644 doc/device-tree-bindings/pci/x86-pci.txt

diff --git a/doc/device-tree-bindings/pci/x86-pci.txt 
b/doc/device-tree-bindings/pci/x86-pci.txt
new file mode 100644
index 00..3aa5bd9a46
--- /dev/null
+++ b/doc/device-tree-bindings/pci/x86-pci.txt
@@ -0,0 +1,24 @@
+x86 PCI DT details:
+===
+
+Some options are available to affect how PCI operates on x86.
+
+Optional properties:
+- u-boot,skip-auto-config-until-reloc : Don't set up PCI configuration until
+   after U-Boot has relocated. Normally if PCI is used before relocation,
+   this happens before relocation also. Some platforms set up static
+   configuration in TPL/SPL to reduce code size and boot time, since these
+   phases only know about a small subset of PCI devices.
+
+Example:
+
+pci {
+   compatible = "pci-x86";
+   #address-cells = <3>;
+   #size-cells = <2>;
+   u-boot,dm-pre-reloc;
+   ranges = <0x0200 0x0 0xc000 0xc000 0 0x1000
+   0x4200 0x0 0xb000 0xb000 0 0x1000
+   0x0100 0x0 0x1000 0x1000 0 0xefff>;
+   u-boot,skip-auto-config-until-reloc;
+};
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 896cb6b23a..b09fb4f993 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -970,12 +970,15 @@ static int pci_uclass_pre_probe(struct udevice *bus)
hose->bus = bus;
hose->first_busno = bus->seq;
hose->last_busno = bus->seq;
+   hose->skip_auto_config_until_reloc =
+   dev_read_bool(bus, "u-boot,skip-auto-config-until-reloc");
 
return 0;
 }
 
 static int pci_uclass_post_probe(struct udevice *bus)
 {
+   struct pci_controller *hose = dev_get_uclass_priv(bus);
int ret;
 
debug("%s: probing bus %d\n", __func__, bus->seq);
@@ -983,11 +986,13 @@ static int pci_uclass_post_probe(struct udevice *bus)
if (ret)
return ret;
 
-#if CONFIG_IS_ENABLED(PCI_PNP)
-   ret = pci_auto_config_devices(bus);
-   if (ret < 0)
-   return ret;
-#endif
+   if (CONFIG_IS_ENABLED(PCI_PNP) &&
+   (!hose->skip_auto_config_until_reloc ||
+(gd->flags & GD_FLG_RELOC))) {
+   ret = pci_auto_config_devices(bus);
+   if (ret < 0)
+   return log_msg_ret("pci auto-config", ret);
+   }
 
 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
/*
diff --git a/include/pci.h b/include/pci.h
index ff59ac0e69..de17d0ffba 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -571,15 +571,22 @@ extern void pci_cfgfunc_config_device(struct 
pci_controller* hose, pci_dev_t dev
 
 #define INDIRECT_TYPE_NO_PCIE_LINK 1
 
-/*
+/**
  * Structure of a PCI controller (host bridge)
  *
  * With driver model this is dev_get_uclass_priv(bus)
+ *
+ * @skip_auto_config_until_reloc: true to avoid auto-config until U-Boot has
+ * relocated. Normally if PCI is used before relocation, this happens
+ * before relocation also. Some platforms set up static configuration in
+ * TPL/SPL to reduce code size and boot time, since these phases only know
+ * about a small subset of PCI devices. This is normally false.
  */
 struct pci_controller {
 #ifdef CONFIG_DM_PCI
struct udevice *bus;
struct udevice *ctlr;
+   bool skip_auto_config_until_reloc;
 #else
struct pci_controller *next;
 #endif
-- 
2.24.0.432.g9d3f5f5b63-goog

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[U-Boot] [PATCH v5 006/101] net: Move the checksum functions to lib/

2019-11-24 Thread Simon Glass
These functions are used by code outside the network support, so move them
to lib/ to be more accessible.

Without this, the functions are only accessible if CONFIG_NET is defined.
Many boards do not enable that option but still want to do checksums in
this format.

Fix up a few code-style nits while we are here.

Signed-off-by: Simon Glass 
---

Changes in v5: None
Changes in v4:
- Expand commit message to better explain the need to checksum functions

Changes in v3: None
Changes in v2: None

 lib/Makefile|  2 +-
 lib/net_utils.c | 48 
 net/Makefile|  1 -
 net/checksum.c  | 59 -
 4 files changed, 49 insertions(+), 61 deletions(-)
 delete mode 100644 net/checksum.c

diff --git a/lib/Makefile b/lib/Makefile
index 0c89b4896f..505527d58a 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -76,7 +76,7 @@ endif
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_SPL_YMODEM_SUPPORT) += crc16.o
 obj-$(CONFIG_$(SPL_TPL_)HASH_SUPPORT) += crc16.o
-obj-$(CONFIG_SPL_NET_SUPPORT) += net_utils.o
+obj-y += net_utils.o
 endif
 obj-$(CONFIG_ADDR_MAP) += addr_map.o
 obj-y += qsort.o
diff --git a/lib/net_utils.c b/lib/net_utils.c
index 9fb9d4a4b0..252290210f 100644
--- a/lib/net_utils.c
+++ b/lib/net_utils.c
@@ -41,3 +41,51 @@ struct in_addr string_to_ip(const char *s)
addr.s_addr = htonl(addr.s_addr);
return addr;
 }
+
+uint compute_ip_checksum(const void *vptr, uint nbytes)
+{
+   int sum, oddbyte;
+   const unsigned short *ptr = vptr;
+
+   sum = 0;
+   while (nbytes > 1) {
+   sum += *ptr++;
+   nbytes -= 2;
+   }
+   if (nbytes == 1) {
+   oddbyte = 0;
+   ((u8 *)&oddbyte)[0] = *(u8 *)ptr;
+   ((u8 *)&oddbyte)[1] = 0;
+   sum += oddbyte;
+   }
+   sum = (sum >> 16) + (sum & 0x);
+   sum += (sum >> 16);
+   sum = ~sum & 0x;
+
+   return sum;
+}
+
+uint add_ip_checksums(uint offset, uint sum, uint new)
+{
+   ulong checksum;
+
+   sum = ~sum & 0x;
+   new = ~new & 0x;
+   if (offset & 1) {
+   /*
+* byte-swap the sum if it came from an odd offset; since the
+* computation is endian-independent this works.
+*/
+   new = ((new >> 8) & 0xff) | ((new << 8) & 0xff00);
+   }
+   checksum = sum + new;
+   if (checksum > 0x)
+   checksum -= 0x;
+
+   return (~checksum) & 0x;
+}
+
+int ip_checksum_ok(const void *addr, uint nbytes)
+{
+   return !(compute_ip_checksum(addr, nbytes) & 0xfffe);
+}
diff --git a/net/Makefile b/net/Makefile
index 2a700c8401..fef71b940a 100644
--- a/net/Makefile
+++ b/net/Makefile
@@ -5,7 +5,6 @@
 
 #ccflags-y += -DDEBUG
 
-obj-y += checksum.o
 obj-$(CONFIG_NET)  += arp.o
 obj-$(CONFIG_CMD_BOOTP) += bootp.o
 obj-$(CONFIG_CMD_CDP)  += cdp.o
diff --git a/net/checksum.c b/net/checksum.c
deleted file mode 100644
index 16ef416356..00
--- a/net/checksum.c
+++ /dev/null
@@ -1,59 +0,0 @@
-// SPDX-License-Identifier: BSD-2-Clause
-/*
- * This file was originally taken from the FreeBSD project.
- *
- * Copyright (c) 2001 Charles Mott 
- * Copyright (c) 2008 coresystems GmbH
- * All rights reserved.
- */
-
-#include 
-#include 
-
-unsigned compute_ip_checksum(const void *vptr, unsigned nbytes)
-{
-   int sum, oddbyte;
-   const unsigned short *ptr = vptr;
-
-   sum = 0;
-   while (nbytes > 1) {
-   sum += *ptr++;
-   nbytes -= 2;
-   }
-   if (nbytes == 1) {
-   oddbyte = 0;
-   ((u8 *)&oddbyte)[0] = *(u8 *)ptr;
-   ((u8 *)&oddbyte)[1] = 0;
-   sum += oddbyte;
-   }
-   sum = (sum >> 16) + (sum & 0x);
-   sum += (sum >> 16);
-   sum = ~sum & 0x;
-
-   return sum;
-}
-
-unsigned add_ip_checksums(unsigned offset, unsigned sum, unsigned new)
-{
-   unsigned long checksum;
-
-   sum = ~sum & 0x;
-   new = ~new & 0x;
-   if (offset & 1) {
-   /*
-* byte-swap the sum if it came from an odd offset; since the
-* computation is endian independant this works.
-*/
-   new = ((new >> 8) & 0xff) | ((new << 8) & 0xff00);
-   }
-   checksum = sum + new;
-   if (checksum > 0x)
-   checksum -= 0x;
-
-   return (~checksum) & 0x;
-}
-
-int ip_checksum_ok(const void *addr, unsigned nbytes)
-{
-   return !(compute_ip_checksum(addr, nbytes) & 0xfffe);
-}
-- 
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[U-Boot] [PATCH v5 019/101] x86: power: Add an ACPI PMC uclass

2019-11-24 Thread Simon Glass
Intel x86 SoCs have a power manager/controller which handles several
power-related aspects of the platform. Add a uclass for this, with a few
useful operations.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v5: None
Changes in v4:
- Fix alpha order in Kconfig
- Switch over to use pinctrl for pad init/config

Changes in v3:
- Rename power-mgr uclass to acpi-pmc

Changes in v2: None

 drivers/power/Kconfig|   2 +
 drivers/power/acpi_pmc/Kconfig   |  25 +++
 drivers/power/acpi_pmc/Makefile  |   5 +
 drivers/power/acpi_pmc/acpi-pmc-uclass.c | 188 +++
 include/dm/uclass-id.h   |   1 +
 include/power/acpi_pmc.h | 185 ++
 6 files changed, 406 insertions(+)
 create mode 100644 drivers/power/acpi_pmc/Kconfig
 create mode 100644 drivers/power/acpi_pmc/Makefile
 create mode 100644 drivers/power/acpi_pmc/acpi-pmc-uclass.c
 create mode 100644 include/power/acpi_pmc.h

diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index 9495dca33b..cb2c6fe3eb 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -1,5 +1,7 @@
 menu "Power"
 
+source "drivers/power/acpi_pmc/Kconfig"
+
 source "drivers/power/domain/Kconfig"
 
 source "drivers/power/pmic/Kconfig"
diff --git a/drivers/power/acpi_pmc/Kconfig b/drivers/power/acpi_pmc/Kconfig
new file mode 100644
index 00..472a61a9fd
--- /dev/null
+++ b/drivers/power/acpi_pmc/Kconfig
@@ -0,0 +1,25 @@
+config ACPI_PMC
+   bool "Power Manager (x86 PMC) support"
+   help
+ Enable support for an x86-style power-management controller which
+ provides features including checking whether the system started from
+ resume, powering off the system and enabling/disabling the reset
+ mechanism.
+
+config SPL_ACPI_PMC
+   bool "Power Manager (x86 PMC) support in SPL"
+   default y if ACPI_PMC
+   help
+ Enable support for an x86-style power-management controller which
+ provides features including checking whether the system started from
+ resume, powering off the system and enabling/disabling the reset
+ mechanism.
+
+config TPL_ACPI_PMC
+   bool "Power Manager (x86 PMC) support in TPL"
+   default y if ACPI_PMC
+   help
+ Enable support for an x86-style power-management controller which
+ provides features including checking whether the system started from
+ resume, powering off the system and enabling/disabling the reset
+ mechanism.
diff --git a/drivers/power/acpi_pmc/Makefile b/drivers/power/acpi_pmc/Makefile
new file mode 100644
index 00..7c1ba05c9f
--- /dev/null
+++ b/drivers/power/acpi_pmc/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2019 Google LLC
+
+obj-$(CONFIG_$(SPL_TPL_)ACPI_PMC) += acpi-pmc-uclass.o
diff --git a/drivers/power/acpi_pmc/acpi-pmc-uclass.c 
b/drivers/power/acpi_pmc/acpi-pmc-uclass.c
new file mode 100644
index 00..653c71b948
--- /dev/null
+++ b/drivers/power/acpi_pmc/acpi-pmc-uclass.c
@@ -0,0 +1,188 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#define LOG_CATEGORY UCLASS_ACPI_PMC
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+enum {
+   PM1_STS = 0x00,
+   PM1_EN  = 0x02,
+   PM1_CNT = 0x04,
+
+   GPE0_STS= 0x20,
+   GPE0_EN = 0x30,
+};
+
+struct tco_regs {
+   u32 tco_rld;
+   u32 tco_sts;
+   u32 tco1_cnt;
+   u32 tco_tmr;
+};
+
+enum {
+   TCO_STS_TIMEOUT = 1 << 3,
+   TCO_STS_SECOND_TO_STS   = 1 << 17,
+   TCO1_CNT_HLT= 1 << 11,
+};
+
+static void pmc_fill_pm_reg_info(struct udevice *dev)
+{
+   struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
+   int i;
+
+   upriv->pm1_sts = inw(upriv->acpi_base + PM1_STS);
+   upriv->pm1_en = inw(upriv->acpi_base + PM1_EN);
+   upriv->pm1_cnt = inw(upriv->acpi_base + PM1_CNT);
+
+   log_debug("pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n",
+ upriv->pm1_sts, upriv->pm1_en, upriv->pm1_cnt);
+
+   for (i = 0; i < GPE0_REG_MAX; i++) {
+   upriv->gpe0_sts[i] = inl(upriv->acpi_base + GPE0_STS + i * 4);
+   upriv->gpe0_en[i] = inl(upriv->acpi_base + GPE0_EN + i * 4);
+   log_debug("gpe0_sts[%d]: %08x gpe0_en[%d]: %08x\n", i,
+ upriv->gpe0_sts[i], i, upriv->gpe0_en[i]);
+   }
+}
+
+int pmc_disable_tco_base(ulong tco_base)
+{
+   struct tco_regs *regs = (struct tco_regs *)tco_base;
+
+   debug("tco_base %lx = %x\n", (ulong)®s->tco1_cnt, TCO1_CNT_HLT);
+   setio_32(®s->tco1_cnt, TCO1_CNT_HLT);
+
+   return 0;
+}
+
+int pmc_init(struct udevice *dev)
+{
+   const struct acpi_pmc_ops *ops = acpi_pmc_get_ops(dev);
+   int ret;
+
+   pmc_fill_pm_reg_info(dev);
+   if (!ops->init)
+

[U-Boot] [PATCH v5 016/101] x86: timer: Reduce timer code size in TPL on Intel CPUs

2019-11-24 Thread Simon Glass
Most of the timer-calibration methods are not needed on recent Intel CPUs
and just increase code size. Add an option to use the known-good way to
get the clock frequency in TPL. Size reduction is about 700 bytes.

Note that version 1 of this commit caused bootstage to crash since the CPU
was not identified. This is corrected by changes previously applied to
make sure that the CPU is identified before spl_init() is called, such as

   39146a2e0b x86: Move CPU init to before spl_init()

Signed-off-by: Simon Glass 
---

Changes in v5: None
Changes in v4:
- Update commit message to indicate that CPU-identity bug is fixed

Changes in v3: None
Changes in v2: None

 drivers/timer/Kconfig | 9 +
 drivers/timer/tsc_timer.c | 7 +--
 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 41f9755133..96cc49273f 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -188,6 +188,15 @@ config X86_TSC_READ_BASE
  The only exception is when U-Boot is used as a secondary bootloader,
  where this option should be enabled.
 
+config TPL_X86_TSC_TIMER_NATIVE
+   bool "x86 TSC timer uses native calibration"
+   depends on TPL && X86_TSC_TIMER
+   help
+ Selects native timer calibration for TPL and don't include the other
+ methods in the code. This helps to reduce code size in TPL and works
+ on fairly modern Intel chips. Code-size reductions is about 700
+ bytes.
+
 config MTK_TIMER
bool "MediaTek timer support"
depends on TIMER
diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c
index a11a82f21a..ffa2ac74c3 100644
--- a/drivers/timer/tsc_timer.c
+++ b/drivers/timer/tsc_timer.c
@@ -49,8 +49,7 @@ static unsigned long native_calibrate_tsc(void)
return 0;
 
crystal_freq = tsc_info.ecx / 1000;
-
-   if (!crystal_freq) {
+   if (!CONFIG_IS_ENABLED(X86_TSC_TIMER_NATIVE) && !crystal_freq) {
switch (gd->arch.x86_model) {
case INTEL_FAM6_SKYLAKE_MOBILE:
case INTEL_FAM6_SKYLAKE_DESKTOP:
@@ -406,6 +405,10 @@ static void tsc_timer_ensure_setup(bool early)
if (fast_calibrate)
goto done;
 
+   /* Reduce code size by dropping other methods */
+   if (CONFIG_IS_ENABLED(X86_TSC_TIMER_NATIVE))
+   panic("no timer");
+
fast_calibrate = cpu_mhz_from_cpuid();
if (fast_calibrate)
goto done;
-- 
2.24.0.432.g9d3f5f5b63-goog

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[U-Boot] [PATCH v5 017/101] x86: Drop unnecessary cpu code for TPL

2019-11-24 Thread Simon Glass
We don't need to know every detail about the CPU in TPL. Drop some
superfluous functions to reduce code size. Add a simple CPU detection
algorithm which just supports Intel and AMD, since we only support TPL
on Intel, so far.

Signed-off-by: Simon Glass 
---

Changes in v5: None
Changes in v4:
- Drop 'if (0)' call to deep_magic_nexgen_probe() and use #ifndef instead
- Fix 'what' typo

Changes in v3: None
Changes in v2: None

 arch/x86/cpu/cpu.c  |  4 
 arch/x86/cpu/i386/cpu.c | 41 +
 2 files changed, 41 insertions(+), 4 deletions(-)

diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 9ee4b0294a..4795863b33 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -45,6 +45,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifndef CONFIG_TPL_BUILD
 static const char *const x86_vendor_name[] = {
[X86_VENDOR_INTEL] = "Intel",
[X86_VENDOR_CYRIX] = "Cyrix",
@@ -57,6 +58,7 @@ static const char *const x86_vendor_name[] = {
[X86_VENDOR_NSC]   = "NSC",
[X86_VENDOR_SIS]   = "SiS",
 };
+#endif
 
 int __weak x86_cleanup_before_linux(void)
 {
@@ -113,6 +115,7 @@ int icache_status(void)
return 1;
 }
 
+#ifndef CONFIG_TPL_BUILD
 const char *cpu_vendor_name(int vendor)
 {
const char *name;
@@ -123,6 +126,7 @@ const char *cpu_vendor_name(int vendor)
 
return name;
 }
+#endif
 
 char *cpu_get_name(char *name)
 {
diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c
index 31663714a0..1b0ca0c90b 100644
--- a/arch/x86/cpu/i386/cpu.c
+++ b/arch/x86/cpu/i386/cpu.c
@@ -20,6 +20,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -57,6 +58,8 @@ struct cpuinfo_x86 {
uint8_t x86_mask;
 };
 
+/* gcc 7.3 does not wwant to drop x86_vendors, so use #ifdef */
+#ifndef CONFIG_TPL_BUILD
 /*
  * List of cpu vendor strings along with their normalized
  * id values.
@@ -77,6 +80,7 @@ static const struct {
{ X86_VENDOR_NSC,   "Geode by NSC", },
{ X86_VENDOR_SIS,   "SiS SiS SiS ", },
 };
+#endif
 
 static void load_ds(u32 segment)
 {
@@ -198,6 +202,7 @@ static inline int test_cyrix_52div(void)
return (unsigned char) (test >> 8) == 0x02;
 }
 
+#ifndef CONFIG_TPL_BUILD
 /*
  * Detect a NexGen CPU running without BIOS hypercode new enough
  * to have CPUID. (Thanks to Herbert Oppmann)
@@ -218,6 +223,7 @@ static int deep_magic_nexgen_probe(void)
: "=a" (ret) : : "cx", "dx");
return  ret;
 }
+#endif
 
 static bool has_cpuid(void)
 {
@@ -229,6 +235,7 @@ static bool has_mtrr(void)
return cpuid_edx(0x0001) & (1 << 12) ? true : false;
 }
 
+#ifndef CONFIG_TPL_BUILD
 static int build_vendor_name(char *vendor_name)
 {
struct cpuid_result result;
@@ -241,14 +248,40 @@ static int build_vendor_name(char *vendor_name)
 
return result.eax;
 }
+#endif
 
 static void identify_cpu(struct cpu_device_id *cpu)
 {
+   cpu->device = 0; /* fix gcc 4.4.4 warning */
+
+   /*
+* Do a quick and dirty check to save space - Intel and AMD only and
+* just the vendor. This is enough for most TPL code.
+*/
+   if (spl_phase() == PHASE_TPL) {
+   struct cpuid_result result;
+
+   result = cpuid(0x);
+   switch (result.ecx >> 24) {
+   case 'l': /* GenuineIntel */
+   cpu->vendor = X86_VENDOR_INTEL;
+   break;
+   case 'D': /* AuthenticAMD */
+   cpu->vendor = X86_VENDOR_AMD;
+   break;
+   default:
+   cpu->vendor = X86_VENDOR_ANY;
+   break;
+   }
+   return;
+   }
+
+/* gcc 7.3 does not want to drop x86_vendors, so use #ifdef */
+#ifndef CONFIG_TPL_BUILD
char vendor_name[16];
int i;
 
vendor_name[0] = '\0'; /* Unset */
-   cpu->device = 0; /* fix gcc 4.4.4 warning */
 
/* Find the id and vendor_name */
if (!has_cpuid()) {
@@ -264,9 +297,8 @@ static void identify_cpu(struct cpu_device_id *cpu)
/* Detect NexGen with old hypercode */
else if (deep_magic_nexgen_probe())
memcpy(vendor_name, "NexGenDriven", 13);
-   }
-   if (has_cpuid()) {
-   int  cpuid_level;
+   } else {
+   int cpuid_level;
 
cpuid_level = build_vendor_name(vendor_name);
vendor_name[12] = '\0';
@@ -286,6 +318,7 @@ static void identify_cpu(struct cpu_device_id *cpu)
break;
}
}
+#endif
 }
 
 static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms)
-- 
2.24.0.432.g9d3f5f5b63-goog

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[U-Boot] [PATCH v5 029/101] x86: Correct mrccache find_next_mrc_cache() calculation

2019-11-24 Thread Simon Glass
This should take account of the end of the new cache record since a record
cannot extend beyond the end of the flash region. This problem was not
seen before due to the alignment of the relatively small amount of MRC
data.

But with Apollo Lake the MRC data is about 45KB, even if most of it is
zeroes.

Fix this bug and update the parameter name to be less confusing.

Signed-off-by: Simon Glass 
---

Changes in v5: None
Changes in v4:
- Add comments about MRC-cache records being the same size
- apollolake -> Apollo Lake

Changes in v3:
- Add an extra size parameter to the find_next_mrc_cache() function

Changes in v2: None

 arch/x86/lib/mrccache.c | 18 ++
 1 file changed, 14 insertions(+), 4 deletions(-)

diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c
index 33bb52039b..9d56685d36 100644
--- a/arch/x86/lib/mrccache.c
+++ b/arch/x86/lib/mrccache.c
@@ -80,21 +80,31 @@ struct mrc_data_container *mrccache_find_current(struct 
mrc_region *entry)
 /**
  * find_next_mrc_cache() - get next cache entry
  *
+ * This moves to the next cache entry in the region, making sure it has enough
+ * space to hold data of size @data_size.
+ *
  * @entry: MRC cache flash area
  * @cache: Entry to start from
+ * @data_size: Required data size of the new entry. Note that we assume that
+ * all cache entries are the same size
  *
  * @return next cache entry if found, NULL if we got to the end
  */
 static struct mrc_data_container *find_next_mrc_cache(struct mrc_region *entry,
-   struct mrc_data_container *cache)
+   struct mrc_data_container *prev, int data_size)
 {
+   struct mrc_data_container *cache;
ulong base_addr, end_addr;
 
base_addr = entry->base + entry->offset;
end_addr = base_addr + entry->length;
 
-   cache = next_mrc_block(cache);
-   if ((ulong)cache >= end_addr) {
+   /*
+* We assume that all cache entries are the same size, but let's use
+* data_size here for clarity.
+*/
+   cache = next_mrc_block(prev);
+   if ((ulong)cache + mrc_block_size(data_size) > end_addr) {
/* Crossed the boundary */
cache = NULL;
debug("%s: no available entries found\n", __func__);
@@ -131,7 +141,7 @@ int mrccache_update(struct udevice *sf, struct mrc_region 
*entry,
 
/* Move to the next block, which will be the first unused block */
if (cache)
-   cache = find_next_mrc_cache(entry, cache);
+   cache = find_next_mrc_cache(entry, cache, cur->data_size);
 
/*
 * If we have got to the end, erase the entire mrc-cache area and start
-- 
2.24.0.432.g9d3f5f5b63-goog

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[U-Boot] [PATCH v5 031/101] x86: Adjust mrccache_get_region() to support get_mmap()

2019-11-24 Thread Simon Glass
It is now possible to obtain the memory map for a SPI controllers instead
of having it hard-coded in the device tree. Update the code to support
this.

Signed-off-by: Simon Glass 
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Use SPI mmap() instead of SPI flash

 arch/x86/lib/mrccache.c | 18 ++
 1 file changed, 14 insertions(+), 4 deletions(-)

diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c
index 50c72bf962..7136166be6 100644
--- a/arch/x86/lib/mrccache.c
+++ b/arch/x86/lib/mrccache.c
@@ -210,6 +210,9 @@ int mrccache_get_region(struct udevice **devp, struct 
mrc_region *entry)
 {
struct udevice *dev;
ofnode mrc_node;
+   ulong map_base;
+   uint map_size;
+   uint offset;
u32 reg[2];
int ret;
 
@@ -221,10 +224,15 @@ int mrccache_get_region(struct udevice **devp, struct 
mrc_region *entry)
ret = uclass_find_first_device(UCLASS_SPI_FLASH, &dev);
if (ret)
return log_msg_ret("Cannot find SPI flash\n", ret);
-   ret = dev_read_u32_array(dev, "memory-map", reg, 2);
-   if (ret)
-   return log_msg_ret("Cannot find memory map\n", ret);
-   entry->base = reg[0];
+   ret = dm_spi_get_mmap(dev, &map_base, &map_size, &offset);
+   if (!ret) {
+   entry->base = map_base;
+   } else {
+   ret = dev_read_u32_array(dev, "memory-map", reg, 2);
+   if (ret)
+   return log_msg_ret("Cannot find memory map\n", ret);
+   entry->base = reg[0];
+   }
 
/* Find the place where we put the MRC cache */
mrc_node = dev_read_subnode(dev, "rw-mrc-cache");
@@ -239,6 +247,8 @@ int mrccache_get_region(struct udevice **devp, struct 
mrc_region *entry)
 
if (devp)
*devp = dev;
+   debug("MRC cache in '%s', offset %x, len %x, base %x\n",
+ dev->name, entry->offset, entry->length, entry->base);
 
return 0;
 }
-- 
2.24.0.432.g9d3f5f5b63-goog

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[U-Boot] [PATCH v5 014/101] Revert "RFC: sandbox: net: Suppress the MAC-address warnings"

2019-11-24 Thread Simon Glass
This reverts commit 96ac4def8b6686de8566b91419ce98cd5765079b.

Signed-off-by: Simon Glass 
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/sandbox/cpu/state.c | 12 ++--
 arch/sandbox/include/asm/state.h |  5 +
 cmd/nvedit.c |  8 
 include/configs/sandbox.h|  7 +--
 include/env.h| 12 
 net/eth-uclass.c | 11 ++-
 test/dm/test-main.c  |  2 +-
 7 files changed, 11 insertions(+), 46 deletions(-)

diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c
index 70b278e4e2..dee5fde4f7 100644
--- a/arch/sandbox/cpu/state.c
+++ b/arch/sandbox/cpu/state.c
@@ -351,7 +351,7 @@ bool state_get_skip_delays(void)
return state->skip_delays;
 }
 
-void state_reset_for_test(struct sandbox_state *state, bool eth_vars)
+void state_reset_for_test(struct sandbox_state *state)
 {
/* No reset yet, so mark it as such. Always allow power reset */
state->last_sysreset = SYSRESET_COUNT;
@@ -367,14 +367,6 @@ void state_reset_for_test(struct sandbox_state *state, 
bool eth_vars)
 */
INIT_LIST_HEAD(&state->mapmem_head);
state->next_tag = state->ram_size;
-
-   if (eth_vars) {
-   /* set up some environment variables needed by the eth tests */
-   env_set_for_test("ethaddr", "00:00:11:22:33:44");
-   env_set_for_test("eth1addr", "00:00:11:22:33:45");
-   env_set_for_test("eth3addr", "00:00:11:22:33:46");
-   env_set_for_test("eth5addr", "00:00:11:22:33:47");
-   }
 }
 
 int state_init(void)
@@ -385,7 +377,7 @@ int state_init(void)
state->ram_buf = os_malloc(state->ram_size);
assert(state->ram_buf);
 
-   state_reset_for_test(state, false);
+   state_reset_for_test(state);
/*
 * Example of how to use GPIOs:
 *
diff --git a/arch/sandbox/include/asm/state.h b/arch/sandbox/include/asm/state.h
index 4fa3b094a9..ad3e94beb9 100644
--- a/arch/sandbox/include/asm/state.h
+++ b/arch/sandbox/include/asm/state.h
@@ -251,11 +251,8 @@ bool state_get_skip_delays(void);
  * state_reset_for_test() - Reset ready to re-run tests
  *
  * This clears out any test state ready for another test run.
- *
- * @param stateSandbox state to update
- * @param eth_vars Set environment variables for eth tests
  */
-void state_reset_for_test(struct sandbox_state *state, bool eth_vars);
+void state_reset_for_test(struct sandbox_state *state);
 
 /**
  * state_show() - Show information about the sandbox state
diff --git a/cmd/nvedit.c b/cmd/nvedit.c
index 6a01d755bb..99a3bc57b1 100644
--- a/cmd/nvedit.c
+++ b/cmd/nvedit.c
@@ -299,14 +299,6 @@ static int _do_env_set(int flag, int argc, char * const 
argv[], int env_flag)
return 0;
 }
 
-int env_set_for_test(const char *varname, const char *value)
-{
-   const char * const argv[4] = { "setenv", varname, value, NULL };
-
-   assert(value);
-   return _do_env_set(0, 3, (char * const *)argv, 0);
-}
-
 int env_set(const char *varname, const char *varvalue)
 {
const char * const argv[4] = { "setenv", varname, varvalue, NULL };
diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index 0866cc3b63..1c13055cdc 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h
@@ -96,8 +96,11 @@
"stderr=serial,vidconsole\0"
 #endif
 
-/* Note that some ethernet variables are set in state_reset_for_test() */
-#define SANDBOX_ETH_SETTINGS   "ipaddr=1.2.3.4\0"
+#define SANDBOX_ETH_SETTINGS   "ethaddr=00:00:11:22:33:44\0" \
+   "eth1addr=00:00:11:22:33:45\0" \
+   "eth3addr=00:00:11:22:33:46\0" \
+   "eth5addr=00:00:11:22:33:47\0" \
+   "ipaddr=1.2.3.4\0"
 
 #define MEM_LAYOUT_ENV_SETTINGS \
"bootm_size=0x1000\0" \
diff --git a/include/env.h b/include/env.h
index bc48a72cde..b72239f6a5 100644
--- a/include/env.h
+++ b/include/env.h
@@ -145,18 +145,6 @@ int env_get_yesno(const char *var);
  */
 int env_set(const char *varname, const char *value);
 
-/**
- * env_set_for_test() - Set the value of a variable for testing
- *
- * This works as if the variable value was defined in the built-in environment,
- * so uses a flags value of 0. This should only be used in tests.
- *
- * @varname: Variable to adjust
- * @value: Value to set for the variable (cannot be NULL)
- * @return 0 if OK, 1 on error
- */
-int env_set_for_test(const char *varname, const char *value);
-
 /**
  * env_get_ulong() - Return an environment variable as an integer value
  *
diff --git a/net/eth-uclass.c b/net/eth-uclass.c
index 6c19536138..3bd98b01ad 100644
--- a/net/eth-uclass.c
+++ b/net/eth-uclass.c
@@ -485,12 +485,6 @@ static int eth_post_probe(struct udevice 

[U-Boot] [PATCH v5 018/101] x86: Drop unnecessary interrupt code for TPL

2019-11-24 Thread Simon Glass
We don't expect an exception in TPL and don't need to set up interrupts in
TPL. Drop this whole file.

Signed-off-by: Simon Glass 
---

Changes in v5: None
Changes in v4:
- Drop the whole interrupt file for TPL

Changes in v3: None
Changes in v2: None

 arch/x86/cpu/i386/Makefile | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/x86/cpu/i386/Makefile b/arch/x86/cpu/i386/Makefile
index 0c47252610..18e152074a 100644
--- a/arch/x86/cpu/i386/Makefile
+++ b/arch/x86/cpu/i386/Makefile
@@ -5,5 +5,7 @@
 
 obj-y += call64.o
 obj-y += cpu.o
+ifndef CONFIG_TPL_BUILD
 obj-y += interrupt.o
+endif
 obj-y += setjmp.o
-- 
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[U-Boot] [PATCH v5 012/101] board_r: Move early-timer init later

2019-11-24 Thread Simon Glass
At present the early timer init happens as soon as driver mode is set up.
This makes it impossible to do any in that needs driver model but must run
before devices are problem (as needed with Intel's FSP-S, for example).

In any case it is not a good idea to tie probing of particular drivers too
closely to the DM init.

Create a new function to init the timer and put it a bit later in the
sequence.

Signed-off-by: Simon Glass 
---

Changes in v5: None
Changes in v4:
- Add new patch to move early-timer init later

Changes in v3: None
Changes in v2: None

 common/board_r.c| 19 ++-
 drivers/pinctrl/Kconfig | 14 ++
 2 files changed, 28 insertions(+), 5 deletions(-)

diff --git a/common/board_r.c b/common/board_r.c
index e385696a6d..70736397e4 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -306,16 +306,24 @@ static int initr_dm(void)
bootstage_accum(BOOTSTATE_ID_ACCUM_DM_R);
if (ret)
return ret;
-#ifdef CONFIG_TIMER_EARLY
-   ret = dm_timer_init();
-   if (ret)
-   return ret;
-#endif
 
return 0;
 }
 #endif
 
+static int initr_dm_devices(void)
+{
+   int ret;
+
+   if (IS_ENABLED(CONFIG_TIMER_EARLY)) {
+   ret = dm_timer_init();
+   if (ret)
+   return ret;
+   }
+
+   return 0;
+}
+
 static int initr_bootstage(void)
 {
bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_R, "board_init_r");
@@ -702,6 +710,7 @@ static init_fnc_t init_sequence_r[] = {
efi_memory_init,
 #endif
initr_binman,
+   initr_dm_devices,
stdio_init_tables,
initr_serial,
initr_announce,
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index eadcfd6652..449f614eb2 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -82,6 +82,13 @@ config SPL_PINCTRL
  This option is an SPL-variant of the PINCTRL option.
  See the help of PINCTRL for details.
 
+config TPL_PINCTRL
+   bool "Support pin controllers in TPL"
+   depends on TPL && TPL_DM
+   help
+ This option is an TPL variant of the PINCTRL option.
+ See the help of PINCTRL for details.
+
 config SPL_PINCTRL_FULL
bool "Support full pin controllers in SPL"
depends on SPL_PINCTRL && SPL_OF_CONTROL
@@ -91,6 +98,13 @@ config SPL_PINCTRL_FULL
  This option is an SPL-variant of the PINCTRL_FULL option.
  See the help of PINCTRL_FULL for details.
 
+config TPL_PINCTRL_FULL
+   bool "Support full pin controllers in TPL"
+   depends on TPL_PINCTRL && TPL_OF_CONTROL
+   help
+ This option is an TPL-variant of the PINCTRL_FULL option.
+ See the help of PINCTRL_FULL for details.
+
 config SPL_PINCTRL_GENERIC
bool "Support generic pin controllers in SPL"
depends on SPL_PINCTRL_FULL
-- 
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[U-Boot] [PATCH v5 011/101] fdt: Show the preprocessed .dts file on error

2019-11-24 Thread Simon Glass
When device-tree compilation fails it is sometimes tricky to see which
line is broken, since the input file to dtc is a pre-processed version
of the device tree.

Add a line that points to the file that needs to be checked:

When the error is in the main .dts file, output is something like this:

   output: 'Error: arch/x86/dts/.chromebook_coral.dtb.pre.tmp:478.46-47
syntax error
   FATAL ERROR: Unable to parse input tree

but in fact looking at that file shows nothing useful:

   PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_157, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD)

Instead we need to look at the preprocessed file, which shows:

   163 ((1U << 30) | (1 << 10)) ((0xb << 10) | PAD_CFG1_IOSSTATE_HIZCRX1)

Here it is clear that PAD_CFG1_IOSSTATE_HIZCRX1 is not defined and so is
not being resolved by the preprocessor.

This commit adds an additional useful message:

   Check arch/x86/dts/.chromebook_coral.dtb.dts.tmp for errors

Note that if the error is reported in an included file, such as
u-boot.dtsi then the output is the following:

   Error: arch/x86/dts/u-boot.dtsi:137.14-15 syntax error
   FATAL ERROR: Unable to parse input tree

But again, if the error is due to a preprocessor failure, like this:

   filename = CONFIG_IFW_INPUT_FILE;

then you can't tell what the problem is by looking at the source. All you
see is the original code:

intel-ifwi {
filename = CONFIG_IFW_INPUT_FILE;
...
};
};
intel-fsp-m {
filename = CONFIG_FSP_FILE_M;
};

Everything looks fine. But looking at the output of the preprocessor:

 intel-ifwi {
  filename = CONFIG_IFW_INPUT_FILE;
  ...
 };
 intel-fsp-m {
  filename = "fsp_m.bin";
 };

This shows that the filename (normally "fitimage.bin") has not been
inserted the preprocess, leading to the realisation that the value should
be CONFIG_IFWI_INPUT_FILE.

If the above does not make sense, I encourage people to try introducing
errors in the device tree preprocessed values.

Signed-off-by: Simon Glass 
---

Changes in v5: None
Changes in v4:
- One last desperate attempt to try to explain the purpose of this commit
- Update the message to mention the preprocessed file, not un-preprocessed

Changes in v3:
- Update example error message to better show the intended purpose

Changes in v2: None

 scripts/Makefile.lib | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index ef116e0e0a..c10cd83a0a 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -300,7 +300,9 @@ cmd_dtc = mkdir -p $(dir ${dtc-tmp}) ; \
$(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $(pre-tmp) 
; \
$(DTC) -O dtb -o $@ -b 0 \
-i $(dir $<) $(DTC_FLAGS) \
-   -d $(depfile).dtc.tmp $(dtc-tmp) ; \
+   -d $(depfile).dtc.tmp $(dtc-tmp) || \
+   (echo "Check $(shell pwd)/$(pre-tmp) for errors" && false) \
+   ; \
cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile) ; \
sed -i "s:$(pre-tmp):$(<):" $(depfile)
 
-- 
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[U-Boot] [PATCH v5 021/101] x86: power: Add a 'pmc' command

2019-11-24 Thread Simon Glass
Add a simple command to show information about the PMC.

Signed-off-by: Simon Glass 
---

Changes in v5: None
Changes in v4: None
Changes in v3:
- Rename power-mgr uclass to acpi-pmc

Changes in v2: None

 arch/Kconfig |  1 +
 cmd/Kconfig  |  8 ++
 cmd/Makefile |  1 +
 cmd/pmc.c| 81 
 4 files changed, 91 insertions(+)
 create mode 100644 cmd/pmc.c

diff --git a/arch/Kconfig b/arch/Kconfig
index 8094e18663..e1f1fcd275 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -135,6 +135,7 @@ config SANDBOX
imply DM_MDIO_MUX
imply ACPI_PMC
imply ACPI_PMC_SANDBOX
+   imply CMD_PMC
 
 config SH
bool "SuperH architecture"
diff --git a/cmd/Kconfig b/cmd/Kconfig
index cf982ff65e..acf04dc6ac 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -228,6 +228,14 @@ config CMD_LICENSE
help
  Print GPL license text
 
+config CMD_PMC
+   bool "pmc"
+   help
+ Provides access to the Intel Power-Management Controller (PMC) so
+ that its state can be examined. This does not currently support
+ changing the state but it is still useful for debugging and seeing
+ what is going on.
+
 config CMD_REGINFO
bool "reginfo"
depends on PPC
diff --git a/cmd/Makefile b/cmd/Makefile
index 2d723ea0f0..7d54220531 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -108,6 +108,7 @@ ifdef CONFIG_PCI
 obj-$(CONFIG_CMD_PCI) += pci.o
 endif
 obj-$(CONFIG_CMD_PINMUX) += pinmux.o
+obj-$(CONFIG_CMD_PMC) += pmc.o
 obj-$(CONFIG_CMD_PXE) += pxe.o
 obj-$(CONFIG_CMD_WOL) += wol.o
 obj-$(CONFIG_CMD_QFW) += qfw.o
diff --git a/cmd/pmc.c b/cmd/pmc.c
new file mode 100644
index 00..cafeba9fcc
--- /dev/null
+++ b/cmd/pmc.c
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Intel PMC command
+ *
+ * Copyright 2019 Google LLC
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+static int get_pmc_dev(struct udevice **devp)
+{
+   struct udevice *dev;
+   int ret;
+
+   ret = uclass_first_device_err(UCLASS_ACPI_PMC, &dev);
+   if (ret) {
+   printf("Could not find device (err=%d)\n", ret);
+   return ret;
+   }
+   ret = pmc_init(dev);
+   if (ret) {
+   printf("Could not init device (err=%d)\n", ret);
+   return ret;
+   }
+   *devp = dev;
+
+   return 0;
+}
+
+static int do_pmc_init(cmd_tbl_t *cmdtp, int flag, int argc, char *const 
argv[])
+{
+   struct udevice *dev;
+   int ret;
+
+   ret = get_pmc_dev(&dev);
+   if (ret)
+   return CMD_RET_FAILURE;
+
+   return 0;
+}
+
+static int do_pmc_info(cmd_tbl_t *cmdtp, int flag, int argc, char *const 
argv[])
+{
+   struct udevice *dev;
+   int ret;
+
+   ret = get_pmc_dev(&dev);
+   if (ret)
+   return CMD_RET_FAILURE;
+   pmc_dump_info(dev);
+
+   return 0;
+}
+
+static cmd_tbl_t cmd_pmc_sub[] = {
+   U_BOOT_CMD_MKENT(init, 0, 1, do_pmc_init, "", ""),
+   U_BOOT_CMD_MKENT(info, 0, 1, do_pmc_info, "", ""),
+};
+
+static int do_pmc(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+   const cmd_tbl_t *cp;
+
+   if (argc < 2) /* no subcommand */
+   return cmd_usage(cmdtp);
+
+   cp = find_cmd_tbl(argv[1], &cmd_pmc_sub[0], ARRAY_SIZE(cmd_pmc_sub));
+   if (!cp)
+   return CMD_RET_USAGE;
+
+   return cp->cmd(cmdtp, flag, argc, argv);
+}
+
+U_BOOT_CMD(
+   pmc, 2, 1, do_pmc, "Power-management controller info",
+   "info - read state and show info about the PMC\n"
+   "pmc init - read state from the PMC\n"
+   );
-- 
2.24.0.432.g9d3f5f5b63-goog

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[U-Boot] [PATCH v5 013/101] RFC: sandbox: net: Suppress the MAC-address warnings

2019-11-24 Thread Simon Glass
These warnings appear every thing sandbox is run (see below) and dwarf the
actual useful output. Suppress them in two ways:

1. For the mismatch warnings, only set the ethaddr environment
variables when running tests.

2. For the 'MAC address from ROM' warning, never print this on sandbox.

Signed-off-by: Simon Glass 
---
Unfortunately this breaks the tests so is not applicable as is:

$ /tmp/b/sandbox/u-boot -T -c "ut dm eth_prime"

U-Boot 2019.10-00508-g95f6257285-dirty (Oct 13 2019 - 09:21:34 -0600)

Model: sandbox
DRAM:  128 MiB
WDT:   Started with servicing (60s timeout)
MMC:   mmc2: 2 (SD), mmc1: 1 (SD), mmc0: 0 (SD)
In:serial
Out:   vidconsole
Err:   vidconsole
Model: sandbox
SCSI:
Net:
Error: eth@10002000 address not set.
eth-1: eth@10002000
Error: eth@10003000 address not set.
, eth-1: eth@10003000
Error: sbe5 address not set.
, eth-1: sbe5
Error: eth@10004000 address not set.
, eth-1: eth@10004000
Test: dm_test_eth_prime: eth.c
Test: dm_test_eth_prime: eth.c (flat tree)
Failures: 0

Old output:

U-Boot 2019.10-rc2

Model: sandbox
DRAM:  128 MiB

Warning: host_lo MAC addresses don't match:
Address in ROM is  a6:28:b7:47:28:93
Address in environment is  00:00:11:22:33:44

Warning: host_enp5s0 MAC addresses don't match:
Address in ROM is  a6:28:b7:47:28:93
Address in environment is  00:00:11:22:33:45

Warning: host_eth6 using MAC address from ROM

Warning: host_docker0 MAC addresses don't match:
Address in ROM is  a6:28:b7:47:28:93
Address in environment is  00:00:11:22:33:46

Warning: host_docker_gwbridge using MAC address from ROM

Warning: host_veth1118e68 MAC addresses don't match:
Address in ROM is  a6:28:b7:47:28:93
Address in environment is  00:00:11:22:33:47
WDT:   Not found!
MMC:
In:cros-ec-keyb
Out:   vidconsole
Err:   vidconsole
Model: sandbox
SCSI:
Net:   eth0: host_lo, eth1: host_enp5s0, eth2: host_eth6, eth3: host_docker0, 
eth4: host_docker_gwbridge, eth5: host_veth1118e68
Error: eth@10002000 address not set.
, eth-1: eth@10002000
Test 'pmc_base' not found

Warning: host_lo MAC addresses don't match:
Address in ROM is  2a:24:9a:31:90:f8
Address in environment is  00:00:11:22:33:44

Warning: host_enp5s0 MAC addresses don't match:
Address in ROM is  ce:23:d9:74:6f:6c
Address in environment is  00:00:11:22:33:45

Warning: host_eth6 using MAC address from ROM

Warning: host_docker0 MAC addresses don't match:
Address in ROM is  ee:22:1c:3b:be:bc
Address in environment is  00:00:11:22:33:46

Warning: host_docker_gwbridge using MAC address from ROM

Warning: host_veth1118e68 MAC addresses don't match:
Address in ROM is  ae:20:9e:3d:a4:9f
Address in environment is  00:00:11:22:33:47

New output:
U-Boot 2019.10

Model: sandbox
DRAM:  128 MiB
WDT:   Not found!
MMC:
In:cros-ec-keyb
Out:   vidconsole
Err:   vidconsole
Model: sandbox
SCSI:
Net:   eth0: host_lo, eth1: host_enp5s0, eth2: host_eth6, eth3: host_docker0, 
eth4: host_docker_gwbridge, eth5: host_vethc7e1b9e
Error: eth@10002000 address not set.
, eth-1: eth@10002000
Hit any key to stop autoboot:  0
=>


Changes in v5: None
Changes in v4: None
Changes in v3:
- Only supress the 'MAC address from ROM' warning on sandbox
- Set the environment variables at runtime to avoid other warnings

Changes in v2: None

 arch/sandbox/cpu/state.c | 12 ++--
 arch/sandbox/include/asm/state.h |  5 -
 cmd/nvedit.c |  8 
 include/configs/sandbox.h|  7 ++-
 include/env.h| 12 
 net/eth-uclass.c | 11 +--
 test/dm/test-main.c  |  2 +-
 7 files changed, 46 insertions(+), 11 deletions(-)

diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c
index dee5fde4f7..70b278e4e2 100644
--- a/arch/sandbox/cpu/state.c
+++ b/arch/sandbox/cpu/state.c
@@ -351,7 +351,7 @@ bool state_get_skip_delays(void)
return state->skip_delays;
 }
 
-void state_reset_for_test(struct sandbox_state *state)
+void state_reset_for_test(struct sandbox_state *state, bool eth_vars)
 {
/* No reset yet, so mark it as such. Always allow power reset */
state->last_sysreset = SYSRESET_COUNT;
@@ -367,6 +367,14 @@ void state_reset_for_test(struct sandbox_state *state)
 */
INIT_LIST_HEAD(&state->mapmem_head);
state->next_tag = state->ram_size;
+
+   if (eth_vars) {
+   /* set up some environment variables needed by the eth tests */
+   env_set_for_test("ethaddr", "00:00:11:22:33:44");
+   env_set_for_test("eth1addr", "00:00:11:22:33:45");
+   env_set_for_test("eth3addr", "00:00:11:22:33:46");
+   env_set_for_test("eth5addr", "00:00:11:22:33:47");
+   }
 }
 
 int state_init(void)
@@ -377,7 +385,7 @@ int state_init(void)
state->ram_buf = os_malloc(state->ram_size);
assert(state->ram_buf);
 
-   state_reset_for_test(state);
+   state_reset_for_test(state, false);
 

[U-Boot] [PATCH v5 022/101] pci: Add support for p2sb uclass

2019-11-24 Thread Simon Glass
The Primary-to-Sideband bus (P2SB) is used to access various peripherals
through memory-mapped I/O in a large chunk of PCI space. The space is
segmented into different channels and peripherals are accessed by
device-specific means within those channels. Devices should be added in
the device tree as subnodes of the p2sb.

This adds a uclass and enables it for sandbox.

Signed-off-by: Simon Glass 

---

Changes in v5:
- Add a way to obtain the port ID for a device

Changes in v4:
- Adjust condition for binding children

Changes in v3: None
Changes in v2: None

 configs/sandbox_defconfig |   1 +
 configs/sandbox_spl_defconfig |   1 +
 drivers/misc/Kconfig  |  33 ++
 drivers/misc/Makefile |   1 +
 drivers/misc/p2sb-uclass.c| 216 ++
 include/dm/uclass-id.h|   1 +
 include/p2sb.h| 135 +
 7 files changed, 388 insertions(+)
 create mode 100644 drivers/misc/p2sb-uclass.c
 create mode 100644 include/p2sb.h

diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index a8144436eb..5a3c4f151d 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -151,6 +151,7 @@ CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCI_SANDBOX=y
+CONFIG_P2SB=y
 CONFIG_PHY=y
 CONFIG_PHY_SANDBOX=y
 CONFIG_PINCTRL=y
diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig
index 02702fa7a5..478e4bd9d4 100644
--- a/configs/sandbox_spl_defconfig
+++ b/configs/sandbox_spl_defconfig
@@ -136,6 +136,7 @@ CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCI_SANDBOX=y
+CONFIG_P2SB=y
 CONFIG_PHY=y
 CONFIG_PHY_SANDBOX=y
 CONFIG_PINCTRL=y
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 82bb093c56..71643af9c2 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -226,6 +226,39 @@ config NUVOTON_NCT6102D
  disable the legacy UART, the watchdog or other devices
  in the Nuvoton Super IO chips on X86 platforms.
 
+config P2SB
+   bool "Intel Primary-to-Sideband Bus"
+   depends on X86 || SANDBOX
+   help
+ This enables support for the Intel Primary-to-Sideband bus,
+ abbreviated to P2SB. The P2SB is used to access various peripherals
+ such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI
+ space. The space is segmented into different channels and peripherals
+ are accessed by device-specific means within those channels. Devices
+ should be added in the device tree as subnodes of the P2SB. A
+ Peripheral Channel Register? (PCR) API is provided to access those
+ devices - see pcr_readl(), etc.
+
+config SPL_P2SB
+   bool "Intel Primary-to-Sideband Bus in SPL"
+   depends on SPL && (X86 || SANDBOX)
+   help
+ The Primary-to-Sideband bus is used to access various peripherals
+ through memory-mapped I/O in a large chunk of PCI space. The space is
+ segmented into different channels and peripherals are accessed by
+ device-specific means within those channels. Devices should be added
+ in the device tree as subnodes of the p2sb.
+
+config TPL_P2SB
+   bool "Intel Primary-to-Sideband Bus in TPL"
+   depends on TPL && (X86 || SANDBOX)
+   help
+ The Primary-to-Sideband bus is used to access various peripherals
+ through memory-mapped I/O in a large chunk of PCI space. The space is
+ segmented into different channels and peripherals are accessed by
+ device-specific means within those channels. Devices should be added
+ in the device tree as subnodes of the p2sb.
+
 config PWRSEQ
bool "Enable power-sequencing drivers"
depends on DM
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 55976d6be5..78b598b367 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -49,6 +49,7 @@ obj-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o
 obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o
 obj-$(CONFIG_NS87308) += ns87308.o
 obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o
+obj-$(CONFIG_P2SB) += p2sb-uclass.o
 obj-$(CONFIG_PCA9551_LED) += pca9551_led.o
 obj-$(CONFIG_$(SPL_)PWRSEQ) += pwrseq-uclass.o
 obj-$(CONFIG_QFW) += qfw.o
diff --git a/drivers/misc/p2sb-uclass.c b/drivers/misc/p2sb-uclass.c
new file mode 100644
index 00..a198700b5f
--- /dev/null
+++ b/drivers/misc/p2sb-uclass.c
@@ -0,0 +1,216 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Uclass for Primary-to-sideband bus, used to access various peripherals
+ *
+ * Copyright 2019 Google LLC
+ * Written by Simon Glass 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define PCR_COMMON_IOSF_1_01
+
+static void *_pcr_reg_address(struct udevice *dev, uint offset)
+{
+   struct p2sb_child_platdata *pplat = dev_get_parent_platdata(dev);
+   struct udevice *p2sb = dev_get_parent(dev);
+   struct p2sb_uc_priv *upriv = dev_get_uclass_priv(p2s

[U-Boot] [PATCH v5 026/101] sandbox: Add a test for IRQ

2019-11-24 Thread Simon Glass
Add a simple sandbox test for this uclass.

Signed-off-by: Simon Glass 
---

Changes in v5: None
Changes in v4:
- Drop itss uclass change in Makefile (now in previous patch)
- Drop sandbox defconfig change now that p2sb change is correct
- Enable IRQ for sandbox64 too to avoid build error

Changes in v3:
- Change the sandbox test from ITSS to IRQ

Changes in v2: None

 arch/sandbox/dts/test.dts  |  4 +++
 configs/sandbox64_defconfig|  1 +
 configs/sandbox_flattree_defconfig |  1 +
 configs/sandbox_spl_defconfig  |  1 +
 drivers/misc/Makefile  |  1 +
 drivers/misc/irq_sandbox.c | 55 ++
 test/dm/Makefile   |  1 +
 test/dm/irq.c  | 32 +
 8 files changed, 96 insertions(+)
 create mode 100644 drivers/misc/irq_sandbox.c
 create mode 100644 test/dm/irq.c

diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 9c8c4e2709..57513a449f 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -353,6 +353,10 @@
vss-microvolts = <0>;
};
 
+   irq {
+   compatible = "sandbox,irq";
+   };
+
lcd {
u-boot,dm-pre-reloc;
compatible = "sandbox,lcd-sdl";
diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig
index 229e268972..5b85818eff 100644
--- a/configs/sandbox64_defconfig
+++ b/configs/sandbox64_defconfig
@@ -114,6 +114,7 @@ CONFIG_CROS_EC_I2C=y
 CONFIG_CROS_EC_LPC=y
 CONFIG_CROS_EC_SANDBOX=y
 CONFIG_CROS_EC_SPI=y
+CONFIG_IRQ=y
 CONFIG_PWRSEQ=y
 CONFIG_SPL_PWRSEQ=y
 CONFIG_I2C_EEPROM=y
diff --git a/configs/sandbox_flattree_defconfig 
b/configs/sandbox_flattree_defconfig
index ab4d26d012..7a7731120f 100644
--- a/configs/sandbox_flattree_defconfig
+++ b/configs/sandbox_flattree_defconfig
@@ -100,6 +100,7 @@ CONFIG_CROS_EC_I2C=y
 CONFIG_CROS_EC_LPC=y
 CONFIG_CROS_EC_SANDBOX=y
 CONFIG_CROS_EC_SPI=y
+CONFIG_IRQ=y
 CONFIG_PWRSEQ=y
 CONFIG_SPL_PWRSEQ=y
 CONFIG_I2C_EEPROM=y
diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig
index 0dea858eda..90c0f22ad3 100644
--- a/configs/sandbox_spl_defconfig
+++ b/configs/sandbox_spl_defconfig
@@ -120,6 +120,7 @@ CONFIG_CROS_EC_I2C=y
 CONFIG_CROS_EC_LPC=y
 CONFIG_CROS_EC_SANDBOX=y
 CONFIG_CROS_EC_SPI=y
+CONFIG_IRQ=y
 CONFIG_PWRSEQ=y
 CONFIG_SPL_PWRSEQ=y
 CONFIG_MMC_SANDBOX=y
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 28313e4a65..d4e8638dea 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_GDSYS_IOEP) += gdsys_ioep.o
 obj-$(CONFIG_GDSYS_RXAUI_CTRL) += gdsys_rxaui_ctrl.o
 obj-$(CONFIG_GDSYS_SOC) += gdsys_soc.o
 obj-$(CONFIG_IRQ) += irq-uclass.o
+obj-$(CONFIG_SANDBOX) += irq_sandbox.o
 obj-$(CONFIG_$(SPL_)I2C_EEPROM) += i2c_eeprom.o
 obj-$(CONFIG_IHS_FPGA) += ihs_fpga.o
 obj-$(CONFIG_IMX8) += imx8/
diff --git a/drivers/misc/irq_sandbox.c b/drivers/misc/irq_sandbox.c
new file mode 100644
index 00..6dda1a4c44
--- /dev/null
+++ b/drivers/misc/irq_sandbox.c
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Sandbox driver for interrupts
+ *
+ * Copyright 2019 Google LLC
+ */
+
+#include 
+#include 
+#include 
+
+static int sandbox_set_polarity(struct udevice *dev, uint irq, bool active_low)
+{
+   if (irq > 10)
+   return -EINVAL;
+
+   return 0;
+}
+
+static int sandbox_route_pmc_gpio_gpe(struct udevice *dev, uint pmc_gpe_num)
+{
+   if (pmc_gpe_num > 10)
+   return -ENOENT;
+
+   return pmc_gpe_num + 1;
+}
+
+static int sandbox_snapshot_polarities(struct udevice *dev)
+{
+   return 0;
+}
+
+static int sandbox_restore_polarities(struct udevice *dev)
+{
+   return 0;
+}
+
+static const struct irq_ops sandbox_irq_ops = {
+   .route_pmc_gpio_gpe = sandbox_route_pmc_gpio_gpe,
+   .set_polarity   = sandbox_set_polarity,
+   .snapshot_polarities= sandbox_snapshot_polarities,
+   .restore_polarities = sandbox_restore_polarities,
+};
+
+static const struct udevice_id sandbox_irq_ids[] = {
+   { .compatible = "sandbox,irq"},
+   { }
+};
+
+U_BOOT_DRIVER(sandbox_irq_drv) = {
+   .name   = "sandbox_irq",
+   .id = UCLASS_IRQ,
+   .of_match   = sandbox_irq_ids,
+   .ops= &sandbox_irq_ops,
+};
diff --git a/test/dm/Makefile b/test/dm/Makefile
index 129ccb3b49..a268783169 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_DM_GPIO) += gpio.o
 obj-$(CONFIG_DM_HWSPINLOCK) += hwspinlock.o
 obj-$(CONFIG_DM_I2C) += i2c.o
 obj-$(CONFIG_SOUND) += i2s.o
+obj-y += irq.o
 obj-$(CONFIG_LED) += led.o
 obj-$(CONFIG_DM_MAILBOX) += mailbox.o
 obj-$(CONFIG_DM_MMC) += mmc.o
diff --git a/test/dm/irq.c b/test/dm/irq.c
new file mode 100644
index 00..726189c59f
--- /dev/null
+++ b/test/dm/irq.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Test for irq uclass
+ *
+ * Copyright 2019

[U-Boot] [PATCH v5 023/101] sandbox: Disable mmio by default in tests

2019-11-24 Thread Simon Glass
When reseting sandbox for tests, disable mmio support since that is the
default state.

Signed-off-by: Simon Glass 
---

Changes in v5: None
Changes in v4:
- Split out into a separate patch

Changes in v3: None
Changes in v2: None

 arch/sandbox/cpu/state.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c
index dee5fde4f7..cd46e000f5 100644
--- a/arch/sandbox/cpu/state.c
+++ b/arch/sandbox/cpu/state.c
@@ -356,6 +356,7 @@ void state_reset_for_test(struct sandbox_state *state)
/* No reset yet, so mark it as such. Always allow power reset */
state->last_sysreset = SYSRESET_COUNT;
state->sysreset_allowed[SYSRESET_POWER_OFF] = true;
+   state->allow_memio = false;
 
memset(&state->wdt, '\0', sizeof(state->wdt));
memset(state->spi, '\0', sizeof(state->spi));
-- 
2.24.0.432.g9d3f5f5b63-goog

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[U-Boot] [PATCH v5 045/101] x86: fsp: Add FSP2 base support

2019-11-24 Thread Simon Glass
Add support for some important configuration options and FSP memory init.
The memory init uses swizzle tables from the device tree.

Support for the FSP_S binary is also included.

Bootstage timing is used for both FSP_M and FSP_S and memory-mapped SPI
reads.

Signed-off-by: Simon Glass 
---

Changes in v5:
- Drop SAFETY_MARGIN

Changes in v4:
- Add a LOG_CATEGORY for silicon init
- Drop duplicate VBT file CONFIG
- Enable HAVE_VBT for FSP2 also
- Explain the 'twisty headers' comment
- Fix FSP_M reference to refer to FSP_S in commit message
- Fix comment on fsp_silicon_init()
- Rename arch_fsp_s_preinit() to arch_fsps_preinit()
- Rename get_coreboot_fsp() and add comments
- Switch over to use pinctrl for pad init/config
- Use lower-case pinctrl in arch_cpu_init_dm()

Changes in v3:
- Add a proper implementation of fsp_notify
- Add an fsp: tag
- Add bootstage timing for memory-mapped reads
- Add fsp_locate_fsp to locate an fsp component
- Add fspm_done() hook
- Add support for FSP-S component and VBT
- Simplify types for fsp_locate_fsp()
- Switch mmap to use SPI instead of SPI flash

Changes in v2: None

 arch/x86/Kconfig |  54 ++-
 arch/x86/include/asm/fsp2/fsp_api.h  |  63 
 arch/x86/include/asm/fsp2/fsp_internal.h |  97 +
 arch/x86/lib/fsp2/Makefile   |  10 ++
 arch/x86/lib/fsp2/fsp_common.c   |  13 ++
 arch/x86/lib/fsp2/fsp_dram.c |  77 ++
 arch/x86/lib/fsp2/fsp_init.c | 174 +++
 arch/x86/lib/fsp2/fsp_meminit.c  |  97 +
 arch/x86/lib/fsp2/fsp_silicon_init.c |  54 +++
 arch/x86/lib/fsp2/fsp_support.c  | 131 +
 include/bootstage.h  |   3 +
 11 files changed, 770 insertions(+), 3 deletions(-)
 create mode 100644 arch/x86/include/asm/fsp2/fsp_api.h
 create mode 100644 arch/x86/include/asm/fsp2/fsp_internal.h
 create mode 100644 arch/x86/lib/fsp2/Makefile
 create mode 100644 arch/x86/lib/fsp2/fsp_common.c
 create mode 100644 arch/x86/lib/fsp2/fsp_dram.c
 create mode 100644 arch/x86/lib/fsp2/fsp_init.c
 create mode 100644 arch/x86/lib/fsp2/fsp_meminit.c
 create mode 100644 arch/x86/lib/fsp2/fsp_silicon_init.c
 create mode 100644 arch/x86/lib/fsp2/fsp_support.c

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 17a6fe6d3d..6bac5d5fe8 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -326,7 +326,7 @@ config X86_RAMTEST
 
 config FLASH_DESCRIPTOR_FILE
string "Flash descriptor binary filename"
-   depends on HAVE_INTEL_ME
+   depends on HAVE_INTEL_ME || FSP_VERSION2
default "descriptor.bin"
help
  The filename of the file to use as flash descriptor in the
@@ -411,6 +411,54 @@ config FSP_ADDR
  The default base address of 0xfffc indicates that the binary must
  be located at offset 0xc from the beginning of a 1MB flash device.
 
+if FSP_VERSION2
+
+config FSP_FILE_T
+   string "Firmware-Support-Package binary filename (Temp RAM)"
+   default "fsp_t.bin"
+   help
+ The filename of the file to use for the temporary-RAM init phase from
+ the Firmware-Support-Package binary. Put this in the board directory.
+ It is used to set up an initial area of RAM which can be used for the
+ stack and other purposes, while bringing up the main system DRAM.
+
+config FSP_ADDR_T
+   hex "Firmware-Support-Package binary location (Temp RAM)"
+   default 0x8000
+   help
+ FSP is not Position-Independent Code (PIC) and FSP components have to
+ be rebased if placed at a location which is different from the
+ perferred base address specified during the FSP build. Use Intel's
+ Binary Configuration Tool (BCT) to do the rebase.
+
+config FSP_FILE_M
+   string "Firmware-Support-Package binary filename (Memory Init)"
+   default "fsp_m.bin"
+   help
+ The filename of the file to use for the RAM init phase from the
+ Firmware Support Package binary. Put this in the board directory.
+ It is used to set up the main system DRAM and runs in SPL, once
+ temporary RAM (CAR) is working.
+
+config FSP_FILE_S
+   string "Firmware-Support-Package binary filename (Silicon Init)"
+   default "fsp_s.bin"
+   help
+ The filename of the file to use for the Silicon init phase from the
+ Firmware Support Package binary. Put this in the board directory.
+ It is used to set up the silicon to work correctly and must be
+ executed after DRAM is running.
+
+config IFWI_INPUT_FILE
+   string "Filename containing FIT (Firmware Interface Table) with IFWI"
+   default "fitimage.bin"
+   help
+ The IFWI is obtained by running a tool on this file to extract the
+ IFWI. Put this in the board directory. The IFWI contains U-Boot TPL,
+ microcode and other internal items.
+
+endif
+
 config FSP_TE

[U-Boot] [PATCH v5 037/101] x86: Move fsp_prepare_mrc_cache() to fsp1 directory

2019-11-24 Thread Simon Glass
This function needs to be different for FSP2, so move the existing
function into the fsp1 directory. Since it is only called from one file,
drop it from the header file.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/x86/include/asm/fsp/fsp_support.h |  7 ---
 arch/x86/lib/fsp/fsp_common.c  | 20 
 arch/x86/lib/fsp1/fsp_common.c | 20 
 3 files changed, 20 insertions(+), 27 deletions(-)

diff --git a/arch/x86/include/asm/fsp/fsp_support.h 
b/arch/x86/include/asm/fsp/fsp_support.h
index 4ac27d26f5..29e511415c 100644
--- a/arch/x86/include/asm/fsp/fsp_support.h
+++ b/arch/x86/include/asm/fsp/fsp_support.h
@@ -143,13 +143,6 @@ int fsp_init_phase_pci(void);
  */
 int fsp_scan_for_ram_size(void);
 
-/**
- * fsp_prepare_mrc_cache() - Find the DRAM training data from the MRC cache
- *
- * @return pointer to data, or NULL if no cache or no data found in the cache
- */
-void *fsp_prepare_mrc_cache(void);
-
 /**
  * fsp_notify() - FSP notification wrapper function
  *
diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c
index c1c30ce0eb..6b7a614e92 100644
--- a/arch/x86/lib/fsp/fsp_common.c
+++ b/arch/x86/lib/fsp/fsp_common.c
@@ -57,26 +57,6 @@ void board_final_cleanup(void)
debug("OK\n");
 }
 
-void *fsp_prepare_mrc_cache(void)
-{
-   struct mrc_data_container *cache;
-   struct mrc_region entry;
-   int ret;
-
-   ret = mrccache_get_region(MRC_TYPE_NORMAL, NULL, &entry);
-   if (ret)
-   return NULL;
-
-   cache = mrccache_find_current(&entry);
-   if (!cache)
-   return NULL;
-
-   debug("%s: mrc cache at %p, size %x checksum %04x\n", __func__,
- cache->data, cache->data_size, cache->checksum);
-
-   return cache->data;
-}
-
 #ifdef CONFIG_HAVE_ACPI_RESUME
 int fsp_save_s3_stack(void)
 {
diff --git a/arch/x86/lib/fsp1/fsp_common.c b/arch/x86/lib/fsp1/fsp_common.c
index e8066d8de3..ec9c218778 100644
--- a/arch/x86/lib/fsp1/fsp_common.c
+++ b/arch/x86/lib/fsp1/fsp_common.c
@@ -18,6 +18,26 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static void *fsp_prepare_mrc_cache(void)
+{
+   struct mrc_data_container *cache;
+   struct mrc_region entry;
+   int ret;
+
+   ret = mrccache_get_region(MRC_TYPE_NORMAL, NULL, &entry);
+   if (ret)
+   return NULL;
+
+   cache = mrccache_find_current(&entry);
+   if (!cache)
+   return NULL;
+
+   debug("%s: mrc cache at %p, size %x checksum %04x\n", __func__,
+ cache->data, cache->data_size, cache->checksum);
+
+   return cache->data;
+}
+
 int arch_fsp_init(void)
 {
void *nvs;
-- 
2.24.0.432.g9d3f5f5b63-goog

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[U-Boot] [PATCH v5 030/101] x86: Adjust mrccache_get_region() to use livetree

2019-11-24 Thread Simon Glass
Change the algorithm to first find the flash device then read the
properties using the livetree API. With this change the device is not
probed so this needs to be done in mrccache_save().

Signed-off-by: Simon Glass 
---

Changes in v5: None
Changes in v4: None
Changes in v3:
- Update mrccache livetree patch to just convert to livetree

Changes in v2: None

 arch/x86/lib/mrccache.c | 55 +++--
 1 file changed, 26 insertions(+), 29 deletions(-)

diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c
index 9d56685d36..50c72bf962 100644
--- a/arch/x86/lib/mrccache.c
+++ b/arch/x86/lib/mrccache.c
@@ -14,6 +14,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -206,45 +208,37 @@ int mrccache_reserve(void)
 
 int mrccache_get_region(struct udevice **devp, struct mrc_region *entry)
 {
-   const void *blob = gd->fdt_blob;
-   int node, mrc_node;
+   struct udevice *dev;
+   ofnode mrc_node;
u32 reg[2];
int ret;
 
-   /* Find the flash chip within the SPI controller node */
-   node = fdtdec_next_compatible(blob, 0, COMPAT_GENERIC_SPI_FLASH);
-   if (node < 0) {
-   debug("%s: Cannot find SPI flash\n", __func__);
-   return -ENOENT;
-   }
-
-   if (fdtdec_get_int_array(blob, node, "memory-map", reg, 2)) {
-   debug("%s: Cannot find memory map\n", __func__);
-   return -EINVAL;
-   }
+   /*
+* Find the flash chip within the SPI controller node. Avoid probing
+* the device here since it may put it into a strange state where the
+* memory map cannot be read.
+*/
+   ret = uclass_find_first_device(UCLASS_SPI_FLASH, &dev);
+   if (ret)
+   return log_msg_ret("Cannot find SPI flash\n", ret);
+   ret = dev_read_u32_array(dev, "memory-map", reg, 2);
+   if (ret)
+   return log_msg_ret("Cannot find memory map\n", ret);
entry->base = reg[0];
 
/* Find the place where we put the MRC cache */
-   mrc_node = fdt_subnode_offset(blob, node, "rw-mrc-cache");
-   if (mrc_node < 0) {
-   debug("%s: Cannot find node\n", __func__);
-   return -EPERM;
-   }
+   mrc_node = dev_read_subnode(dev, "rw-mrc-cache");
+   if (!ofnode_valid(mrc_node))
+   return log_msg_ret("Cannot find node", -EPERM);
 
-   if (fdtdec_get_int_array(blob, mrc_node, "reg", reg, 2)) {
-   debug("%s: Cannot find address\n", __func__);
-   return -EINVAL;
-   }
+   ret = ofnode_read_u32_array(mrc_node, "reg", reg, 2);
+   if (ret)
+   return log_msg_ret("Cannot find address", ret);
entry->offset = reg[0];
entry->length = reg[1];
 
-   if (devp) {
-   ret = uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node,
-devp);
-   debug("ret = %d\n", ret);
-   if (ret)
-   return ret;
-   }
+   if (devp)
+   *devp = dev;
 
return 0;
 }
@@ -262,6 +256,9 @@ int mrccache_save(void)
  gd->arch.mrc_output_len);
 
ret = mrccache_get_region(&sf, &entry);
+   if (ret)
+   goto err_entry;
+   ret = device_probe(sf);
if (ret)
goto err_entry;
data  = (struct mrc_data_container *)gd->arch.mrc_output;
-- 
2.24.0.432.g9d3f5f5b63-goog

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[U-Boot] [PATCH v5 008/101] i2c: designware: Avoid using static data

2019-11-24 Thread Simon Glass
Drivers are not allowed to use static data since they may be used in SPL
where BSS is not available.

It is possible that driver model may provide support for numbering devices
in the future. But for now, move this to global_data.

Signed-off-by: Simon Glass 
---

Changes in v5: None
Changes in v4:
- Add new patch to drop static data in designware i2c driver

Changes in v3: None
Changes in v2: None

 arch/x86/include/asm/global_data.h | 1 +
 drivers/i2c/designware_i2c_pci.c   | 9 ++---
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/x86/include/asm/global_data.h 
b/arch/x86/include/asm/global_data.h
index 7f3ada06f6..0e7b946205 100644
--- a/arch/x86/include/asm/global_data.h
+++ b/arch/x86/include/asm/global_data.h
@@ -96,6 +96,7 @@ struct arch_global_data {
ulong table;/* Table pointer from previous loader */
int turbo_state;/* Current turbo state */
struct irq_routing_table *pirq_routing_table;
+   int dw_i2c_num_cards;   /* Used by designware i2c driver */
 #ifdef CONFIG_SEABIOS
u32 high_table_ptr;
u32 high_table_limit;
diff --git a/drivers/i2c/designware_i2c_pci.c b/drivers/i2c/designware_i2c_pci.c
index e8fc6f2a90..8d6bb37f5c 100644
--- a/drivers/i2c/designware_i2c_pci.c
+++ b/drivers/i2c/designware_i2c_pci.c
@@ -34,7 +34,6 @@ static int designware_i2c_pci_probe(struct udevice *dev)
 
 static int designware_i2c_pci_bind(struct udevice *dev)
 {
-   static int num_cards;
char name[20];
 
/*
@@ -45,9 +44,13 @@ static int designware_i2c_pci_bind(struct udevice *dev)
 * using this driver is impossible for PCIe I2C devices.
 * This can be removed, once a better (correct) way for this
 * is found and implemented.
+*
+* TODO(s...@chromium.org): Perhaps if uclasses had platdata this would
+* be possible. We cannot use static data in drivers since they may be
+* used in SPL or before relocation.
 */
-   dev->req_seq = num_cards;
-   sprintf(name, "i2c_designware#%u", num_cards++);
+   dev->req_seq = gd->arch.dw_i2c_num_cards++;
+   sprintf(name, "i2c_designware#%u", dev->req_seq);
device_set_name(dev, name);
 
return 0;
-- 
2.24.0.432.g9d3f5f5b63-goog

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[U-Boot] [PATCH v5 046/101] x86: fsp: Set up an MTRR for the graphics frame buffer

2019-11-24 Thread Simon Glass
The FSP-S may do this but at least for coral it does not. Set this up so
that graphics is not deathly slow.

It isn't clear whether the FSP is expected to set up MTRR. It is not
mentioned in the APL FSP document.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/x86/lib/fsp/fsp_graphics.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/x86/lib/fsp/fsp_graphics.c b/arch/x86/lib/fsp/fsp_graphics.c
index 91d2d08557..226c7e66b3 100644
--- a/arch/x86/lib/fsp/fsp_graphics.c
+++ b/arch/x86/lib/fsp/fsp_graphics.c
@@ -8,6 +8,7 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -97,6 +98,9 @@ static int fsp_video_probe(struct udevice *dev)
if (ret)
goto err;
 
+   mtrr_add_request(MTRR_TYPE_WRCOMB, vesa->phys_base_ptr, 256 << 20);
+   mtrr_commit(true);
+
printf("%dx%dx%d\n", uc_priv->xsize, uc_priv->ysize,
   vesa->bits_per_pixel);
 
-- 
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[U-Boot] [PATCH v5 089/101] x86: apl: Add hostbridge driver

2019-11-24 Thread Simon Glass
This driver models the hostbridge as a northbridge. It simply sets up the
graphics BAR. It supports of-platdata.

Signed-off-by: Simon Glass 
---

Changes in v5: None
Changes in v4:
- Avoid needing to know internals of pinctrl in this driver
- Move code to pinctrl driver
- Switch over to use pinctrl for pad init/config

Changes in v3:
- Move pad programming into the hostbridge to reduce TPL device-tree size
- Use pci_get_devfn()

Changes in v2: None

 arch/x86/cpu/apollolake/Makefile |   1 +
 arch/x86/cpu/apollolake/hostbridge.c | 179 +++
 2 files changed, 180 insertions(+)
 create mode 100644 arch/x86/cpu/apollolake/hostbridge.c

diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile
index 3a8c2f66a3..4d3c08f84e 100644
--- a/arch/x86/cpu/apollolake/Makefile
+++ b/arch/x86/cpu/apollolake/Makefile
@@ -4,5 +4,6 @@
 
 obj-$(CONFIG_SPL_BUILD) += systemagent.o
 
+obj-y += hostbridge.o
 obj-y += pmc.o
 obj-y += uart.o
diff --git a/arch/x86/cpu/apollolake/hostbridge.c 
b/arch/x86/cpu/apollolake/hostbridge.c
new file mode 100644
index 00..25fb51dd9a
--- /dev/null
+++ b/arch/x86/cpu/apollolake/hostbridge.c
@@ -0,0 +1,179 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+ * struct apl_hostbridge_platdata - platform data for hostbridge
+ *
+ * @num_cfgs: Number of configuration words for each pad
+ * @early_pads: Early pad data to set up, each (pad, cfg0, cfg1)
+ * @early_pads_count: Number of pads to process
+ * @pciex_region_size: BAR length in bytes
+ * @bdf: Bus/device/function of hostbridge
+ */
+struct apl_hostbridge_platdata {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+   struct dtd_intel_apl_hostbridge dtplat;
+#endif
+   u32 *early_pads;
+   int early_pads_count;
+   uint pciex_region_size;
+   pci_dev_t bdf;
+};
+
+enum {
+   PCIEXBAR= 0x60,
+   PCIEXBAR_LENGTH_256MB   = 0,
+   PCIEXBAR_LENGTH_128MB,
+   PCIEXBAR_LENGTH_64MB,
+
+   PCIEXBAR_PCIEXBAREN = 1 << 0,
+
+   TSEG= 0xb8,  /* TSEG base */
+};
+
+static int apl_hostbridge_early_init_pinctrl(struct udevice *dev)
+{
+   struct apl_hostbridge_platdata *plat = dev_get_platdata(dev);
+   struct udevice *pinctrl;
+   int ret;
+
+   ret = uclass_first_device_err(UCLASS_PINCTRL, &pinctrl);
+   if (ret)
+   return log_msg_ret("no hostbridge pinctrl", ret);
+
+   return pinctrl_config_pads(pinctrl, plat->early_pads,
+  plat->early_pads_count);
+}
+
+static int apl_hostbridge_early_init(struct udevice *dev)
+{
+   struct apl_hostbridge_platdata *plat = dev_get_platdata(dev);
+   u32 region_size;
+   ulong base;
+   u32 reg;
+   int ret;
+
+   /* Set up the MCHBAR */
+   pci_x86_read_config(plat->bdf, MCHBAR, &base, PCI_SIZE_32);
+   base = MCH_BASE_ADDRESS;
+   pci_x86_write_config(plat->bdf, MCHBAR, base | 1, PCI_SIZE_32);
+
+   /*
+* The PCIEXBAR is assumed to live in the memory mapped IO space under
+* 4GiB
+*/
+   pci_x86_write_config(plat->bdf, PCIEXBAR + 4, 0, PCI_SIZE_32);
+
+   switch (plat->pciex_region_size >> 20) {
+   default:
+   case 256:
+   region_size = PCIEXBAR_LENGTH_256MB;
+   break;
+   case 128:
+   region_size = PCIEXBAR_LENGTH_128MB;
+   break;
+   case 64:
+   region_size = PCIEXBAR_LENGTH_64MB;
+   break;
+   }
+
+   reg = CONFIG_MMCONF_BASE_ADDRESS | (region_size << 1)
+   | PCIEXBAR_PCIEXBAREN;
+   pci_x86_write_config(plat->bdf, PCIEXBAR, reg, PCI_SIZE_32);
+
+   /*
+* TSEG defines the base of SMM range. BIOS determines the base
+* of TSEG memory which must be at or below Graphics base of GTT
+* Stolen memory, hence its better to clear TSEG register early
+* to avoid power on default non-zero value (if any).
+*/
+   pci_x86_write_config(plat->bdf, TSEG, 0, PCI_SIZE_32);
+
+   ret = apl_hostbridge_early_init_pinctrl(dev);
+   if (ret)
+   return log_msg_ret("pinctrl", ret);
+
+   return 0;
+}
+
+static int apl_hostbridge_ofdata_to_platdata(struct udevice *dev)
+{
+   struct apl_hostbridge_platdata *plat = dev_get_platdata(dev);
+   struct udevice *pinctrl;
+   int ret;
+
+   /*
+* The host bridge holds the early pad data needed to get through TPL.
+* This is a small amount of data, enough to fit in TPL, so we keep it
+* separate from the full pad data, stored in the fsp-s subnode. That
+* subnode is not present in TPL, to save space.
+*/
+   ret = uclass_first_device_err(UCLASS_PINCTRL, &pinctrl);
+   if (ret)
+   return log_msg_ret("no hostbridge PINCTRL", ret);
+

[U-Boot] [PATCH v5 054/101] x86: Update the fsp command for FSP2

2019-11-24 Thread Simon Glass
The current 'fsp' command only works with FSP1. Update it to handle FSP2
as well. Convert everything to hex which is what U-Boot uses.

Signed-off-by: Simon Glass 
---

Changes in v5: None
Changes in v4:
- Explain why FSP-M cannot be shown
- Use hex for size values also

Changes in v3:
- Convert code to use hex increased of decimal
- Update the 'fsp' command for FSP2, instead of disabling it

Changes in v2: None

 cmd/x86/fsp.c | 65 ++-
 1 file changed, 44 insertions(+), 21 deletions(-)

diff --git a/cmd/x86/fsp.c b/cmd/x86/fsp.c
index b3b663021b..6e485fb144 100644
--- a/cmd/x86/fsp.c
+++ b/cmd/x86/fsp.c
@@ -5,23 +5,38 @@
 
 #include 
 #include 
-#include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
 static int do_hdr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-   struct fsp_header *hdr = fsp_find_header();
-   u32 img_addr = hdr->img_base;
-   char *sign = (char *)&hdr->sign;
+   struct fsp_header *hdr;
+   u32 img_addr;
+   char *sign;
+   uint addr;
int i;
 
-   printf("FSP: binary 0x%08x, header 0x%08x\n",
-  CONFIG_FSP_ADDR, (int)hdr);
+#ifdef CONFIG_FSP_VERSION2
+   /*
+* Only FSP-S is displayed. FSP-M was used in SPL but may not still be
+* around, and we didn't keep a pointer to it.
+*/
+   hdr = gd->arch.fsp_s_hdr;
+   img_addr = hdr->img_base;
+   addr = img_addr;
+#else
+   addr = CONFIG_FSP_ADDR;
+   hdr = fsp_find_header();
+   img_addr = hdr->img_base;
+#endif
+   sign = (char *)&hdr->sign;
+
+   printf("FSP: binary %08x, header %08x\n", addr, (int)hdr);
printf("Header : sign ");
for (i = 0; i < sizeof(hdr->sign); i++)
printf("%c", *sign++);
-   printf(", size %d, rev %d\n", hdr->hdr_len, hdr->hdr_rev);
+   printf(", size %x, rev %d\n", hdr->hdr_len, hdr->hdr_rev);
printf("Image  : rev ");
if (hdr->hdr_rev == FSP_HEADER_REVISION_1) {
printf("%d.%d",
@@ -34,24 +49,32 @@ static int do_hdr(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
printf(", id ");
for (i = 0; i < ARRAY_SIZE(hdr->img_id); i++)
printf("%c", hdr->img_id[i]);
-   printf(", addr 0x%08x, size %d\n", img_addr, hdr->img_size);
-   if (hdr->hdr_rev == FSP_HEADER_REVISION_2) {
+   printf(", addr %08x, size %x\n", img_addr, hdr->img_size);
+   if (hdr->hdr_rev >= FSP_HEADER_REVISION_1) {
printf("GFX:%ssupported\n",
   hdr->img_attr & FSP_ATTR_GRAPHICS_SUPPORT ? " " : " un");
}
-   printf("VPD: addr 0x%08x, size %d\n",
+   printf("VPD: addr %08x, size %x\n",
   hdr->cfg_region_off + img_addr, hdr->cfg_region_size);
-   printf("\nNumber of APIs Supported : %d\n", hdr->api_num);
-   printf("\tTempRamInit : 0x%08x\n", hdr->fsp_tempram_init + img_addr);
-   printf("\tFspInit : 0x%08x\n", hdr->fsp_init + img_addr);
-   printf("\tFspNotify   : 0x%08x\n", hdr->fsp_notify + img_addr);
-   if (hdr->hdr_rev == FSP_HEADER_REVISION_2) {
-   printf("\tMemoryInit  : 0x%08x\n",
-  hdr->fsp_mem_init + img_addr);
-   printf("\tTempRamExit : 0x%08x\n",
-  hdr->fsp_tempram_exit + img_addr);
-   printf("\tSiliconInit : 0x%08x\n",
-  hdr->fsp_silicon_init + img_addr);
+   if (hdr->hdr_rev <= FSP_HEADER_REVISION_2)
+   printf("\nNumber of APIs Supported : %d\n", hdr->api_num);
+   if (hdr->fsp_tempram_init)
+   printf("\tTempRamInit : %08x\n",
+  hdr->fsp_tempram_init + img_addr);
+   if (hdr->fsp_init)
+   printf("\tFspInit : %08x\n", hdr->fsp_init + img_addr);
+   if (hdr->fsp_notify)
+   printf("\tFspNotify   : %08x\n", hdr->fsp_notify + img_addr);
+   if (hdr->hdr_rev >= FSP_HEADER_REVISION_1) {
+   if (hdr->fsp_mem_init)
+   printf("\tMemoryInit  : %08x\n",
+  hdr->fsp_mem_init + img_addr);
+   if (hdr->fsp_tempram_exit)
+   printf("\tTempRamExit : %08x\n",
+  hdr->fsp_tempram_exit + img_addr);
+   if (hdr->fsp_silicon_init)
+   printf("\tSiliconInit : %08x\n",
+  hdr->fsp_silicon_init + img_addr);
}
 
return 0;
-- 
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[U-Boot] [PATCH v5 040/101] x86: Don't imply libfdt or SPI flash in TPL

2019-11-24 Thread Simon Glass
We don't want to pull in libfdt if of-platdata is being used, since it
reduces the available code-size saves. Also, SPI flash is seldom needed
in TPL.

Drop these options.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v5: None
Changes in v4: None
Changes in v3:
- Don't imply SPI flash either
- Rewrite commit message

Changes in v2: None

 arch/Kconfig | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/arch/Kconfig b/arch/Kconfig
index 6865e1f909..54de91afb3 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -204,14 +204,11 @@ config X86
imply SPL_SYSCON
# TPL
imply TPL_DM
-   imply TPL_OF_LIBFDT
imply TPL_DRIVERS_MISC_SUPPORT
imply TPL_GPIO_SUPPORT
imply TPL_LIBCOMMON_SUPPORT
imply TPL_LIBGENERIC_SUPPORT
imply TPL_SERIAL_SUPPORT
-   imply TPL_SPI_FLASH_SUPPORT
-   imply TPL_SPI_SUPPORT
imply TPL_OF_CONTROL
imply TPL_TIMER
imply TPL_REGMAP
-- 
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[U-Boot] [PATCH v5 038/101] x86: Set the DRAM banks to reflect real location

2019-11-24 Thread Simon Glass
At present with fsp a single DRAM bank is added which extends to the
whole size of memory. However there is typically only 2GB of memory
available below the 4GB boundary, and this is what is used by U-Boot while
running in 32-bit mode.

Scan the tables to set the banks correct. The first bank is set to memory
below 4GB, and the rest of memory is put into subsequent banks.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v5: None
Changes in v4: None
Changes in v3:
- Move mtrr_add_request() call to next patch

Changes in v2: None

 arch/x86/lib/fsp/fsp_dram.c | 30 +-
 1 file changed, 29 insertions(+), 1 deletion(-)

diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c
index 2d1023068f..3ede9b73fe 100644
--- a/arch/x86/lib/fsp/fsp_dram.c
+++ b/arch/x86/lib/fsp/fsp_dram.c
@@ -37,8 +37,36 @@ int fsp_scan_for_ram_size(void)
 
 int dram_init_banksize(void)
 {
+   const struct hob_header *hdr;
+   struct hob_res_desc *res_desc;
+   phys_addr_t low_end;
+   uint bank;
+
+   low_end = 0;
+   for (bank = 1, hdr = gd->arch.hob_list;
+bank < CONFIG_NR_DRAM_BANKS && !end_of_hob(hdr);
+hdr = get_next_hob(hdr)) {
+   if (hdr->type != HOB_TYPE_RES_DESC)
+   continue;
+   res_desc = (struct hob_res_desc *)hdr;
+   if (res_desc->type != RES_SYS_MEM &&
+   res_desc->type != RES_MEM_RESERVED)
+   continue;
+   if (res_desc->phys_start < (1ULL << 32)) {
+   low_end = max(low_end,
+ res_desc->phys_start + res_desc->len);
+   continue;
+   }
+
+   gd->bd->bi_dram[bank].start = res_desc->phys_start;
+   gd->bd->bi_dram[bank].size = res_desc->len;
+   log_debug("ram %llx %llx\n", gd->bd->bi_dram[bank].start,
+ gd->bd->bi_dram[bank].size);
+   }
+
+   /* Add the memory below 4GB */
gd->bd->bi_dram[0].start = 0;
-   gd->bd->bi_dram[0].size = gd->ram_size;
+   gd->bd->bi_dram[0].size = low_end;
 
return 0;
 }
-- 
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[U-Boot] [PATCH v5 028/101] x86: Reduce mrccache record alignment size

2019-11-24 Thread Simon Glass
At present the records are 4KB in size. This is unnecessarily large when
the SPI-flash erase size is 256 bytes. Reduce it so it will be more
efficient with Apollo Lake's 24-byte variable-data record.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 

---

Changes in v5: None
Changes in v4:
- apollolake -> Apollo Lake

Changes in v3: None
Changes in v2: None

 arch/x86/include/asm/mrccache.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/mrccache.h b/arch/x86/include/asm/mrccache.h
index 40fda856ff..abf5818223 100644
--- a/arch/x86/include/asm/mrccache.h
+++ b/arch/x86/include/asm/mrccache.h
@@ -7,7 +7,7 @@
 #ifndef _ASM_MRCCACHE_H
 #define _ASM_MRCCACHE_H
 
-#define MRC_DATA_ALIGN 0x1000
+#define MRC_DATA_ALIGN 0x100
 #define MRC_DATA_SIGNATURE (('M' << 0) | ('R' << 8) | \
 ('C' << 16) | ('D'<<24))
 
-- 
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[U-Boot] [PATCH v5 039/101] x86: Set up the MTRR for SDRAM

2019-11-24 Thread Simon Glass
Set up MTRRs for the FSP SDRAM regions to improve performance.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v5:
- Fix FST typo

Changes in v4: None
Changes in v3:
- Move mtrr_add_request() call into this patch

Changes in v2: None

 arch/x86/lib/fsp/fsp_dram.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c
index 3ede9b73fe..9ca898a0cd 100644
--- a/arch/x86/lib/fsp/fsp_dram.c
+++ b/arch/x86/lib/fsp/fsp_dram.c
@@ -8,6 +8,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -60,6 +61,8 @@ int dram_init_banksize(void)
 
gd->bd->bi_dram[bank].start = res_desc->phys_start;
gd->bd->bi_dram[bank].size = res_desc->len;
+   mtrr_add_request(MTRR_TYPE_WRBACK, res_desc->phys_start,
+res_desc->len);
log_debug("ram %llx %llx\n", gd->bd->bi_dram[bank].start,
  gd->bd->bi_dram[bank].size);
}
@@ -68,6 +71,8 @@ int dram_init_banksize(void)
gd->bd->bi_dram[0].start = 0;
gd->bd->bi_dram[0].size = low_end;
 
+   mtrr_add_request(MTRR_TYPE_WRBACK, 0, low_end);
+
return 0;
 }
 
-- 
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[U-Boot] [PATCH v5 033/101] x86: Tidy up error handling in mrccache_save()

2019-11-24 Thread Simon Glass
This function is a bit confusing at present due to the error handling.
Update it to remove the goto, returning errors as they happen.

While we are here, use hex for the data size since this is the norm in
U-Boot.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v5: None
Changes in v4: None
Changes in v3:
- Move an additional error handling fix from a future patch

Changes in v2: None

 arch/x86/lib/mrccache.c | 19 +++
 1 file changed, 7 insertions(+), 12 deletions(-)

diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c
index 6e561fe528..712bacd5d2 100644
--- a/arch/x86/lib/mrccache.c
+++ b/arch/x86/lib/mrccache.c
@@ -168,7 +168,7 @@ int mrccache_update(struct udevice *sf, struct mrc_region 
*entry,
 cur);
if (ret) {
debug("Failed to write to SPI flash\n");
-   return ret;
+   return log_msg_ret("Cannot update mrccache", ret);
}
 
return 0;
@@ -261,28 +261,23 @@ int mrccache_save(void)
 
if (!gd->arch.mrc_output_len)
return 0;
-   debug("Saving %d bytes of MRC output data to SPI flash\n",
+   debug("Saving %#x bytes of MRC output data to SPI flash\n",
  gd->arch.mrc_output_len);
 
ret = mrccache_get_region(&sf, &entry);
if (ret)
-   goto err_entry;
+   return log_msg_ret("Cannot get region", ret);
ret = device_probe(sf);
if (ret)
-   goto err_entry;
+   return log_msg_ret("Cannot probe device", ret);
cache = gd->arch.mrc_cache;
ret = mrccache_update(sf, &entry, cache);
-   if (!ret) {
+   if (!ret)
debug("Saved MRC data with checksum %04x\n", cache->checksum);
-   } else if (ret == -EEXIST) {
+   else if (ret == -EEXIST)
debug("MRC data is the same as last time, skipping save\n");
-   ret = 0;
-   }
 
-err_entry:
-   if (ret)
-   debug("%s: Failed: %d\n", __func__, ret);
-   return ret;
+   return 0;
 }
 
 int mrccache_spl_save(void)
-- 
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[U-Boot] [PATCH v5 043/101] x86: fsp: Make graphics support common to FSP1/2

2019-11-24 Thread Simon Glass
Both versions of FSP can use the same graphics support, so move it into
the common directory.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/x86/lib/fsp/Makefile | 3 +++
 arch/x86/lib/{fsp1 => fsp}/fsp_graphics.c | 2 +-
 arch/x86/lib/fsp1/Makefile| 1 -
 3 files changed, 4 insertions(+), 2 deletions(-)
 rename arch/x86/lib/{fsp1 => fsp}/fsp_graphics.c (98%)

diff --git a/arch/x86/lib/fsp/Makefile b/arch/x86/lib/fsp/Makefile
index 9e34856473..da6c0a886a 100644
--- a/arch/x86/lib/fsp/Makefile
+++ b/arch/x86/lib/fsp/Makefile
@@ -4,4 +4,7 @@
 
 obj-y += fsp_common.o
 obj-y += fsp_dram.o
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_VIDEO_FSP) += fsp_graphics.o
+endif
 obj-y += fsp_support.o
diff --git a/arch/x86/lib/fsp1/fsp_graphics.c b/arch/x86/lib/fsp/fsp_graphics.c
similarity index 98%
rename from arch/x86/lib/fsp1/fsp_graphics.c
rename to arch/x86/lib/fsp/fsp_graphics.c
index 52e71334f9..91d2d08557 100644
--- a/arch/x86/lib/fsp1/fsp_graphics.c
+++ b/arch/x86/lib/fsp/fsp_graphics.c
@@ -7,7 +7,7 @@
 #include 
 #include 
 #include 
-#include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
diff --git a/arch/x86/lib/fsp1/Makefile b/arch/x86/lib/fsp1/Makefile
index 870de71bd7..1cf5e54191 100644
--- a/arch/x86/lib/fsp1/Makefile
+++ b/arch/x86/lib/fsp1/Makefile
@@ -5,5 +5,4 @@
 obj-y += fsp_car.o
 obj-y += fsp_common.o
 obj-y += fsp_dram.o
-obj-$(CONFIG_VIDEO_FSP) += fsp_graphics.o
 obj-y += fsp_support.o
-- 
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[U-Boot] [PATCH v5 063/101] x86: spi: Don't enable SPI_FLASH_BAR by default

2019-11-24 Thread Simon Glass
We don't normally need this on x86 unless the size of SPI flash devices is
larger than 16MB. This can be enabled by particular SoCs as needed, since
it adds to code size.

Drop the default enabling of this option on x86.

Signed-off-by: Simon Glass 
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/spi/Kconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 8588866489..fae2040af8 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -142,7 +142,6 @@ config FSL_DSPI
 
 config ICH_SPI
bool "Intel ICH SPI driver"
-   imply SPI_FLASH_BAR
help
  Enable the Intel ICH SPI driver. This driver can be used to
  access the SPI NOR flash on platforms embedding this Intel
-- 
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[U-Boot] [PATCH v5 065/101] spi: ich: Move the protection/lockdown code into a function

2019-11-24 Thread Simon Glass
Reduce the size of the probe function but putting this code into its own
function.

Also remove the assumption that the PCH is always a parent of the SPI
controller, as this is not the case APL platforms. Use driver model to
find the PCH instead.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/spi/ich.c | 63 ---
 drivers/spi/ich.h |  1 +
 2 files changed, 44 insertions(+), 20 deletions(-)

diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index 3eb4599ba2..4d61be02ec 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -98,13 +98,14 @@ static void ich_set_bbar(struct ich_spi_priv *ctlr, 
uint32_t minaddr)
 /* @return 1 if the SPI flash supports the 33MHz speed */
 static int ich9_can_do_33mhz(struct udevice *dev)
 {
+   struct ich_spi_priv *priv = dev_get_priv(dev);
u32 fdod, speed;
 
/* Observe SPI Descriptor Component Section 0 */
-   dm_pci_write_config32(dev->parent, 0xb0, 0x1000);
+   dm_pci_write_config32(priv->pch, 0xb0, 0x1000);
 
/* Extract the Write/Erase SPI Frequency from descriptor */
-   dm_pci_read_config32(dev->parent, 0xb4, &fdod);
+   dm_pci_read_config32(priv->pch, 0xb4, &fdod);
 
/* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */
speed = (fdod >> 21) & 7;
@@ -432,6 +433,37 @@ static int ich_spi_adjust_size(struct spi_slave *slave, 
struct spi_mem_op *op)
return 0;
 }
 
+static int ich_protect_lockdown(struct udevice *dev)
+{
+   struct ich_spi_platdata *plat = dev_get_platdata(dev);
+   struct ich_spi_priv *priv = dev_get_priv(dev);
+   int ret = -ENOSYS;
+
+   /* Disable the BIOS write protect so write commands are allowed */
+   if (priv->pch)
+   ret = pch_set_spi_protect(priv->pch, false);
+   if (ret == -ENOSYS) {
+   u8 bios_cntl;
+
+   bios_cntl = ich_readb(priv, priv->bcr);
+   bios_cntl &= ~BIT(5);   /* clear Enable InSMM_STS (EISS) */
+   bios_cntl |= 1; /* Write Protect Disable (WPD) */
+   ich_writeb(priv, bios_cntl, priv->bcr);
+   } else if (ret) {
+   debug("%s: Failed to disable write-protect: err=%d\n",
+ __func__, ret);
+   return ret;
+   }
+
+   /* Lock down SPI controller settings if required */
+   if (plat->lockdown) {
+   ich_spi_config_opcode(dev);
+   spi_lock_down(plat, priv->base);
+   }
+
+   return 0;
+}
+
 static int ich_init_controller(struct udevice *dev,
   struct ich_spi_platdata *plat,
   struct ich_spi_priv *ctlr)
@@ -497,30 +529,15 @@ static int ich_spi_probe(struct udevice *dev)
 {
struct ich_spi_platdata *plat = dev_get_platdata(dev);
struct ich_spi_priv *priv = dev_get_priv(dev);
-   uint8_t bios_cntl;
int ret;
 
ret = ich_init_controller(dev, plat, priv);
if (ret)
return ret;
-   /* Disable the BIOS write protect so write commands are allowed */
-   ret = pch_set_spi_protect(dev->parent, false);
-   if (ret == -ENOSYS) {
-   bios_cntl = ich_readb(priv, priv->bcr);
-   bios_cntl &= ~BIT(5);   /* clear Enable InSMM_STS (EISS) */
-   bios_cntl |= 1; /* Write Protect Disable (WPD) */
-   ich_writeb(priv, bios_cntl, priv->bcr);
-   } else if (ret) {
-   debug("%s: Failed to disable write-protect: err=%d\n",
- __func__, ret);
-   return ret;
-   }
 
-   /* Lock down SPI controller settings if required */
-   if (plat->lockdown) {
-   ich_spi_config_opcode(dev);
-   spi_lock_down(plat, priv->base);
-   }
+   ret = ich_protect_lockdown(dev);
+   if (ret)
+   return ret;
 
priv->cur_speed = priv->max_speed;
 
@@ -579,9 +596,15 @@ static int ich_spi_child_pre_probe(struct udevice *dev)
 static int ich_spi_ofdata_to_platdata(struct udevice *dev)
 {
struct ich_spi_platdata *plat = dev_get_platdata(dev);
+   struct ich_spi_priv *priv = dev_get_priv(dev);
int node = dev_of_offset(dev);
int ret;
 
+   /* Find a PCH if there is one */
+   uclass_first_device(UCLASS_PCH, &priv->pch);
+   if (!priv->pch)
+   priv->pch = dev_get_parent(dev);
+
ret = fdt_node_check_compatible(gd->fdt_blob, node, "intel,ich7-spi");
if (ret == 0) {
plat->ich_version = ICHV_7;
diff --git a/drivers/spi/ich.h b/drivers/spi/ich.h
index 3dfb2aaff1..77057878a5 100644
--- a/drivers/spi/ich.h
+++ b/drivers/spi/ich.h
@@ -191,6 +191,7 @@ struct ich_spi_priv {
ulong max_speed;/* Maximum bus speed in MHz */
ulong cur_speed;/* Current bus speed */
struct sp

[U-Boot] [PATCH v5 064/101] spi: ich: Move init function just above probe()

2019-11-24 Thread Simon Glass
It is annoying to have some of the init code in a different part of the
file. Move ich_init_controller() to just above probe() to keep things
together.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/spi/ich.c | 122 +++---
 1 file changed, 61 insertions(+), 61 deletions(-)

diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index a4e4ad55c6..3eb4599ba2 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -112,67 +112,6 @@ static int ich9_can_do_33mhz(struct udevice *dev)
return speed == 1;
 }
 
-static int ich_init_controller(struct udevice *dev,
-  struct ich_spi_platdata *plat,
-  struct ich_spi_priv *ctlr)
-{
-   ulong sbase_addr;
-   void *sbase;
-
-   /* SBASE is similar */
-   pch_get_spi_base(dev->parent, &sbase_addr);
-   sbase = (void *)sbase_addr;
-   debug("%s: sbase=%p\n", __func__, sbase);
-
-   if (plat->ich_version == ICHV_7) {
-   struct ich7_spi_regs *ich7_spi = sbase;
-
-   ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu);
-   ctlr->menubytes = sizeof(ich7_spi->opmenu);
-   ctlr->optype = offsetof(struct ich7_spi_regs, optype);
-   ctlr->addr = offsetof(struct ich7_spi_regs, spia);
-   ctlr->data = offsetof(struct ich7_spi_regs, spid);
-   ctlr->databytes = sizeof(ich7_spi->spid);
-   ctlr->status = offsetof(struct ich7_spi_regs, spis);
-   ctlr->control = offsetof(struct ich7_spi_regs, spic);
-   ctlr->bbar = offsetof(struct ich7_spi_regs, bbar);
-   ctlr->preop = offsetof(struct ich7_spi_regs, preop);
-   ctlr->base = ich7_spi;
-   } else if (plat->ich_version == ICHV_9) {
-   struct ich9_spi_regs *ich9_spi = sbase;
-
-   ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu);
-   ctlr->menubytes = sizeof(ich9_spi->opmenu);
-   ctlr->optype = offsetof(struct ich9_spi_regs, optype);
-   ctlr->addr = offsetof(struct ich9_spi_regs, faddr);
-   ctlr->data = offsetof(struct ich9_spi_regs, fdata);
-   ctlr->databytes = sizeof(ich9_spi->fdata);
-   ctlr->status = offsetof(struct ich9_spi_regs, ssfs);
-   ctlr->control = offsetof(struct ich9_spi_regs, ssfc);
-   ctlr->speed = ctlr->control + 2;
-   ctlr->bbar = offsetof(struct ich9_spi_regs, bbar);
-   ctlr->preop = offsetof(struct ich9_spi_regs, preop);
-   ctlr->bcr = offsetof(struct ich9_spi_regs, bcr);
-   ctlr->pr = &ich9_spi->pr[0];
-   ctlr->base = ich9_spi;
-   } else {
-   debug("ICH SPI: Unrecognised ICH version %d\n",
- plat->ich_version);
-   return -EINVAL;
-   }
-
-   /* Work out the maximum speed we can support */
-   ctlr->max_speed = 2000;
-   if (plat->ich_version == ICHV_9 && ich9_can_do_33mhz(dev))
-   ctlr->max_speed = 3300;
-   debug("ICH SPI: Version ID %d detected at %p, speed %ld\n",
- plat->ich_version, ctlr->base, ctlr->max_speed);
-
-   ich_set_bbar(ctlr, 0);
-
-   return 0;
-}
-
 static void spi_lock_down(struct ich_spi_platdata *plat, void *sbase)
 {
if (plat->ich_version == ICHV_7) {
@@ -493,6 +432,67 @@ static int ich_spi_adjust_size(struct spi_slave *slave, 
struct spi_mem_op *op)
return 0;
 }
 
+static int ich_init_controller(struct udevice *dev,
+  struct ich_spi_platdata *plat,
+  struct ich_spi_priv *ctlr)
+{
+   ulong sbase_addr;
+   void *sbase;
+
+   /* SBASE is similar */
+   pch_get_spi_base(dev->parent, &sbase_addr);
+   sbase = (void *)sbase_addr;
+   debug("%s: sbase=%p\n", __func__, sbase);
+
+   if (plat->ich_version == ICHV_7) {
+   struct ich7_spi_regs *ich7_spi = sbase;
+
+   ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu);
+   ctlr->menubytes = sizeof(ich7_spi->opmenu);
+   ctlr->optype = offsetof(struct ich7_spi_regs, optype);
+   ctlr->addr = offsetof(struct ich7_spi_regs, spia);
+   ctlr->data = offsetof(struct ich7_spi_regs, spid);
+   ctlr->databytes = sizeof(ich7_spi->spid);
+   ctlr->status = offsetof(struct ich7_spi_regs, spis);
+   ctlr->control = offsetof(struct ich7_spi_regs, spic);
+   ctlr->bbar = offsetof(struct ich7_spi_regs, bbar);
+   ctlr->preop = offsetof(struct ich7_spi_regs, preop);
+   ctlr->base = ich7_spi;
+   } else if (plat->ich_version == ICHV_9) {
+   struct ich9_spi_regs *ich9_spi = sbase;
+
+   ctlr->opmenu = offsetof(struct ich9

[U-Boot] [PATCH v5 020/101] x86: sandbox: Add a PMC emulator and test

2019-11-24 Thread Simon Glass
Add a simple PMC for sandbox to permit tests to run.

Signed-off-by: Simon Glass 
---

Changes in v5: None
Changes in v4: None
Changes in v3:
- Rename power-mgr uclass to acpi-pmc
- Tidy up Makefile rules to reduce duplication

Changes in v2: None

 arch/Kconfig  |   2 +
 arch/sandbox/dts/sandbox.dtsi |  14 ++
 arch/sandbox/dts/test.dts |  14 ++
 arch/sandbox/include/asm/test.h   |   1 +
 drivers/Makefile  |   1 +
 drivers/power/acpi_pmc/Kconfig|   9 ++
 drivers/power/acpi_pmc/Makefile   |   1 +
 drivers/power/acpi_pmc/pmc_emul.c | 246 ++
 drivers/power/acpi_pmc/sandbox.c  |  97 
 test/dm/Makefile  |   1 +
 test/dm/pmc.c |  33 
 11 files changed, 419 insertions(+)
 create mode 100644 drivers/power/acpi_pmc/pmc_emul.c
 create mode 100644 drivers/power/acpi_pmc/sandbox.c
 create mode 100644 test/dm/pmc.c

diff --git a/arch/Kconfig b/arch/Kconfig
index 141e48bc43..8094e18663 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -133,6 +133,8 @@ config SANDBOX
imply PHYLIB
imply DM_MDIO
imply DM_MDIO_MUX
+   imply ACPI_PMC
+   imply ACPI_PMC_SANDBOX
 
 config SH
bool "SuperH architecture"
diff --git a/arch/sandbox/dts/sandbox.dtsi b/arch/sandbox/dts/sandbox.dtsi
index f09bc70b0d..7bf144f532 100644
--- a/arch/sandbox/dts/sandbox.dtsi
+++ b/arch/sandbox/dts/sandbox.dtsi
@@ -100,6 +100,17 @@
};
 
pci-controller {
+   pci@1e,0 {
+   compatible = "sandbox,pmc";
+   reg = <0xf000 0 0 0 0>;
+   sandbox,emul = <&pmc_emul>;
+   gpe0-dwx-mask = <0xf>;
+   gpe0-dwx-shift-base = <4>;
+   gpe0-dw = <6 7 9>;
+   gpe0-sts = <0x20>;
+   gpe0-en = <0x30>;
+   };
+
pci@1f,0 {
compatible = "pci-generic";
reg = <0xf800 0 0 0 0>;
@@ -109,6 +120,9 @@
 
emul {
compatible = "sandbox,pci-emul-parent";
+   pmc_emul: emul@1e,0 {
+   compatible = "sandbox,pmc-emul";
+   };
swap_case_emul: emul@1f,0 {
compatible = "sandbox,swap-case";
};
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index fdb08f2111..99905677ab 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -471,6 +471,17 @@
   0x01000810 0 0 0 0>;
sandbox,emul = <&swap_case_emul0_1>;
};
+   pci@1e,0 {
+   compatible = "sandbox,pmc";
+   reg = <0xf000 0 0 0 0>;
+   sandbox,emul = <&pmc_emul1e>;
+   acpi-base = <0x400>;
+   gpe0-dwx-mask = <0xf>;
+   gpe0-dwx-shift-base = <4>;
+   gpe0-dw = <6 7 9>;
+   gpe0-sts = <0x20>;
+   gpe0-en = <0x30>;
+   };
pci@1f,0 {
compatible = "pci-generic";
/* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
@@ -491,6 +502,9 @@
swap_case_emul0_1f: emul0@1f,0 {
compatible = "sandbox,swap-case";
};
+   pmc_emul1e: emul@1e,0 {
+   compatible = "sandbox,pmc-emul";
+   };
};
 
pci1: pci-controller1 {
diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h
index b885e1a14f..fa40d21f3f 100644
--- a/arch/sandbox/include/asm/test.h
+++ b/arch/sandbox/include/asm/test.h
@@ -13,6 +13,7 @@
 
 #define SANDBOX_PCI_VENDOR_ID  0x1234
 #define SANDBOX_PCI_SWAP_CASE_EMUL_ID  0x5678
+#define SANDBOX_PCI_PMC_EMUL_ID0x5677
 #define SANDBOX_PCI_CLASS_CODE PCI_CLASS_CODE_COMM
 #define SANDBOX_PCI_CLASS_SUB_CODE PCI_CLASS_SUB_CODE_COMM_SERIAL
 
diff --git a/drivers/Makefile b/drivers/Makefile
index 0befeddfcb..4f460edc95 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_$(SPL_TPL_)VIRTIO) += virtio/
 obj-$(CONFIG_$(SPL_)DM_MAILBOX) += mailbox/
 obj-$(CONFIG_$(SPL_)REMOTEPROC) += remoteproc/
 obj-$(CONFIG_$(SPL_TPL_)TPM) += tpm/
+obj-$(CONFIG_$(SPL_TPL_)ACPI_PMC) += power/acpi_pmc/
 
 ifndef CONFIG_TPL_BUILD
 ifdef CONFIG_SPL_BUILD
diff --git a/drivers/power/acpi_pmc/Kconfig b/drivers/power/acpi_pmc/Kconfig
index 472a61a9fd..fcd50e36ca 100644
--- a/drivers/power/acpi_pmc/Kconfig
+++ b/drivers/power/acpi_pmc/Kconfig
@@ -23,3 +23,12 @@ config TPL_ACPI_PMC
  provides features including checking whether the system started from
  resume, powering off the system and enabling/disabling the reset
  mechanism.
+
+config ACPI_PMC_SANDBOX
+   boo

[U-Boot] [PATCH v5 032/101] x86: Add a new global_data member for the cache record

2019-11-24 Thread Simon Glass
At present we reuse the mrc_output char * to also point to the cache
record after it has been set up. This is confusing and doesn't save much
data space.

Add a new mrc_cache member instead.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/x86/include/asm/global_data.h |  2 ++
 arch/x86/lib/mrccache.c| 11 +--
 2 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/arch/x86/include/asm/global_data.h 
b/arch/x86/include/asm/global_data.h
index 0e7b946205..3212b006eb 100644
--- a/arch/x86/include/asm/global_data.h
+++ b/arch/x86/include/asm/global_data.h
@@ -10,6 +10,7 @@
 #ifndef __ASSEMBLY__
 
 #include 
+#include 
 
 enum pei_boot_mode_t {
PEI_BOOT_NONE = 0,
@@ -93,6 +94,7 @@ struct arch_global_data {
/* MRC training data to save for the next boot */
char *mrc_output;
unsigned int mrc_output_len;
+   struct mrc_data_container *mrc_cache;
ulong table;/* Table pointer from previous loader */
int turbo_state;/* Current turbo state */
struct irq_routing_table *pirq_routing_table;
diff --git a/arch/x86/lib/mrccache.c b/arch/x86/lib/mrccache.c
index 7136166be6..6e561fe528 100644
--- a/arch/x86/lib/mrccache.c
+++ b/arch/x86/lib/mrccache.c
@@ -188,8 +188,7 @@ static void mrccache_setup(void *data)
cache->reserved = 0;
memcpy(cache->data, gd->arch.mrc_output, cache->data_size);
 
-   /* gd->arch.mrc_output now points to the container */
-   gd->arch.mrc_output = (char *)cache;
+   gd->arch.mrc_cache = cache;
 }
 
 int mrccache_reserve(void)
@@ -255,7 +254,7 @@ int mrccache_get_region(struct udevice **devp, struct 
mrc_region *entry)
 
 int mrccache_save(void)
 {
-   struct mrc_data_container *data;
+   struct mrc_data_container *cache;
struct mrc_region entry;
struct udevice *sf;
int ret;
@@ -271,10 +270,10 @@ int mrccache_save(void)
ret = device_probe(sf);
if (ret)
goto err_entry;
-   data  = (struct mrc_data_container *)gd->arch.mrc_output;
-   ret = mrccache_update(sf, &entry, data);
+   cache = gd->arch.mrc_cache;
+   ret = mrccache_update(sf, &entry, cache);
if (!ret) {
-   debug("Saved MRC data with checksum %04x\n", data->checksum);
+   debug("Saved MRC data with checksum %04x\n", cache->checksum);
} else if (ret == -EEXIST) {
debug("MRC data is the same as last time, skipping save\n");
ret = 0;
-- 
2.24.0.432.g9d3f5f5b63-goog

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[U-Boot] [PATCH v5 091/101] x86: apl: Add LPC driver

2019-11-24 Thread Simon Glass
This driver the LPC and provides a few functions to set up LPC features.
These should probably use ioctls() or perhaps, better, have specific
uclass methods.

Signed-off-by: Simon Glass 
---

Changes in v5: None
Changes in v4:
- Add comments for exported functions
- Tidy up header guards
- Use 'Apollo Lake'
- Use BIT() macro a bit more
- Use tabs instead of spaces

Changes in v3:
- Drop unused code in lpc_configure_pads()
- Fix value of LPC_BC_LE

Changes in v2: None

 arch/x86/cpu/apollolake/Makefile   |   1 +
 arch/x86/cpu/apollolake/lpc.c  | 141 +
 arch/x86/include/asm/arch-apollolake/lpc.h |  82 
 3 files changed, 224 insertions(+)
 create mode 100644 arch/x86/cpu/apollolake/lpc.c
 create mode 100644 arch/x86/include/asm/arch-apollolake/lpc.h

diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile
index 2d78368150..31045a03c1 100644
--- a/arch/x86/cpu/apollolake/Makefile
+++ b/arch/x86/cpu/apollolake/Makefile
@@ -6,5 +6,6 @@ obj-$(CONFIG_SPL_BUILD) += systemagent.o
 
 obj-y += hostbridge.o
 obj-y += itss.o
+obj-y += lpc.o
 obj-y += pmc.o
 obj-y += uart.o
diff --git a/arch/x86/cpu/apollolake/lpc.c b/arch/x86/cpu/apollolake/lpc.c
new file mode 100644
index 00..b14eed6508
--- /dev/null
+++ b/arch/x86/cpu/apollolake/lpc.c
@@ -0,0 +1,141 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Google LLC
+ *
+ * From coreboot Apollo Lake support lpc.c
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+void lpc_configure_pads(void)
+{
+   /* All pads are configured by the hostbridge */
+}
+
+void lpc_enable_fixed_io_ranges(uint io_enables)
+{
+   pci_x86_clrset_config(PCH_DEV_LPC, LPC_IO_ENABLES, 0, io_enables,
+ PCI_SIZE_16);
+}
+
+/*
+ * Find the first unused IO window.
+ * Returns -1 if not found, 0 for reg 0x84, 1 for reg 0x88 ...
+ */
+static int find_unused_pmio_window(void)
+{
+   int i;
+   ulong lgir;
+
+   for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) {
+   pci_x86_read_config(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(i),
+   &lgir, PCI_SIZE_32);
+
+   if (!(lgir & LPC_LGIR_EN))
+   return i;
+   }
+
+   return -1;
+}
+
+int lpc_open_pmio_window(uint base, uint size)
+{
+   int i, lgir_reg_num;
+   u32 lgir_reg_offset, lgir, window_size, alignment;
+   ulong bridged_size, bridge_base;
+   ulong reg;
+
+   log_debug("LPC: Trying to open IO window from %x size %x\n", base,
+ size);
+
+   bridged_size = 0;
+   bridge_base = base;
+
+   while (bridged_size < size) {
+   /* Each IO range register can only open a 256-byte window */
+   window_size = min(size, (uint)LPC_LGIR_MAX_WINDOW_SIZE);
+
+   /* Window size must be a power of two for the AMASK to work */
+   alignment = 1UL << (order_base_2(window_size));
+   window_size = ALIGN(window_size, alignment);
+
+   /* Address[15:2] in LGIR[15:12] and Mask[7:2] in LGIR[23:18] */
+   lgir = (bridge_base & LPC_LGIR_ADDR_MASK) | LPC_LGIR_EN;
+   lgir |= ((window_size - 1) << 16) & LPC_LGIR_AMASK_MASK;
+
+   /* Skip programming if same range already programmed */
+   for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) {
+   pci_x86_read_config(PCH_DEV_LPC,
+   LPC_GENERIC_IO_RANGE(i), ®,
+   PCI_SIZE_32);
+   if (lgir == reg)
+   return -EALREADY;
+   }
+
+   lgir_reg_num = find_unused_pmio_window();
+   if (lgir_reg_num < 0) {
+   log_err("LPC: Cannot open IO window: %lx size %lx\n",
+   bridge_base, size - bridged_size);
+   log_err("No more IO windows\n");
+
+   return -ENOSPC;
+   }
+   lgir_reg_offset = LPC_GENERIC_IO_RANGE(lgir_reg_num);
+
+   pci_x86_write_config(PCH_DEV_LPC, lgir_reg_offset, lgir,
+PCI_SIZE_32);
+
+   log_debug("LPC: Opened IO window LGIR%d: base %lx size %x\n",
+ lgir_reg_num, bridge_base, window_size);
+
+   bridged_size += window_size;
+   bridge_base += window_size;
+   }
+
+   return 0;
+}
+
+void lpc_io_setup_comm_a_b(void)
+{
+   /* ComA Range 3F8h-3FFh [2:0] */
+   u16 com_ranges = LPC_IOD_COMA_RANGE;
+   u16 com_enable = LPC_IOE_COMA_EN;
+
+   /* ComB Range 2F8h-2FFh [6:4] */
+   if (0) {
+   com_ranges |= LPC_IOD_COMB_RANGE;
+   com_enable |= LPC_IOE_COMB_EN;
+   }
+
+   /* Setup I/O Decode Range Register for LPC */
+   pci_write_config16(PCH_DEV

[U-Boot] [PATCH v5 057/101] x86: Add an option to control the position of SPL

2019-11-24 Thread Simon Glass
For Apollo Lake SPL is run from CAR (cache-as-RAM) which is in a different
location from where SPL must be placed in ROM. In other words, although
SPL runs before SDRAM is set up, it is not execute-in-place (XIP).

Add a Kconfig option for the ROM position.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v5: None
Changes in v4:
- apollolake -> Apollo Lake

Changes in v3:
- Add SPL condition to the option

Changes in v2: None

 arch/x86/Kconfig | 5 +
 arch/x86/dts/u-boot.dtsi | 4 ++--
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index e105fda2f2..ae96e69f86 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -904,4 +904,9 @@ config X86_OFFSET_U_BOOT
depends on HAVE_SYS_TEXT_BASE
default SYS_TEXT_BASE
 
+config X86_OFFSET_SPL
+   hex "Offset of SPL in ROM image"
+   depends on SPL && X86
+   default SPL_TEXT_BASE
+
 endmenu
diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
index d84c64880a..fad3e7c951 100644
--- a/arch/x86/dts/u-boot.dtsi
+++ b/arch/x86/dts/u-boot.dtsi
@@ -45,7 +45,7 @@
};
 #endif
u-boot-spl {
-   offset = ;
+   offset = ;
};
u-boot-spl-dtb {
};
@@ -54,7 +54,7 @@
};
 #elif defined(CONFIG_SPL)
u-boot-spl-with-ucode-ptr {
-   offset = ;
+   offset = ;
};
u-boot-dtb-with-ucode2 {
type = "u-boot-dtb-with-ucode";
-- 
2.24.0.432.g9d3f5f5b63-goog

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[U-Boot] [PATCH v5 015/101] x86: timer: use a timer base of 0

2019-11-24 Thread Simon Glass
On x86 platforms the timer is reset to 0 when the SoC is reset. Having
this as the timer base is useful since it provides an indication of how
long it takes before U-Boot is running.

When U-Boot sets the timer base to something else, time is lost and we
no-longer have an accurate account of the time since reset. This
particularly affects bootstage.

Change the default to not read the timer base, leaving it at 0. Add an
option for when U-Boot is the secondary bootloader.

Signed-off-by: Simon Glass 
---

Changes in v5: None
Changes in v4:
- Enable option for slimbootloader, coreboot, efi
- Reverse the sense of the CONFIG option

Changes in v3: None
Changes in v2: None

 arch/x86/cpu/coreboot/Kconfig   |  1 +
 arch/x86/cpu/slimbootloader/Kconfig |  1 +
 drivers/timer/Kconfig   | 14 ++
 drivers/timer/tsc_timer.c   |  3 ++-
 lib/efi/Kconfig |  1 +
 5 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/arch/x86/cpu/coreboot/Kconfig b/arch/x86/cpu/coreboot/Kconfig
index 93f61f2fa4..c8e6a889d0 100644
--- a/arch/x86/cpu/coreboot/Kconfig
+++ b/arch/x86/cpu/coreboot/Kconfig
@@ -24,5 +24,6 @@ config SYS_COREBOOT
imply CMD_CBFS
imply FS_CBFS
imply CBMEM_CONSOLE
+   imply X86_TSC_READ_BASE
 
 endif
diff --git a/arch/x86/cpu/slimbootloader/Kconfig 
b/arch/x86/cpu/slimbootloader/Kconfig
index 3ea4c9958c..58a9ca01a9 100644
--- a/arch/x86/cpu/slimbootloader/Kconfig
+++ b/arch/x86/cpu/slimbootloader/Kconfig
@@ -17,3 +17,4 @@ config SYS_SLIMBOOTLOADER
imply USB_EHCI_HCD
imply USB_XHCI_HCD
imply E1000
+   imply X86_TSC_READ_BASE
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 5f4bc6edb6..41f9755133 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -174,6 +174,20 @@ config X86_TSC_TIMER
help
  Select this to enable Time-Stamp Counter (TSC) timer for x86.
 
+config X86_TSC_READ_BASE
+   bool "Read the TSC timer base on start-up"
+   depends on X86_TSC_TIMER
+   help
+ On x86 platforms the TSC timer tick starts at the value 0 on reset.
+ This it makes no sense to read the timer on boot and use that as the
+ base, since we will miss some time taken to load U-Boot, etc. This
+ delay is controlled by the SoC and we cannot reduce it, but for
+ bootstage we want to record the time since reset as accurately as
+ possible.
+
+ The only exception is when U-Boot is used as a secondary bootloader,
+ where this option should be enabled.
+
 config MTK_TIMER
bool "MediaTek timer support"
depends on TIMER
diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c
index 637c8ff25a..a11a82f21a 100644
--- a/drivers/timer/tsc_timer.c
+++ b/drivers/timer/tsc_timer.c
@@ -396,7 +396,8 @@ static void tsc_timer_ensure_setup(bool early)
 {
if (gd->arch.tsc_inited)
return;
-   gd->arch.tsc_base = rdtsc();
+   if (IS_ENABLED(CONFIG_X86_TSC_READ_BASE))
+   gd->arch.tsc_base = rdtsc();
 
if (!gd->arch.clock_rate) {
unsigned long fast_calibrate;
diff --git a/lib/efi/Kconfig b/lib/efi/Kconfig
index 919e314a0c..93b8564492 100644
--- a/lib/efi/Kconfig
+++ b/lib/efi/Kconfig
@@ -1,6 +1,7 @@
 config EFI
bool "Support running U-Boot from EFI"
depends on X86
+   imply X86_TSC_READ_BASE
help
  U-Boot can be started from EFI on certain platforms. This allows
  EFI to perform most of the system init and then jump to U-Boot for
-- 
2.24.0.432.g9d3f5f5b63-goog

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[U-Boot] [PATCH v5 097/101] x86: apl: Add P2SB driver

2019-11-24 Thread Simon Glass
Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports
various child devices. It supposed both device tree and of-platdata.

Signed-off-by: Simon Glass 
---

Changes in v5: None
Changes in v4:
- Detect zero mmio address
- Use BIT() macro bit more
- apollolake -> Apollo Lake

Changes in v3:
- Use pci_get_devfn()

Changes in v2: None

 arch/x86/cpu/apollolake/Makefile |   1 +
 arch/x86/cpu/apollolake/p2sb.c   | 167 +++
 2 files changed, 168 insertions(+)
 create mode 100644 arch/x86/cpu/apollolake/p2sb.c

diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile
index edde122f75..dc6df15dab 100644
--- a/arch/x86/cpu/apollolake/Makefile
+++ b/arch/x86/cpu/apollolake/Makefile
@@ -15,6 +15,7 @@ endif
 obj-y += hostbridge.o
 obj-y += itss.o
 obj-y += lpc.o
+obj-y += p2sb.o
 obj-y += pch.o
 obj-y += pmc.o
 obj-y += uart.o
diff --git a/arch/x86/cpu/apollolake/p2sb.c b/arch/x86/cpu/apollolake/p2sb.c
new file mode 100644
index 00..0a5deaf4a0
--- /dev/null
+++ b/arch/x86/cpu/apollolake/p2sb.c
@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Primary-to-Sideband Bridge
+ *
+ * Copyright 2019 Google LLC
+ */
+
+#define LOG_CATEGORY UCLASS_P2SB
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+struct p2sb_platdata {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+   struct dtd_intel_apl_p2sb dtplat;
+#endif
+   ulong mmio_base;
+   pci_dev_t bdf;
+};
+
+/* PCI config space registers */
+#define HPTC_OFFSET0x60
+#define HPTC_ADDR_ENABLE_BIT   BIT(7)
+
+/* High Performance Event Timer Configuration */
+#define P2SB_HPTC  0x60
+#define P2SB_HPTC_ADDRESS_ENABLE   BIT(7)
+
+/*
+ * ADDRESS_SELECTENCODING_RANGE
+ *  0 0xfed0  - 0xfed0 03ff
+ *  1 0xfed0 1000 - 0xfed0 13ff
+ *  2 0xfed0 2000 - 0xfed0 23ff
+ *  3 0xfed0 3000 - 0xfed0 33ff
+ */
+#define P2SB_HPTC_ADDRESS_SELECT_0 (0 << 0)
+#define P2SB_HPTC_ADDRESS_SELECT_1 (1 << 0)
+#define P2SB_HPTC_ADDRESS_SELECT_2 (2 << 0)
+#define P2SB_HPTC_ADDRESS_SELECT_3 (3 << 0)
+
+/*
+ * apl_p2sb_early_init() - Enable decoding for HPET range
+ *
+ * This is needed for FspMemoryInit to store and retrieve a global data
+ * pointer
+ *
+ * @dev: P2SB device
+ * @return 0 if OK, -ve on error
+ */
+static int apl_p2sb_early_init(struct udevice *dev)
+{
+   struct p2sb_platdata *plat = dev_get_platdata(dev);
+   pci_dev_t pdev = plat->bdf;
+
+   /*
+* Enable decoding for HPET memory address range.
+* HPTC_OFFSET(0x60) bit 7, when set the P2SB will decode
+* the High Performance Timer memory address range
+* selected by bits 1:0
+*/
+   pci_x86_write_config(pdev, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT,
+PCI_SIZE_8);
+
+   /* Enable PCR Base address in PCH */
+   pci_x86_write_config(pdev, PCI_BASE_ADDRESS_0, plat->mmio_base,
+PCI_SIZE_32);
+   pci_x86_write_config(pdev, PCI_BASE_ADDRESS_1, 0, PCI_SIZE_32);
+
+   /* Enable P2SB MSE */
+   pci_x86_write_config(pdev, PCI_COMMAND, PCI_COMMAND_MASTER |
+PCI_COMMAND_MEMORY, PCI_SIZE_8);
+
+   return 0;
+}
+
+static int apl_p2sb_spl_init(struct udevice *dev)
+{
+   /* Enable decoding for HPET. Needed for FSP global pointer storage */
+   dm_pci_write_config(dev, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 |
+   P2SB_HPTC_ADDRESS_ENABLE, PCI_SIZE_8);
+
+   return 0;
+}
+
+int apl_p2sb_ofdata_to_platdata(struct udevice *dev)
+{
+   struct p2sb_uc_priv *upriv = dev_get_uclass_priv(dev);
+   struct p2sb_platdata *plat = dev_get_platdata(dev);
+
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+   int ret;
+
+   if (spl_phase() == PHASE_TPL) {
+   u32 base[2];
+
+   /* TPL sets up the initial BAR */
+   ret = dev_read_u32_array(dev, "early-regs", base,
+ARRAY_SIZE(base));
+   if (ret)
+   return log_msg_ret("Missing/short early-regs", ret);
+   plat->mmio_base = base[0];
+   plat->bdf = pci_get_devfn(dev);
+   if (plat->bdf < 0)
+   return log_msg_ret("Cannot get p2sb PCI address",
+  plat->bdf);
+   } else {
+   plat->mmio_base = dev_read_addr_pci(dev);
+   /* Don't set BDF since it should not be used */
+   if (!plat->mmio_base || plat->mmio_base == FDT_ADDR_T_NONE)
+   return -EINVAL;
+   }
+#else
+   plat->mmio_base = plat->dtplat.early_regs[0];
+   plat->bdf = pci_ofplat_get_devfn(plat->dtplat.reg[0]);
+#endif
+   upriv->mmio_base = plat->mmio_base;
+   debug("p2sb: mmio_base=%x\n

[U-Boot] [PATCH v5 060/101] x86: Separate out U-Boot and device tree in ROM image

2019-11-24 Thread Simon Glass
At present binman does not support updating a device tree that is part of
U-Boot (i.e u-boot.bin). Separate the entries into two so that we can get
updated entry information. This makes binman_entry_find() work correctly.

Do the same for SPL tool.

In both cases, group the two parts into a section so that SPL symbols get
the correct total size.

It may be possible for binman to handle this automatically at some point,
by ignoring u-boot.bin and always creating it from u-boot-nodtb.bin and
u-boot.dtb

Signed-off-by: Simon Glass 
---

Changes in v5:
- Change SPL as well
- Group U-Boot and device tree into a section

Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/x86/dts/u-boot.dtsi | 12 ++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
index e0cca58640..72cea1b276 100644
--- a/arch/x86/dts/u-boot.dtsi
+++ b/arch/x86/dts/u-boot.dtsi
@@ -45,12 +45,20 @@
};
 #endif
u-boot-spl {
+   type = "section";
offset = ;
-   };
-   u-boot-spl-dtb {
+   u-boot-spl {
+   };
+   u-boot-spl-dtb {
+   };
};
u-boot {
+   type = "section";
offset = ;
+   u-boot-nodtb {
+   };
+   u-boot-dtb {
+   };
};
 #elif defined(CONFIG_SPL)
u-boot-spl-with-ucode-ptr {
-- 
2.24.0.432.g9d3f5f5b63-goog

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[U-Boot] [PATCH v5 061/101] x86: Make MSR_PKG_POWER_SKU common

2019-11-24 Thread Simon Glass
This is used on several boards so add it to the common file. Also add a
useful power-limit value while we are here.

Reviewed-by: Bin Meng 
Signed-off-by: Simon Glass 
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/x86/include/asm/arch-broadwell/cpu.h | 1 -
 arch/x86/include/asm/arch-ivybridge/model_206ax.h | 1 -
 arch/x86/include/asm/msr-index.h  | 9 -
 3 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/arch/x86/include/asm/arch-broadwell/cpu.h 
b/arch/x86/include/asm/arch-broadwell/cpu.h
index 3bc3bd6609..2b39a76fbd 100644
--- a/arch/x86/include/asm/arch-broadwell/cpu.h
+++ b/arch/x86/include/asm/arch-broadwell/cpu.h
@@ -27,7 +27,6 @@
 
 #define MSR_VR_CURRENT_CONFIG  0x601
 #define MSR_VR_MISC_CONFIG 0x603
-#define MSR_PKG_POWER_SKU  0x614
 #define MSR_DDR_RAPL_LIMIT 0x618
 #define MSR_VR_MISC_CONFIG20x636
 
diff --git a/arch/x86/include/asm/arch-ivybridge/model_206ax.h 
b/arch/x86/include/asm/arch-ivybridge/model_206ax.h
index 4839ebc312..5c066294bc 100644
--- a/arch/x86/include/asm/arch-ivybridge/model_206ax.h
+++ b/arch/x86/include/asm/arch-ivybridge/model_206ax.h
@@ -43,7 +43,6 @@
 #define MSR_PP1_CURRENT_CONFIG 0x602
 #define  PP1_CURRENT_LIMIT_SNB (35 << 3) /* 35 A */
 #define  PP1_CURRENT_LIMIT_IVB (50 << 3) /* 50 A */
-#define MSR_PKG_POWER_SKU  0x614
 
 #define IVB_CONFIG_TDP_MIN_CPUID   0x306a2
 #define MSR_CONFIG_TDP_LEVEL1  0x649
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 5bc8b6c22c..79a9369de1 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -241,10 +241,17 @@
 #define  PKG_POWER_LIMIT_CLAMP (1 << 16)
 #define  PKG_POWER_LIMIT_TIME_SHIFT17
 #define  PKG_POWER_LIMIT_TIME_MASK 0x7f
+/*
+ * For Mobile, RAPL default PL1 time window value set to 28 seconds.
+ * RAPL time window calculation defined as follows:
+ * Time Window = (float)((1+X/4)*(2*^Y), X Corresponds to [23:22],
+ * Y to [21:17] in MSR 0x610. 28 sec is equal to 0x6e.
+ */
+#define  MB_POWER_LIMIT1_TIME_DEFAULT  0x6e
 
 #define MSR_PKG_ENERGY_STATUS  0x0611
 #define MSR_PKG_PERF_STATUS0x0613
-#define MSR_PKG_POWER_INFO 0x0614
+#define MSR_PKG_POWER_SKU  0x614
 
 #define MSR_DRAM_POWER_LIMIT   0x0618
 #define MSR_DRAM_ENERGY_STATUS 0x0619
-- 
2.24.0.432.g9d3f5f5b63-goog

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[U-Boot] [PATCH v5 094/101] x86: apl: Add SPL loaders

2019-11-24 Thread Simon Glass
Add loaders for SPL and TPL so that the next stage can be loaded from
memory-mapped SPI or, failing that, the Fast SPI driver.

Signed-off-by: Simon Glass 

---

Changes in v5:
- Add L2 cache flush functoin
- Drop SAFETY_MARGIN

Changes in v4: None
Changes in v3:
- Add a driver for APL SPI for TPL (using of-platdata)
- Support TPL without CONFIG_TPL_SPI_SUPPORT
- Support bootstage timing

Changes in v2: None

 arch/x86/cpu/apollolake/Makefile |   2 +
 arch/x86/cpu/apollolake/spl.c| 197 +++
 2 files changed, 199 insertions(+)
 create mode 100644 arch/x86/cpu/apollolake/spl.c

diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile
index 875d454157..1fde400d77 100644
--- a/arch/x86/cpu/apollolake/Makefile
+++ b/arch/x86/cpu/apollolake/Makefile
@@ -2,7 +2,9 @@
 #
 # Copyright 2019 Google LLC
 
+obj-$(CONFIG_SPL_BUILD) += spl.o
 obj-$(CONFIG_SPL_BUILD) += systemagent.o
+
 ifndef CONFIG_TPL_BUILD
 obj-y += punit.o
 endif
diff --git a/arch/x86/cpu/apollolake/spl.c b/arch/x86/cpu/apollolake/spl.c
new file mode 100644
index 00..2c8222524e
--- /dev/null
+++ b/arch/x86/cpu/apollolake/spl.c
@@ -0,0 +1,197 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+binman_sym_declare(ulong, u_boot_spl, image_pos);
+binman_sym_declare(ulong, u_boot_spl, size);
+/* U-Boot image_pos is declared by common/spl/spl.c */
+binman_sym_declare(ulong, u_boot_any, size);
+
+static ulong get_image_pos(void)
+{
+   return spl_phase() == PHASE_TPL ?
+   binman_sym(ulong, u_boot_spl, image_pos) :
+   binman_sym(ulong, u_boot_any, image_pos);
+}
+
+static ulong get_image_size(void)
+{
+   return spl_phase() == PHASE_TPL ?
+   binman_sym(ulong, u_boot_spl, size) :
+   binman_sym(ulong, u_boot_any, size);
+}
+
+/* This reads the next phase from mapped SPI flash */
+static int rom_load_image(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev)
+{
+   ulong spl_pos = get_image_pos();
+   ulong spl_size = get_image_size();
+   struct udevice *dev;
+   ulong map_base;
+   size_t map_size;
+   uint offset;
+   int ret;
+
+   spl_image->size = CONFIG_SYS_MONITOR_LEN;  /* We don't know SPL size */
+   spl_image->entry_point = spl_phase() == PHASE_TPL ?
+   CONFIG_SPL_TEXT_BASE : CONFIG_SYS_TEXT_BASE;
+   spl_image->load_addr = spl_image->entry_point;
+   spl_image->os = IH_OS_U_BOOT;
+   spl_image->name = "U-Boot";
+   debug("Reading from mapped SPI %lx, size %lx", spl_pos, spl_size);
+
+   if (CONFIG_IS_ENABLED(SPI_FLASH_SUPPORT)) {
+   ret = uclass_find_first_device(UCLASS_SPI_FLASH, &dev);
+   if (ret)
+   return log_msg_ret("spi_flash", ret);
+   if (!dev)
+   return log_msg_ret("spi_flash dev", -ENODEV);
+   ret = dm_spi_get_mmap(dev, &map_base, &map_size, &offset);
+   if (ret)
+   return log_msg_ret("mmap", ret);
+   } else {
+   ret = fast_spi_get_bios_mmap(PCH_DEV_SPI, &map_base, &map_size,
+&offset);
+   if (ret)
+   return ret;
+   }
+   spl_pos += map_base & ~0xff00;
+   debug(", base %lx, pos %lx\n", map_base, spl_pos);
+   bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi");
+   memcpy((void *)spl_image->load_addr, (void *)spl_pos, spl_size);
+   cpu_flush_l1d_to_l2();
+   bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI);
+
+   return 0;
+}
+SPL_LOAD_IMAGE_METHOD("Mapped SPI", 2, BOOT_DEVICE_SPI_MMAP, rom_load_image);
+
+#if CONFIG_IS_ENABLED(SPI_FLASH_SUPPORT)
+
+static int apl_flash_std_read(struct udevice *dev, u32 offset, size_t len,
+ void *buf)
+{
+   struct spi_flash *flash = dev_get_uclass_priv(dev);
+   struct mtd_info *mtd = &flash->mtd;
+   size_t retlen;
+
+   return log_ret(mtd->_read(mtd, offset, len, &retlen, buf));
+}
+
+static int apl_flash_probe(struct udevice *dev)
+{
+   return spi_flash_std_probe(dev);
+}
+
+/*
+ * Manually set the parent of the SPI flash to SPI, since dtoc doesn't. We also
+ * need to allocate the parent_platdata since by the time this function is
+ * called device_bind() has already gone past that step.
+ */
+static int apl_flash_bind(struct udevice *dev)
+{
+   if (CONFIG_IS_ENABLED(OF_PLATDATA)) {
+   struct dm_spi_slave_platdata *plat;
+   struct udevice *spi;
+   int ret;
+
+   ret = uclass_first_device_err(UCLASS_SPI, &spi);
+   if (ret)
+   return ret;
+   dev->parent = spi;
+
+   plat = calloc(sizeof(*plat), 

[U-Boot] [PATCH v5 024/101] sandbox: Add PCI driver and test for p2sb

2019-11-24 Thread Simon Glass
Add a sandbox driver and PCI-device emulator for p2sb. Also add a test
which uses a simple 'adder' driver to test the p2sb functionality.

Signed-off-by: Simon Glass 
---

Changes in v5: None
Changes in v4:
- Drop change to message about a missing uclass
- Drop empty operations struct since p2sb does not need it
- Drop pmic_pm8916 driver name and use a sandbox name instead
- Split out mmio changes into a separate patch

Changes in v3:
- Fix build errors in sandbox_spl, etc

Changes in v2: None

 arch/sandbox/dts/test.dts  |  13 ++
 arch/sandbox/include/asm/test.h|   1 +
 configs/sandbox64_defconfig|   2 +
 configs/sandbox_defconfig  |   3 +-
 configs/sandbox_flattree_defconfig |   3 +
 configs/sandbox_spl_defconfig  |   2 +
 configs/tools-only_defconfig   |   2 +
 drivers/misc/Makefile  |   2 +
 drivers/misc/p2sb_emul.c   | 272 +
 drivers/misc/p2sb_sandbox.c|  40 +
 drivers/misc/sandbox_adder.c   |  60 +++
 test/dm/Makefile   |   1 +
 test/dm/p2sb.c |  28 +++
 13 files changed, 428 insertions(+), 1 deletion(-)
 create mode 100644 drivers/misc/p2sb_emul.c
 create mode 100644 drivers/misc/p2sb_sandbox.c
 create mode 100644 drivers/misc/sandbox_adder.c
 create mode 100644 test/dm/p2sb.c

diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 99905677ab..9c8c4e2709 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -471,6 +471,16 @@
   0x01000810 0 0 0 0>;
sandbox,emul = <&swap_case_emul0_1>;
};
+   p2sb-pci@2,0 {
+   compatible = "sandbox,p2sb";
+   reg = <0x02001010 0 0 0 0>;
+   sandbox,emul = <&p2sb_emul>;
+
+   adder {
+   intel,p2sb-port-id = <3>;
+   compatible = "sandbox,adder";
+   };
+   };
pci@1e,0 {
compatible = "sandbox,pmc";
reg = <0xf000 0 0 0 0>;
@@ -502,6 +512,9 @@
swap_case_emul0_1f: emul0@1f,0 {
compatible = "sandbox,swap-case";
};
+   p2sb_emul: emul@2,0 {
+   compatible = "sandbox,p2sb-emul";
+   };
pmc_emul1e: emul@1e,0 {
compatible = "sandbox,pmc-emul";
};
diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h
index fa40d21f3f..fdb0ecfed1 100644
--- a/arch/sandbox/include/asm/test.h
+++ b/arch/sandbox/include/asm/test.h
@@ -14,6 +14,7 @@
 #define SANDBOX_PCI_VENDOR_ID  0x1234
 #define SANDBOX_PCI_SWAP_CASE_EMUL_ID  0x5678
 #define SANDBOX_PCI_PMC_EMUL_ID0x5677
+#define SANDBOX_PCI_P2SB_EMUL_ID   0x5676
 #define SANDBOX_PCI_CLASS_CODE PCI_CLASS_CODE_COMM
 #define SANDBOX_PCI_CLASS_SUB_CODE PCI_CLASS_SUB_CODE_COMM_SERIAL
 
diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig
index 716096abc5..229e268972 100644
--- a/configs/sandbox64_defconfig
+++ b/configs/sandbox64_defconfig
@@ -83,6 +83,8 @@ CONFIG_DEVRES=y
 CONFIG_DEBUG_DEVRES=y
 CONFIG_ADC=y
 CONFIG_ADC_SANDBOX=y
+CONFIG_AXI=y
+CONFIG_AXI_SANDBOX=y
 CONFIG_CLK=y
 CONFIG_CPU=y
 CONFIG_DM_DEMO=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 5a3c4f151d..f3d5c2319a 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -132,6 +132,8 @@ CONFIG_CROS_EC_I2C=y
 CONFIG_CROS_EC_LPC=y
 CONFIG_CROS_EC_SANDBOX=y
 CONFIG_CROS_EC_SPI=y
+CONFIG_IRQ=y
+CONFIG_P2SB=y
 CONFIG_PWRSEQ=y
 CONFIG_SPL_PWRSEQ=y
 CONFIG_I2C_EEPROM=y
@@ -151,7 +153,6 @@ CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCI_SANDBOX=y
-CONFIG_P2SB=y
 CONFIG_PHY=y
 CONFIG_PHY_SANDBOX=y
 CONFIG_PINCTRL=y
diff --git a/configs/sandbox_flattree_defconfig 
b/configs/sandbox_flattree_defconfig
index 774c278bce..ab4d26d012 100644
--- a/configs/sandbox_flattree_defconfig
+++ b/configs/sandbox_flattree_defconfig
@@ -67,6 +67,8 @@ CONFIG_DEVRES=y
 CONFIG_DEBUG_DEVRES=y
 CONFIG_ADC=y
 CONFIG_ADC_SANDBOX=y
+CONFIG_AXI=y
+CONFIG_AXI_SANDBOX=y
 CONFIG_CLK=y
 CONFIG_CLK_COMPOSITE_CCF=y
 CONFIG_SANDBOX_CLK_CCF=y
@@ -117,6 +119,7 @@ CONFIG_PCI=y
 CONFIG_DM_PCI=y
 CONFIG_DM_PCI_COMPAT=y
 CONFIG_PCI_SANDBOX=y
+CONFIG_P2SB=y
 CONFIG_PHY=y
 CONFIG_PHY_SANDBOX=y
 CONFIG_PINCTRL=y
diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig
index 478e4bd9d4..0dea858eda 100644
--- a/configs/sandbox_spl_defconfig
+++ b/configs/sandbox_spl_defconfig
@@ -88,6 +88,8 @@ CONFIG_DEBUG_DEVRES=y
 # CONFIG_SPL_SIMPLE_BUS is not set
 CONFIG_ADC=y
 CONFIG_ADC_SANDBOX=y
+CONFIG_AXI=y
+CONFIG_AXI_SANDBOX=y
 CONFIG_CLK=y
 CONFIG_CPU=y
 CONFIG_DM_DEMO=y
diff --git a/configs/tools-only_defconfig b/configs/tools-only_defconfig
index e

[U-Boot] [PATCH v5 078/101] x86: Enable pinctrl in SPL and TPL

2019-11-24 Thread Simon Glass
If these phases are used we typically want to enable pinctrl in then, so
that pad setup and GPIO access are possible.

Signed-off-by: Simon Glass 
---

Changes in v5:
- Correct build error in chromebook_samus_tpl

Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/Kconfig   | 2 ++
 configs/chromebook_samus_tpl_defconfig | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/arch/Kconfig b/arch/Kconfig
index 54de91afb3..ae9c93ed7b 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -193,6 +193,7 @@ config X86
imply SPL_OF_LIBFDT
imply SPL_DRIVERS_MISC_SUPPORT
imply SPL_GPIO_SUPPORT
+   imply SPL_PINCTRL
imply SPL_LIBCOMMON_SUPPORT
imply SPL_LIBGENERIC_SUPPORT
imply SPL_SERIAL_SUPPORT
@@ -206,6 +207,7 @@ config X86
imply TPL_DM
imply TPL_DRIVERS_MISC_SUPPORT
imply TPL_GPIO_SUPPORT
+   imply TPL_PINCTRL
imply TPL_LIBCOMMON_SUPPORT
imply TPL_LIBGENERIC_SUPPORT
imply TPL_SERIAL_SUPPORT
diff --git a/configs/chromebook_samus_tpl_defconfig 
b/configs/chromebook_samus_tpl_defconfig
index fc6ceeac70..44e6d33181 100644
--- a/configs/chromebook_samus_tpl_defconfig
+++ b/configs/chromebook_samus_tpl_defconfig
@@ -73,6 +73,8 @@ CONFIG_SYS_I2C_DW=y
 CONFIG_TPL_MISC=y
 CONFIG_CROS_EC=y
 CONFIG_CROS_EC_LPC=y
+# CONFIG_SPL_PINCTRL is not set
+# CONFIG_TPL_PINCTRL is not set
 CONFIG_SYS_NS16550=y
 CONFIG_SOUND=y
 CONFIG_SOUND_I8254=y
-- 
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[U-Boot] [PATCH v5 095/101] x86: apl: Add a CPU driver

2019-11-24 Thread Simon Glass
Add a bare-bones CPU driver so that CPUs can be probed.

Signed-off-by: Simon Glass 
---

Changes in v5:
- Add L2 cache flush function
- Drop SAFETY_MARGIN

Changes in v4:
- Change apollolake to apl
- Tidy up header guards

Changes in v3:
- Add two more defines for the CPU driver
- Expand comments for BOOT_FROM_FAST_SPI_FLASH

Changes in v2: None

 arch/x86/cpu/apollolake/Makefile   |  2 +
 arch/x86/cpu/apollolake/cpu.c  | 51 ++
 arch/x86/cpu/apollolake/cpu_common.c   | 17 
 arch/x86/include/asm/arch-apollolake/cpu.h | 26 +++
 arch/x86/include/asm/msr-index.h   |  1 +
 5 files changed, 97 insertions(+)
 create mode 100644 arch/x86/cpu/apollolake/cpu.c
 create mode 100644 arch/x86/cpu/apollolake/cpu_common.c
 create mode 100644 arch/x86/include/asm/arch-apollolake/cpu.h

diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile
index 1fde400d77..37e42092ec 100644
--- a/arch/x86/cpu/apollolake/Makefile
+++ b/arch/x86/cpu/apollolake/Makefile
@@ -4,8 +4,10 @@
 
 obj-$(CONFIG_SPL_BUILD) += spl.o
 obj-$(CONFIG_SPL_BUILD) += systemagent.o
+obj-y += cpu_common.o
 
 ifndef CONFIG_TPL_BUILD
+obj-y += cpu.o
 obj-y += punit.o
 endif
 
diff --git a/arch/x86/cpu/apollolake/cpu.c b/arch/x86/cpu/apollolake/cpu.c
new file mode 100644
index 00..089923e85a
--- /dev/null
+++ b/arch/x86/cpu/apollolake/cpu.c
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+struct cpu_apl_priv {
+};
+
+static int apl_get_info(struct udevice *dev, struct cpu_info *info)
+{
+   return cpu_intel_get_info(info, INTEL_BCLK_MHZ);
+}
+
+static int apl_get_count(struct udevice *dev)
+{
+   return 4;
+}
+
+static int cpu_x86_apl_probe(struct udevice *dev)
+{
+   return 0;
+}
+
+static const struct cpu_ops cpu_x86_apl_ops = {
+   .get_desc   = cpu_x86_get_desc,
+   .get_info   = apl_get_info,
+   .get_count  = apl_get_count,
+   .get_vendor = cpu_x86_get_vendor,
+};
+
+static const struct udevice_id cpu_x86_apl_ids[] = {
+   { .compatible = "intel,apl-cpu" },
+   { }
+};
+
+U_BOOT_DRIVER(cpu_x86_apl_drv) = {
+   .name   = "cpu_x86_apl",
+   .id = UCLASS_CPU,
+   .of_match   = cpu_x86_apl_ids,
+   .bind   = cpu_x86_bind,
+   .probe  = cpu_x86_apl_probe,
+   .ops= &cpu_x86_apl_ops,
+   .priv_auto_alloc_size   = sizeof(struct cpu_apl_priv),
+   .flags  = DM_FLAG_PRE_RELOC,
+};
diff --git a/arch/x86/cpu/apollolake/cpu_common.c 
b/arch/x86/cpu/apollolake/cpu_common.c
new file mode 100644
index 00..ba6bda37bc
--- /dev/null
+++ b/arch/x86/cpu/apollolake/cpu_common.c
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#include 
+#include 
+#include 
+
+void cpu_flush_l1d_to_l2(void)
+{
+   struct msr_t msr;
+
+   msr = msr_read(MSR_POWER_MISC);
+   msr.lo |= FLUSH_DL1_L2;
+   msr_write(MSR_POWER_MISC, msr);
+}
diff --git a/arch/x86/include/asm/arch-apollolake/cpu.h 
b/arch/x86/include/asm/arch-apollolake/cpu.h
new file mode 100644
index 00..4a4b27daa9
--- /dev/null
+++ b/arch/x86/include/asm/arch-apollolake/cpu.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2019 Google LLC
+ */
+
+#ifndef _ASM_ARCH_CPU_H
+#define _ASM_ARCH_CPU_H
+
+/* Common Timer Copy (CTC) frequency - 19.2MHz */
+#define CTC_FREQ   1920
+
+/*
+ * Set to true to use the fast SPI driver to boot, instead of mapped SPI.
+ * You also need to enable CONFIG_APL_SPI_FLASH_BOOT.
+ */
+#define BOOT_FROM_FAST_SPI_FLASH   false
+
+#define MAX_PCIE_PORTS 6
+#define CLKREQ_DISABLED0xf
+
+#ifndef __ASSEMBLY__
+/* Flush L1D to L2 */
+void cpu_flush_l1d_to_l2(void);
+#endif
+
+#endif /* _ASM_ARCH_CPU_H */
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 79a9369de1..246c14f815 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -70,6 +70,7 @@
 #define MSR_IA32_BBL_CR_CTL0x0119
 #define MSR_IA32_BBL_CR_CTL3   0x011e
 #define MSR_POWER_MISC 0x0120
+#define  FLUSH_DL1_L2  (1 << 8)
 #define ENABLE_ULFM_AUTOCM_MASK(1 << 2)
 #define ENABLE_INDP_AUTOCM_MASK(1 << 3)
 
-- 
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[U-Boot] [PATCH v5 055/101] x86: Update .dtsi file for FSP2

2019-11-24 Thread Simon Glass
Include the IFWI section and the FSP-M binary. The FSP-T binary is not
currently used, as CAR is set up manually.

Also drop the FSP binary as this relates only to FSP1.

Reviewed-by: Bin Meng 
Signed-off-by: Simon Glass 
---

Changes in v5: None
Changes in v4: None
Changes in v3:
- Add FSP-S and VBT also
- Drop VBT as we already have it elsewhere

Changes in v2: None

 arch/x86/dts/u-boot.dtsi | 32 +++-
 1 file changed, 31 insertions(+), 1 deletion(-)

diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
index 850fe3ac11..14e3c13072 100644
--- a/arch/x86/dts/u-boot.dtsi
+++ b/arch/x86/dts/u-boot.dtsi
@@ -100,12 +100,42 @@
offset = ;
};
 #endif
-#ifdef CONFIG_HAVE_FSP
+#ifdef CONFIG_FSP_VERSION1
intel-fsp {
filename = CONFIG_FSP_FILE;
offset = ;
};
 #endif
+#ifdef CONFIG_FSP_VERSION2
+   intel-descriptor {
+   filename = CONFIG_FLASH_DESCRIPTOR_FILE;
+   };
+   intel-ifwi {
+   filename = CONFIG_IFWI_INPUT_FILE;
+   convert-fit;
+
+   section {
+   size = <0x8000>;
+   ifwi-replace;
+   ifwi-subpart = "IBBP";
+   ifwi-entry = "IBBL";
+   u-boot-tpl {
+   };
+   x86-start16-tpl {
+   offset = <0x7800>;
+   };
+   x86-reset16-tpl {
+   offset = <0x7ff0>;
+   };
+   };
+   };
+   intel-fsp-m {
+   filename = CONFIG_FSP_FILE_M;
+   };
+   intel-fsp-s {
+   filename = CONFIG_FSP_FILE_S;
+   };
+#endif
 #ifdef CONFIG_HAVE_CMC
intel-cmc {
filename = CONFIG_CMC_FILE;
-- 
2.24.0.432.g9d3f5f5b63-goog

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[U-Boot] [PATCH v5 027/101] x86: Define the SPL image start

2019-11-24 Thread Simon Glass
Define this symbol so that we can use binman symbols correctly.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/x86/cpu/u-boot-spl.lds | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/x86/cpu/u-boot-spl.lds b/arch/x86/cpu/u-boot-spl.lds
index c1e9bfbf66..e6c22895b3 100644
--- a/arch/x86/cpu/u-boot-spl.lds
+++ b/arch/x86/cpu/u-boot-spl.lds
@@ -17,7 +17,10 @@ SECTIONS
 
. = IMAGE_TEXT_BASE;/* Location of bootcode in flash */
__text_start = .;
-   .text  : { *(.text*); }
+   .text  : {
+   __image_copy_start = .;
+   *(.text*);
+   }
 
. = ALIGN(4);
 
-- 
2.24.0.432.g9d3f5f5b63-goog

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[U-Boot] [PATCH v5 084/101] x86: apl: Add PMC driver

2019-11-24 Thread Simon Glass
Add a driver for the Apollo Lake SoC. It supports the basic operations and
can use device tree or of-platdata.

Signed-off-by: Simon Glass 
---

Changes in v5: None
Changes in v4:
- Fix Makefile copyright message
- Fix incorrect mask check in pmc_gpe_init()
- Switch over to use pinctrl for pad init/config
- Tidy up header guards
- Use pci_ofplat_get_devfn()
- apollolake -> Apollo Lake

Changes in v3:
- Use pci_get_devfn()

Changes in v2: None

 arch/x86/cpu/apollolake/Makefile  |   5 +
 arch/x86/cpu/apollolake/pmc.c | 216 ++
 arch/x86/include/asm/arch-apollolake/pm.h |  19 ++
 drivers/power/acpi_pmc/acpi-pmc-uclass.c  |  56 ++
 4 files changed, 296 insertions(+)
 create mode 100644 arch/x86/cpu/apollolake/Makefile
 create mode 100644 arch/x86/cpu/apollolake/pmc.c
 create mode 100644 arch/x86/include/asm/arch-apollolake/pm.h

diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile
new file mode 100644
index 00..5e136b6515
--- /dev/null
+++ b/arch/x86/cpu/apollolake/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2019 Google LLC
+
+obj-y += pmc.o
diff --git a/arch/x86/cpu/apollolake/pmc.c b/arch/x86/cpu/apollolake/pmc.c
new file mode 100644
index 00..683c6082f2
--- /dev/null
+++ b/arch/x86/cpu/apollolake/pmc.c
@@ -0,0 +1,216 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 Intel Corporation.
+ * Copyright 2019 Google LLC
+ *
+ * Modified from coreboot pmclib.c, pmc.c and pmutil.c
+ */
+
+#define LOG_CATEGORY UCLASS_ACPI_PMC
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define GPIO_GPE_CFG   0x1050
+
+/* Memory mapped IO registers behind PMC_BASE_ADDRESS */
+#define PRSTS  0x1000
+#define GEN_PMCON1 0x1020
+#define  COLD_BOOT_STS BIT(27)
+#define  COLD_RESET_STSBIT(26)
+#define  WARM_RESET_STSBIT(25)
+#define  GLOBAL_RESET_STS  BIT(24)
+#define  SRS   BIT(20)
+#define  MS4V  BIT(18)
+#define  RPS   BIT(2)
+#define GEN_PMCON1_CLR1_BITS   (COLD_BOOT_STS | COLD_RESET_STS | \
+WARM_RESET_STS | GLOBAL_RESET_STS | \
+SRS | MS4V)
+#define GEN_PMCON2 0x1024
+#define GEN_PMCON3 0x1028
+
+/* Offset of TCO registers from ACPI base I/O address */
+#define TCO_REG_OFFSET 0x60
+#define TCO1_STS   0x64
+#define   DMISCI_STS   BIT(9)
+#define   BOOT_STS BIT(18)
+#define TCO2_STS   0x66
+#define TCO1_CNT   0x68
+#define   TCO_LOCK BIT(12)
+#define TCO2_CNT   0x6a
+
+enum {
+   ETR = 0x1048,
+   CF9_LOCK= 1UL << 31,
+   CF9_GLB_RST = 1 << 20,
+};
+
+struct apl_pmc_platdata {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+   struct dtd_intel_apl_pmc dtplat;
+#endif
+   pci_dev_t bdf;
+};
+
+static int apl_pmc_fill_power_state(struct udevice *dev)
+{
+   struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
+
+   upriv->tco1_sts = inw(upriv->acpi_base + TCO1_STS);
+   upriv->tco2_sts = inw(upriv->acpi_base + TCO2_STS);
+
+   upriv->prsts = readl(upriv->pmc_bar0 + PRSTS);
+   upriv->gen_pmcon1 = readl(upriv->pmc_bar0 + GEN_PMCON1);
+   upriv->gen_pmcon2 = readl(upriv->pmc_bar0 + GEN_PMCON2);
+   upriv->gen_pmcon3 = readl(upriv->pmc_bar0 + GEN_PMCON3);
+
+   return 0;
+}
+
+static int apl_prev_sleep_state(struct udevice *dev, int prev_sleep_state)
+{
+   struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
+
+   /* WAK_STS bit will not be set when waking from G3 state */
+   if (!(upriv->pm1_sts & WAK_STS) &&
+   (upriv->gen_pmcon1 & COLD_BOOT_STS))
+   prev_sleep_state = ACPI_S5;
+
+   return prev_sleep_state;
+}
+
+static int apl_disable_tco(struct udevice *dev)
+{
+   struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
+
+   pmc_disable_tco_base(upriv->acpi_base + TCO_REG_OFFSET);
+
+   return 0;
+}
+
+static int apl_global_reset_set_enable(struct udevice *dev, bool enable)
+{
+   struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
+
+   if (enable)
+   setbits_le32(upriv->pmc_bar0 + ETR, CF9_GLB_RST);
+   else
+   clrbits_le32(upriv->pmc_bar0 + ETR, CF9_GLB_RST);
+
+   return 0;
+}
+
+int apl_pmc_ofdata_to_uc_platdata(struct udevice *dev)
+{
+   struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
+   struct apl_pmc_platdata *plat = dev_get_platdata(dev);
+
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+   u32 base[6];
+   int size;
+   int ret;
+
+   ret = dev_read_u32_array(dev, "early-regs", base, ARRAY_SIZE(base));
+   if (ret)
+   return log_msg_ret("Missing/short early-regs", ret);
+   upriv->pmc_bar0 = (void *)base[0];
+   upriv->pmc_bar2 = (void *)base[2];
+   upriv->acpi_base = base[

[U-Boot] [PATCH v5 053/101] x86: Disable microcode section for FSP2

2019-11-24 Thread Simon Glass
At present we don't support loading microcode with FSP2. The correct way
to do this is by adding it to the FIT. For now, disable including
microcode in the image.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v5: None
Changes in v4: None
Changes in v3:
- Drop unnecessary #else part of CONFIG_HAVE_MICROCODE

Changes in v2: None

 arch/x86/Kconfig | 4 
 arch/x86/dts/u-boot.dtsi | 7 +++
 2 files changed, 11 insertions(+)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 3dde26ca93..a1c5f5526c 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -588,6 +588,10 @@ config HAVE_REFCODE
   broadwell) U-Boot will be missing some critical setup steps.
   Various peripherals may fail to work.
 
+config HAVE_MICROCODE
+   bool
+   default y if !FSP_VERSION2
+
 config SMP
bool "Enable Symmetric Multiprocessing"
default n
diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
index 33441c7c80..850fe3ac11 100644
--- a/arch/x86/dts/u-boot.dtsi
+++ b/arch/x86/dts/u-boot.dtsi
@@ -37,11 +37,13 @@
};
 #endif
 #ifdef CONFIG_TPL
+#ifdef CONFIG_HAVE_MICROCODE
u-boot-tpl-with-ucode-ptr {
offset = ;
};
u-boot-tpl-dtb {
};
+#endif
u-boot-spl {
offset = ;
};
@@ -77,11 +79,16 @@
offset = ;
};
 #endif
+#ifdef CONFIG_HAVE_MICROCODE
u-boot-dtb-with-ucode {
};
u-boot-ucode {
align = <16>;
};
+#else
+   u-boot-dtb {
+   };
+#endif
 #ifdef CONFIG_HAVE_X86_FIT
intel-fit {
};
-- 
2.24.0.432.g9d3f5f5b63-goog

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[U-Boot] [PATCH v5 056/101] x86: Add an option to control the position of U-Boot

2019-11-24 Thread Simon Glass
The existing work-around for positioning U-Boot in the ROM when it
actually runs from RAM still exists and there is not obvious way to change
this.

Add a proper Kconfig option to handle this case. This also adds a new bool
property to indicate whether CONFIG_SYS_TEXT_BASE exists.

Signed-off-by: Simon Glass 
---

Changes in v5: None
Changes in v4:
- Rename option to HAVE_SYS_TEXT_BASE

Changes in v3: None
Changes in v2: None

 Kconfig|  9 ++---
 arch/x86/Kconfig   |  5 +
 arch/x86/dts/u-boot.dtsi   | 18 +++---
 configs/chromebook_samus_tpl_defconfig |  1 +
 configs/qemu-x86_64_defconfig  |  1 +
 5 files changed, 16 insertions(+), 18 deletions(-)

diff --git a/Kconfig b/Kconfig
index e22417ec44..33198ff798 100644
--- a/Kconfig
+++ b/Kconfig
@@ -544,9 +544,14 @@ config SYS_EXTRA_OPTIONS
  configuration to Kconfig. Since this option will be removed sometime,
  new boards should not use this option.
 
-config SYS_TEXT_BASE
+config HAVE_SYS_TEXT_BASE
+   bool
depends on !NIOS2 && !XTENSA
depends on !EFI_APP
+   default y
+
+config SYS_TEXT_BASE
+   depends on HAVE_SYS_TEXT_BASE
default 0x8080 if ARCH_OMAP2PLUS || ARCH_K3
default 0x4a00 if ARCH_SUNXI && !MACH_SUN9I && !MACH_SUN8I_V3S
default 0x2a00 if ARCH_SUNXI && MACH_SUN9I
@@ -555,8 +560,6 @@ config SYS_TEXT_BASE
help
  The address in memory that U-Boot will be running from, initially.
 
-
-
 config SYS_CLK_FREQ
depends on ARC || ARCH_SUNXI || MPC83xx
int "CPU clock frequency"
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index a1c5f5526c..e105fda2f2 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -899,4 +899,9 @@ config CACHE_QOS_SIZE_PER_BIT
depends on INTEL_CAR_CQOS
default 0x2 # 128 KB
 
+config X86_OFFSET_U_BOOT
+   hex "Offset of U-Boot in ROM image"
+   depends on HAVE_SYS_TEXT_BASE
+   default SYS_TEXT_BASE
+
 endmenu
diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
index 14e3c13072..d84c64880a 100644
--- a/arch/x86/dts/u-boot.dtsi
+++ b/arch/x86/dts/u-boot.dtsi
@@ -50,7 +50,7 @@
u-boot-spl-dtb {
};
u-boot {
-   offset = ;
+   offset = ;
};
 #elif defined(CONFIG_SPL)
u-boot-spl-with-ucode-ptr {
@@ -60,23 +60,11 @@
type = "u-boot-dtb-with-ucode";
};
u-boot {
-   /*
-* TODO(s...@chromium.org):
-* Normally we use CONFIG_SYS_TEXT_BASE as the flash offset. But
-* for boards with textbase in SDRAM we cannot do this. Just use
-* an assumed-valid value (1MB before the end of flash) here so
-* that we can actually build an image for coreboot, etc.
-* We need a better solution, perhaps a separate Kconfig.
-*/
-#if CONFIG_SYS_TEXT_BASE == 0x111
-   offset = <0xfff0>;
-#else
-   offset = ;
-#endif
+   offset = ;
};
 #else
u-boot-with-ucode-ptr {
-   offset = ;
+   offset = ;
};
 #endif
 #ifdef CONFIG_HAVE_MICROCODE
diff --git a/configs/chromebook_samus_tpl_defconfig 
b/configs/chromebook_samus_tpl_defconfig
index df1eed8986..fc6ceeac70 100644
--- a/configs/chromebook_samus_tpl_defconfig
+++ b/configs/chromebook_samus_tpl_defconfig
@@ -16,6 +16,7 @@ CONFIG_HAVE_REFCODE=y
 CONFIG_SMP=y
 CONFIG_HAVE_VGA_BIOS=y
 CONFIG_SPL_TEXT_BASE=0xffe7
+CONFIG_X86_OFFSET_U_BOOT=0xfff0
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_SHOW_BOOT_PROGRESS=y
diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig
index 0990628007..b2360bfd7b 100644
--- a/configs/qemu-x86_64_defconfig
+++ b/configs/qemu-x86_64_defconfig
@@ -13,6 +13,7 @@ CONFIG_SMP=y
 CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_GENERATE_MP_TABLE=y
 CONFIG_GENERATE_ACPI_TABLE=y
+CONFIG_X86_OFFSET_U_BOOT=0xfff0
 CONFIG_SPL_TEXT_BASE=0xfffd
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BUILD_ROM=y
-- 
2.24.0.432.g9d3f5f5b63-goog

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[U-Boot] [PATCH v5 025/101] x86: Move UCLASS_IRQ into a separate file

2019-11-24 Thread Simon Glass
Update this uclass to support the needs of the Apollo Lake ITSS. It
supports four operations.

Move the uclass into a separate directory so that sandbox can use it too.
Add a new Kconfig to control it and enable this on x86.

Signed-off-by: Simon Glass 
---

Changes in v5: None
Changes in v4:
- Drop itss uclass in Makefile
- Fix 'enabled' typo
- apollolake -> Apollo Lake

Changes in v3:
- Add two more operations to IRQ
- Use the IRQ uclass instead of creating a new ITSS uclass

Changes in v2: None

 arch/Kconfig  |  1 +
 arch/x86/cpu/irq.c|  5 ---
 drivers/misc/Kconfig  |  9 
 drivers/misc/Makefile |  1 +
 drivers/misc/irq-uclass.c | 53 +++
 include/irq.h | 88 +++
 6 files changed, 152 insertions(+), 5 deletions(-)
 create mode 100644 drivers/misc/irq-uclass.c
 create mode 100644 include/irq.h

diff --git a/arch/Kconfig b/arch/Kconfig
index e1f1fcd275..6865e1f909 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -186,6 +186,7 @@ config X86
imply USB_HOST_ETHER
imply PCH
imply RTC_MC146818
+   imply IRQ
 
# Thing to enable for when SPL/TPL are enabled: SPL
imply SPL_DM
diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c
index 3adc155818..cb183496b7 100644
--- a/arch/x86/cpu/irq.c
+++ b/arch/x86/cpu/irq.c
@@ -370,8 +370,3 @@ U_BOOT_DRIVER(irq_router_drv) = {
.probe  = irq_router_probe,
.priv_auto_alloc_size = sizeof(struct irq_router),
 };
-
-UCLASS_DRIVER(irq) = {
-   .id = UCLASS_IRQ,
-   .name   = "irq",
-};
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 71643af9c2..f18aa8f7ba 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -203,6 +203,15 @@ config FSL_SEC_MON
  Security Monitor can be transitioned on any security failures,
  like software violations or hardware security violations.
 
+config IRQ
+   bool "Intel Interrupt controller"
+   depends on X86 || SANDBOX
+   help
+ This enables support for Intel interrupt controllers, including ITSS.
+ Some devices have extra features, such as Apollo Lake. The
+ device has its own uclass since there are several operations
+ involved.
+
 config JZ4780_EFUSE
bool "Ingenic JZ4780 eFUSE support"
depends on ARCH_JZ47XX
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 44c9e3ef08..28313e4a65 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -41,6 +41,7 @@ obj-$(CONFIG_FS_LOADER) += fs_loader.o
 obj-$(CONFIG_GDSYS_IOEP) += gdsys_ioep.o
 obj-$(CONFIG_GDSYS_RXAUI_CTRL) += gdsys_rxaui_ctrl.o
 obj-$(CONFIG_GDSYS_SOC) += gdsys_soc.o
+obj-$(CONFIG_IRQ) += irq-uclass.o
 obj-$(CONFIG_$(SPL_)I2C_EEPROM) += i2c_eeprom.o
 obj-$(CONFIG_IHS_FPGA) += ihs_fpga.o
 obj-$(CONFIG_IMX8) += imx8/
diff --git a/drivers/misc/irq-uclass.c b/drivers/misc/irq-uclass.c
new file mode 100644
index 00..d5182cf149
--- /dev/null
+++ b/drivers/misc/irq-uclass.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2015, Bin Meng 
+ */
+
+#include 
+#include 
+#include 
+
+int irq_route_pmc_gpio_gpe(struct udevice *dev, uint pmc_gpe_num)
+{
+   const struct irq_ops *ops = irq_get_ops(dev);
+
+   if (!ops->route_pmc_gpio_gpe)
+   return -ENOSYS;
+
+   return ops->route_pmc_gpio_gpe(dev, pmc_gpe_num);
+}
+
+int irq_set_polarity(struct udevice *dev, uint irq, bool active_low)
+{
+   const struct irq_ops *ops = irq_get_ops(dev);
+
+   if (!ops->set_polarity)
+   return -ENOSYS;
+
+   return ops->set_polarity(dev, irq, active_low);
+}
+
+int irq_snapshot_polarities(struct udevice *dev)
+{
+   const struct irq_ops *ops = irq_get_ops(dev);
+
+   if (!ops->snapshot_polarities)
+   return -ENOSYS;
+
+   return ops->snapshot_polarities(dev);
+}
+
+int irq_restore_polarities(struct udevice *dev)
+{
+   const struct irq_ops *ops = irq_get_ops(dev);
+
+   if (!ops->restore_polarities)
+   return -ENOSYS;
+
+   return ops->restore_polarities(dev);
+}
+
+UCLASS_DRIVER(irq) = {
+   .id = UCLASS_IRQ,
+   .name   = "irq",
+};
diff --git a/include/irq.h b/include/irq.h
new file mode 100644
index 00..01ded64f16
--- /dev/null
+++ b/include/irq.h
@@ -0,0 +1,88 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * IRQ is a type of interrupt controller used on recent Intel SoC.
+ *
+ * Copyright 2019 Google LLC
+ */
+
+#ifndef __irq_H
+#define __irq_H
+
+/**
+ * struct irq_ops - Operations for the IRQ
+ */
+struct irq_ops {
+   /**
+* route_pmc_gpio_gpe() - Get the GPIO for an event
+*
+* @dev: IRQ device
+* @pmc_gpe_num: Event number to check
+* @returns GPIO for the event, or -ENOENT if none
+*/
+   int (*route_pmc_gpio_gpe)(struct udevice *dev, uint pmc_gpe_num);
+
+   /**
+   

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