[U-Boot] [PATCH V3 01/16] clk: introduce clk_dev_binded

[Peng Fan]

When support Clock Common Framework, U-Boot use dev for
clk tree information, there is no clk->parent. When
support composite clk, it contains mux/gate/divider,
but the mux/gate/divider is not binded with device.
So we could not use dev_get_uclass_priv to get the correct
clk_mux/gate/divider. So add clk_dev_binded to let
choose the correct method.

Signed-off-by: Peng Fan 
---

V3:
 None
V2:
 Rebase

 drivers/clk/clk.c | 8 
 include/clk.h | 9 +
 2 files changed, 17 insertions(+)

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 7d748c9fc7..39b3087067 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -55,3 +55,11 @@ const char *clk_hw_get_name(const struct clk *hw)
 {
return hw->dev->name;
 }
+
+bool clk_dev_binded(struct clk *clk)
+{
+   if (clk->dev && (clk->dev->flags & DM_FLAG_BOUND))
+   return true;
+
+   return false;
+}
diff --git a/include/clk.h b/include/clk.h
index f8f56d9cf0..2ebc905e04 100644
--- a/include/clk.h
+++ b/include/clk.h
@@ -356,4 +356,13 @@ static inline bool clk_valid(struct clk *clk)
  * @return zero on success, or -ENOENT on error
  */
 int clk_get_by_id(ulong id, struct clk **clkp);
+
+/**
+ * clk_dev_binded() - Check whether the clk has a device binded
+ *
+ * @clkA pointer to the clk
+ *
+ * @return true on binded, or false on no
+ */
+bool clk_dev_binded(struct clk *clk);
 #endif
-- 
2.16.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V3 02/16] clk: use clk_dev_binded

[Peng Fan]

Preparing to support composite clk.

Signed-off-by: Peng Fan 
---

V3:
 None
V2:
 Rebase

 drivers/clk/clk-divider.c | 4 ++--
 drivers/clk/clk-mux.c | 6 --
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 6921c76a48..2ed9ed6ab8 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -69,8 +69,8 @@ unsigned long divider_recalc_rate(struct clk *hw, unsigned 
long parent_rate,
 
 static ulong clk_divider_recalc_rate(struct clk *clk)
 {
-   struct clk_divider *divider =
-   to_clk_divider(dev_get_clk_ptr(clk->dev));
+   struct clk_divider *divider = to_clk_divider(clk_dev_binded(clk) ?
+   dev_get_clk_ptr(clk->dev) : clk);
unsigned long parent_rate = clk_get_parent_rate(clk);
unsigned int val;
 
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 3c075aa09e..81d1e7ebee 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -35,7 +35,8 @@
 int clk_mux_val_to_index(struct clk *clk, u32 *table, unsigned int flags,
 unsigned int val)
 {
-   struct clk_mux *mux = to_clk_mux(clk);
+   struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
+   dev_get_clk_ptr(clk->dev) : clk);
int num_parents = mux->num_parents;
 
if (table) {
@@ -61,7 +62,8 @@ int clk_mux_val_to_index(struct clk *clk, u32 *table, 
unsigned int flags,
 
 static u8 clk_mux_get_parent(struct clk *clk)
 {
-   struct clk_mux *mux = to_clk_mux(clk);
+   struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
+   dev_get_clk_ptr(clk->dev) : clk);
u32 val;
 
 #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
-- 
2.16.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V3 03/16] clk: mux: add set parent support

[Peng Fan]

Add set parent support for clk mux

Signed-off-by: Peng Fan 
---

V3:
 None
V2:
 Rebase

 drivers/clk/clk-mux.c| 70 ++--
 include/linux/clk-provider.h |  2 ++
 2 files changed, 70 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 81d1e7ebee..5acc0b8cbd 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -60,7 +60,24 @@ int clk_mux_val_to_index(struct clk *clk, u32 *table, 
unsigned int flags,
return val;
 }
 
-static u8 clk_mux_get_parent(struct clk *clk)
+unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index)
+{
+   unsigned int val = index;
+
+   if (table) {
+   val = table[index];
+   } else {
+   if (flags & CLK_MUX_INDEX_BIT)
+   val = 1 << index;
+
+   if (flags & CLK_MUX_INDEX_ONE)
+   val++;
+   }
+
+   return val;
+}
+
+u8 clk_mux_get_parent(struct clk *clk)
 {
struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
dev_get_clk_ptr(clk->dev) : clk);
@@ -77,8 +94,57 @@ static u8 clk_mux_get_parent(struct clk *clk)
return clk_mux_val_to_index(clk, mux->table, mux->flags, val);
 }
 
+static int clk_fetch_parent_index(struct clk *clk,
+ struct clk *parent)
+{
+   struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
+   dev_get_clk_ptr(clk->dev) : clk);
+
+   int i;
+
+   if (!parent)
+   return -EINVAL;
+
+   for (i = 0; i < mux->num_parents; i++) {
+   if (!strcmp(parent->dev->name, mux->parent_names[i]))
+   return i;
+   }
+
+   return -EINVAL;
+}
+
+static int clk_mux_set_parent(struct clk *clk, struct clk *parent)
+{
+   struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
+   dev_get_clk_ptr(clk->dev) : clk);
+   int index;
+   u32 val;
+   u32 reg;
+
+   index = clk_fetch_parent_index(clk, parent);
+   if (index < 0) {
+   printf("Could not fetch index\n");
+   return index;
+   }
+
+   val = clk_mux_index_to_val(mux->table, mux->flags, index);
+
+   if (mux->flags & CLK_MUX_HIWORD_MASK) {
+   reg = mux->mask << (mux->shift + 16);
+   } else {
+   reg = readl(mux->reg);
+   reg &= ~(mux->mask << mux->shift);
+   }
+   val = val << mux->shift;
+   reg |= val;
+   writel(reg, mux->reg);
+
+   return 0;
+}
+
 const struct clk_ops clk_mux_ops = {
-   .get_rate = clk_generic_get_rate,
+   .get_rate = clk_generic_get_rate,
+   .set_parent = clk_mux_set_parent,
 };
 
 struct clk *clk_hw_register_mux_table(struct device *dev, const char *name,
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 43a25e9c6a..7e44045c16 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -66,6 +66,8 @@ struct clk_mux {
 };
 
 #define to_clk_mux(_clk) container_of(_clk, struct clk_mux, clk)
+extern const struct clk_ops clk_mux_ops;
+u8 clk_mux_get_parent(struct clk *clk);
 
 struct clk_div_table {
unsigned intval;
-- 
2.16.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V3 09/16] clk: imx: gate2 add set rate

[Peng Fan]

Add set rate for imx clk-gate2

Signed-off-by: Peng Fan 
---

V3:
 None
V2:
 Rebase

 drivers/clk/imx/clk-gate2.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/clk/imx/clk-gate2.c b/drivers/clk/imx/clk-gate2.c
index 571be32088..1b9db6e791 100644
--- a/drivers/clk/imx/clk-gate2.c
+++ b/drivers/clk/imx/clk-gate2.c
@@ -60,7 +60,18 @@ static int clk_gate2_disable(struct clk *clk)
return 0;
 }
 
+static ulong clk_gate2_set_rate(struct clk *clk, ulong rate)
+{
+   struct clk *parent = clk_get_parent(clk);
+
+   if (parent)
+   return clk_set_rate(parent, rate);
+
+   return -ENODEV;
+}
+
 static const struct clk_ops clk_gate2_ops = {
+   .set_rate = clk_gate2_set_rate,
.enable = clk_gate2_enable,
.disable = clk_gate2_disable,
.get_rate = clk_generic_get_rate,
-- 
2.16.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V3 12/16] clk: add composite clk support

[Peng Fan]

Import clk composite clk support from Linux Kernel 5.1-rc5

Signed-off-by: Peng Fan 
---

V3:
 None
V2:
 Rebase

 drivers/clk/Kconfig  |  14 
 drivers/clk/Makefile |   1 +
 drivers/clk/clk-composite.c  | 160 +++
 include/linux/clk-provider.h |  22 ++
 4 files changed, 197 insertions(+)
 create mode 100644 drivers/clk/clk-composite.c

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 5e92446c18..a3f0171b45 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -53,6 +53,13 @@ config SPL_CLK_CCF
  Enable this option if you want to (re-)use the Linux kernel's Common
  Clock Framework [CCF] code in U-Boot's SPL.
 
+config SPL_CLK_COMPOSITE_CCF
+   bool "SPL Common Clock Framework [CCF] composite clk support "
+   depends on SPL_CLK_CCF
+   help
+ Enable this option if you want to (re-)use the Linux kernel's Common
+ Clock Framework [CCF] composite code in U-Boot's SPL.
+
 config CLK_CCF
bool "Common Clock Framework [CCF] support "
depends on CLK_IMX6Q || SANDBOX_CLK_CCF
@@ -60,6 +67,13 @@ config CLK_CCF
  Enable this option if you want to (re-)use the Linux kernel's Common
  Clock Framework [CCF] code in U-Boot's clock driver.
 
+config CLK_COMPOSITE_CCF
+   bool "Common Clock Framework [CCF] composite clk support "
+   depends on CLK_CCF
+   help
+ Enable this option if you want to (re-)use the Linux kernel's Common
+ Clock Framework [CCF] composite code in U-Boot's clock driver.
+
 config CLK_STM32F
bool "Enable clock driver support for STM32F family"
depends on CLK && (STM32F7 || STM32F4)
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 39154eca59..68aabe1ca9 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_rate.o
 obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_factor.o
 obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk.o clk-divider.o clk-mux.o clk-gate.o
 obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk-fixed-factor.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_COMPOSITE_CCF) += clk-composite.o
 
 obj-y += analogbits/
 obj-y += imx/
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
new file mode 100644
index 00..a5626c33d1
--- /dev/null
+++ b/drivers/clk/clk-composite.c
@@ -0,0 +1,160 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2013 NVIDIA CORPORATION.  All rights reserved.
+ * Copyright 2019 NXP
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "clk.h"
+
+#define UBOOT_DM_CLK_COMPOSITE "clk_composite"
+
+static u8 clk_composite_get_parent(struct clk *clk)
+{
+   struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ?
+   (struct clk *)dev_get_clk_ptr(clk->dev) : clk);
+   struct clk *mux = composite->mux;
+
+   return clk_mux_get_parent(mux);
+}
+
+static int clk_composite_set_parent(struct clk *clk, struct clk *parent)
+{
+   struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ?
+   (struct clk *)dev_get_clk_ptr(clk->dev) : clk);
+   const struct clk_ops *mux_ops = composite->mux_ops;
+   struct clk *mux = composite->mux;
+
+   return mux_ops->set_parent(mux, parent);
+}
+
+static unsigned long clk_composite_recalc_rate(struct clk *clk)
+{
+   struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ?
+   (struct clk *)dev_get_clk_ptr(clk->dev) : clk);
+   const struct clk_ops *rate_ops = composite->rate_ops;
+   struct clk *rate = composite->rate;
+
+   return rate_ops->get_rate(rate);
+}
+
+static ulong clk_composite_set_rate(struct clk *clk, unsigned long rate)
+{
+   struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ?
+   (struct clk *)dev_get_clk_ptr(clk->dev) : clk);
+   const struct clk_ops *rate_ops = composite->rate_ops;
+   struct clk *clk_rate = composite->rate;
+
+   return rate_ops->set_rate(clk_rate, rate);
+}
+
+static int clk_composite_enable(struct clk *clk)
+{
+   struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ?
+   (struct clk *)dev_get_clk_ptr(clk->dev) : clk);
+   const struct clk_ops *gate_ops = composite->gate_ops;
+   struct clk *gate = composite->gate;
+
+   return gate_ops->enable(gate);
+}
+
+static int clk_composite_disable(struct clk *clk)
+{
+   struct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ?
+   (struct clk *)dev_get_clk_ptr(clk->dev) : clk);
+   const struct clk_ops *gate_ops = composite->gate_ops;
+   struct clk *gate = composite->gate;
+
+   gate_ops->disable(gate);
+
+   return 0;
+}
+
+struct clk_ops clk_composite_ops = {
+   /* This will be set according to clk_register_composite */
+};
+
+struct clk *clk_register_composite(struct device *dev, con

[U-Boot] [PATCH V3 04/16] clk: export mux/divider ops

[Peng Fan]

Export mux/divider ops and divider_recalc_rate for composite usage

Signed-off-by: Peng Fan 
---

V3:
 None
V2:
 Rebase
 Export divider_recalc_rate

 include/linux/clk-provider.h | 5 +
 1 file changed, 5 insertions(+)

diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 7e44045c16..6d62f862d2 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -96,6 +96,11 @@ struct clk_divider {
 #define CLK_DIVIDER_ROUND_CLOSEST  BIT(4)
 #define CLK_DIVIDER_READ_ONLY  BIT(5)
 #define CLK_DIVIDER_MAX_AT_ZEROBIT(6)
+extern const struct clk_ops clk_divider_ops;
+unsigned long divider_recalc_rate(struct clk *hw, unsigned long parent_rate,
+ unsigned int val,
+ const struct clk_div_table *table,
+ unsigned long flags, unsigned long width);
 
 struct clk_fixed_factor {
struct clk  clk;
-- 
2.16.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V3 07/16] clk: fixed_rate: export clk_fixed_rate

[Peng Fan]

Export the structure for others to use.

Signed-off-by: Peng Fan 
---

V3:
 None
V2:
 Rebase

 drivers/clk/clk_fixed_rate.c | 8 +---
 include/linux/clk-provider.h | 7 +++
 2 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c
index 1fdf8c4e54..08cce0d79b 100644
--- a/drivers/clk/clk_fixed_rate.c
+++ b/drivers/clk/clk_fixed_rate.c
@@ -6,13 +6,7 @@
 #include 
 #include 
 #include 
-
-struct clk_fixed_rate {
-   struct clk clk;
-   unsigned long fixed_rate;
-};
-
-#define to_clk_fixed_rate(dev) ((struct clk_fixed_rate *)dev_get_platdata(dev))
+#include 
 
 static ulong clk_fixed_rate_get_rate(struct clk *clk)
 {
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 8b04ecd7a5..f42df9b90f 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -129,6 +129,13 @@ struct clk_fixed_factor {
 #define to_clk_fixed_factor(_clk) container_of(_clk, struct clk_fixed_factor,\
   clk)
 
+struct clk_fixed_rate {
+   struct clk clk;
+   unsigned long fixed_rate;
+};
+
+#define to_clk_fixed_rate(dev) ((struct clk_fixed_rate *)dev_get_platdata(dev))
+
 int clk_register(struct clk *clk, const char *drv_name, const char *name,
 const char *parent_name);
 
-- 
2.16.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V3 05/16] clk: add clk-gate support

[Peng Fan]

Import clk-gate support from Linux Kernel 5.1-rc5

Signed-off-by: Peng Fan 
---

V2:
 None
V3:
 Rebase

 drivers/clk/Makefile |   2 +-
 drivers/clk/clk-gate.c   | 148 +++
 include/linux/clk-provider.h |  18 ++
 3 files changed, 167 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/clk-gate.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index b7fec605c6..39154eca59 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -7,7 +7,7 @@
 obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o
 obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_rate.o
 obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_factor.o
-obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk.o clk-divider.o clk-mux.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk.o clk-divider.o clk-mux.o clk-gate.o
 obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk-fixed-factor.o
 
 obj-y += analogbits/
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
new file mode 100644
index 00..a3a1fdd3b2
--- /dev/null
+++ b/drivers/clk/clk-gate.c
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2010-2011 Canonical Ltd 
+ * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd 
+ * Copyright 2019 NXP
+ *
+ * Gated clock implementation
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "clk.h"
+
+#define UBOOT_DM_CLK_GATE "clk_gate"
+
+/**
+ * DOC: basic gatable clock which can gate and ungate it's output
+ *
+ * Traits of this clock:
+ * prepare - clk_(un)prepare only ensures parent is (un)prepared
+ * enable - clk_enable and clk_disable are functional & control gating
+ * rate - inherits rate from parent.  No clk_set_rate support
+ * parent - fixed parent.  No clk_set_parent support
+ */
+
+/*
+ * It works on following logic:
+ *
+ * For enabling clock, enable = 1
+ * set2dis = 1 -> clear bit-> set = 0
+ * set2dis = 0 -> set bit  -> set = 1
+ *
+ * For disabling clock, enable = 0
+ * set2dis = 1 -> set bit  -> set = 1
+ * set2dis = 0 -> clear bit-> set = 0
+ *
+ * So, result is always: enable xor set2dis.
+ */
+static void clk_gate_endisable(struct clk *clk, int enable)
+{
+   struct clk_gate *gate = to_clk_gate(clk_dev_binded(clk) ?
+   dev_get_clk_ptr(clk->dev) : clk);
+   int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
+   u32 reg;
+
+   set ^= enable;
+
+   if (gate->flags & CLK_GATE_HIWORD_MASK) {
+   reg = BIT(gate->bit_idx + 16);
+   if (set)
+   reg |= BIT(gate->bit_idx);
+   } else {
+   reg = readl(gate->reg);
+
+   if (set)
+   reg |= BIT(gate->bit_idx);
+   else
+   reg &= ~BIT(gate->bit_idx);
+   }
+
+   writel(reg, gate->reg);
+}
+
+static int clk_gate_enable(struct clk *clk)
+{
+   clk_gate_endisable(clk, 1);
+
+   return 0;
+}
+
+static int clk_gate_disable(struct clk *clk)
+{
+   clk_gate_endisable(clk, 0);
+
+   return 0;
+}
+
+int clk_gate_is_enabled(struct clk *clk)
+{
+   struct clk_gate *gate = to_clk_gate(clk_dev_binded(clk) ?
+   dev_get_clk_ptr(clk->dev) : clk);
+   u32 reg;
+
+   reg = readl(gate->reg);
+
+   /* if a set bit disables this clk, flip it before masking */
+   if (gate->flags & CLK_GATE_SET_TO_DISABLE)
+   reg ^= BIT(gate->bit_idx);
+
+   reg &= BIT(gate->bit_idx);
+
+   return reg ? 1 : 0;
+}
+
+const struct clk_ops clk_gate_ops = {
+   .enable = clk_gate_enable,
+   .disable = clk_gate_disable,
+   .get_rate = clk_generic_get_rate,
+};
+
+struct clk *clk_register_gate(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags,
+ void __iomem *reg, u8 bit_idx,
+ u8 clk_gate_flags, spinlock_t *lock)
+{
+   struct clk_gate *gate;
+   struct clk *clk;
+   int ret;
+
+   if (clk_gate_flags & CLK_GATE_HIWORD_MASK) {
+   if (bit_idx > 15) {
+   pr_err("gate bit exceeds LOWORD field\n");
+   return ERR_PTR(-EINVAL);
+   }
+   }
+
+   /* allocate the gate */
+   gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+   if (!gate)
+   return ERR_PTR(-ENOMEM);
+
+   /* struct clk_gate assignments */
+   gate->reg = reg;
+   gate->bit_idx = bit_idx;
+   gate->flags = clk_gate_flags;
+
+   clk = &gate->clk;
+
+   ret = clk_register(clk, UBOOT_DM_CLK_GATE, name, parent_name);
+   if (ret) {
+   kfree(gate);
+   return ERR_PTR(ret);
+   }
+
+   return clk;
+}
+
+U_BOOT_DRIVER(clk_gate) = {
+   .name   = UBOOT_DM_CLK_GATE,
+   .id = UCLASS_CLK,
+   .ops= &clk_gate_ops,
+   .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/include/linux

[U-Boot] [PATCH V3 13/16] clk: gate: support sandbox

[Peng Fan]

Introduce io_gate_val for sandbox clk gate test usage

Signed-off-by: Peng Fan 
---

V3:
 None
V2:
 Rebase

 drivers/clk/clk-gate.c   | 11 +++
 include/linux/clk-provider.h |  3 +++
 2 files changed, 14 insertions(+)

diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index a3a1fdd3b2..70b8794554 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -55,7 +55,11 @@ static void clk_gate_endisable(struct clk *clk, int enable)
if (set)
reg |= BIT(gate->bit_idx);
} else {
+#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
+   reg = gate->io_gate_val;
+#else
reg = readl(gate->reg);
+#endif
 
if (set)
reg |= BIT(gate->bit_idx);
@@ -86,7 +90,11 @@ int clk_gate_is_enabled(struct clk *clk)
dev_get_clk_ptr(clk->dev) : clk);
u32 reg;
 
+#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
+   reg = gate->io_gate_val;
+#else
reg = readl(gate->reg);
+#endif
 
/* if a set bit disables this clk, flip it before masking */
if (gate->flags & CLK_GATE_SET_TO_DISABLE)
@@ -128,6 +136,9 @@ struct clk *clk_register_gate(struct device *dev, const 
char *name,
gate->reg = reg;
gate->bit_idx = bit_idx;
gate->flags = clk_gate_flags;
+#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
+   gate->io_gate_val = *(u32 *)reg;
+#endif
 
clk = &gate->clk;
 
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index b9547736ee..02ff1a311a 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -75,6 +75,9 @@ struct clk_gate {
void __iomem*reg;
u8  bit_idx;
u8  flags;
+#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
+   u32 io_gate_val;
+#endif
 };
 
 #define to_clk_gate(_clk) container_of(_clk, struct clk_gate, clk)
-- 
2.16.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V3 06/16] clk: divider set rate supporrt

[Peng Fan]

Signed-off-by: Peng Fan 
---

V3:
 None
V2:
 Rebase

 drivers/clk/clk-divider.c | 88 +++
 1 file changed, 88 insertions(+)

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 2ed9ed6ab8..822e09b084 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -18,6 +18,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include "clk.h"
@@ -86,8 +87,95 @@ static ulong clk_divider_recalc_rate(struct clk *clk)
   divider->flags, divider->width);
 }
 
+static bool _is_valid_table_div(const struct clk_div_table *table,
+   unsigned int div)
+{
+   const struct clk_div_table *clkt;
+
+   for (clkt = table; clkt->div; clkt++)
+   if (clkt->div == div)
+   return true;
+   return false;
+}
+
+static bool _is_valid_div(const struct clk_div_table *table, unsigned int div,
+ unsigned long flags)
+{
+   if (flags & CLK_DIVIDER_POWER_OF_TWO)
+   return is_power_of_2(div);
+   if (table)
+   return _is_valid_table_div(table, div);
+   return true;
+}
+
+static unsigned int _get_table_val(const struct clk_div_table *table,
+  unsigned int div)
+{
+   const struct clk_div_table *clkt;
+
+   for (clkt = table; clkt->div; clkt++)
+   if (clkt->div == div)
+   return clkt->val;
+   return 0;
+}
+
+static unsigned int _get_val(const struct clk_div_table *table,
+unsigned int div, unsigned long flags, u8 width)
+{
+   if (flags & CLK_DIVIDER_ONE_BASED)
+   return div;
+   if (flags & CLK_DIVIDER_POWER_OF_TWO)
+   return __ffs(div);
+   if (flags & CLK_DIVIDER_MAX_AT_ZERO)
+   return (div == clk_div_mask(width) + 1) ? 0 : div;
+   if (table)
+   return  _get_table_val(table, div);
+   return div - 1;
+}
+int divider_get_val(unsigned long rate, unsigned long parent_rate,
+   const struct clk_div_table *table, u8 width,
+   unsigned long flags)
+{
+   unsigned int div, value;
+
+   div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
+
+   if (!_is_valid_div(table, div, flags))
+   return -EINVAL;
+
+   value = _get_val(table, div, flags, width);
+
+   return min_t(unsigned int, value, clk_div_mask(width));
+}
+
+static ulong clk_divider_set_rate(struct clk *clk, unsigned long rate)
+{
+   struct clk_divider *divider = to_clk_divider(clk_dev_binded(clk) ?
+   dev_get_clk_ptr(clk->dev) : clk);
+   unsigned long parent_rate = clk_get_parent_rate(clk);
+   int value;
+   u32 val;
+
+   value = divider_get_val(rate, parent_rate, divider->table,
+   divider->width, divider->flags);
+   if (value < 0)
+   return value;
+
+   if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
+   val = clk_div_mask(divider->width) << (divider->shift + 16);
+   } else {
+   val = readl(divider->reg);
+   val &= ~(clk_div_mask(divider->width) << divider->shift);
+   }
+   val |= (u32)value << divider->shift;
+   writel(val, divider->reg);
+
+   return clk_get_rate(clk);
+}
+
 const struct clk_ops clk_divider_ops = {
.get_rate = clk_divider_recalc_rate,
+   .set_rate = clk_divider_set_rate,
 };
 
 static struct clk *_register_divider(struct device *dev, const char *name,
-- 
2.16.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V3 11/16] clk-provider: include clk-uclass.h

[Peng Fan]

Because clk-provider use clk_ops, so let's include clk-uclass.h

Signed-off-by: Peng Fan 
---

V3:
 patch moved to before adding composite clock
V2:
 Rebase

 include/linux/clk-provider.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index f42df9b90f..522e73e851 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -8,6 +8,7 @@
  */
 #ifndef __LINUX_CLK_PROVIDER_H
 #define __LINUX_CLK_PROVIDER_H
+#include 
 
 static inline void clk_dm(ulong id, struct clk *clk)
 {
-- 
2.16.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V3 10/16] dm: clk: ignore default settings when node not valid

[Peng Fan]

When the device not binded with a node, we need ignore
the parents and rate settings.

Cc: Simon Glass 
Cc: Jagan Teki 
Cc: Philipp Tomsich 
Cc: Neil Armstrong 
Cc: Andreas Dannenberg 
Signed-off-by: Peng Fan 
---

V3:
 None
V2:
 Rebase

 drivers/clk/clk-uclass.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 85dfe712f5..cee4d912b0 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -285,6 +285,9 @@ int clk_set_defaults(struct udevice *dev)
 {
int ret;
 
+   if (!dev_of_valid(dev))
+   return 0;
+
/* If this not in SPL and pre-reloc state, don't take any action. */
if (!(IS_ENABLED(CONFIG_SPL_BUILD) || (gd->flags & GD_FLG_RELOC)))
return 0;
-- 
2.16.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V3 16/16] test: dm: clk_ccf: test composite clk

[Peng Fan]

Test composite clk with dm ccf

Signed-off-by: Peng Fan 
---

V3:
 None
V2:
 Rebase

 test/dm/clk_ccf.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/test/dm/clk_ccf.c b/test/dm/clk_ccf.c
index 8d397593a3..bbc4b500e8 100644
--- a/test/dm/clk_ccf.c
+++ b/test/dm/clk_ccf.c
@@ -56,6 +56,14 @@ static int dm_test_clk_ccf(struct unit_test_state *uts)
pclk = clk_get_parent(clk);
ut_asserteq_str("pll3_80m", pclk->dev->name);
 
+   /* Test the composite of CCF */
+   ret = clk_get_by_id(SANDBOX_CLK_I2C, &clk);
+   ut_assertok(ret);
+   ut_asserteq_str("i2c", clk->dev->name);
+
+   rate = clk_get_rate(clk);
+   ut_asserteq(rate, 6000);
+
return 1;
 }
 
-- 
2.16.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V3 14/16] configs: sandbox: Enable composite clk

[Peng Fan]

Enable composite clk for sandbox test

Signed-off-by: Peng Fan 
---

V3:
 Moved patch order earlier
V2:
 Rebase

 configs/sandbox_defconfig  | 1 +
 configs/sandbox_flattree_defconfig | 1 +
 2 files changed, 2 insertions(+)

diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index aa09c4571a..7355e3aa1e 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -93,6 +93,7 @@ CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_DM_BOOTCOUNT=y
 CONFIG_DM_BOOTCOUNT_RTC=y
 CONFIG_CLK=y
+CONFIG_CLK_COMPOSITE_CCF=y
 CONFIG_SANDBOX_CLK_CCF=y
 CONFIG_CPU=y
 CONFIG_DM_DEMO=y
diff --git a/configs/sandbox_flattree_defconfig 
b/configs/sandbox_flattree_defconfig
index a70793b7ad..898815fe53 100644
--- a/configs/sandbox_flattree_defconfig
+++ b/configs/sandbox_flattree_defconfig
@@ -66,6 +66,7 @@ CONFIG_DEBUG_DEVRES=y
 CONFIG_ADC=y
 CONFIG_ADC_SANDBOX=y
 CONFIG_CLK=y
+CONFIG_CLK_COMPOSITE_CCF=y
 CONFIG_SANDBOX_CLK_CCF=y
 CONFIG_CPU=y
 CONFIG_DM_DEMO=y
-- 
2.16.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V3 08/16] clk: imx: import clk heplers

[Peng Fan]

Import some clk helpers from Linux Kernel for i.MX8MM usage

Signed-off-by: Peng Fan 
---

V3:
 None
V2:
 Rebase

 drivers/clk/imx/clk.h | 81 +++
 1 file changed, 81 insertions(+)

diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index e6d51830e8..1d480d8722 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -36,6 +36,23 @@ static inline struct clk *imx_clk_gate2(const char *name, 
const char *parent,
shift, 0x3, 0);
 }
 
+static inline struct clk *imx_clk_gate4(const char *name, const char *parent,
+   void __iomem *reg, u8 shift)
+{
+   return clk_register_gate2(NULL, name, parent,
+   CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
+   reg, shift, 0x3, 0);
+}
+
+static inline struct clk *imx_clk_gate4_flags(const char *name,
+   const char *parent, void __iomem *reg, u8 shift,
+   unsigned long flags)
+{
+   return clk_register_gate2(NULL, name, parent,
+   flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
+   reg, shift, 0x3, 0);
+}
+
 static inline struct clk *imx_clk_fixed_factor(const char *name,
const char *parent, unsigned int mult, unsigned int div)
 {
@@ -50,6 +67,14 @@ static inline struct clk *imx_clk_divider(const char *name, 
const char *parent,
reg, shift, width, 0);
 }
 
+static inline struct clk *imx_clk_divider2(const char *name, const char 
*parent,
+   void __iomem *reg, u8 shift, u8 width)
+{
+   return clk_register_divider(NULL, name, parent,
+   CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
+   reg, shift, width, 0);
+}
+
 struct clk *imx_clk_pfd(const char *name, const char *parent_name,
void __iomem *reg, u8 idx);
 
@@ -57,6 +82,16 @@ struct clk *imx_clk_fixup_mux(const char *name, void __iomem 
*reg,
  u8 shift, u8 width, const char * const *parents,
  int num_parents, void (*fixup)(u32 *val));
 
+static inline struct clk *imx_clk_mux_flags(const char *name,
+   void __iomem *reg, u8 shift, u8 width,
+   const char * const *parents, int num_parents,
+   unsigned long flags)
+{
+   return clk_register_mux(NULL, name, parents, num_parents,
+   flags | CLK_SET_RATE_NO_REPARENT, reg, shift,
+   width, 0);
+}
+
 static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
u8 shift, u8 width, const char * const *parents,
int num_parents)
@@ -66,4 +101,50 @@ static inline struct clk *imx_clk_mux(const char *name, 
void __iomem *reg,
width, 0);
 }
 
+static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg,
+   u8 shift, u8 width, const char * const *parents,
+   int num_parents)
+{
+   return clk_register_mux(NULL, name, parents, num_parents,
+   CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
+   reg, shift, width, 0);
+}
+
+static inline struct clk *imx_clk_gate(const char *name, const char *parent,
+   void __iomem *reg, u8 shift)
+{
+   return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
+   shift, 0, NULL);
+}
+
+static inline struct clk *imx_clk_gate_flags(const char *name, const char 
*parent,
+   void __iomem *reg, u8 shift, unsigned long flags)
+{
+   return clk_register_gate(NULL, name, parent, flags | 
CLK_SET_RATE_PARENT, reg,
+   shift, 0, NULL);
+}
+
+static inline struct clk *imx_clk_gate3(const char *name, const char *parent,
+   void __iomem *reg, u8 shift)
+{
+   return clk_register_gate(NULL, name, parent,
+   CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
+   reg, shift, 0, NULL);
+}
+
+struct clk *imx8m_clk_composite_flags(const char *name,
+   const char * const *parent_names,
+   int num_parents, void __iomem *reg, unsigned long flags);
+
+#define __imx8m_clk_composite(name, parent_names, reg, flags) \
+   imx8m_clk_composite_flags(name, parent_names, \
+   ARRAY_SIZE(parent_names), reg, \
+   flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
+
+#define imx8m_clk_composite(name, parent_names, reg) \
+   __imx8m_clk_composite(name, parent_names, reg, 0)
+
+#define imx8m_clk_composite_critical(name, parent_names, reg) \
+   __imx8m_clk_composite(name, parent_names, reg, CLK_IS_CRITICAL)
+
 #endif /* __MACH_IMX_CLK_H */
-- 
2.16.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH V3 15/16] clk: sandbox: add composite clk

[Peng Fan]

Add composite clk to sandbox driver

Signed-off-by: Peng Fan 
---

V3:
 None
V2:
 Rebase

 drivers/clk/clk_sandbox_ccf.c | 80 +++
 include/sandbox-clk.h |  1 +
 2 files changed, 81 insertions(+)

diff --git a/drivers/clk/clk_sandbox_ccf.c b/drivers/clk/clk_sandbox_ccf.c
index edeb0f2cf3..e126f18d8e 100644
--- a/drivers/clk/clk_sandbox_ccf.c
+++ b/drivers/clk/clk_sandbox_ccf.c
@@ -130,6 +130,80 @@ U_BOOT_DRIVER(sandbox_clk_gate2) = {
.ops= &clk_gate2_ops,
 };
 
+static unsigned long sandbox_clk_composite_divider_recalc_rate(struct clk *clk)
+{
+   struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk);
+   struct clk_composite *composite = (struct clk_composite *)clk->data;
+   ulong parent_rate = clk_get_parent_rate(&composite->clk);
+   unsigned int val;
+
+   val = divider->io_divider_val;
+   val >>= divider->shift;
+   val &= clk_div_mask(divider->width);
+
+   return divider_recalc_rate(clk, parent_rate, val, divider->table,
+  divider->flags, divider->width);
+}
+
+static const struct clk_ops sandbox_clk_composite_divider_ops = {
+   .get_rate = sandbox_clk_composite_divider_recalc_rate,
+};
+
+struct clk *sandbox_clk_composite(const char *name,
+ const char * const *parent_names,
+ int num_parents, void __iomem *reg,
+ unsigned long flags)
+{
+   struct clk *clk = ERR_PTR(-ENOMEM);
+   struct clk_divider *div = NULL;
+   struct clk_gate *gate = NULL;
+   struct clk_mux *mux = NULL;
+
+   mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+   if (!mux)
+   goto fail;
+
+   mux->reg = reg;
+   mux->shift = 24;
+   mux->mask = 0x7;
+   mux->num_parents = num_parents;
+   mux->flags = flags;
+   mux->parent_names = parent_names;
+
+   div = kzalloc(sizeof(*div), GFP_KERNEL);
+   if (!div)
+   goto fail;
+
+   div->reg = reg;
+   div->shift = 16;
+   div->width = 3;
+   div->flags = CLK_DIVIDER_ROUND_CLOSEST | flags;
+
+   gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+   if (!gate)
+   goto fail;
+
+   gate->reg = reg;
+   gate->bit_idx = 28;
+   gate->flags = flags;
+
+   clk = clk_register_composite(NULL, name,
+parent_names, num_parents,
+&mux->clk, &clk_mux_ops, &div->clk,
+&sandbox_clk_composite_divider_ops,
+&gate->clk, &clk_gate_ops, flags);
+   if (IS_ERR(clk))
+   goto fail;
+
+   return clk;
+
+fail:
+   kfree(gate);
+   kfree(div);
+   kfree(mux);
+   return ERR_CAST(clk);
+}
+
 /* --- Sandbox Gate --- */
 /* The CCF core driver itself */
 static const struct udevice_id sandbox_clk_ccf_test_ids[] = {
@@ -138,6 +212,7 @@ static const struct udevice_id sandbox_clk_ccf_test_ids[] = 
{
 };
 
 static const char *const usdhc_sels[] = { "pll3_60m", "pll3_80m", };
+static const char *const i2c_sels[] = { "pll3_60m", "pll3_80m", };
 
 static int sandbox_clk_ccf_probe(struct udevice *dev)
 {
@@ -174,6 +249,11 @@ static int sandbox_clk_ccf_probe(struct udevice *dev)
   sandbox_clk_mux("usdhc2_sel", ®, 17, 1, usdhc_sels,
   ARRAY_SIZE(usdhc_sels)));
 
+   reg = BIT(28) | BIT(24) | BIT(16);
+   clk_dm(SANDBOX_CLK_I2C,
+  sandbox_clk_composite("i2c", i2c_sels, ARRAY_SIZE(i2c_sels),
+®, 0));
+
return 0;
 }
 
diff --git a/include/sandbox-clk.h b/include/sandbox-clk.h
index 37c9838f76..f449de1364 100644
--- a/include/sandbox-clk.h
+++ b/include/sandbox-clk.h
@@ -19,6 +19,7 @@ enum {
SANDBOX_CLK_ECSPI1,
SANDBOX_CLK_USDHC1_SEL,
SANDBOX_CLK_USDHC2_SEL,
+   SANDBOX_CLK_I2C,
 };
 
 enum sandbox_pllv3_type {
-- 
2.16.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] rpi: increase SYS_BOOTM_LEN to 64M

[Matthias Brugger]

Hi Laurent,

On 07/06/2019 17:04, Bonnans, Laurent wrote:
> On AArch64, kernel images are not self-decompressing and easily exceed
> the 8MB limit.
> 
> Signed-off-by: Laurent Bonnans 
> ---
>  include/configs/rpi.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/include/configs/rpi.h b/include/configs/rpi.h
> index 9ce41767a9..1a5ae26ae7 100644
> --- a/include/configs/rpi.h
> +++ b/include/configs/rpi.h
> @@ -55,6 +55,7 @@
>  #define CONFIG_SYS_MEMTEST_START 0x0010
>  #define CONFIG_SYS_MEMTEST_END   0x0020
>  #define CONFIG_LOADADDR  0x0020
> +#define CONFIG_SYS_BOOTM_LEN SZ_64M
>  

Sorry for the late reply.
If it's only needed for ARM64 then we should make it set for this architecture,
right?

Next time you send a patch, plese add the maintainers mailinglist. This way I'll
find the patch easier.

Thanks,
Matthias
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] (Offlist) Re: U-Boot/EBBR plugfest at ELC-EU?

[Matthias Brugger]

On 30/07/2019 17:33, Grant Likely wrote:
> 
> 
>>> On 24 Jul 2019, at 14:39, Daniel Kiper  wrote:
>>>
 On Mon, Jul 08, 2019 at 01:27:11PM +, Steve McIntyre wrote:
 On Mon, Jul 08, 2019 at 11:18:56AM +0100, Leif Lindholm wrote:
 On Mon, Jul 08, 2019 at 12:13:07PM +0200, Daniel Kiper wrote:
>> I don't know yet - UEFI Asia plugfest date hasn't been decided yet,
>> and is likely to end up around the same time. And actually another
>> unrelated event too.
>>
>> Certainly, Lyon is a quite convenient train journey from here :)
>>
>> But I'm also happy to look into GRUB issues on 32-bit systems remotely
>> if someone could point me at them.
>
> I am not planning to be at ELC-E but I can help remotely if it is
> needed. However, there is another option. There is pretty good chance
> that I will get a MC slot at LPC. I am looking for people who want to
> talk. The overall plan is to devote this MC for boot stuff with focus
> on security. So, this maybe good place to discuss this. However, I am
> not ARM expert, so, I would like to see Leif and/or Alex or somebody
> else familiar with ARM stuff there too.

 If I can get a ticket, I'm already intending to attend plumbers.

 Registered on the waiting list.
>>
>> Folks, our LPC MC was accepted:
>>  
>> https://linuxplumbersconf.org/event/4/page/34-accepted-microconferences#security
>>  
>> https://www.linuxplumbersconf.org/blog/2019/system-boot-and-security-microconference-accepted-into-2019-linux-plumbers-conference/
>>
>> If you want to discuss something there please put a topic proposal on
>> LPC site. CfP closes on 2nd of August. If you need a pass or invite an
>> expert drop me a line.
> 
> Thanks Daniel,
> 
> It is certainly a worthy discussion topic for LPC. I’ll see if I can draft 
> something for the CfP on Friday. Unfortunately, I may not be at LPC. I’m not 
> even on the waiting list yet.
> 
> Having an LPC topic is separate from the plugfest idea which is intended to 
> be a hacking sprint. I need to make a decision ASAP so I can give the LF an 
> answer by 8th Aug. Who is available Monday at 16:00BST to discuss?
> 

I'll be most probably on holidays and in a tent without my computer.

Regards,
Matthias
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH 1/1] clk: meson: remove duplicate logic

[Neil Armstrong]

On 30/07/2019 23:03, Heinrich Schuchardt wrote:
> First thing we check in meson_clk_set_rate_by_id() is current_rate == rate.
> There is not need to check it again.
> 
> Signed-off-by: Heinrich Schuchardt 
> ---
>  drivers/clk/meson/gxbb.c | 5 +
>  1 file changed, 1 insertion(+), 4 deletions(-)
> 
> diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
> index 2cb53fb92d..abb5337e78 100644
> --- a/drivers/clk/meson/gxbb.c
> +++ b/drivers/clk/meson/gxbb.c
> @@ -823,10 +823,7 @@ static ulong meson_clk_set_rate_by_id(struct clk *clk, 
> unsigned long id,
>   case CLKID_MPLL1:
>   case CLKID_MPLL2:
>   case CLKID_CLK81:
> - if (current_rate != rate)
> - return -EINVAL;
> -
> - return 0;
> + return -EINVAL;
>   case CLKID_VPU:
>   return meson_clk_set_rate_by_id(clk,
>   meson_mux_get_parent(clk, CLKID_VPU), rate,
> --
> 2.20.1
> 

Acked-by: Neil Armstrong 

Applied on u-boot-amlogic

Thanks,
Neil
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH 0/3] amlogic: Add support for Odroid-N2

[Neil Armstrong]

On 29/07/2019 15:45, Neil Armstrong wrote:
> ODROID-N2 is a single board computer manufactured by Hardkernel Co. Ltd
> with the following specifications:
> 
>  - Amlogic S922X ARM Cortex-A53 dual-core + Cortex-A73 quad-core SoC
>  - 4GB DDR4 SDRAM
>  - Gigabit Ethernet
>  - HDMI 2.1 4K/60Hz display
>  - 40-pin GPIO header
>  - 4 x USB 3.0 Host, 1 x USB OTG
>  - eMMC, microSD
>  - Infrared receiver
> 
> This patchset :
> - adds the Odroid-N2 from Linux 5.3-rc1
> - fixes 4GiB memory support
> - adds board support
> 
> The board directory is W400, the name of the Amlogic Reference Design
> of Amlogic G12B with Gigabit boards, which will be used for similar
> boards.
> 
> Changes since v1:
> - Fix typo in README.odroid-n2
> 
> Neil Armstrong (3):
>   ARM: dts: add support for Odroid-N2
>   ARM: meson-g12a: Handle 4GiB DRAM size
>   board: amlogic: add support for Odroid-N2
> 
>  arch/arm/dts/Makefile |   3 +-
>  arch/arm/dts/meson-g12b-odroid-n2.dts | 386 ++
>  arch/arm/dts/meson-g12b.dtsi  |  82 
>  arch/arm/mach-meson/board-g12a.c  |  13 +-
>  board/amlogic/w400/MAINTAINERS|   6 +
>  board/amlogic/w400/Makefile   |   6 +
>  board/amlogic/w400/README.odroid-n2   | 130 ++
>  board/amlogic/w400/README.w400| 130 ++
>  board/amlogic/w400/w400.c |  18 +
>  configs/odroid-n2_defconfig   |  56 +++
>  .../dt-bindings/sound/meson-g12a-tohdmitx.h   |  13 +
>  11 files changed, 836 insertions(+), 7 deletions(-)
>  create mode 100644 arch/arm/dts/meson-g12b-odroid-n2.dts
>  create mode 100644 arch/arm/dts/meson-g12b.dtsi
>  create mode 100644 board/amlogic/w400/MAINTAINERS
>  create mode 100644 board/amlogic/w400/Makefile
>  create mode 100644 board/amlogic/w400/README.odroid-n2
>  create mode 100644 board/amlogic/w400/README.w400
>  create mode 100644 board/amlogic/w400/w400.c
>  create mode 100644 configs/odroid-n2_defconfig
>  create mode 100644 include/dt-bindings/sound/meson-g12a-tohdmitx.h
> 

Applied on u-boot-amlogic

Neil
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] board_r: re-order the board_early_init_r()

[Matthias Brugger]

On 24/07/2019 14:22, Kever Yang wrote:
> 
> On 2019/7/24 下午6:22, Simon Goldschmidt wrote:
>> On Wed, Jul 24, 2019 at 12:01 PM Kever Yang  
>> wrote:
>>> The board_early_init_r() suppose to be called before board_init(),
>>> then the board callback functions in board_r will be:
>>> - board_early_init_r()
>>> - board_init()
>>> - board_late_init()
>> Searching through the code, elixir.bootlin.com gives me 52 definitions
>> of board_early_init_r(). Does this patch break any of those boards
>> when it changes the order of those calls?
> 
> I do have check some of the implement and most of them should be OK, but to be
> honest,
> 
> I'm don't have any of those boards, and not sure if this break any of them, 
> and
> I'm not sure
> 
> if people using this interface have notice it's after the board_init().
> 
> When I try to use this board_early_init_r(), I thought this is before
> board_init(), but it actually
> 
> after the board_init(), that make people confusing.
> 
> I think the _early_ one should be at the first, isn't it?

I agree. Maybe we should rename it to board_post_init?

Regards,
Matthias
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] ARM: dts: Sync Amlogic G12A with Linux 5.3-rc1

[Neil Armstrong]

On 22/07/2019 10:16, Neil Armstrong wrote:
> Sync the Amlogic Meson G12A DT and Bindings file with the Linux 5.3-rc1
> from the commit 5f9e832c1370 ("Linus 5.3-rc1").
> 
> Also remove the meson-g12a-u-boot.dtsi and meson-g12a-u200-u-boot.dtsi,
> now conflicting with the main DT content.
> 
> Signed-off-by: Neil Armstrong 
> ---
>  arch/arm/dts/meson-g12a-u-boot.dtsi|  216 ---
>  arch/arm/dts/meson-g12a-u200-u-boot.dtsi   |   63 -
>  arch/arm/dts/meson-g12a-u200.dts   |  122 +-
>  arch/arm/dts/meson-g12a.dtsi   | 1825 +++-
>  include/dt-bindings/clock/axg-aoclkc.h |7 +-
>  include/dt-bindings/clock/axg-audio-clkc.h |   30 +-
>  include/dt-bindings/clock/g12a-clkc.h  |3 +-
>  7 files changed, 1928 insertions(+), 338 deletions(-)
>  delete mode 100644 arch/arm/dts/meson-g12a-u-boot.dtsi
>  delete mode 100644 arch/arm/dts/meson-g12a-u200-u-boot.dtsi
> 
> diff --git a/arch/arm/dts/meson-g12a-u-boot.dtsi 
> b/arch/arm/dts/meson-g12a-u-boot.dtsi
> deleted file mode 100644
> index 8e0c81f199..00
> --- a/arch/arm/dts/meson-g12a-u-boot.dtsi
> +++ /dev/null
> @@ -1,216 +0,0 @@
> -// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> -/*
> - * Copyright (c) 2019 BayLibre, SAS.
> - * Author: Neil Armstrong 
> - */
> -
> -/ {
> - soc {
> - ethmac: ethernet@ff3f {
> - compatible = "amlogic,meson-axg-dwmac", 
> "snps,dwmac-3.710",
> -  "snps,dwmac";
> - reg = <0x0 0xff3f 0x0 0x1
> -0x0 0xff634540 0x0 0x8>;
> - interrupts = ;
> - interrupt-names = "macirq";
> - clocks = <&clkc CLKID_ETH>,
> -  <&clkc CLKID_FCLK_DIV2>,
> -  <&clkc CLKID_MPLL2>;
> - clock-names = "stmmaceth", "clkin0", "clkin1";
> - status = "disabled";
> -
> - mdio0: mdio {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "snps,dwmac-mdio";
> - };
> - };
> -
> - sd_emmc_a: sd@ffe03000 {
> - compatible = "amlogic,meson-axg-mmc";
> - reg = <0x0 0xffe03000 0x0 0x800>;
> - interrupts = ;
> - status = "disabled";
> - clocks = <&clkc CLKID_SD_EMMC_A>,
> -  <&clkc CLKID_SD_EMMC_A_CLK0>,
> -  <&clkc CLKID_FCLK_DIV2>;
> - clock-names = "core", "clkin0", "clkin1";
> - resets = <&reset RESET_SD_EMMC_A>;
> - };
> -
> - sd_emmc_b: sd@ffe05000 {
> - compatible = "amlogic,meson-axg-mmc";
> - reg = <0x0 0xffe05000 0x0 0x800>;
> - interrupts = ;
> - status = "disabled";
> - clocks = <&clkc CLKID_SD_EMMC_B>,
> -  <&clkc CLKID_SD_EMMC_B_CLK0>,
> -  <&clkc CLKID_FCLK_DIV2>;
> - clock-names = "core", "clkin0", "clkin1";
> - resets = <&reset RESET_SD_EMMC_B>;
> - };
> -
> - sd_emmc_c: mmc@ffe07000 {
> - compatible = "amlogic,meson-axg-mmc";
> - reg = <0x0 0xffe07000 0x0 0x800>;
> - interrupts = ;
> - status = "disabled";
> - clocks = <&clkc CLKID_SD_EMMC_C>,
> -  <&clkc CLKID_SD_EMMC_C_CLK0>,
> -  <&clkc CLKID_FCLK_DIV2>;
> - clock-names = "core", "clkin0", "clkin1";
> - resets = <&reset RESET_SD_EMMC_C>;
> - };
> - };
> -};
> -
> -&periphs_pinctrl {
> - emmc_pins: emmc {
> - mux {
> - groups = "emmc_nand_d0",
> -  "emmc_nand_d1",
> -  "emmc_nand_d2",
> -  "emmc_nand_d3",
> -  "emmc_nand_d4",
> -  "emmc_nand_d5",
> -  "emmc_nand_d6",
> -  "emmc_nand_d7",
> -  "emmc_clk",
> -  "emmc_cmd";
> - function = "emmc";
> - bias-pull-up;
> - };
> - };
> -
> - emmc_ds_pins: emmc-ds {
> - mux {
> - groups = "emmc_nand_ds";
> - function = "emmc";
> - bias-pull-down;
> - };
> - };
> -
> - emmc_clk_gate_pins: emmc_clk_gate {
> - mux {
> - groups = "BOOT_8";
> - function 

[U-Boot] [PATCH] pci_ep: Fix Coverity warning

[Ramon Fried]

Fix the following Coverity warning:
CID 244086:  Incorrect expression  (BAD_COMPARE)
Comparing pointer "ep_bar" against NULL using anything besides == or
is likely to be incorrect.

Fixes: 914026d25848 ("drivers: pci_ep: Introduce UCLASS_PCI_EP uclass")

Signed-off-by: Ramon Fried 
---
 drivers/pci_endpoint/pci_ep-uclass.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci_endpoint/pci_ep-uclass.c 
b/drivers/pci_endpoint/pci_ep-uclass.c
index 2f9c70398d..9f53a9a9b9 100644
--- a/drivers/pci_endpoint/pci_ep-uclass.c
+++ b/drivers/pci_endpoint/pci_ep-uclass.c
@@ -43,7 +43,7 @@ int pci_ep_set_bar(struct udevice *dev, uint func_no, struct 
pci_bar *ep_bar)
int flags = ep_bar->flags;
 
/* Some basic bar validity checks */
-   if (ep_bar->barno > BAR_5 || ep_bar < BAR_0)
+   if (ep_bar->barno > BAR_5 || ep_bar->barno < BAR_0)
return -EINVAL;
 
if ((ep_bar->barno == BAR_5 &&
-- 
2.20.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] rpi3: Enable verified boot from FIT image

[Jun Nie]

Matthias Brugger  于2019年7月31日周三 下午4:05写道：
>
>
>
> On 11/07/2019 05:55, Jun Nie wrote:
> > Enable verified boot from FIT image with select configs
> > and specify boot script image node in FIT image, the FIT
> > image is verified before it is run.
> >
> > Code that reusing dtb in firmware is disabled, so that
> > the dtb with pubic key packed in u-boot.bin can be used
> > to verify the signature of next stage FIT image.
> >
> > Signed-off-by: Jun Nie 
> > ---
> >  board/raspberrypi/rpi/rpi.c |  6 ++
> >  include/configs/rpi.h   | 15 ++-
> >  2 files changed, 20 insertions(+), 1 deletion(-)
> >
> > diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
> > index 617c892..950ee84 100644
> > --- a/board/raspberrypi/rpi/rpi.c
> > +++ b/board/raspberrypi/rpi/rpi.c
> > @@ -297,6 +297,7 @@ static void set_fdtfile(void)
> >   env_set("fdtfile", fdtfile);
> >  }
> >
> > +#ifndef CONFIG_FIT_SIGNATURE
> >  /*
> >   * If the firmware provided a valid FDT at boot time, let's expose it in
> >   * ${fdt_addr} so it may be passed unmodified to the kernel.
> > @@ -311,6 +312,7 @@ static void set_fdt_addr(void)
> >
> >   env_set_hex("fdt_addr", fw_dtb_pointer);
> >  }
> > +#endif
> >
> >  /*
> >   * Prevent relocation from stomping on a firmware provided FDT blob.
> > @@ -393,7 +395,9 @@ static void set_serial_number(void)
> >
> >  int misc_init_r(void)
> >  {
> > +#ifndef CONFIG_FIT_SIGNATURE
> >   set_fdt_addr();
> > +#endif
> >   set_fdtfile();
> >   set_usbethaddr();
> >  #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> > @@ -470,6 +474,7 @@ int board_init(void)
> >   return bcm2835_power_on_module(BCM2835_MBOX_POWER_DEVID_USB_HCD);
> >  }
> >
> > +#ifndef CONFIG_FIT_SIGNATURE
> >  /*
> >   * If the firmware passed a device tree use it for U-Boot.
> >   */
> > @@ -479,6 +484,7 @@ void *board_fdt_blob_setup(void)
> >   return NULL;
> >   return (void *)fw_dtb_pointer;
> >  }
> > +#endif
>
> Just to get this clear we need this because we want to pass the device tree 
> via
> OF_SEPARATE, correct?

You are right.  U-boot need to read he signature from dtb.

>
> >
> >  int ft_board_setup(void *blob, bd_t *bd)
> >  {
> > diff --git a/include/configs/rpi.h b/include/configs/rpi.h
> > index f76c7d1..ba91205 100644
> > --- a/include/configs/rpi.h
> > +++ b/include/configs/rpi.h
> > @@ -180,11 +180,24 @@
> >
> >  #include 
> >
> > +#ifdef CONFIG_FIT_SIGNATURE
> > +#define FIT_BOOT_CMD \
> > + "boot_a_script="\
> > + "load ${devtype} ${devnum}:${distro_bootpart} " \
> > + "${scriptaddr} ${prefix}${script}; "\
> > + "iminfo ${scriptaddr};" \
> > + "if test $? -eq 1; then reset; fi;" \
> > + "source ${scriptaddr}:bootscr\0"
> > +#else
> > +#define FIT_BOOT_CMD ""
> > +#endif
> > +
>
> Doesn't this overwrite the boot_a_script in distro_bootcmd?
>
> Would it make sense to add FIT booting to the distro boot command?
>
> Regards,
> Matthias

Yes, it overwrite the boot_a_script in distro_bootcmd. It is make
sense to add this to the distro boot command. I can send another patch
to move these lines to common code later.

>
> >  #define CONFIG_EXTRA_ENV_SETTINGS \
> >   "dhcpuboot=usb start; dhcp u-boot.uimg; bootm\0" \
> >   ENV_DEVICE_SETTINGS \
> >   ENV_MEM_LAYOUT_SETTINGS \
> > - BOOTENV
> > + BOOTENV \
> > + FIT_BOOT_CMD
> >
> >
> >  #endif
> >
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] sifive: riscv: update Hifive Unleashed configuration infrastructure

[Anup Patel]

On Tue, Jul 30, 2019 at 11:01 PM Sagar Kadam  wrote:
>
> Hello Anup,
>
> On Tue, Jul 30, 2019 at 9:12 AM Anup Patel  wrote:
> >
> > On Mon, Jul 29, 2019 at 6:13 PM Sagar Shrikant Kadam
> >  wrote:
> > >
> > > This patch aligns the current implementation of HiFive Unleashed
> > > board configuration framework with the one described in 
> > > doc/README.kconfig.
> > >
> > > Signed-off-by: Sagar Shrikant Kadam 
> > > ---
> > >  arch/riscv/Kconfig   |   6 +-
> > >  arch/riscv/cpu/generic/Kconfig   |  12 ---
> > >  arch/riscv/cpu/generic/Makefile  |   6 --
> > >  arch/riscv/cpu/generic/cpu.c |  35 ---
> > >  arch/riscv/cpu/generic/dram.c|  37 ---
> > >  arch/riscv/cpu/u54-mc/Kconfig|  12 +++
> > >  arch/riscv/cpu/u54-mc/Makefile   |   6 ++
> > >  arch/riscv/cpu/u54-mc/cpu.c  |  35 +++
> > >  arch/riscv/cpu/u54-mc/dram.c |  37 +++
> > >  arch/riscv/include/asm/arch-fu540-c000/clk.h |  14 +++
> > >  arch/riscv/include/asm/arch-generic/clk.h|  14 ---
> > >  board/sifive/fu540/Kconfig   |  49 --
> > >  board/sifive/fu540/MAINTAINERS   |   9 --
> > >  board/sifive/fu540/Makefile  |   5 -
> > >  board/sifive/fu540/fu540.c   | 139 
> > > ---
> > >  board/sifive/hifive_unleashed/Kconfig|  52 ++
> > >  board/sifive/hifive_unleashed/MAINTAINERS|   9 ++
> > >  board/sifive/hifive_unleashed/Makefile   |   5 +
> > >  board/sifive/hifive_unleashed/fu540.c| 139 
> > > +++
> > >  configs/hifive_unleashed_defconfig   |  11 +++
> > >  configs/sifive_fu540_defconfig   |  11 ---
> > >  include/configs/hifive_unleashed.h   |  47 +
> > >  include/configs/sifive-fu540.h   |  47 -
> > >  23 files changed, 370 insertions(+), 367 deletions(-)
> > >  delete mode 100644 arch/riscv/cpu/generic/Kconfig
> > >  delete mode 100644 arch/riscv/cpu/generic/Makefile
> > >  delete mode 100644 arch/riscv/cpu/generic/cpu.c
> > >  delete mode 100644 arch/riscv/cpu/generic/dram.c
> > >  create mode 100644 arch/riscv/cpu/u54-mc/Kconfig
> > >  create mode 100644 arch/riscv/cpu/u54-mc/Makefile
> > >  create mode 100644 arch/riscv/cpu/u54-mc/cpu.c
> > >  create mode 100644 arch/riscv/cpu/u54-mc/dram.c
> > >  create mode 100644 arch/riscv/include/asm/arch-fu540-c000/clk.h
> > >  delete mode 100644 arch/riscv/include/asm/arch-generic/clk.h
> > >  delete mode 100644 board/sifive/fu540/Kconfig
> > >  delete mode 100644 board/sifive/fu540/MAINTAINERS
> > >  delete mode 100644 board/sifive/fu540/Makefile
> > >  delete mode 100644 board/sifive/fu540/fu540.c
> > >  create mode 100644 board/sifive/hifive_unleashed/Kconfig
> > >  create mode 100644 board/sifive/hifive_unleashed/MAINTAINERS
> > >  create mode 100644 board/sifive/hifive_unleashed/Makefile
> > >  create mode 100644 board/sifive/hifive_unleashed/fu540.c
> > >  create mode 100644 configs/hifive_unleashed_defconfig
> > >  delete mode 100644 configs/sifive_fu540_defconfig
> > >  create mode 100644 include/configs/hifive_unleashed.h
> > >  delete mode 100644 include/configs/sifive-fu540.h
> > >
> >
> > I agree with Bin's concerns.
> >
> > Please don't rename generic CPU support under arch/riscv
> >
> > We should think long-term here. If every SOC vendor starts adding
> > their CPU support directory under arch/riscv then U-Boot RISC port
> > will be eventually difficult to manage and we will also have duplicate
> > code across various CPU support.
> >
> > IMHO, we should avoid adding new CPU support under arch/riscv
> > as much as possible. We can call weak functions from generic CPU
> > support and board support code can implement it. We should only
> > add new CPU support under arch/riscv when we are not able to
> > re-use generic CPU support.
> >
>
> Yes, your points are valid. I am Ok with it.
> My intent here was that as the support for riscv in U-boot is in its
> early stages
> and doing it now would be better as minimum changes will be required and
> going ahead as other CPU vendors introduce their CPU under arch/riscv/
> we could isolate a generic CPU code as it grows.

Thanks.

Let's try to make arch/riscv/cpu/generic extensible from start itself so
that it is relatively easy to fit newer RISC-V SOCs and boards.

>
> >
> > Other board support renaming is fine but there is lot of documentation
> If board support renaming is fine. Shall I submit another patch
> excluding the CPU
> changes?

Yes, please send another revision.

Also have consider updating U-Boot and OpenSBI documentation as
separate patches.

Regards,
Anup
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH] imx: mx6slevk: enable DM_SPI and DM_SPI_FLASH

[Peng Fan]

With DM_SPI and DM_SPI_FLASH enabled, we could get:

spi  0  [   ]   mxc_spi   |   |   |   `-- ecspi@02008000
spi_flash0  [   ]   spi_flash_std |   |   |   `-- m25p80@0

Signed-off-by: Peng Fan 
---
 board/freescale/mx6slevk/mx6slevk.c | 28 
 configs/mx6slevk_defconfig  |  2 ++
 configs/mx6slevk_spinor_defconfig   |  2 ++
 configs/mx6slevk_spl_defconfig  |  2 ++
 4 files changed, 6 insertions(+), 28 deletions(-)

diff --git a/board/freescale/mx6slevk/mx6slevk.c 
b/board/freescale/mx6slevk/mx6slevk.c
index 4c48679037..33ae91c307 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -15,7 +15,6 @@
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
@@ -41,9 +40,6 @@ DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   | \
PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
 
-#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-
 #define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |\
PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\
PAD_CTL_DSE_80ohm | PAD_CTL_HYS |   \
@@ -120,25 +116,6 @@ static iomux_v3_cfg_t const fec_pads[] = {
MX6_PAD_FEC_TX_CLK__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
-#ifdef CONFIG_MXC_SPI
-static iomux_v3_cfg_t ecspi1_pads[] = {
-   MX6_PAD_ECSPI1_MISO__ECSPI_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
-   MX6_PAD_ECSPI1_MOSI__ECSPI_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
-   MX6_PAD_ECSPI1_SCLK__ECSPI_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
-   MX6_PAD_ECSPI1_SS0__GPIO4_IO11  | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-int board_spi_cs_gpio(unsigned bus, unsigned cs)
-{
-   return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 11)) : -1;
-}
-
-static void setup_spi(void)
-{
-   imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
-}
-#endif
-
 static void setup_iomux_uart(void)
 {
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
@@ -232,11 +209,6 @@ int board_init(void)
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
-#ifdef CONFIG_MXC_SPI
-   gpio_request(IMX_GPIO_NR(4, 11), "spi_cs");
-   setup_spi();
-#endif
-
 #ifdef CONFIG_FEC_MXC
setup_fec();
 #endif
diff --git a/configs/mx6slevk_defconfig b/configs/mx6slevk_defconfig
index 643cad4a65..b1c8161da6 100644
--- a/configs/mx6slevk_defconfig
+++ b/configs/mx6slevk_defconfig
@@ -35,6 +35,7 @@ CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC_IMX=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=2000
@@ -50,6 +51,7 @@ CONFIG_DM_REGULATOR_PFUZE100=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_SPI=y
+CONFIG_DM_SPI=y
 CONFIG_MXC_SPI=y
 CONFIG_DM_THERMAL=y
 CONFIG_USB=y
diff --git a/configs/mx6slevk_spinor_defconfig 
b/configs/mx6slevk_spinor_defconfig
index 3dada9961a..282b10cd8f 100644
--- a/configs/mx6slevk_spinor_defconfig
+++ b/configs/mx6slevk_spinor_defconfig
@@ -35,6 +35,7 @@ CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC_IMX=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=2000
@@ -50,6 +51,7 @@ CONFIG_DM_REGULATOR_PFUZE100=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_SPI=y
+CONFIG_DM_SPI=y
 CONFIG_MXC_SPI=y
 CONFIG_DM_THERMAL=y
 CONFIG_USB=y
diff --git a/configs/mx6slevk_spl_defconfig b/configs/mx6slevk_spl_defconfig
index 63a7a74b0a..5958065c62 100644
--- a/configs/mx6slevk_spl_defconfig
+++ b/configs/mx6slevk_spl_defconfig
@@ -44,6 +44,7 @@ CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_FSL_ESDHC_IMX=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=2000
@@ -59,6 +60,7 @@ CONFIG_DM_REGULATOR_PFUZE100=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_SPI=y
+CONFIG_DM_SPI=y
 CONFIG_MXC_SPI=y
 CONFIG_DM_THERMAL=y
 CONFIG_USB=y
-- 
2.16.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] sifive: riscv: update Hifive Unleashed configuration infrastructure

[Andreas Schwab]

On Jul 30 2019, Sagar Kadam  wrote:

> I do remember using "git mv" here.

git mv is identical to git rm + git add.  A git repository has no
concept of file renames.

Andreas.

-- 
Andreas Schwab, SUSE Labs, sch...@suse.de
GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE  1748 E4D4 88E3 0EEA B9D7
"And now for something completely different."
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] board_r: re-order the board_early_init_r()

[Kever Yang]

On 2019/7/31 下午3:23, Matthias Brugger wrote:


On 24/07/2019 14:22, Kever Yang wrote:

On 2019/7/24 下午6:22, Simon Goldschmidt wrote:

On Wed, Jul 24, 2019 at 12:01 PM Kever Yang  wrote:

The board_early_init_r() suppose to be called before board_init(),
then the board callback functions in board_r will be:
- board_early_init_r()
- board_init()
- board_late_init()

Searching through the code, elixir.bootlin.com gives me 52 definitions
of board_early_init_r(). Does this patch break any of those boards
when it changes the order of those calls?

I do have check some of the implement and most of them should be OK, but to be
honest,

I'm don't have any of those boards, and not sure if this break any of them, and
I'm not sure

if people using this interface have notice it's after the board_init().

When I try to use this board_early_init_r(), I thought this is before
board_init(), but it actually

after the board_init(), that make people confusing.

I think the _early_ one should be at the first, isn't it?

I agree. Maybe we should rename it to board_post_init?

Sorry , do you mean add/rename a board_post_init() for what's done by
board_early_init_r() now and then add/move ad board api before board_init()?
There is a board_late_init(), which is after env init, a new 
board_post_init() seems

not a good idea.


Here is the Kconfig help for BOARD_EARLY_INIT_R, which also means we it 
should

be called before board_init().

config BOARD_EARLY_INIT_R
    bool "Call board-specific init after relocation"
help
  Some boards need to perform initialisation as directly after
  relocation. With this option, U-Boot calls board_early_init_r()
  in the post-relocation init sequence.


Thanks,

- Kever



Regards,
Matthias




___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH 0/3] amlogic: Add support for Odroid-N2

[Mark Kettenis]

> From: Neil Armstrong 
> Date: Wed, 31 Jul 2019 09:18:10 +0200
> 
> On 29/07/2019 15:45, Neil Armstrong wrote:
> > ODROID-N2 is a single board computer manufactured by Hardkernel Co. Ltd
> > with the following specifications:
> > 
> >  - Amlogic S922X ARM Cortex-A53 dual-core + Cortex-A73 quad-core SoC
> >  - 4GB DDR4 SDRAM
> >  - Gigabit Ethernet
> >  - HDMI 2.1 4K/60Hz display
> >  - 40-pin GPIO header
> >  - 4 x USB 3.0 Host, 1 x USB OTG
> >  - eMMC, microSD
> >  - Infrared receiver
> > 
> > This patchset :
> > - adds the Odroid-N2 from Linux 5.3-rc1
> > - fixes 4GiB memory support
> > - adds board support
> > 
> > The board directory is W400, the name of the Amlogic Reference Design
> > of Amlogic G12B with Gigabit boards, which will be used for similar
> > boards.
> > 
> > Changes since v1:
> > - Fix typo in README.odroid-n2
> > 
> > Neil Armstrong (3):
> >   ARM: dts: add support for Odroid-N2
> >   ARM: meson-g12a: Handle 4GiB DRAM size
> >   board: amlogic: add support for Odroid-N2
> > 
> >  arch/arm/dts/Makefile |   3 +-
> >  arch/arm/dts/meson-g12b-odroid-n2.dts | 386 ++
> >  arch/arm/dts/meson-g12b.dtsi  |  82 
> >  arch/arm/mach-meson/board-g12a.c  |  13 +-
> >  board/amlogic/w400/MAINTAINERS|   6 +
> >  board/amlogic/w400/Makefile   |   6 +
> >  board/amlogic/w400/README.odroid-n2   | 130 ++
> >  board/amlogic/w400/README.w400| 130 ++
> >  board/amlogic/w400/w400.c |  18 +
> >  configs/odroid-n2_defconfig   |  56 +++
> >  .../dt-bindings/sound/meson-g12a-tohdmitx.h   |  13 +
> >  11 files changed, 836 insertions(+), 7 deletions(-)
> >  create mode 100644 arch/arm/dts/meson-g12b-odroid-n2.dts
> >  create mode 100644 arch/arm/dts/meson-g12b.dtsi
> >  create mode 100644 board/amlogic/w400/MAINTAINERS
> >  create mode 100644 board/amlogic/w400/Makefile
> >  create mode 100644 board/amlogic/w400/README.odroid-n2
> >  create mode 100644 board/amlogic/w400/README.w400
> >  create mode 100644 board/amlogic/w400/w400.c
> >  create mode 100644 configs/odroid-n2_defconfig
> >  create mode 100644 include/dt-bindings/sound/meson-g12a-tohdmitx.h
> > 
> 
> Applied on u-boot-amlogic

FWIW, this made it possible for me to finally build a U-Boot with UEFI
support that can run the OpenBSD bootloader and kernel.  Now I just
need to finish writing the device drivers for the Amlogic-specific
hardware blocks ;).

So, feel free to add:

  Tested-by: Mark Kettenis 

if for some reason you need to respin the series
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH 0/3] amlogic: Add support for Odroid-N2

[Neil Armstrong]

Hi,

On 31/07/2019 11:30, Mark Kettenis wrote:
>> From: Neil Armstrong 
>> Date: Wed, 31 Jul 2019 09:18:10 +0200
>>
>> On 29/07/2019 15:45, Neil Armstrong wrote:
>>> ODROID-N2 is a single board computer manufactured by Hardkernel Co. Ltd
>>> with the following specifications:
>>>
>>>  - Amlogic S922X ARM Cortex-A53 dual-core + Cortex-A73 quad-core SoC
>>>  - 4GB DDR4 SDRAM
>>>  - Gigabit Ethernet
>>>  - HDMI 2.1 4K/60Hz display
>>>  - 40-pin GPIO header
>>>  - 4 x USB 3.0 Host, 1 x USB OTG
>>>  - eMMC, microSD
>>>  - Infrared receiver
>>>
>>> This patchset :
>>> - adds the Odroid-N2 from Linux 5.3-rc1
>>> - fixes 4GiB memory support
>>> - adds board support
>>>
>>> The board directory is W400, the name of the Amlogic Reference Design
>>> of Amlogic G12B with Gigabit boards, which will be used for similar
>>> boards.
>>>
>>> Changes since v1:
>>> - Fix typo in README.odroid-n2
>>>
>>> Neil Armstrong (3):
>>>   ARM: dts: add support for Odroid-N2
>>>   ARM: meson-g12a: Handle 4GiB DRAM size
>>>   board: amlogic: add support for Odroid-N2
>>>
>>>  arch/arm/dts/Makefile |   3 +-
>>>  arch/arm/dts/meson-g12b-odroid-n2.dts | 386 ++
>>>  arch/arm/dts/meson-g12b.dtsi  |  82 
>>>  arch/arm/mach-meson/board-g12a.c  |  13 +-
>>>  board/amlogic/w400/MAINTAINERS|   6 +
>>>  board/amlogic/w400/Makefile   |   6 +
>>>  board/amlogic/w400/README.odroid-n2   | 130 ++
>>>  board/amlogic/w400/README.w400| 130 ++
>>>  board/amlogic/w400/w400.c |  18 +
>>>  configs/odroid-n2_defconfig   |  56 +++
>>>  .../dt-bindings/sound/meson-g12a-tohdmitx.h   |  13 +
>>>  11 files changed, 836 insertions(+), 7 deletions(-)
>>>  create mode 100644 arch/arm/dts/meson-g12b-odroid-n2.dts
>>>  create mode 100644 arch/arm/dts/meson-g12b.dtsi
>>>  create mode 100644 board/amlogic/w400/MAINTAINERS
>>>  create mode 100644 board/amlogic/w400/Makefile
>>>  create mode 100644 board/amlogic/w400/README.odroid-n2
>>>  create mode 100644 board/amlogic/w400/README.w400
>>>  create mode 100644 board/amlogic/w400/w400.c
>>>  create mode 100644 configs/odroid-n2_defconfig
>>>  create mode 100644 include/dt-bindings/sound/meson-g12a-tohdmitx.h
>>>
>>
>> Applied on u-boot-amlogic
> 
> FWIW, this made it possible for me to finally build a U-Boot with UEFI
> support that can run the OpenBSD bootloader and kernel.  Now I just
> need to finish writing the device drivers for the Amlogic-specific
> hardware blocks ;).
> 
> So, feel free to add:
> 
>   Tested-by: Mark Kettenis 
> 
> if for some reason you need to respin the series
> 

Nice, I haven't sent the PR, so I'll add it !

Thanks for testing !

Neil

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 4/4] arm: dts: Add PCI-E controller for mt7623

[Frank Wunderlich]

this Patch adds pcie-controller node for mt7623

Signed-off-by: Frank Wunderlich 
---
 arch/arm/dts/mt7623.dtsi | 108 +++
 1 file changed, 108 insertions(+)

diff --git a/arch/arm/dts/mt7623.dtsi b/arch/arm/dts/mt7623.dtsi
index 64079c61bf..5d7c62bb8d 100644
--- a/arch/arm/dts/mt7623.dtsi
+++ b/arch/arm/dts/mt7623.dtsi
@@ -255,6 +255,114 @@
#reset-cells = <1>;
};

+   pcie: pcie-controller@1a14 {
+   compatible = "mediatek,mt7623-pcie";
+   device_type = "pci";
+   reg = <0x1a14 0x1000>, /* PCIe shared registers */
+ <0x1a142000 0x1000>, /* Port0 registers */
+ <0x1a143000 0x1000>, /* Port1 registers */
+ <0x1a144000 0x1000>; /* Port2 registers */
+   reg-names = "subsys", "port0", "port1", "port2";
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0xf800 0 0 0>;
+   interrupt-map = <0x 0 0 0 &sysirq GIC_SPI 193
+   IRQ_TYPE_LEVEL_LOW>,
+   <0x0800 0 0 0 &sysirq GIC_SPI 194
+   IRQ_TYPE_LEVEL_LOW>,
+   <0x1000 0 0 0 &sysirq GIC_SPI 195
+   IRQ_TYPE_LEVEL_LOW>;
+   clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
+<&hifsys CLK_HIFSYS_PCIE0>,
+<&hifsys CLK_HIFSYS_PCIE1>,
+<&hifsys CLK_HIFSYS_PCIE2>;
+   clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
+   reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
+   phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
+   power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>;
+   bus-range = <0x00 0xff>;
+   status = "okay";
+   ranges = <0x8100 0 0x1a16 0x1a16 0 0x0001
+ 0x8300 0 0x6000 0x6000 0 0x1000>;
+
+   pcie@0,0 {
+   device_type = "pci";
+   reg = <0x 0 0 0 0>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 0>;
+   interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193
+   IRQ_TYPE_LEVEL_LOW>;
+   ranges;
+   num-lanes = <1>;
+   status = "disabled";
+   };
+
+   pcie@1,0 {
+   device_type = "pci";
+   reg = <0x0800 0 0 0 0>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 0>;
+   interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194
+   IRQ_TYPE_LEVEL_LOW>;
+   ranges;
+   num-lanes = <1>;
+   status = "disabled";
+   };
+
+   pcie@2,0 {
+   device_type = "pci";
+   reg = <0x1000 0 0 0 0>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 0>;
+   interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195
+   IRQ_TYPE_LEVEL_LOW>;
+   ranges;
+   num-lanes = <1>;
+   status = "disabled";
+   };
+   };
+
+   pcie0_phy: pcie-phy@1a149000 {
+   compatible = "mediatek,generic-tphy-v1";
+   reg = <0x1a149000 0x0700>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+   status = "disabled";
+
+   pcie0_port: pcie-phy@1a149900 {
+   reg = <0x1a149900 0x0700>;
+   clocks = <&clk26m>;
+   clock-names = "ref";
+   #phy-cells = <1>;
+   status = "okay";
+   };
+   };
+
+   pcie1_phy: pcie-phy@1a14a000 {
+   compatible = "mediatek,generic-tphy-v1";
+   reg = <0x1a14a000 0x0700>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+   status = "disabled";
+
+   pcie1_port: pcie-phy@1a14a900 {
+   reg = <0x1a14a900 0x0700>;
+   clocks = <&clk26m>;
+   clock-names = "ref";
+   #phy-cells = <1>;
+   statu

[U-Boot] [PATCH 1/4] ahci-pci: ASM1061 report wrong class, but support AHCI.

[Frank Wunderlich]

From: Oleksandr Rybalko 

Tested-by: Frank Wunderlich 
Signed-off-by: Frank Wunderlich 
Signed-off-by: Oleksandr Rybalko 
---
 drivers/ata/ahci-pci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/ata/ahci-pci.c b/drivers/ata/ahci-pci.c
index 1ca439d3fa..11ec98b56f 100644
--- a/drivers/ata/ahci-pci.c
+++ b/drivers/ata/ahci-pci.c
@@ -35,6 +35,7 @@ U_BOOT_DRIVER(ahci_pci) = {

 static struct pci_device_id ahci_pci_supported[] = {
{ PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_SATA_AHCI, ~0) },
+   { PCI_DEVICE(0x1b21, 0x0611) },
{},
 };

--
2.17.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 0/4] add pcie/ahci for mt7623/bpi-r2

[Frank Wunderlich]

with this Patchseries i want to add ahci-support (sata) for bananapi-r2

pci-driver may support other devices too using mt2701 for pcie,
but in first step pcie is only activated for mt7623 (dts)

Patches depend on hifsys-patches from ryder.lee:

https://patchwork.ozlabs.org/project/uboot/list/?series=121987

Frank Wunderlich (1):
  arm: dts: Add PCI-E controller for mt7623

Oleksandr Rybalko (3):
  ahci-pci: ASM1061 report wrong class, but support AHCI.
  ata: ahci: Don't forget to clear upper address regs.
  pci: mediatek: Add pci-driver for mt2701

 arch/arm/dts/mt7623.dtsi | 108 +
 drivers/ata/ahci-pci.c   |   1 +
 drivers/ata/ahci.c   |   9 +-
 drivers/pci/Kconfig  |   6 +
 drivers/pci/Makefile |   1 +
 drivers/pci/pci-mt2701.c | 490 +++
 6 files changed, 613 insertions(+), 2 deletions(-)
 create mode 100644 drivers/pci/pci-mt2701.c

--
2.17.1
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 2/4] ata: ahci: Don't forget to clear upper address regs.

[Frank Wunderlich]

From: Oleksandr Rybalko 

In 32bits mode upper bits need to be set to 0, otherwise controller will
try to DMA into not existing memory and stops with error.

Tested-by: Frank Wunderlich 
Signed-off-by: Frank Wunderlich 
Signed-off-by: Oleksandr Rybalko 
---
 drivers/ata/ahci.c | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index e3135bb75f..716f9c1c7e 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -593,10 +593,15 @@ static int ahci_port_start(struct ahci_uc_priv *uc_priv, 
u8 port)
pp->cmd_tbl_sg =
(struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);

-   writel_with_flush((unsigned long)pp->cmd_slot,
- port_mmio + PORT_LST_ADDR);
+   writel_with_flush((u32)pp->cmd_slot, port_mmio + PORT_LST_ADDR);
+#ifndef CONFIG_PHYS_64BIT
+   writel_with_flush(0, port_mmio + PORT_LST_ADDR_HI);
+#endif

writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
+#ifndef CONFIG_PHYS_64BIT
+   writel_with_flush(0, port_mmio + PORT_FIS_ADDR_HI);
+#endif

 #ifdef CONFIG_SUNXI_AHCI
sunxi_dma_init(port_mmio);
--
2.17.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 3/4] pci: mediatek: Add pci-driver for mt2701

[Frank Wunderlich]

From: Oleksandr Rybalko 

this chip is used in MT7623 and some other Mediatek SoCs for pcie

Tested-by: Frank Wunderlich 
Signed-off-by: Frank Wunderlich 
Signed-off-by: Oleksandr Rybalko 
---
 drivers/pci/Kconfig  |   6 +
 drivers/pci/Makefile |   1 +
 drivers/pci/pci-mt2701.c | 490 +++
 3 files changed, 497 insertions(+)
 create mode 100644 drivers/pci/pci-mt2701.c

diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 3fe38f7315..cfe8ba5e52 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -145,4 +145,10 @@ config PCI_MVEBU
  Say Y here if you want to enable PCIe controller support on
  Armada XP/38x SoCs.

+config PCIE_MT2701
+   bool "Mediatek 2701 PCI-E"
+   help
+ Say Y here if you want to enable PCIe controller support on
+ Mediatek MT7623
+
 endif
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index b5ebd50c85..a4c4002b9c 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -38,3 +38,4 @@ obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie_layerscape_gen4.o \
pcie_layerscape_gen4_fixup.o
 obj-$(CONFIG_PCI_XILINX) += pcie_xilinx.o
 obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o
+obj-$(CONFIG_PCIE_MT2701) += pci-mt2701.o
diff --git a/drivers/pci/pci-mt2701.c b/drivers/pci/pci-mt2701.c
new file mode 100644
index 00..5904f15330
--- /dev/null
+++ b/drivers/pci/pci-mt2701.c
@@ -0,0 +1,490 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  Mediatek MT7623 SoC PCIE support
+ *
+ *  Copyright (C) 2015 Mediatek
+ *  Copyright (C) 2015 John Crispin 
+ *  Copyright (C) 2015 Ziv Huang 
+ *  Copyright (C) 2019 Oleksandr Rybalko 
+ */
+
+#include 
+#include 
+
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#define iowrite32(v, a)writel(v, a)
+#define iowrite16(v, a)writew(v, a)
+#define iowrite8(v, a) writeb(v, a)
+#define ioread32(a)readl(a)
+#define ioread16(a)readw(a)
+#define ioread8(a) readb(a)
+
+#define RT_HIFSYS_BASE 0x1a00
+#define RT_PCIE_BASE   0x1a14
+#define RT_PCIE_IOWIN_BASE 0x1a16
+#define RT_PCIE_IOWIN_SIZE 0x0001
+#define RT_PCIE_MEMWIN_BASE0x6000
+#define RT_PCIE_MEMWIN_SIZE0x1000
+
+#define RD(x)  readl(RT_PCIE_BASE | (x))
+#define WR(x, v)   writel(v, RT_PCIE_BASE | (x))
+
+#define SYSCFG10x14
+#define RSTCTL 0x34
+#define RSTSTAT0x38
+#define PCICFG 0x00
+#define PCIINT 0x08
+#define PCIENA 0x0c
+#define CFGADDR0x20
+#define CFGDATA0x24
+#define MEMBASE0x28
+#define IOBASE 0x2c
+
+#define BAR0SETUP  0x10
+#define IMBASEBAR0 0x18
+#define PCIE_CLASS 0x34
+#define PCIE_SISTAT0x50
+
+#define MTK_PCIE_HIGH_PERF BIT(14)
+#define PCIEP0_BASE0x2000
+#define PCIEP1_BASE0x3000
+#define PCIEP2_BASE0x4000
+
+#define PHY_P0_CTL 0x9000
+#define PHY_P1_CTL 0xa000
+#define PHY_P2_CTL 0x4000 /* in USB space */
+
+#define RSTCTL_PCIE0_RST   BIT(24)
+#define RSTCTL_PCIE1_RST   BIT(25)
+#define RSTCTL_PCIE2_RST   BIT(26)
+#define MAX_PORT_NUM   3
+
+struct resource {
+   char *name;
+   u32 start;
+   u32 end;
+};
+
+struct mt_pcie {
+   char name[16];
+};
+
+static struct mtk_pcie_port {
+   int id;
+   int enable;
+   u32 base;
+   u32 phy_base;
+   u32 perst_n;
+   u32 reset;
+   u32 interrupt_en;
+   int irq;
+   u32 link;
+} mtk_pcie_port[] = {
+   { 0, 1, PCIEP0_BASE, PHY_P0_CTL, BIT(1), RSTCTL_PCIE0_RST, BIT(20) },
+   { 1, 1, PCIEP1_BASE, PHY_P1_CTL, BIT(2), RSTCTL_PCIE1_RST, BIT(21) },
+   { 2, 0, PCIEP2_BASE, PHY_P2_CTL, BIT(3), RSTCTL_PCIE2_RST, BIT(22) },
+};
+
+struct mtk_pcie {
+   struct device *dev;
+   void __iomem *sys_base; /* HIF SYSCTL registers */
+   void __iomem *pcie_base;/* PCIE registers */
+   void __iomem *usb_base; /* USB registers */
+
+   struct resource io;
+   struct resource pio;
+   struct resource mem;
+   struct resource prefetch;
+   struct resource busn;
+
+   u32 io_bus_addr;
+   u32 mem_bus_addr;
+
+   struct clk *clk;
+   int pcie_card_link;
+};
+
+static const struct mtk_phy_init {
+   u32 reg;
+   u32 mask;
+   u32 val;
+} mtk_phy_init[] = {
+   { 0xc00, 0x33000, 0x22000 },
+   { 0xb04, 0xe000, 0x4000 },
+   { 0xb00, 0xe, 0x4 },
+   { 0xc3C, 0x, 0x3c },
+   { 0xc48, 0x, 0x36 },
+   { 0xc0c, 0x3000, 0x1000 },
+   { 0xc08, 0x3800c0, 0xc0 },
+   { 0xc10, 0xf, 0x2 },
+   { 0xc0c, 0xf000, 0x1000 },
+   { 0xc14, 0xf, 0xa },
+

[U-Boot] [PATCH v1 0/9] apalis-tk1: fixes/updates for v2019.10

[Igor Opaniuk]

Misc. fixes related to pinmux configuration (fan), default bootargs,
reset reason output and power rail configuration.

Dominik Sliwa (2):
  apalis-tk1/t30: colibri_t30: display reset reason
  apalis-tk1: remove non-esential power rails on boot

Igor Opaniuk (5):
  apalis-tk1: set apalis gpio 8 aka fan_en
  apalis-tk1: provide proper USB vendor id
  apalis-tk1: enable user debug by default
  apalis-tk1: add pcie_aspm=off to defargs
  apalis-tk1: switch to zImage

Marcel Ziswiler (2):
  apalis-tk1: do not explicitly release reset_moci#
  apalis-tk1: remove default vesa vga mode from vidargs

 arch/arm/mach-tegra/sys_info.c| 32 -
 arch/arm/mach-tegra/tegra124/cpu.c| 45 +++
 board/toradex/apalis-tk1/apalis-tk1.c | 10 +
 board/toradex/apalis-tk1/as3722_init.c| 23 ++
 .../apalis-tk1/pinmux-config-apalis-tk1.h |  2 +-
 configs/apalis-tk1_defconfig  |  2 +-
 include/configs/apalis-tk1.h  | 17 +++
 7 files changed, 111 insertions(+), 20 deletions(-)

-- 
2.17.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v1 1/9] apalis-tk1: do not explicitly release reset_moci#

[Igor Opaniuk]

From: Marcel Ziswiler 

By keeping RESET_MOCI_CTRL low we avoid explicitly releasing
RESET_MOCI#.

Please note that module hardware versions up to V1.1A will already
release RESET_MOCI# in hardware coming out of reset.

Please further note that with this change the USB hub on the Apalis
Evaluation board is kept in reset in U-Boot and therefore none of its
ports are operational in U-Boot.

Signed-off-by: Marcel Ziswiler 
Signed-off-by: Igor Opaniuk 
---

 board/toradex/apalis-tk1/pinmux-config-apalis-tk1.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/toradex/apalis-tk1/pinmux-config-apalis-tk1.h 
b/board/toradex/apalis-tk1/pinmux-config-apalis-tk1.h
index 1584d9b2d3..d2d24c4391 100644
--- a/board/toradex/apalis-tk1/pinmux-config-apalis-tk1.h
+++ b/board/toradex/apalis-tk1/pinmux-config-apalis-tk1.h
@@ -39,7 +39,7 @@ static const struct tegra_gpio_config apalis_tk1_gpio_inits[] 
= {
GPIO_INIT(R,1,   OUT0), /* Shift_CTRL_Dir_In[1] */
GPIO_INIT(R,2,   OUT0), /* Shift_CTRL_OE[3] */
GPIO_INIT(S,3,   OUT0), /* Shift_CTRL_Dir_In[2] */
-   GPIO_INIT(U,4,   OUT1),
+   GPIO_INIT(U,4,   OUT0), /* RESET_MOCI_CTRL */
GPIO_INIT(W,3,   IN),
GPIO_INIT(W,5,   IN),
GPIO_INIT(BB,   0,  IN),
-- 
2.17.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v1 2/9] apalis-tk1: set apalis gpio 8 aka fan_en

[Igor Opaniuk]

From: Igor Opaniuk 

Make sure the Apalis GPIO 8 aka FAN_EN is on when using Apalis TK1
modules.

Signed-off-by: Igor Opaniuk 
Signed-off-by: Dominik Sliwa 
---

 board/toradex/apalis-tk1/apalis-tk1.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/board/toradex/apalis-tk1/apalis-tk1.c 
b/board/toradex/apalis-tk1/apalis-tk1.c
index b87e9e7a3e..d57c5042dd 100644
--- a/board/toradex/apalis-tk1/apalis-tk1.c
+++ b/board/toradex/apalis-tk1/apalis-tk1.c
@@ -19,6 +19,7 @@
 
 #define LAN_DEV_OFF_N  TEGRA_GPIO(O, 6)
 #define LAN_RESET_NTEGRA_GPIO(S, 2)
+#define FAN_EN TEGRA_GPIO(DD, 2)
 #define LAN_WAKE_N TEGRA_GPIO(O, 5)
 #ifdef CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT
 #define PEX_PERST_NTEGRA_GPIO(DD, 1) /* Apalis GPIO7 */
@@ -241,6 +242,15 @@ void tegra_pcie_board_port_reset(struct tegra_pcie_port 
*port)
 }
 #endif /* CONFIG_PCI_TEGRA */
 
+/*
+ * Enable/start PWM CPU fan
+ */
+void start_cpu_fan(void)
+{
+   gpio_request(FAN_EN, "FAN_EN");
+   gpio_direction_output(FAN_EN, 1);
+}
+
 /*
  * Backlight off before OS handover
  */
-- 
2.17.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v1 9/9] apalis-tk1: remove non-esential power rails on boot

[Igor Opaniuk]

From: Dominik Sliwa 

When mainline kernels reboot TK1 they use SW_RESET,
that reset mode does not reset PMIC. Some rails
need to be off for RAM Re-repair to work correctly.

Signed-off-by: Dominik Sliwa 
Signed-off-by: Igor Opaniuk 
---

 arch/arm/mach-tegra/tegra124/cpu.c | 45 ++
 board/toradex/apalis-tk1/as3722_init.c | 23 +
 2 files changed, 68 insertions(+)

diff --git a/arch/arm/mach-tegra/tegra124/cpu.c 
b/arch/arm/mach-tegra/tegra124/cpu.c
index 992c0beb04..abc050c27b 100644
--- a/arch/arm/mach-tegra/tegra124/cpu.c
+++ b/arch/arm/mach-tegra/tegra124/cpu.c
@@ -238,6 +238,45 @@ static bool is_partition_powered(u32 partid)
return !!(reg & (1 << partid));
 }
 
+static void unpower_partition(u32 partid)
+{
+   struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+   debug("%s: part ID = %08X\n", __func__, partid);
+   /* Is the partition on? */
+   if (is_partition_powered(partid)) {
+   /* Yes, toggle the partition power state (ON -> OFF) */
+   debug("power_partition, toggling state\n");
+   writel(START_CP | partid, &pmc->pmc_pwrgate_toggle);
+
+   /* Wait for the power to come down */
+   while (is_partition_powered(partid))
+   ;
+
+   /* Give I/O signals time to stabilize */
+   udelay(IO_STABILIZATION_DELAY);
+   }
+}
+
+void unpower_cpus(void)
+{
+   debug("%s entry: G cluster\n", __func__);
+
+   /* Power down the fast cluster rail partition */
+   debug("%s: CRAIL\n", __func__);
+   unpower_partition(CRAIL);
+
+   /* Power down the fast cluster non-CPU partition */
+   debug("%s: C0NC\n", __func__);
+   unpower_partition(C0NC);
+
+   /* Power down the fast cluster CPU0 partition */
+   debug("%s: CE0\n", __func__);
+   unpower_partition(CE0);
+
+   debug("%s: done\n", __func__);
+}
+
 static void power_partition(u32 partid)
 {
struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
@@ -284,6 +323,12 @@ void start_cpu(u32 reset_vector)
 
debug("%s entry, reset_vector = %x\n", __func__, reset_vector);
 
+   /*
+* High power clusters are on after software reset,
+* it may interfere with tegra124_ram_repair.
+* unpower them.
+*/
+   unpower_cpus();
tegra124_init_clocks();
 
/* Set power-gating timer multiplier */
diff --git a/board/toradex/apalis-tk1/as3722_init.c 
b/board/toradex/apalis-tk1/as3722_init.c
index bd754e5fcf..15f8dce2f1 100644
--- a/board/toradex/apalis-tk1/as3722_init.c
+++ b/board/toradex/apalis-tk1/as3722_init.c
@@ -43,6 +43,29 @@ void pmic_enable_cpu_vdd(void)
udelay(10 * 1000);
 #endif
 
+   /*
+* Make sure all non-fused regulators are down.
+* That way we're in known state after software reboot from linux
+*/
+   tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+   tegra_i2c_ll_write_data(0x0003, I2C_SEND_2_BYTES);
+   udelay(10 * 1000);
+   tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+   tegra_i2c_ll_write_data(0x0004, I2C_SEND_2_BYTES);
+   udelay(10 * 1000);
+   tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+   tegra_i2c_ll_write_data(0x001b, I2C_SEND_2_BYTES);
+   udelay(10 * 1000);
+   tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+   tegra_i2c_ll_write_data(0x0014, I2C_SEND_2_BYTES);
+   udelay(10 * 1000);
+   tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+   tegra_i2c_ll_write_data(0x001a, I2C_SEND_2_BYTES);
+   udelay(10 * 1000);
+   tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
+   tegra_i2c_ll_write_data(0x0019, I2C_SEND_2_BYTES);
+   udelay(10 * 1000);
+
debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__);
/*
 * Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus.
-- 
2.17.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v1 8/9] apalis-tk1: remove default vesa vga mode from vidargs

[Igor Opaniuk]

From: Marcel Ziswiler 

Remove video=tegrafb0:640x480-16@60 aka VESA VGA mode from vidargs in
order for the panel specification in the device tree to be used. This
causes the default to be the 10.1" LVDS display which will be available
in the Toradex webshop shortly.

Signed-off-by: Marcel Ziswiler 
Signed-off-by: Igor Opaniuk 
---

 include/configs/apalis-tk1.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h
index 10f2948c62..843e64e3cc 100644
--- a/include/configs/apalis-tk1.h
+++ b/include/configs/apalis-tk1.h
@@ -137,7 +137,7 @@
"load ${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \
"source ${loadaddr}\0" \
USB_BOOTCMD \
-   "vidargs=video=tegrafb0:640x480-16@60 fbcon=map:1\0"
+   "vidargs=fbcon=map:1\0"
 
 /* Increase console I/O buffer size */
 #undef CONFIG_SYS_CBSIZE
-- 
2.17.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v1 7/9] apalis-tk1/t30: colibri_t30: display reset reason

[Igor Opaniuk]

From: Dominik Sliwa 

Display proper reset reason after the SoC info.

Signed-off-by: Dominik Sliwa 
Signed-off-by: Igor Opaniuk 
---

 arch/arm/mach-tegra/sys_info.c | 32 ++--
 1 file changed, 22 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-tegra/sys_info.c b/arch/arm/mach-tegra/sys_info.c
index 9975f33e0b..5dc998a52b 100644
--- a/arch/arm/mach-tegra/sys_info.c
+++ b/arch/arm/mach-tegra/sys_info.c
@@ -6,24 +6,36 @@
 
 #include 
 #include 
+#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA30)
+#include 
 
-static void upstring(char *s)
+static char *get_reset_cause(void)
 {
-   while (*s) {
-   *s = toupper(*s);
-   s++;
+   struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
+
+   switch (pmc->pmc_reset_status) {
+   case 0x00:
+   return "POR";
+   case 0x01:
+   return "WATCHDOG";
+   case 0x02:
+   return "SENSOR";
+   case 0x03:
+   return "SW_MAIN";
+   case 0x04:
+   return "LP0";
}
+   return "UNKNOWN";
 }
+#endif
 
 /* Print CPU information */
 int print_cpuinfo(void)
 {
-   char soc_name[10];
-
-   strncpy(soc_name, CONFIG_SYS_SOC, 10);
-   upstring(soc_name);
-   puts(soc_name);
-   puts("\n");
+   printf("SoC: %s\n", CONFIG_SYS_SOC);
+#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA30)
+   printf("Reset cause: %s\n", get_reset_cause());
+#endif
 
/* TBD: Add printf of major/minor rev info, stepping, etc. */
return 0;
-- 
2.17.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v1 5/9] apalis-tk1: add pcie_aspm=off to defargs

[Igor Opaniuk]

From: Igor Opaniuk 

Disabling ASPM fixes incompatibilities with some PCIe cards

Signed-off-by: Dominik Sliwa 
Signed-off-by: Igor Opaniuk 
---

 include/configs/apalis-tk1.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h
index efc52841d1..0bde1697bb 100644
--- a/include/configs/apalis-tk1.h
+++ b/include/configs/apalis-tk1.h
@@ -112,7 +112,7 @@
"console=ttyS0\0" \
"defargs=lp0_vec=2064@0xf46ff000 core_edp_mv=1150 core_edp_ma=4000 " \
"usb_port_owner_info=2 lane_owner_info=6 emc_max_dvfs=0 " \
-   "user_debug=30\0" \
+   "user_debug=30 pcie_aspm=off\0" \
"dfu_alt_info=" DFU_ALT_EMMC_INFO "\0" \
EMMC_BOOTCMD \
"fdt_board=eval\0" \
-- 
2.17.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v1 4/9] apalis-tk1: enable user debug by default

[Igor Opaniuk]

From: Igor Opaniuk 

Let the kernel print some debug messages when a user program
crashes due to an exception.

Signed-off-by: Stefan Agner 
Signed-off-by: Igor Opaniuk 
---

 include/configs/apalis-tk1.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h
index b4ddd1bdc6..efc52841d1 100644
--- a/include/configs/apalis-tk1.h
+++ b/include/configs/apalis-tk1.h
@@ -111,7 +111,8 @@
"boot_file=uImage\0" \
"console=ttyS0\0" \
"defargs=lp0_vec=2064@0xf46ff000 core_edp_mv=1150 core_edp_ma=4000 " \
-   "usb_port_owner_info=2 lane_owner_info=6 emc_max_dvfs=0\0" \
+   "usb_port_owner_info=2 lane_owner_info=6 emc_max_dvfs=0 " \
+   "user_debug=30\0" \
"dfu_alt_info=" DFU_ALT_EMMC_INFO "\0" \
EMMC_BOOTCMD \
"fdt_board=eval\0" \
-- 
2.17.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v1 6/9] apalis-tk1: switch to zImage

[Igor Opaniuk]

From: Igor Opaniuk 

Switch to the generic compressed Kernel image type (zImage) instead of
the U-Boot specific uImage format.

Signed-off-by: Bhuvanchandra DV 
Signed-off-by: Igor Opaniuk 
---

 include/configs/apalis-tk1.h | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h
index 0bde1697bb..10f2948c62 100644
--- a/include/configs/apalis-tk1.h
+++ b/include/configs/apalis-tk1.h
@@ -42,7 +42,7 @@
 #define DFU_ALT_EMMC_INFO  "apalis-tk1.img raw 0x0 0x500 mmcpart 1; " \
"boot part 0 1 mmcpart 0; " \
"rootfs part 0 2 mmcpart 0; " \
-   "uImage fat 0 1 mmcpart 0; " \
+   "zImage fat 0 1 mmcpart 0; " \
"tegra124-apalis-eval.dtb fat 0 1 mmcpart 0"
 
 #define EMMC_BOOTCMD \
@@ -54,7 +54,7 @@
"run emmcdtbload; " \
"load mmc ${emmcdev}:${emmcbootpart} ${kernel_addr_r} " \
"${boot_file} && run fdt_fixup && " \
-   "bootm ${kernel_addr_r} - ${dtbparam}\0" \
+   "bootz ${kernel_addr_r} - ${dtbparam}\0" \
"emmcbootpart=1\0" \
"emmcdev=0\0" \
"emmcdtbload=setenv dtbparam; load mmc ${emmcdev}:${emmcbootpart} " \
@@ -68,7 +68,7 @@
"nfsboot=pci enum; run setup; setenv bootargs ${defargs} ${nfsargs} " \
"${setupargs} ${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \
"run nfsdtbload; dhcp ${kernel_addr_r} " \
-   "&& run fdt_fixup && bootm ${kernel_addr_r} - ${dtbparam}\0" \
+   "&& run fdt_fixup && bootz ${kernel_addr_r} - ${dtbparam}\0" \
"nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} " \
"${soc}-apalis-${fdt_board}.dtb " \
"&& setenv dtbparam ${fdt_addr_r}\0"
@@ -81,7 +81,7 @@
"${vidargs}; echo Booting from SD card in 8bit slot...; " \
"run sddtbload; load mmc ${sddev}:${sdbootpart} " \
"${kernel_addr_r} ${boot_file} && run fdt_fixup && " \
-   "bootm ${kernel_addr_r} - ${dtbparam}\0" \
+   "bootz ${kernel_addr_r} - ${dtbparam}\0" \
"sdbootpart=1\0" \
"sddev=1\0" \
"sddtbload=setenv dtbparam; load mmc ${sddev}:${sdbootpart} " \
@@ -98,7 +98,7 @@
"${usbargs} ${vidargs}; echo Booting from USB stick...; " \
"run usbdtbload; load usb ${usbdev}:${usbbootpart} " \
"${kernel_addr_r} ${boot_file} && run fdt_fixup && " \
-   "bootm ${kernel_addr_r} - ${dtbparam}\0" \
+   "bootz ${kernel_addr_r} - ${dtbparam}\0" \
"usbbootpart=1\0" \
"usbdev=0\0" \
"usbdtbload=setenv dtbparam; load usb ${usbdev}:${usbbootpart} " \
@@ -108,7 +108,7 @@
"usbrootpart=2\0"
 
 #define BOARD_EXTRA_ENV_SETTINGS \
-   "boot_file=uImage\0" \
+   "boot_file=zImage\0" \
"console=ttyS0\0" \
"defargs=lp0_vec=2064@0xf46ff000 core_edp_mv=1150 core_edp_ma=4000 " \
"usb_port_owner_info=2 lane_owner_info=6 emc_max_dvfs=0 " \
-- 
2.17.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v1 3/9] apalis-tk1: provide proper USB vendor id

[Igor Opaniuk]

From: Igor Opaniuk 

Use unified values for USB Product/Vendor numbers
when the config block is missing

Signed-off-by: Max Krummenacher 
Signed-off-by: Igor Opaniuk 
---

 configs/apalis-tk1_defconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/apalis-tk1_defconfig b/configs/apalis-tk1_defconfig
index 41f3aff149..ceefe4e86a 100644
--- a/configs/apalis-tk1_defconfig
+++ b/configs/apalis-tk1_defconfig
@@ -56,7 +56,7 @@ CONFIG_USB_EHCI_TEGRA=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Toradex"
 CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
-CONFIG_USB_GADGET_PRODUCT_NUM=0x
+CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
 CONFIG_CI_UDC=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_OF_LIBFDT_OVERLAY=y
-- 
2.17.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] rpi: increase SYS_BOOTM_LEN to 64M

[Bonnans, Laurent]

On 7/31/19 9:12 AM, Matthias Brugger wrote:

> Hi Laurent,
>
> On 07/06/2019 17:04, Bonnans, Laurent wrote:
>> On AArch64, kernel images are not self-decompressing and easily exceed
>> the 8MB limit.
>>
>> Signed-off-by: Laurent Bonnans 
>> ---
>>   include/configs/rpi.h | 1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/include/configs/rpi.h b/include/configs/rpi.h
>> index 9ce41767a9..1a5ae26ae7 100644
>> --- a/include/configs/rpi.h
>> +++ b/include/configs/rpi.h
>> @@ -55,6 +55,7 @@
>>   #define CONFIG_SYS_MEMTEST_START   0x0010
>>   #define CONFIG_SYS_MEMTEST_END 0x0020
>>   #define CONFIG_LOADADDR0x0020
>> +#define CONFIG_SYS_BOOTM_LENSZ_64M
>>   
> Sorry for the late reply.
> If it's only needed for ARM64 then we should make it set for this 
> architecture,
> right?

That seems to be the best call indeed. Then I wonder if we should just 
set the default larger if CONFIG_ARM64 because the problem should arise 
almost in all case, I believe. There is a similar define in 
sunxi-common.h for example.

But anyway, that's a larger debate, I'll send another patch with the 
ARM64 check in the header file.

> Next time you send a patch, plese add the maintainers mailinglist. This way 
> I'll
> find the patch easier.

Yes, sorry about that. Only realized it later...


Laurent
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v2] rpi: increase SYS_BOOTM_LEN to 64M on ARM64

[Bonnans, Laurent]

On AArch64, kernel images are not self-decompressing and easily exceed
the 8MB limit.

Signed-off-by: Laurent Bonnans 
---
Changes for v2:
  - only override SYS_BOOTM_LEN in ARM64 case

 include/configs/rpi.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/include/configs/rpi.h b/include/configs/rpi.h
index f76c7d18ef..394377b31e 100644
--- a/include/configs/rpi.h
+++ b/include/configs/rpi.h
@@ -56,6 +56,10 @@
 #define CONFIG_SYS_MEMTEST_END 0x0020
 #define CONFIG_LOADADDR0x0020
 
+#ifdef CONFIG_ARM64
+#define CONFIG_SYS_BOOTM_LEN   SZ_64M
+#endif
+
 /* Devices */
 /* GPIO */
 #define CONFIG_BCM2835_GPIO
-- 
2.20.1
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] Please pull u-boot-mmc

[Peng Fan]

Hi Tom,

Please pull u-boot-mmc

CI build: https://travis-ci.org/MrVan/u-boot/builds/565839867
---
A new mmc/sd block test case
Bug fixes for sdhci and mv_sdhci
---

Thanks,
Peng.

The following changes since commit d0d07ba86afc8074d79e436b1ba4478fa0f0c1b5:

  Prepare v2019.10-rc1 (2019-07-29 21:16:16 -0400)

are available in the Git repository at:

  https://gitlab.denx.de/u-boot/custodians/u-boot-mmc.git tags/mmc-7-31

for you to fetch changes up to fea3939d31ccde5b8372bc5506a35ac169de03c8:

  mmc: relocate code comment (2019-07-31 15:31:36 +0800)


Baruch Siach (3):
  mmc: mv_sdhci: fix uninitialized pointer deref on probe
  mmc: sdhci: fix chip detect gpio property name
  mmc: relocate code comment

Jean-Jacques Hiblot (1):
  test/py: add MMC/SD block write test

Weijie Gao (1):
  mmc: mtk-sd: add WATCHDOG_RESET() to prevent watchdog timeout

 drivers/mmc/mmc.c|   2 +-
 drivers/mmc/mtk-sd.c |   3 +++
 drivers/mmc/mv_sdhci.c   |   6 +++---
 drivers/mmc/sdhci.c  |   2 +-
 test/py/tests/test_mmc_wr.py | 105 
+
 5 files changed, 113 insertions(+), 5 deletions(-)
 create mode 100644 test/py/tests/test_mmc_wr.py
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [GIT] Pull request: u-boot-clk (31.07.2019)

[Lukasz Majewski]

Dear Tom,

Please find a PR for u-boot-clk branch:

Change log:
- Port more CCF code to work with i.MX8 devices.





The following changes since commit 75551c8bfc9545e31ec2ce238cac3857904007b8:

  Merge branch '2019-07-26-ti-imports' (2019-07-27 19:50:52 -0400)

are available in the git repository at:

  g...@gitlab.denx.de:u-boot/custodians/u-boot-clk.git 

for you to fetch changes up to 4f895988adc021d96c02cbcbb7b899c57ecbae4a:

  test: dm: clk_ccf: test composite clk (2019-07-31 09:20:51 +0200)


Peng Fan (16):
  clk: introduce clk_dev_binded
  clk: use clk_dev_binded
  clk: mux: add set parent support
  clk: export mux/divider ops
  clk: add clk-gate support
  clk: divider set rate supporrt
  clk: fixed_rate: export clk_fixed_rate
  clk: imx: import clk heplers
  clk: imx: gate2 add set rate
  dm: clk: ignore default settings when node not valid
  clk-provider: include clk-uclass.h
  clk: add composite clk support
  clk: gate: support sandbox
  configs: sandbox: Enable composite clk
  clk: sandbox: add composite clk
  test: dm: clk_ccf: test composite clk

 configs/sandbox_defconfig  |   1 +
 configs/sandbox_flattree_defconfig |   1 +
 drivers/clk/Kconfig|  14 +++
 drivers/clk/Makefile   |   3 +-
 drivers/clk/clk-composite.c| 160 

 drivers/clk/clk-divider.c  |  92 
+++-
 drivers/clk/clk-gate.c | 159 
+++
 drivers/clk/clk-mux.c  |  76 ++--
 drivers/clk/clk-uclass.c   |   3 ++
 drivers/clk/clk.c  |   8 
 drivers/clk/clk_fixed_rate.c   |   8 +---
 drivers/clk/clk_sandbox_ccf.c  |  80 ++
 drivers/clk/imx/clk-gate2.c|  11 ++
 drivers/clk/imx/clk.h  |  81 ++
 include/clk.h  |   9 +
 include/linux/clk-provider.h   |  58 
 include/sandbox-clk.h  |   1 +
 test/dm/clk_ccf.c  |   8 
 18 files changed, 759 insertions(+), 14 deletions(-)
 create mode 100644 drivers/clk/clk-composite.cc create mode 100644 
drivers/clk/clk-gate.c



Travis-CI: 
https://travis-ci.org/lmajewski/u-boot-dfu/builds/565844770


Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de


pgp0WoojRIWrm.pgp
Description: OpenPGP digital signature
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PULL] u-boot-sh/master

[Tom Rini]

On Tue, Jul 30, 2019 at 02:07:23PM +0200, Marek Vasut wrote:

> The following changes since commit 0de815356474912ef5bef9a69f0327a5a93bb2c2:
> 
>   Merge branch '2019-07-17-master-imports' (2019-07-18 11:31:37 -0400)
> 
> are available in the Git repository at:
> 
>   git://git.denx.de/u-boot-sh.git master
> 
> for you to fetch changes up to b5f563e588d134b2cb96a2f54332b7727ee4cdad:
> 
>   pinctrl: renesas: fix R-Car gpio0_00 operation fails with 'gpio
> -input' command (2019-07-29 13:38:55 +0200)
> 

Applied to u-boot/master, thanks!

-- 
Tom


signature.asc
Description: PGP signature
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [GIT PULL] Xilinx/FPGA patches for v2019.10

[Tom Rini]

On Tue, Jul 30, 2019 at 05:23:20PM +0200, Michal Simek wrote:

> Hi Tom,
> 
> I just came from vacation and didn't catch rc1 merge window. Here are
> patches I have collected in connection to Xilinx and FPGA.
> 
> Thanks,
> Michal
> 
> 
> The following changes since commit d0d07ba86afc8074d79e436b1ba4478fa0f0c1b5:
> 
>   Prepare v2019.10-rc1 (2019-07-29 21:16:16 -0400)
> 
> are available in the Git repository at:
> 
>   g...@gitlab.denx.de:u-boot/custodians/u-boot-microblaze.git
> tags/xilinx-for-v2019.10
> 
> for you to fetch changes up to cd228cc04afc79c1383be707d0b812f45dfd53aa:
> 
>   arm64: zynqmp: Do not include pm_cfg_obj.o when SPL is disabled
> (2019-07-30 17:09:58 +0200)
> 

Applied to u-boot/master, thanks!




-- 
Tom


signature.asc
Description: PGP signature
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] Please pull u-boot-video

[Tom Rini]

On Tue, Jul 30, 2019 at 08:07:54PM +0200, Anatolij Gustschin wrote:

> Hi Tom,
> 
> here some more video patches I missed to include in the recent pull request.
> Travis CI: https://travis-ci.org/vdsao/u-boot-video/builds/565440648
> 
> Thanks,
> Anatolij
> 
> The following changes since commit 970baf16d1322d3930a57fc78ddfb15d594d690c:
> 
>   video: arm: rpi: Bail out early if querying video information fails 
> (2019-07-29 10:14:04 +0200)
> 
> are available in the Git repository at:
> 
>   https://gitlab.denx.de/u-boot/custodians/u-boot-video.git 
> tags/video-for-2019.10-rc1
> 
> for you to fetch changes up to 42a7ce27d97022f4abbba142dfa00d1450512f0a:
> 
>   mxc_ipuv3_fb.c: enable a backlight on a panel (2019-07-30 12:58:33 +0200)
> 

Applied to u-boot/master, thanks!

-- 
Tom


signature.asc
Description: PGP signature
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH 3/4] pci: mediatek: Add pci-driver for mt2701

[Ryder Lee]

+ GSS_MTK_Uboot_upstream 

On Wed, 2019-07-31 at 13:51 +0200, Frank Wunderlich wrote:
> From: Oleksandr Rybalko 
> 
> this chip is used in MT7623 and some other Mediatek SoCs for pcie
> 
> Tested-by: Frank Wunderlich 
> Signed-off-by: Frank Wunderlich 
> Signed-off-by: Oleksandr Rybalko 
> ---
>  drivers/pci/Kconfig  |   6 +
>  drivers/pci/Makefile |   1 +
>  drivers/pci/pci-mt2701.c | 490 +++
>  3 files changed, 497 insertions(+)
>  create mode 100644 drivers/pci/pci-mt2701.c

Rename 'pci-mt2701.c' to 'pcie-mediatek.c' and then change the subject.

Obviously, this is an intermediate version of Linux patch, so I suggest
to take a look at the latest version of vanilla Kernel:
https://github.com/torvalds/linux/blob/master/drivers/pci/controller/pcie-mediatek.c

Please see my comments inline: 

> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
> index 3fe38f7315..cfe8ba5e52 100644
> --- a/drivers/pci/Kconfig
> +++ b/drivers/pci/Kconfig
> @@ -145,4 +145,10 @@ config PCI_MVEBU
> Say Y here if you want to enable PCIe controller support on
> Armada XP/38x SoCs.
> 
> +config PCIE_MT2701
> + bool "Mediatek 2701 PCI-E"
> + help
> +   Say Y here if you want to enable PCIe controller support on
> +   Mediatek MT7623
> +
>  endif
> diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
> index b5ebd50c85..a4c4002b9c 100644
> --- a/drivers/pci/Makefile
> +++ b/drivers/pci/Makefile
> @@ -38,3 +38,4 @@ obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += 
> pcie_layerscape_gen4.o \
>   pcie_layerscape_gen4_fixup.o
>  obj-$(CONFIG_PCI_XILINX) += pcie_xilinx.o
>  obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o
> +obj-$(CONFIG_PCIE_MT2701) += pci-mt2701.o
> diff --git a/drivers/pci/pci-mt2701.c b/drivers/pci/pci-mt2701.c
> new file mode 100644
> index 00..5904f15330
> --- /dev/null
> +++ b/drivers/pci/pci-mt2701.c
> @@ -0,0 +1,490 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + *  Mediatek MT7623 SoC PCIE support
> + *
> + *  Copyright (C) 2015 Mediatek
> + *  Copyright (C) 2015 John Crispin 
> + *  Copyright (C) 2015 Ziv Huang 
> + *  Copyright (C) 2019 Oleksandr Rybalko 
> + */
> +
> +#include 
> +#include 
> +
> +#include 
> +#include 
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#define iowrite32(v, a)  writel(v, a)
> +#define iowrite16(v, a)  writew(v, a)
> +#define iowrite8(v, a)   writeb(v, a)
> +#define ioread32(a)  readl(a)
> +#define ioread16(a)  readw(a)
> +#define ioread8(a)   readb(a)

Remove these defines.

> +#define RT_HIFSYS_BASE   0x1a00
> +#define RT_PCIE_BASE 0x1a14
> +#define RT_PCIE_IOWIN_BASE   0x1a16
> +#define RT_PCIE_IOWIN_SIZE   0x0001
> +#define RT_PCIE_MEMWIN_BASE  0x6000
> +#define RT_PCIE_MEMWIN_SIZE  0x1000

Move these base to dts.

> +#define RD(x)readl(RT_PCIE_BASE | (x))
> +#define WR(x, v) writel(v, RT_PCIE_BASE | (x))
> +
> +#define SYSCFG1  0x14
> +#define RSTCTL   0x34
> +#define RSTSTAT  0x38
> +#define PCICFG   0x00
> +#define PCIINT   0x08
> +#define PCIENA   0x0c
> +#define CFGADDR  0x20
> +#define CFGDATA  0x24
> +#define MEMBASE  0x28
> +#define IOBASE   0x2c
> +
> +#define BAR0SETUP0x10
> +#define IMBASEBAR0   0x18
> +#define PCIE_CLASS   0x34
> +#define PCIE_SISTAT  0x50
> +
> +#define MTK_PCIE_HIGH_PERF   BIT(14)
> +#define PCIEP0_BASE  0x2000
> +#define PCIEP1_BASE  0x3000
> +#define PCIEP2_BASE  0x4000
> +
> +#define PHY_P0_CTL   0x9000
> +#define PHY_P1_CTL   0xa000
> +#define PHY_P2_CTL   0x4000 /* in USB space */
> +
> +#define RSTCTL_PCIE0_RST BIT(24)
> +#define RSTCTL_PCIE1_RST BIT(25)
> +#define RSTCTL_PCIE2_RST BIT(26)
> +#define MAX_PORT_NUM 3
> +
> +struct resource {
> + char *name;
> + u32 start;
> + u32 end;
> +};
> +
> +struct mt_pcie {
> + char name[16];
> +};
> +
> +static struct mtk_pcie_port {
> + int id;
> + int enable;
> + u32 base;
> + u32 phy_base;
> + u32 perst_n;
> + u32 reset;
> + u32 interrupt_en;
> + int irq;
> + u32 link;
> +} mtk_pcie_port[] = {
> + { 0, 1, PCIEP0_BASE, PHY_P0_CTL, BIT(1), RSTCTL_PCIE0_RST, BIT(20) },
> + { 1, 1, PCIEP1_BASE, PHY_P1_CTL, BIT(2), RSTCTL_PCIE1_RST, BIT(21) },
> + { 2, 0, PCIEP2_BASE, PHY_P2_CTL, BIT(3), RSTCTL_PCIE2_RST, BIT(22) },
> +};

move some of mtk_pcie_port[] to dts.

> +struct mtk_pcie {
> + struct device *dev;
> + void __iomem *sys_base; /* HIF SYSCTL registers */
> + void __iomem *pcie_base;/* PCIE registers */
> + void __iomem *usb_base; /* USB registers */
> +
> + struct resource io;
> + struc

Re: [U-Boot] [PATCH v1 1/9] apalis-tk1: do not explicitly release reset_moci#

[Oleksandr Suvorov]

On Wed, Jul 31, 2019 at 3:05 PM Igor Opaniuk  wrote:
>
> From: Marcel Ziswiler 
>
> By keeping RESET_MOCI_CTRL low we avoid explicitly releasing
> RESET_MOCI#.
>
> Please note that module hardware versions up to V1.1A will already
> release RESET_MOCI# in hardware coming out of reset.
>
> Please further note that with this change the USB hub on the Apalis
> Evaluation board is kept in reset in U-Boot and therefore none of its
> ports are operational in U-Boot.
>
> Signed-off-by: Marcel Ziswiler 
> Signed-off-by: Igor Opaniuk 

Reviewed-by: Oleksandr Suvorov 

> ---
>
>  board/toradex/apalis-tk1/pinmux-config-apalis-tk1.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/board/toradex/apalis-tk1/pinmux-config-apalis-tk1.h 
> b/board/toradex/apalis-tk1/pinmux-config-apalis-tk1.h
> index 1584d9b2d3..d2d24c4391 100644
> --- a/board/toradex/apalis-tk1/pinmux-config-apalis-tk1.h
> +++ b/board/toradex/apalis-tk1/pinmux-config-apalis-tk1.h
> @@ -39,7 +39,7 @@ static const struct tegra_gpio_config 
> apalis_tk1_gpio_inits[] = {
> GPIO_INIT(R,1,   OUT0), /* Shift_CTRL_Dir_In[1] */
> GPIO_INIT(R,2,   OUT0), /* Shift_CTRL_OE[3] */
> GPIO_INIT(S,3,   OUT0), /* Shift_CTRL_Dir_In[2] */
> -   GPIO_INIT(U,4,   OUT1),
> +   GPIO_INIT(U,4,   OUT0), /* RESET_MOCI_CTRL */
> GPIO_INIT(W,3,   IN),
> GPIO_INIT(W,5,   IN),
> GPIO_INIT(BB,   0,  IN),
> --
> 2.17.1
>
> ___
> U-Boot mailing list
> U-Boot@lists.denx.de
> https://lists.denx.de/listinfo/u-boot



-- 
Best regards
Oleksandr Suvorov

Toradex AG
Altsagenstrasse 5 | 6048 Horw/Luzern | Switzerland | T: +41 41 500
4800 (main line)
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH v1 2/9] apalis-tk1: set apalis gpio 8 aka fan_en

[Oleksandr Suvorov]

On Wed, Jul 31, 2019 at 3:07 PM Igor Opaniuk  wrote:
>
> From: Igor Opaniuk 
>
> Make sure the Apalis GPIO 8 aka FAN_EN is on when using Apalis TK1
> modules.
>
> Signed-off-by: Igor Opaniuk 
> Signed-off-by: Dominik Sliwa 

Reviewed-by: Oleksandr Suvorov 

> ---
>
>  board/toradex/apalis-tk1/apalis-tk1.c | 10 ++
>  1 file changed, 10 insertions(+)
>
> diff --git a/board/toradex/apalis-tk1/apalis-tk1.c 
> b/board/toradex/apalis-tk1/apalis-tk1.c
> index b87e9e7a3e..d57c5042dd 100644
> --- a/board/toradex/apalis-tk1/apalis-tk1.c
> +++ b/board/toradex/apalis-tk1/apalis-tk1.c
> @@ -19,6 +19,7 @@
>
>  #define LAN_DEV_OFF_N  TEGRA_GPIO(O, 6)
>  #define LAN_RESET_NTEGRA_GPIO(S, 2)
> +#define FAN_EN TEGRA_GPIO(DD, 2)
>  #define LAN_WAKE_N TEGRA_GPIO(O, 5)
>  #ifdef CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT
>  #define PEX_PERST_NTEGRA_GPIO(DD, 1) /* Apalis GPIO7 */
> @@ -241,6 +242,15 @@ void tegra_pcie_board_port_reset(struct tegra_pcie_port 
> *port)
>  }
>  #endif /* CONFIG_PCI_TEGRA */
>
> +/*
> + * Enable/start PWM CPU fan
> + */
> +void start_cpu_fan(void)
> +{
> +   gpio_request(FAN_EN, "FAN_EN");
> +   gpio_direction_output(FAN_EN, 1);
> +}
> +
>  /*
>   * Backlight off before OS handover
>   */
> --
> 2.17.1
>
> ___
> U-Boot mailing list
> U-Boot@lists.denx.de
> https://lists.denx.de/listinfo/u-boot



-- 
Best regards
Oleksandr Suvorov

Toradex AG
Altsagenstrasse 5 | 6048 Horw/Luzern | Switzerland | T: +41 41 500
4800 (main line)
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH v1 3/9] apalis-tk1: provide proper USB vendor id

[Oleksandr Suvorov]

On Wed, Jul 31, 2019 at 3:09 PM Igor Opaniuk  wrote:
>
> From: Igor Opaniuk 
>
> Use unified values for USB Product/Vendor numbers
> when the config block is missing
>
> Signed-off-by: Max Krummenacher 
> Signed-off-by: Igor Opaniuk 

Reviewed-by: Oleksandr Suvorov 

> ---
>
>  configs/apalis-tk1_defconfig | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/configs/apalis-tk1_defconfig b/configs/apalis-tk1_defconfig
> index 41f3aff149..ceefe4e86a 100644
> --- a/configs/apalis-tk1_defconfig
> +++ b/configs/apalis-tk1_defconfig
> @@ -56,7 +56,7 @@ CONFIG_USB_EHCI_TEGRA=y
>  CONFIG_USB_GADGET=y
>  CONFIG_USB_GADGET_MANUFACTURER="Toradex"
>  CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
> -CONFIG_USB_GADGET_PRODUCT_NUM=0x
> +CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
>  CONFIG_CI_UDC=y
>  CONFIG_USB_GADGET_DOWNLOAD=y
>  CONFIG_OF_LIBFDT_OVERLAY=y
> --
> 2.17.1
>
> ___
> U-Boot mailing list
> U-Boot@lists.denx.de
> https://lists.denx.de/listinfo/u-boot



-- 
Best regards

Oleksandr Suvorov
cryo...@gmail.com
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH v1 5/9] apalis-tk1: add pcie_aspm=off to defargs

[Oleksandr Suvorov]

On Wed, Jul 31, 2019 at 3:09 PM Igor Opaniuk  wrote:
>
> From: Igor Opaniuk 
>
> Disabling ASPM fixes incompatibilities with some PCIe cards
>
> Signed-off-by: Dominik Sliwa 
> Signed-off-by: Igor Opaniuk 

Reviewed-by: Oleksandr Suvorov 

> ---
>
>  include/configs/apalis-tk1.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h
> index efc52841d1..0bde1697bb 100644
> --- a/include/configs/apalis-tk1.h
> +++ b/include/configs/apalis-tk1.h
> @@ -112,7 +112,7 @@
> "console=ttyS0\0" \
> "defargs=lp0_vec=2064@0xf46ff000 core_edp_mv=1150 core_edp_ma=4000 " \
> "usb_port_owner_info=2 lane_owner_info=6 emc_max_dvfs=0 " \
> -   "user_debug=30\0" \
> +   "user_debug=30 pcie_aspm=off\0" \
> "dfu_alt_info=" DFU_ALT_EMMC_INFO "\0" \
> EMMC_BOOTCMD \
> "fdt_board=eval\0" \
> --
> 2.17.1
>
> ___
> U-Boot mailing list
> U-Boot@lists.denx.de
> https://lists.denx.de/listinfo/u-boot



-- 
Best regards

Oleksandr Suvorov
cryo...@gmail.com
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH v1 6/9] apalis-tk1: switch to zImage

[Oleksandr Suvorov]

On Wed, Jul 31, 2019 at 3:09 PM Igor Opaniuk  wrote:
>
> From: Igor Opaniuk 
>
> Switch to the generic compressed Kernel image type (zImage) instead of
> the U-Boot specific uImage format.
>
> Signed-off-by: Bhuvanchandra DV 
> Signed-off-by: Igor Opaniuk 

Reviewed-by: Oleksandr Suvorov 

> ---
>
>  include/configs/apalis-tk1.h | 12 ++--
>  1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h
> index 0bde1697bb..10f2948c62 100644
> --- a/include/configs/apalis-tk1.h
> +++ b/include/configs/apalis-tk1.h
> @@ -42,7 +42,7 @@
>  #define DFU_ALT_EMMC_INFO  "apalis-tk1.img raw 0x0 0x500 mmcpart 1; " \
> "boot part 0 1 mmcpart 0; " \
> "rootfs part 0 2 mmcpart 0; " \
> -   "uImage fat 0 1 mmcpart 0; " \
> +   "zImage fat 0 1 mmcpart 0; " \
> "tegra124-apalis-eval.dtb fat 0 1 mmcpart 0"
>
>  #define EMMC_BOOTCMD \
> @@ -54,7 +54,7 @@
> "run emmcdtbload; " \
> "load mmc ${emmcdev}:${emmcbootpart} ${kernel_addr_r} " \
> "${boot_file} && run fdt_fixup && " \
> -   "bootm ${kernel_addr_r} - ${dtbparam}\0" \
> +   "bootz ${kernel_addr_r} - ${dtbparam}\0" \
> "emmcbootpart=1\0" \
> "emmcdev=0\0" \
> "emmcdtbload=setenv dtbparam; load mmc ${emmcdev}:${emmcbootpart} " \
> @@ -68,7 +68,7 @@
> "nfsboot=pci enum; run setup; setenv bootargs ${defargs} ${nfsargs} " 
> \
> "${setupargs} ${vidargs}; echo Booting via DHCP/TFTP/NFS...; 
> " \
> "run nfsdtbload; dhcp ${kernel_addr_r} " \
> -   "&& run fdt_fixup && bootm ${kernel_addr_r} - ${dtbparam}\0" \
> +   "&& run fdt_fixup && bootz ${kernel_addr_r} - ${dtbparam}\0" \
> "nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} " \
> "${soc}-apalis-${fdt_board}.dtb " \
> "&& setenv dtbparam ${fdt_addr_r}\0"
> @@ -81,7 +81,7 @@
> "${vidargs}; echo Booting from SD card in 8bit slot...; " \
> "run sddtbload; load mmc ${sddev}:${sdbootpart} " \
> "${kernel_addr_r} ${boot_file} && run fdt_fixup && " \
> -   "bootm ${kernel_addr_r} - ${dtbparam}\0" \
> +   "bootz ${kernel_addr_r} - ${dtbparam}\0" \
> "sdbootpart=1\0" \
> "sddev=1\0" \
> "sddtbload=setenv dtbparam; load mmc ${sddev}:${sdbootpart} " \
> @@ -98,7 +98,7 @@
> "${usbargs} ${vidargs}; echo Booting from USB stick...; " \
> "run usbdtbload; load usb ${usbdev}:${usbbootpart} " \
> "${kernel_addr_r} ${boot_file} && run fdt_fixup && " \
> -   "bootm ${kernel_addr_r} - ${dtbparam}\0" \
> +   "bootz ${kernel_addr_r} - ${dtbparam}\0" \
> "usbbootpart=1\0" \
> "usbdev=0\0" \
> "usbdtbload=setenv dtbparam; load usb ${usbdev}:${usbbootpart} " \
> @@ -108,7 +108,7 @@
> "usbrootpart=2\0"
>
>  #define BOARD_EXTRA_ENV_SETTINGS \
> -   "boot_file=uImage\0" \
> +   "boot_file=zImage\0" \
> "console=ttyS0\0" \
> "defargs=lp0_vec=2064@0xf46ff000 core_edp_mv=1150 core_edp_ma=4000 " \
> "usb_port_owner_info=2 lane_owner_info=6 emc_max_dvfs=0 " \
> --
> 2.17.1
>
> ___
> U-Boot mailing list
> U-Boot@lists.denx.de
> https://lists.denx.de/listinfo/u-boot



-- 
Best regards

Oleksandr Suvorov
cryo...@gmail.com
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH v1 8/9] apalis-tk1: remove default vesa vga mode from vidargs

[Oleksandr Suvorov]

On Wed, Jul 31, 2019 at 3:08 PM Igor Opaniuk  wrote:
>
> From: Marcel Ziswiler 
>
> Remove video=tegrafb0:640x480-16@60 aka VESA VGA mode from vidargs in
> order for the panel specification in the device tree to be used. This
> causes the default to be the 10.1" LVDS display which will be available
> in the Toradex webshop shortly.
>
> Signed-off-by: Marcel Ziswiler 
> Signed-off-by: Igor Opaniuk 

Reviewed-by: Oleksandr Suvorov 

> ---
>
>  include/configs/apalis-tk1.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h
> index 10f2948c62..843e64e3cc 100644
> --- a/include/configs/apalis-tk1.h
> +++ b/include/configs/apalis-tk1.h
> @@ -137,7 +137,7 @@
> "load ${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \
> "source ${loadaddr}\0" \
> USB_BOOTCMD \
> -   "vidargs=video=tegrafb0:640x480-16@60 fbcon=map:1\0"
> +   "vidargs=fbcon=map:1\0"
>
>  /* Increase console I/O buffer size */
>  #undef CONFIG_SYS_CBSIZE
> --
> 2.17.1
>
> ___
> U-Boot mailing list
> U-Boot@lists.denx.de
> https://lists.denx.de/listinfo/u-boot



-- 
Best regards
Oleksandr Suvorov

Toradex AG
Altsagenstrasse 5 | 6048 Horw/Luzern | Switzerland | T: +41 41 500
4800 (main line)
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH v2 2/2] serial: lpuart: request dm device removal when booting OS

[Anatolij Gustschin]

Hi Peng,

On Mon, 15 Jul 2019 03:02:46 +
Peng Fan peng@nxp.com wrote:
... 
> > +static int lpuart_serial_remove(struct udevice *dev) {
> > +   if (dev == gd->cur_serial_dev)
> > +   dev->flags |= DM_FLAG_REMOVE_WITH_PD_ON;  
> 
> How about introduce a device tree property for DM? Then
> Set the flags in common code, not in specific driver.

we should not add more DT properties which are not describing the
hardware, I think. Current plan is to drop this patch and do additional
check dev != gd->cur_serial_dev in device_remove(), as Lokesh suggested.

--
Anatolij
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH v1 9/9] apalis-tk1: remove non-esential power rails on boot

[Oleksandr Suvorov]

On Wed, Jul 31, 2019 at 3:07 PM Igor Opaniuk  wrote:
>
> From: Dominik Sliwa 
>
> When mainline kernels reboot TK1 they use SW_RESET,
> that reset mode does not reset PMIC. Some rails
> need to be off for RAM Re-repair to work correctly.
>
> Signed-off-by: Dominik Sliwa 
> Signed-off-by: Igor Opaniuk 

Reviewed-by: Oleksandr Suvorov 

> ---
>
>  arch/arm/mach-tegra/tegra124/cpu.c | 45 ++
>  board/toradex/apalis-tk1/as3722_init.c | 23 +
>  2 files changed, 68 insertions(+)
>
> diff --git a/arch/arm/mach-tegra/tegra124/cpu.c 
> b/arch/arm/mach-tegra/tegra124/cpu.c
> index 992c0beb04..abc050c27b 100644
> --- a/arch/arm/mach-tegra/tegra124/cpu.c
> +++ b/arch/arm/mach-tegra/tegra124/cpu.c
> @@ -238,6 +238,45 @@ static bool is_partition_powered(u32 partid)
> return !!(reg & (1 << partid));
>  }
>
> +static void unpower_partition(u32 partid)
> +{
> +   struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
> +
> +   debug("%s: part ID = %08X\n", __func__, partid);
> +   /* Is the partition on? */
> +   if (is_partition_powered(partid)) {
> +   /* Yes, toggle the partition power state (ON -> OFF) */
> +   debug("power_partition, toggling state\n");
> +   writel(START_CP | partid, &pmc->pmc_pwrgate_toggle);
> +
> +   /* Wait for the power to come down */
> +   while (is_partition_powered(partid))
> +   ;
> +
> +   /* Give I/O signals time to stabilize */
> +   udelay(IO_STABILIZATION_DELAY);
> +   }
> +}
> +
> +void unpower_cpus(void)
> +{
> +   debug("%s entry: G cluster\n", __func__);
> +
> +   /* Power down the fast cluster rail partition */
> +   debug("%s: CRAIL\n", __func__);
> +   unpower_partition(CRAIL);
> +
> +   /* Power down the fast cluster non-CPU partition */
> +   debug("%s: C0NC\n", __func__);
> +   unpower_partition(C0NC);
> +
> +   /* Power down the fast cluster CPU0 partition */
> +   debug("%s: CE0\n", __func__);
> +   unpower_partition(CE0);
> +
> +   debug("%s: done\n", __func__);
> +}
> +
>  static void power_partition(u32 partid)
>  {
> struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
> @@ -284,6 +323,12 @@ void start_cpu(u32 reset_vector)
>
> debug("%s entry, reset_vector = %x\n", __func__, reset_vector);
>
> +   /*
> +* High power clusters are on after software reset,
> +* it may interfere with tegra124_ram_repair.
> +* unpower them.
> +*/
> +   unpower_cpus();
> tegra124_init_clocks();
>
> /* Set power-gating timer multiplier */
> diff --git a/board/toradex/apalis-tk1/as3722_init.c 
> b/board/toradex/apalis-tk1/as3722_init.c
> index bd754e5fcf..15f8dce2f1 100644
> --- a/board/toradex/apalis-tk1/as3722_init.c
> +++ b/board/toradex/apalis-tk1/as3722_init.c
> @@ -43,6 +43,29 @@ void pmic_enable_cpu_vdd(void)
> udelay(10 * 1000);
>  #endif
>
> +   /*
> +* Make sure all non-fused regulators are down.
> +* That way we're in known state after software reboot from linux
> +*/
> +   tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
> +   tegra_i2c_ll_write_data(0x0003, I2C_SEND_2_BYTES);
> +   udelay(10 * 1000);
> +   tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
> +   tegra_i2c_ll_write_data(0x0004, I2C_SEND_2_BYTES);
> +   udelay(10 * 1000);
> +   tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
> +   tegra_i2c_ll_write_data(0x001b, I2C_SEND_2_BYTES);
> +   udelay(10 * 1000);
> +   tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
> +   tegra_i2c_ll_write_data(0x0014, I2C_SEND_2_BYTES);
> +   udelay(10 * 1000);
> +   tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
> +   tegra_i2c_ll_write_data(0x001a, I2C_SEND_2_BYTES);
> +   udelay(10 * 1000);
> +   tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
> +   tegra_i2c_ll_write_data(0x0019, I2C_SEND_2_BYTES);
> +   udelay(10 * 1000);
> +
> debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__);
> /*
>  * Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus.
> --
> 2.17.1
>
> ___
> U-Boot mailing list
> U-Boot@lists.denx.de
> https://lists.denx.de/listinfo/u-boot



-- 
Best regards

Oleksandr Suvorov
cryo...@gmail.com
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH v2 1/2] dm: core: device: switch off power domain after device removal

[Anatolij Gustschin]

Hi Lokesh,

On Tue, 23 Jul 2019 19:35:43 +0530
Lokesh Vutla lokeshvu...@ti.com wrote:
...  
> > +   if (CONFIG_IS_ENABLED(POWER_DOMAIN) && dev->parent &&
> > +   device_get_uclass_id(dev) != UCLASS_POWER_DOMAIN &&
> > +   !(dev->flags & DM_FLAG_REMOVE_WITH_PD_ON)) {  
> 
> This is going to hit every board and all serial drivers needs to be updated. 
> Can
> we add an extra check here for (dev != gd->cur_serial_dev).

Will do it in v3 patch, thanks!

--
Anatolij
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 1/1] sunxi: Fix pll1 clock calculation

[Stefan Mavrodiev]

clock_sun6i.c is used for sun6i, sun8i and sun50i SoC families.
PLL1 clock sets the default system clock, defined as:
  sun6i: 100800
  sun8i: 100800
  sun50i: 81600

With the current calculation, m = 2 and k = 3. Solving for n,
this results 28. Solving back:
  (24MHz * 28 * 3) / 2 = 1008MHz

However if the requested clock is 816, n is 22.66 rounded
to 22, which results:
  (24MHz * 28 * 3) / 2 = 792MHz

Changing k to 4 satisfies both system clocks:
  (24E6 * 21 * 4) / 2 = 1008MHz
  (24E6 * 17 * 4) / 2 = 816MHz

Signed-off-by: Stefan Mavrodiev 
---
 arch/arm/mach-sunxi/clock_sun6i.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-sunxi/clock_sun6i.c 
b/arch/arm/mach-sunxi/clock_sun6i.c
index 1628f3a7b6..6ca38f73d9 100644
--- a/arch/arm/mach-sunxi/clock_sun6i.c
+++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -118,7 +118,7 @@ void clock_set_pll1(unsigned int clk)
if (clk > 115200) {
k = 2;
} else if (clk > 76800) {
-   k = 3;
+   k = 4;
m = 2;
}
 
-- 
2.17.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] imx7d: CPU core issue in secure mode

[Fabio Estevam]

[Adding Bryan and Breno]

Hi Bryan,

I think you worked on allowing the CAAM driver in Linux to work on
i.MX7D running in non-secure when you created:
commit 22191ac35344 ("drivers/crypto/fsl: assign job-rings to non-TrustZone")

It was reverted later by Breno as it broke secure boot.

If I understand correctly the current solution is to let OP-TEE deal
with job-rings initialization.

Is there any other alternative to use the mainline kernel CAAM driver
in non-secure if someone is not using OP-TEE?

Thanks,

Fabio Estevam

On Fri, Jul 12, 2019 at 5:20 AM Tobias Junghans
 wrote:
>
> Hi Peng,
>
> Am Freitag, 12. Juli 2019, 05:38:21 CEST schrieb Peng Fan:
> > Try "setenv bootm_boot_mode nonsec" in U-Boot stage.
>
> Unfortunately this does not help. I tried the following setups:
>
> CONFIG_SECURE_BOOT=y
> CONFIG_CPU_V7_HAS_NONSEC=y
> CONFIG_CPU_V7_HAS_VIRT=y
> CONFIG_ARCH_SUPPORT_PSCI=y
> CONFIG_ARMV7_NONSEC=y
> CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
> CONFIG_ARMV7_VIRT=y
> CONFIG_ARMV7_PSCI=y
> CONFIG_ARMV7_PSCI_NR_CPUS=2
> CONFIG_FSL_CAAM=y
> CONFIG_SYS_FSL_HAS_SEC=y
> CONFIG_SYS_FSL_SEC_COMPAT_4=y
> # CONFIG_SYS_FSL_SEC_BE is not set
> CONFIG_SYS_FSL_SEC_COMPAT=4
> CONFIG_SYS_FSL_SEC_LE=y
>
>
> Booting with bootm_boot_mode=nonsec
>
>
> U-Boot 2019.07 (Jul 12 2019 - 10:02:31 +0200)
> CPU:   Freescale i.MX7D rev1.3 1000 MHz (running at 792 MHz)
> ..
> SEC0: RNG instantiated
> ..
>
>
> [0.00] Booting Linux on physical CPU 0x0
> [0.00] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d
> [0.00] CPU: div instructions available: patching division code
> [0.00] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing
> instruction cache
> [0.00] percpu: Embedded 16 pages/cpu s34380 r8192 d22964 u65536
> [0.00] pcpu-alloc: s34380 r8192 d22964 u65536 alloc=16*4096
> [0.00] pcpu-alloc: [0] 0 [0] 1
> [0.00] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
> ..
> [0.00] psci: probing for conduit method from DT.
> [0.00] psci: PSCIv1.0 detected in firmware.
> [0.00] psci: Using standard PSCI v0.2 function IDs
> [0.00] psci: Trusted OS migration not required
> [0.00] psci: SMC Calling Convention v1.0
> ..
> [0.002872] CPU: Testing write buffer coherency: ok
> [0.003224] CPU0: update cpu_capacity 1024
> [0.003234] CPU0: thread -1, cpu 0, socket 0, mpidr 8000
> [0.004687] smp: Bringing up secondary CPUs ...
> [0.005424] CPU1: update cpu_capacity 1024
> [0.005432] CPU1: thread -1, cpu 1, socket 0, mpidr 8001
> [0.005553] smp: Brought up 1 node, 2 CPUs
> [0.005568] CPU: All CPU(s) started in HYP mode.
> [0.005571] CPU: Virtualization extensions available.
> ..
> [0.185229] caam 3090.caam: device ID = 0x0a160300 (Era 8)
> [0.185240] caam 3090.caam: job rings = 3, qi = 0
> [0.186894] caam_jr 30901000.jr0: failed to flush job ring 0
> [0.192721] caam_jr: probe of 30901000.jr0 failed with error -5
> [0.192846] caam_jr 30902000.jr1: failed to flush job ring 1
> [0.198796] caam_jr: probe of 30902000.jr1 failed with error -5
> [0.198989] caam_jr 30903000.jr1: failed to flush job ring 2
> [0.204957] caam_jr: probe of 30903000.jr1 failed with error -5
> [0.212619] Job Ring Device allocation for transform failed
>
>
>
> Same configuration with
>
> setenv bootm_boot_mode=sec
>
> [0.00] Booting Linux on physical CPU 0x0
> [0.00] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d
> [0.00] CPU: div instructions available: patching division code
> [0.00] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing
> instruction cache
> [0.00] percpu: Embedded 16 pages/cpu s34380 r8192 d22964 u65536
> [0.00] pcpu-alloc: s34380 r8192 d22964 u65536 alloc=16*4096
> [0.00] pcpu-alloc: [0] 0 [0] 1
> [0.00] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
> [0.002866] CPU: Testing write buffer coherency: ok
> [0.003217] CPU0: update cpu_capacity 1024
> [0.003226] CPU0: thread -1, cpu 0, socket 0, mpidr 8000
> [0.004673] smp: Bringing up secondary CPUs ...
> [0.005174] smp: Brought up 1 node, 1 CPU
> [0.005188] CPU: All CPU(s) started in SVC mode.
> ..
> [0.185631] caam 3090.caam: device ID = 0x0a160300 (Era 8)
> [0.185643] caam 3090.caam: job rings = 3, qi = 0
> [0.196909] caam algorithms registered in /proc/crypto
> [0.199620] caam_jr 30901000.jr0: registering rng-caam
>
>
> => only 1 CPU core up.
>
>
> Now I tried to disable the CAAM driver and secure boot support in U-Boot
>
> # CONFIG_SECURE_BOOT is not set
> CONFIG_CPU_V7_HAS_NONSEC=y
> CONFIG_CPU_V7_HAS_VIRT=y
> CONFIG_ARCH_SUPPORT_PSCI=y
> CONFIG_ARMV7_NONSEC=y
> CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
> CONFIG_ARMV7_VIRT=y
> CONFIG_ARMV7_PSCI=y
> CONFIG_ARMV7_PSCI_NR_CPUS=2
> # CONFIG_FSL_CAAM is not set
> CONFIG_SYS_FSL_SEC_COMPAT_4=y
> # CONFIG_S

[U-Boot] [PATCH] Revert "ARM: davinci: da850: Manual pinmux only when PINCTRL not available"

[Adam Ford]

This reverts commit 877ab2423bc257045a06bc23d4b9440b82bda6fb.

The above patch was designed to shrink code by only pin-muxing items
needed for SPL in SPL and relying on driver model or SPL to mux other
items.  Unfortunately, da850evm_direct_nor doesn't use SPL so items
that were only muxed during SPL are not muxed causing the board
to no longer boot.

Signed-off-by: Adam Ford 

diff --git a/board/davinci/da8xxevm/da850evm.c 
b/board/davinci/da8xxevm/da850evm.c
index fcf9334ba9..849905cf8a 100644
--- a/board/davinci/da8xxevm/da850evm.c
+++ b/board/davinci/da8xxevm/da850evm.c
@@ -215,29 +215,21 @@ static const struct pinmux_config gpio_pins[] = {
 };
 
 const struct pinmux_resource pinmuxes[] = {
-#ifndef CONFIG_SPL_BUILD
 #ifdef CONFIG_DRIVER_TI_EMAC
PINMUX_ITEM(emac_pins_mdio),
 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
PINMUX_ITEM(emac_pins_rmii),
 #else
PINMUX_ITEM(emac_pins_mii),
-#endif /* CONFIG_DRIVER_TI_EMAC */
-#endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
-#endif /* CONFIG_SPL_BUILD */
+#endif
+#endif
 #ifdef CONFIG_SPI_FLASH
-#if !CONFIG_IS_ENABLED(PINCTRL)
PINMUX_ITEM(spi1_pins_base),
PINMUX_ITEM(spi1_pins_scs0),
 #endif
-#endif
-#if !CONFIG_IS_ENABLED(PINCTRL)
PINMUX_ITEM(uart2_pins_txrx),
PINMUX_ITEM(uart2_pins_rtscts),
-#endif
-#if !CONFIG_IS_ENABLED(PINCTRL)
PINMUX_ITEM(i2c0_pins),
-#endif
 #ifdef CONFIG_NAND_DAVINCI
PINMUX_ITEM(emifa_pins_cs3),
PINMUX_ITEM(emifa_pins_cs4),
@@ -248,10 +240,8 @@ const struct pinmux_resource pinmuxes[] = {
 #endif
PINMUX_ITEM(gpio_pins),
 #ifdef CONFIG_MMC_DAVINCI
-#if !CONFIG_IS_ENABLED(PINCTRL)
PINMUX_ITEM(mmc0_pins),
 #endif
-#endif
 };
 
 const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
-- 
2.17.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] question about spi flash driver for large ST micro

[Valero, Miguel]

Hi there.
I was wondering whether you have plans to add support for the BP3 and 
Top/Bottom bits of the Status Register, making it possible to lock flash 
regions with full flexibility, within the device constrains of course.
That would be the current stm_lock() and friends.

Further, do you have plans to implement the individual sector protection 
(potentially with password protection) for the ST micro compatible devices?

If so, would you please share your roadmap with us?

Thank you.
Miguel Valero
Senior SW Engineer
Aker Solutions

miguel.val...@akersolutions.com |  
www.akersolutions.com

Aker Solutions AS
Visiting address: Joseph Kellersvei 20, 3408 Tranby, Norway
Postal address: PO Box 73, 3401 Lier, Norway
Registered in Norway, registration no. 929 877 950 VAT

[cid:image001.png@01D40189.CC3F6100]




This e-mail and any attachment are confidential and may be privileged or 
otherwise protected from disclosure. It is solely intended for the person(s) 
named above. If you are not the intended recipient, any reading, use, 
disclosure, copying or distribution of all or parts of this e-mail or 
associated attachments is strictly prohibited. If you are not an intended 
recipient, please notify the sender immediately by replying to this message or 
by telephone and delete this e-mail and any attachments permanently from your 
system.
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH 3/4] pci: mediatek: Add pci-driver for mt2701

[Aleksandr Rybalko]

Hello Ryder.

ср, 31 лип. 2019 о 15:45 Ryder Lee  пише:

> + GSS_MTK_Uboot_upstream 
>
> On Wed, 2019-07-31 at 13:51 +0200, Frank Wunderlich wrote:
> > From: Oleksandr Rybalko 
> >
> > this chip is used in MT7623 and some other Mediatek SoCs for pcie
> >
> > Tested-by: Frank Wunderlich 
> > Signed-off-by: Frank Wunderlich 
> > Signed-off-by: Oleksandr Rybalko 
> > ---
> >  drivers/pci/Kconfig  |   6 +
> >  drivers/pci/Makefile |   1 +
> >  drivers/pci/pci-mt2701.c | 490 +++
> >  3 files changed, 497 insertions(+)
> >  create mode 100644 drivers/pci/pci-mt2701.c
>
> Rename 'pci-mt2701.c' to 'pcie-mediatek.c' and then change the subject.
>

So you promise us, that Mediatek will never produce PCI-E controller which
will be totally different from that one? :)


>
> Obviously, this is an intermediate version of Linux patch, so I suggest
> to take a look at the latest version of vanilla Kernel:
>
> https://github.com/torvalds/linux/blob/master/drivers/pci/controller/pcie-mediatek.c
>
> Please see my comments inline:
>
> > diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
> > index 3fe38f7315..cfe8ba5e52 100644
> > --- a/drivers/pci/Kconfig
> > +++ b/drivers/pci/Kconfig
> > @@ -145,4 +145,10 @@ config PCI_MVEBU
> > Say Y here if you want to enable PCIe controller support on
> > Armada XP/38x SoCs.
> >
> > +config PCIE_MT2701
> > + bool "Mediatek 2701 PCI-E"
> > + help
> > +   Say Y here if you want to enable PCIe controller support on
> > +   Mediatek MT7623
> > +
> >  endif
> > diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
> > index b5ebd50c85..a4c4002b9c 100644
> > --- a/drivers/pci/Makefile
> > +++ b/drivers/pci/Makefile
> > @@ -38,3 +38,4 @@ obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) +=
> pcie_layerscape_gen4.o \
> >   pcie_layerscape_gen4_fixup.o
> >  obj-$(CONFIG_PCI_XILINX) += pcie_xilinx.o
> >  obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o
> > +obj-$(CONFIG_PCIE_MT2701) += pci-mt2701.o
> > diff --git a/drivers/pci/pci-mt2701.c b/drivers/pci/pci-mt2701.c
> > new file mode 100644
> > index 00..5904f15330
> > --- /dev/null
> > +++ b/drivers/pci/pci-mt2701.c
> > @@ -0,0 +1,490 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + *  Mediatek MT7623 SoC PCIE support
> > + *
> > + *  Copyright (C) 2015 Mediatek
> > + *  Copyright (C) 2015 John Crispin 
> > + *  Copyright (C) 2015 Ziv Huang 
> > + *  Copyright (C) 2019 Oleksandr Rybalko 
> > + */
> > +
> > +#include 
> > +#include 
> > +
> > +#include 
> > +#include 
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +#define iowrite32(v, a)  writel(v, a)
> > +#define iowrite16(v, a)  writew(v, a)
> > +#define iowrite8(v, a)   writeb(v, a)
> > +#define ioread32(a)  readl(a)
> > +#define ioread16(a)  readw(a)
> > +#define ioread8(a)   readb(a)
>
> Remove these defines.
>
> > +#define RT_HIFSYS_BASE   0x1a00
> > +#define RT_PCIE_BASE 0x1a14
> > +#define RT_PCIE_IOWIN_BASE   0x1a16
> > +#define RT_PCIE_IOWIN_SIZE   0x0001
> > +#define RT_PCIE_MEMWIN_BASE  0x6000
> > +#define RT_PCIE_MEMWIN_SIZE  0x1000
>
> Move these base to dts.
>

Already there (ranges), just not used yet.


>
> > +#define RD(x)readl(RT_PCIE_BASE | (x))
> > +#define WR(x, v) writel(v, RT_PCIE_BASE | (x))
> > +
> > +#define SYSCFG1  0x14
> > +#define RSTCTL   0x34
> > +#define RSTSTAT  0x38
> > +#define PCICFG   0x00
> > +#define PCIINT   0x08
> > +#define PCIENA   0x0c
> > +#define CFGADDR  0x20
> > +#define CFGDATA  0x24
> > +#define MEMBASE  0x28
> > +#define IOBASE   0x2c
> > +
> > +#define BAR0SETUP0x10
> > +#define IMBASEBAR0   0x18
> > +#define PCIE_CLASS   0x34
> > +#define PCIE_SISTAT  0x50
> > +
> > +#define MTK_PCIE_HIGH_PERF   BIT(14)
> > +#define PCIEP0_BASE  0x2000
> > +#define PCIEP1_BASE  0x3000
> > +#define PCIEP2_BASE  0x4000
> > +
> > +#define PHY_P0_CTL   0x9000
> > +#define PHY_P1_CTL   0xa000
> > +#define PHY_P2_CTL   0x4000 /* in USB space */
> > +
> > +#define RSTCTL_PCIE0_RST BIT(24)
> > +#define RSTCTL_PCIE1_RST BIT(25)
> > +#define RSTCTL_PCIE2_RST BIT(26)
> > +#define MAX_PORT_NUM 3
> > +
> > +struct resource {
> > + char *name;
> > + u32 start;
> > + u32 end;
> > +};
> > +
> > +struct mt_pcie {
> > + char name[16];
> > +};
> > +
> > +static struct mtk_pcie_port {
> > + int id;
> > + int enable;
> > + u32 base;
> > + u32 phy_base;
> > + u32 perst_n;
> > + u32 reset;
> > + u32 interrupt_en;
> > + int irq;
> > + u32 link;
> > +} mtk_pcie_port[] = {
> > + { 0, 1, PCIEP0_BASE, PHY_P0_CTL, BIT(1

Re: [U-Boot] [PATCH 3/4] pci: mediatek: Add pci-driver for mt2701

[Ryder Lee]

On Wed, 2019-07-31 at 17:13 +0300, Aleksandr Rybalko wrote:
> Hello Ryder.
> 
> 
> ср, 31 лип. 2019 о 15:45 Ryder Lee  пише:
> 
> + GSS_MTK_Uboot_upstream 
> 
> On Wed, 2019-07-31 at 13:51 +0200, Frank Wunderlich wrote:
> > From: Oleksandr Rybalko 
> > 
> > this chip is used in MT7623 and some other Mediatek SoCs for
> pcie
> > 
> > Tested-by: Frank Wunderlich 
> > Signed-off-by: Frank Wunderlich 
> > Signed-off-by: Oleksandr Rybalko 
> > ---
> >  drivers/pci/Kconfig  |   6 +
> >  drivers/pci/Makefile |   1 +
> >  drivers/pci/pci-mt2701.c | 490
> +++
> >  3 files changed, 497 insertions(+)
> >  create mode 100644 drivers/pci/pci-mt2701.c
> 
> Rename 'pci-mt2701.c' to 'pcie-mediatek.c' and then change the
> subject.
> 
> 
> So you promise us, that Mediatek will never produce PCI-E controller
> which will be totally different from that one? :)

imho we can use single driver for different IP generation and that is
what we did in linux now.

MT7623/MT2701 - mtk_pcie_soc_v1
MT7622/MT7629 - v2
gen3 IP - TBD
>  
> 
> Obviously, this is an intermediate version of Linux patch, so
> I suggest
> to take a look at the latest version of vanilla Kernel:
> 
> https://github.com/torvalds/linux/blob/master/drivers/pci/controller/pcie-mediatek.c
> 
> Please see my comments inline: 
> 
> > diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
> > index 3fe38f7315..cfe8ba5e52 100644
> > --- a/drivers/pci/Kconfig
> > +++ b/drivers/pci/Kconfig
> > @@ -145,4 +145,10 @@ config PCI_MVEBU
> > Say Y here if you want to enable PCIe controller
> support on
> > Armada XP/38x SoCs.
> > 
> > +config PCIE_MT2701
> > + bool "Mediatek 2701 PCI-E"
> > + help
> > +   Say Y here if you want to enable PCIe controller
> support on
> > +   Mediatek MT7623
> > +
> >  endif
> > diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
> > index b5ebd50c85..a4c4002b9c 100644
> > --- a/drivers/pci/Makefile
> > +++ b/drivers/pci/Makefile
> > @@ -38,3 +38,4 @@ obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) +=
> pcie_layerscape_gen4.o \
> >   pcie_layerscape_gen4_fixup.o
> >  obj-$(CONFIG_PCI_XILINX) += pcie_xilinx.o
> >  obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o
> > +obj-$(CONFIG_PCIE_MT2701) += pci-mt2701.o
> > diff --git a/drivers/pci/pci-mt2701.c
> b/drivers/pci/pci-mt2701.c
> > new file mode 100644
> > index 00..5904f15330
> > --- /dev/null
> > +++ b/drivers/pci/pci-mt2701.c
> > @@ -0,0 +1,490 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + *  Mediatek MT7623 SoC PCIE support
> > + *
> > + *  Copyright (C) 2015 Mediatek
> > + *  Copyright (C) 2015 John Crispin 
> > + *  Copyright (C) 2015 Ziv Huang 
> > + *  Copyright (C) 2019 Oleksandr Rybalko 
> > + */
> > +
> > +#include 
> > +#include 
> > +
> > +#include 
> > +#include 
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +#define iowrite32(v, a)  writel(v, a)
> > +#define iowrite16(v, a)  writew(v, a)
> > +#define iowrite8(v, a)   writeb(v, a)
> > +#define ioread32(a)  readl(a)
> > +#define ioread16(a)  readw(a)
> > +#define ioread8(a)   readb(a)
> 
> Remove these defines.
> 
> > +#define RT_HIFSYS_BASE   0x1a00
> > +#define RT_PCIE_BASE 0x1a14
> > +#define RT_PCIE_IOWIN_BASE   0x1a16
> > +#define RT_PCIE_IOWIN_SIZE   0x0001
> > +#define RT_PCIE_MEMWIN_BASE  0x6000
> > +#define RT_PCIE_MEMWIN_SIZE  0x1000
> 
> Move these base to dts.
> 
> 
> Already there (ranges), just not used yet.

so it's better remove unused parts, right?
> 
> > +#define RD(x)readl(RT_PCIE_BASE | (x))
> > +#define WR(x, v) writel(v, RT_PCIE_BASE | (x))
> > +
> > +#define SYSCFG1  0x14
> > +#define RSTCTL   0x34
> > +#define RSTSTAT  0x38
> > +#define PCICFG   0x00
> > +#define PCIINT   0x08
> > +#define PCIENA   0x0c
> > +#define CFGADDR  0x20
> > +#define CFGDATA   

Re: [U-Boot] [PATCH 3/4] pci: mediatek: Add pci-driver for mt2701

[Ryder Lee]

On Wed, 2019-07-31 at 22:35 +0800, Ryder Lee wrote:
> On Wed, 2019-07-31 at 17:13 +0300, Aleksandr Rybalko wrote:
> > Hello Ryder.
> > 
> > 
> > ср, 31 лип. 2019 о 15:45 Ryder Lee  пише:
> > 
> > + GSS_MTK_Uboot_upstream 
> > 
> > On Wed, 2019-07-31 at 13:51 +0200, Frank Wunderlich wrote:
> > > From: Oleksandr Rybalko 
> > > 
> > > this chip is used in MT7623 and some other Mediatek SoCs for
> > pcie
> > > 
> > > Tested-by: Frank Wunderlich 
> > > Signed-off-by: Frank Wunderlich 
> > > Signed-off-by: Oleksandr Rybalko 
> > > ---
> > >  drivers/pci/Kconfig  |   6 +
> > >  drivers/pci/Makefile |   1 +
> > >  drivers/pci/pci-mt2701.c | 490
> > +++
> > >  3 files changed, 497 insertions(+)
> > >  create mode 100644 drivers/pci/pci-mt2701.c
> > 
> > Rename 'pci-mt2701.c' to 'pcie-mediatek.c' and then change the
> > subject.
> > 
> > 
> > So you promise us, that Mediatek will never produce PCI-E controller
> > which will be totally different from that one? :)
> 
> imho we can use single driver for different IP generation and that is
> what we did in linux now.
> 
> MT7623/MT2701 - mtk_pcie_soc_v1
> MT7622/MT7629 - v2
> gen3 IP - TBD
> >  
> > 
> > Obviously, this is an intermediate version of Linux patch, so
> > I suggest
> > to take a look at the latest version of vanilla Kernel:
> > 
> > https://github.com/torvalds/linux/blob/master/drivers/pci/controller/pcie-mediatek.c
> > 
> > Please see my comments inline: 
> > 
> > > diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
> > > index 3fe38f7315..cfe8ba5e52 100644
> > > --- a/drivers/pci/Kconfig
> > > +++ b/drivers/pci/Kconfig
> > > @@ -145,4 +145,10 @@ config PCI_MVEBU
> > > Say Y here if you want to enable PCIe controller
> > support on
> > > Armada XP/38x SoCs.
> > > 
> > > +config PCIE_MT2701
> > > + bool "Mediatek 2701 PCI-E"
> > > + help
> > > +   Say Y here if you want to enable PCIe controller
> > support on
> > > +   Mediatek MT7623
> > > +
> > >  endif
> > > diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
> > > index b5ebd50c85..a4c4002b9c 100644
> > > --- a/drivers/pci/Makefile
> > > +++ b/drivers/pci/Makefile
> > > @@ -38,3 +38,4 @@ obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) +=
> > pcie_layerscape_gen4.o \
> > >   pcie_layerscape_gen4_fixup.o
> > >  obj-$(CONFIG_PCI_XILINX) += pcie_xilinx.o
> > >  obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o
> > > +obj-$(CONFIG_PCIE_MT2701) += pci-mt2701.o
> > > diff --git a/drivers/pci/pci-mt2701.c
> > b/drivers/pci/pci-mt2701.c
> > > new file mode 100644
> > > index 00..5904f15330
> > > --- /dev/null
> > > +++ b/drivers/pci/pci-mt2701.c
> > > @@ -0,0 +1,490 @@
> > > +// SPDX-License-Identifier: GPL-2.0+
> > > +/*
> > > + *  Mediatek MT7623 SoC PCIE support
> > > + *
> > > + *  Copyright (C) 2015 Mediatek
> > > + *  Copyright (C) 2015 John Crispin 
> > > + *  Copyright (C) 2015 Ziv Huang 
> > > + *  Copyright (C) 2019 Oleksandr Rybalko 
> > > + */
> > > +
> > > +#include 
> > > +#include 
> > > +
> > > +#include 
> > > +#include 
> > > +
> > > +#include 
> > > +#include 
> > > +#include 
> > > +#include 
> > > +
> > > +#define iowrite32(v, a)  writel(v, a)
> > > +#define iowrite16(v, a)  writew(v, a)
> > > +#define iowrite8(v, a)   writeb(v, a)
> > > +#define ioread32(a)  readl(a)
> > > +#define ioread16(a)  readw(a)
> > > +#define ioread8(a)   readb(a)
> > 
> > Remove these defines.
> > 
> > > +#define RT_HIFSYS_BASE   0x1a00
> > > +#define RT_PCIE_BASE 0x1a14
> > > +#define RT_PCIE_IOWIN_BASE   0x1a16
> > > +#define RT_PCIE_IOWIN_SIZE   0x0001
> > > +#define RT_PCIE_MEMWIN_BASE  0x6000
> > > +#define RT_PCIE_MEMWIN_SIZE  0x1000
> > 
> > Move these base to dts.
> > 
> > 
> > Already there (ranges), just not used yet.
> 
> so it's better remove unused parts, right?
> > 
> > > +#define RD(x)readl(RT_PCIE_BASE | (x))
> > > +#define WR(x, v) writel(v, RT_PCIE_BASE | (x))
> > > +
> > > +#define SYSCFG1  0x14
> > > +#define RSTCTL   0x34
> > 

[U-Boot] [PATCH 1/7] net: sh_eth: Add R8A77980 V3H gether support

[Marek Vasut]

The R8A77980 V3H gether needs a few minor adjustments to the sh_eth
driver, add them to support ethernet on R8A77980.

Signed-off-by: Marek Vasut 
Cc: Joe Hershberger 
Cc: Nobuhiro Iwamatsu 
---
 drivers/net/sh_eth.c | 15 +++
 drivers/net/sh_eth.h |  6 +-
 2 files changed, 16 insertions(+), 5 deletions(-)

diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index da79b766a6..485c4b71ad 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -374,10 +374,16 @@ static void sh_eth_write_hwaddr(struct sh_eth_info 
*port_info,
 static void sh_eth_mac_regs_config(struct sh_eth_dev *eth, unsigned char *mac)
 {
struct sh_eth_info *port_info = ð->port_info[eth->port];
+   unsigned long edmr;
 
/* Configure e-dmac registers */
-   sh_eth_write(port_info, (sh_eth_read(port_info, EDMR) & ~EMDR_DESC_R) |
-   (EMDR_DESC | EDMR_EL), EDMR);
+   edmr = sh_eth_read(port_info, EDMR);
+   edmr &= ~EMDR_DESC_R;
+   edmr |= EMDR_DESC | EDMR_EL;
+#if defined(CONFIG_R8A77980)
+   edmr |= EDMR_NBST;
+#endif
+   sh_eth_write(port_info, edmr, EDMR);
 
sh_eth_write(port_info, 0, EESIPR);
sh_eth_write(port_info, 0, TRSCER);
@@ -407,7 +413,7 @@ static void sh_eth_mac_regs_config(struct sh_eth_dev *eth, 
unsigned char *mac)
 
 #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
sh_eth_write(port_info, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
-#elif defined(CONFIG_RCAR_GEN2)
+#elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_R8A77980)
sh_eth_write(port_info, sh_eth_read(port_info, RMIIMR) | 0x1, RMIIMR);
 #endif
 }
@@ -426,7 +432,7 @@ static int sh_eth_phy_regs_config(struct sh_eth_dev *eth)
sh_eth_write(port_info, GECMR_100B, GECMR);
 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
sh_eth_write(port_info, 1, RTRATE);
-#elif defined(CONFIG_RCAR_GEN2)
+#elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_R8A77980)
val = ECMR_RTM;
 #endif
} else if (phy->speed == 10) {
@@ -931,6 +937,7 @@ static const struct udevice_id sh_ether_ids[] = {
{ .compatible = "renesas,ether-r8a7791" },
{ .compatible = "renesas,ether-r8a7793" },
{ .compatible = "renesas,ether-r8a7794" },
+   { .compatible = "renesas,gether-r8a77980" },
{ }
 };
 
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index e1bbd4913f..564cdaccb7 100644
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -358,6 +358,9 @@ static const u16 
sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 #elif defined(CONFIG_R7S72100)
 #define SH_ETH_TYPE_RZ
 #define BASE_IO_ADDR   0xE8203000
+#elif defined(CONFIG_R8A77980)
+#define SH_ETH_TYPE_GETHER
+#define BASE_IO_ADDR   0xE740
 #endif
 
 /*
@@ -374,6 +377,7 @@ enum EDSR_BIT {
 
 /* EDMR */
 enum DMAC_M_BIT {
+   EDMR_NBST   = 0x80, /* DMA transfer burst mode */
EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
EDMR_SRST   = 0x03, /* Receive/Send reset */
@@ -563,7 +567,7 @@ enum FELIC_MODE_BIT {
ECMR_PRM = 0x0001,
 #ifdef CONFIG_CPU_SH7724
ECMR_RTM = 0x0010,
-#elif defined(CONFIG_RCAR_GEN2)
+#elif defined(CONFIG_RCAR_GEN2) || defined (CONFIG_R8A77980)
ECMR_RTM = 0x0004,
 #endif
 
-- 
2.20.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 2/7] net: sh_eth: Fix 64bit build warnings

[Marek Vasut]

Fix various type warnings when building this driver for 64bit machine.

Signed-off-by: Marek Vasut 
Cc: Joe Hershberger 
Cc: Nobuhiro Iwamatsu 
---
 drivers/net/sh_eth.c | 24 
 drivers/net/sh_eth.h |  8 
 2 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 485c4b71ad..2d5c97062f 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -37,8 +37,8 @@
 #if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && \
!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 #define flush_cache_wback(addr, len)\
-   flush_dcache_range((u32)addr, \
-   (u32)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE)))
+   flush_dcache_range((unsigned long)addr, \
+   (unsigned long)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE)))
 #else
 #define flush_cache_wback(...)
 #endif
@@ -46,11 +46,11 @@
 #if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
 #define invalidate_cache(addr, len)\
{   \
-   u32 line_size = CONFIG_SH_ETHER_ALIGNE_SIZE;\
-   u32 start, end; \
+   unsigned long line_size = CONFIG_SH_ETHER_ALIGNE_SIZE;  \
+   unsigned long start, end;   \
\
-   start = (u32)addr;  \
-   end = start + len;  \
+   start = (unsigned long)addr;\
+   end = start + len;  \
start &= ~(line_size - 1);  \
end = ((end + line_size - 1) & ~(line_size - 1));   \
\
@@ -74,7 +74,7 @@ static int sh_eth_send_common(struct sh_eth_dev *eth, void 
*packet, int len)
}
 
/* packet must be a 4 byte boundary */
-   if ((int)packet & 3) {
+   if ((uintptr_t)packet & 3) {
printf(SHETHER_NAME ": %s: packet not 4 byte aligned\n"
, __func__);
ret = -EFAULT;
@@ -211,7 +211,7 @@ static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
 
/* Make sure we use a P2 address (non-cacheable) */
port_info->tx_desc_base =
-   (struct tx_desc_s *)ADDR_TO_P2((u32)port_info->tx_desc_alloc);
+   (struct tx_desc_s 
*)ADDR_TO_P2((uintptr_t)port_info->tx_desc_alloc);
port_info->tx_desc_cur = port_info->tx_desc_base;
 
/* Initialize all descriptors */
@@ -265,7 +265,7 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
 
/* Make sure we use a P2 address (non-cacheable) */
port_info->rx_desc_base =
-   (struct rx_desc_s *)ADDR_TO_P2((u32)port_info->rx_desc_alloc);
+   (struct rx_desc_s 
*)ADDR_TO_P2((uintptr_t)port_info->rx_desc_alloc);
 
port_info->rx_desc_cur = port_info->rx_desc_base;
 
@@ -281,7 +281,7 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
goto err_buf_alloc;
}
 
-   port_info->rx_buf_base = (u8 *)ADDR_TO_P2((u32)port_info->rx_buf_alloc);
+   port_info->rx_buf_base = (u8 
*)ADDR_TO_P2((uintptr_t)port_info->rx_buf_alloc);
 
/* Initialize all descriptors */
for (cur_rx_desc = port_info->rx_desc_base,
@@ -700,7 +700,7 @@ static int sh_ether_recv(struct udevice *dev, int flags, 
uchar **packetp)
struct sh_ether_priv *priv = dev_get_priv(dev);
struct sh_eth_dev *eth = &priv->shdev;
struct sh_eth_info *port_info = ð->port_info[eth->port];
-   uchar *packet = (uchar *)ADDR_TO_P2(port_info->rx_desc_cur->rd2);
+   uchar *packet = (uchar 
*)ADDR_TO_P2((uintptr_t)port_info->rx_desc_cur->rd2);
int len;
 
len = sh_eth_recv_start(eth);
@@ -850,7 +850,7 @@ static int sh_ether_probe(struct udevice *udev)
eth->port = CONFIG_SH_ETHER_USE_PORT;
eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
eth->port_info[eth->port].iobase =
-   (void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port);
+   (void __iomem *)(uintptr_t)(BASE_IO_ADDR + 0x800 * eth->port);
 
 #if CONFIG_IS_ENABLED(CLK)
ret = clk_enable(&priv->clk);
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index 564cdaccb7..d197dfdc40 100644
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -15,20 +15,20 @@
 #if defined(CONFIG_SH)
 /* Malloc returns addresses in the P1 area (cacheable). However we need to
use area P2 (non-cacheable) */
-#define ADDR_TO_P2(addr)   int)(addr) & ~0xe000) | 0xa000))
+#define ADDR_TO_P2(addr)   uintptr_t)(addr) & ~0xe000) | 
0xa000))
 
 /* The ethernet controller needs to use physical addresses */
 #if defined(CONFIG_SH_32BIT)
-#define ADDR_TO_PHY(addr)  int)(addr) & ~0xe000) | 0x4000))
+#define ADDR_TO_PHY(addr)  uintptr_t)(addr) & ~0xe000) | 
0x4000))
 #else
-#define ADDR_TO_PHY(addr)  ((int)(addr) & ~0xe000)
+#define ADDR_TO_PHY(addr)  ((uintptr_t)(addr) & ~0xe000)
 #endif
 

[U-Boot] [PATCH 3/7] pinctrl: renesas: Add R8A77980 V3H PFC tables

[Marek Vasut]

Import R8A77980 V3H PFC tables from Linux 5.1.21 , commit 4a9b1eb8bc3b.

Signed-off-by: Marek Vasut 
Cc: Nobuhiro Iwamatsu 
---
 drivers/pinctrl/renesas/Kconfig|   10 +
 drivers/pinctrl/renesas/Makefile   |1 +
 drivers/pinctrl/renesas/pfc-r8a77980.c | 2895 
 drivers/pinctrl/renesas/pfc.c  |   11 +
 drivers/pinctrl/renesas/sh_pfc.h   |1 +
 5 files changed, 2918 insertions(+)
 create mode 100644 drivers/pinctrl/renesas/pfc-r8a77980.c

diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig
index 0ffd7fcfd4..4d3d68d307 100644
--- a/drivers/pinctrl/renesas/Kconfig
+++ b/drivers/pinctrl/renesas/Kconfig
@@ -97,6 +97,16 @@ config PINCTRL_PFC_R8A77970
  the GPIO definitions and pin control functions for each available
  multiplex function.
 
+config PINCTRL_PFC_R8A77980
+   bool "Renesas RCar Gen3 R8A77980 pin control driver"
+   depends on PINCTRL_PFC
+   help
+ Support pin multiplexing control on Renesas RCar Gen3 R8A77980 SoCs.
+
+ The driver is controlled by a device tree node which contains both
+ the GPIO definitions and pin control functions for each available
+ multiplex function.
+
 config PINCTRL_PFC_R8A77990
bool "Renesas RCar Gen3 R8A77990 pin control driver"
depends on PINCTRL_PFC
diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile
index e8703f681e..a92f787a89 100644
--- a/drivers/pinctrl/renesas/Makefile
+++ b/drivers/pinctrl/renesas/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o
 obj-$(CONFIG_PINCTRL_PFC_R8A77965) += pfc-r8a77965.o
 obj-$(CONFIG_PINCTRL_PFC_R8A77970) += pfc-r8a77970.o
+obj-$(CONFIG_PINCTRL_PFC_R8A77980) += pfc-r8a77980.o
 obj-$(CONFIG_PINCTRL_PFC_R8A77990) += pfc-r8a77990.o
 obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o
 obj-$(CONFIG_PINCTRL_PFC_R7S72100) += pfc-r7s72100.o
diff --git a/drivers/pinctrl/renesas/pfc-r8a77980.c 
b/drivers/pinctrl/renesas/pfc-r8a77980.c
new file mode 100644
index 00..607b60aaf9
--- /dev/null
+++ b/drivers/pinctrl/renesas/pfc-r8a77980.c
@@ -0,0 +1,2895 @@
+// SPDX-Lincense-Identifier: GPL 2.0
+/*
+ * R8A77980 processor support - PFC hardware block.
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018 Cogent Embedded, Inc.
+ *
+ * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+ *
+ * R-Car Gen3 processor support - PFC hardware block.
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "sh_pfc.h"
+
+#define CPU_ALL_PORT(fn, sfx)  \
+   PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),  \
+   PORT_GP_28(1, fn, sfx), \
+   PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),  \
+   PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
+   PORT_GP_25(4, fn, sfx), \
+   PORT_GP_15(5, fn, sfx)
+
+/*
+ * F_() : just information
+ * FM() : macro for FN_xxx / xxx_MARK
+ */
+
+/* GPSR0 */
+#define GPSR0_21   F_(DU_EXODDF_DU_ODDF_DISP_CDE,  IP2_23_20)
+#define GPSR0_20   F_(DU_EXVSYNC_DU_VSYNC, IP2_19_16)
+#define GPSR0_19   F_(DU_EXHSYNC_DU_HSYNC, IP2_15_12)
+#define GPSR0_18   F_(DU_DOTCLKOUT,IP2_11_8)
+#define GPSR0_17   F_(DU_DB7,  IP2_7_4)
+#define GPSR0_16   F_(DU_DB6,  IP2_3_0)
+#define GPSR0_15   F_(DU_DB5,  IP1_31_28)
+#define GPSR0_14   F_(DU_DB4,  IP1_27_24)
+#define GPSR0_13   F_(DU_DB3,  IP1_23_20)
+#define GPSR0_12   F_(DU_DB2,  IP1_19_16)
+#define GPSR0_11   F_(DU_DG7,  IP1_15_12)
+#define GPSR0_10   F_(DU_DG6,  IP1_11_8)
+#define GPSR0_9F_(DU_DG5,  IP1_7_4)
+#define GPSR0_8F_(DU_DG4,  IP1_3_0)
+#define GPSR0_7F_(DU_DG3,  IP0_31_28)
+#define GPSR0_6F_(DU_DG2,  IP0_27_24)
+#define GPSR0_5F_(DU_DR7,  IP0_23_20)
+#define GPSR0_4F_(DU_DR6,  IP0_19_16)
+#define GPSR0_3F_(DU_DR5,  IP0_15_12)
+#define GPSR0_2F_(DU_DR4,  IP0_11_8)
+#define GPSR0_1F_(DU_DR3,  IP0_7_4)
+#define GPSR0_0F_(DU_DR2,  IP0_3_0)
+
+/* GPSR1 */
+#define GPSR1_27   F_(DIGRF_CLKOUT,IP8_31_28)
+#define GPSR1_26   F_(DIGRF_CLKIN, IP8_27_24)
+#define GPSR1_25   F_(CANFD_CLK_A, IP8_23_20)
+#define GPSR1_24   F_(CANFD1_RX,   IP8_19_16)
+#define GPSR1_23   F_(CANFD1_TX,   IP8_15_12)
+#define GPSR1_22   F_(CANFD0_RX_A

[U-Boot] [PATCH 5/7] ARM: dts: renesas: Add R8A77980 V3H DTs and headers

[Marek Vasut]

Import R8A77980 V3H DTs and headers from Linux 5.1.21 , commit 4a9b1eb8bc3b.

Signed-off-by: Marek Vasut 
Cc: Nobuhiro Iwamatsu 
---
 arch/arm/dts/r8a77980-u-boot.dtsi |   24 +
 arch/arm/dts/r8a77980.dtsi| 1589 +
 include/dt-bindings/clock/r8a77980-cpg-mssr.h |   51 +
 include/dt-bindings/power/r8a77980-sysc.h |   43 +
 4 files changed, 1707 insertions(+)
 create mode 100644 arch/arm/dts/r8a77980-u-boot.dtsi
 create mode 100644 arch/arm/dts/r8a77980.dtsi
 create mode 100644 include/dt-bindings/clock/r8a77980-cpg-mssr.h
 create mode 100644 include/dt-bindings/power/r8a77980-sysc.h

diff --git a/arch/arm/dts/r8a77980-u-boot.dtsi 
b/arch/arm/dts/r8a77980-u-boot.dtsi
new file mode 100644
index 00..7135244794
--- /dev/null
+++ b/arch/arm/dts/r8a77980-u-boot.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot on RCar R8A77980 SoC
+ *
+ * Copyright (C) 2019 Marek Vasut 
+ */
+
+#include "r8a779x-u-boot.dtsi"
+
+&extalr_clk {
+   u-boot,dm-pre-reloc;
+};
+
+/ {
+   soc {
+   rpc: rpc@0xee20 {
+   compatible = "renesas,rpc-r8a77980", "renesas,rpc";
+   reg = <0 0xee20 0 0x100>, <0 0x0800 0 0>;
+   clocks = <&cpg CPG_MOD 917>;
+   bank-width = <2>;
+   status = "disabled";
+   };
+   };
+};
diff --git a/arch/arm/dts/r8a77980.dtsi b/arch/arm/dts/r8a77980.dtsi
new file mode 100644
index 00..4081622d54
--- /dev/null
+++ b/arch/arm/dts/r8a77980.dtsi
@@ -0,0 +1,1589 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the R-Car V3H (R8A77980) SoC
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018 Cogent Embedded, Inc.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+/ {
+   compatible = "renesas,r8a77980";
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   aliases {
+   i2c0 = &i2c0;
+   i2c1 = &i2c1;
+   i2c2 = &i2c2;
+   i2c3 = &i2c3;
+   i2c4 = &i2c4;
+   i2c5 = &i2c5;
+   };
+
+   /* External CAN clock - to be overridden by boards that provide it */
+   can_clk: can {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <0>;
+   };
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   a53_0: cpu@0 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a53";
+   reg = <0>;
+   clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
+   power-domains = <&sysc R8A77980_PD_CA53_CPU0>;
+   next-level-cache = <&L2_CA53>;
+   enable-method = "psci";
+   };
+
+   a53_1: cpu@1 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a53";
+   reg = <1>;
+   clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
+   power-domains = <&sysc R8A77980_PD_CA53_CPU1>;
+   next-level-cache = <&L2_CA53>;
+   enable-method = "psci";
+   };
+
+   a53_2: cpu@2 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a53";
+   reg = <2>;
+   clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
+   power-domains = <&sysc R8A77980_PD_CA53_CPU2>;
+   next-level-cache = <&L2_CA53>;
+   enable-method = "psci";
+   };
+
+   a53_3: cpu@3 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a53";
+   reg = <3>;
+   clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
+   power-domains = <&sysc R8A77980_PD_CA53_CPU3>;
+   next-level-cache = <&L2_CA53>;
+   enable-method = "psci";
+   };
+
+   L2_CA53: cache-controller {
+   compatible = "cache";
+   power-domains = <&sysc R8A77980_PD_CA53_SCU>;
+   cache-unified;
+   cache-level = <2>;
+   };
+   };
+
+   extal_clk: extal {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   /* This value must be overridden by the board */
+   clock-frequency = <0>;
+   };
+
+   extalr_clk: extalr {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   /* This value must be overridden by the board */
+   clock-frequency = <0>;
+   };
+
+   /* External PCIe clock - ca

[U-Boot] [PATCH 6/7] ARM: renesas: Add R8A77980 V3H platform code

[Marek Vasut]

Add a few bits of platform code to support R8A77980 V3H SoC.

Signed-off-by: Marek Vasut 
Cc: Nobuhiro Iwamatsu 
---
 arch/arm/mach-rmobile/Kconfig.64 | 5 +
 arch/arm/mach-rmobile/cpu_info.c | 1 +
 arch/arm/mach-rmobile/include/mach/rmobile.h | 1 +
 3 files changed, 7 insertions(+)

diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64
index 27d29f797f..2d549f7bb4 100644
--- a/arch/arm/mach-rmobile/Kconfig.64
+++ b/arch/arm/mach-rmobile/Kconfig.64
@@ -22,6 +22,11 @@ config R8A77970
imply CLK_R8A77970
imply PINCTRL_PFC_R8A77970
 
+config R8A77980
+   bool "Renesas SoC R8A77980"
+   imply CLK_R8A77980
+   imply PINCTRL_PFC_R8A77980
+
 config R8A77990
bool "Renesas SoC R8A77990"
imply CLK_R8A77990
diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c
index 784a2a28d5..dc407d2a61 100644
--- a/arch/arm/mach-rmobile/cpu_info.c
+++ b/arch/arm/mach-rmobile/cpu_info.c
@@ -64,6 +64,7 @@ static const struct {
{ RMOBILE_CPU_TYPE_R8A7796, "R8A7796" },
{ RMOBILE_CPU_TYPE_R8A77965, "R8A77965" },
{ RMOBILE_CPU_TYPE_R8A77970, "R8A77970" },
+   { RMOBILE_CPU_TYPE_R8A77980, "R8A77980" },
{ RMOBILE_CPU_TYPE_R8A77990, "R8A77990" },
{ RMOBILE_CPU_TYPE_R8A77995, "R8A77995" },
{ 0x0, "CPU" },
diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h 
b/arch/arm/mach-rmobile/include/mach/rmobile.h
index aa8d43e59b..a50249dc96 100644
--- a/arch/arm/mach-rmobile/include/mach/rmobile.h
+++ b/arch/arm/mach-rmobile/include/mach/rmobile.h
@@ -36,6 +36,7 @@
 #define RMOBILE_CPU_TYPE_R8A7796   0x52
 #define RMOBILE_CPU_TYPE_R8A77965  0x55
 #define RMOBILE_CPU_TYPE_R8A77970  0x54
+#define RMOBILE_CPU_TYPE_R8A77980  0x56
 #define RMOBILE_CPU_TYPE_R8A77990  0x57
 #define RMOBILE_CPU_TYPE_R8A77995  0x58
 
-- 
2.20.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 7/7] ARM: renesas: Add R8A77980 V3H Condor board code

[Marek Vasut]

Add board code for the R8A77980 V3H Condor board.

Signed-off-by: Marek Vasut 
Cc: Nobuhiro Iwamatsu 
---
 arch/arm/dts/Makefile   |   1 +
 arch/arm/dts/r8a77980-condor-u-boot.dts |  34 +++
 arch/arm/dts/r8a77980-condor.dts| 292 
 arch/arm/mach-rmobile/Kconfig.64|   7 +
 board/renesas/condor/Kconfig|  15 ++
 board/renesas/condor/MAINTAINERS|   6 +
 board/renesas/condor/Makefile   |  13 ++
 board/renesas/condor/condor.c   |  55 +
 configs/r8a77980_condor_defconfig   |  69 ++
 include/configs/condor.h|  41 
 10 files changed, 533 insertions(+)
 create mode 100644 arch/arm/dts/r8a77980-condor-u-boot.dts
 create mode 100644 arch/arm/dts/r8a77980-condor.dts
 create mode 100644 board/renesas/condor/Kconfig
 create mode 100644 board/renesas/condor/MAINTAINERS
 create mode 100644 board/renesas/condor/Makefile
 create mode 100644 board/renesas/condor/condor.c
 create mode 100644 configs/r8a77980_condor_defconfig
 create mode 100644 include/configs/condor.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 49d1faef32..5f4ffc5717 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -640,6 +640,7 @@ dtb-$(CONFIG_RCAR_GEN3) += \
r8a77965-m3nulcb-u-boot.dtb \
r8a77965-salvator-x-u-boot.dtb \
r8a77970-eagle-u-boot.dtb \
+   r8a77980-condor-u-boot.dtb \
r8a77990-ebisu-u-boot.dtb \
r8a77995-draak-u-boot.dtb
 
diff --git a/arch/arm/dts/r8a77980-condor-u-boot.dts 
b/arch/arm/dts/r8a77980-condor-u-boot.dts
new file mode 100644
index 00..1b22c7f0b9
--- /dev/null
+++ b/arch/arm/dts/r8a77980-condor-u-boot.dts
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source extras for U-Boot for the Condor board
+ *
+ * Copyright (C) 2019 Marek Vasut 
+ */
+
+#include "r8a77980-condor.dts"
+#include "r8a77980-u-boot.dtsi"
+
+/ {
+   aliases {
+   spi0 = &rpc;
+   };
+};
+
+&rpc {
+   num-cs = <1>;
+   status = "okay";
+   spi-max-frequency = <5000>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   flash0: spi-flash@0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "s25fs512s", "jedec,spi-nor";
+   spi-max-frequency = <5000>;
+   spi-tx-bus-width = <1>;
+   spi-rx-bus-width = <1>;
+   reg = <0>;
+   status = "okay";
+   };
+};
diff --git a/arch/arm/dts/r8a77980-condor.dts b/arch/arm/dts/r8a77980-condor.dts
new file mode 100644
index 00..5a7012be0d
--- /dev/null
+++ b/arch/arm/dts/r8a77980-condor.dts
@@ -0,0 +1,292 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the Condor board
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018 Cogent Embedded, Inc.
+ */
+
+/dts-v1/;
+#include "r8a77980.dtsi"
+
+/ {
+   model = "Renesas Condor board based on r8a77980";
+   compatible = "renesas,condor", "renesas,r8a77980";
+
+   aliases {
+   serial0 = &scif0;
+   ethernet0 = &gether;
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   memory@4800 {
+   device_type = "memory";
+   /* first 128MB is reserved for secure area. */
+   reg = <0 0x4800 0 0x7800>;
+   };
+
+   d3_3v: regulator-0 {
+   compatible = "regulator-fixed";
+   regulator-name = "D3.3V";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-boot-on;
+   regulator-always-on;
+   };
+
+   vddq_vin01: regulator-1 {
+   compatible = "regulator-fixed";
+   regulator-name = "VDDQ_VIN01";
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   regulator-boot-on;
+   regulator-always-on;
+   };
+
+   d1_8v: regulator-2 {
+   compatible = "regulator-fixed";
+   regulator-name = "D1.8V";
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   regulator-boot-on;
+   regulator-always-on;
+   };
+
+   hdmi-out {
+   compatible = "hdmi-connector";
+   type = "a";
+
+   port {
+   hdmi_con: endpoint {
+   remote-endpoint = <&adv7511_out>;
+   };
+   };
+   };
+
+   lvds-decoder {
+   compatible = "thine,thc63lvd1024";
+   vcc-supply = <&d3_3v>;
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@0 {
+   reg = 

[U-Boot] [PATCH 4/7] clk: renesas: Add R8A77980 V3H clock tables

[Marek Vasut]

Import R8A77980 V3H clock tables from Linux 5.1.21 , commit 4a9b1eb8bc3b.

Signed-off-by: Marek Vasut 
Cc: Nobuhiro Iwamatsu 
---
 drivers/clk/renesas/Kconfig |   6 +
 drivers/clk/renesas/Makefile|   1 +
 drivers/clk/renesas/r8a77980-cpg-mssr.c | 255 
 3 files changed, 262 insertions(+)
 create mode 100644 drivers/clk/renesas/r8a77980-cpg-mssr.c

diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 3862c1b848..e78817829b 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -72,6 +72,12 @@ config CLK_R8A77970
help
  Enable this to support the clocks on Renesas R8A77970 SoC.
 
+config CLK_R8A77980
+   bool "Renesas R8A77980 clock driver"
+   depends on CLK_RCAR_GEN3
+   help
+ Enable this to support the clocks on Renesas R8A77980 SoC.
+
 config CLK_R8A77990
bool "Renesas R8A77990 clock driver"
depends on CLK_RCAR_GEN3
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index 26b343994c..88339e9d7e 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -10,5 +10,6 @@ obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A77965) += r8a77965-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o
 obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
diff --git a/drivers/clk/renesas/r8a77980-cpg-mssr.c 
b/drivers/clk/renesas/r8a77980-cpg-mssr.c
new file mode 100644
index 00..6fe8ea5edf
--- /dev/null
+++ b/drivers/clk/renesas/r8a77980-cpg-mssr.c
@@ -0,0 +1,255 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * r8a77980 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018 Cogent Embedded, Inc.
+ *
+ * Based on r8a7795-cpg-mssr.c
+ *
+ * Copyright (C) 2015 Glider bvba
+ */
+
+#include 
+#include 
+#include 
+
+#include 
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen3-cpg.h"
+
+enum clk_ids {
+   /* Core Clock Outputs exported to DT */
+   LAST_DT_CORE_CLK = R8A77980_CLK_OSC,
+
+   /* External Input Clocks */
+   CLK_EXTAL,
+   CLK_EXTALR,
+
+   /* Internal Core Clocks */
+   CLK_MAIN,
+   CLK_PLL1,
+   CLK_PLL2,
+   CLK_PLL3,
+   CLK_PLL1_DIV2,
+   CLK_PLL1_DIV4,
+   CLK_S0,
+   CLK_S1,
+   CLK_S2,
+   CLK_S3,
+   CLK_SDSRC,
+   CLK_RPCSRC,
+   CLK_OCO,
+
+   /* Module Clocks */
+   MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a77980_core_clks[] = {
+   /* External Clock Inputs */
+   DEF_INPUT("extal",  CLK_EXTAL),
+   DEF_INPUT("extalr", CLK_EXTALR),
+
+   /* Internal Core Clocks */
+   DEF_BASE(".main",   CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
+   DEF_BASE(".pll1",   CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
+   DEF_BASE(".pll2",   CLK_PLL2, CLK_TYPE_GEN3_PLL2, CLK_MAIN),
+   DEF_BASE(".pll3",   CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
+
+   DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1,   2, 1),
+   DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2,  2, 1),
+   DEF_FIXED(".s0",CLK_S0,CLK_PLL1_DIV2,  2, 1),
+   DEF_FIXED(".s1",CLK_S1,CLK_PLL1_DIV2,  3, 1),
+   DEF_FIXED(".s2",CLK_S2,CLK_PLL1_DIV2,  4, 1),
+   DEF_FIXED(".s3",CLK_S3,CLK_PLL1_DIV2,  6, 1),
+   DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2,  2, 1),
+   DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
+   DEF_RATE(".oco",CLK_OCO,   32768),
+
+   DEF_BASE("rpc", R8A77980_CLK_RPC, CLK_TYPE_GEN3_RPC,
+CLK_RPCSRC),
+   DEF_BASE("rpcd2",   R8A77980_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
+R8A77980_CLK_RPC),
+
+   /* Core Clock Outputs */
+   DEF_FIXED("ztr",R8A77980_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
+   DEF_FIXED("ztrd2",  R8A77980_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
+   DEF_FIXED("zt", R8A77980_CLK_ZT,CLK_PLL1_DIV2,  4, 1),
+   DEF_FIXED("zx", R8A77980_CLK_ZX,CLK_PLL1_DIV2,  2, 1),
+   DEF_FIXED("s0d1",   R8A77980_CLK_S0D1,  CLK_S0, 1, 1),
+   DEF_FIXED("s0d2",   R8A77980_CLK_S0D2,  CLK_S0, 2, 1),
+   DEF_FIXED("s0d3",   R8A77980_CLK_S0D3,  CLK_S0, 3, 1),
+   DEF_FIXED("s0d4",   R8A77980_CLK_S0D4,  CLK_S0, 4, 1),
+   DEF_FIXED("s0d6",   R8A77980_CLK_S0D6,  CLK_S0, 6, 1),
+   DEF_FIXED("s0d12",  R8A77980_CLK_S0D12, CLK_S0,12, 1),
+   DEF_FIXED("s0d24",  R8A77980_CLK_S0D24, CLK_S0,24, 1),
+   DEF_FIXED("s1d1",   R8A77980_CLK_S1D1,  CLK_S1, 1, 1),
+   DEF_FIXED("s1d2

Re: [U-Boot] [PATCH v2 1/2] dm: core: device: switch off power domain after device removal

[Anatolij Gustschin]

Hi Simon,

On Thu, 18 Jul 2019 09:22:20 -0600
Simon Glass s...@chromium.org wrote:
...
> > >  drivers/core/device-remove.c | 9 +
> > >  include/dm/device.h  | 6 ++
> > >  2 files changed, 15 insertions(+)  
> 
> Unfortunately this causes a test failure (make qcheck). Can you please
> take a look?

The dm power_domain test worked, but later when
 dm_test_destroy()
  -> uclass_destroy()
removes devices, first 'power-domain' device is removed, then
the 'power-domain-test' device. When removing the latter, we run

 if (!power_domain_get(dev, &pd))
   power_domain_off(&pd);

and this probes sandbox_power_domain driver for 'power-domain' device
activating this device again. Then 'power-domain-test' device is removed,
but 'power-domain' is active. When unbinding it later, we get this error
in device_unbind():

if (dev->flags & DM_FLAG_ACTIVATED)
return -EINVAL;

Following will fix it:

diff --git a/drivers/core/device-remove.c b/drivers/core/device-remove.c
index 586fadee0a..fadb05c944 100644
--- a/drivers/core/device-remove.c
+++ b/drivers/core/device-remove.c
@@ -64,7 +64,8 @@ int device_unbind(struct udevice *dev)
if (!dev)
return -EINVAL;
 
-   if (dev->flags & DM_FLAG_ACTIVATED)
+   if (dev->flags & DM_FLAG_ACTIVATED &&
+   device_get_uclass_id(dev) != UCLASS_POWER_DOMAIN)
return -EINVAL;
 
if (!(dev->flags & DM_FLAG_BOUND))

But I'm not sure if this it the correct approach. What do you think?

Thanks,
Anatolij
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH 3/4] pci: mediatek: Add pci-driver for mt2701

[Frank Wunderlich]

Hi Ryder,

you know that we cannot write a full, multi-device driver here :)

> Gesendet: Mittwoch, 31. Juli 2019 um 17:23 Uhr
> Von: "Ryder Lee" 
> > imho we can use single driver for different IP generation and that is
> > what we did in linux now.
> >
> > MT7623/MT2701 - mtk_pcie_soc_v1
> > MT7622/MT7629 - v2
> > gen3 IP - TBD

i ack that's the right way, but this cannot be done by people outside (that do 
not have knowledge about multiple chips the driver should cover) and not only 
in freetime, so our approach was to create a driver for this chip (that is also 
used by other soc) as base for future developement (extending for other boards).

on any time it needs to be replaced by a more universal variant to have not the 
same code multiple times. but thats far away from we can do here

it's not the best code (based on magic values and portability to other 
devices), but from my point of view we have working sata and do not modify 
existing code too much (to avoid side-effects), but only figuring out which 
consts are used in linux take much time for us

> > phy driver is used for configuring basic settings, there is no complex
> > logic in it. we can even copy and paste the entire block from that
> > driver.
you know the technical details :)
what we do is read out registers in linux and try to adapt this in uboot ;) 
because drivercode itself is too big for us to understand

> > .version = MTK_PHY_V1
> > case PHY_TYPE_PCIE:
> > pcie_phy_instance_init(tphy, instance);
> More specifically, we should use pci_generic_mmap_write/read_config()
> for standard set of confi read/write operations so that we can get rid
> of the helpers here.

a general way is right, but not possible to created by people not working for 
mtk :) without the right documentation

we do not have the knowledge to port a driver like this from linux to uboot

> I think the uboot driver end up dealing with nothing but just doing some
> initial parts (< 300 lines I guess), or you can take pcie_xilinx or
> pci_tegra as examples.
> > we can directly replace these chunks with mtk_pcie_startup_port()
> > (pcie-mediatek.c) and there are many defines for the registers/bit
> > field.

i tried this, but just C&P does not work ( i'm not that naive :) ) because of 
many depencies (functions used in linux-variant), i have already changed some 
things, but it ended in needed touching corefiles of uboot (e.g. extending 
pci.h) which may break other drivers.

but at least i have this version (with some fix-ups you've mentioned here) on 
my github-repo so that everybody can use it for my board/other boards using 
mt2701

https://github.com/frank-w/u-boot/commits/2019-07-bpi-r2-sata_new (will merge 
that in other main branches till official driver is there)

regards Frank
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 0/7] Add TPL support for Pine64 Rock64 board.

[Matwey V. Kornilov]

This series adds initial TPL support for Pine64 Rock64 board.

The ROCK64 is a credit card size SBC based on Rockchip RK3328 Quad-Core ARM 
Cortex A53.

The series has been tested with ATF v2.1.

Some patches in the series are taken from 
https://github.com/rockchip-linux/u-boot
Credits are given in each patch separately. 

Kever Yang (5):
  rockchip: ram: add full feature rk3328 DRAM driver
  rockchip: dts: rk3328: update dmc node for driver
  rockchip: dts: rk3328: enable the drivers need by TPL/SPL
  rockchip: Kconfig: enable TPL support for rk3328
  rockchip: evb-rk3328: enable defconfig options for TPL/SPL

Matwey V. Kornilov (2):
  configs: rk3328: enable TPL for rock64-rk3328_defconfig
  doc: rockchip: Adapt Pine64 Rock64 board instructions

 arch/arm/dts/rk3328-evb.dts   |3 +
 arch/arm/dts/rk3328-rock64-u-boot.dtsi|2 +
 arch/arm/dts/rk3328-sdram-ddr3-666.dtsi   |  215 +
 arch/arm/dts/rk3328-sdram-lpddr3-1600.dtsi|  215 +
 arch/arm/dts/rk3328-sdram-lpddr3-666.dtsi |  215 +
 arch/arm/dts/rk3328.dtsi  |   12 +-
 arch/arm/include/asm/arch-rockchip/sdram_rk3328.h |  441 +
 arch/arm/mach-rockchip/Kconfig|   21 +
 configs/evb-rk3328_defconfig  |   37 +-
 configs/rock64-rk3328_defconfig   |   14 +
 doc/README.rockchip   |   10 +-
 drivers/ram/rockchip/sdram_rk3328.c   | 1018 -
 12 files changed, 2187 insertions(+), 16 deletions(-)
 create mode 100644 arch/arm/dts/rk3328-sdram-ddr3-666.dtsi
 create mode 100644 arch/arm/dts/rk3328-sdram-lpddr3-1600.dtsi
 create mode 100644 arch/arm/dts/rk3328-sdram-lpddr3-666.dtsi
 create mode 100644 arch/arm/include/asm/arch-rockchip/sdram_rk3328.h

-- 
2.16.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 5/7] rockchip: evb-rk3328: enable defconfig options for TPL/SPL

[Matwey V. Kornilov]

From: Kever Yang 

Enable driver options for TPL/SPL in evb-rk3328_defconfig.

Signed-off-by: Kever Yang 
[cherry picked from commit 
https://github.com/rockchip-linux/u-boot/commit/df4f40acb449815384e397dcaf5b618bbc6cd855
 with minor modifications]
Signed-off-by: Matwey V. Kornilov 
---
 configs/evb-rk3328_defconfig | 37 +++--
 1 file changed, 35 insertions(+), 2 deletions(-)

diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig
index fcc04f27ec..12be1dedc6 100644
--- a/configs/evb-rk3328_defconfig
+++ b/configs/evb-rk3328_defconfig
@@ -1,5 +1,11 @@
 CONFIG_ARM=y
 CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
 CONFIG_SYS_TEXT_BASE=0x0020
 CONFIG_ROCKCHIP_RK3328=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
@@ -9,31 +15,50 @@ CONFIG_DEBUG_UART_CLOCK=2400
 CONFIG_DEBUG_UART=y
 # CONFIG_ANDROID_BOOT_IMAGE is not set
 CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-evb.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_ATF_SUPPORT=y
+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_TPL_BOOTROM_SUPPORT=y
+CONFIG_TPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_TPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_TPL_SERIAL_PRESENT=y
+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4
+CONFIG_SPL_STACK_R_ADDR=0x60
+CONFIG_DEFAULT_DEVICE_TREE="rk3328-evb"
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TIME=y
-CONFIG_DEFAULT_DEVICE_TREE="rk3328-evb"
 CONFIG_SPL_OF_CONTROL=y
+CONFIG_TPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names 
interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TPL_DM=y
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
+CONFIG_TPL_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_SPL_SYSCON=y
+CONFIG_TPL_SYSCON=y
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
+CONFIG_TPL_CLK=y
 CONFIG_FASTBOOT_BUF_ADDR=0x800800
 CONFIG_FASTBOOT_FLASH=y
 CONFIG_FASTBOOT_FLASH_MMC_DEV=1
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 CONFIG_ROCKCHIP_GPIO=y
+CONFIG_TPL_OF_PLATDATA=y
 CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
@@ -44,6 +69,7 @@ CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
 CONFIG_PHY=y
 CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_RK8XX=y
 CONFIG_REGULATOR_PWM=y
@@ -51,9 +77,14 @@ CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_REGULATOR_RK8XX=y
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_TPL_RAM=y
 CONFIG_BAUDRATE=150
 CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
 CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
@@ -69,4 +100,6 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x2207
 CONFIG_USB_GADGET_PRODUCT_NUM=0x330a
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USE_TINY_PRINTF=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_TPL_TINY_MEMSET=y
 CONFIG_ERRNO_STR=y
-- 
2.16.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 3/7] rockchip: dts: rk3328: enable the drivers need by TPL/SPL

[Matwey V. Kornilov]

From: Kever Yang 

Enable the drivers need by TPL/SPL with 'u-boot,dm-pre-reloc'.

Signed-off-by: Kever Yang 
[cherry picked from commit 
https://github.com/rockchip-linux/u-boot/commit/664225d1610d77ef64ed9a4f42d36474362592cc]
Signed-off-by: Matwey V. Kornilov 
---
 arch/arm/dts/rk3328-evb.dts | 2 ++
 arch/arm/dts/rk3328.dtsi| 1 +
 2 files changed, 3 insertions(+)

diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts
index 3b01dd0a87..fa8b1b18da 100644
--- a/arch/arm/dts/rk3328-evb.dts
+++ b/arch/arm/dts/rk3328-evb.dts
@@ -61,6 +61,7 @@
 };
 
 &uart2 {
+   u-boot,dm-pre-reloc;
status = "okay";
 };
 
@@ -77,6 +78,7 @@
 };
 
 &emmc {
+   u-boot,dm-pre-reloc;
bus-width = <8>;
cap-mmc-highspeed;
supports-emmc;
diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi
index a080ae8d69..4ec5d3e1f3 100644
--- a/arch/arm/dts/rk3328.dtsi
+++ b/arch/arm/dts/rk3328.dtsi
@@ -363,6 +363,7 @@
};
 
cru: clock-controller@ff44 {
+   u-boot,dm-pre-reloc;
compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
reg = <0x0 0xff44 0x0 0x1000>;
rockchip,grf = <&grf>;
-- 
2.16.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 2/7] rockchip: dts: rk3328: update dmc node for driver

[Matwey V. Kornilov]

From: Kever Yang 

Update dmc node for full feature driver.

Signed-off-by: Kever Yang 
[cherry picked from commit 
https://github.com/rockchip-linux/u-boot/commit/1e1495636574c78ea9d3af3e0aae95d5204612d6
 with minor modifications]
Signed-off-by: Matwey V. Kornilov 
---
 arch/arm/dts/rk3328-evb.dts|   1 +
 arch/arm/dts/rk3328-rock64-u-boot.dtsi |   2 +
 arch/arm/dts/rk3328-sdram-ddr3-666.dtsi| 215 +
 arch/arm/dts/rk3328-sdram-lpddr3-1600.dtsi | 215 +
 arch/arm/dts/rk3328-sdram-lpddr3-666.dtsi  | 215 +
 arch/arm/dts/rk3328.dtsi   |  11 +-
 6 files changed, 656 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/dts/rk3328-sdram-ddr3-666.dtsi
 create mode 100644 arch/arm/dts/rk3328-sdram-lpddr3-1600.dtsi
 create mode 100644 arch/arm/dts/rk3328-sdram-lpddr3-666.dtsi

diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts
index ec594a8452..3b01dd0a87 100644
--- a/arch/arm/dts/rk3328-evb.dts
+++ b/arch/arm/dts/rk3328-evb.dts
@@ -5,6 +5,7 @@
 
 /dts-v1/;
 #include "rk3328.dtsi"
+#include "rk3328-sdram-ddr3-666.dtsi"
 
 / {
model = "Rockchip RK3328 EVB";
diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi 
b/arch/arm/dts/rk3328-rock64-u-boot.dtsi
index b077436cbc..a01f758e9f 100644
--- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi
@@ -4,6 +4,8 @@
  * SPDX-License-Identifier: GPL-2.0+
  */
 
+#include "rk3328-sdram-lpddr3-1600.dtsi"
+
 / {
aliases {
mmc0 = &emmc;
diff --git a/arch/arm/dts/rk3328-sdram-ddr3-666.dtsi 
b/arch/arm/dts/rk3328-sdram-ddr3-666.dtsi
new file mode 100644
index 00..d99e7e0352
--- /dev/null
+++ b/arch/arm/dts/rk3328-sdram-ddr3-666.dtsi
@@ -0,0 +1,215 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+&dmc {
+   rockchip,sdram-params = <
+   0x1
+   0xC
+   0x3
+   0x1
+   0x0
+   0x0
+   0x10
+   0x10
+   0
+
+   0x9028b189
+   0x
+   0x0021
+   0x0482
+   0x0015
+   0x0222
+   0x00ff
+
+   333
+   3
+   0
+
+   0x
+   0x43041001
+   0x0064
+   0x0028003b
+   0x00d0
+   0x00020053
+   0x00d4
+   0x0002
+   0x00d8
+   0x0100
+   0x00dc
+   0x0320
+   0x00e0
+   0x
+   0x00e4
+   0x0009
+   0x00f4
+   0x000f011f
+   0x0100
+   0x07090b06
+   0x0104
+   0x00050209
+   0x0108
+   0x03030407
+   0x010c
+   0x00202006
+   0x0110
+   0x03020204
+   0x0114
+   0x03030202
+   0x0120
+   0x0903
+   0x0180
+   0x00800020
+   0x0184
+   0x
+   0x0190
+   0x07010001
+   0x0198
+   0x05001100
+   0x01a0
+   0xc043
+   0x0240
+   0x06000604
+   0x0244
+   0x0201
+   0x0250
+   0x0f00
+   0x0490
+   0x0001
+   0x
+   0x
+   0x
+   0x
+   0x
+   0x
+   0x
+   0x
+   0x
+   0x
+
+   0x0004
+   0x000a
+   0x0028
+   0x0006
+   0x002c
+   0x
+   0x0030
+   0x0005
+   0x
+   0x
+
+   0x77
+   0x88
+   0x79
+   0x79
+   0x87
+   0x97
+   0x87
+   0x78
+   0x77
+   0x78
+   0x87
+   0x88
+   0x87
+   0x87
+   0x77
+
+   0x78
+   0x78
+   0x78
+   0x78
+   0x78
+   0x78
+   0x78
+   0x78
+   0x78
+   0x69
+   0x9
+
+   0x77
+   0x78
+   0x77
+   0x78
+   0x77
+   0x78
+   0x77
+

[U-Boot] [PATCH 1/7] rockchip: ram: add full feature rk3328 DRAM driver

[Matwey V. Kornilov]

From: Kever Yang 

This driver supports DDR3/LPDDR3/DDR4 SDRAM initialization.

Signed-off-by: YouMin Chen 
Signed-off-by: Kever Yang 
[cherry picked from commit 
https://github.com/rockchip-linux/u-boot/commit/9fb0777ec3cc6a89af9d2e0969c3bfe58306a88d
 with minor modifications]
Signed-off-by: Matwey V. Kornilov 
---
 arch/arm/include/asm/arch-rockchip/sdram_rk3328.h |  441 +
 drivers/ram/rockchip/sdram_rk3328.c   | 1018 -
 2 files changed, 1456 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-rockchip/sdram_rk3328.h

diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h 
b/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h
new file mode 100644
index 00..11411ead10
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3328.h
@@ -0,0 +1,441 @@
+/*
+ * Copyright (C) 2016-2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_SDRAM_RK3328_H
+#define _ASM_ARCH_SDRAM_RK3328_H
+
+#define SR_IDLE93
+#define PD_IDLE13
+#define SDRAM_ADDR 0x
+#define PATTERN(0x5aa5f00f)
+
+/* ddr pctl registers define */
+#define DDR_PCTL2_MSTR 0x0
+#define DDR_PCTL2_STAT 0x4
+#define DDR_PCTL2_MSTR10x8
+#define DDR_PCTL2_MRCTRL0  0x10
+#define DDR_PCTL2_MRCTRL1  0x14
+#define DDR_PCTL2_MRSTAT   0x18
+#define DDR_PCTL2_MRCTRL2  0x1c
+#define DDR_PCTL2_DERATEEN 0x20
+#define DDR_PCTL2_DERATEINT0x24
+#define DDR_PCTL2_PWRCTL   0x30
+#define DDR_PCTL2_PWRTMG   0x34
+#define DDR_PCTL2_HWLPCTL  0x38
+#define DDR_PCTL2_RFSHCTL0 0x50
+#define DDR_PCTL2_RFSHCTL1 0x54
+#define DDR_PCTL2_RFSHCTL2 0x58
+#define DDR_PCTL2_RFSHCTL4 0x5c
+#define DDR_PCTL2_RFSHCTL3 0x60
+#define DDR_PCTL2_RFSHTMG  0x64
+#define DDR_PCTL2_RFSHTMG1 0x68
+#define DDR_PCTL2_RFSHCTL5 0x6c
+#define DDR_PCTL2_INIT00xd0
+#define DDR_PCTL2_INIT10xd4
+#define DDR_PCTL2_INIT20xd8
+#define DDR_PCTL2_INIT30xdc
+#define DDR_PCTL2_INIT40xe0
+#define DDR_PCTL2_INIT50xe4
+#define DDR_PCTL2_INIT60xe8
+#define DDR_PCTL2_INIT70xec
+#define DDR_PCTL2_DIMMCTL  0xf0
+#define DDR_PCTL2_RANKCTL  0xf4
+#define DDR_PCTL2_CHCTL0xfc
+#define DDR_PCTL2_DRAMTMG0 0x100
+#define DDR_PCTL2_DRAMTMG1 0x104
+#define DDR_PCTL2_DRAMTMG2 0x108
+#define DDR_PCTL2_DRAMTMG3 0x10c
+#define DDR_PCTL2_DRAMTMG4 0x110
+#define DDR_PCTL2_DRAMTMG5 0x114
+#define DDR_PCTL2_DRAMTMG6 0x118
+#define DDR_PCTL2_DRAMTMG7 0x11c
+#define DDR_PCTL2_DRAMTMG8 0x120
+#define DDR_PCTL2_DRAMTMG9 0x124
+#define DDR_PCTL2_DRAMTMG100x128
+#define DDR_PCTL2_DRAMTMG110x12c
+#define DDR_PCTL2_DRAMTMG120x130
+#define DDR_PCTL2_DRAMTMG130x134
+#define DDR_PCTL2_DRAMTMG140x138
+#define DDR_PCTL2_DRAMTMG150x13c
+#define DDR_PCTL2_DRAMTMG160x140
+#define DDR_PCTL2_ZQCTL0   0x180
+#define DDR_PCTL2_ZQCTL1   0x184
+#define DDR_PCTL2_ZQCTL2   0x188
+#define DDR_PCTL2_ZQSTAT   0x18c
+#define DDR_PCTL2_DFITMG0  0x190
+#define DDR_PCTL2_DFITMG1  0x194
+#define DDR_PCTL2_DFILPCFG00x198
+#define DDR_PCTL2_DFILPCFG10x19c
+#define DDR_PCTL2_DFIUPD0  0x1a0
+#define DDR_PCTL2_DFIUPD1  0x1a4
+#define DDR_PCTL2_DFIUPD2  0x1a8
+#define DDR_PCTL2_DFIMISC  0x1b0
+#define DDR_PCTL2_DFITMG2  0x1b4
+#define DDR_PCTL2_DFITMG3  0x1b8
+#define DDR_PCTL2_DFISTAT  0x1bc
+#define DDR_PCTL2_DBICTL   0x1c0
+#define DDR_PCTL2_ADDRMAP0 0x200
+#define DDR_PCTL2_ADDRMAP1 0x204
+#define DDR_PCTL2_ADDRMAP2 0x208
+#define DDR_PCTL2_ADDRMAP3 0x20c
+#define DDR_PCTL2_ADDRMAP4 0x210
+#define DDR_PCTL2_ADDRMAP5 0x214
+#define DDR_PCTL2_ADDRMAP6 0x218
+#define DDR_PCTL2_ADDRMAP7 0x21c
+#define DDR_PCTL2_ADDRMAP8 0x220
+#define DDR_PCTL2_ADDRMAP9 0x224
+#define DDR_PCTL2_ADDRMAP100x228
+#define DDR_PCTL2_ADDRMAP110x22c
+#define DDR_PCTL2_ODTCFG   0x240
+#define DDR_PCTL2_ODTMAP   0x244
+#define DDR_PCTL2_SCHED0x250
+#define DDR_PCTL2_SCHED1   0x254
+#define DDR_PCTL2_PERFHPR1 0x25c
+#def

[U-Boot] [PATCH 6/7] configs: rk3328: enable TPL for rock64-rk3328_defconfig

[Matwey V. Kornilov]

Signed-off-by: Matwey V. Kornilov 
---
 configs/rock64-rk3328_defconfig | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig
index ef453e72c1..6484845fb6 100644
--- a/configs/rock64-rk3328_defconfig
+++ b/configs/rock64-rk3328_defconfig
@@ -34,15 +34,20 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_TIME=y
 CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64"
 CONFIG_SPL_OF_CONTROL=y
+CONFIG_TPL_OF_CONTROL=y
 CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names 
interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_TPL_OF_PLATDATA=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
+CONFIG_TPL_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_SPL_SYSCON=y
+CONFIG_TPL_SYSCON=y
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
+CONFIG_TPL_CLK=y
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
@@ -65,6 +70,7 @@ CONFIG_REGULATOR_RK8XX=y
 CONFIG_PWM_ROCKCHIP=y
 CONFIG_RAM=y
 CONFIG_SPL_RAM=y
+CONFIG_TPL_RAM=y
 CONFIG_DM_RESET=y
 CONFIG_BAUDRATE=150
 CONFIG_DEBUG_UART_SHIFT=2
@@ -85,4 +91,12 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x330a
 CONFIG_USB_GADGET_DWC2_OTG=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_SPL_TINY_MEMSET=y
+CONFIG_TPL_TINY_MEMSET=y
 CONFIG_ERRNO_STR=y
+CONFIG_TPL_DM=y
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_TPL_BOOTROM_SUPPORT=y
+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
-- 
2.16.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 7/7] doc: rockchip: Adapt Pine64 Rock64 board instructions

[Matwey V. Kornilov]

Now we have our own TPL implementation. Remove obsolete notes.

Signed-off-by: Matwey V. Kornilov 
---
 doc/README.rockchip | 10 ++
 1 file changed, 2 insertions(+), 8 deletions(-)

diff --git a/doc/README.rockchip b/doc/README.rockchip
index 8ccbb87264..7d4dc1b33b 100644
--- a/doc/README.rockchip
+++ b/doc/README.rockchip
@@ -309,17 +309,11 @@ Booting from an SD card on Pine64 Rock64 (RK3328)
 =
 
 For Rock64 rk3328 board the following three parts are required:
-TPL, SPL, and the u-boot image tree blob. While u-boot-spl.bin and
-u-boot.itb are to be compiled as usual, TPL is currently not
-implemented in u-boot, so you need to pick one from rkbin:
-
-  - Get the rkbin
-
-=> git clone https://github.com/rockchip-linux/rkbin.git
+TPL, SPL, and the u-boot image tree blob.
 
   - Create TPL/SPL image
 
-=> tools/mkimage -n rk3328 -T rksd -d 
rkbin/bin/rk33/rk3328_ddr_333MHz_v1.16.bin idbloader.img
+=> tools/mkimage -n rk3328 -T rksd -d tpl/u-boot-tpl.bin idbloader.img
 => cat spl/u-boot-spl.bin >> idbloader.img
 
   - Write TPL/SPL image at 64 sector
-- 
2.16.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 4/7] rockchip: Kconfig: enable TPL support for rk3328

[Matwey V. Kornilov]

From: Kever Yang 

Enable TPL support and some related option in Kconfig.

Signed-off-by: Kever Yang 
[cherry picked from commit 
https://github.com/rockchip-linux/u-boot/commit/430b01462bf3f24aaf7920ae2587a6943c39ab5d
 with minor modifications]
Signed-off-by: Matwey V. Kornilov 
---
 arch/arm/mach-rockchip/Kconfig | 21 +
 1 file changed, 21 insertions(+)

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index e337d06b99..22cbb3a9a4 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -110,9 +110,14 @@ config ROCKCHIP_RK3328
select ARM64
select SUPPORT_SPL
select SPL
+   select SUPPORT_TPL
+   select TPL
+   select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL
+   select TPL_NEEDS_SEPARATE_STACK if TPL
imply ROCKCHIP_COMMON_BOARD
imply SPL_ROCKCHIP_COMMON_BOARD
imply SPL_SERIAL_SUPPORT
+   imply TPL_SERIAL_SUPPORT
imply SPL_SEPARATE_BSS
select ENABLE_ARM_SOC_BOOT0_HOOK
select DEBUG_UART_BOARD_INIT
@@ -124,6 +129,22 @@ config ROCKCHIP_RK3328
  and video codec support. Peripherals include Gigabit Ethernet,
  USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
 
+if ROCKCHIP_RK3328
+
+config TPL_LDSCRIPT
+   default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
+
+config TPL_TEXT_BASE
+default 0xff091000
+
+config TPL_MAX_SIZE
+default 28672
+
+config TPL_STACK
+default 0xff098000
+
+endif
+
 config ROCKCHIP_RK3368
bool "Support Rockchip RK3368"
select ARM64
-- 
2.16.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v2 1/2] watchdog: omap_wdt: Convert watchdog driver to use DT and DM

[sunil . m]

From: Suniel Mahesh 

This patch adds device tree and driver model watchdog support,
converts the legacy omap watchdog driver to driver model for
TI AM335x chipsets. The following compile warning is removed:

= WARNING ==
This board does not use CONFIG_WDT (DM watchdog support).
Please update the board to use CONFIG_WDT before the
v2019.10 release.
Failure to update by the deadline may result in board removal.
See doc/driver-model/MIGRATION.txt for more info.


CONFIG_HW_WATCHDOG is no more a default option for AM33XX devices
after DT/DM conversion, adjusted kconfig accordingly.

DM watchdog support is enabled by default in SPL. The SPL image
doesn't fit into SRAM because of size constraints and build breaks
with an overflow. For this reason DM watchdog support should be
disabled in SPL, driver code should be adjusted accordingly to serve
this purpose.
Built and tested on AM335x device (BeagleboneBlack), compile tested
for all other AM33xx based boards.

Signed-off-by: Suniel Mahesh 
---
Changes for v2:

- changed description a bit to make more sense.
- Travis CI build is performed on am33xx, omap branches apart from others.
  
https://travis-ci.org/sunielmahesh/u-boot/builds/566028250?utm_medium=notification&utm_source=email";
---
 arch/arm/include/asm/ti-common/omap_wdt.h |   5 ++
 configs/am335x_evm_defconfig  |   2 +
 drivers/watchdog/Kconfig  |   9 ++-
 drivers/watchdog/Makefile |   1 +
 drivers/watchdog/omap_wdt.c   | 114 ++
 5 files changed, 130 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/ti-common/omap_wdt.h 
b/arch/arm/include/asm/ti-common/omap_wdt.h
index 7d72e3a..fbc421b 100644
--- a/arch/arm/include/asm/ti-common/omap_wdt.h
+++ b/arch/arm/include/asm/ti-common/omap_wdt.h
@@ -56,4 +56,9 @@ struct wd_timer {
unsigned int wdt_unfr;  /* offset 0x100 */
 };
 
+struct omap3_wdt_priv {
+   struct wd_timer *regs;
+   unsigned int wdt_trgr_pattern;
+};
+
 #endif /* __OMAP_WDT_H__ */
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index ff96f19..fa6b030 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -58,6 +58,8 @@ CONFIG_DM_SPI=y
 CONFIG_OMAP3_SPI=y
 CONFIG_TIMER=y
 CONFIG_OMAP_TIMER=y
+CONFIG_WDT=y
+CONFIG_WDT_OMAP3=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_DM_USB_GADGET=y
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index ccda432..c2a63c3 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -37,7 +37,6 @@ config OMAP_WATCHDOG
bool "TI OMAP watchdog driver"
depends on ARCH_OMAP2PLUS
select HW_WATCHDOG
-   default y if AM33XX
help
  Say Y here to enable the OMAP3+ watchdog driver.
 
@@ -122,6 +121,14 @@ config WDT_MTK
  The watchdog timer is stopped when initialized.
  It performs full SoC reset.
 
+config WDT_OMAP3
+bool "TI OMAP watchdog timer support"
+depends on WDT && ARCH_OMAP2PLUS
+default y if AM33XX
+help
+ This enables OMAP3+ watchdog timer driver, which can be
+ found on some TI chipsets and inline with driver model.
+
 config WDT_ORION
bool "Orion watchdog timer support"
depends on WDT
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 97aa6a8..c40667a 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o
 obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o
 obj-$(CONFIG_WDT_MT7621) += mt7621_wdt.o
 obj-$(CONFIG_WDT_MTK) += mtk_wdt.o
+obj-$(CONFIG_WDT_OMAP3) += omap_wdt.o
 obj-$(CONFIG_WDT_SP805) += sp805_wdt.o
 obj-$(CONFIG_WDT_STM32MP) += stm32mp_wdt.o
 obj-$(CONFIG_WDT_TANGIER) += tangier_wdt.o
diff --git a/drivers/watchdog/omap_wdt.c b/drivers/watchdog/omap_wdt.c
index 343adb0..86f7cf1 100644
--- a/drivers/watchdog/omap_wdt.c
+++ b/drivers/watchdog/omap_wdt.c
@@ -42,10 +42,14 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
 
 /* Hardware timeout in seconds */
 #define WDT_HW_TIMEOUT 60
 
+#if !CONFIG_IS_ENABLED(WDT)
 static unsigned int wdt_trgr_pattern = 0x1234;
 
 void hw_watchdog_reset(void)
@@ -134,3 +138,113 @@ void hw_watchdog_init(void)
while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WSPR)
;
 }
+#else
+static int omap3_wdt_reset(struct udevice *dev)
+{
+   struct omap3_wdt_priv *priv = dev_get_priv(dev);
+
+   priv->wdt_trgr_pattern = 0x1234;
+/*
+ * Somebody just triggered watchdog reset and write to WTGR register
+ * is in progress. It is resetting right now, no need to trigger it
+ * again
+ */
+   if ((readl(&priv->regs->wdtwwps)) & WDT_WWPS_PEND_WTGR)
+   return 0;
+
+   priv->wdt_trgr_pattern = ~(priv->wdt_trgr_pattern);
+   writel(priv->wdt_trgr_pattern, &priv->regs->wdtwtgr);
+/*
+ * Don't wait

[U-Boot] [PATCH v2 2/2] watchdog: omap_wdt: Disable DM watchdog support in SPL

[sunil . m]

From: Suniel Mahesh 

This patch disables DM watchdog support for SPL builds and uses
the legacy omap watchdog driver on TI AM335x chipsets.

The following build error is reported if DM watchdog support was
enabled in SPL:

  CC  spl/drivers/usb/gadget/rndis.o
  LD  spl/drivers/usb/gadget/built-in.o
  LD  spl/drivers/usb/musb-new/built-in.o
  LD  spl/drivers/built-in.o
  LD  spl/u-boot-spl
arm-linux-ld.bfd: u-boot-spl section .u_boot_list will not fit in region .sram
arm-linux-ld.bfd: region .sram overflowed by 440 bytes
make[1]: *** [spl/u-boot-spl] Error 1
make: *** [spl/u-boot-spl] Error 2

Adjusted WATCHDOG_RESET macro accordingly. Earlier it was pointing
to hw_watchdog_reset. Since CONFIG_WATCHDOG replaces CONFIG_HW_WATCHDOG,
now WATCHDOG_RESET macro points to watchdog_reset. This watchdog_reset
is not defined anywhere for am33xx/omap2 and needs to be defined. Fixed
this by simply calling hw_watchdog_reset in watchdog_reset.

Built and tested on AM335x device (BeagleboneBlack), compile tested for
all other AM33xx/omap2 based boards.

Signed-off-by: Suniel Mahesh 
---
Changes for v2:

- changed description a bit to make more sense.
- As suggested by Tom Rini, Travis CI build is performed on
  am33xx, omap branches apart from others, it is a success.
  
https://travis-ci.org/sunielmahesh/u-boot/builds/566028250?utm_medium=notification&utm_source=email";
---
 arch/arm/mach-omap2/boot-common.c | 2 +-
 configs/am335x_evm_defconfig  | 1 +
 drivers/watchdog/omap_wdt.c   | 7 +++
 include/watchdog.h| 2 +-
 4 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/boot-common.c 
b/arch/arm/mach-omap2/boot-common.c
index c8b8ac6..c9549aa 100644
--- a/arch/arm/mach-omap2/boot-common.c
+++ b/arch/arm/mach-omap2/boot-common.c
@@ -208,7 +208,7 @@ void spl_board_init(void)
 #if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW_SUPPORT)
arch_misc_init();
 #endif
-#if defined(CONFIG_HW_WATCHDOG)
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
hw_watchdog_init();
 #endif
 #ifdef CONFIG_AM33XX
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index fa6b030..c0f7ccc 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -60,6 +60,7 @@ CONFIG_TIMER=y
 CONFIG_OMAP_TIMER=y
 CONFIG_WDT=y
 CONFIG_WDT_OMAP3=y
+# CONFIG_SPL_WDT is not set
 CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_DM_USB_GADGET=y
diff --git a/drivers/watchdog/omap_wdt.c b/drivers/watchdog/omap_wdt.c
index 86f7cf1..d5857be 100644
--- a/drivers/watchdog/omap_wdt.c
+++ b/drivers/watchdog/omap_wdt.c
@@ -138,7 +138,14 @@ void hw_watchdog_init(void)
while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WSPR)
;
 }
+
+void watchdog_reset(void)
+{
+   hw_watchdog_reset();
+}
+
 #else
+
 static int omap3_wdt_reset(struct udevice *dev)
 {
struct omap3_wdt_priv *priv = dev_get_priv(dev);
diff --git a/include/watchdog.h b/include/watchdog.h
index 3a357de..41c9aa7 100644
--- a/include/watchdog.h
+++ b/include/watchdog.h
@@ -77,7 +77,7 @@ int init_func_watchdog_reset(void);
  * Prototypes from $(CPU)/cpu.c.
  */
 
-#if defined(CONFIG_HW_WATCHDOG) && !defined(__ASSEMBLY__)
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) && 
!defined(__ASSEMBLY__)
void hw_watchdog_init(void);
 #endif
 
-- 
2.7.4

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH v2 1/2] dm: core: device: switch off power domain after device removal

[Simon Glass]

Hi Anatolij,

On Wed, 31 Jul 2019 at 10:01, Anatolij Gustschin  wrote:
>
> Hi Simon,
>
> On Thu, 18 Jul 2019 09:22:20 -0600
> Simon Glass s...@chromium.org wrote:
> ...
> > > >  drivers/core/device-remove.c | 9 +
> > > >  include/dm/device.h  | 6 ++
> > > >  2 files changed, 15 insertions(+)
> >
> > Unfortunately this causes a test failure (make qcheck). Can you please
> > take a look?
>
> The dm power_domain test worked, but later when
>  dm_test_destroy()
>   -> uclass_destroy()
> removes devices, first 'power-domain' device is removed, then
> the 'power-domain-test' device. When removing the latter, we run
>
>  if (!power_domain_get(dev, &pd))
>power_domain_off(&pd);
>
> and this probes sandbox_power_domain driver for 'power-domain' device
> activating this device again. Then 'power-domain-test' device is removed,
> but 'power-domain' is active. When unbinding it later, we get this error
> in device_unbind():
>
> if (dev->flags & DM_FLAG_ACTIVATED)
> return -EINVAL;

This is because you are not allowed to unbind an active device. You
must deactivate it (device_remove()) first.

>
> Following will fix it:
>
> diff --git a/drivers/core/device-remove.c b/drivers/core/device-remove.c
> index 586fadee0a..fadb05c944 100644
> --- a/drivers/core/device-remove.c
> +++ b/drivers/core/device-remove.c
> @@ -64,7 +64,8 @@ int device_unbind(struct udevice *dev)
> if (!dev)
> return -EINVAL;
>
> -   if (dev->flags & DM_FLAG_ACTIVATED)
> +   if (dev->flags & DM_FLAG_ACTIVATED &&
> +   device_get_uclass_id(dev) != UCLASS_POWER_DOMAIN)
> return -EINVAL;
>
> if (!(dev->flags & DM_FLAG_BOUND))
>
> But I'm not sure if this it the correct approach. What do you think?

That doesn't look right to me. Power supplies should be removed before
being unbound, just like any other device.

Regards,
Simon
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH] board_r: re-order the board_early_init_r()

[Simon Glass]

Hi Kever,

On Wed, 24 Jul 2019 at 04:01, Kever Yang  wrote:
>
> The board_early_init_r() suppose to be called before board_init(),
> then the board callback functions in board_r will be:
> - board_early_init_r()
> - board_init()
> - board_late_init()

board_early_init_r() was introduced for PowerPC as part of creating
the generic board-init code (board_f.c and board_r.c).

I wonder whether any board is actually using both board_init() and
board_early_init_r(). To me they serve the same function.

So I think we should remove board_early_init_r() and change all uses
to board_init() instead. I expect they will mostly be PowerPC.

>
> Signed-off-by: Kever Yang 
> ---
>
>  common/board_r.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/common/board_r.c b/common/board_r.c
> index abc31b17b8..c5e33c4654 100644
> --- a/common/board_r.c
> +++ b/common/board_r.c
> @@ -681,6 +681,9 @@ static init_fnc_t init_sequence_r[] = {
>  #ifdef CONFIG_DM
> initr_dm,
>  #endif
> +#if defined(CONFIG_BOARD_EARLY_INIT_R)
> +   board_early_init_r,
> +#endif
>  #if defined(CONFIG_ARM) || defined(CONFIG_NDS32) || defined(CONFIG_RISCV) || 
> \
> defined(CONFIG_SANDBOX)
> board_init, /* Setup chipselects */
> @@ -712,9 +715,6 @@ static init_fnc_t init_sequence_r[] = {
>  #endif
>  #ifdef CONFIG_ADDR_MAP
> initr_addr_map,
> -#endif
> -#if defined(CONFIG_BOARD_EARLY_INIT_R)
> -   board_early_init_r,
>  #endif
> INIT_FUNC_WATCHDOG_RESET
>  #ifdef CONFIG_POST
> --
> 2.17.1
>

Regards,
Simon
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 1/2] avb: Fix build when CONFIG_OPTEE_TA_AVB is disabled

[Sam Protsenko]

When having only these AVB related configs enabled:

CONFIG_AVB_VERIFY=y
CONFIG_CMD_AVB=y
CONFIG_LIBAVB=y

build fails with next errors:

common/avb_verify.c: In function 'read_persistent_value':
common/avb_verify.c:867:6: warning: implicit declaration of function
'get_open_session'
common/avb_verify.c:870:45: error: 'struct AvbOpsData' has no member
named 'tee'
common/avb_verify.c:894:7: warning: implicit declaration of function
'invoke_func'
common/avb_verify.c: In function 'write_persistent_value':
common/avb_verify.c:931:45: error: 'struct AvbOpsData' has no member
   named 'tee'

Guard read_persistent_value() and write_persistent_value() functions
by checking if CONFIG_OPTEE_TA_AVB is enabled (as those are only used in
that case) to fix the build with mentioned configuration.

Signed-off-by: Sam Protsenko 
---
 common/avb_verify.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/common/avb_verify.c b/common/avb_verify.c
index 32034d927c..36898a610f 100644
--- a/common/avb_verify.c
+++ b/common/avb_verify.c
@@ -851,6 +851,7 @@ static AvbIOResult get_size_of_partition(AvbOps *ops,
return AVB_IO_RESULT_OK;
 }
 
+#ifdef CONFIG_OPTEE_TA_AVB
 static AvbIOResult read_persistent_value(AvbOps *ops,
 const char *name,
 size_t buffer_size,
@@ -968,6 +969,8 @@ free_name:
 
return rc;
 }
+#endif
+
 /**
  * 
  * AVB2.0 AvbOps alloc/initialisation/free
-- 
2.20.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 2/2] cmd: avb: Fix compiler warnings

[Sam Protsenko]

When building U-Boot with AVB enabled, compiler shows next warnings:

cmd/avb.c: In function 'do_avb_read_pvalue':
cmd/avb.c:371:18: warning: format '%ld' expects argument of type
  'long int', but argument 2 has type 'size_t'
  {aka 'unsigned int'} [-Wformat=]
   printf("Read %ld bytes, value = %s\n", bytes_read,
~~^   ~~
%d

cmd/avb.c: In function 'do_avb_write_pvalue':
cmd/avb.c:404:19: warning: format '%ld' expects argument of type
  'long int', but argument 2 has type '__kernel_size_t'
  {aka 'unsigned int'} [-Wformat=]
   printf("Wrote %ld bytes\n", strlen(value) + 1);
 ~~^   ~
 %d

Fix those by using "%zu" specified.

Signed-off-by: Sam Protsenko 
---
 cmd/avb.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/cmd/avb.c b/cmd/avb.c
index c5af4a2e46..3f6fd763a0 100644
--- a/cmd/avb.c
+++ b/cmd/avb.c
@@ -368,7 +368,7 @@ int do_avb_read_pvalue(cmd_tbl_t *cmdtp, int flag, int argc,
 
if (avb_ops->read_persistent_value(avb_ops, name, bytes, buffer,
   &bytes_read) == AVB_IO_RESULT_OK) {
-   printf("Read %ld bytes, value = %s\n", bytes_read,
+   printf("Read %zu bytes, value = %s\n", bytes_read,
   (char *)buffer);
free(buffer);
return CMD_RET_SUCCESS;
@@ -401,7 +401,7 @@ int do_avb_write_pvalue(cmd_tbl_t *cmdtp, int flag, int 
argc,
if (avb_ops->write_persistent_value(avb_ops, name, strlen(value) + 1,
(const uint8_t *)value) ==
AVB_IO_RESULT_OK) {
-   printf("Wrote %ld bytes\n", strlen(value) + 1);
+   printf("Wrote %zu bytes\n", strlen(value) + 1);
return CMD_RET_SUCCESS;
}
 
-- 
2.20.1

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH v2 1/2] dm: core: device: switch off power domain after device removal

[Anatolij Gustschin]

Hi Simon,

On Wed, 31 Jul 2019 10:29:50 -0600
Simon Glass s...@chromium.org wrote:
...
>> But I'm not sure if this it the correct approach. What do you think?  
> 
> That doesn't look right to me. Power supplies should be removed before
> being unbound, just like any other device.

OK, I tried to remove the associated power domain device explicitly
and this seems to work, at least with sandbox power domain driver.
Will rework the patch and resend. Thanks!

--
Anatolij
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [RFC] drivers: dma: ti-edma3: Enable edma3-tpcc

[Tom Rini]

On Sun, Jun 09, 2019 at 08:34:46AM -0500, Adam Ford wrote:

> Enable edma3-tpcc controllers for future use with some
> Davinci devices.
> 
> Signed-off-by: Adam Ford 
> 
> diff --git a/arch/arm/mach-davinci/cpu.c b/arch/arm/mach-davinci/cpu.c
> index f97ad3fc74..e26365cdb1 100644
> --- a/arch/arm/mach-davinci/cpu.c
> +++ b/arch/arm/mach-davinci/cpu.c
> @@ -91,6 +91,15 @@ int set_cpu_clk_info(void)
>   return 0;
>  }
>  
> +void enable_edma3_clocks(void)
> +{
> +
> +}
> +
> +void disable_edma3_clocks(void)
> +{
> +
> +}
>  /*
>   * Initializes on-chip ethernet controllers.
>   * to override, implement board_eth_init()
> diff --git a/drivers/dma/ti-edma3.c b/drivers/dma/ti-edma3.c
> index 7e11b13e45..4619eeae55 100644
> --- a/drivers/dma/ti-edma3.c
> +++ b/drivers/dma/ti-edma3.c
> @@ -565,6 +565,7 @@ static const struct dma_ops ti_edma3_ops = {
>  
>  static const struct udevice_id ti_edma3_ids[] = {
>   { .compatible = "ti,edma3" },
> + { .compatible = "ti,edma3-tpcc" },
>   { }
>  };

I know this is RFC, so my comment is I want to wait until there's actual
code before we do anything more here, thanks!

-- 
Tom


signature.asc
Description: PGP signature
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [BISECTED] [BUG]: MMC initialization hang at Zynq Z-turn board

[Matwey V. Kornilov]

Hello,

I am running Zynq Z-turn board and I face the following issue with MMC
initialization in SPL.
With u-boot master, I see the message similar to the following:

U-Boot SPL 2019.07-00352-gb5f3eb3393 (Jul 31 2019 - 20:03:42 +0300)
mmc boot
Trying to boot from MMC1

Then, the u-boot waits forever. I've tried to add debug prints and
found that execution is stalled somewhere inside mmc_init().
Using bisect I've found that the following broken commit is the following:

commit 3d296365e4e8823c7c0d4b568fa7accfae4bf895 (refs/bisect/bad)
Author: Faiz Abbas 
Date:   Tue Jun 11 00:43:34 2019 +0530

mmc: sdhci: Add support for sdhci-caps-mask

Add Support for masking some bits in the capabilities
register of a host controller.

Also remove the redundant readl() into caps1.

Signed-off-by: Faiz Abbas 
Reviewed-by: Tom Rini 

Until that commit the behavior was the following:

U-Boot SPL 2019.07-00351-g889a4dfc55 (Jul 31 2019 - 20:01:41 +0300)
mmc boot
Trying to boot from MMC1
spl_load_image_fat_os: error reading image system.dtb, err - -2
spl_load_image_fat: error reading image u-boot.img, err - -2
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###

There were no u-boot.img at the SD card while testing, so this error
message is expected here.
5456935a1da3 ("ARM: zynq: Add configuration for Z-turn board") was
applied at the top of every testing commit to allow the board
initialization in SPL.

What could be wrong with that commit and how could I fix the board?

-- 
With best regards,
Matwey V. Kornilov
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH v4] board/BuR/brsmarc1: initial commit

[Tom Rini]

On Wed, Jul 31, 2019 at 06:31:39AM +0200, Hannes Schmelzer wrote:

> This commit adds support for the B&R brsmarc1 SoM.
> 
> The SoM is based on TI's AM335x SoC.
> Mainly vxWorks 6.9.4.x is running on the board,
> doing some PLC stuff on various carrier boards.
> 
> Signed-off-by: Hannes Schmelzer 

Sorry I wasn't clear enough.  This needs to be rebased and updated for
the ENV settings being in Kconfig now.

-- 
Tom


signature.asc
Description: PGP signature
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] (Offlist) Re: U-Boot/EBBR plugfest at ELC-EU?

[Daniel Kiper]

On Tue, Jul 30, 2019 at 03:33:27PM +, Grant Likely wrote:
> >> On 24 Jul 2019, at 14:39, Daniel Kiper  wrote:
> >>> On Mon, Jul 08, 2019 at 01:27:11PM +, Steve McIntyre wrote:
> >>> On Mon, Jul 08, 2019 at 11:18:56AM +0100, Leif Lindholm wrote:
> >>> On Mon, Jul 08, 2019 at 12:13:07PM +0200, Daniel Kiper wrote:
> > I don't know yet - UEFI Asia plugfest date hasn't been decided yet,
> > and is likely to end up around the same time. And actually another
> > unrelated event too.
> >
> > Certainly, Lyon is a quite convenient train journey from here :)
> >
> > But I'm also happy to look into GRUB issues on 32-bit systems remotely
> > if someone could point me at them.
> 
>  I am not planning to be at ELC-E but I can help remotely if it is
>  needed. However, there is another option. There is pretty good chance
>  that I will get a MC slot at LPC. I am looking for people who want to
>  talk. The overall plan is to devote this MC for boot stuff with focus
>  on security. So, this maybe good place to discuss this. However, I am
>  not ARM expert, so, I would like to see Leif and/or Alex or somebody
>  else familiar with ARM stuff there too.
> >>>
> >>> If I can get a ticket, I'm already intending to attend plumbers.
> >>>
> >>> Registered on the waiting list.
> >
> > Folks, our LPC MC was accepted:
> >  
> > https://linuxplumbersconf.org/event/4/page/34-accepted-microconferences#security
> >  
> > https://www.linuxplumbersconf.org/blog/2019/system-boot-and-security-microconference-accepted-into-2019-linux-plumbers-conference/
> >
> > If you want to discuss something there please put a topic proposal on
> > LPC site. CfP closes on 2nd of August. If you need a pass or invite an
> > expert drop me a line.
>
> Thanks Daniel,
>
> It is certainly a worthy discussion topic for LPC. I’ll see if I can
> draft something for the CfP on Friday. Unfortunately, I may not be at

Please do it!

> LPC. I’m not even on the waiting list yet.

I cannot promise anything but if we accept your proposal then there is a
chance that you will get a pass from us.

Daniel
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH] ARM: omap3: overo: Fix MMC init for SPL

[anselm . busse]

From: Anselm Busse 

The SPL for the Overo board does not initialise the MMC. Hence, it cannot load 
the main boot loader from the SD card susequently. This Patch moves the 
initialisation code for the MMC so it gets included in the SPL.

---
 board/overo/common.c | 25 +
 board/overo/overo.c  | 14 --
 2 files changed, 25 insertions(+), 14 deletions(-)

diff --git a/board/overo/common.c b/board/overo/common.c
index fc02d66d53..851f55d43c 100644
--- a/board/overo/common.c
+++ b/board/overo/common.c
@@ -38,6 +38,31 @@ int board_init(void)
return 0;
 }
 
+#if defined(CONFIG_MMC)
+int board_mmc_init(bd_t *bis)
+{
+   return omap_mmc_init(0, 0, 0, -1, -1);
+}
+#endif
+
+#if defined(CONFIG_MMC)
+void board_mmc_power_init(void)
+{
+   twl4030_power_mmc_init(0);
+}
+#endif
+
+#if defined(CONFIG_SPL_OS_BOOT)
+int spl_start_uboot(void)
+{
+   /* break into full u-boot on 'c' */
+   if (serial_tstc() && serial_getc() == 'c')
+   return 1;
+
+   return 0;
+}
+#endif /* CONFIG_SPL_OS_BOOT */
+
 #define MUX_OVERO() \
  /*SDRC*/\
MUX_VAL(CP(SDRC_D0),(IEN  | PTD | DIS | M0)) /*SDRC_D0*/\
diff --git a/board/overo/overo.c b/board/overo/overo.c
index 8fa41f8155..3d57f945f4 100644
--- a/board/overo/overo.c
+++ b/board/overo/overo.c
@@ -376,20 +376,6 @@ int board_eth_init(bd_t *bis)
 }
 #endif
 
-#if defined(CONFIG_MMC)
-int board_mmc_init(bd_t *bis)
-{
-   return omap_mmc_init(0, 0, 0, -1, -1);
-}
-#endif
-
-#if defined(CONFIG_MMC)
-void board_mmc_power_init(void)
-{
-   twl4030_power_mmc_init(0);
-}
-#endif
-
 #if defined(CONFIG_USB_EHCI_HCD)
 static struct omap_usbhs_board_data usbhs_bdata = {
.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
-- 
2.22.0

___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

[U-Boot] [PULL u-boot] Please pull u-boot-amlogic-20190731

[Neil Armstrong]

Hi Tom,

This PR adds support for the Odroid-N2 board and sync the Amlogic G12A DT
with Linux 5.3-rc1, removing the local DT in -u-boot.dtsi files.
It also includes the last minute fix from Heinrich in the gxbb clock driver.

The CI jobs passed at 
https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic/pipelines/376

Thanks,
Neil

The following changes since commit d0d07ba86afc8074d79e436b1ba4478fa0f0c1b5:

  Prepare v2019.10-rc1 (2019-07-29 21:16:16 -0400)

are available in the Git repository at:

  https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic.git 
tags/u-boot-amlogic-20190731

for you to fetch changes up to 0c0cdc86103a1f579cb9f86a3c7c076abb383542:

  clk: meson: remove duplicate logic (2019-07-31 12:11:04 +0200)


- sync Amlogic G12A DT with linux 5.3-rc1
- add support for 4GiB DRAM memory
- add support for Amlogic G12B based Odroid-N2
- small duplicate logic fix for gxbb clock driver


Heinrich Schuchardt (1):
  clk: meson: remove duplicate logic

Neil Armstrong (4):
  ARM: dts: Sync Amlogic G12A with Linux 5.3-rc1
  ARM: dts: add support for Odroid-N2
  ARM: meson-g12a: Handle 4GiB DRAM size
  board: amlogic: add support for Odroid-N2

 arch/arm/dts/Makefile   |3 +-
 arch/arm/dts/meson-g12a-u-boot.dtsi |  216 ---
 arch/arm/dts/meson-g12a-u200-u-boot.dtsi|   63 -
 arch/arm/dts/meson-g12a-u200.dts|  122 +-
 arch/arm/dts/meson-g12a.dtsi| 1825 ++-
 arch/arm/dts/meson-g12b-odroid-n2.dts   |  386 +
 arch/arm/dts/meson-g12b.dtsi|   82 +
 arch/arm/mach-meson/board-g12a.c|   13 +-
 board/amlogic/w400/MAINTAINERS  |6 +
 board/amlogic/w400/Makefile |6 +
 board/amlogic/w400/README.odroid-n2 |  130 ++
 board/amlogic/w400/README.w400  |  130 ++
 board/amlogic/w400/w400.c   |   18 +
 configs/odroid-n2_defconfig |   56 +
 drivers/clk/meson/gxbb.c|5 +-
 include/dt-bindings/clock/axg-aoclkc.h  |7 +-
 include/dt-bindings/clock/axg-audio-clkc.h  |   30 +-
 include/dt-bindings/clock/g12a-clkc.h   |3 +-
 include/dt-bindings/sound/meson-g12a-tohdmitx.h |   13 +
 19 files changed, 2765 insertions(+), 349 deletions(-)
 delete mode 100644 arch/arm/dts/meson-g12a-u-boot.dtsi
 delete mode 100644 arch/arm/dts/meson-g12a-u200-u-boot.dtsi
 create mode 100644 arch/arm/dts/meson-g12b-odroid-n2.dts
 create mode 100644 arch/arm/dts/meson-g12b.dtsi
 create mode 100644 board/amlogic/w400/MAINTAINERS
 create mode 100644 board/amlogic/w400/Makefile
 create mode 100644 board/amlogic/w400/README.odroid-n2
 create mode 100644 board/amlogic/w400/README.w400
 create mode 100644 board/amlogic/w400/w400.c
 create mode 100644 configs/odroid-n2_defconfig
 create mode 100644 include/dt-bindings/sound/meson-g12a-tohdmitx.h
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Re: [U-Boot] [PATCH 31/39] env: Drop _ENTRY

[Simon Glass]

Hi Joe,

On Tue, 30 Jul 2019 at 15:35, Joe Hershberger  wrote:
>
> On Sun, Jul 28, 2019 at 9:28 AM Simon Glass  wrote:
> >
> > This typedef does not need to be defined in the search.h header since it
> > is only used in one file (hashtable.c). Remove it from the header and
> > change it to a struct.
> >
> > Signed-off-by: Simon Glass 
> > ---
> >
> >  include/search.h | 2 +-
> >  lib/hashtable.c  | 7 ---
> >  2 files changed, 5 insertions(+), 4 deletions(-)
> >
> > diff --git a/include/search.h b/include/search.h
> > index efa8bcbef6..c99648f80b 100644
> > --- a/include/search.h
> > +++ b/include/search.h
> > @@ -42,7 +42,7 @@ struct env_entry {
> >
> >  /* Data type for reentrant functions.  */
> >  struct hsearch_data {
> > -   struct _ENTRY *table;
> > +   struct env_entry_node *table;
>
> Don't you need an opaque definition of this?

I don't see why. We can just use struct env_entry_node which is opaque
if the definition is not available.

>
> Also, there is an opaque definition of _ENTRY in this file that needs
> to go away.

Where is that? I can't see it.

>
> > unsigned int size;
> > unsigned int filled;
> >  /*
> > diff --git a/lib/hashtable.c b/lib/hashtable.c
> > index c77b68f4e6..1093d8adaa 100644
> > --- a/lib/hashtable.c
> > +++ b/lib/hashtable.c
> > @@ -59,10 +59,10 @@
> >   * which describes the current status.
> >   */
> >
> > -typedef struct _ENTRY {
> > +struct env_entry_node {
> > int used;
> > struct env_entry entry;
> > -} _ENTRY;
> > +};
> >
> >
> >  static void _hdelete(const char *key, struct hsearch_data *htab,
> > @@ -120,7 +120,8 @@ int hcreate_r(size_t nel, struct hsearch_data *htab)
> > htab->filled = 0;
> >
> > /* allocate memory and zero out */
> > -   htab->table = (_ENTRY *) calloc(htab->size + 1, sizeof(_ENTRY));
> > +   htab->table = (struct env_entry_node *)calloc(htab->size + 1,
> > +   sizeof(struct 
> > env_entry_node));
> > if (htab->table == NULL)
> > return 0;
> >
> > --
> > 2.22.0.709.g102302147b-goog
> >

Regards,
Simon
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot