Re: [U-Boot] [PATCH 4/4] arm: zynq: use i2c cadence DM driver
Hi Michal,
On Fri, Jul 20, 2018 at 6:57 AM Michal Simek wrote:
> On 9.7.2018 07:00, Luis Araneda wrote:
> > [...]
> > --- a/arch/arm/dts/zynq-syzygy-hub.dts
> > +++ b/arch/arm/dts/zynq-syzygy-hub.dts
> > @@ -15,6 +15,7 @@
> > aliases {
> > ethernet0 = &gem0;
> > serial0 = &uart0;
> > + i2c0 = &i2c1;
> > mmc0 = &sdhci0;
> > };
> >
>
> This can be separate patch.
Ok
> > diff --git a/arch/arm/dts/zynq-zybo.dts b/arch/arm/dts/zynq-zybo.dts
> > index 3844822305..b5e0f3d9b3 100644
> > --- a/arch/arm/dts/zynq-zybo.dts
> > +++ b/arch/arm/dts/zynq-zybo.dts
> > @@ -14,6 +14,8 @@
> > ethernet0 = &gem0;
> > serial0 = &uart1;
> > spi0 = &qspi;
> > + i2c0 = &i2c0;
> > + i2c1 = &i2c1;
> > mmc0 = &sdhci0;
> > };
> >
> > @@ -49,6 +51,14 @@
> > };
> > };
> >
> > +&i2c0 {
> > + status = "okay";
> > +};
> > +
> > +&i2c1 {
> > + status = "okay";
> > +};
> > +
>
> IIRC zybo has no connection from PS to i2c and it is done via PL.
> And deal was that only things which are in PS part should be listed in
> DTS file. It means this shouldn't be here.
The PS has I2C peripherals. For the Zybo in particular, there are two
I2Cs, which must be routed through the PL to be connected to the
EEPROM and HDMI port respectively. That means that if the PL is not
programmed, the I2C driver binds and works properly but the SCL and
SDA signals of the I2C peripherals are not connected to anything.
So, I'm not sure if the rule is applicable here, because the I2Cs are
in PS, but to properly use them you have to program the PL.
Besides, adding the aliases and nodes was the only way I could find to
make the driver work (bind) automatically. If I don't add the aliases,
the I2C devices are not assigned a bus (-1), and if I don't add the
nodes, the driver does not bind.
If the I2C nodes don't belong in the .dts file, and I'm using DM
(which will eventually be mandatory), does that means I would have to
bind the driver manually to obtain the current functionality without
DM? I suppose that's possible (don't know how). It sounds like the
functionality provided by device-tree overlays.
> > &qspi {
> > u-boot,dm-pre-reloc;
> > status = "okay";
> > diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
> > index dcbf788918..5b9ee10a90 100644
> > --- a/board/xilinx/zynq/board.c
> > +++ b/board/xilinx/zynq/board.c
> > @@ -8,6 +8,7 @@
> > #include
> > #include
> > #include
> > +#include
> > #include
> > #include
> > #include
> > @@ -76,10 +77,25 @@ int board_late_init(void)
> > int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
> > {
> > #if defined(CONFIG_MAC_ADDR_IN_I2C_EEPROM)
> > - if (eeprom_read(CONFIG_MAC_ADDR_I2C_EEPROM_CHIP_ADDR,
> > - CONFIG_MAC_ADDR_I2C_EEPROM_DATA_ADDR_START,
> > - ethaddr, 6))
> > - printf("I2C EEPROM MAC address read failed\n");
> > + int ret;
> > + struct udevice *bus, *dev;
> > +
> > + ret = uclass_get_device_by_seq(UCLASS_I2C,
> > +CONFIG_MAC_ADDR_I2C_EEPROM_BUS,
> > +&bus);
> > + if (!ret)
> > + ret = i2c_get_chip(bus,
> > +CONFIG_MAC_ADDR_I2C_EEPROM_CHIP_ADDR,
> > +1, &dev);
> > + if (!ret)
> > + ret = i2c_set_chip_offset_len(dev,
> > +
> > CONFIG_MAC_ADDR_I2C_EEPROM_DATA_ADDR_LEN);
> > + if (!ret)
> > + ret = dm_i2c_read(dev,
> > + CONFIG_MAC_ADDR_I2C_EEPROM_DATA_ADDR_START,
> > + ethaddr, 6);
> > + if (ret)
> > + printf("I2C EEPROM MAC address read failed (%i)\n", ret);
> > #endif
>
> In ZynqMP there is also call i2c_set_bus_num which is what you do above.
>
> I don't think that make sense to duplicate this code in board files.
> This should go to core. I think eeprom hasn't been converted to DM and
> that's the thing which should happen first. Then calling sequence should
> be the same in board files.
Ok. I'm assuming that you are referring to the eeprom command? because
I found the i2c_eeprom driver (CONFIG_I2C_EEPROM), which is using DM.
But, I'm not sure if we can use it because it has the same problems of
the I2C nodes above, and this is even worse, as the driver won't bind
unless the PL is programmed first.
> > --- a/configs/syzygy_hub_defconfig
> > +++ b/configs/syzygy_hub_defconfig
> > @@ -18,7 +18,6 @@ CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
> > CONFIG_SPL_STACK_R=y
> > CONFIG_SPL_OS_BOOT=y
> > CONFIG_SYS_PROMPT="Zynq> "
> > -CONFIG_CMD_EEPROM=y
>
> this will caused regression.
Is it because someone could have been using the command?
Thanks,
Luis Araneda.
___
U-Boot ma
Re: [U-Boot] [PATCH 2/2] arm: zynq: add support for the zybo z7 board
Hi Michal, On Fri, Jul 20, 2018 at 3:09 AM Michal Simek wrote: > On 13.7.2018 17:44, Luis Araneda wrote: > > [...] > > +CONFIG_DM_I2C=y > > +CONFIG_SYS_I2C_CADENCE=y > > +CONFIG_MMC_SDHCI=y > > +CONFIG_MMC_SDHCI_ZYNQ=y > > +CONFIG_SPI_FLASH=y > > +CONFIG_SPI_FLASH_BAR=y > > +CONFIG_SPI_FLASH_SPANSION=y > > +CONFIG_PHY_REALTEK=y > > +CONFIG_ZYNQ_GEM=y > > +CONFIG_DEBUG_UART_ZYNQ=y > > +CONFIG_ZYNQ_SERIAL=y > > +CONFIG_ZYNQ_QSPI=y > > +CONFIG_USB=y > > +CONFIG_USB_EHCI_HCD=y > > +CONFIG_USB_ULPI_VIEWPORT=y > > +CONFIG_USB_ULPI=y > > +CONFIG_USB_STORAGE=y > > +CONFIG_USB_GADGET=y > > +CONFIG_USB_GADGET_MANUFACTURER="Xilinx" > > +CONFIG_USB_GADGET_VENDOR_NUM=0x03fd > > +CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 > > +CONFIG_CI_UDC=y > > +CONFIG_USB_GADGET_DOWNLOAD=y > > +CONFIG_USB_FUNCTION_THOR=y > > +CONFIG_DISPLAY=y > > Not sure if make sense to enable this CONFIG_DISPLAY but the rest is fine. Probably not, I selected it because the Zybo had it selected. I'll remove it for v2. Additionally, for v2 I'll will be using the zynq_i2c driver (not DM) because the I2C peripherals on this board are connected like the Zybo. For more details, refer to the reply of "[PATCH 4/4] arm: zynq: use i2c cadence DM driver" Thanks, Luis Araneda. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] Support of kernels > 16 MiB on Raspberry Pi
Hi! I just wanted to let you know that I recently upgraded to U-Boot 2018.07 from Debian Experimental [0] and everything works now! Thanks to everybody involved [1]! Best regards Alexander Kurtz [0] https://tracker.debian.org/pkg/u-boot [1] https://github.com/u-boot/u-boot/commits/v2018.07/include/configs/rpi.h signature.asc Description: This is a digitally signed message part ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 00/13] Allwinner H6 support (w/ SPL)
This patchset trys to add support for Allwinner H6 SoC to U-Boot. Allwinner H6 is a quite new Allwinner SoC, with several parts changed a lot (memory map, DRAM controller, CCU, so on). The position which SPL will be loaded (SRAM A1) also changed to 0x2. The Pine H64 board support comes with this patchset, as this is the first H6 board that I can get (being early bird). Icenowy Zheng (13): sunxi: change SUNXI_HIGH_SRAM option to SUNXI_SRAM_ADDRESS sunxi: add basic memory map definitions of H6 SoC sunxi: change RMR64's RVBAR address for H6 sunxi: change ATF position for H6 sunxi: add config for SPL at 0x2 on H6 sunxi: change GIC address on H6 sunxi: add clock code for H6 sunxi: use sun6i-style watchdog for H6 sunxi: add UART0 setup for H6 sunxi: add MMC support for H6 sunxi: add DRAM support to H6 sunxi: add support for Allwinner H6 SoC sunxi: add support for Pine H64 board arch/arm/dts/Makefile | 2 + arch/arm/dts/sun50i-h6-pine-h64.dts | 185 + arch/arm/dts/sun50i-h6.dtsi | 288 +++ arch/arm/include/asm/arch-sunxi/boot0.h | 4 + arch/arm/include/asm/arch-sunxi/clock.h | 2 + .../include/asm/arch-sunxi/clock_sun50i_h6.h | 320 arch/arm/include/asm/arch-sunxi/cpu.h | 2 + .../include/asm/arch-sunxi/cpu_sun50i_h6.h| 73 ++ arch/arm/include/asm/arch-sunxi/dram.h| 2 + .../include/asm/arch-sunxi/dram_sun50i_h6.h | 297 +++ arch/arm/include/asm/arch-sunxi/gpio.h| 1 + arch/arm/include/asm/arch-sunxi/mmc.h | 2 +- arch/arm/include/asm/arch-sunxi/spl.h | 6 +- arch/arm/include/asm/arch-sunxi/timer.h | 2 +- arch/arm/mach-sunxi/Kconfig | 37 +- arch/arm/mach-sunxi/Makefile | 2 + arch/arm/mach-sunxi/board.c | 6 +- arch/arm/mach-sunxi/clock_sun50i_h6.c | 94 +++ arch/arm/mach-sunxi/cpu_info.c| 2 + arch/arm/mach-sunxi/dram_sun50i_h6.c | 754 ++ arch/arm/mach-sunxi/rmr_switch.S | 6 + board/sunxi/MAINTAINERS | 5 + board/sunxi/board.c | 7 + board/sunxi/mksunxi_fit_atf.sh| 10 +- common/spl/Kconfig| 2 +- configs/pine_h64_defconfig| 15 + drivers/mmc/sunxi_mmc.c | 13 +- include/configs/sun50i.h | 5 + include/configs/sunxi-common.h| 24 +- include/dt-bindings/clock/sun50i-h6-ccu.h | 125 +++ include/dt-bindings/clock/sun50i-h6-r-ccu.h | 24 + include/dt-bindings/reset/sun50i-h6-ccu.h | 73 ++ include/dt-bindings/reset/sun50i-h6-r-ccu.h | 17 + 33 files changed, 2377 insertions(+), 30 deletions(-) create mode 100644 arch/arm/dts/sun50i-h6-pine-h64.dts create mode 100644 arch/arm/dts/sun50i-h6.dtsi create mode 100644 arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h create mode 100644 arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h create mode 100644 arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h create mode 100644 arch/arm/mach-sunxi/clock_sun50i_h6.c create mode 100644 arch/arm/mach-sunxi/dram_sun50i_h6.c create mode 100644 configs/pine_h64_defconfig create mode 100644 include/dt-bindings/clock/sun50i-h6-ccu.h create mode 100644 include/dt-bindings/clock/sun50i-h6-r-ccu.h create mode 100644 include/dt-bindings/reset/sun50i-h6-ccu.h create mode 100644 include/dt-bindings/reset/sun50i-h6-r-ccu.h -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 02/13] sunxi: add basic memory map definitions of H6 SoC
The Allwinner H6 SoC come with a totally new memory map. Add basical definition of the new memory map into a header file, and let the cpu.h header include it in the situation of H6. Signed-off-by: Icenowy Zheng Reviewed-by: Andre Przywara --- Changes in v2: - Change SRAM A1 address to CONFIG_SUNXI_SRAM_ADDRESS. - Added Andre's Reviewed-by tag. arch/arm/include/asm/arch-sunxi/cpu.h | 2 + .../include/asm/arch-sunxi/cpu_sun50i_h6.h| 73 +++ 2 files changed, 75 insertions(+) create mode 100644 arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h index 0534ccc8da..4c399b0a15 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu.h +++ b/arch/arm/include/asm/arch-sunxi/cpu.h @@ -8,6 +8,8 @@ #if defined(CONFIG_MACH_SUN9I) #include +#elif defined(CONFIG_MACH_SUN50I_H6) +#include #else #include #endif diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h new file mode 100644 index 00..f568def8b4 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2017 Icenowy Zheng + * + * SPDX-License-Identifier:GPL-2.0+ + */ + +#ifndef _SUNXI_CPU_SUN50I_H6_H +#define _SUNXI_CPU_SUN50I_H6_H + +#define SUNXI_SRAM_A1_BASE CONFIG_SUNXI_SRAM_ADDRESS +#define SUNXI_SRAM_C_BASE 0x00028000 +#define SUNXI_SRAM_A2_BASE 0x0010 + +#define SUNXI_DE3_BASE 0x0100 +#define SUNXI_SS_BASE 0x01904000 +#define SUNXI_EMCE_BASE0x01905000 + +#define SUNXI_SRAMC_BASE 0x0300 +#define SUNXI_CCM_BASE 0x03001000 +#define SUNXI_DMA_BASE 0x03002000 +/* SID address space starts at 0x03006000, but e-fuse is at offset 0x200 */ +#define SUNXI_SIDC_BASE0x03006000 +#define SNUXI_SID_BASE 0x03006200 +#define SUNXI_TIMER_BASE 0x03009000 +#define SUNXI_PIO_BASE 0x0300B000 +#define SUNXI_PSI_BASE 0x0300C000 + +#define SUNXI_GIC400_BASE 0x0302 +#define SUNXI_IOMMU_BASE 0x030F + +#define SUNXI_DRAM_COM_BASE0x04002000 +#define SUNXI_DRAM_CTL0_BASE 0x04003000 +#define SUNXI_DRAM_PHY0_BASE 0x04005000 +#define SUNXI_NFC_BASE 0x04011000 +#define SUNXI_MMC0_BASE0x0402 +#define SUNXI_MMC1_BASE0x04021000 +#define SUNXI_MMC2_BASE0x04022000 + +#define SUNXI_UART0_BASE 0x0500 +#define SUNXI_UART1_BASE 0x05000400 +#define SUNXI_UART2_BASE 0x05000800 +#define SUNXI_UART3_BASE 0x05000C00 +#define SUNXI_TWI0_BASE0x05002000 +#define SUNXI_TWI1_BASE0x05002400 +#define SUNXI_TWI2_BASE0x05002800 +#define SUNXI_TWI3_BASE0x05002C00 +#define SUNXI_SPI0_BASE0x0501 +#define SUNXI_SPI1_BASE0x05011000 +#define SUNXI_GMAC_BASE0x0502 +#define SUNXI_USB0_BASE0x0510 +#define SUNXI_XHCI_BASE0x0520 +#define SUNXI_USB3_BASE0x05311000 +#define SUNXI_PCIE_BASE0x0540 + +#define SUNXI_HDMI_BASE0x0600 +#define SUNXI_TCON_TOP_BASE0x0651 +#define SUNXI_TCON_LCD0_BASE 0x06511000 +#define SUNXI_TCON_TV0_BASE0x06515000 + +#define SUNXI_RTC_BASE 0x0700 +#define SUNXI_R_CPUCFG_BASE0x07000400 +#define SUNXI_PRCM_BASE0x0701 +#define SUNXI_R_PIO_BASE 0x07022000 +#define SUNXI_R_UART_BASE 0x0708 +#define SUNXI_R_TWI_BASE 0x07081400 + +#ifndef __ASSEMBLY__ +void sunxi_board_init(void); +void sunxi_reset(void); +int sunxi_get_sid(unsigned int *sid); +#endif + +#endif /* _SUNXI_CPU_SUN9I_H */ -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 01/13] sunxi: change SUNXI_HIGH_SRAM option to SUNXI_SRAM_ADDRESS
The new Allwinner H6 SoC has its SRAM A1 at neither 0x0 nor 0x1, but it's at 0x2. Thus the SUNXI_HIGH_SRAM option needs to be refactored to support this new configuration. Change it to SUNXI_SRAM_ADDRESS, which holds the real address of SRAM A1 in the memory map. Signed-off-by: Icenowy Zheng Reviewed-by: Andre Przywara Acked-by: Maxime Ripard --- Changes in v2: - Added Maxime's Acked-by and Andre's Reviewed-by tags. arch/arm/include/asm/arch-sunxi/spl.h | 6 +- arch/arm/mach-sunxi/Kconfig | 14 +- include/configs/sunxi-common.h| 19 +++ 3 files changed, 17 insertions(+), 22 deletions(-) diff --git a/arch/arm/include/asm/arch-sunxi/spl.h b/arch/arm/include/asm/arch-sunxi/spl.h index 4277d836e5..55f2deb18d 100644 --- a/arch/arm/include/asm/arch-sunxi/spl.h +++ b/arch/arm/include/asm/arch-sunxi/spl.h @@ -11,11 +11,7 @@ #define SPL_SIGNATURE "SPL" /* marks "sunxi" SPL header */ #define SPL_HEADER_VERSION 2 -#ifdef CONFIG_SUNXI_HIGH_SRAM -#define SPL_ADDR 0x1 -#else -#define SPL_ADDR 0x0 -#endif +#define SPL_ADDR CONFIG_SUNXI_SRAM_ADDRESS /* The low 8-bits of the 'boot_media' field in the SPL header */ #define SUNXI_BOOTED_FROM_MMC0 0 diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 678e33dd40..ccf4b35734 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -73,16 +73,15 @@ config SUN8I_RSB with various RSB based devices, such as AXP223, AXP8XX PMICs, and AC100/AC200 ICs. -config SUNXI_HIGH_SRAM - bool - default n +config SUNXI_SRAM_ADDRESS + hex + default 0x1 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5 + default 0x0 ---help--- Older Allwinner SoCs have their mask boot ROM mapped just below 4GB, with the first SRAM region being located at address 0. Some newer SoCs map the boot ROM at address 0 instead and move the - SRAM to 64KB, just behind the mask ROM. - Chips using the latter setup are supposed to select this option to - adjust the addresses accordingly. + SRAM to a different address. config SUNXI_A64_TIMER_ERRATUM bool @@ -257,7 +256,6 @@ config MACH_SUN9I select CPU_V7A select DRAM_SUN9I select SUN6I_PRCM - select SUNXI_HIGH_SRAM select SUNXI_GEN_SUN6I select SUN8I_RSB select SUPPORT_SPL @@ -269,7 +267,6 @@ config MACH_SUN50I select PHY_SUN4I_USB select SUNXI_DE2 select SUNXI_GEN_SUN6I - select SUNXI_HIGH_SRAM select SUPPORT_SPL select SUNXI_DRAM_DW select SUNXI_DRAM_DW_32BIT @@ -281,7 +278,6 @@ config MACH_SUN50I_H5 bool "sun50i (Allwinner H5)" select ARM64 select MACH_SUNXI_H3_H5 - select SUNXI_HIGH_SRAM select FIT select SPL_LOAD_FIT diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 21371f4919..1b5daa8928 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -82,20 +82,19 @@ #define CONFIG_SPL_BSS_MAX_SIZE0x0008 /* 512 KiB */ -#ifdef CONFIG_SUNXI_HIGH_SRAM /* * The A80's A1 sram starts at 0x0001 rather then at 0x and is * slightly bigger. Note that it is possible to map the first 32 KiB of the * A1 at 0x like with older SoCs by writing 0x16aa0001 to the * undocumented 0x008000e0 SYS_CTRL register. Where the 16aa is a key and * the 1 actually activates the mapping of the first 32 KiB to 0x. + * A64 and H5 also has SRAM A1 at 0x0001, but no magic remap register + * is known yet. + * H6 has SRAM A1 at 0x0002. */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x1 -#define CONFIG_SYS_INIT_RAM_SIZE 0x08000 /* FIXME: 40 KiB ? */ -#else -#define CONFIG_SYS_INIT_RAM_ADDR 0x0 -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */ -#endif +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SUNXI_SRAM_ADDRESS +/* FIXME: this may be larger on some SoCs */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */ #define CONFIG_SYS_INIT_SP_OFFSET \ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) @@ -187,7 +186,11 @@ #define CONFIG_SPL_BOARD_LOAD_IMAGE #endif -#ifdef CONFIG_SUNXI_HIGH_SRAM +/* + * We cannot use expressions here, because expressions won't be evaluated in + * autoconf.mk. + */ +#if CONFIG_SUNXI_SRAM_ADDRESS == 0x1 #define CONFIG_SPL_TEXT_BASE 0x10060 /* sram start+header */ #define CONFIG_SPL_MAX_SIZE0x7fa0 /* 32 KiB */ #ifdef CONFIG_ARM64 -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 04/13] sunxi: change ATF position for H6
H6 has different SRAM A2 address, so the ATF load address is also different. Add judgment code to sunxi 64-bit FIT generation script. It will judge the SoC by the device tree's name. Signed-off-by: Icenowy Zheng --- Changes in v2: - Use CONFIG_MACH_SUN50I_H6 rather than DT prefix to judge H6. board/sunxi/mksunxi_fit_atf.sh | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/board/sunxi/mksunxi_fit_atf.sh b/board/sunxi/mksunxi_fit_atf.sh index 36abe9efed..88ad719747 100755 --- a/board/sunxi/mksunxi_fit_atf.sh +++ b/board/sunxi/mksunxi_fit_atf.sh @@ -13,6 +13,12 @@ if [ ! -f $BL31 ]; then BL31=/dev/null fi +if grep -q "^CONFIG_MACH_SUN50I_H6=y" .config; then + BL31_ADDR=0x104000 +else + BL31_ADDR=0x44000 +fi + cat << __HEADER_EOF /dts-v1/; @@ -35,8 +41,8 @@ cat << __HEADER_EOF type = "firmware"; arch = "arm64"; compression = "none"; - load = <0x44000>; - entry = <0x44000>; + load = <$BL31_ADDR>; + entry = <$BL31_ADDR>; }; __HEADER_EOF -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 03/13] sunxi: change RMR64's RVBAR address for H6
Allwinner H6 has a different RVBAR address with A64/H5. Add conditional RVBAR configuration into the code which does RMR switch. Signed-off-by: Icenowy Zheng Reviewed-by: Andre Przywara --- Changes in v2: - Added Andre's Reviewed-by tag. arch/arm/include/asm/arch-sunxi/boot0.h | 4 arch/arm/mach-sunxi/rmr_switch.S| 6 ++ 2 files changed, 10 insertions(+) diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h b/arch/arm/include/asm/arch-sunxi/boot0.h index c826fec415..54c144afd8 100644 --- a/arch/arm/include/asm/arch-sunxi/boot0.h +++ b/arch/arm/include/asm/arch-sunxi/boot0.h @@ -26,7 +26,11 @@ .word 0xf57ff06f // isb sy .word 0xe320f003 // wfi .word 0xeafd // b @wfi +#ifndef CONFIG_MACH_SUN50I_H6 .word 0x017000a0 // writeable RVBAR mapping address +#else + .word 0x09010040 // writeable RVBAR mapping address +#endif #ifdef CONFIG_SPL_BUILD .word CONFIG_SPL_TEXT_BASE #else diff --git a/arch/arm/mach-sunxi/rmr_switch.S b/arch/arm/mach-sunxi/rmr_switch.S index cefa93001b..fafd306f95 100644 --- a/arch/arm/mach-sunxi/rmr_switch.S +++ b/arch/arm/mach-sunxi/rmr_switch.S @@ -26,9 +26,15 @@ @ reference and to be able to regenerate a (probably fixed) version of this @ code found in encoded form in boot0.h. +#include + .text +#ifndef CONFIG_MACH_SUN50I_H6 ldr r1, =0x017000a0 @ MMIO mapped RVBAR[0] register +#else + ldr r1, =0x09010040 @ MMIO mapped RVBAR[0] register +#endif ldr r0, =0x57aA7add @ start address, to be replaced str r0, [r1] dsb sy -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 07/13] sunxi: add clock code for H6
The new Allwinner H6 SoC has a brand new CCU layout.
Add clock code for it.
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Move the /4 divider in clk_get_pll6() to prevent possible overflow.
arch/arm/include/asm/arch-sunxi/clock.h | 2 +
.../include/asm/arch-sunxi/clock_sun50i_h6.h | 320 ++
arch/arm/mach-sunxi/Makefile | 1 +
arch/arm/mach-sunxi/clock_sun50i_h6.c | 94 +
4 files changed, 417 insertions(+)
create mode 100644 arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
create mode 100644 arch/arm/mach-sunxi/clock_sun50i_h6.c
diff --git a/arch/arm/include/asm/arch-sunxi/clock.h
b/arch/arm/include/asm/arch-sunxi/clock.h
index 46c3eed377..5994130e6b 100644
--- a/arch/arm/include/asm/arch-sunxi/clock.h
+++ b/arch/arm/include/asm/arch-sunxi/clock.h
@@ -16,6 +16,8 @@
/* clock control module regs definition */
#if defined(CONFIG_MACH_SUN8I_A83T)
#include
+#elif defined(CONFIG_MACH_SUN50I_H6)
+#include
#elif defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \
defined(CONFIG_MACH_SUN50I)
#include
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
new file mode 100644
index 00..e36937059b
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
@@ -0,0 +1,320 @@
+/*
+ * Allwinner H6 clock register definitions
+ *
+ * (C) Copyright 2017 Icenowy Zheng
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _SUNXI_CLOCK_SUN50I_H6_H
+#define _SUNXI_CLOCK_SUN50I_H6_H
+
+struct sunxi_ccm_reg {
+ u32 pll1_cfg; /* 0x000 pll1 (cpux) control */
+ u8 reserved_0x004[12];
+ u32 pll5_cfg; /* 0x010 pll5 (ddr) control */
+ u8 reserved_0x014[12];
+ u32 pll6_cfg; /* 0x020 pll6 (periph0) control */
+ u8 reserved_0x020[4];
+ u32 pll_periph1_cfg;/* 0x028 pll periph1 control */
+ u8 reserved_0x028[4];
+ u32 pll7_cfg; /* 0x030 pll7 (gpu) control */
+ u8 reserved_0x034[12];
+ u32 pll3_cfg; /* 0x040 pll3 (video0) control */
+ u8 reserved_0x044[4];
+ u32 pll_video1_cfg; /* 0x048 pll video1 control */
+ u8 reserved_0x04c[12];
+ u32 pll4_cfg; /* 0x058 pll4 (ve) control */
+ u8 reserved_0x05c[4];
+ u32 pll10_cfg; /* 0x060 pll10 (de) control */
+ u8 reserved_0x064[12];
+ u32 pll9_cfg; /* 0x070 pll9 (hsic) control */
+ u8 reserved_0x074[4];
+ u32 pll2_cfg; /* 0x078 pll2 (audio) control */
+ u8 reserved_0x07c[148];
+ u32 pll5_pat; /* 0x110 pll5 (ddr) pattern */
+ u8 reserved_0x114[20];
+ u32 pll_periph1_pat0; /* 0x128 pll periph1 pattern0 */
+ u32 pll_periph1_pat1; /* 0x12c pll periph1 pattern1 */
+ u32 pll7_pat0; /* 0x130 pll7 (gpu) pattern0 */
+ u32 pll7_pat1; /* 0x134 pll7 (gpu) pattern1 */
+ u8 reserved_0x138[8];
+ u32 pll3_pat0; /* 0x140 pll3 (video0) pattern0 */
+ u32 pll3_pat1; /* 0x144 pll3 (video0) pattern1 */
+ u32 pll_video1_pat0;/* 0x148 pll video1 pattern0 */
+ u32 pll_video1_pat1;/* 0x14c pll video1 pattern1 */
+ u8 reserved_0x150[8];
+ u32 pll4_pat0; /* 0x158 pll4 (ve) pattern0 */
+ u32 pll4_pat1; /* 0x15c pll4 (ve) pattern1 */
+ u32 pll10_pat0; /* 0x160 pll10 (de) pattern0 */
+ u32 pll10_pat1; /* 0x164 pll10 (de) pattern1 */
+ u8 reserved_0x168[8];
+ u32 pll9_pat0; /* 0x170 pll9 (hsic) pattern0 */
+ u32 pll9_pat1; /* 0x174 pll9 (hsic) pattern1 */
+ u32 pll2_pat0; /* 0x178 pll2 (audio) pattern0 */
+ u32 pll2_pat1; /* 0x17c pll2 (audio) pattern1 */
+ u8 reserved_0x180[384];
+ u32 pll1_bias; /* 0x300 pll1 (cpux) bias */
+ u8 reserved_0x304[12];
+ u32 pll5_bias; /* 0x310 pll5 (ddr) bias */
+ u8 reserved_0x314[12];
+ u32 pll6_bias; /* 0x320 pll6 (periph0) bias */
+ u8 reserved_0x324[4];
+ u32 pll_periph1_bias; /* 0x328 pll periph1 bias */
+ u8 reserved_0x32c[4];
+ u32 pll7_bias; /* 0x330 pll7 (gpu) bias */
+ u8 reserved_0x334[12];
+ u32 pll3_bias; /* 0x340 pll3 (video0) bias */
+ u8 reserved_0x344[4];
+ u32 pll_video1_bias;/* 0x348 pll video1 bias */
+ u8 reserved_0x34c[12];
+ u32 pll4_bias; /* 0x358 pll4 (ve) bias */
+ u8 reserved_0x35c[4];
+ u32 pll10_bias; /* 0x360 pll10 (de) bias */
+ u8 reserved_0x364[12];
+ u32 pll9_bias; /* 0x370 pll9 (hsic) bias */
+ u8 reserved_0x374[4];
+ u32 pll2_bias; /* 0x378 pll2 (audio) bias */
+ u8 reserved_0x37c[132];
+ u32 pll1_tun; /* 0x400 pll1 (cpux) tunning */
+ u8 reserved_0x404[252];
+ u3
[U-Boot] [PATCH v2 05/13] sunxi: add config for SPL at 0x20000 on H6
On the new Allwinner H6 SoC, the SRAM A2 address (SPL load address) is at 0x2, which is different with any old Allwinner SoCs. Add SPL position and size configuration for this. Signed-off-by: Icenowy Zheng Reviewed-by: Andre Przywara --- Changes in v2: - Added Andre's Reviewed-by tag. include/configs/sunxi-common.h | 5 + 1 file changed, 5 insertions(+) diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 1b5daa8928..4db770d69d 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -199,6 +199,11 @@ #else #define LOW_LEVEL_SRAM_STACK 0x00018000 #endif /* !CONFIG_ARM64 */ +#elif CONFIG_SUNXI_SRAM_ADDRESS == 0x2 +#define CONFIG_SPL_TEXT_BASE 0x20060 /* sram start+header */ +#define CONFIG_SPL_MAX_SIZE0x7fa0 /* 32 KiB */ +/* end of SRAM A2 on H6 for now */ +#define LOW_LEVEL_SRAM_STACK 0x00118000 #else #define CONFIG_SPL_TEXT_BASE 0x60/* sram start+header */ #define CONFIG_SPL_MAX_SIZE0x5fa0 /* 24KB on sun4i/sun7i */ -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 06/13] sunxi: change GIC address on H6
As the Allwinner H6 chip has a new memory map, its GIC MMIO address is thus different. Change the address on H6. Signed-off-by: Icenowy Zheng Reviewed-by: Andre Przywara --- Changes in v2: - Added Andre's Reviewed-by tag. include/configs/sun50i.h | 5 + 1 file changed, 5 insertions(+) diff --git a/include/configs/sun50i.h b/include/configs/sun50i.h index 5ce2cde388..e029218cf8 100644 --- a/include/configs/sun50i.h +++ b/include/configs/sun50i.h @@ -17,8 +17,13 @@ #define CONFIG_SUNXI_USB_PHYS 1 +#ifndef CONFIG_MACH_SUN50I_H6 #define GICD_BASE 0x1c81000 #define GICC_BASE 0x1c82000 +#else +#define GICD_BASE 0x3021000 +#define GICC_BASE 0x3022000 +#endif /* * Include common sunxi configuration where most the settings are -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 08/13] sunxi: use sun6i-style watchdog for H6
The H6 SoC has a sun6i-style watchdog in its timer part.
Enable the usage of it.
Signed-off-by: Icenowy Zheng
---
arch/arm/include/asm/arch-sunxi/timer.h | 2 +-
arch/arm/mach-sunxi/board.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/timer.h
b/arch/arm/include/asm/arch-sunxi/timer.h
index cb02dd8bf8..6f138d04b8 100644
--- a/arch/arm/include/asm/arch-sunxi/timer.h
+++ b/arch/arm/include/asm/arch-sunxi/timer.h
@@ -76,7 +76,7 @@ struct sunxi_timer_reg {
struct sunxi_tgp tgp[4];
u8 res5[8];
u32 cpu_cfg;
-#elif defined(CONFIG_SUNXI_GEN_SUN6I)
+#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6)
u8 res3[16];
struct sunxi_wdog wdog[5]; /* We have 5 watchdogs */
#endif
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 58fef05bd7..40a6436ca5 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -282,7 +282,7 @@ void reset_cpu(ulong addr)
/* sun5i sometimes gets stuck without this */
writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
}
-#elif defined(CONFIG_SUNXI_GEN_SUN6I)
+#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6)
static const struct sunxi_wdog *wdog =
((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
--
2.17.1
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[U-Boot] [PATCH v2 10/13] sunxi: add MMC support for H6
The Allwinner H6 SoC has 3 MMC controllers like the ones in A64, with
the MMC2 come with the capability to do crypto by EMCE.
Add MMC support for H6. EMCE support is not added yet.
Signed-off-by: Icenowy Zheng
---
arch/arm/include/asm/arch-sunxi/mmc.h | 2 +-
board/sunxi/board.c | 7 +++
drivers/mmc/sunxi_mmc.c | 13 -
3 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h
b/arch/arm/include/asm/arch-sunxi/mmc.h
index 1574b8e8fe..d98c53faaa 100644
--- a/arch/arm/include/asm/arch-sunxi/mmc.h
+++ b/arch/arm/include/asm/arch-sunxi/mmc.h
@@ -45,7 +45,7 @@ struct sunxi_mmc {
u32 chda; /* 0x90 */
u32 cbda; /* 0x94 */
u32 res2[26];
-#ifdef CONFIG_SUNXI_GEN_SUN6I
+#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6)
u32 res3[64];
#endif
u32 fifo; /* 0x100 / 0x200 FIFO access address */
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 5ed1b8bae1..857d5ff010 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -443,6 +443,13 @@ static void mmc_pinmux_setup(int sdc)
sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
sunxi_gpio_set_drv(pin, 2);
}
+#elif defined(CONFIG_MACH_SUN50I_H6)
+ /* SDC2: PC4-PC14 */
+ for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) {
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
#elif defined(CONFIG_MACH_SUN9I)
/* SDC2: PC6-PC16 */
for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 7fa1ae8b16..39f15eb423 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -70,10 +70,12 @@ static int mmc_resource_init(int sdc_no)
priv->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
priv->mclkreg = &ccm->sd2_clk_cfg;
break;
+#ifdef SUNXI_MMC3_BASE
case 3:
priv->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
priv->mclkreg = &ccm->sd3_clk_cfg;
break;
+#endif
default:
printf("Wrong mmc number %d\n", sdc_no);
return -1;
@@ -116,6 +118,9 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv,
unsigned int hz)
#ifdef CONFIG_MACH_SUN9I
pll = CCM_MMC_CTRL_PLL_PERIPH0;
pll_hz = clock_get_pll4_periph0();
+#elif defined(CONFIG_MACH_SUN50I_H6)
+ pll = CCM_MMC_CTRL_PLL6X2;
+ pll_hz = clock_get_pll6() * 2;
#else
pll = CCM_MMC_CTRL_PLL6;
pll_hz = clock_get_pll6();
@@ -494,7 +499,7 @@ struct mmc *sunxi_mmc_init(int sdc_no)
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
cfg->host_caps = MMC_MODE_4BIT;
-#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I)
+#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I) ||
defined(CONFIG_MACH_SUN50I_H6)
if (sdc_no == 2)
cfg->host_caps = MMC_MODE_8BIT;
#endif
@@ -509,6 +514,7 @@ struct mmc *sunxi_mmc_init(int sdc_no)
/* config ahb clock */
debug("init mmc %d clock and io\n", sdc_no);
+#if !defined(CONFIG_MACH_SUN50I_H6)
setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
#ifdef CONFIG_SUNXI_GEN_SUN6I
@@ -519,6 +525,11 @@ struct mmc *sunxi_mmc_init(int sdc_no)
/* sun9i has a mmc-common module, also set the gate and reset there */
writel(SUNXI_MMC_COMMON_CLK_GATE | SUNXI_MMC_COMMON_RESET,
SUNXI_MMC_COMMON_BASE + 4 * sdc_no);
+#endif
+#else /* CONFIG_MACH_SUN50I_H6 */
+ setbits_le32(&ccm->sd_gate_reset, 1 << sdc_no);
+ /* unassert reset */
+ setbits_le32(&ccm->sd_gate_reset, 1 << (RESET_SHIFT + sdc_no));
#endif
ret = mmc_set_mod_clk(priv, 2400);
if (ret)
--
2.17.1
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[U-Boot] [PATCH v2 09/13] sunxi: add UART0 setup for H6
The UART0 on H6 is available at PH bank (and PF bank, but the PF one is
muxed with SD card).
Add pinmux configuration.
Signed-off-by: Icenowy Zheng
Reviewed-by: Andre Przywara
---
Changes in v2:
- Added Andre's Reviewed-by tag.
arch/arm/include/asm/arch-sunxi/gpio.h | 1 +
arch/arm/mach-sunxi/board.c| 4
2 files changed, 5 insertions(+)
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h
b/arch/arm/include/asm/arch-sunxi/gpio.h
index e4fe54d8b8..6a5eafc3d3 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -198,6 +198,7 @@ enum sunxi_gpio_number {
#define SUN6I_GPH_TWI2 2
#define SUN6I_GPH_UART02
#define SUN9I_GPH_UART02
+#define SUN50I_H6_GPH_UART02
#define SUNXI_GPI_SDC3 2
#define SUN7I_GPI_TWI3 3
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 40a6436ca5..d22a84ea6b 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -107,6 +107,10 @@ static int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0);
sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H6)
+ sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H6_GPH_UART0);
+ sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H6_GPH_UART0);
+ sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
--
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[U-Boot] [PATCH v2 13/13] sunxi: add support for Pine H64 board
Pine H64 is a SBC with Allwinner H6 SoC produced by Pine64. It features
1GiB/2GiB/4GiB(3GiB usable) DRAM, two USB 2.0 ports, one USB 3.0 port
and a mPCIE slot.
Add support for it.
The device tree is from Linux next-20180720.
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Sync device tree to next-20180720.
arch/arm/dts/Makefile | 2 +
arch/arm/dts/sun50i-h6-pine-h64.dts | 185
board/sunxi/MAINTAINERS | 5 +
configs/pine_h64_defconfig | 15 +++
4 files changed, 207 insertions(+)
create mode 100644 arch/arm/dts/sun50i-h6-pine-h64.dts
create mode 100644 configs/pine_h64_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9607239b03..2cfd39c4e3 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -385,6 +385,8 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \
sun50i-h5-orangepi-pc2.dtb \
sun50i-h5-orangepi-prime.dtb \
sun50i-h5-orangepi-zero-plus2.dtb
+dtb-$(CONFIG_MACH_SUN50I_H6) += \
+ sun50i-h6-pine-h64.dtb
dtb-$(CONFIG_MACH_SUN50I) += \
sun50i-a64-amarula-relic.dtb \
sun50i-a64-bananapi-m64.dtb \
diff --git a/arch/arm/dts/sun50i-h6-pine-h64.dts
b/arch/arm/dts/sun50i-h6-pine-h64.dts
new file mode 100644
index 00..ceffc40810
--- /dev/null
+++ b/arch/arm/dts/sun50i-h6-pine-h64.dts
@@ -0,0 +1,185 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (c) 2017 Icenowy Zheng
+ */
+
+/dts-v1/;
+
+#include "sun50i-h6.dtsi"
+
+#include
+
+/ {
+ model = "Pine H64";
+ compatible = "pine64,pine-h64", "allwinner,sun50i-h6";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ heartbeat {
+ label = "pine-h64:green:heartbeat";
+ gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
+ };
+
+ link {
+ label = "pine-h64:white:link";
+ gpios = <&r_pio 0 3 GPIO_ACTIVE_HIGH>; /* PL3 */
+ };
+
+ status {
+ label = "pine-h64:blue:status";
+ gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */
+ };
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ vmmc-supply = <®_cldo1>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins>;
+ vmmc-supply = <®_cldo1>;
+ vqmmc-supply = <®_bldo2>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
+
+&r_i2c {
+ status = "okay";
+
+ axp805: pmic@36 {
+ compatible = "x-powers,axp805", "x-powers,axp806";
+ reg = <0x36>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ x-powers,self-working-mode;
+
+ regulators {
+ reg_aldo1: aldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-name = "vcc-pl";
+ };
+
+ reg_aldo2: aldo2 {
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-name = "vcc-ac200";
+ };
+
+ reg_aldo3: aldo3 {
+ /* This regulator is connected with CLDO1 */
+ regulator-always-on;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-name = "vcc-3v3-1";
+ };
+
+ reg_bldo1: bldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-name = "vcc-bias-pll";
+ };
+
+ reg_bldo2: bldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-name = "vcc-efuse-pcie-hdmi-io";
+ };
+
+ reg_bldo3: bldo3 {
+ regulator-always-on;
+ regulator-mi
[U-Boot] [PATCH v2 12/13] sunxi: add support for Allwinner H6 SoC
Allwinner H6 is a new SoC from Allwinner features USB3 and PCIe
interfaces.
This patch adds support for it.
The corresponding DTSI file, from Linux next-20180720, is also
introduced.
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Sync device tree to next-20180720.
arch/arm/dts/sun50i-h6.dtsi | 288
arch/arm/mach-sunxi/Kconfig | 17 +-
arch/arm/mach-sunxi/cpu_info.c | 2 +
common/spl/Kconfig | 2 +-
include/dt-bindings/clock/sun50i-h6-ccu.h | 125 +
include/dt-bindings/clock/sun50i-h6-r-ccu.h | 24 ++
include/dt-bindings/reset/sun50i-h6-ccu.h | 73 +
include/dt-bindings/reset/sun50i-h6-r-ccu.h | 17 ++
8 files changed, 546 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/dts/sun50i-h6.dtsi
create mode 100644 include/dt-bindings/clock/sun50i-h6-ccu.h
create mode 100644 include/dt-bindings/clock/sun50i-h6-r-ccu.h
create mode 100644 include/dt-bindings/reset/sun50i-h6-ccu.h
create mode 100644 include/dt-bindings/reset/sun50i-h6-r-ccu.h
diff --git a/arch/arm/dts/sun50i-h6.dtsi b/arch/arm/dts/sun50i-h6.dtsi
new file mode 100644
index 00..cfa5fffcf6
--- /dev/null
+++ b/arch/arm/dts/sun50i-h6.dtsi
@@ -0,0 +1,288 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (C) 2017 Icenowy Zheng
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <1>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@2 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <2>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@3 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <3>;
+ enable-method = "psci";
+ };
+ };
+
+ iosc: internal-osc-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <1600>;
+ clock-accuracy = <3>;
+ clock-output-names = "iosc";
+ };
+
+ osc24M: osc24M_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <2400>;
+ clock-output-names = "osc24M";
+ };
+
+ osc32k: osc32k_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "osc32k";
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = ,
+,
+,
+;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ ccu: clock@3001000 {
+ compatible = "allwinner,sun50i-h6-ccu";
+ reg = <0x03001000 0x1000>;
+ clocks = <&osc24M>, <&osc32k>, <&iosc>;
+ clock-names = "hosc", "losc", "iosc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ gic: interrupt-controller@3021000 {
+ compatible = "arm,gic-400";
+ reg = <0x03021000 0x1000>,
+ <0x03022000 0x2000>,
+ <0x03024000 0x2000>,
+ <0x03026000 0x2000>;
+ interrupts = ;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
+ pio: pinctrl@300b000 {
+ compatible = "allwinner,sun50i-h6-pinctrl";
+ reg = <0x0300b000 0x400>;
+ interrupts = ,
+,
+,
+;
+ clocks = <&ccu CLK_APB1>, <&osc24M>, <&osc32k>;
[U-Boot] [PATCH v2 11/13] sunxi: add DRAM support to H6
The Allwinner H6 SoC comes with a set of new DRAM controller+PHY combo.
Both the controller and the PHY seem to be originate from DesignWare,
and are similar to the ones in ZynqMP SoCs.
This commit introduces an initial DRAM driver for H6, which contains
only LPDDR3 support. The currently known SBCs with H6 all come with
LPDDR3 memory, including Pine H64 and several Orange Pi's.
The BSP DRAM initialization code is closed source and violates GPL. Code
in this commit is written by experimenting, referring the code/document
of other users of the IPs (mainly the ZynqMP, as it's the only found PHY
reference) and disassebling the BSP blob.
Thanks for Jernej Skrabec for review and fix some issues in this driver
(including the most critical one which made it to work), and rewrite
some code from register dump!
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Change timing to make it more close to BSP.
- Add single-rank support.
- Added a huge section of comment to describe the structure of the H6
DRAM controller.
arch/arm/include/asm/arch-sunxi/dram.h| 2 +
.../include/asm/arch-sunxi/dram_sun50i_h6.h | 297 +++
arch/arm/mach-sunxi/Kconfig | 6 +
arch/arm/mach-sunxi/Makefile | 1 +
arch/arm/mach-sunxi/dram_sun50i_h6.c | 754 ++
5 files changed, 1060 insertions(+)
create mode 100644 arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h
create mode 100644 arch/arm/mach-sunxi/dram_sun50i_h6.c
diff --git a/arch/arm/include/asm/arch-sunxi/dram.h
b/arch/arm/include/asm/arch-sunxi/dram.h
index a5c091eeaa..8002b7efdc 100644
--- a/arch/arm/include/asm/arch-sunxi/dram.h
+++ b/arch/arm/include/asm/arch-sunxi/dram.h
@@ -27,6 +27,8 @@
#include
#elif defined(CONFIG_MACH_SUN9I)
#include
+#elif defined(CONFIG_MACH_SUN50I_H6)
+#include
#else
#include
#endif
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h
b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h
new file mode 100644
index 00..eeb4da5c3f
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h
@@ -0,0 +1,297 @@
+/*
+ * H6 dram controller register and constant defines
+ *
+ * (C) Copyright 2017 Icenowy Zheng
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _SUNXI_DRAM_SUN50I_H6_H
+#define _SUNXI_DRAM_SUN50I_H6_H
+
+enum sunxi_dram_type {
+ SUNXI_DRAM_TYPE_DDR3 = 3,
+ SUNXI_DRAM_TYPE_DDR4,
+ SUNXI_DRAM_TYPE_LPDDR2 = 6,
+ SUNXI_DRAM_TYPE_LPDDR3,
+};
+
+/*
+ * The following information is mainly retrieved by disassembly and some FPGA
+ * test code of sun50iw3 platform.
+ */
+struct sunxi_mctl_com_reg {
+ u32 cr; /* 0x000 control register */
+ u8 reserved_0x004[4]; /* 0x004 */
+ u32 unk_0x008; /* 0x008 */
+ u32 tmr;/* 0x00c timer register */
+ u8 reserved_0x010[4]; /* 0x010 */
+ u32 unk_0x014; /* 0x014 */
+ u8 reserved_0x018[8]; /* 0x018 */
+ u32 maer0; /* 0x020 master enable register 0 */
+ u32 maer1; /* 0x024 master enable register 1 */
+ u32 maer2; /* 0x028 master enable register 2 */
+ u8 reserved_0x02c[468]; /* 0x02c */
+ u32 bwcr; /* 0x200 bandwidth control register */
+ u8 reserved_0x204[12]; /* 0x204 */
+ /*
+* The last master configured by BSP libdram is at 0x49x, so the
+* size of this struct array is set to 41 (0x29) now.
+*/
+ struct {
+ u32 cfg0; /* 0x0 */
+ u32 cfg1; /* 0x4 */
+ u8 reserved_0x8[8]; /* 0x8 */
+ } master[41]; /* 0x210 + index * 0x10 */
+};
+check_member(sunxi_mctl_com_reg, master[40].reserved_0x8, 0x498);
+
+/*
+ * The following register information are retrieved from some similar DRAM
+ * controllers, including the DRAM controllers in Allwinner A23/A80 SoCs,
+ * Rockchip RK3328 SoC, NXP i.MX7 SoCs and Xilinx Zynq UltraScale+ SoCs.
+ *
+ * The DRAM controller in Allwinner A23/A80 SoCs and NXP i.MX7 SoCs seems
+ * to be older than the one in Allwinner H6, as the DRAMTMG9 register
+ * is missing in these SoCs. (From the product specifications of these
+ * SoCs they're not capable of DDR4)
+ *
+ * Information sources:
+ * - dram_sun9i.h and dram_sun8i_a23.h in the same directory.
+ * - sdram_rk3328.h from the RK3328 TPL DRAM patchset
+ * - i.MX 7Solo Applications Processor Reference Manual (IMX7SRM)
+ * - Zynq UltraScale+ MPSoC Register Reference (UG1087)
+ */
+struct sunxi_mctl_ctl_reg {
+ u32 mstr; /* 0x000 */
+ u32 statr; /* 0x004 unused */
+ u32 mstr1; /* 0x008 unused */
+ u32 unk_0x00c; /* 0x00c */
+ u32 mrctrl0;/* 0x010 unused */
+ u32 mrctrl1;/* 0x014 unused */
+ u32 mrstatr;/* 0x018 unused */
+ u32 mrctrl2;/* 0x01c unused */
+
Re: [U-Boot] [PULL] Please pull u-boot-rockchip/master
On Sat, Jul 21, 2018 at 02:00:05AM +0200, Dr. Philipp Tomsich wrote: > Tom, > > The first batch of changes for u-boot-rockchip/master in this iteration is > ready for you to pull. > The associated Travis report (prior to the rebase) is at > https://travis-ci.org/ptomsich/u-boot-rockchip/builds/406299101 > > Thanks, > Philipp. > > > The following changes since commit 0dd1fc09bb16869fd8adaaad082cd554c60b2c1a: > > board/imgtec/boston: Add new defconfigs to the MAINTAINERS list (2018-07-20 > 15:55:10 -0400) > > are available in the git repository at: > > git://git.denx.de/u-boot-rockchip.git master > > for you to fetch changes up to a2a5053a15e4059c7445737d60f7b8425ca863f8: > > rockchip: utilize CONFIG_DEFAULT_FDT_FILE (2018-07-21 01:56:59 +0200) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot,2/3] ARM: add RK3399 Ficus board
Ezequiel, This series breaks the build (see https://travis-ci.org/ptomsich/u-boot-rockchip/builds/406351695). Did you test with Travis prior to submitting? When you revise, I’d also prefer a ‘rockchip:’ and a ‘board:’ tag over the ARM tag … Thanks, Philipp. > On 20 Jul 2018, at 19:30, Philipp Tomsich > wrote: > >> This commit adds support for RK3399 Ficus board, >> aka ROCK960 Enterprise Edition. >> >> Following peripherals are tested and known to work: >> * Gigabit Ethernet >> * USB 2.0 >> * MMC >> >> Signed-off-by: Ezequiel Garcia >> Reviewed-by: Simon Glass >> Reviewed-by: Philipp Tomsich >> --- >> arch/arm/dts/Makefile| 1 + >> arch/arm/dts/rk3399-ficus.dts| 564 +++ >> board/rockchip/evb_rk3399/README | 2 + >> configs/ficus-rk3399_defconfig | 71 >> 4 files changed, 638 insertions(+) >> create mode 100644 arch/arm/dts/rk3399-ficus.dts >> create mode 100644 configs/ficus-rk3399_defconfig >> > > Acked-by: Philipp Tomsich > ___ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/1] config: remove unused CONFIG_SPL_RELOC_STACK_SIZE
Symbol CONFIG_SPL_RELOC_STACK_SIZE is not used anywhere. So remove it. Signed-off-by: Heinrich Schuchardt --- successfully build on Travis CI https://travis-ci.org/xypron2/u-boot/builds/406556618 --- include/configs/B4860QDS.h | 1 - include/configs/C29XPCIE.h | 1 - include/configs/P1010RDB.h | 1 - include/configs/P1022DS.h | 1 - include/configs/T102xQDS.h | 1 - include/configs/T102xRDB.h | 1 - include/configs/T104xRDB.h | 1 - include/configs/T208xQDS.h | 1 - include/configs/T208xRDB.h | 1 - include/configs/T4240RDB.h | 1 - include/configs/p1_p2_rdb_pc.h | 1 - include/configs/t4qds.h| 1 - scripts/config_whitelist.txt | 1 - 13 files changed, 13 deletions(-) diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index 9aa082bf60..723d18ee23 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -178,7 +178,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) -#define CONFIG_SPL_RELOC_STACK_SIZE(22 << 10) #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_DCSRBAR 0xf000 diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 0ae43fa355..4de25a3d06 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -303,7 +303,6 @@ #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) -#define CONFIG_SPL_RELOC_STACK_SIZE(32 << 10) #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024) #define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10) #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index b29a5113aa..c45bc348e6 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -498,7 +498,6 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) -#define CONFIG_SPL_RELOC_STACK_SIZE(16 << 10) #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) #define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10) #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024) diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 582dd360cd..ce41ab74f9 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -306,7 +306,6 @@ #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) -#define CONFIG_SPL_RELOC_STACK_SIZE(32 << 10) #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index f0ba796b4e..136c651b08 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -200,7 +200,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) -#define CONFIG_SPL_RELOC_STACK_SIZE(22 << 10) #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_DCSRBAR 0xf000 diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 3778095760..4a8836e023 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -223,7 +223,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) -#define CONFIG_SPL_RELOC_STACK_SIZE(22 << 10) #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_DCSRBAR 0xf000 diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 8dbadc0f38..455a415ca5 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -236,7 +236,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) -#define CONFIG_SPL_RELOC_STACK_SIZE(22 << 10) #define CONFIG_SYS_DCSRBAR 0xf000 #define CONF
[U-Boot] [PATCH 1/1] drivers: rtc: correctly set week day for mc146818
The driver sets the weekday incorrectly when called by the 'date set' command. Sunday is 1, Saturday is 7 unlike in U-Boot (see data sheet https://www.nxp.com/docs/en/data-sheet/MC146818.pdf, table 3). Signed-off-by: Heinrich Schuchardt --- drivers/rtc/mc146818.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/rtc/mc146818.c b/drivers/rtc/mc146818.c index 744c0f4d75..b98c39d821 100644 --- a/drivers/rtc/mc146818.c +++ b/drivers/rtc/mc146818.c @@ -143,7 +143,8 @@ static int mc146818_set(struct rtc_time *tmp) mc146818_write8(RTC_YEAR, bin2bcd(tmp->tm_year % 100)); mc146818_write8(RTC_MONTH, bin2bcd(tmp->tm_mon)); - mc146818_write8(RTC_DAY_OF_WEEK, bin2bcd(tmp->tm_wday)); + /* Sunday = 1, Saturday = 7 */ + mc146818_write8(RTC_DAY_OF_WEEK, bin2bcd(tmp->tm_wday + 1)); mc146818_write8(RTC_DATE_OF_MONTH, bin2bcd(tmp->tm_mday)); mc146818_write8(RTC_HOURS, bin2bcd(tmp->tm_hour)); mc146818_write8(RTC_MINUTES, bin2bcd(tmp->tm_min)); -- 2.18.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] watchdog: mx25: use the imx_watchdog driver for mx25
From: Martin Kaiser
The existing imx_watchdog driver is compatible with mx25 chipsets.
Add a WDOG1_BASE_ADDR define for the base address and enable the driver
in watchdog's Makefile.
To use the driver, a board must define CONFIG_IMX_WATCHDOG and
CONFIG_HW_WATCHDOG.
This fixes an issue when booting an mx25 chip via usb/serial. In this
case, the boot rom will always enable the watchdog. If u-boot is running
in interactive mode and the watchdog is not serviced, the system is
rebooted when the watchdog expires.
Signed-off-by: Martin Kaiser
---
arch/arm/include/asm/arch-mx25/imx-regs.h | 1 +
drivers/watchdog/Makefile | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h
b/arch/arm/include/asm/arch-mx25/imx-regs.h
index e0ee486..947a757 100644
--- a/arch/arm/include/asm/arch-mx25/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx25/imx-regs.h
@@ -354,6 +354,7 @@ struct cspi_regs {
#define IMX_GPIO2_BASE (0x53FD)
#define IMX_SDMA_BASE (0x53FD4000)
#define IMX_WDT_BASE (0x53FDC000)
+#define WDOG1_BASE_ADDRIMX_WDT_BASE
#define IMX_PWM1_BASE (0x53FE)
#define IMX_RTIC_BASE (0x53FEC000)
#define IMX_IIM_BASE (0x53FF)
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index f405f51..08406ca 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -5,7 +5,7 @@
obj-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o
obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o
-ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 mx7 vf610))
+ifneq (,$(filter $(SOC), mx25 mx31 mx35 mx5 mx6 mx7 vf610))
obj-y += imx_watchdog.o
endif
obj-$(CONFIG_S5P) += s5p_wdt.o
--
2.1.4
___
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[U-Boot] [PATCH] configs: omap3_logic: Remove USB Storage and enable CONFIG_BLK
With the pending requirement for CONFIG_BLK, this patch removes the USB_STORAGE option which assumes that DM_USB is enabled, but isn't yet available for the omap2340 musb glue among other issues. Once the USB issues are resolved, a future patch can enable them again. Signed-off-by: Adam Ford diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig index cd8ffd5adf..d902fe3498 100644 --- a/configs/omap3_logic_defconfig +++ b/configs/omap3_logic_defconfig @@ -30,7 +30,6 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_SPL_OF_PLATDATA=y # CONFIG_ENV_IS_IN_FAT is not set CONFIG_ENV_IS_IN_NAND=y -# CONFIG_BLK is not set CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x8200 CONFIG_DM_I2C=y @@ -57,7 +56,6 @@ CONFIG_USB_OMAP3=y CONFIG_USB_MUSB_GADGET=y CONFIG_USB_MUSB_OMAP2PLUS=y CONFIG_TWL4030_USB=y -CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="TI" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] watchdog: mx25: use the imx_watchdog driver for mx25
On Sat, Jul 21, 2018 at 2:47 PM, Martin Kaiser wrote: > From: Martin Kaiser > > The existing imx_watchdog driver is compatible with mx25 chipsets. > Add a WDOG1_BASE_ADDR define for the base address and enable the driver > in watchdog's Makefile. > > To use the driver, a board must define CONFIG_IMX_WATCHDOG and > CONFIG_HW_WATCHDOG. > > This fixes an issue when booting an mx25 chip via usb/serial. In this > case, the boot rom will always enable the watchdog. If u-boot is running > in interactive mode and the watchdog is not serviced, the system is > rebooted when the watchdog expires. > > Signed-off-by: Martin Kaiser Reviewed-by: Fabio Estevam ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, 1/1] env: typo in description of ENV_IS_IN_REMOTE
On Sat, Mar 17, 2018 at 10:53:11PM +, Heinrich Schuchardt wrote: > %s/remove/remote/ > > Signed-off-by: Heinrich Schuchardt Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] env: Simplify Makefile using $(SPL_TPL_)
On Tue, Jun 26, 2018 at 10:03:22AM -0700, York Sun wrote: > Add Kconfig options SPL_ENV_* and TPL_ENV_* and simplify Makefile. > This allows SPL/TPL image has different environment setting from > full feature U-Boot. > > Signed-off-by: York Sun Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 1/2] Add BOOTCOUNT_BOOTLIMIT to set reboot limit
Add ability to set environment bootlimit from Kconfig
Signed-off-by: Alex Kiernan
---
Changes in v3: None
Changes in v2: None
drivers/bootcount/Kconfig | 8
include/env_default.h | 3 +++
2 files changed, 11 insertions(+)
diff --git a/drivers/bootcount/Kconfig b/drivers/bootcount/Kconfig
index d335ed14b9..9a0bd516d9 100644
--- a/drivers/bootcount/Kconfig
+++ b/drivers/bootcount/Kconfig
@@ -72,6 +72,14 @@ config BOOTCOUNT_AT91
endchoice
+config BOOTCOUNT_BOOTLIMIT
+ int "Maximum number of reboot cycles allowed"
+ default 0
+ help
+ Set the Maximum number of reboot cycles allowed without the boot
+ counter being cleared.
+ If set to 0 do not set a boot limit in the environment.
+
config BOOTCOUNT_ALEN
int "I2C address length"
default 1
diff --git a/include/env_default.h b/include/env_default.h
index bd600cfa44..86b639d3e2 100644
--- a/include/env_default.h
+++ b/include/env_default.h
@@ -104,6 +104,9 @@ const uchar default_environment[] = {
"soc=" CONFIG_SYS_SOC "\0"
#endif
#endif
+#if defined(CONFIG_BOOTCOUNT_BOOTLIMIT) && (CONFIG_BOOTCOUNT_BOOTLIMIT > 0)
+ "bootlimit="__stringify(CONFIG_BOOTCOUNT_BOOTLIMIT)"\0"
+#endif
#ifdef CONFIG_EXTRA_ENV_SETTINGS
CONFIG_EXTRA_ENV_SETTINGS
#endif
--
2.17.1
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[U-Boot] [PATCH v3 0/2] Add bootlimit to Kconfig
This patch series adds the bootlimit environment variable to Kconfig and migrates users to it. Changes in v3: - Rebase - Add Lukasz' Reviewed-by Changes in v2: - include display5 in the migration to Kconfig Alex Kiernan (2): Add BOOTCOUNT_BOOTLIMIT to set reboot limit Migrate bootlimit to Kconfig configs/calimain_defconfig | 1 + configs/display5_defconfig | 1 + configs/draco_defconfig| 1 + configs/etamin_defconfig | 1 + configs/ge_bx50v3_defconfig| 1 + configs/km_kirkwood_128m16_defconfig | 1 + configs/km_kirkwood_defconfig | 1 + configs/km_kirkwood_pci_defconfig | 1 + configs/kmcoge4_defconfig | 1 + configs/kmcoge5ne_defconfig| 1 + configs/kmcoge5un_defconfig| 1 + configs/kmeter1_defconfig | 1 + configs/kmlion1_defconfig | 1 + configs/kmnusa_defconfig | 1 + configs/kmopti2_defconfig | 1 + configs/kmsugp1_defconfig | 1 + configs/kmsupx5_defconfig | 1 + configs/kmsuv31_defconfig | 1 + configs/kmtegr1_defconfig | 1 + configs/kmtepr2_defconfig | 1 + configs/kmvect1_defconfig | 1 + configs/mgcoge3un_defconfig| 1 + configs/mx53ppd_defconfig | 1 + configs/portl2_defconfig | 1 + configs/pxm2_defconfig | 1 + configs/rastaban_defconfig | 1 + configs/rut_defconfig | 1 + configs/suvd3_defconfig| 1 + configs/thuban_defconfig | 1 + configs/tuge1_defconfig| 1 + configs/tuxx1_defconfig| 1 + drivers/bootcount/Kconfig | 8 include/configs/calimain.h | 1 - include/configs/display5.h | 1 - include/configs/ge_bx50v3.h| 1 - include/configs/km/keymile-common.h| 1 - include/configs/mx53ppd.h | 1 - include/configs/siemens-am33x-common.h | 1 - include/env_default.h | 3 +++ 39 files changed, 42 insertions(+), 6 deletions(-) -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 2/2] Migrate bootlimit to Kconfig
Migrate boards which set bootlimit in the environment to Kconfig. We exclude gurnard_defconfig which includes a bootlimit=, but doesn't set CONFIG_BOOTCOUNT_LIMIT, so we'd fail to include a bootlimit setting if we migrated it. display5_defconfig and display5_factory_defconfig share a SYS_CONFIG_NAME, but only display5_defconfig enables CONFIG_BOOTCOUNT_LIMIT, so we fail to set bootlimit= in display5_factory_defconfig. This is okay because the display5_factory_defconfig doesn't need to have it set, as it is only meant to prepare the board in the factory. Environment changes for all modified configs as seen from buildman: boards.cfg is up to date. Nothing to do. Summary of 3 commits for 32 boards (8 threads, 1 job per thread) 01: Merge git://git.denx.de/u-boot-x86 arm: + draco etamin rastaban pxm2 display5 thuban rut 02: Add BOOTCOUNT_BOOTLIMIT to set reboot limit 03: Migrate bootlimit to Kconfig - display5_factory: bootlimit=3 Signed-off-by: Alex Kiernan Reviewed-by: Lukasz Majewski --- Changes in v3: - Rebase - Add Lukasz' Reviewed-by Changes in v2: - include display5 in the migration to Kconfig configs/calimain_defconfig | 1 + configs/display5_defconfig | 1 + configs/draco_defconfig| 1 + configs/etamin_defconfig | 1 + configs/ge_bx50v3_defconfig| 1 + configs/km_kirkwood_128m16_defconfig | 1 + configs/km_kirkwood_defconfig | 1 + configs/km_kirkwood_pci_defconfig | 1 + configs/kmcoge4_defconfig | 1 + configs/kmcoge5ne_defconfig| 1 + configs/kmcoge5un_defconfig| 1 + configs/kmeter1_defconfig | 1 + configs/kmlion1_defconfig | 1 + configs/kmnusa_defconfig | 1 + configs/kmopti2_defconfig | 1 + configs/kmsugp1_defconfig | 1 + configs/kmsupx5_defconfig | 1 + configs/kmsuv31_defconfig | 1 + configs/kmtegr1_defconfig | 1 + configs/kmtepr2_defconfig | 1 + configs/kmvect1_defconfig | 1 + configs/mgcoge3un_defconfig| 1 + configs/mx53ppd_defconfig | 1 + configs/portl2_defconfig | 1 + configs/pxm2_defconfig | 1 + configs/rastaban_defconfig | 1 + configs/rut_defconfig | 1 + configs/suvd3_defconfig| 1 + configs/thuban_defconfig | 1 + configs/tuge1_defconfig| 1 + configs/tuxx1_defconfig| 1 + include/configs/calimain.h | 1 - include/configs/display5.h | 1 - include/configs/ge_bx50v3.h| 1 - include/configs/km/keymile-common.h| 1 - include/configs/mx53ppd.h | 1 - include/configs/siemens-am33x-common.h | 1 - 37 files changed, 31 insertions(+), 6 deletions(-) diff --git a/configs/calimain_defconfig b/configs/calimain_defconfig index 7908cfcc34..55782463ae 100644 --- a/configs/calimain_defconfig +++ b/configs/calimain_defconfig @@ -22,6 +22,7 @@ CONFIG_CMD_PING=y CONFIG_CMD_DIAG=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_BOOTCOUNT_ADDR=0x01C23000 # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y diff --git a/configs/display5_defconfig b/configs/display5_defconfig index 1f3007f1be..0222144bf3 100644 --- a/configs/display5_defconfig +++ b/configs/display5_defconfig @@ -56,6 +56,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=02008000.spi.1:128k(SPL),1m(u-boot),64k(env1), CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y CONFIG_SYS_BOOTCOUNT_ADDR=0x020CC068 CONFIG_FSL_ESDHC=y diff --git a/configs/draco_defconfig b/configs/draco_defconfig index 5c61659fe5..3f91b0699c 100644 --- a/configs/draco_defconfig +++ b/configs/draco_defconfig @@ -56,6 +56,7 @@ CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_NAND=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y +CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_DFU_NAND=y CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y diff --git a/configs/etamin_defconfig b/configs/etamin_defconfig index 3bb9b2e34e..1ffea06294 100644 --- a/configs/etamin_defconfig +++ b/configs/etamin_defconfig @@ -56,6 +56,7 @@ CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_NAND=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_ENV=y +CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_DFU_NAND=y CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig index b312920a25..78bc91ff2c 100644 --- a/configs/ge_bx50v3_defconfig +++ b/configs/ge_bx50v3_defconfig @@ -28,6 +28,7 @@ CONFIG_DOS_PARTITION=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_EXT=y +CONFIG_BOOTCOUNT_BOOTLIMIT=10 CONFIG_SYS_BOOTCOUNT_EXT_DEVPART="1:5" CONFIG_SYS_BOOTCOUNT_ADDR=0x7000A000 CONFIG_FSL_ESDHC=y diff --git a/configs/km_kirkwood_128m16_defconfig b/configs/km_kirkwood_128m16_defconf
[U-Boot] [PATCH] configs: am3517-evm: Setup NAND booting
The NAND offsets for the kernel and U-Boot were missing. This patch sets up the offsets so the AM3517-EVM can boot from NAND when DIP switches S7:1 and S7:4 are to the OFF position Signed-off-by: Adam Ford diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig index 3b8e2900eb..41ab3fd373 100644 --- a/configs/am3517_evm_defconfig +++ b/configs/am3517_evm_defconfig @@ -18,6 +18,9 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_MTD_SUPPORT=y CONFIG_SYS_PROMPT="AM3517_EVM # " # CONFIG_CMD_IMI is not set +CONFIG_CMD_SPL=y +CONFIG_CMD_SPL_NAND_OFS=0xaa +CONFIG_CMD_SPL_WRITE_SIZE=0x2 # CONFIG_CMD_EEPROM is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_GPT is not set @@ -37,6 +40,8 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y CONFIG_SYS_NAND_BUSWIDTH_16BIT=y +CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y +CONFIG_SYS_NAND_U_BOOT_OFFS=0x8 CONFIG_SPL_NAND_SIMPLE=y CONFIG_CONS_INDEX=3 CONFIG_SYS_NS16550=y -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] ARM: AM3517-EVM: Update Maintainer
The previous e-mail pointing to Vaibhav Hiremath is bouncing and has for some time. This updates it to myself and I work for Logic PD the manufacturer of the AM3517-SOM and EVM Signed-off-by: Adam Ford diff --git a/board/logicpd/am3517evm/MAINTAINERS b/board/logicpd/am3517evm/MAINTAINERS index 7f03ac12ee..198023fb15 100644 --- a/board/logicpd/am3517evm/MAINTAINERS +++ b/board/logicpd/am3517evm/MAINTAINERS @@ -1,5 +1,5 @@ AM3517EVM BOARD -M: Vaibhav Hiremath +M: Adam Ford S: Maintained F: board/logicpd/am3517evm/ F: include/configs/am3517_evm.h -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] Revert "fdt_support: Use CONFIG_NR_DRAM_BANKS if defined"
This reverts commit 5e5745465c94605720295fab942eacbdd215db90.
The reverted commit didn't support the scenario where there are less
DRAM banks in U-Boot than in Linux.
Also, it didn't introduce any new functionality, only limitaion.
User could just increase MEMORY_BANKS_MAX if it's too small.
---
common/fdt_support.c | 4
1 file changed, 4 deletions(-)
diff --git a/common/fdt_support.c b/common/fdt_support.c
index 812eca8173..26f50a94ee 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -409,11 +409,7 @@ static int fdt_pack_reg(const void *fdt, void *buf, u64
*address, u64 *size,
return p - (char *)buf;
}
-#ifdef CONFIG_NR_DRAM_BANKS
-#define MEMORY_BANKS_MAX CONFIG_NR_DRAM_BANKS
-#else
#define MEMORY_BANKS_MAX 4
-#endif
int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks)
{
int err, nodeoffset;
--
2.18.0
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[U-Boot] [PATCH 1/1] efi_selftest: correct block device unit test
The UEFI specification mandates that the create flag is only used in
conjunction with both the read and the write flag.
Signed-off-by: Heinrich Schuchardt
---
lib/efi_selftest/efi_selftest_block_device.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/efi_selftest/efi_selftest_block_device.c
b/lib/efi_selftest/efi_selftest_block_device.c
index b82e405030..1cd13042e9 100644
--- a/lib/efi_selftest/efi_selftest_block_device.c
+++ b/lib/efi_selftest/efi_selftest_block_device.c
@@ -415,7 +415,7 @@ static int execute(void)
#ifdef CONFIG_FAT_WRITE
/* Write file */
- ret = root->open(root, &file, (s16 *)L"u-boot.txt",
+ ret = root->open(root, &file, (s16 *)L"u-boot.txt", EFI_FILE_MODE_READ |
EFI_FILE_MODE_WRITE | EFI_FILE_MODE_CREATE, 0);
if (ret != EFI_SUCCESS) {
efi_st_error("Failed to open file\n");
--
2.18.0
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Re: [U-Boot] [PATCH 00/17] fs: fat: extend FAT write operations
Hello Tom, hello Alex, I have been testing the patches. They are working fine for ASCII file names. To support Unicode file names extra work will be needed. But probably we should postpone this to a later patch series. There are some dependencies with my work for correcting errors in Unicode handling for the EFI branch. Should the patches be passed via efi-next? Best regards Heinrich ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
