Re: [U-Boot] [PATCH v3] Add single register pin controller driver
Hi Felix, Not 'hijacking' a patch, just following Linux Developer's Certificate of Origin 1.1 guidelines. As you know, I contacted you directly with this patch suggestion prior to posting to the mailing list (keeping strictly to rule c). I had hoped you would make a new version: > On 09.03.2017 08:53, James Balean wrote: >> Did you want to test/submit this? Perhaps I misinterpreted your response, which stated: On Fri, 10 Mar 2017 at 04:13, Felix Brack wrote: > This and probably more has to be accessible by _all_ mailing list subscribers. Please post there. This was confusing, as I could see no way to convert this work to a patch of your unapproved v2 patch (being new to this process). On Sat, 11 Mar 2017 at 00:07, Felix Brack wrote: > Remove this "Signed-off-by" tag as I neither made nor tested these modifications. My understanding from the 'submitting patches' guide is that the square bracket nomenclature I used indicates minor changes to an existing patch, thereby providing you with credit whilst also denoting that you do not endorse the changes. > What if I fix a bug in my v2 patch? Should I then increase from v2 to v4? Perhaps someone can clarify, but it seems logical that the version number is in order of contribution to the project, rather than being tied to any specific user. Especially given the software license it is under. Kind regards, James Balean ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 0/8] Allwinner DesignWare DRAM controller refactors and V3s SPL support
Allwinner H5/A64/V3s/R40 SoCs all feature a DRAM controller like the one in Allwinner H3, which seems from DesignWare. They do not have properly licensed official DRAM initialization code (some have even no public readable code), but they can be supported by slightly altering the H3 code (this can be done by checking register dump). This patchset mainly targets on Allwinner V3s support. Allwinner V3s have a co-packaged 64MiB DDR2 DRAM chip, and a DRAM controller nearly the same as the one in Allwinner H3 (the chip id of H3 is 0x1680, and V3s is 0x1681), but with only at most 16-bit bus width. Even the ZQ quirk in H3 is done in V3s (at least by stock boot0). Patch 1 makes reusing H3 DRAM code a Kconfig option. Patch 2 renames bus-width related macros, in order to prepare for 16-bit controllers. Patch 3 really introduces 16-bit controllers support. Patch 4 adds bank detection code to H3 DRAM initialization code, as some DDR2 chips have only 4 banks, not 8. Patch 5 adds Kconfig options to select DRAM type and timing. This patch should be merged as soon as possible, as the work to adapt to Pine64 SoPine/Pinebook and Olimex TERES I needs it (these boards use A64 and LPDDR3 DRAM). Patch 6 adds DDR2 support to the DW DRAM code. Patch 7 adds timing for the DDR2 chip co-packaged with V3s. Patch 8 really adds support for V3s DRAM controller -- currently only the DDR2 chip co-packaged with V3s will be used with this controller. More precise adjustments to the controller is still TODO, but current code can make it work. Icenowy Zheng (8): sunxi: makes an invisible option for H3-like DRAM controllers sunxi: Rename bus-width related macros in H3 DRAM code sunxi: add option for 16-bit DW DRAM controller sunxi: add bank detection code to H3 DRAM initialization code sunxi: Add selective DRAM type and timing sunxi: add support for DDR2 DRAM for DesignWare-like DRAM controller sunxi: add timing info for the DDR2 in V3s SoC sunxi: add support for V3s DRAM controller arch/arm/include/asm/arch-sunxi/dram.h | 4 +- .../{dram_sun8i_h3.h => dram_sunxi_dw.h} | 36 - arch/arm/mach-sunxi/Makefile | 3 +- .../{dram_sun8i_h3.c => dram_sunxi_dw.c} | 179 +++-- arch/arm/mach-sunxi/dram_timings/Makefile | 2 + arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c| 84 ++ arch/arm/mach-sunxi/dram_timings/ddr3_1333.c | 84 ++ board/sunxi/Kconfig| 60 +++ 8 files changed, 325 insertions(+), 127 deletions(-) rename arch/arm/include/asm/arch-sunxi/{dram_sun8i_h3.h => dram_sunxi_dw.h} (85%) rename arch/arm/mach-sunxi/{dram_sun8i_h3.c => dram_sunxi_dw.c} (79%) create mode 100644 arch/arm/mach-sunxi/dram_timings/Makefile create mode 100644 arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c create mode 100644 arch/arm/mach-sunxi/dram_timings/ddr3_1333.c -- 2.12.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 2/8] sunxi: Rename bus-width related macros in H3 DRAM code
The DesignWare DRAM controller used by H3 and newer SoCs use a bit to identify whether the DRAM is half-width. As H3 itself come with 32-bit DRAM, the two modes of the bit used to be named "MCTL_CR_32BIT" and "MCTL_CR_16BIT", but for SoCs with 16-bit DRAM they're really 8-bit and 16-bit. Rename the bit's macro, and also rename the variable name in dram_sun8i_h3.c. This commit do not add 16-bit DRAM controller support, but the support will be introduced in next commit. Signed-off-by: Icenowy Zheng --- arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h | 6 +++--- arch/arm/mach-sunxi/dram_sunxi_dw.c | 11 ++- 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h index 25d07d9863..48bd6f7c0f 100644 --- a/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h +++ b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h @@ -52,9 +52,9 @@ struct sunxi_mctl_com_reg { #define MCTL_CR_SEQUENTIAL (0x1 << 15) #define MCTL_CR_INTERLEAVED(0x0 << 15) -#define MCTL_CR_32BIT (0x1 << 12) -#define MCTL_CR_16BIT (0x0 << 12) -#define MCTL_CR_BUS_WIDTH(x) ((x) == 32 ? MCTL_CR_32BIT : MCTL_CR_16BIT) +#define MCTL_CR_FULL_WIDTH (0x1 << 12) +#define MCTL_CR_HALF_WIDTH (0x0 << 12) +#define MCTL_CR_BUS_FULL_WIDTH(x) ((x) << 12) #define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8) #define MCTL_CR_ROW_BITS(x)(((x) - 1) << 4) diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c index 9f7cc7fd4c..0c73a43075 100644 --- a/arch/arm/mach-sunxi/dram_sunxi_dw.c +++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c @@ -28,7 +28,7 @@ #define LINES_PER_BYTE_LANE(BITS_PER_BYTE + 3) struct dram_para { u16 page_size; - u8 bus_width; + u8 bus_full_width; u8 dual_rank; u8 row_bits; const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE]; @@ -358,7 +358,8 @@ static void mctl_set_cr(struct dram_para *para) (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; writel(MCTL_CR_BL8 | MCTL_CR_2T | MCTL_CR_DDR3 | MCTL_CR_INTERLEAVED | - MCTL_CR_EIGHT_BANKS | MCTL_CR_BUS_WIDTH(para->bus_width) | + MCTL_CR_EIGHT_BANKS | + MCTL_CR_BUS_FULL_WIDTH(para->bus_full_width) | (para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) | MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW_BITS(para->row_bits), &mctl_com->cr); @@ -471,7 +472,7 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para) } /* set half DQ */ - if (para->bus_width != 32) { + if (!para->bus_full_width) { writel(0x0, &mctl_ctl->dx[2].gcr); writel(0x0, &mctl_ctl->dx[3].gcr); } @@ -509,7 +510,7 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para) ((readl(&mctl_ctl->dx[3].gsr[0]) >> 24) & 0x1)) { writel(0x0, &mctl_ctl->dx[2].gcr); writel(0x0, &mctl_ctl->dx[3].gcr); - para->bus_width = 16; + para->bus_full_width = 0; } mctl_set_cr(para); @@ -613,7 +614,7 @@ unsigned long sunxi_dram_init(void) struct dram_para para = { .dual_rank = 0, - .bus_width = 32, + .bus_full_width = 1, .row_bits = 15, .page_size = 4096, -- 2.12.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/8] sunxi: makes an invisible option for H3-like DRAM controllers
Allwinner SoCs after H3 (e.g. A64, H5, R40, V3s) uses a H3-like DesignWare DRAM controller, which do not have official free DRAM initialization code, but can use modified dram_sun8i_h3.c. Add a invisible option for easier DRAM initialization code reuse. Signed-off-by: Icenowy Zheng Acked-by: Maxime Ripard --- arch/arm/include/asm/arch-sunxi/dram.h | 4 ++-- .../include/asm/arch-sunxi/{dram_sun8i_h3.h => dram_sunxi_dw.h} | 0 arch/arm/mach-sunxi/Makefile | 2 +- arch/arm/mach-sunxi/{dram_sun8i_h3.c => dram_sunxi_dw.c} | 0 board/sunxi/Kconfig | 9 + 5 files changed, 12 insertions(+), 3 deletions(-) rename arch/arm/include/asm/arch-sunxi/{dram_sun8i_h3.h => dram_sunxi_dw.h} (100%) rename arch/arm/mach-sunxi/{dram_sun8i_h3.c => dram_sunxi_dw.c} (100%) diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/asm/arch-sunxi/dram.h index 53e6d471d2..80abac95b8 100644 --- a/arch/arm/include/asm/arch-sunxi/dram.h +++ b/arch/arm/include/asm/arch-sunxi/dram.h @@ -24,8 +24,8 @@ #include #elif defined(CONFIG_MACH_SUN8I_A83T) #include -#elif defined(CONFIG_MACH_SUN8I_H3) || defined(CONFIG_MACH_SUN50I) -#include +#elif defined(CONFIG_SUNXI_DRAM_DW) +#include #elif defined(CONFIG_MACH_SUN9I) #include #else diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h similarity index 100% rename from arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h rename to arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index 7daba1169c..b8f01e3b61 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -48,7 +48,7 @@ obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o obj-$(CONFIG_MACH_SUN8I_A23) += dram_sun8i_a23.o obj-$(CONFIG_MACH_SUN8I_A33) += dram_sun8i_a33.o obj-$(CONFIG_MACH_SUN8I_A83T) += dram_sun8i_a83t.o -obj-$(CONFIG_MACH_SUN8I_H3)+= dram_sun8i_h3.o +obj-$(CONFIG_SUNXI_DRAM_DW)+= dram_sunxi_dw.o obj-$(CONFIG_MACH_SUN9I) += dram_sun9i.o obj-$(CONFIG_MACH_SUN50I) += dram_sun8i_h3.o endif diff --git a/arch/arm/mach-sunxi/dram_sun8i_h3.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c similarity index 100% rename from arch/arm/mach-sunxi/dram_sun8i_h3.c rename to arch/arm/mach-sunxi/dram_sunxi_dw.c diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 56b7513fe3..e71fdaee86 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -42,6 +42,13 @@ config SUNXI_GEN_SUN6I separate ahb reset control registers, custom pmic bus, new style watchdog, etc. +config SUNXI_DRAM_DW + bool + ---help--- + Select this for sunxi SoCs which uses a DRAM controller like the + DesignWare controller used in H3, mainly SoCs after H3, which do + not have official open-source DRAM initialization code, but can + use modified H3 DRAM initialization code. choice prompt "Sunxi SoC Variant" @@ -113,6 +120,7 @@ config MACH_SUN8I_H3 select ARCH_SUPPORT_PSCI select SUNXI_GEN_SUN6I select SUPPORT_SPL + select SUNXI_DRAM_DW select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT config MACH_SUN8I_V3S @@ -135,6 +143,7 @@ config MACH_SUN50I select ARM64 select SUNXI_GEN_SUN6I select SUPPORT_SPL + select SUNXI_DRAM_DW endchoice -- 2.12.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] omap3_overo: Reduce SPL size
Borrowing from omap3_logic, switch to SPL_SYS_MALLOC_SIMPLE and moving the stack to DDR as soon as we're able. Signed-off-by: Tom Rini --- configs/omap3_overo_defconfig | 4 1 file changed, 4 insertions(+) diff --git a/configs/omap3_overo_defconfig b/configs/omap3_overo_defconfig index e841948ae6fb..0fa05cb0fa8a 100644 --- a/configs/omap3_overo_defconfig +++ b/configs/omap3_overo_defconfig @@ -4,6 +4,10 @@ CONFIG_TARGET_OMAP3_OVERO=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_STACK_R_ADDR=0x8200 +CONFIG_SPL_STACK_R=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_OS_BOOT=y CONFIG_HUSH_PARSER=y -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] omap3_overo: Reduce SPL size
On Sat, Mar 11, 2017 at 3:34 PM, Tom Rini wrote: > Borrowing from omap3_logic, switch to SPL_SYS_MALLOC_SIMPLE and moving > the stack to DDR as soon as we're able. Should we do that for all the omap3 devices? > Signed-off-by: Tom Rini > --- > configs/omap3_overo_defconfig | 4 > 1 file changed, 4 insertions(+) > > diff --git a/configs/omap3_overo_defconfig b/configs/omap3_overo_defconfig > index e841948ae6fb..0fa05cb0fa8a 100644 > --- a/configs/omap3_overo_defconfig > +++ b/configs/omap3_overo_defconfig > @@ -4,6 +4,10 @@ CONFIG_TARGET_OMAP3_OVERO=y > CONFIG_SYS_CONSOLE_INFO_QUIET=y > CONFIG_VERSION_VARIABLE=y > CONFIG_SPL=y > +CONFIG_SPL_SYS_MALLOC_SIMPLE=y > +CONFIG_SPL_STACK_R_ADDR=0x8200 > +CONFIG_SPL_STACK_R=y > +CONFIG_SYS_MALLOC_F_LEN=0x2000 > CONFIG_SPL_MTD_SUPPORT=y > CONFIG_SPL_OS_BOOT=y > CONFIG_HUSH_PARSER=y > -- > 1.9.1 > > ___ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 3/8] sunxi: add option for 16-bit DW DRAM controller
Some Allwinner SoCs features a DesignWare-like controller with only 16 bit bus width. Add support for them. Signed-off-by: Icenowy Zheng --- arch/arm/mach-sunxi/dram_sunxi_dw.c | 34 +- board/sunxi/Kconfig | 16 2 files changed, 45 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c index 0c73a43075..b08998c0d1 100644 --- a/arch/arm/mach-sunxi/dram_sunxi_dw.c +++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c @@ -298,6 +298,13 @@ static void mctl_h3_zq_calibration_quirk(struct dram_para *para) { struct sunxi_mctl_ctl_reg * const mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + int zq_count; + +#if defined CONFIG_SUNXI_DRAM_DW_16BIT + zq_count = 4; +#else + zq_count = 6; +#endif if ((readl(SUNXI_SRAMC_BASE + 0x24) & 0xff) == 0 && (readl(SUNXI_SRAMC_BASE + 0xf0) & 0x1) == 0) { @@ -326,7 +333,7 @@ static void mctl_h3_zq_calibration_quirk(struct dram_para *para) writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]); - for (i = 0; i < 6; i++) { + for (i = 0; i < zq_count; i++) { u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf; writel((zq << 20) | (zq << 16) | (zq << 12) | @@ -348,7 +355,9 @@ static void mctl_h3_zq_calibration_quirk(struct dram_para *para) writel((zq_val[1] << 16) | zq_val[0], &mctl_ctl->zqdr[0]); writel((zq_val[3] << 16) | zq_val[2], &mctl_ctl->zqdr[1]); - writel((zq_val[5] << 16) | zq_val[4], &mctl_ctl->zqdr[2]); + if (zq_count > 4) + writel((zq_val[5] << 16) | zq_val[4], + &mctl_ctl->zqdr[2]); } } @@ -473,8 +482,14 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para) /* set half DQ */ if (!para->bus_full_width) { +#if defined CONFIG_SUNXI_DRAM_DW_32BIT writel(0x0, &mctl_ctl->dx[2].gcr); writel(0x0, &mctl_ctl->dx[3].gcr); +#elif defined CONFIG_SUNXI_DRAM_DW_16BIT + writel(0x0, &mctl_ctl->dx[1].gcr); +#else +#error Unsupported DRAM bus width! +#endif } /* data training configuration */ @@ -499,20 +514,29 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para) /* detect ranks and bus width */ if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20)) { /* only one rank */ - if (((readl(&mctl_ctl->dx[0].gsr[0]) >> 24) & 0x2) || - ((readl(&mctl_ctl->dx[1].gsr[0]) >> 24) & 0x2)) { + if (((readl(&mctl_ctl->dx[0].gsr[0]) >> 24) & 0x2) +#if defined CONFIG_SUNXI_DRAM_DW_32BIT + || ((readl(&mctl_ctl->dx[1].gsr[0]) >> 24) & 0x2) +#endif + ) { clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24, 0x1 << 24); para->dual_rank = 0; } /* only half DQ width */ +#if defined CONFIG_SUNXI_DRAM_DW_32BIT if (((readl(&mctl_ctl->dx[2].gsr[0]) >> 24) & 0x1) || ((readl(&mctl_ctl->dx[3].gsr[0]) >> 24) & 0x1)) { writel(0x0, &mctl_ctl->dx[2].gcr); writel(0x0, &mctl_ctl->dx[3].gcr); para->bus_full_width = 0; } - +#elif defined CONFIG_SUNXI_DRAM_DW_16BIT + if ((readl(&mctl_ctl->dx[1].gsr[0]) >> 24) & 0x1) { + writel(0x0, &mctl_ctl->dx[1].gcr); + para->bus_full_width = 0; + } +#endif mctl_set_cr(para); udelay(20); diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index e71fdaee86..d8a1e341e8 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -50,6 +50,20 @@ config SUNXI_DRAM_DW not have official open-source DRAM initialization code, but can use modified H3 DRAM initialization code. +if SUNXI_DRAM_DW +config SUNXI_DRAM_DW_16BIT + bool + ---help--- + Select this for sunxi SoCs with DesignWare DRAM controller and + have only 16-bit memory buswidth. + +config SUNXI_DRAM_DW_32BIT + bool + ---help--- + Select this for sunxi SoCs with DesignWare DRAM controller with + 32-bit memory buswidth. +endif + choice prompt "Sunxi SoC Variant" optional @@ -121,6 +135,7 @@ config MACH_SUN8I_H3 select SUNXI_GEN_SUN6I select SUPPORT_SPL select SUNXI_DRAM_DW + select SUNXI_DRAM_DW_32BIT select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT config MACH_SUN8I_V3S @@ -144,6 +159,7 @@ config MACH_SUN50I select SUNXI_GEN_SUN6I select SUPPORT_SPL select SUNXI_DRAM_DW + select SUNXI_DRAM_DW_32BIT endchoice -- 2.12.0 _
[U-Boot] [PATCH 4/8] sunxi: add bank detection code to H3 DRAM initialization code
Some DDR2 DRAM have only four banks, not eight. Add code to detect this situation. Signed-off-by: Icenowy Zheng --- arch/arm/mach-sunxi/dram_sunxi_dw.c | 19 +++ 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c index b08998c0d1..bb4457d2b8 100644 --- a/arch/arm/mach-sunxi/dram_sunxi_dw.c +++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c @@ -31,6 +31,7 @@ struct dram_para { u8 bus_full_width; u8 dual_rank; u8 row_bits; + u8 bank_bits; const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE]; const u8 dx_write_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE]; const u8 ac_delays[31]; @@ -367,7 +368,7 @@ static void mctl_set_cr(struct dram_para *para) (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; writel(MCTL_CR_BL8 | MCTL_CR_2T | MCTL_CR_DDR3 | MCTL_CR_INTERLEAVED | - MCTL_CR_EIGHT_BANKS | + (para->bank_bits == 3 ? MCTL_CR_EIGHT_BANKS : MCTL_CR_FOUR_BANKS) | MCTL_CR_BUS_FULL_WIDTH(para->bus_full_width) | (para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) | MCTL_CR_PAGE_SIZE(para->page_size) | @@ -575,10 +576,19 @@ static void mctl_auto_detect_dram_size(struct dram_para *para) /* detect row address bits */ para->page_size = 512; para->row_bits = 16; + para->bank_bits = 2; mctl_set_cr(para); for (para->row_bits = 11; para->row_bits < 16; para->row_bits++) - if (mctl_mem_matches((1 << (para->row_bits + 3)) * para->page_size)) + if (mctl_mem_matches((1 << (para->row_bits + para->bank_bits)) * para->page_size)) + break; + + /* detect bank address bits */ + para->bank_bits = 3; + mctl_set_cr(para); + + for (para->bank_bits = 2; para->bank_bits < 3; para->bank_bits++) + if (mctl_mem_matches((1 << para->bank_bits) * para->page_size)) break; /* detect page size */ @@ -640,6 +650,7 @@ unsigned long sunxi_dram_init(void) .dual_rank = 0, .bus_full_width = 1, .row_bits = 15, + .bank_bits = 3, .page_size = 4096, #if defined(CONFIG_MACH_SUN8I_H3) @@ -689,6 +700,6 @@ unsigned long sunxi_dram_init(void) mctl_auto_detect_dram_size(¶); mctl_set_cr(¶); - return (1UL << (para.row_bits + 3)) * para.page_size * - (para.dual_rank ? 2 : 1); + return (1UL << (para.row_bits + para.bank_bits)) * para.page_size * + (para.dual_rank ? 2 : 1); } -- 2.12.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 5/8] sunxi: Add selective DRAM type and timing
DRAM chip varies, and one code cannot satisfy all DRAMs. Add options to select a timing set. Currently only DDR3-1333 (the original set) is added into it. Signed-off-by: Icenowy Zheng --- arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h | 30 ++ arch/arm/mach-sunxi/Makefile| 1 + arch/arm/mach-sunxi/dram_sunxi_dw.c | 116 ++-- arch/arm/mach-sunxi/dram_timings/Makefile | 1 + arch/arm/mach-sunxi/dram_timings/ddr3_1333.c| 84 + board/sunxi/Kconfig | 18 6 files changed, 140 insertions(+), 110 deletions(-) create mode 100644 arch/arm/mach-sunxi/dram_timings/Makefile create mode 100644 arch/arm/mach-sunxi/dram_timings/ddr3_1333.c diff --git a/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h index 48bd6f7c0f..61da150c14 100644 --- a/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h +++ b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h @@ -191,4 +191,34 @@ struct sunxi_mctl_ctl_reg { #define DXBDLR_WRITE_DELAY(x) ((x) << 8) #define DXBDLR_READ_DELAY(x) ((x) << 0) +/* + * The delay parameters below allow to allegedly specify delay times of some + * unknown unit for each individual bit trace in each of the four data bytes + * the 32-bit wide access consists of. Also three control signals can be + * adjusted individually. + */ +#define BITS_PER_BYTE 8 +#define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE) +/* The eight data lines (DQn) plus DM, DQS and DQSN */ +#define LINES_PER_BYTE_LANE(BITS_PER_BYTE + 3) +struct dram_para { + u16 page_size; + u8 bus_full_width; + u8 dual_rank; + u8 row_bits; + u8 bank_bits; + const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE]; + const u8 dx_write_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE]; + const u8 ac_delays[31]; +}; + +static inline int ns_to_t(int nanoseconds) +{ + const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2; + + return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000); +} + +void mctl_set_timing_params(uint16_t socid, struct dram_para *para); + #endif /* _SUNXI_DRAM_SUN8I_H3_H */ diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index b8f01e3b61..e1b6fe8d5c 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -49,6 +49,7 @@ obj-$(CONFIG_MACH_SUN8I_A23) += dram_sun8i_a23.o obj-$(CONFIG_MACH_SUN8I_A33) += dram_sun8i_a33.o obj-$(CONFIG_MACH_SUN8I_A83T) += dram_sun8i_a83t.o obj-$(CONFIG_SUNXI_DRAM_DW)+= dram_sunxi_dw.o +obj-$(CONFIG_SUNXI_DRAM_DW)+= dram_timings/ obj-$(CONFIG_MACH_SUN9I) += dram_sun9i.o obj-$(CONFIG_MACH_SUN50I) += dram_sun8i_h3.o endif diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c index bb4457d2b8..401f6a4624 100644 --- a/arch/arm/mach-sunxi/dram_sunxi_dw.c +++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c @@ -16,34 +16,6 @@ #include #include -/* - * The delay parameters below allow to allegedly specify delay times of some - * unknown unit for each individual bit trace in each of the four data bytes - * the 32-bit wide access consists of. Also three control signals can be - * adjusted individually. - */ -#define BITS_PER_BYTE 8 -#define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE) -/* The eight data lines (DQn) plus DM, DQS and DQSN */ -#define LINES_PER_BYTE_LANE(BITS_PER_BYTE + 3) -struct dram_para { - u16 page_size; - u8 bus_full_width; - u8 dual_rank; - u8 row_bits; - u8 bank_bits; - const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE]; - const u8 dx_write_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE]; - const u8 ac_delays[31]; -}; - -static inline int ns_to_t(int nanoseconds) -{ - const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2; - - return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000); -} - static void mctl_phy_init(u32 val) { struct sunxi_mctl_ctl_reg * const mctl_ctl = @@ -190,87 +162,6 @@ static void mctl_set_master_priority(uint16_t socid) } } -static void mctl_set_timing_params(uint16_t socid, struct dram_para *para) -{ - struct sunxi_mctl_ctl_reg * const mctl_ctl = - (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; - - u8 tccd = 2; - u8 tfaw = ns_to_t(50); - u8 trrd = max(ns_to_t(10), 4); - u8 trcd = ns_to_t(15); - u8 trc = ns_to_t(53); - u8 txp = max(ns_to_t(8), 3); - u8 twtr = max(ns_to_t(8), 4); - u8 trtp = max(ns_to_t(8), 4); - u8 twr = max(ns_to_t(15), 3); - u8 trp = ns_to_t(15); - u8 tras = ns_to_t(38); - u16 trefi = ns_to_t(7800) / 32; - u16 trfc= ns_to_t(350); - - u8 tmrw = 0; - u8 tmrd = 4; - u8 tmod = 1
[U-Boot] [PATCH 6/8] sunxi: add support for DDR2 DRAM for DesignWare-like DRAM controller
The DesignWare-like DRAM controllers in Allwinner chips have DDR2 DRAM support, add support for it in the driver. No real DDR2 chip info is added in this commit. Signed-off-by: Icenowy Zheng --- arch/arm/mach-sunxi/dram_sunxi_dw.c | 2 ++ board/sunxi/Kconfig | 3 +++ 2 files changed, 5 insertions(+) diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c index 401f6a4624..e9dafb0527 100644 --- a/arch/arm/mach-sunxi/dram_sunxi_dw.c +++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c @@ -261,6 +261,8 @@ static void mctl_set_cr(struct dram_para *para) writel(MCTL_CR_BL8 | MCTL_CR_2T | MCTL_CR_INTERLEAVED | #if defined CONFIG_SUNXI_DRAM_DDR3 MCTL_CR_DDR3 | +#elif defined CONFIG_SUNXI_DRAM_DDR2 + MCTL_CR_DDR2 | #else #error Unsupported DRAM type! #endif diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 7e03ee8b36..b785de7f0e 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -196,6 +196,9 @@ if SUNXI_DRAM_DW config SUNXI_DRAM_DDR3 bool +config SUNXI_DRAM_DDR2 + bool + choice prompt "DRAM Type and Timing" default SUNXI_DRAM_DDR3_1333 -- 2.12.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 7/8] sunxi: add timing info for the DDR2 in V3s SoC
Allwinner V3s SoC features a co-packaged DDR2 DRAM chip, which needs its timing param. Add the timing info for it, and make this chip selectable. Signed-off-by: Icenowy Zheng --- arch/arm/mach-sunxi/dram_timings/Makefile | 1 + arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c | 84 + board/sunxi/Kconfig | 7 +++ 3 files changed, 92 insertions(+) create mode 100644 arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c diff --git a/arch/arm/mach-sunxi/dram_timings/Makefile b/arch/arm/mach-sunxi/dram_timings/Makefile index 7e71c76a5c..a4c9dc556c 100644 --- a/arch/arm/mach-sunxi/dram_timings/Makefile +++ b/arch/arm/mach-sunxi/dram_timings/Makefile @@ -1 +1,2 @@ obj-$(CONFIG_SUNXI_DRAM_DDR3_1333) += ddr3_1333.o +obj-$(CONFIG_SUNXI_DRAM_DDR2_V3S) += ddr2_v3s.o diff --git a/arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c b/arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c new file mode 100644 index 00..9077f86a8b --- /dev/null +++ b/arch/arm/mach-sunxi/dram_timings/ddr2_v3s.c @@ -0,0 +1,84 @@ +#include +#include +#include + +void mctl_set_timing_params(uint16_t socid, struct dram_para *para) +{ + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + + u8 tccd = 1; + u8 tfaw = ns_to_t(50); + u8 trrd = max(ns_to_t(10), 2); + u8 trcd = ns_to_t(20); + u8 trc = ns_to_t(65); + u8 txp = 2; + u8 twtr = max(ns_to_t(8), 2); + u8 trtp = max(ns_to_t(8), 2); + u8 twr = max(ns_to_t(15), 3); + u8 trp = ns_to_t(15); + u8 tras = ns_to_t(45); + u16 trefi = ns_to_t(7800) / 32; + u16 trfc= ns_to_t(328); + + u8 tmrw = 0; + u8 tmrd = 2; + u8 tmod = 12; + u8 tcke = 3; + u8 tcksrx = 5; + u8 tcksre = 5; + u8 tckesr = 4; + u8 trasmax = 27; + + u8 tcl = 3; /* CL 6 */ + u8 tcwl = 3; /* CWL 6 */ + u8 t_rdata_en = 1; + u8 wr_latency = 1; + + u32 tdinit0 = (400 * CONFIG_DRAM_CLK) + 1; /* 400us */ + u32 tdinit1 = (500 * CONFIG_DRAM_CLK) / 1000 + 1; /* 500ns */ + u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */ + u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1;/* 1us */ + + u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */ + u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */ + u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ + + /* set mode register */ + writel(0x263, &mctl_ctl->mr[0]); + writel(0x4, &mctl_ctl->mr[1]); + writel(0x0, &mctl_ctl->mr[2]); + writel(0x0, &mctl_ctl->mr[3]); + + /* set DRAM timing */ + writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) | + DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras), + &mctl_ctl->dramtmg[0]); + writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc), + &mctl_ctl->dramtmg[1]); + writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) | + DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd), + &mctl_ctl->dramtmg[2]); + writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod), + &mctl_ctl->dramtmg[3]); + writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) | + DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]); + writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) | + DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), + &mctl_ctl->dramtmg[5]); + + /* set two rank timing */ + clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0), + (0x66 << 8) | (0x10 << 0)); + + /* set PHY interface timing, write latency and read latency configure */ + writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) | + (wr_latency << 0), &mctl_ctl->pitmg[0]); + + /* set PHY timing, PTR0-2 use default */ + writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]); + writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]); + + /* set refresh timing */ + writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg); +} diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index b785de7f0e..ddf720f50d 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -210,6 +210,13 @@ config SUNXI_DRAM_DDR3_1333 This option is the original only supported memory type, which suits many H3/H5/A64 boards available now. +config SUNXI_DRAM_DDR2_V3S + bool "DDR2 found in V3s chip" + select SUNXI_DRAM_DDR2 + ---help--- + This option is only for the DDR2 memory chip whic
[U-Boot] [PATCH 8/8] sunxi: add support for V3s DRAM controller
Allwinner V3s features a DRAM controller like the on in H3, but with a DDR2 DRAM. Add support for it. Signed-off-by: Icenowy Zheng --- arch/arm/mach-sunxi/dram_sunxi_dw.c | 3 +++ board/sunxi/Kconfig | 9 - 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c index e9dafb0527..a520fe3501 100644 --- a/arch/arm/mach-sunxi/dram_sunxi_dw.c +++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c @@ -568,6 +568,9 @@ unsigned long sunxi_dram_init(void) */ #if defined(CONFIG_MACH_SUN8I_H3) uint16_t socid = SOCID_H3; +#elif defined(CONFIG_MACH_SUN8I_V3S) + /* TODO: set delays and mbus priority for V3s */ + uint16_t socid = SOCID_H3; #elif defined(CONFIG_MACH_SUN50I) uint16_t socid = SOCID_A64; #endif diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index ddf720f50d..61d5dc69be 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -145,6 +145,10 @@ config MACH_SUN8I_V3S select CPU_V7_HAS_VIRT select ARCH_SUPPORT_PSCI select SUNXI_GEN_SUN6I + select SUPPORT_SPL + select SUNXI_DRAM_DW + select SUNXI_DRAM_DW_16BIT + select SUNXI_DRAM_DDR2_V3S select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT config MACH_SUN9I @@ -201,11 +205,13 @@ config SUNXI_DRAM_DDR2 choice prompt "DRAM Type and Timing" - default SUNXI_DRAM_DDR3_1333 + default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S + default SUNXI_DRAM_DDR2_V3s if MACH_SUN8I_V3S config SUNXI_DRAM_DDR3_1333 bool "DDR3 1333" select SUNXI_DRAM_DDR3 + depends on !MACH_SUN8I_V3S ---help--- This option is the original only supported memory type, which suits many H3/H5/A64 boards available now. @@ -213,6 +219,7 @@ config SUNXI_DRAM_DDR3_1333 config SUNXI_DRAM_DDR2_V3S bool "DDR2 found in V3s chip" select SUNXI_DRAM_DDR2 + depends on MACH_SUN8I_V3S ---help--- This option is only for the DDR2 memory chip which is co-packaged in Allwinner V3s SoC. -- 2.12.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 0/2] add armv7m cache support
This patchset adds armv7m instruction/data caches support & enable it for stm32f7. Changed in v2: - changed strucures for memory mapped cache registers to MACROs - added lines better readability. - replaced magic numbers with MACROs. Vikas Manocha (2): armv7m: add instruction & data cache support stm32f7: enable instruction & data cache arch/arm/cpu/armv7m/Makefile | 2 +- arch/arm/cpu/armv7m/cache.c | 294 ++ arch/arm/include/asm/armv7m.h | 26 +++- arch/arm/lib/Makefile | 2 + arch/arm/mach-stm32/stm32f7/soc.c | 2 + include/configs/stm32f746-disco.h | 4 +- 6 files changed, 324 insertions(+), 6 deletions(-) create mode 100644 arch/arm/cpu/armv7m/cache.c -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 2/2] stm32f7: enable instruction & data cache
It also enables commands for cache enable/disable/status. Signed-off-by: Vikas Manocha --- Changed in v2: None arch/arm/mach-stm32/stm32f7/soc.c | 2 ++ include/configs/stm32f746-disco.h | 4 +--- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-stm32/stm32f7/soc.c b/arch/arm/mach-stm32/stm32f7/soc.c index 8baee99..ca54603 100644 --- a/arch/arm/mach-stm32/stm32f7/soc.c +++ b/arch/arm/mach-stm32/stm32f7/soc.c @@ -60,6 +60,8 @@ int arch_cpu_init(void) (V7M_MPU_RASR_XN_ENABLE | V7M_MPU_RASR_AP_RW_RW | 0x01 << V7M_MPU_RASR_TEX_SHIFT +| 0x01 << V7M_MPU_RASR_B_SHIFT +| 0x01 << V7M_MPU_RASR_C_SHIFT | V7M_MPU_RASR_SIZE_8MB | V7M_MPU_RASR_EN) , &V7M_MPU->rasr diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h index ae3211a..9e9406a 100644 --- a/include/configs/stm32f746-disco.h +++ b/include/configs/stm32f746-disco.h @@ -14,9 +14,6 @@ #define CONFIG_SYS_INIT_SP_ADDR0x2005 #define CONFIG_SYS_TEXT_BASE 0x0800 -#define CONFIG_SYS_ICACHE_OFF -#define CONFIG_SYS_DCACHE_OFF - /* * Configuration of the external SDRAM memory */ @@ -82,4 +79,5 @@ #define CONFIG_CMDLINE_EDITING #define CONFIG_CMD_MEM +#define CONFIG_CMD_CACHE #endif /* __CONFIG_H */ -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 1/2] armv7m: add instruction & data cache support
This patch adds armv7m instruction & data cache support. Signed-off-by: Vikas Manocha --- Changed in v2: - changed strucures for memory mapped cache registers to MACROs - added lines better readability. - replaced magic numbers with MACROs. arch/arm/cpu/armv7m/Makefile | 2 +- arch/arm/cpu/armv7m/cache.c | 294 ++ arch/arm/include/asm/armv7m.h | 26 +++- arch/arm/lib/Makefile | 2 + 4 files changed, 321 insertions(+), 3 deletions(-) create mode 100644 arch/arm/cpu/armv7m/cache.c diff --git a/arch/arm/cpu/armv7m/Makefile b/arch/arm/cpu/armv7m/Makefile index aff60e8..41efe11 100644 --- a/arch/arm/cpu/armv7m/Makefile +++ b/arch/arm/cpu/armv7m/Makefile @@ -6,4 +6,4 @@ # extra-y := start.o -obj-y += cpu.o +obj-y += cpu.o cache.o diff --git a/arch/arm/cpu/armv7m/cache.c b/arch/arm/cpu/armv7m/cache.c new file mode 100644 index 000..cc17366 --- /dev/null +++ b/arch/arm/cpu/armv7m/cache.c @@ -0,0 +1,294 @@ +/* + * (C) Copyright 2017 + * Vikas Manocha, ST Micoelectronics, vikas.mano...@st.com. + * + * SPDX-License-Identifier:GPL-2.0+ + */ + +#include +#include +#include +#include + +/* Cache maintenance operation registers */ + +#define IC_IALLU 0x00 +#define INVAL_ICACHE_POU 0 + +#define IC_IMVALU 0x08 +#define DC_IMVAC 0x0C +#define DC_ISW 0x10 +#define DC_CMVAU 0x14 +#define DC_CMVAC 0x18 +#define DC_CSW 0x1C +#define DC_CIMVAC 0x20 +#define DC_CISW0x24 +#define WAYS_SHIFT 30 +#define SETS_SHIFT 5 + +/* armv7m processor feature registers */ + +#define CLIDR 0x00 +#define CTR0x04 + +#define CCSIDR 0x08 +#define MASK_NUM_WAYS GENMASK(12, 3) +#define MASK_NUM_SETS GENMASK(27, 13) +#define NUM_WAYS_SHIFT 3 +#define NUM_SETS_SHIFT 13 + +#define CSSELR 0x0C +#define SEL_I_OR_D BIT(0) + +void *const v7m_cache_maint = (void *)V7M_CACHE_MAINT_BASE; +void *const v7m_processor = (void *)V7M_PROC_FTR_BASE; + + +enum cache_type { + DCACHE = 0, + ICACHE, +}; + +/* PoU : Point of Unification, Poc: Point of Coherency */ +enum cache_action { + INVALIDATE_POU, /* for i-cache invalidate by address */ + INVALIDATE_POC, /* for d-cache invalidate by address */ + INVALIDATE_SET_WAY, /* for d-cache invalidate by sets/ways */ + FLUSH_POU, + FLUSH_POC, + FLUSH_SET_WAY, + FLUSH_INVAL_POC, + FLUSH_INVAL_SET_WAY, +}; + +#ifndef CONFIG_SYS_DCACHE_OFF +struct dcache_config { + uint32_t ways; + uint32_t sets; +}; + +static void get_cache_ways_sets(struct dcache_config *cache) +{ + cache->ways = (readl(v7m_processor + CCSIDR) & MASK_NUM_WAYS) + >> NUM_WAYS_SHIFT; + cache->sets = (readl(v7m_processor + CCSIDR) & MASK_NUM_SETS) + >> NUM_SETS_SHIFT; +} + +static uint32_t *get_action_reg_set_ways(enum cache_action action) +{ + switch (action) { + case INVALIDATE_SET_WAY: + return v7m_cache_maint + DC_ISW; + case FLUSH_SET_WAY: + return v7m_cache_maint + DC_CSW; + case FLUSH_INVAL_SET_WAY: + return v7m_cache_maint + DC_CISW; + default: + break; + }; + + return NULL; +} + +static uint32_t *get_action_reg_range(enum cache_action action) +{ + switch (action) { + case INVALIDATE_POU: + return v7m_cache_maint + IC_IMVALU; + case INVALIDATE_POC: + return v7m_cache_maint + DC_IMVAC; + case FLUSH_POU: + return v7m_cache_maint + DC_CMVAU; + case FLUSH_POC: + return v7m_cache_maint + DC_CMVAC; + case FLUSH_INVAL_POC: + return v7m_cache_maint + DC_CIMVAC; + default: + break; + } + + return NULL; +} + +static uint32_t get_cline_size(enum cache_type type) +{ + uint32_t size; + + if (type == DCACHE) + clrbits_le32(v7m_processor + CSSELR, BIT(SEL_I_OR_D)); + else if (type == ICACHE) + setbits_le32(v7m_processor + CSSELR, BIT(SEL_I_OR_D)); + dsb(); + + size = readl(v7m_processor + CCSIDR) & GENMASK(2, 0); + size = size * 4 + 4; /* 0 means 4, 1 means 8 & so on */ + debug("cache line size is %d\n", size); + + return size; +} + +int action_cache_range(enum cache_action action, uint32_t start_addr, + int64_t size) +{ + uint32_t cline_size; + uint32_t *action_reg; + enum cache_type type; + + action_reg = get_action_reg_range(action); + if (!action_reg) + return -EINVAL; + if (action == INVALIDATE_POU) + type = ICACHE; + else + type = DCACHE; + + /* cache line
Re: [U-Boot] [PATCH v4 1/3] sunxi: add basic V3s support
11.03.2017, 10:09, "Icenowy Zheng" : > Basic U-Boot support is now present for V3s. > > Some memory addresses are changed specially for V3s, as the original > address map cannot fit into a so small DRAM. > > As the DRAM controller code needs a big refactor, the SPL support is > disabled in this version. > > Signed-off-by: Icenowy Zheng > Acked-by: Maxime Ripard > Reviewed-by: Jagan Teki > --- > Changes in v4: > - Enable PSCI for the SoC. (For virtualization support, although it > seems to be a joke to use virtualization on systems with 64MiB DRAM) > - Add Maxime's ACK and Jagan's Reviewed-By. > > Changes in v3: > - Remove some dead codes. > > arch/arm/include/asm/arch-sunxi/gpio.h | 1 + > arch/arm/mach-sunxi/board.c | 4 > arch/arm/mach-sunxi/cpu_info.c | 2 ++ > board/sunxi/Kconfig | 15 +-- > include/configs/sun8i.h | 2 ++ > include/configs/sunxi-common.h | 30 +++--- > 6 files changed, 49 insertions(+), 5 deletions(-) > > diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h > b/arch/arm/include/asm/arch-sunxi/gpio.h > index 85a4ec3b0e..24f85206c8 100644 > --- a/arch/arm/include/asm/arch-sunxi/gpio.h > +++ b/arch/arm/include/asm/arch-sunxi/gpio.h > @@ -161,6 +161,7 @@ enum sunxi_gpio_number { > #define SUN8I_GPB_UART2 2 > #define SUN8I_A33_GPB_UART0 3 > #define SUN8I_A83T_GPB_UART0 2 > +#define SUN8I_V3S_GPB_UART0 3 > #define SUN50I_GPB_UART0 4 > > #define SUNXI_GPC_NAND 2 > diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c > index 52be5b0551..90b3b94e51 100644 > --- a/arch/arm/mach-sunxi/board.c > +++ b/arch/arm/mach-sunxi/board.c > @@ -110,6 +110,10 @@ static int gpio_init(void) > sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0); > sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0); > sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP); > +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3S) > + sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0); > + sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0); > + sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP); > #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I) > sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0); > sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0); > diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c > index f1f6fd5ba4..15f1e0e45a 100644 > --- a/arch/arm/mach-sunxi/cpu_info.c > +++ b/arch/arm/mach-sunxi/cpu_info.c > @@ -87,6 +87,8 @@ int print_cpuinfo(void) > printf("CPU: Allwinner A83T (SUN8I %04x)\n", sunxi_get_sram_id()); > #elif defined CONFIG_MACH_SUN8I_H3 > printf("CPU: Allwinner H3 (SUN8I %04x)\n", sunxi_get_sram_id()); > +#elif defined CONFIG_MACH_SUN8I_V3S > + printf("CPU: Allwinner V3s (SUN8I %04x)\n", sunxi_get_sram_id()); > #elif defined CONFIG_MACH_SUN9I > puts("CPU: Allwinner A80 (SUN9I)\n"); > #elif defined CONFIG_MACH_SUN50I > diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig > index 37b42521a4..56b7513fe3 100644 > --- a/board/sunxi/Kconfig > +++ b/board/sunxi/Kconfig > @@ -115,6 +115,15 @@ config MACH_SUN8I_H3 > select SUPPORT_SPL > select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT > > +config MACH_SUN8I_V3S > + bool "sun8i (Allwinner V3s)" > + select CPU_V7 > + select CPU_V7_HAS_NONSEC > + select CPU_V7_HAS_VIRT > + select ARCH_SUPPORT_PSCI > + select SUNXI_GEN_SUN6I > + select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT > + > config MACH_SUN9I > bool "sun9i (Allwinner A80)" > select CPU_V7 > @@ -132,7 +141,8 @@ endchoice > # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33" > config MACH_SUN8I > bool > - default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || > MACH_SUN8I_A83T > + default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || \ > + MACH_SUN8I_A83T || MACH_SUN8I_V3S > > config RESERVE_ALLWINNER_BOOT0_HEADER > bool "reserve space for Allwinner boot0 header" > @@ -485,7 +495,8 @@ config AXP_GPIO > > config VIDEO > bool "Enable graphical uboot console on HDMI, LCD or VGA" > - depends on !MACH_SUN8I_A83T && !MACH_SUN8I_H3 && !MACH_SUN9I && !MACH_SUN50I > + depends on !MACH_SUN8I_A83T && !MACH_SUN8I_H3 && !MACH_SUN8I_V3S && \ > + !MACH_SUN9I && !MACH_SUN50I > default y > ---help--- > Say Y here to add support for using a cfb console on the HDMI, LCD > diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h > index a4c3fb69e4..6ac42acaea 100644 > --- a/include/configs/sun8i.h > +++ b/include/configs/sun8i.h > @@ -21,6 +21,8 @@ > #define CONFIG_SUNXI_USB_PHYS 4 > #elif defined CONFIG_MACH_SUN8I_A83T > #define CONFIG_SUNXI_USB_PHYS 3 > +#elif defined CONFIG_MACH_SUN8I_V3S > + #define CONFIG_SUNXI_USB_PHYS 1 > #else > #define CONFIG_SUNXI_USB_PHYS 2 > #endif > diff --git a/include/configs/sunxi
Re: [U-Boot] [PATCH] omap3_overo: Reduce SPL size
On Sat, Mar 11, 2017 at 04:08:47PM +, Peter Robinson wrote: > On Sat, Mar 11, 2017 at 3:34 PM, Tom Rini wrote: > > Borrowing from omap3_logic, switch to SPL_SYS_MALLOC_SIMPLE and moving > > the stack to DDR as soon as we're able. > > Should we do that for all the omap3 devices? Yes. I'm probably doing this one first on its own so that we can bring in the thumb errata patch (which grows this one into non-linking in travis). But I think I should hold off on the errata patch until after the release, just to be safe. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] arm: omap-common: Fix typo in CONFIG_OMAP54XX guard
On Tue, Mar 07, 2017 at 03:42:24AM +0100, Matthijs van Duin wrote: > Some initialization was unintentionally being skipped on omap5. > > Fixes: f5af0827f276 ("arm: omap-common: Guard some parts of the code with > CONFIG_OMAP44XX/OMAP54XX") > Signed-off-by: Matthijs van Duin > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] tools: binman: change shebang from python into python2
On Mon, Mar 06, 2017 at 09:07:11PM +0100, Jörg Krause wrote: > This tool does not work with Python 3. Change the shebang to make sure the > script is run by a Python 2 interpreter. > > Signed-off-by: Jörg Krause Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [U-Boot, v2] arm: OMAP2+: nandecc: propagate error to command return status
On Mon, Mar 06, 2017 at 01:54:30PM +0100, Ladislav Michl wrote: > Currently nandecc returns zero even if underlaying > omap_nand_switch_ecc function fails. Fix that by > propagating error returned to command return value. > > Signed-off-by: Ladislav Michl > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/2] armv7m: add instruction & data cache support
On 03/12/2017 01:13 AM, Vikas Manocha wrote: > This patch adds armv7m instruction & data cache support. > > Signed-off-by: Vikas Manocha > --- > > Changed in v2: > - changed strucures for memory mapped cache registers to MACROs Macro is written in lowercase, FYI ... > - added lines better readability. > - replaced magic numbers with MACROs. > > arch/arm/cpu/armv7m/Makefile | 2 +- > arch/arm/cpu/armv7m/cache.c | 294 > ++ > arch/arm/include/asm/armv7m.h | 26 +++- > arch/arm/lib/Makefile | 2 + > 4 files changed, 321 insertions(+), 3 deletions(-) > create mode 100644 arch/arm/cpu/armv7m/cache.c > > diff --git a/arch/arm/cpu/armv7m/Makefile b/arch/arm/cpu/armv7m/Makefile > index aff60e8..41efe11 100644 > --- a/arch/arm/cpu/armv7m/Makefile > +++ b/arch/arm/cpu/armv7m/Makefile > @@ -6,4 +6,4 @@ > # > > extra-y := start.o > -obj-y += cpu.o > +obj-y += cpu.o cache.o > diff --git a/arch/arm/cpu/armv7m/cache.c b/arch/arm/cpu/armv7m/cache.c > new file mode 100644 > index 000..cc17366 > --- /dev/null > +++ b/arch/arm/cpu/armv7m/cache.c > @@ -0,0 +1,294 @@ > +/* > + * (C) Copyright 2017 > + * Vikas Manocha, ST Micoelectronics, vikas.mano...@st.com. > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include > +#include > +#include > +#include > + > +/* Cache maintenance operation registers */ > + > +#define IC_IALLU 0x00 > +#define INVAL_ICACHE_POU 0 > + > +#define IC_IMVALU0x08 > +#define DC_IMVAC 0x0C > +#define DC_ISW 0x10 > +#define DC_CMVAU 0x14 > +#define DC_CMVAC 0x18 > +#define DC_CSW 0x1C > +#define DC_CIMVAC0x20 > +#define DC_CISW 0x24 Would be nice to have some more distinguishing name here, so one can easily git grep for those reg names and make sense of their name without reading the datasheet . > +#define WAYS_SHIFT 30 > +#define SETS_SHIFT 5 Is this always 30 and 5 , on all CPUs ? > +/* armv7m processor feature registers */ > + > +#define CLIDR0x00 > +#define CTR 0x04 > + > +#define CCSIDR 0x08 > +#define MASK_NUM_WAYSGENMASK(12, 3) > +#define MASK_NUM_SETSGENMASK(27, 13) > +#define NUM_WAYS_SHIFT 3 > +#define NUM_SETS_SHIFT 13 > + > +#define CSSELR 0x0C > +#define SEL_I_OR_D BIT(0) > + > +void *const v7m_cache_maint = (void *)V7M_CACHE_MAINT_BASE; > +void *const v7m_processor = (void *)V7M_PROC_FTR_BASE; Needed ? Why don't you just use the macro directly ? > + > + > +enum cache_type { > + DCACHE = 0, > + ICACHE, > +}; > + > +/* PoU : Point of Unification, Poc: Point of Coherency */ > +enum cache_action { > + INVALIDATE_POU, /* for i-cache invalidate by address */ > + INVALIDATE_POC, /* for d-cache invalidate by address */ > + INVALIDATE_SET_WAY, /* for d-cache invalidate by sets/ways */ > + FLUSH_POU, > + FLUSH_POC, > + FLUSH_SET_WAY, > + FLUSH_INVAL_POC, > + FLUSH_INVAL_SET_WAY, > +}; > + > +#ifndef CONFIG_SYS_DCACHE_OFF > +struct dcache_config { > + uint32_t ways; > + uint32_t sets; u32 , this is not userspace ... > +}; > + > +static void get_cache_ways_sets(struct dcache_config *cache) > +{ > + cache->ways = (readl(v7m_processor + CCSIDR) & MASK_NUM_WAYS) > + >> NUM_WAYS_SHIFT; > + cache->sets = (readl(v7m_processor + CCSIDR) & MASK_NUM_SETS) > + >> NUM_SETS_SHIFT; Do you need to read the reg twice ? > +} > + > +static uint32_t *get_action_reg_set_ways(enum cache_action action) > +{ > + switch (action) { > + case INVALIDATE_SET_WAY: > + return v7m_cache_maint + DC_ISW; > + case FLUSH_SET_WAY: > + return v7m_cache_maint + DC_CSW; > + case FLUSH_INVAL_SET_WAY: > + return v7m_cache_maint + DC_CISW; > + default: > + break; > + }; > + > + return NULL; > +} > + > +static uint32_t *get_action_reg_range(enum cache_action action) > +{ > + switch (action) { > + case INVALIDATE_POU: > + return v7m_cache_maint + IC_IMVALU; > + case INVALIDATE_POC: > + return v7m_cache_maint + DC_IMVAC; > + case FLUSH_POU: > + return v7m_cache_maint + DC_CMVAU; > + case FLUSH_POC: > + return v7m_cache_maint + DC_CMVAC; > + case FLUSH_INVAL_POC: > + return v7m_cache_maint + DC_CIMVAC; > + default: > + break; > + } > + > + return NULL; > +} > + > +static uint32_t get_cline_size(enum cache_type type) > +{ > + uint32_t size; > + > + if (type == DCACHE) > + clrbits_le32(v7m_processor + CSSELR, BIT(SEL_I_OR_D)); > + else if (type == ICACHE) > + setbits_le32(v7m_processor + CSSELR, BIT(SEL_I_OR_D)); >
[U-Boot] [PATCH] mmc: drop unnecessary send_status request
It's redundant to send cmd13 after cmd9 whose response is not R1b. The card devices will not be busy w/ cmd9. Signed-off-by: Ziyuan Xu --- drivers/mmc/mmc.c | 4 1 file changed, 4 deletions(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 3648950..72fc177 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -,7 +,6 @@ static int mmc_startup(struct mmc *mmc) struct mmc_cmd cmd; ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN); - int timeout = 1000; bool has_parts = false; bool part_completed; struct blk_desc *bdesc; @@ -1167,9 +1166,6 @@ static int mmc_startup(struct mmc *mmc) err = mmc_send_cmd(mmc, &cmd, NULL); - /* Waiting for the ready status */ - mmc_send_status(mmc, timeout); - if (err) return err; -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot