Re: [U-Boot] [PATCH] dm: ns16550: Add support for reg-offset property
On 25.2.2016 05:47, Derald D. Woods wrote: > On Wed, Feb 24, 2016 at 12:26:09PM +0100, Michal Simek wrote: >> On 24.2.2016 11:56, Adam Ford wrote: >>> On Tue, Feb 23, 2016 at 12:38 AM, Simon Glass wrote: Hi Michal, On 22 February 2016 at 00:40, Michal Simek wrote: > On 19.2.2016 21:55, Simon Glass wrote: >> Hi Michal, >> >> On 16 February 2016 at 08:17, Michal Simek >> wrote: >>> reg-offset is the part of standard 8250 binding in the kernel. >>> It is shifting start of address space by reg-offset. >>> On Xilinx platform this offset is typically 0x1000. >>> >>> Signed-off-by: Michal Simek >>> --- >>> >>> drivers/serial/ns16550.c | 6 -- >>> include/ns16550.h| 1 + >>> 2 files changed, 5 insertions(+), 2 deletions(-) >> >> Reviewed-by: Simon Glass >> >> Do you support the debug UART feature on your boards? > > yes. I do support it but there you can put just address plus offset and > there is no reason to add one more option to Kconfig. > But let me know if you think that this is incorrect flow. >>> >>> This patch seems to break my OMAP3 board. Does anyone know if I need >>> to set a certain offset for OMAP3 to make this work (and where is the >>> right place for it) ? >> >> Are you using DT init? Check your DT description if there is reg-offset >> property. I expect if your board worked before and you remove this >> property it will start to work again. >> > > I am seeing the same problem with my BeagleBoard Rev. C4. There is > something common, to more than one board, happening with this commit. You should enable debug console and send the log. Do you have enough space for malloc? The patch is quite simple and if your DT has no this property there are not so many options what can be problematic. I expect when you enable debug console you will get more information. Thanks, Michal ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v2, 3/7] drivers: block: disk-uclass: implement scsi_init()
On Wednesday 24 February 2016 09:50 PM, Tom Rini wrote:
> On Wed, Feb 03, 2016 at 05:29:36PM +0530, Mugunthan V N wrote:
>
>> Implement scsi_init() api to probe driver model based sata
>> devices.
>>
>> Signed-off-by: Mugunthan V N
>> Reviewed-by: Simon Glass
>> ---
>> drivers/block/disk-uclass.c | 39 +++
>> 1 file changed, 39 insertions(+)
>>
>> diff --git a/drivers/block/disk-uclass.c b/drivers/block/disk-uclass.c
>> index d665b35..4bd7b56 100644
>> --- a/drivers/block/disk-uclass.c
>> +++ b/drivers/block/disk-uclass.c
>> @@ -7,6 +7,45 @@
>>
>> #include
>> #include
>> +#include
>> +#include
>> +#include
>> +
>> +int scsi_get_device(int index, struct udevice **devp)
>> +{
>> +struct udevice *dev;
>> +int ret;
>> +
>> +ret = uclass_find_device(UCLASS_DISK, index, &dev);
>> +if (ret || !dev) {
>> +printf("%d device not found\n", index);
>> +return ret;
>> +}
>> +
>> +ret = device_probe(dev);
>> +if (ret) {
>> +error("device probe error\n");
>> +return ret;
>> +}
>> +
>> +*devp = dev;
>> +
>> +return ret;
>> +}
>> +
>> +void scsi_init(void)
>> +{
>> +struct udevice *dev;
>> +int ret;
>> +
>> +ret = scsi_get_device(0, &dev);
>> +if (ret || !dev) {
>> +error("scsi device not found\n");
>> +return;
>> +}
>> +
>> +scsi_scan(1);
>> +}
>>
>> UCLASS_DRIVER(disk) = {
>> .id = UCLASS_DISK,
>
> OK, this patch is a problem. Many platforms already define scsi_init()
> and aren't moved over so now fail to build. Mele_M5 is one of many
> examples here, thanks!
>
Oops, sorry I didn't run buildman before submitting the patches, will
make sure running buildman before submitting patches in future.
Issue is when a platform is converted to DM, by default CONFIG_DISK is
selected through Kconfig whether the platform has block device or not,
disk_uclass driver is compile which results in build break when the
platform has scsi_init already defined and not not converted to DM.
The following diff solves the issue, and CONFIG_DISK has to be selected
for platforms which supports disk (sata, ide etc)
Simon, Are you Okay with the patch, so that I can send it as a separate
fixup patch.
diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig
index 915c1eb..e62bf75 100644
--- a/drivers/block/Kconfig
+++ b/drivers/block/Kconfig
@@ -1,7 +1,7 @@
config DISK
bool "Support disk controllers with driver model"
depends on DM
- default y if DM
+ default n if DM
help
This enables a uclass for disk controllers in U-Boot. Various driver
types can use this, such as AHCI/SATA. It does not provide any
standard
Regards
Mugunthan V N
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[U-Boot] [PATCH] mmc: sdhci: Clear internal clock enable bit
Disable internal clock by clearing the internal clock enable bit. This bit needs to be cleared too when we stop the SDCLK for changing the frequency divisor. This bit should be set to zero when the device is not using the Host controller. Signed-off-by: Siva Durga Prasad Paladugu --- drivers/mmc/sdhci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 8586d89..cab0148 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -303,7 +303,7 @@ static int sdhci_set_clock(struct mmc *mmc, unsigned int clock) } reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL); - reg &= ~SDHCI_CLOCK_CARD_EN; + reg &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN); sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); if (clock == 0) -- 2.1.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 01/10] thunderx: Calculate TCR dynamically
On Wed, Feb 24, 2016 at 06:39:22PM +0100, Alexander Graf wrote:
> On 02/24/2016 02:37 PM, Mark Rutland wrote:
> >On Wed, Feb 24, 2016 at 01:11:35PM +0100, Alexander Graf wrote:
> >>+ /* Calculate the maximum physical (and thus virtual) address */
> >>+ if (max_addr > (1ULL << 44)) {
> >>+ ips = 5;
> >>+ va_bits = 48;
> >>+ } else if (max_addr > (1ULL << 42)) {
> >>+ ips = 4;
> >>+ va_bits = 44;
> >>+ } else if (max_addr > (1ULL << 40)) {
> >>+ ips = 3;
> >>+ va_bits = 42;
> >>+ } else if (max_addr > (1ULL << 36)) {
> >>+ ips = 2;
> >>+ va_bits = 40;
> >>+ } else if (max_addr > (1ULL << 32)) {
> >>+ ips = 1;
> >>+ va_bits = 36;
> >>+ } else {
> >>+ ips = 0;
> >>+ va_bits = 32;
> >>+ }
> >In Linux we program IPS to the maximum PARange from ID_AA64MMFR0.
> >
> >If you did the same here you wouldn't have to iterate over all the
> >memory map entries to determine the maximum PA you care about (though
> >you may still need to do that for the VA size).
>
> Since we'd want to find the largest number for VA to trim one level
> of page table if we can, I don't see how it would buy is much to
> take the maximum supported PARange of the core into account.
It would simply be a saving of lines, as you'd program the same IPS
value regardless of max_addr (and you have to expect that PARange is
sufficient regardless).
Otherwise, yes, it doesn't buy you anything.
Thanks,
Mark.
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[U-Boot] [PATCH] ARM: zynq: Enable option to overwrite default variables
Enable overwriting variables out of main config file.
Signed-off-by: Michal Simek
---
include/configs/zynq-common.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 4a81d41d0f8f..41c416ae5d1d 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -211,6 +211,7 @@
#endif
/* Default environment */
+#ifndef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
"fit_image=fit.itb\0" \
"load_addr=0x200\0" \
@@ -233,6 +234,7 @@
"load usb 0 ${load_addr} ${fit_image} && " \
"bootm ${load_addr}; fi\0" \
DFU_ALT_INFO
+#endif
#define CONFIG_BOOTCOMMAND "run $modeboot"
#define CONFIG_BOOTDELAY 3 /* -1 to Disable autoboot */
--
1.9.1
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Re: [U-Boot] [PATCH] dm: ns16550: Add support for reg-offset property
On Thu, Feb 25, 2016 at 09:11:24AM +0100, Michal Simek wrote: > On 25.2.2016 05:47, Derald D. Woods wrote: > > On Wed, Feb 24, 2016 at 12:26:09PM +0100, Michal Simek wrote: > >> On 24.2.2016 11:56, Adam Ford wrote: > >>> On Tue, Feb 23, 2016 at 12:38 AM, Simon Glass wrote: > Hi Michal, > > On 22 February 2016 at 00:40, Michal Simek > wrote: > > On 19.2.2016 21:55, Simon Glass wrote: > >> Hi Michal, > >> > >> On 16 February 2016 at 08:17, Michal Simek > >> wrote: > >>> reg-offset is the part of standard 8250 binding in the kernel. > >>> It is shifting start of address space by reg-offset. > >>> On Xilinx platform this offset is typically 0x1000. > >>> > >>> Signed-off-by: Michal Simek > >>> --- > >>> > >>> drivers/serial/ns16550.c | 6 -- > >>> include/ns16550.h| 1 + > >>> 2 files changed, 5 insertions(+), 2 deletions(-) > >> > >> Reviewed-by: Simon Glass > >> > >> Do you support the debug UART feature on your boards? > > > > yes. I do support it but there you can put just address plus offset and > > there is no reason to add one more option to Kconfig. > > But let me know if you think that this is incorrect flow. > > >>> > >>> This patch seems to break my OMAP3 board. Does anyone know if I need > >>> to set a certain offset for OMAP3 to make this work (and where is the > >>> right place for it) ? > >> > >> Are you using DT init? Check your DT description if there is reg-offset > >> property. I expect if your board worked before and you remove this > >> property it will start to work again. > >> > > > > I am seeing the same problem with my BeagleBoard Rev. C4. There is > > something common, to more than one board, happening with this commit. > > You should enable debug console and send the log. > Do you have enough space for malloc? > I will have little time this weekend to go further. Some things will need to be un-configured to have enough space. I am around 7 KiB over with DEBUG enabled. Derald > The patch is quite simple and if your DT has no this property there are > not so many options what can be problematic. > I expect when you enable debug console you will get more information. > > Thanks, > Michal > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3] test/py: Add option to skip SPL signature checking
Provide user option to skip SPL signature verification for cases where
u-boot is build with SPL support but full U-Boot is also verified
without SPL.
If you want to support this feature please add env__spl_skipped = True
to your boardenv configuration file.
For example Xilinx Zynq is using this feature where the same U-Boot
binary is checked with SPL and without SPL(with FSBL).
Signed-off-by: Michal Simek
---
Changes in v3:
- Remove Stephen's lines
- Fix my misundersting what Stephen was asking for. Use diferent
variable name but use origin env__spl_skipped board variable name
which was renamed in v2.
Changes in v2:
- nits in commit message
- Rename to env_spl_skipped from env__spl_skipped
test/py/u_boot_console_base.py | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/test/py/u_boot_console_base.py b/test/py/u_boot_console_base.py
index d6502c6e64cb..318e28824cc2 100644
--- a/test/py/u_boot_console_base.py
+++ b/test/py/u_boot_console_base.py
@@ -307,7 +307,9 @@ class ConsoleBase(object):
config_spl = bcfg.get('config_spl', 'n') == 'y'
config_spl_serial_support = bcfg.get('config_spl_serial_support',
'n') == 'y'
-if config_spl and config_spl_serial_support:
+env_spl_skipped = self.config.env.get('env__spl_skipped',
+ False)
+if config_spl and config_spl_serial_support and not
env_spl_skipped:
m = self.p.expect([pattern_u_boot_spl_signon] +
self.bad_patterns)
if m != 0:
--
1.9.1
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Re: [U-Boot] [PATCH v2] test/py: Add option to skip SPL signature checking
On 23.2.2016 18:17, Stephen Warren wrote:
> On 02/23/2016 02:40 AM, Michal Simek wrote:
>> Provide user option to skip SPL signature verification for cases where
>> u-boot is build with SPL support but full U-Boot is also verified
>> without SPL.
>>
>> If you want to support this feature please add env__spl_skipped = True
>> to your boardenv configuration file.
>>
>> For example Xilinx Zynq is using this feature where the same U-Boot
>> binary is checked with SPL and without SPL(with FSBL).
>>
>> Signed-off-by: Michal Simek
>> Tested-by: Stephen Warren
>> Acked-by: Stephen Warren
>
> Actually, NAK now...
I have removed your lines from v3.
>
>> diff --git a/test/py/u_boot_console_base.py
>> b/test/py/u_boot_console_base.py
>> index d6502c6e64cb..b48d07261ff2 100644
>> --- a/test/py/u_boot_console_base.py
>> +++ b/test/py/u_boot_console_base.py
>> @@ -307,7 +307,9 @@ class ConsoleBase(object):
>> config_spl = bcfg.get('config_spl', 'n') == 'y'
>> config_spl_serial_support =
>> bcfg.get('config_spl_serial_support',
>>'n') == 'y'
>> -if config_spl and config_spl_serial_support:
>> +config_spl_skip = self.config.env.get('env_spl_skipped',
>> + False)
>
> I was talking about renaming the Python variable config_spl_skip, not
> the boardenv_*.py variable env__spl_skipped.
>
> The boardenv_*.py variable should be env__* to match existing variables
> in the Python file.
>
> I was requesting that the Python variable be named env_... not
> config_... since it contains "board environment" not "config" data.
I misunderstood your description in v1.
Hopefully in v3 this will be correct.
> (BTW, you probably want to Cc Tom Rini on the next patch version since I
> assume he'd apply this)
Done.
Thanks,
Michal
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Re: [U-Boot] [PATCH] serial: Move carriage return before line feed for some serial drivers
This is a request for more information.
On 02/24/2016 06:41 PM, Alison Wang wrote:
In general, a carriage return needs to execute before a line feed.
The patch is to change some serial drivers based on this rule, such
as serial_mxc.c, serial_pxa.c, serial_s3c24x0.c and usbtty.c.
You write "In general, a carriage return needs to execute before a line
feed. The patch is to change some serial drivers based on this rule"
Please provide a reference. I'd probably benefit from deeper knowledge
of this subject. I had not heard this rule before.
Thank you,
Jim
Signed-off-by: Alison Wang
---
drivers/serial/serial_mxc.c | 8
drivers/serial/serial_pxa.c | 8
drivers/serial/serial_s3c24x0.c | 8
drivers/serial/usbtty.c | 7 ---
4 files changed, 16 insertions(+), 15 deletions(-)
diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index 51485c0..1563bb3 100644
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -164,15 +164,15 @@ static int mxc_serial_getc(void)
static void mxc_serial_putc(const char c)
{
+ /* If \n, also do \r */
+ if (c == '\n')
+ serial_putc('\r');
+
__REG(UART_PHYS + UTXD) = c;
/* wait for transmitter to be ready */
while (!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY))
WATCHDOG_RESET();
-
- /* If \n, also do \r */
- if (c == '\n')
- serial_putc ('\r');
}
/*
diff --git a/drivers/serial/serial_pxa.c b/drivers/serial/serial_pxa.c
index 8fbcc10..1eb19ec 100644
--- a/drivers/serial/serial_pxa.c
+++ b/drivers/serial/serial_pxa.c
@@ -156,6 +156,10 @@ void pxa_putc_dev(unsigned int uart_index, const char c)
{
struct pxa_uart_regs *uart_regs;
+ /* If \n, also do \r */
+ if (c == '\n')
+ pxa_putc_dev(uart_index, '\r');
+
uart_regs = pxa_uart_index_to_regs(uart_index);
if (!uart_regs)
hang();
@@ -163,10 +167,6 @@ void pxa_putc_dev(unsigned int uart_index, const char c)
while (!(readl(&uart_regs->lsr) & LSR_TEMT))
WATCHDOG_RESET();
writel(c, &uart_regs->thr);
-
- /* If \n, also do \r */
- if (c == '\n')
- pxa_putc_dev (uart_index,'\r');
}
/*
diff --git a/drivers/serial/serial_s3c24x0.c b/drivers/serial/serial_s3c24x0.c
index d4e7df2..0f0878a 100644
--- a/drivers/serial/serial_s3c24x0.c
+++ b/drivers/serial/serial_s3c24x0.c
@@ -135,14 +135,14 @@ static void _serial_putc(const char c, const int
dev_index)
{
struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
+ /* If \n, also do \r */
+ if (c == '\n')
+ serial_putc('\r');
+
while (!(readl(&uart->utrstat) & 0x2))
/* wait for room in the tx FIFO */ ;
writeb(c, &uart->utxh);
-
- /* If \n, also do \r */
- if (c == '\n')
- serial_putc('\r');
}
static inline void serial_putc_dev(unsigned int dev_index, const char c)
diff --git a/drivers/serial/usbtty.c b/drivers/serial/usbtty.c
index 75f0ec3..2e19813 100644
--- a/drivers/serial/usbtty.c
+++ b/drivers/serial/usbtty.c
@@ -434,11 +434,12 @@ void usbtty_putc(struct stdio_dev *dev, const char c)
if (!usbtty_configured ())
return;
- buf_push (&usbtty_output, &c, 1);
/* If \n, also do \r */
if (c == '\n')
buf_push (&usbtty_output, "\r", 1);
+ buf_push(&usbtty_output, &c, 1);
+
/* Poll at end to handle new data... */
if ((usbtty_output.size + 2) >= usbtty_output.totalsize) {
usbtty_poll ();
@@ -498,8 +499,8 @@ void usbtty_puts(struct stdio_dev *dev, const char *str)
n = next_nl_pos (str);
if (str[n] == '\n') {
- __usbtty_puts (str, n + 1);
- __usbtty_puts ("\r", 1);
+ __usbtty_puts("\r", 1);
+ __usbtty_puts(str, n + 1);
str += (n + 1);
len -= (n + 1);
} else {
--
Jim Chargin
AJA Video Systems j...@aja.com
(530) 271-3334 http://www.aja.com
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Re: [U-Boot] [PATCH v3] test/py: Add option to skip SPL signature checking
On Thu, Feb 25, 2016 at 02:58:24PM +0100, Michal Simek wrote:
> Provide user option to skip SPL signature verification for cases where
> u-boot is build with SPL support but full U-Boot is also verified
> without SPL.
>
> If you want to support this feature please add env__spl_skipped = True
> to your boardenv configuration file.
>
> For example Xilinx Zynq is using this feature where the same U-Boot
> binary is checked with SPL and without SPL(with FSBL).
>
> Signed-off-by: Michal Simek
OK, so I'm quite confused as to why there's this patch and also
https://patchwork.ozlabs.org/patch/584240/ which I am (or was) about to
push (bisecting some patches that had problems, that I had hoped to push
out has delayed me pushing a bunch of things). Does Heiko's patch also
fix the problem you see? Is one of these better than the other?
Thanks!
> ---
>
> Changes in v3:
> - Remove Stephen's lines
> - Fix my misundersting what Stephen was asking for. Use diferent
> variable name but use origin env__spl_skipped board variable name
> which was renamed in v2.
>
> Changes in v2:
> - nits in commit message
> - Rename to env_spl_skipped from env__spl_skipped
>
> test/py/u_boot_console_base.py | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/test/py/u_boot_console_base.py b/test/py/u_boot_console_base.py
> index d6502c6e64cb..318e28824cc2 100644
> --- a/test/py/u_boot_console_base.py
> +++ b/test/py/u_boot_console_base.py
> @@ -307,7 +307,9 @@ class ConsoleBase(object):
> config_spl = bcfg.get('config_spl', 'n') == 'y'
> config_spl_serial_support = bcfg.get('config_spl_serial_support',
> 'n') == 'y'
> -if config_spl and config_spl_serial_support:
> +env_spl_skipped = self.config.env.get('env__spl_skipped',
> + False)
> +if config_spl and config_spl_serial_support and not
> env_spl_skipped:
> m = self.p.expect([pattern_u_boot_spl_signon] +
>self.bad_patterns)
> if m != 0:
> --
> 1.9.1
>
--
Tom
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Re: [U-Boot] [PATCH v3] test/py: Add option to skip SPL signature checking
Hi Tom, 2016-02-25 15:30 GMT+01:00 Tom Rini : > On Thu, Feb 25, 2016 at 02:58:24PM +0100, Michal Simek wrote: > > Provide user option to skip SPL signature verification for cases where > > > u-boot is build with SPL support but full U-Boot is also verified > > without SPL. > > > > If you want to support this feature please add env__spl_skipped = True > > to your boardenv configuration file. > > > > For example Xilinx Zynq is using this feature where the same U-Boot > > binary is checked with SPL and without SPL(with FSBL). > > > > Signed-off-by: Michal Simek > > OK, so I'm quite confused as to why there's this patch and also > https://patchwork.ozlabs.org/patch/584240/ which I am (or was) about to > push (bisecting some patches that had problems, that I had hoped to push > out has delayed me pushing a bunch of things). Does Heiko's patch also > fix the problem you see? Is one of these better than the other? > Thanks! This is based on the top of Heiko patch. Heiko patch is fixing problem where you have SPL enabled but you don't have any SPL serial output which you can't track. My patch is fixing different problem which is that you have SPL enabled and SPL serial is also there but your booting flow has not SPL there. For example testing on QEMU. Testing without reruning SPL. Testing the same u-boot elf with different bootloader. That's why we talked about adding option to user to skip SPL checking via boardenv file. Thanks, Michal ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V5 7/7] board: ti: AM57xx: Add detection logic for AM57xx-evm
On 02/25/2016 01:06 AM, Lokesh Vutla wrote: > [..snip..] > [...] >> "setenv fdtfile dra72-evm.dtb; fi;" \ >> "if test $board_name = beagle_x15; then " \ >> "setenv fdtfile am57xx-beagle-x15.dtb; fi;" \ >> +"if test $board_name = am57xx_evm; then " \ >> +"setenv fdtfile am57xx-beagle-x15.dtb; fi;" \ > > Is it the same dtb file for am57xx_evm as well? or is this intentional > and will be updated later? Yes - it should be the same dtb file for 2 reasons: A) At this point in patch, we dont want to break am57xx-evm - mentioned in diffstat to remind ourselves. B) we are attempting to move all these "cape" like variants into device tree overlays -> in which case the same dtb is reused even for am57xx-evm, and overlay with panel and touchscreen for the "gpevm" panel board. So, in almost with 80% certainty, we might not introduce a am57xx_evm.dtb in upstream - we really dont need to. In fact, upstream kernel and current master u-boot does bootup successfully, and would like to maintain it so (point A). -- Regards, Nishanth Menon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Please pull u-boot-fsl-qoriq master
On Wed, Feb 24, 2016 at 05:02:52PM +, york sun wrote: > Tom, > > The following changes since commit 595af9db2422fa5ae734cfe615415b17a5098f34: > > Merge branch 'master' of git://www.denx.de/git/u-boot-imx (2016-02-21 > 07:56:16 > -0500) > > are available in the git repository at: > > > git://git.denx.de/u-boot-fsl-qoriq.git master > > for you to fetch changes up to a08b1921b4a477abe1ac4482fae9ec4bcb3cd27e: > > armv7: ls102xa: Move smmu and stream id initialization into the common soc > code (2016-02-24 08:51:15 -0800) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PULL] u-boot-socfpga/master
On Wed, Feb 24, 2016 at 07:14:34PM +0100, Marek Vasut wrote: > The following changes since commit 52dd704bf8eda7ca039cdb398ec0b6895c3ef939: > > Merge branch 'master' of http://git.denx.de/u-boot-sunxi (2016-02-23 > 15:35:47 -0500) > > are available in the git repository at: > > git://git.denx.de/u-boot-socfpga.git master > > for you to fetch changes up to e6e34ca3ad43eae88faccb01282385416d23e6e7: > > arm: socfpga: Fix ethernet reset handling (2016-02-24 19:13:03 +0100) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PULL] u-boot-usb/master
On Wed, Feb 24, 2016 at 07:13:47PM +0100, Marek Vasut wrote: > The following changes since commit 52dd704bf8eda7ca039cdb398ec0b6895c3ef939: > > Merge branch 'master' of http://git.denx.de/u-boot-sunxi (2016-02-23 > 15:35:47 -0500) > > are available in the git repository at: > > git://git.denx.de/u-boot-usb.git master > > for you to fetch changes up to d7d8c00575c8ae766d387c763395470410427b69: > > implement Fastboot via USB OTG on bcm28155_ap boards (2016-02-24 > 19:12:33 +0100) > Applied to u-boot/master, thanks! But note and please fix ASAP: Building current source for 1 boards (1 thread, 6 jobs per thread) aarch64: + p2571 +(p2571) In file included from arch/arm/include/asm/byteorder.h:29:0, +(p2571) from include/compiler.h:125, +(p2571) from include/image.h:19, +(p2571) from include/common.h:88, +(p2571) from drivers/usb/host/ehci-hcd.c:10: +(p2571)td->qt_buffer[idx] = cpu_to_hc32(virt_to_phys((void *)addr)); +(p2571) ^ +(p2571) include/linux/byteorder/little_endian.h:34:51: note: in definition of macro ‘__cpu_to_le32’ +(p2571) #define __cpu_to_le32(x) ((__force __le32)(__u32)(x)) +(p2571)^ +(p2571) drivers/usb/host/ehci-hcd.c:250:24: note: in expansion of macro ‘cpu_to_hc32’ +(p2571) ^ w+(p2571) drivers/usb/host/ehci-hcd.c: In function ‘ehci_td_buffer’: w+(p2571) drivers/usb/host/ehci-hcd.c:250:49: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] Also seen on p2371-2180 and p2371- -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, 1/4] gpio: stm32_gpio: move clock config from driver to board
On Thu, Feb 11, 2016 at 03:47:17PM -0800, Vikas Manocha wrote: > This patch removes the gpio clock enable from gpio driver & move it in the > board code, making it possible to use the gpio driver with other socs. > > Signed-off-by: Vikas Manocha Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot,v2,07/18] usb: Rename ehci-fsl.h to ehci-ci.h
On Sun, Feb 07, 2016 at 09:57:27PM +0100, Mateusz Kulikowski wrote: > Most of ehci-fsl header describe USB controller > designed by Chipidea and used by various SoC vendors. > > This patch renames it to a generic header: ehci-ci.h > Contents of file are not changed (so it contains several > references to freescale SoCs). > > Signed-off-by: Mateusz Kulikowski > Acked-by: Marek Vasut > Tested-by: Simon Glass Please note that there are more instances of usb/ehci-fsl.h that need to be caught and renamed. Thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, 2/4] gpio: stm32_gpio: move base addresses to the soc file
On Thu, Feb 11, 2016 at 03:47:18PM -0800, Vikas Manocha wrote: > Base addresses for GPIOs could be different for different socs, this > patch moves the base addresses from driver to the soc specific location. > > Signed-off-by: Vikas Manocha Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: keystone2: Get rid of unused clock files
On Wed, Feb 24, 2016 at 05:48:43PM -0600, Nishanth Menon wrote:
> With commit fe772ebd285b ("ARM: keystone2: Use common definition for
> clk_get_rate"), we have centralized the clock code into a common clock
> logic and the redundant files, unfortunately remained... Clean that
> up.
>
> Signed-off-by: Nishanth Menon
Reviewed-by: Tom Rini
--
Tom
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Re: [U-Boot] [U-Boot, 1/4] tools: -Wno-deprecated-declarations for OpenSSL on darwin
On Tue, Feb 16, 2016 at 11:29:28PM +0100, Andreas Bießmann wrote: > Since OpenSSL is deprecated on OS X in favour of Common Crypto API disable the > warning for this host OS. > > Another solution would be to add some glue layer for crypto stuff, but I think > this is not worth the effort. > > Signed-off-by: Andreas Bießmann > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, 4/4] stm32: add support for stm32f7 & stm32f746 discovery board
On Thu, Feb 11, 2016 at 03:47:20PM -0800, Vikas Manocha wrote: > This patch adds support for stm32f7 family & stm32f746 board. > > Signed-off-by: Vikas Manocha Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot,3/4] samsung: fix mkorigenspl for darwin
On Tue, Feb 16, 2016 at 11:29:30PM +0100, Andreas Bießmann wrote: > Compiling the mkorigenspl tool on darwin complains about undefined ulong. Fix > this by using the unified way. > > Signed-off-by: Andreas Bießmann Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, 3/4] stm32x7: add support for stm32x7 serial driver
On Thu, Feb 11, 2016 at 03:47:19PM -0800, Vikas Manocha wrote: > This patch adds support for stm32f7 family usart peripheral. > > Signed-off-by: Vikas Manocha > Reviewed-by: Simon Glass Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Gracefully handle 64-bit signed-extended 32-bit Load addresses
On Tue, Feb 16, 2016 at 08:57:46AM -0500, William Cohen wrote: > To follow the MIPS 32-bit and 64-bit memory map conventions (*) recent > MIPS Linux kernels are using a 64-bit sign extended value > (0x8001) for the 32-bit load address (0x8001) of the > Creator CI20 board kernel. When this 64-bit argument was passed to > mkimage running on a 32-bit machine such as the Creator CI20 board the > load address was incorrectly formed from the upper 32-bit sign-extend > bits (0x) by the strtoul instead of from the lower 32-bits > (0x8001). The mkimage should be able to tolerate the longer > sign-extended 64-bit version of the 32-bit arguments with the use of > strtoull. Use of the strtoll in place of the strtol in mkimage.c > resolves the issue of self hosted kernel builds for the Creator CI20 > board (+) and (++). > > (*) > http://techpubs.sgi.com/library/dynaweb_docs/0620/SGI_Developer/books/DevDriver_PG/sgi_html/ch01.html > (+) https://github.com/MIPS/CI20_linux/issues/23 > (++) https://github.com/MIPS/CI20_linux/issues/22 > > Signed-off-by: William Cohen Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v3] test/py: only check for SPL signature if SPL uses serial output
On Wed, Feb 17, 2016 at 06:32:51PM +0100, Heiko Schocher wrote: > check for U-Boot SPL signature only if SPL really has a serial output. > So check if CONFIG_SPL_SERIAL_SUPPORT is active in board config. > > Signed-off-by: Heiko Schocher > Tested-by: Stephen Warren > Reviewed-by: Stephen Warren Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, 4/4] pci_rom: fix may be used uninitialized warning
On Tue, Feb 16, 2016 at 11:29:31PM +0100, Andreas Bießmann wrote: > Building pci_rom.c with my toolchain complains about may be used uninitialized > rom varaible: > Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, V2] OMAP3SOM BOARD: Auto detect Logic PD Models
On Wed, Feb 17, 2016 at 09:49:49PM -0600, Adam Ford wrote: > Logic PD makes four different system on modules. This patch will auto > detect the board type and identify the corresponding device tree image. > > V2: > Added 'default:' case to switch statement > Since board_late_init() is defined as int, we now return 0 > > Signed-off-by: Derald Woods > Signed-off-by: Adam Ford Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot,1/5] board/BuR: drop ETH-support in SPL-Stage
On Fri, Feb 19, 2016 at 12:09:42PM +0100, Hannes Schmelzer wrote: > During very early prototype-phase we did boot the AM335x boards > initially from CPSW-EMAC. > > Now we don't need this feature anymore. > > So we drop it to save MLO-space and having therefore a more quickly > boot. > > Signed-off-by: Hannes Schmelzer > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot,01/10] arm: am437x: cm-t43: fix cm-t43 boot
On Fri, Feb 19, 2016 at 07:19:41PM +0200, Nikita Kiryanov wrote: > spl_board_init() is necessary for boot. Remove the #undef that keeps > it out of the boot sequence. > > Cc: Tom Rini > Cc: Albert Aribaud > Cc: Igor Grinberg > Signed-off-by: Nikita Kiryanov > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, 4/5] board/BuR: split bur_am335x_common.h into am335x-specific and BuR common parts
On Fri, Feb 19, 2016 at 12:09:45PM +0100, Hannes Schmelzer wrote: > bur_am335x_common.h today holds all common configuration which is shared > over all B&R boards. > > In future we want to bring up boards which are not based on AM335x only > but we still want to have common configuration over all B&R boards > independent from their architecture. > > To prepare this we introduce a new file "bur_cfg_common.h", where we > move all common things, which are not architecture specific, from > bur_am335x_common.h. > > On B&R am335x boards we include from now: > > #include > #include > > On other B&R boards, we include only > #include > > Signed-off-by: Hannes Schmelzer > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, 02/10] arm: am437x: cm-t43: migrate CONFIG_DM_SERIAL to config file
On Fri, Feb 19, 2016 at 07:19:42PM +0200, Nikita Kiryanov wrote: > Move CONFIG_DM_SERIAL to cm_t43_defconfig. This forces us to update the > CONFIG_SYS_NS16550_REG_SIZE value for SPL. > > Cc: Tom Rini > Cc: Albert Aribaud > Cc: Igor Grinberg > Signed-off-by: Nikita Kiryanov > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot,5/5] board/BuR/kwb: cosmetic changes
On Fri, Feb 19, 2016 at 12:09:46PM +0100, Hannes Schmelzer wrote: > - fixup typo > - fixup identation > > Signed-off-by: Hannes Schmelzer > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot,04/10] arm: am437x: cm-t43: define prompt
On Fri, Feb 19, 2016 at 07:19:44PM +0200, Nikita Kiryanov wrote: > Define prompt for cm-t43. > > Cc: Tom Rini > Cc: Albert Aribaud > Cc: Igor Grinberg > Signed-off-by: Nikita Kiryanov > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, 03/10] arm: am437x: cm-t43: support all available SPI flash chips
On Fri, Feb 19, 2016 at 07:19:43PM +0200, Nikita Kiryanov wrote: > Add full support for SPI flash chips to future-proof U-Boot for cm-t43. > > Cc: Tom Rini > Cc: Albert Aribaud > Cc: Igor Grinberg > Signed-off-by: Nikita Kiryanov > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot,05/10] arm: am437x: cm-t43: split board file
On Fri, Feb 19, 2016 at 07:19:45PM +0200, Nikita Kiryanov wrote: > Simplify the board file by splitting it to spl portion and u-boot portion. > Some unnecessary includes were identified and removed. No functional changes. > > Cc: Tom Rini > Cc: Albert Aribaud > Cc: Igor Grinberg > Signed-off-by: Nikita Kiryanov > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, 06/10] pmic: tps65218: add useful functions and defines
On Fri, Feb 19, 2016 at 07:19:46PM +0200, Nikita Kiryanov wrote: > Add the following functions: > tps65218_reg_read() for accessing redisters > tps65218_toggle_fseal() for toggling the fseal bit > tps65218_lock_fsea() for locking the fseal bit to 1 > > Add the following defines: > All status register bits > > Cc: Tom Rini > Cc: Albert Aribaud > Cc: Igor Grinberg > Signed-off-by: Nikita Kiryanov > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, 10/10] arm: am437x: cm-t43: update parameters for raw mmc boot
On Fri, Feb 19, 2016 at 07:19:50PM +0200, Nikita Kiryanov wrote: > Update U-Boot offset and size for raw mmc boot. > > Cc: Tom Rini > Cc: Albert Aribaud > Cc: Igor Grinberg > Signed-off-by: Nikita Kiryanov > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot,07/10] arm: am437x: cm-t43: set tps fseal bit
On Fri, Feb 19, 2016 at 07:19:47PM +0200, Nikita Kiryanov wrote: > Set TPS65218 FSEAL bit to 1 so that RTC could be powered using on-board > 3V battery. This is necessary so that time and date will survive reboots and > power offs. > > Cc: Tom Rini > Cc: Albert Aribaud > Cc: Igor Grinberg > Signed-off-by: Nikita Kiryanov > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v2] MAINTAINERS: Update no longer valid maintainers' status
On Sun, Feb 21, 2016 at 07:54:41PM -0800, Bin Meng wrote: > The following maintainers' email addresses are no longer valid. > > vipin.ku...@st.com > martin.kra...@tq-systems.de > kim.phill...@freescale.com > fgret...@spaceteq.co.za > > Update status of the components they used to maintain to be: > S: Orphaned (Since 2016-02) > > Signed-off-by: Bin Meng Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, 08/10] arm: am437x: cm-t43: get rid of enable_vtt_regulator()
On Fri, Feb 19, 2016 at 07:19:48PM +0200, Nikita Kiryanov wrote: > CM-T43 does not have a vtt regulator. Remove the function that's supposed > to enable it. > > Cc: Tom Rini > Cc: Albert Aribaud > Cc: Igor Grinberg > Signed-off-by: Nikita Kiryanov > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] tools: Update openrisc toolchain information
On Sun, Feb 21, 2016 at 09:18:02PM -0800, Bin Meng wrote: > Since commit 87da2690ab81b5f29f83dc85c55f933e6ef414bc > "openrisc: updating build tools naming convention", openrisc > kernel.org toolchain is out of date and cannot build U-Boot. > Update buildman and moveconfig tools to refer to the new one. > > Signed-off-by: Bin Meng Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] arm: am437x: cm-t43: bring back BOOTDELAY feature
On Sun, Feb 21, 2016 at 01:59:20PM +0200, Nikita Kiryanov wrote: > Commit 755324 (configs: Use config_distro_defaults.h in ti_armv7_common.h) > made ti_armv7_common.h include config_distro_defaults.h. This breaks the > bootdelay feature in cm_t43 because now the > - #include ti_armv7_common.h (#define CONFIG_BOOTDELAY 1) > - #undef CONFIG_BOOTDELAY > - #include config_distro_defaults.h (#define CONFIG_BOOTDELAY 2) > dance in cm_t43.h is no longer valid and in fact leads to CONFIG_BOOTDELAY > not being defined. > > Adapt the config file to the new inclusion hierarchy. > > Cc: Tom Rini > Cc: Albert Aribaud > Cc: Igor Grinberg > Signed-off-by: Nikita Kiryanov > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] booti: Help text rework.
On Mon, Feb 22, 2016 at 08:59:08PM +0100, Karsten Merker wrote: > Fix spelling errors in the "booti" help text and bring it more > in line with the bootm/bootz help texts. > > Signed-off-by: Karsten Merker Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] rpi: set board serial number in environment
On Mon, Feb 22, 2016 at 10:06:47PM +0100, Lubomir Rintel wrote: > Gets propagated into the device tree and then into /proc/cpuinfo where > users often expect it. > > Signed-off-by: Lubomir Rintel > Tested-by: Stephen Warren > Reviewed-by: Stephen Warren Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] cmd: mem: Show 64bit addresses which are tested
On Wed, Feb 24, 2016 at 08:36:02AM +0100, Michal Simek wrote: > Fix print message to show full 64bit addresses. > > Signed-off-by: Michal Simek Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] rpi: always scroll by 10 lines
On Mon, Feb 22, 2016 at 10:15:33PM +0100, Lubomir Rintel wrote: > Scrolling the simple framebuffer is really slow in Raspberry Pi to the > point it delays the boot by a second or two and makes longer output > inconvenient to follow (printenv, md). > > Signed-off-by: Lubomir Rintel > Acked-by: Stephen Warren Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] microblaze: Add missing chosen node
On Wed, Feb 24, 2016 at 12:37:50PM +0100, Michal Simek wrote: > fdtgrep requires /chosen node to be specified or at least more nodes which > stays in DTS to generate output. > Error message: > ./tools/fdtgrep -b u-boot,dm-pre-reloc -RT dts/dt.dtb -n /chosen -O > dtb | ./tools/fdtgrep -r -O dtb - -o spl/u-boot-spl.dtb -P pinctrl-0 -P > pinctrl-names -P clocks -P clock-names -P interrupt-parent > Error: FDT_ERR_BADMAGIC > > This patch add empty chosen node to keep fdtgrep happy and pass > compilation for in tree DTS file. > > Signed-off-by: Michal Simek Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] dts: keep clock-names and clocks in SPL DTB if SPL_CLK is enabled
On 23 February 2016 at 22:09, Simon Glass wrote: > On 3 February 2016 at 04:51, Masahiro Yamada > wrote: >> These two properties are necessary for SPL to get clocks from DT. >> >> Note: >> For now, only clock look-up by index is supported (clk_get_by_index() >> function), so "clock-names" is never parsed in U-Boot. However, we >> may want to support something like clk_get_by_name() in the future, >> so let's keep "clock-names" as well as "clocks". >> >> Signed-off-by: Masahiro Yamada >> --- >> >> dts/Kconfig | 2 ++ >> 1 file changed, 2 insertions(+) > > Acked-by: Simon Glass Applied to u-boot-dm, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] patman: fix series-notes handling for buildman
On 23 February 2016 at 22:12, Simon Glass wrote:
> On 2 February 2016 at 02:24, Albert ARIBAUD wrote:
>> A patman series with a 'Series-notes' section causes
>> buildman to crash with:
>>
>> self.series.notes += self.section
>> TypeError: cannot concatenate 'str' and 'list' objects
>>
>> Fix by initializing series.notes as a one-element array
>> rather than a scalar.
>>
>> Signed-off-by: Albert ARIBAUD
>> ---
>>
>> Changes in v2:
>> - fix typo in commit message ("rathen" -> "rather")
>> - actually limit array initialization to series.notes
>>
>> tools/patman/series.py | 5 -
>> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> Acked-by: Simon Glass
> Tested-by: Simon Glass
>
> Thanks.
Applied to u-boot-dm, thanks!
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Re: [U-Boot] [PATCH v3] test/py: Add option to skip SPL signature checking
On Thu, Feb 25, 2016 at 02:58:24PM +0100, Michal Simek wrote: > Provide user option to skip SPL signature verification for cases where > u-boot is build with SPL support but full U-Boot is also verified > without SPL. > > If you want to support this feature please add env__spl_skipped = True > to your boardenv configuration file. > > For example Xilinx Zynq is using this feature where the same U-Boot > binary is checked with SPL and without SPL(with FSBL). > > Signed-off-by: Michal Simek Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] dm: Remove ARM dcc from the list
On Wed, Feb 24, 2016 at 08:34:16AM +0100, Michal Simek wrote: > Remove ARM Debug communication channel driver from the list > of not converted drivers to DM. > > Signed-off-by: Michal Simek Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 00/16] image: Fix various test failures
Hi, On 24 February 2016 at 09:14, Simon Glass wrote: > Recent changes have broken the FIT and vboot tests. Also the SPI tests have > been wrong since before the last release and were disabled. > > This series collects together the required fixes. > > Note: The FIT and vboot tests are hard to run (in that each requires manual > effort). At some point we should be able to bring these into Stephen Warren's > test framework. > > Changes in v2: > - Fix double space in comment > - Use SANDBOX_TIMER_RATE instead of an open-coded value > > Simon Glass (16): > image: Correct the OS location code to work on sandbox > Revert "image-fit: Fix signature checking" > image: Fix FIT and vboot tests to exit sandbox correctly > trace: Fix compiler warnings in trace > lib: Don't instrument the div64 function > trace: Improve the trace test number recognition > timer: Support tracing fully > timer: Provide an early timer > timer: Set up the real timer after driver model is available > sandbox: timer: Support the early timer > sandbox: Correct ordering of defconfig > sandbox: Enable the early timer > sandbox: spi: Add more debugging to SPI emulation > sandbox: spi: Remove an incorrect free() > spi: Correct two error return values > spi: Re-enable the SPI flash tests > > cmd/trace.c | 4 ++-- > common/board_f.c | 6 ++ > common/board_r.c | 14 -- > common/bootm.c| 2 +- > common/image-fit.c| 16 +--- > configs/sandbox_defconfig | 11 ++- > drivers/mtd/spi/sandbox.c | 14 ++ > drivers/mtd/spi/sf_probe.c| 4 +--- > drivers/mtd/spi/spi_flash.c | 2 +- > drivers/timer/Kconfig | 10 ++ > drivers/timer/sandbox_timer.c | 18 +++--- > drivers/timer/timer-uclass.c | 6 +++--- > include/image.h | 5 + > include/timer.h | 21 + > lib/div64.c | 3 ++- > lib/time.c| 28 +--- > test/dm/Makefile | 4 ++-- > test/image/test-fit.py| 4 > test/trace/test-trace.sh | 4 +++- > test/vboot/sandbox-u-boot.dts | 3 +++ > 20 files changed, 137 insertions(+), 42 deletions(-) > > -- > 2.7.0.rc3.207.g0ac5344 > I would like to apply this series tomorrow as it fixes various test problems for the release. Please let me know if there are any issues. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v2, 3/7] drivers: block: disk-uclass: implement scsi_init()
Hi Mugunthan,
On 25 February 2016 at 02:34, Mugunthan V N wrote:
> On Wednesday 24 February 2016 09:50 PM, Tom Rini wrote:
>> On Wed, Feb 03, 2016 at 05:29:36PM +0530, Mugunthan V N wrote:
>>
>>> Implement scsi_init() api to probe driver model based sata
>>> devices.
>>>
>>> Signed-off-by: Mugunthan V N
>>> Reviewed-by: Simon Glass
>>> ---
>>> drivers/block/disk-uclass.c | 39 +++
>>> 1 file changed, 39 insertions(+)
>>>
>>> diff --git a/drivers/block/disk-uclass.c b/drivers/block/disk-uclass.c
>>> index d665b35..4bd7b56 100644
>>> --- a/drivers/block/disk-uclass.c
>>> +++ b/drivers/block/disk-uclass.c
>>> @@ -7,6 +7,45 @@
>>>
>>> #include
>>> #include
>>> +#include
>>> +#include
>>> +#include
>>> +
>>> +int scsi_get_device(int index, struct udevice **devp)
>>> +{
>>> +struct udevice *dev;
>>> +int ret;
>>> +
>>> +ret = uclass_find_device(UCLASS_DISK, index, &dev);
>>> +if (ret || !dev) {
>>> +printf("%d device not found\n", index);
>>> +return ret;
>>> +}
>>> +
>>> +ret = device_probe(dev);
>>> +if (ret) {
>>> +error("device probe error\n");
>>> +return ret;
>>> +}
>>> +
>>> +*devp = dev;
>>> +
>>> +return ret;
>>> +}
>>> +
>>> +void scsi_init(void)
>>> +{
>>> +struct udevice *dev;
>>> +int ret;
>>> +
>>> +ret = scsi_get_device(0, &dev);
>>> +if (ret || !dev) {
>>> +error("scsi device not found\n");
>>> +return;
>>> +}
>>> +
>>> +scsi_scan(1);
>>> +}
>>>
>>> UCLASS_DRIVER(disk) = {
>>> .id = UCLASS_DISK,
>>
>> OK, this patch is a problem. Many platforms already define scsi_init()
>> and aren't moved over so now fail to build. Mele_M5 is one of many
>> examples here, thanks!
>>
>
> Oops, sorry I didn't run buildman before submitting the patches, will
> make sure running buildman before submitting patches in future.
>
> Issue is when a platform is converted to DM, by default CONFIG_DISK is
> selected through Kconfig whether the platform has block device or not,
> disk_uclass driver is compile which results in build break when the
> platform has scsi_init already defined and not not converted to DM.
>
> The following diff solves the issue, and CONFIG_DISK has to be selected
> for platforms which supports disk (sata, ide etc)
>
> Simon, Are you Okay with the patch, so that I can send it as a separate
> fixup patch.
It is OK, but please enable CONFIG_DISK in chromebook_link_defconfig.
It is the only user at present.
With driver model we actually don't want scsi_init() to be implemented
in the end. It's fine for now. The driver-model block-device series
will make some changes here down the track. We'll have UCLASS_SATA (or
similar) rather than something as generic as UCLASS_DISK.
>
> diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig
> index 915c1eb..e62bf75 100644
> --- a/drivers/block/Kconfig
> +++ b/drivers/block/Kconfig
> @@ -1,7 +1,7 @@
> config DISK
> bool "Support disk controllers with driver model"
> depends on DM
> - default y if DM
> + default n if DM
> help
> This enables a uclass for disk controllers in U-Boot. Various driver
> types can use this, such as AHCI/SATA. It does not provide any
> standard
>
> Regards
> Mugunthan V N
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Regards,
Simon
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[U-Boot] Please pull u-boot-dm
Hi Tom, The following changes since commit 52dd704bf8eda7ca039cdb398ec0b6895c3ef939: Merge branch 'master' of http://git.denx.de/u-boot-sunxi (2016-02-23 15:35:47 -0500) are available in the git repository at: git://git.denx.de/u-boot-dm.git for you to fetch changes up to 070b781b2beb5298cd904fd514ba50e8530b0e2c: patman: fix series-notes handling for buildman (2016-02-24 20:06:19 -0800) Albert ARIBAUD (1): patman: fix series-notes handling for buildman Masahiro Yamada (1): dts: keep clock-names and clocks in SPL DTB if SPL_CLK is enabled dts/Kconfig| 2 ++ tools/patman/series.py | 5 - 2 files changed, 6 insertions(+), 1 deletion(-) Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, 3/5] board/BuR: move everything possible from board's headerfile to KConfig
On Fri, Feb 19, 2016 at 12:09:44PM +0100, Hannes Schmelzer wrote: > We drop everything possible things from board headerfiles and replace > this functionality with responsible settings in Kconfig (_defconfig). > > Signed-off-by: Hannes Schmelzer > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, 2/5] board/BuR: use default u-boot prompt on all B&R boards
On Fri, Feb 19, 2016 at 12:09:43PM +0100, Hannes Schmelzer wrote: > There is no need to have some specific prompt, so we drop this within > defconfigs. > > Signed-off-by: Hannes Schmelzer > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Please pull u-boot-dm
On Thu, Feb 25, 2016 at 08:30:22AM -0700, Simon Glass wrote: > Hi Tom, > > The following changes since commit 52dd704bf8eda7ca039cdb398ec0b6895c3ef939: > > Merge branch 'master' of http://git.denx.de/u-boot-sunxi (2016-02-23 > 15:35:47 -0500) > > are available in the git repository at: > > git://git.denx.de/u-boot-dm.git > > for you to fetch changes up to 070b781b2beb5298cd904fd514ba50e8530b0e2c: > > patman: fix series-notes handling for buildman (2016-02-24 20:06:19 -0800) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, 09/10] arm: am437x: cm-t43: set MPU and CORE voltages on boot
On Fri, Feb 19, 2016 at 07:19:49PM +0200, Nikita Kiryanov wrote: > During boot, U-Boot raises the CPU frequency but the CORE and MPU regulators > are not updated. This is not a problem in cold boot since the default values > that the pmic outputs are correct, but if Linux were to switch the module to a > low power OPP, the new voltage values will be retained after a reboot and the > module will likely hang once U-Boot raises the CPU frequency back up. > > Set both CORE and MPU regulators to to 1.1V on boot. > > Cc: Tom Rini > Cc: Albert Aribaud > Cc: Igor Grinberg > Signed-off-by: Nikita Kiryanov > Reviewed-by: Tom Rini Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/6] ARM: keystone2: Use macro for DSP GEM power domain
From: Suman Anna
Define a macro for the DSP GEM power domain id number and
use it instead of a hard-coded number in the code that
disables all the DSPs on various Keystone2 SoCs.
Signed-off-by: Suman Anna
Signed-off-by: Nishanth Menon
---
arch/arm/mach-keystone/include/mach/hardware.h | 1 +
arch/arm/mach-keystone/keystone.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-keystone/include/mach/hardware.h
b/arch/arm/mach-keystone/include/mach/hardware.h
index edebcd7bc587..8ca19bbcdbe9 100644
--- a/arch/arm/mach-keystone/include/mach/hardware.h
+++ b/arch/arm/mach-keystone/include/mach/hardware.h
@@ -160,6 +160,7 @@ typedef volatile unsigned int *dv_reg_p;
#define KS2_LPSC_GEM_0 15
#define KS2_LPSC_TETRIS52
#define KS2_TETRIS_PWR_DOMAIN 31
+#define KS2_GEM_0_PWR_DOMAIN 8
/* Chip configuration unlock codes and registers */
#define KS2_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38)
diff --git a/arch/arm/mach-keystone/keystone.c
b/arch/arm/mach-keystone/keystone.c
index 11a9357db414..a8071270e9bf 100644
--- a/arch/arm/mach-keystone/keystone.c
+++ b/arch/arm/mach-keystone/keystone.c
@@ -54,7 +54,7 @@ static void turn_off_all_dsps(int num_dsps)
if (psc_disable_module(i + KS2_LPSC_GEM_0))
printf("Cannot disable module for #%d DSP", i);
- if (psc_disable_domain(i + 8))
+ if (psc_disable_domain(i + KS2_GEM_0_PWR_DOMAIN))
printf("Cannot disable domain for #%d DSP", i);
}
}
--
2.7.0
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[U-Boot] [PATCH 0/6] ARM: keystone2: Miscellaneous fixes
Hi, Please find various fixes for DDR, DSP and speed grade operations w.r.t Keystone devices Based on master 52dd704bf8ed Merge branch 'master' of http://git.denx.de/u-boot-sunxi Lokesh Vutla (2): ARM: keystone2: Allow for board specific speed definitions ARM: keystone2: K2G: Add support for different arm/device speeds Suman Anna (2): ARM: keystone2: Use macro for DSP GEM power domain ARM: keystone2: K2G: power-off DSP during boot Vitaly Andrianov (2): ARM: keystone2: use SPD info to configure K2HK and K2E DDR3 ARM: keystone2: use detected ddr3a size arch/arm/mach-keystone/Makefile| 2 + arch/arm/mach-keystone/clock.c | 19 +- arch/arm/mach-keystone/ddr3_spd.c | 466 + arch/arm/mach-keystone/include/mach/clock-k2g.h| 4 +- arch/arm/mach-keystone/include/mach/clock.h| 8 +- arch/arm/mach-keystone/include/mach/ddr3.h | 9 + arch/arm/mach-keystone/include/mach/hardware-k2g.h | 7 +- arch/arm/mach-keystone/include/mach/hardware-k2l.h | 7 + arch/arm/mach-keystone/include/mach/hardware.h | 1 + arch/arm/mach-keystone/keystone.c | 2 +- board/ti/ks2_evm/Makefile | 4 +- board/ti/ks2_evm/board.c | 4 +- board/ti/ks2_evm/board_k2e.c | 2 +- board/ti/ks2_evm/board_k2g.c | 50 ++- board/ti/ks2_evm/board_k2hk.c | 4 +- board/ti/ks2_evm/board_k2l.c | 4 +- board/ti/ks2_evm/ddr3_cfg.c| 159 +-- board/ti/ks2_evm/ddr3_cfg.h| 11 +- board/ti/ks2_evm/ddr3_k2e.c| 51 +-- board/ti/ks2_evm/ddr3_k2hk.c | 97 ++--- include/configs/k2e_evm.h | 2 + include/configs/k2hk_evm.h | 2 + 22 files changed, 628 insertions(+), 287 deletions(-) create mode 100644 arch/arm/mach-keystone/ddr3_spd.c -- 2.7.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 4/6] ARM: keystone2: K2G: Add support for different arm/device speeds
From: Lokesh Vutla
The maximum device and arm speeds can be determined by reading
EFUSE_BOOTROM register. As there is already a framework for reading this
register, adding support for all possible speeds on k2g devices.
Signed-off-by: Lokesh Vutla
Signed-off-by: Nishanth Menon
---
arch/arm/mach-keystone/clock.c | 7 +++-
arch/arm/mach-keystone/include/mach/clock-k2g.h | 4 +-
arch/arm/mach-keystone/include/mach/clock.h | 4 ++
board/ti/ks2_evm/board_k2g.c| 50 +++--
4 files changed, 57 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-keystone/clock.c b/arch/arm/mach-keystone/clock.c
index 1ae3baf982a1..b25db1e3fede 100644
--- a/arch/arm/mach-keystone/clock.c
+++ b/arch/arm/mach-keystone/clock.c
@@ -238,8 +238,11 @@ static int get_max_speed(u32 val, u32 speed_supported, int
*spds)
return spds[speed];
}
- /* If no bit is set, use SPD800 */
- return SPD800;
+ /* If no bit is set, return minimum speed */
+ if (cpu_is_k2g())
+ return SPD200;
+ else
+ return SPD800;
}
static inline u32 read_efuse_bootrom(void)
diff --git a/arch/arm/mach-keystone/include/mach/clock-k2g.h
b/arch/arm/mach-keystone/include/mach/clock-k2g.h
index 214c1d3a8360..74de6202fe50 100644
--- a/arch/arm/mach-keystone/include/mach/clock-k2g.h
+++ b/arch/arm/mach-keystone/include/mach/clock-k2g.h
@@ -12,8 +12,8 @@
#define PLLSET_CMD_LIST""
-#define DEV_SUPPORTED_SPEEDS 0xfff
-#define ARM_SUPPORTED_SPEEDS 0xfff
+#define DEV_SUPPORTED_SPEEDS 0x1ff
+#define ARM_SUPPORTED_SPEEDS 0xff
#define KS2_CLK1_6 sys_clk0_6_clk
diff --git a/arch/arm/mach-keystone/include/mach/clock.h
b/arch/arm/mach-keystone/include/mach/clock.h
index dfebcb03ea57..72724aa4a912 100644
--- a/arch/arm/mach-keystone/include/mach/clock.h
+++ b/arch/arm/mach-keystone/include/mach/clock.h
@@ -63,8 +63,12 @@
#define CLOCK_INDEXES_LIST CLK_LIST(GENERATE_INDX_STR)
enum {
+ SPD200,
+ SPD400,
+ SPD600,
SPD800,
SPD850,
+ SPD900,
SPD1000,
SPD1200,
SPD1250,
diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c
index cdeb056a76c4..b62c41225039 100644
--- a/board/ti/ks2_evm/board_k2g.c
+++ b/board/ti/ks2_evm/board_k2g.c
@@ -23,22 +23,64 @@ unsigned int external_clk[ext_clk_count] = {
[uart_clk] = SYS_CLK,
};
-static struct pll_init_data main_pll_config = {MAIN_PLL, 100, 1, 4};
-static struct pll_init_data tetris_pll_config = {TETRIS_PLL, 100, 1, 4};
+static int arm_speeds[DEVSPEED_NUMSPDS] = {
+ SPD400,
+ SPD600,
+ SPD800,
+ SPD900,
+ SPD1000,
+ SPD900,
+ SPD800,
+ SPD600,
+ SPD400,
+ SPD200,
+};
+
+static int dev_speeds[DEVSPEED_NUMSPDS] = {
+ SPD600,
+ SPD800,
+ SPD900,
+ SPD1000,
+ SPD900,
+ SPD800,
+ SPD600,
+ SPD400,
+};
+
+static struct pll_init_data main_pll_config[NUM_SPDS] = {
+ [SPD400]= {MAIN_PLL, 100, 3, 2},
+ [SPD600]= {MAIN_PLL, 300, 6, 2},
+ [SPD800]= {MAIN_PLL, 200, 3, 2},
+ [SPD900] = {TETRIS_PLL, 75, 1, 2},
+ [SPD1000] = {TETRIS_PLL, 250, 3, 2},
+};
+
+static struct pll_init_data tetris_pll_config[NUM_SPDS] = {
+ [SPD200] = {TETRIS_PLL, 250, 3, 10},
+ [SPD400] = {TETRIS_PLL, 100, 1, 6},
+ [SPD600] = {TETRIS_PLL, 100, 1, 4},
+ [SPD800] = {TETRIS_PLL, 400, 3, 4},
+ [SPD900] = {TETRIS_PLL, 75, 1, 2},
+ [SPD1000] = {TETRIS_PLL, 250, 3, 2},
+};
+
static struct pll_init_data uart_pll_config = {UART_PLL, 64, 1, 4};
static struct pll_init_data nss_pll_config = {NSS_PLL, 250, 3, 2};
static struct pll_init_data ddr3_pll_config = {DDR3A_PLL, 250, 3, 10};
struct pll_init_data *get_pll_init_data(int pll)
{
+ int speed;
struct pll_init_data *data = NULL;
switch (pll) {
case MAIN_PLL:
- data = &main_pll_config;
+ speed = get_max_dev_speed(dev_speeds);
+ data = &main_pll_config[speed];
break;
case TETRIS_PLL:
- data = &tetris_pll_config;
+ speed = get_max_arm_speed(arm_speeds);
+ data = &tetris_pll_config[speed];
break;
case NSS_PLL:
data = &nss_pll_config;
--
2.7.0
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[U-Boot] [PATCH 2/6] ARM: keystone2: K2G: power-off DSP during boot
From: Suman Anna The DSPs are powered on by default upon a Power ON reset, and they are powered off on current Keystone 2 SoCs - K2HK, K2L, K2E during the boot in u-boot. This is not functional on K2G though. Extend the existing DSP power-off support to the only DSP present on K2G. Do note that the PSC clock domain module id for DSP on K2G differs from that of previous Keystone2 SoCs. Signed-off-by: Suman Anna Signed-off-by: Nishanth Menon --- arch/arm/mach-keystone/include/mach/hardware-k2g.h | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-keystone/include/mach/hardware-k2g.h b/arch/arm/mach-keystone/include/mach/hardware-k2g.h index fa4162fe9964..ca2a119d3901 100644 --- a/arch/arm/mach-keystone/include/mach/hardware-k2g.h +++ b/arch/arm/mach-keystone/include/mach/hardware-k2g.h @@ -10,7 +10,7 @@ #ifndef __ASM_ARCH_HARDWARE_K2G_H #define __ASM_ARCH_HARDWARE_K2G_H -#define KS2_NUM_DSPS 0 +#define KS2_NUM_DSPS 1 /* Power and Sleep Controller (PSC) Domains */ #define KS2_LPSC_ALWAYSON 0 @@ -30,7 +30,10 @@ #define KS2_LPSC_MCASP 15 #define KS2_LPSC_SR16 #define KS2_LPSC_MSMC 17 -#define KS2_LPSC_GEM 18 +#ifdef KS2_LPSC_GEM_0 +#undef KS2_LPSC_GEM_0 +#endif +#define KS2_LPSC_GEM_0 18 #define KS2_LPSC_ARM 19 #define KS2_LPSC_ASRC 20 #define KS2_LPSC_ICSS 21 -- 2.7.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/6] ARM: keystone2: Allow for board specific speed definitions
From: Lokesh Vutla
Its not compulsory that speed definition should be same on EFUSE_BOOTROM
register for all keystone 2 devices. So, allow for board specific
speed definitions.
Signed-off-by: Lokesh Vutla
Signed-off-by: Nishanth Menon
---
arch/arm/mach-keystone/clock.c | 12 ++--
arch/arm/mach-keystone/include/mach/clock.h | 4 ++--
board/ti/ks2_evm/board_k2e.c| 2 +-
board/ti/ks2_evm/board_k2hk.c | 4 ++--
board/ti/ks2_evm/board_k2l.c| 4 ++--
5 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/arch/arm/mach-keystone/clock.c b/arch/arm/mach-keystone/clock.c
index 5c6051e76db8..1ae3baf982a1 100644
--- a/arch/arm/mach-keystone/clock.c
+++ b/arch/arm/mach-keystone/clock.c
@@ -228,14 +228,14 @@ void init_plls(void)
}
}
-static int get_max_speed(u32 val, u32 speed_supported)
+static int get_max_speed(u32 val, u32 speed_supported, int *spds)
{
int speed;
/* Left most setbit gives the speed */
for (speed = DEVSPEED_NUMSPDS; speed >= 0; speed--) {
if ((val & BIT(speed)) & speed_supported)
- return speeds[speed];
+ return spds[speed];
}
/* If no bit is set, use SPD800 */
@@ -250,24 +250,24 @@ static inline u32 read_efuse_bootrom(void)
return __raw_readl(KS2_EFUSE_BOOTROM);
}
-int get_max_arm_speed(void)
+int get_max_arm_speed(int *spds)
{
u32 armspeed = read_efuse_bootrom();
armspeed = (armspeed & DEVSPEED_ARMSPEED_MASK) >>
DEVSPEED_ARMSPEED_SHIFT;
- return get_max_speed(armspeed, ARM_SUPPORTED_SPEEDS);
+ return get_max_speed(armspeed, ARM_SUPPORTED_SPEEDS, spds);
}
-int get_max_dev_speed(void)
+int get_max_dev_speed(int *spds)
{
u32 devspeed = read_efuse_bootrom();
devspeed = (devspeed & DEVSPEED_DEVSPEED_MASK) >>
DEVSPEED_DEVSPEED_SHIFT;
- return get_max_speed(devspeed, DEV_SUPPORTED_SPEEDS);
+ return get_max_speed(devspeed, DEV_SUPPORTED_SPEEDS, spds);
}
/**
diff --git a/arch/arm/mach-keystone/include/mach/clock.h
b/arch/arm/mach-keystone/include/mach/clock.h
index cdcff3baee36..dfebcb03ea57 100644
--- a/arch/arm/mach-keystone/include/mach/clock.h
+++ b/arch/arm/mach-keystone/include/mach/clock.h
@@ -124,8 +124,8 @@ struct pll_init_data *get_pll_init_data(int pll);
unsigned long clk_get_rate(unsigned int clk);
unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
int clk_set_rate(unsigned int clk, unsigned long hz);
-int get_max_dev_speed(void);
-int get_max_arm_speed(void);
+int get_max_dev_speed(int *spds);
+int get_max_arm_speed(int *spds);
void pll_pa_clk_sel(void);
#endif
diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c
index f58f62358d3e..cbb3077bc36c 100644
--- a/board/ti/ks2_evm/board_k2e.c
+++ b/board/ti/ks2_evm/board_k2e.c
@@ -61,7 +61,7 @@ struct pll_init_data *get_pll_init_data(int pll)
switch (pll) {
case MAIN_PLL:
- speed = get_max_dev_speed();
+ speed = get_max_dev_speed(speeds);
data = &core_pll_config[speed];
break;
case PASS_PLL:
diff --git a/board/ti/ks2_evm/board_k2hk.c b/board/ti/ks2_evm/board_k2hk.c
index 0bd6b86e2573..e217beaed5e4 100644
--- a/board/ti/ks2_evm/board_k2hk.c
+++ b/board/ti/ks2_evm/board_k2hk.c
@@ -51,11 +51,11 @@ struct pll_init_data *get_pll_init_data(int pll)
switch (pll) {
case MAIN_PLL:
- speed = get_max_dev_speed();
+ speed = get_max_dev_speed(speeds);
data = &core_pll_config[speed];
break;
case TETRIS_PLL:
- speed = get_max_arm_speed();
+ speed = get_max_arm_speed(speeds);
data = &tetris_pll_config[speed];
break;
case PASS_PLL:
diff --git a/board/ti/ks2_evm/board_k2l.c b/board/ti/ks2_evm/board_k2l.c
index d750ad3c0b05..2a2e0057e24e 100644
--- a/board/ti/ks2_evm/board_k2l.c
+++ b/board/ti/ks2_evm/board_k2l.c
@@ -50,11 +50,11 @@ struct pll_init_data *get_pll_init_data(int pll)
switch (pll) {
case MAIN_PLL:
- speed = get_max_dev_speed();
+ speed = get_max_dev_speed(speeds);
data = &core_pll_config[speed];
break;
case TETRIS_PLL:
- speed = get_max_arm_speed();
+ speed = get_max_arm_speed(speeds);
data = &tetris_pll_config[speed];
break;
case PASS_PLL:
--
2.7.0
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[U-Boot] [PATCH 6/6] ARM: keystone2: use detected ddr3a size
From: Vitaly Andrianov
Because KS2 u-boot works in 32 bit address space the existing ram_size
global data field cannot be used. The maximum, which the get_ram_size()
can detect is 2GB only. The ft_board_setup() needs the actual ddr3 size
to fix up dtb.
This commit introduces the ddr3_get_size() which uses SPD data to
calculate the ddr3 size. This function replaces the "ddr3_size"
environment variable, which was used to get the SODIMM size.
For platforms, which don't have SODIMM with SPD and ddr3 is populated to
a board a simple ddr3_get_size function that returns ddr3 size has to be
implemented. See hardware-k2l.h
Signed-off-by: Vitaly Andrianov
Signed-off-by: Nishanth Menon
---
arch/arm/mach-keystone/ddr3_spd.c | 10 ++
arch/arm/mach-keystone/include/mach/ddr3.h | 1 +
arch/arm/mach-keystone/include/mach/hardware-k2l.h | 7 +++
board/ti/ks2_evm/board.c | 4 +---
4 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-keystone/ddr3_spd.c
b/arch/arm/mach-keystone/ddr3_spd.c
index b0768823f2eb..a99b7728cefb 100644
--- a/arch/arm/mach-keystone/ddr3_spd.c
+++ b/arch/arm/mach-keystone/ddr3_spd.c
@@ -427,6 +427,16 @@ static int ddr3_read_spd(ddr3_spd_eeprom_t *spd_params)
return 0;
}
+int ddr3_get_size(void)
+{
+ ddr3_spd_eeprom_t spd_params;
+
+ if (ddr3_read_spd(&spd_params))
+ return 0;
+
+ return ddr3_get_size_in_mb(&spd_params) / 1024;
+}
+
int ddr3_get_dimm_params_from_spd(struct ddr3_spd_cb *spd_cb)
{
struct ddr3_sodimm spd;
diff --git a/arch/arm/mach-keystone/include/mach/ddr3.h
b/arch/arm/mach-keystone/include/mach/ddr3.h
index 68d3cb4245e9..5feffe825b97 100644
--- a/arch/arm/mach-keystone/include/mach/ddr3.h
+++ b/arch/arm/mach-keystone/include/mach/ddr3.h
@@ -66,5 +66,6 @@ void ddr3_err_reset_workaround(void);
void ddr3_enable_ecc(u32 base, int test);
void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
+int ddr3_get_size(void);
#endif
diff --git a/arch/arm/mach-keystone/include/mach/hardware-k2l.h
b/arch/arm/mach-keystone/include/mach/hardware-k2l.h
index 4f1197ea923d..a59e0713593f 100644
--- a/arch/arm/mach-keystone/include/mach/hardware-k2l.h
+++ b/arch/arm/mach-keystone/include/mach/hardware-k2l.h
@@ -105,4 +105,11 @@
/* NETCP */
#define KS2_NETCP_BASE 0x2600
+#ifndef __ASSEMBLY__
+static inline int ddr3_get_size(void)
+{
+ return 2;
+}
+#endif
+
#endif /* __ASM_ARCH_HARDWARE_K2L_H */
diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c
index 7d1709c880af..ca668a7c6902 100644
--- a/board/ti/ks2_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -146,9 +146,7 @@ int ft_board_setup(void *blob, bd_t *bd)
ddr3a_size = 0;
if (lpae) {
- env = getenv("ddr3a_size");
- if (env)
- ddr3a_size = simple_strtol(env, NULL, 10);
+ ddr3a_size = ddr3_get_size();
if ((ddr3a_size != 8) && (ddr3a_size != 4))
ddr3a_size = 0;
}
--
2.7.0
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[U-Boot] [PATCH 5/6] ARM: keystone2: use SPD info to configure K2HK and K2E DDR3
From: Vitaly Andrianov
This commit replaces hard-coded EMIF and PHY DDR3 configurations for
predefined SODIMMs to a calculated configuration. The SODIMM parameters
are read from SODIMM's SPD and used to calculated the configuration.
The current commit supports calculation for DDR3 with 1600MHz and 1333MHz
only.
Signed-off-by: Vitaly Andrianov
Signed-off-by: Lokesh Vutla
Signed-off-by: Nishanth Menon
---
arch/arm/mach-keystone/Makefile| 2 +
arch/arm/mach-keystone/ddr3_spd.c | 456 +
arch/arm/mach-keystone/include/mach/ddr3.h | 8 +
board/ti/ks2_evm/Makefile | 4 +-
board/ti/ks2_evm/ddr3_cfg.c| 159 +-
board/ti/ks2_evm/ddr3_cfg.h| 11 +-
board/ti/ks2_evm/ddr3_k2e.c| 51 ++--
board/ti/ks2_evm/ddr3_k2hk.c | 97 +++---
include/configs/k2e_evm.h | 2 +
include/configs/k2hk_evm.h | 2 +
10 files changed, 532 insertions(+), 260 deletions(-)
create mode 100644 arch/arm/mach-keystone/ddr3_spd.c
diff --git a/arch/arm/mach-keystone/Makefile b/arch/arm/mach-keystone/Makefile
index ffd9eadb0a49..9713fe4d6858 100644
--- a/arch/arm/mach-keystone/Makefile
+++ b/arch/arm/mach-keystone/Makefile
@@ -13,3 +13,5 @@ obj-y += cmd_mon.o
obj-y += msmc.o
obj-y += ddr3.o cmd_ddr3.o
obj-y += keystone.o
+obj-$(CONFIG_K2E_EVM) += ddr3_spd.o
+obj-$(CONFIG_K2HK_EVM) += ddr3_spd.o
diff --git a/arch/arm/mach-keystone/ddr3_spd.c
b/arch/arm/mach-keystone/ddr3_spd.c
new file mode 100644
index ..b0768823f2eb
--- /dev/null
+++ b/arch/arm/mach-keystone/ddr3_spd.c
@@ -0,0 +1,456 @@
+/*
+ * Keystone2: DDR3 SPD configuration
+ *
+ * (C) Copyright 2015
+ * Texas Instruments Incorporated,
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include
+
+#include
+#include
+#include
+#include
+
+#ifdef DUMP_DDR_CONFIG
+static void dump_phy_config(struct ddr3_phy_config *ptr)
+{
+ printf("\npllcr 0x%08X\n", ptr->pllcr);
+ printf("pgcr1_mask 0x%08X\n", ptr->pgcr1_mask);
+ printf("pgcr1_val 0x%08X\n", ptr->pgcr1_val);
+ printf("ptr00x%08X\n", ptr->ptr0);
+ printf("ptr10x%08X\n", ptr->ptr1);
+ printf("ptr20x%08X\n", ptr->ptr2);
+ printf("ptr30x%08X\n", ptr->ptr3);
+ printf("ptr40x%08X\n", ptr->ptr4);
+ printf("dcr_mask0x%08X\n", ptr->dcr_mask);
+ printf("dcr_val 0x%08X\n", ptr->dcr_val);
+ printf("dtpr0 0x%08X\n", ptr->dtpr0);
+ printf("dtpr1 0x%08X\n", ptr->dtpr1);
+ printf("dtpr2 0x%08X\n", ptr->dtpr2);
+ printf("mr0 0x%08X\n", ptr->mr0);
+ printf("mr1 0x%08X\n", ptr->mr1);
+ printf("mr2 0x%08X\n", ptr->mr2);
+ printf("dtcr0x%08X\n", ptr->dtcr);
+ printf("pgcr2 0x%08X\n", ptr->pgcr2);
+ printf("zq0cr1 0x%08X\n", ptr->zq0cr1);
+ printf("zq1cr1 0x%08X\n", ptr->zq1cr1);
+ printf("zq2cr1 0x%08X\n", ptr->zq2cr1);
+ printf("pir_v1 0x%08X\n", ptr->pir_v1);
+ printf("pir_v2 0x%08X\n\n", ptr->pir_v2);
+};
+
+static void dump_emif_config(struct ddr3_emif_config *ptr)
+{
+ printf("\nsdcfg 0x%08X\n", ptr->sdcfg);
+ printf("sdtim1 0x%08X\n", ptr->sdtim1);
+ printf("sdtim2 0x%08X\n", ptr->sdtim2);
+ printf("sdtim3 0x%08X\n", ptr->sdtim3);
+ printf("sdtim4 0x%08X\n", ptr->sdtim4);
+ printf("zqcfg 0x%08X\n", ptr->zqcfg);
+ printf("sdrfc 0x%08X\n\n", ptr->sdrfc);
+};
+#endif
+
+#define TEMP NORMAL_TEMP
+#define VBUS_CLKPERIOD 1.875 /* Corresponds to vbus=533MHz, */
+#define PLLGS_VAL (4000.0 / VBUS_CLKPERIOD) /* 4 us */
+#define PLLPD_VAL (1000.0 / VBUS_CLKPERIOD) /* 1 us */
+#define PLLLOCK_VAL(10.0 / VBUS_CLKPERIOD) /* 100 us */
+#define PLLRST_VAL (9000.0 / VBUS_CLKPERIOD) /* 9 us */
+#define PHYRST_VAL 0x10
+#define DDR_TERM RZQ_4_TERM
+#define SDRAM_DRIVE RZQ_7_IMP
+#define DYN_ODT ODT_DISABLE
+
+enum srt {
+ NORMAL_TEMP,
+ EXTENDED_TEMP
+};
+
+enum out_impedance {
+ RZQ_6_IMP = 0,
+ RZQ_7_IMP
+};
+
+enum die_term {
+ ODT_DISABLE = 0,
+ RZQ_4_TERM,
+ RZQ_2_TERM,
+ RZQ_6_TERM,
+ RZQ_12_TERM,
+ RZQ_8_TERM
+};
+
+struct ddr3_sodimm {
+ u32 t_ck;
+ u32 freqsel;
+ u32 t_xp;
+ u32 t_cke;
+ u32 t_pllpd;
+ u32 t_pllgs;
+ u32 t_phyrst;
+ u32 t_plllock;
+ u32 t_pllrst;
+ u32 t_rfc;
+ u32 t_xs;
+ u32 t_dinit0;
+ u32 t_dinit1;
+ u32 t_dinit2;
+ u32 t_dinit3;
+ u32 t_rtp;
+ u32 t_wtr;
+ u32 t_rp;
+ u32 t_rcd;
+ u32 t_ras;
+ u32 t_rrd;
+ u32 t_rc;
+ u32 t_faw;
+ u32 t_mrd;
Re: [U-Boot] [PATCH 02/10] arm64: Make full va map code more dynamic
On 24.02.16 19:14, Stephen Warren wrote:
> On 02/24/2016 05:11 AM, Alexander Graf wrote:
>> The idea to generate our pages tables from an array of memory ranges
>> is very sound. However, instead of hard coding the code to create up
>> to 2 levels of 64k granule page tables, we really should just create
>> normal 4k page tables that allow us to set caching attributes on 2M
>> or 4k level later on.
>>
>> So this patch moves the full_va mapping code to 4k page size and
>> makes it fully flexible to dynamically create as many levels as
>> necessary for a map (including dynamic 1G/2M pages). It also adds
>> support to dynamically split a large map into smaller ones when
>> some code wants to set dcache attributes.
>>
>> With all this in place, there is very little reason to create your
>> own page tables in board specific files.
>>
>> Signed-off-by: Alexander Graf
>
>> +/*
>> + * This is a recursively called function to count the number of
>> + * page tables we need to cover a particular PTE range. If you
>> + * call this with level = -1 you basically get the full 48 bit
>> + * coverage.
>> + */
>> +static int count_required_pts(u64 addr, int level, u64 maxaddr)
>
> I think this looks correct now. Nits below if a respin is needed for
> other reasons.
>
>> +{
>> +int levelshift = level2shift(level);
>> +u64 levelsize = 1ULL << levelshift;
>> +u64 levelmask = levelsize - 1;
>> +u64 levelend = addr + levelsize;
>> +int r = 0;
>> +int i;
>> +bool is_level = false;
>
> I might suggest renaming that is_level_needed. It's not obvious to me
> exactly what the name "is_level" is intended to represent; the name
> seems to represent whether something (unspecified) is a level or not.
We're basically asking the function whether a PTE for address at
level would be an inval/block/level PTE. is_level marks it as a
level pte.
I could maybe rename this into pte_type and create an enum that is
either PTE_INVAL, PTE_BLOCK or PTE_LEVEL.
>
>> +
>> +for (i = 0; i < ARRAY_SIZE(mem_map); i++) {
>> +struct mm_region *map = &mem_map[i];
>> +u64 start = map->base;
>> +u64 end = start + map->size;
>> +
>> +/* Check if the PTE would overlap with the map */
>> +if (max(addr, start) <= min(levelend, end)) {
>> +start = max(addr, start);
>> +end = min(levelend, end);
>> +
>> +/* We need a sub-pt for this level */
>> +if ((start & levelmask) || (end & levelmask)) {
>> +is_level = true;
>> +break;
>> +}
>> +
>> +/* Lv0 can not do block PTEs, so do levels here too */
>> +if (level <= 0) {
>> +is_level = true;
>> +break;
>> +}
>> +}
>> +}
>> +
>> +/*
>> + * Block PTEs at this level are already covered by the parent page
>> + * table, so we only need to count sub page tables.
>> + */
>> +if (is_level) {
>> +int sublevel = level + 1;
>> +u64 sublevelsize = 1ULL << level2shift(sublevel);
>> +
>> +/* Account for the new sub page table ... */
>> +r = 1;
>
> "Account for the page table at /this/ level"? This may represent the
> top-level (0/1) page table, not just sub page tables. The sub-level
> accounting is via the recursive call to count_required_pts() I believe.
I think the easiest way to visualize what's going on is if we start with
level -1.
We basically ask the function at level -1 whether a PTE at level -1 (48
bits) would fit into a block PTE at level -1 (so the PTE spans all 48
bits) or whether we need to create a new level entry plus page table for it.
Obviously for all entries this resolves into a "yes, create a level PTE
entry and a new page table to point to". So at level=-1 we account for
the root page table which really is a "sub page table" here.
Then we recursively go through the address space that we cover, checking
whether a page fits into inval/block PTEs or we need to create page
tables for it as well.
So at level=0, we really are checking for PTEs that you'd have at
level=0 (38 bits). If the combination at level=0 results
in "level", we need to create a level=1 page table and walk through that
one again.
I agree that the logic seems backwards, but it's the only thing that I
could come up with that has low memory footprint (required to run from
SRAM).
Alex
Does the diff below make it more obvious? It's slightly more runtime
overhead because we set the PTE_BLOCK case as well, but maintainability
of the code wins vs speed imho :).
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 7236455..e8f2632 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -236,6 +236,12 @@ static void split_block(u64 *pte, int level)
set_pte_table(pte, new_table);
}
+enum pte_type {
+ PTE_INVAL,
+ PTE_BLOCK,
+ PTE_LEVEL,
+};
+
/*
* This is a recursive
Re: [U-Boot] [RFC PATCH v4 3/3] common: Fix load and entry addresses in FIT image
On 02/24/2016 04:30 PM, Simon Glass wrote:
> Hi York,
>
> On 24 February 2016 at 15:55, york sun wrote:
>> On 02/16/2016 08:02 AM, Simon Glass wrote:
>>> Hi York,
>>>
>>> On 12 February 2016 at 13:59, York Sun wrote:
FIT image supports more than 32 bits in addresses by using #address-cell
field. However the address length is not handled when parsing FIT images.
>>>
>>> nit: How about saying "fix this by adding support for 64-bit
>>> addresses" or similar
>>>
>>
>> Sure. I can fix that.
>>
Signed-off-by: York Sun
---
Changes in v4:
Separate ulong to phys_addr_t change to another patch.
Changes in v3:
Define PRIpa for host and target in common/image-fit.c so printf works
properly for 32-, 64-bit targets and host tools.
Changes in v2:
Make a common function for both load and entry addresses.
Simplify calculation of addresses in a similar way as fdtdec_get_number()
fdtdec_get_number() is not used, or too many files need to be included
and/or twisted for host tool
Continue to use %08llx for print format for load and entry addresses
because %pa does not always work for host tool (mkimage)
common/image-fit.c | 54
++--
1 file changed, 31 insertions(+), 23 deletions(-)
diff --git a/common/image-fit.c b/common/image-fit.c
index bfa76a2..c000475 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -433,7 +433,7 @@ void fit_image_print(const void *fit, int
image_noffset, const char *p)
if ((type == IH_TYPE_KERNEL) || (type == IH_TYPE_STANDALONE) ||
(type == IH_TYPE_RAMDISK)) {
- fit_image_get_entry(fit, image_noffset, &entry);
+ ret = fit_image_get_entry(fit, image_noffset, &entry);
printf("%s Entry Point: ", p);
if (ret)
printf("unavailable\n");
@@ -675,6 +675,34 @@ int fit_image_get_comp(const void *fit, int noffset,
uint8_t *comp)
return 0;
}
+static int fit_image_get_address(const void *fit, int noffset, char *name,
+ phys_addr_t *load)
+{
+ int len, cell_len;
+ const fdt32_t *cell;
+ unsigned long long load64 = 0;
+
+ cell = fdt_getprop(fit, noffset, name, &len);
+ if (cell == NULL) {
+ fit_get_debug(fit, noffset, name, len);
+ return -1;
+ }
+
+ if (len > sizeof(phys_addr_t)) {
+ printf("Unsupported %s address size\n", name);
+ return -1;
+ }
+
+ cell_len = len >> 2;
+ /* Use load64 to avoid compiling warning for 32-bit target */
+ while (cell_len--) {
+ load64 = (load64 << 32) | uimage_to_cpu(*cell);
+ cell++;
+ }
+ *load = (phys_addr_t)load64;
+
+ return 0;
+}
/**
* fit_image_get_load() - get load addr property for given component
image node
* @fit: pointer to the FIT format image header
@@ -690,17 +718,7 @@ int fit_image_get_comp(const void *fit, int noffset,
uint8_t *comp)
*/
int fit_image_get_load(const void *fit, int noffset, phys_addr_t *load)
{
- int len;
- const uint32_t *data;
-
- data = fdt_getprop(fit, noffset, FIT_LOAD_PROP, &len);
- if (data == NULL) {
- fit_get_debug(fit, noffset, FIT_LOAD_PROP, len);
- return -1;
- }
-
- *load = uimage_to_cpu(*data);
- return 0;
+ return fit_image_get_address(fit, noffset, FIT_LOAD_PROP, load);
>>>
>>> I think it would make sense to have your new fit_image_get_address()
>>> in one patch, and the enhancement to support more address sizes in
>>> another.
>>
>> The new fit_image_get_address() gets correct address. The rest of change is
>> to
>> use the new function. I don't think they can be separated. Maybe I don't
>> understand your comment.
>>
>> I am preparing a new version. Please comment on that if you still feel the
>> same.
>
> I mean:
>
> - patch 1: take the existing 32-bit-only code and put it in a new
> fit_image_get_address() functoin
> - patch 2: enhance your new function to support 64-bit
>
> At present you have these two things co-mingled which I don't think is ideal.
>
I see. Let me work on it.
York
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Re: [U-Boot] [PATCH v3] test/py: Add option to skip SPL signature checking
On 02/25/2016 06:58 AM, Michal Simek wrote: Provide user option to skip SPL signature verification for cases where u-boot is build with SPL support but full U-Boot is also verified without SPL. If you want to support this feature please add env__spl_skipped = True to your boardenv configuration file. For example Xilinx Zynq is using this feature where the same U-Boot binary is checked with SPL and without SPL(with FSBL). Acked-by: Stephen Warren ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Pull request: u-boot-spi/master
On Wednesday 24 February 2016 02:05 AM, Tom Rini wrote: > On Tue, Feb 23, 2016 at 04:19:01PM +0530, Jagan Teki wrote: > >> Hi Tom, >> >> Please pull this series. >> >> thanks! >> Jagan. >> >> The following changes since commit 595af9db2422fa5ae734cfe615415b17a5098f34: >> >> Merge branch 'master' of git://www.denx.de/git/u-boot-imx (2016-02-21 >> 07:56:16 -0500) >> >> are available in the git repository at: >> >> >> git://git.denx.de/u-boot-spi.git master >> >> for you to fetch changes up to 674f3609aad39f099a5c3605643a6be124504b96: >> >> spi: spi-uclass: Set slave wordlen with SPI_DEFAULT_WORDLEN (2016-02-23 >> 16:14:46 +0530) >> > > Applied to u-boot/master, thanks! > > Mugunthan, can you please test QSPI boot on J6 or J6Eco? My board isn't > behaving well and I couldn't walk Nishanth through doing it on his (or, > there's a problem..). Thanks! > Tom, I will do a qspi boot test tomorrow and update here. Regards Mugunthan V N ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 05/11] zymqmp: Replace home grown mmu code with generic table approach
Now that we have nice table driven page table creating code that gives
us everything we need, move to that.
Signed-off-by: Alexander Graf
---
v1 -> v2:
- Move mmu tables into board file
---
arch/arm/cpu/armv8/zynqmp/cpu.c | 217 +---
include/configs/xilinx_zynqmp.h | 2 +
2 files changed, 50 insertions(+), 169 deletions(-)
diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c
index c71f291..5dd3cd8 100644
--- a/arch/arm/cpu/armv8/zynqmp/cpu.c
+++ b/arch/arm/cpu/armv8/zynqmp/cpu.c
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
#include
#define ZYNQ_SILICON_VER_MASK 0xF000
@@ -15,6 +16,53 @@
DECLARE_GLOBAL_DATA_PTR;
+static struct mm_region zynqmp_mem_map[] = {
+ {
+ .base = 0x0UL,
+ .size = 0x8000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+PTE_BLOCK_INNER_SHARE
+ }, {
+ .base = 0x8000UL,
+ .size = 0x7000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+PTE_BLOCK_NON_SHARE |
+PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .base = 0xf800UL,
+ .size = 0x07e0UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+PTE_BLOCK_NON_SHARE |
+PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .base = 0xffe0UL,
+ .size = 0x0020UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+PTE_BLOCK_INNER_SHARE
+ }, {
+ .base = 0x4UL,
+ .size = 0x2UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+PTE_BLOCK_NON_SHARE |
+PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .base = 0x6UL,
+ .size = 0x8UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+PTE_BLOCK_INNER_SHARE
+ }, {
+ .base = 0xeUL,
+ .size = 0xf2UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+PTE_BLOCK_NON_SHARE |
+PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+struct mm_region *mem_map = zynqmp_mem_map;
+
static unsigned int zynqmp_get_silicon_version_secure(void)
{
u32 ver;
@@ -44,172 +92,3 @@ unsigned int zynqmp_get_silicon_version(void)
return ZYNQMP_CSU_VERSION_SILICON;
}
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-#include
-
-#define SECTION_SHIFT_L1 30UL
-#define SECTION_SHIFT_L2 21UL
-#define BLOCK_SIZE_L0 0x80UL
-#define BLOCK_SIZE_L1 (1 << SECTION_SHIFT_L1)
-#define BLOCK_SIZE_L2 (1 << SECTION_SHIFT_L2)
-
-#define TCR_TG1_4K (1 << 31)
-#define TCR_EPD1_DISABLE (1 << 23)
-#define ZYNQMO_VA_BITS 40
-#define ZYNQMP_TCR TCR_TG1_4K | \
- TCR_EPD1_DISABLE | \
- TCR_SHARED_OUTER | \
- TCR_SHARED_INNER | \
- TCR_IRGN_WBWA | \
- TCR_ORGN_WBWA | \
- TCR_T0SZ(ZYNQMO_VA_BITS)
-
-#define MEMORY_ATTRPMD_SECT_AF | PMD_SECT_INNER_SHARE |\
- PMD_ATTRINDX(MT_NORMAL) | \
- PMD_TYPE_SECT
-#define DEVICE_ATTRPMD_SECT_AF | PMD_SECT_PXN |\
- PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_NGNRNE) | \
- PMD_TYPE_SECT
-
-/* 4K size is required to place 512 entries in each level */
-#define TLB_TABLE_SIZE 0x1000
-
-struct attr_tbl {
- u32 num;
- u64 attr;
-};
-
-static struct attr_tbl attr_tbll1t0[4] = { {16, 0x0},
- {8, DEVICE_ATTR},
- {32, MEMORY_ATTR},
- {456, DEVICE_ATTR}
-};
-static struct attr_tbl attr_tbll2t3[4] = { {0x180, DEVICE_ATTR},
- {0x40, 0x0},
- {0x3F, DEVICE_ATTR},
- {0x1, MEMORY_ATTR}
-};
-
-/*
- * This mmu table looks as below
- * Level 0 table contains two entries to 512GB sizes. One is Level1 Table 0
- * and other Level1 Table1.
- * Level1 Table0 contains entries for each 1GB from 0 to 511GB.
- * Level1 Table1 contains entries for each 1GB from 512GB to 1TB.
- * Level2 Table0, Level2 Table1, Level2 Table2 and Level2 Table3 contains
- * entries for each 2MB starting from 0GB, 1GB, 2GB and 3GB respectively.
- */
-static void zynqmp_mmu_setup(void)
-{
- int el;
-
[U-Boot] [PATCH v3 08/11] dwmmc: Increase retry timeout
When enable dcache on HiKey, we're running into MMC command timeouts because our retry loop is now faster than the eMMC (or an external SD card) can answer. Increase the retry count to the same as the timeout value for status reports. The real fix is obviously to not base this whole thing on a cycle counter but on real wall time, but that would be slightly more intrusive. Signed-off-by: Alexander Graf --- drivers/mmc/dw_mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 909e3ca..7329f40 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -189,7 +189,7 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, data ? DIV_ROUND_UP(data->blocks, 8) : 0); int ret = 0, flags = 0, i; unsigned int timeout = 10; - u32 retry = 1; + u32 retry = 10; u32 mask, ctrl; ulong start = get_timer(0); struct bounce_buffer bbstate; -- 1.8.5.6 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 00/11] arm64: Unify MMU code v3
Howdy, Currently on arm64 there is a big pile of mess when it comes to MMU support and page tables. Each board does its own little thing and the generic code is pretty dumb and nobody actually uses it. This patch set tries to clean that up. After this series is applied, all boards except for the FSL Layerscape ones are converted to the new generic page table logic and have icache+dcache enabled. The new code always uses 4k page size. It dynamically allocates 1G or 2M pages for ranges that fit. When a dcache attribute request comes in that requires a smaller granularity than our previous allocation could fulfill, pages get automatically split. I have tested and verified the code works on HiKey (bare metal), vexpress64 (Foundation Model) and zynqmp (QEMU). The TX1 target is untested, but given the simplicity of the maps I doubt it'll break. ThunderX in theory should also work, but I haven't tested it. I would be very happy if people with access to those system could give the patch set a try. With this we're a big step closer to a good base line for EFI payload support, since we can now just require that all boards always have dcache enabled. I would also be incredibly happy if some Freescale people could look at their MMU code and try to unify it into the now cleaned up generic code. I don't think we're far off here. Alex v1 -> v2: - Fix comment for create_table() - Rework page table size calculation - Move mmu tables into board files - New patch: thunderx: Move mmu table into board file v2 -> v3: - Move PGTABLE_SIZE out of the ASSEMBLY section - Run pte splitting code in separate page table - Replace is_level in count_required_pts with more obvious pte_type - New patch: arm64: Disable TTBR1 maps in EL1 Alexander Graf (11): thunderx: Calculate TCR dynamically arm64: Disable TTBR1 maps in EL1 arm64: Make full va map code more dynamic thunderx: Move mmu table into board file zymqmp: Replace home grown mmu code with generic table approach tegra: Replace home grown mmu code with generic table approach vexpress64: Add MMU tables dwmmc: Increase retry timeout hikey: Add MMU tables arm64: Remove non-full-va map code arm64: Only allow dcache disabled in SPL builds arch/arm/cpu/armv8/cache.S | 54 +++ arch/arm/cpu/armv8/cache_v8.c | 546 +++-- arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 37 +- arch/arm/cpu/armv8/zynqmp/cpu.c| 217 +++--- arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 94 ++--- arch/arm/include/asm/armv8/mmu.h | 123 ++ arch/arm/include/asm/global_data.h | 7 +- arch/arm/include/asm/system.h | 12 +- arch/arm/mach-tegra/arm64-mmu.c| 132 +- board/armltd/vexpress64/vexpress64.c | 21 + board/cavium/thunderx/thunderx.c | 24 ++ board/hisilicon/hikey/hikey.c | 21 + doc/README.arm64 | 20 - drivers/mmc/dw_mmc.c | 2 +- include/configs/hikey.h| 4 +- include/configs/thunderx_88xx.h| 30 -- include/configs/vexpress_aemv8a.h | 5 +- 17 files changed, 733 insertions(+), 616 deletions(-) -- 1.8.5.6 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 09/11] hikey: Add MMU tables
The hikey runs with dcache disabled today. There really should be no reason
not to use caches on AArch64, so let's add MMU definitions and enable the
dcache.
Signed-off-by: Alexander Graf
---
v1 -> v2:
- Move tables to .c file
---
board/hisilicon/hikey/hikey.c | 21 +
include/configs/hikey.h | 5 +++--
2 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/board/hisilicon/hikey/hikey.c b/board/hisilicon/hikey/hikey.c
index c4ae40b..1edc807 100644
--- a/board/hisilicon/hikey/hikey.c
+++ b/board/hisilicon/hikey/hikey.c
@@ -19,6 +19,7 @@
#include
#include
#include
+#include
/*TODO drop this table in favour of device tree */
static const struct hikey_gpio_platdata hi6220_gpio[] = {
@@ -87,6 +88,26 @@ U_BOOT_DEVICE(hikey_seriala) = {
.platdata = &serial_platdata,
};
+static struct mm_region hikey_mem_map[] = {
+ {
+ .base = 0x0UL,
+ .size = 0x8000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+PTE_BLOCK_INNER_SHARE
+ }, {
+ .base = 0x8000UL,
+ .size = 0x8000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+PTE_BLOCK_NON_SHARE |
+PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = hikey_mem_map;
+
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_uart_init(void)
{
diff --git a/include/configs/hikey.h b/include/configs/hikey.h
index 796861e..d33dcef 100644
--- a/include/configs/hikey.h
+++ b/include/configs/hikey.h
@@ -21,8 +21,9 @@
#define CONFIG_SUPPORT_RAW_INITRD
-/* Cache Definitions */
-#define CONFIG_SYS_DCACHE_OFF
+/* MMU Definitions */
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_SYS_FULL_VA
#define CONFIG_IDENT_STRING"hikey"
--
1.8.5.6
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[U-Boot] [PATCH v3 03/11] arm64: Make full va map code more dynamic
The idea to generate our pages tables from an array of memory ranges
is very sound. However, instead of hard coding the code to create up
to 2 levels of 64k granule page tables, we really should just create
normal 4k page tables that allow us to set caching attributes on 2M
or 4k level later on.
So this patch moves the full_va mapping code to 4k page size and
makes it fully flexible to dynamically create as many levels as
necessary for a map (including dynamic 1G/2M pages). It also adds
support to dynamically split a large map into smaller ones when
some code wants to set dcache attributes.
With all this in place, there is very little reason to create your
own page tables in board specific files.
Signed-off-by: Alexander Graf
---
v1 -> v2:
- Fix comment for create_table()
- Rework page table size calculation
- s/DPRINTF/debug/g
- Improve panic messages
v2 -> v3:
- Move PGTABLE_SIZE out of the ASSEMBLY section
- Run pte splitting code in separate page table
- Replace is_level in count_required_pts with more obvious pte_type
---
arch/arm/cpu/armv8/cache.S | 54 +
arch/arm/cpu/armv8/cache_v8.c | 448 -
arch/arm/include/asm/armv8/mmu.h | 68 +++---
arch/arm/include/asm/global_data.h | 5 +-
arch/arm/include/asm/system.h | 14 +-
include/configs/thunderx_88xx.h| 14 +-
6 files changed, 495 insertions(+), 108 deletions(-)
diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S
index ab8c089..a9f4fec 100644
--- a/arch/arm/cpu/armv8/cache.S
+++ b/arch/arm/cpu/armv8/cache.S
@@ -10,6 +10,7 @@
#include
#include
#include
+#include
#include
/*
@@ -160,3 +161,56 @@ ENTRY(__asm_flush_l3_cache)
ret
ENDPROC(__asm_flush_l3_cache)
.weak __asm_flush_l3_cache
+
+/*
+ * void __asm_switch_ttbr(ulong new_ttbr)
+ *
+ * Safely switches to a new page table.
+ */
+ENTRY(__asm_switch_ttbr)
+ /* x2 = SCTLR (alive throghout the function) */
+ switch_el x4, 3f, 2f, 1f
+3: mrs x2, sctlr_el3
+ b 0f
+2: mrs x2, sctlr_el2
+ b 0f
+1: mrs x2, sctlr_el1
+0:
+
+ /* Unset CR_M | CR_C | CR_I from SCTLR to disable all caches */
+ movnx1, #(CR_M | CR_C | CR_I)
+ and x1, x2, x1
+ switch_el x4, 3f, 2f, 1f
+3: msr sctlr_el3, x1
+ b 0f
+2: msr sctlr_el2, x1
+ b 0f
+1: msr sctlr_el1, x1
+0: isb
+
+ /* This call only clobbers x30 (lr) and x9 (unused) */
+ mov x3, x30
+ bl __asm_invalidate_tlb_all
+
+ /* From here on we're running safely with caches disabled */
+
+ /* Set TTBR to our first argument */
+ switch_el x4, 3f, 2f, 1f
+3: msr ttbr0_el3, x0
+ b 0f
+2: msr ttbr0_el2, x0
+ b 0f
+1: msr ttbr0_el1, x0
+0: isb
+
+ /* Restore original SCTLR and thus enable caches again */
+ switch_el x4, 3f, 2f, 1f
+3: msr sctlr_el3, x2
+ b 0f
+2: msr sctlr_el2, x2
+ b 0f
+1: msr sctlr_el1, x2
+0: isb
+
+ ret x3
+ENDPROC(__asm_switch_ttbr)
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index d92f2d1..41bb874 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -2,6 +2,9 @@
* (C) Copyright 2013
* David Feng
*
+ * (C) Copyright 2016
+ * Alexander Graf
+ *
* SPDX-License-Identifier:GPL-2.0+
*/
@@ -13,31 +16,28 @@ DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SYS_DCACHE_OFF
-#ifdef CONFIG_SYS_FULL_VA
-static void set_ptl1_entry(u64 index, u64 ptl2_entry)
-{
- u64 *pgd = (u64 *)gd->arch.tlb_addr;
- u64 value;
-
- value = ptl2_entry | PTL1_TYPE_TABLE;
- pgd[index] = value;
-}
-
-static void set_ptl2_block(u64 ptl1, u64 bfn, u64 address, u64 memory_attrs)
-{
- u64 *pmd = (u64 *)ptl1;
- u64 value;
-
- value = address | PTL2_TYPE_BLOCK | PTL2_BLOCK_AF;
- value |= memory_attrs;
- pmd[bfn] = value;
-}
+/*
+ * With 4k page granule, a virtual address is split into 4 lookup parts
+ * spanning 9 bits each:
+ *
+ *___
+ * | | | | | | |
+ * | 0 | Lv0 | Lv1 | Lv2 | Lv3 | off |
+ * |___|___|___|___|___|___|
+ * 63-48 47-39 38-30 29-21 20-12 11-00
+ *
+ * maskpage size
+ *
+ *Lv0: FF80 --
+ *Lv1: 7FC000 1G
+ *Lv2: 3FE0 2M
+ *Lv3: 1FF000 4K
+ *off: FFF
+ */
+#ifdef CONFIG_SYS_FULL_VA
static struct mm_region mem_map[] = CONFIG_SYS_MEM_MAP;
-#define PTL1_ENTRIES CONFIG_SYS_PTL1_ENTRIES
-#define PTL2_ENTRIES CONFIG_SYS_PTL2_ENTRIES
-
static u64 get_tcr(int el, u64 *pips, u64 *pva_bits)
{
u64 max_addr = 0;
@@ -79,8 +79,8 @@ static u64 get_tcr(int el, u64 *pips, u64 *pv
[U-Boot] [PATCH v3 07/11] vexpress64: Add MMU tables
There's no good excuse for running with caches disabled on AArch64,
so let's just move the vexpress64 target to enable the MMU and run
with caches on.
Signed-off-by: Alexander Graf
---
v1 -> v2:
- Move tables to .c file
---
board/armltd/vexpress64/vexpress64.c | 21 +
include/configs/vexpress_aemv8a.h| 6 +++---
2 files changed, 24 insertions(+), 3 deletions(-)
diff --git a/board/armltd/vexpress64/vexpress64.c
b/board/armltd/vexpress64/vexpress64.c
index 6efc8c1..973b579 100644
--- a/board/armltd/vexpress64/vexpress64.c
+++ b/board/armltd/vexpress64/vexpress64.c
@@ -14,6 +14,7 @@
#include
#include
#include "pcie.h"
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -28,6 +29,26 @@ U_BOOT_DEVICE(vexpress_serials) = {
.platdata = &serial_platdata,
};
+static struct mm_region vexpress64_mem_map[] = {
+ {
+ .base = 0x0UL,
+ .size = 0x8000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+PTE_BLOCK_NON_SHARE |
+PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .base = 0x8000UL,
+ .size = 0xff8000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+PTE_BLOCK_INNER_SHARE
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = vexpress64_mem_map;
+
/* This function gets replaced by platforms supporting PCIe.
* The replacement function, eg. on Juno, initialises the PCIe bus.
*/
diff --git a/include/configs/vexpress_aemv8a.h
b/include/configs/vexpress_aemv8a.h
index 133041b..ddb9848 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -19,9 +19,9 @@
#define CONFIG_SUPPORT_RAW_INITRD
-/* Cache Definitions */
-#define CONFIG_SYS_DCACHE_OFF
-#define CONFIG_SYS_ICACHE_OFF
+/* MMU Definitions */
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_SYS_FULL_VA
#define CONFIG_IDENT_STRING" vexpress_aemv8a"
#define CONFIG_BOOTP_VCI_STRING"U-Boot.armv8.vexpress_aemv8a"
--
1.8.5.6
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[U-Boot] [PATCH v3 04/11] thunderx: Move mmu table into board file
The MMU range table can vary depending on things we may only find
out at runtime. While the very simple ThunderX variant does not
change, other boards will, so move the definition from a static
entry in a header file to the board file.
Signed-off-by: Alexander Graf
---
arch/arm/cpu/armv8/cache_v8.c| 8 +++-
arch/arm/include/asm/armv8/mmu.h | 2 ++
board/cavium/thunderx/thunderx.c | 24
include/configs/thunderx_88xx.h | 11 ---
4 files changed, 29 insertions(+), 16 deletions(-)
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 41bb874..f745545 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -36,8 +36,6 @@ DECLARE_GLOBAL_DATA_PTR;
*/
#ifdef CONFIG_SYS_FULL_VA
-static struct mm_region mem_map[] = CONFIG_SYS_MEM_MAP;
-
static u64 get_tcr(int el, u64 *pips, u64 *pva_bits)
{
u64 max_addr = 0;
@@ -46,7 +44,7 @@ static u64 get_tcr(int el, u64 *pips, u64 *pva_bits)
int i;
/* Find the largest address we need to support */
- for (i = 0; i < ARRAY_SIZE(mem_map); i++)
+ for (i = 0; mem_map[i].size || mem_map[i].attrs; i++)
max_addr = max(max_addr, mem_map[i].base + mem_map[i].size);
/* Calculate the maximum physical (and thus virtual) address */
@@ -261,7 +259,7 @@ static int count_required_pts(u64 addr, int level, u64
maxaddr)
int i;
enum pte_type pte_type = PTE_INVAL;
- for (i = 0; i < ARRAY_SIZE(mem_map); i++) {
+ for (i = 0; mem_map[i].size || mem_map[i].attrs; i++) {
struct mm_region *map = &mem_map[i];
u64 start = map->base;
u64 end = start + map->size;
@@ -359,7 +357,7 @@ static void setup_pgtables(void)
create_table();
/* Now add all MMU table entries one after another to the table */
- for (i = 0; i < ARRAY_SIZE(mem_map); i++)
+ for (i = 0; mem_map[i].size || mem_map[i].attrs; i++)
add_map(&mem_map[i]);
/* Create the same thing once more for our emergency page table */
diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index 1c490dc..06126c8 100644
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -203,6 +203,8 @@ struct mm_region {
u64 size;
u64 attrs;
};
+
+extern struct mm_region *mem_map;
#endif
#endif /* _ASM_ARMV8_MMU_H_ */
diff --git a/board/cavium/thunderx/thunderx.c b/board/cavium/thunderx/thunderx.c
index b926767..9131a38 100644
--- a/board/cavium/thunderx/thunderx.c
+++ b/board/cavium/thunderx/thunderx.c
@@ -10,6 +10,7 @@
#include
#include
+#include
#if !CONFIG_IS_ENABLED(OF_CONTROL)
#include
@@ -42,6 +43,29 @@ U_BOOT_DEVICE(thunderx_serial1) = {
DECLARE_GLOBAL_DATA_PTR;
+static struct mm_region thunderx_mem_map[] = {
+ {
+ .base = 0xUL,
+ .size = 0x400UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE,
+ }, {
+ .base = 0x8000UL,
+ .size = 0x400UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+PTE_BLOCK_NON_SHARE,
+ }, {
+ .base = 0x8400UL,
+ .size = 0x400UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+PTE_BLOCK_NON_SHARE,
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = thunderx_mem_map;
+
int board_init(void)
{
return 0;
diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h
index 20b25f7..64e4616 100644
--- a/include/configs/thunderx_88xx.h
+++ b/include/configs/thunderx_88xx.h
@@ -26,17 +26,6 @@
#define CONFIG_SYS_LOWMEM_BASE MEM_BASE
-#define CONFIG_SYS_MEM_MAP {{0xUL, 0x400UL, \
- PTE_BLOCK_MEMTYPE(MT_NORMAL) | \
- PTE_BLOCK_NON_SHARE}, \
-{0x8000UL, 0x400UL, \
- PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
\
- PTE_BLOCK_NON_SHARE}, \
-{0x8400UL, 0x400UL, \
- PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
\
- PTE_BLOCK_NON_SHARE}, \
- }
-
#define CONFIG_SYS_MEM_MAP_SIZE3
#define CONFIG_SYS_VA_BITS 48
--
1.8.5.6
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[U-Boot] [PATCH v3 10/11] arm64: Remove non-full-va map code
By now the code to only have a single page table level with 64k page
size and 42 bit address space is no longer used by any board in tree,
so we can safely remove it.
To clean up code, move the layerscape mmu code to the new defines,
removing redundant field definitions.
Signed-off-by: Alexander Graf
---
v1 -> v2:
- Add layerscape empty mmu table in .c file
---
arch/arm/cpu/armv8/cache_v8.c | 90
arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 37 --
arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 94 +-
arch/arm/include/asm/armv8/mmu.h | 66 +-
arch/arm/include/asm/global_data.h | 2 +-
arch/arm/include/asm/system.h | 12 ++--
doc/README.arm64 | 20 --
include/configs/hikey.h| 1 -
include/configs/tegra210-common.h | 2 -
include/configs/thunderx_88xx.h| 14
include/configs/vexpress_aemv8a.h | 1 -
include/configs/xilinx_zynqmp.h| 2 -
12 files changed, 85 insertions(+), 256 deletions(-)
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index f745545..1c76a15 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -35,7 +35,6 @@ DECLARE_GLOBAL_DATA_PTR;
*off: FFF
*/
-#ifdef CONFIG_SYS_FULL_VA
static u64 get_tcr(int el, u64 *pips, u64 *pva_bits)
{
u64 max_addr = 0;
@@ -381,38 +380,11 @@ static void setup_all_pgtables(void)
gd->arch.tlb_addr = tlb_addr;
}
-#else
-
-inline void set_pgtable_section(u64 *page_table, u64 index, u64 section,
-u64 memory_type, u64 attribute)
-{
- u64 value;
-
- value = section | PMD_TYPE_SECT | PMD_SECT_AF;
- value |= PMD_ATTRINDX(memory_type);
- value |= attribute;
- page_table[index] = value;
-}
-
-inline void set_pgtable_table(u64 *page_table, u64 index, u64 *table_addr)
-{
- u64 value;
-
- value = (u64)table_addr | PMD_TYPE_TABLE;
- page_table[index] = value;
-}
-#endif
-
/* to activate the MMU we need to set up virtual memory */
__weak void mmu_setup(void)
{
-#ifndef CONFIG_SYS_FULL_VA
- bd_t *bd = gd->bd;
- u64 *page_table = (u64 *)gd->arch.tlb_addr, i, j;
-#endif
int el;
-#ifdef CONFIG_SYS_FULL_VA
/* Set up page tables only once */
if (!gd->arch.tlb_fillptr)
setup_all_pgtables();
@@ -420,40 +392,6 @@ __weak void mmu_setup(void)
el = current_el();
set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
MEMORY_ATTRIBUTES);
-#else
- /* Setup an identity-mapping for all spaces */
- for (i = 0; i < (PGTABLE_SIZE >> 3); i++) {
- set_pgtable_section(page_table, i, i << SECTION_SHIFT,
- MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE);
- }
-
- /* Setup an identity-mapping for all RAM space */
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- ulong start = bd->bi_dram[i].start;
- ulong end = bd->bi_dram[i].start + bd->bi_dram[i].size;
- for (j = start >> SECTION_SHIFT;
-j < end >> SECTION_SHIFT; j++) {
- set_pgtable_section(page_table, j, j << SECTION_SHIFT,
- MT_NORMAL, PMD_SECT_NON_SHARE);
- }
- }
-
- /* load TTBR0 */
- el = current_el();
- if (el == 1) {
- set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
- TCR_EL1_RSVD | TCR_FLAGS | TCR_EL1_IPS_BITS,
- MEMORY_ATTRIBUTES);
- } else if (el == 2) {
- set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
- TCR_EL2_RSVD | TCR_FLAGS | TCR_EL2_IPS_BITS,
- MEMORY_ATTRIBUTES);
- } else {
- set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
- TCR_EL3_RSVD | TCR_FLAGS | TCR_EL3_IPS_BITS,
- MEMORY_ATTRIBUTES);
- }
-#endif
/* enable the mmu */
set_sctlr(get_sctlr() | CR_M);
@@ -539,33 +477,6 @@ u64 *__weak arch_get_page_table(void) {
return NULL;
}
-#ifndef CONFIG_SYS_FULL_VA
-void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
-enum dcache_option option)
-{
- u64 *page_table = arch_get_page_table();
- u64 upto, end;
-
- if (page_table == NULL)
- return;
-
- end = ALIGN(start + size, (1 << MMU_SECTION_SHIFT)) >>
- MMU_SECTION_SHIFT;
- start = start >> MMU_SECTION_SHIFT;
- for (upto = start; upto < end; upto++) {
- page_table[upto] &= ~PMD_ATTRINDX_MASK;
- page_table[upto] |= PMD_ATTRINDX(option);
-
[U-Boot] [PATCH v3 06/11] tegra: Replace home grown mmu code with generic table approach
Now that we have nice table driven page table creating code that gives
us everything we need, move to that.
Signed-off-by: Alexander Graf
---
v1 -> v2:
- Move mmu tables into .c file
---
arch/arm/mach-tegra/arm64-mmu.c | 132 +-
include/configs/tegra210-common.h | 2 +
2 files changed, 19 insertions(+), 115 deletions(-)
diff --git a/arch/arm/mach-tegra/arm64-mmu.c b/arch/arm/mach-tegra/arm64-mmu.c
index c227652..501c4f0 100644
--- a/arch/arm/mach-tegra/arm64-mmu.c
+++ b/arch/arm/mach-tegra/arm64-mmu.c
@@ -12,120 +12,22 @@
#include
#include
-DECLARE_GLOBAL_DATA_PTR;
-
-#define SECTION_SHIFT_L1 30UL
-#define SECTION_SHIFT_L2 21UL
-#define BLOCK_SIZE_L0 0x80UL
-#define BLOCK_SIZE_L1 (1 << SECTION_SHIFT_L1)
-#define BLOCK_SIZE_L2 (1 << SECTION_SHIFT_L2)
-
-#define TCR_TG1_4K (1 << 31)
-#define TCR_EPD1_DISABLE (1 << 23)
-#define TEGRA_VA_BITS 40
-#define TEGRA_TCR TCR_TG1_4K | \
- TCR_EPD1_DISABLE | \
- TCR_SHARED_OUTER | \
- TCR_SHARED_INNER | \
- TCR_IRGN_WBWA | \
- TCR_ORGN_WBWA | \
- TCR_T0SZ(TEGRA_VA_BITS)
-
-#define MEMORY_ATTRPMD_SECT_AF | PMD_SECT_INNER_SHARE |\
- PMD_ATTRINDX(MT_NORMAL) | \
- PMD_TYPE_SECT
-#define DEVICE_ATTRPMD_SECT_AF | PMD_SECT_PXN |\
- PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_NGNRNE) | \
- PMD_TYPE_SECT
-
-/* 4K size is required to place 512 entries in each level */
-#define TLB_TABLE_SIZE 0x1000
-
-/*
- * This mmu table looks as below
- * Level 0 table contains two entries to 512GB sizes. One is Level1 Table 0
- * and other Level1 Table1.
- * Level1 Table0 contains entries for each 1GB from 0 to 511GB.
- * Level1 Table1 contains entries for each 1GB from 512GB to 1TB.
- * Level2 Table0, Level2 Table1, Level2 Table2 and Level2 Table3 contains
- * entries for each 2MB starting from 0GB, 1GB, 2GB and 3GB respectively.
- */
-void mmu_setup(void)
-{
- int el;
- u64 i, section_l1t0, section_l1t1;
- u64 section_l2t0, section_l2t1, section_l2t2, section_l2t3;
- u64 *level0_table = (u64 *)gd->arch.tlb_addr;
- u64 *level1_table_0 = (u64 *)(gd->arch.tlb_addr + TLB_TABLE_SIZE);
- u64 *level1_table_1 = (u64 *)(gd->arch.tlb_addr + (2 * TLB_TABLE_SIZE));
- u64 *level2_table_0 = (u64 *)(gd->arch.tlb_addr + (3 * TLB_TABLE_SIZE));
- u64 *level2_table_1 = (u64 *)(gd->arch.tlb_addr + (4 * TLB_TABLE_SIZE));
- u64 *level2_table_2 = (u64 *)(gd->arch.tlb_addr + (5 * TLB_TABLE_SIZE));
- u64 *level2_table_3 = (u64 *)(gd->arch.tlb_addr + (6 * TLB_TABLE_SIZE));
-
- /* Invalidate all table entries */
- memset(level0_table, 0, PGTABLE_SIZE);
-
- level0_table[0] =
- (u64)level1_table_0 | PMD_TYPE_TABLE;
- level0_table[1] =
- (u64)level1_table_1 | PMD_TYPE_TABLE;
-
- /*
-* set level 1 table 0, covering 0 to 512GB
-* set level 1 table 1, covering 512GB to 1TB
-*/
- section_l1t0 = 0;
- section_l1t1 = BLOCK_SIZE_L0;
-
- for (i = 0; i < 512; i++) {
- level1_table_0[i] = section_l1t0;
- if (i >= 4)
- level1_table_0[i] |= MEMORY_ATTR;
- level1_table_1[i] = section_l1t1;
- level1_table_1[i] |= MEMORY_ATTR;
- section_l1t0 += BLOCK_SIZE_L1;
- section_l1t1 += BLOCK_SIZE_L1;
+static struct mm_region tegra_mem_map[] = {
+ {
+ .base = 0x0UL,
+ .size = 0x8000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+PTE_BLOCK_NON_SHARE |
+PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .base = 0x8000UL,
+ .size = 0xff8000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+PTE_BLOCK_INNER_SHARE
+ }, {
+ /* List terminator */
+ 0,
}
+};
- level1_table_0[0] =
- (u64)level2_table_0 | PMD_TYPE_TABLE;
- level1_table_0[1] =
- (u64)level2_table_1 | PMD_TYPE_TABLE;
- level1_table_0[2] =
- (u64)level2_table_2 | PMD_TYPE_TABLE;
- level1_table_0[3] =
- (u64)level2_table_3 | PMD_TYPE_TABLE;
-
- section_l2t0 = 0;
- section_l2t1 = section_l2t0 + BLOCK_SIZE_L1; /* 1GB */
- section_l2t2 = section_l2t1 + BLOCK_SIZE_L1; /* 2GB */
- section_l2t3 = section_l2t2 + BLOCK_SIZE_L1; /* 3GB */
-
- for (i = 0; i < 512; i++) {
- level2_table_0[i] = section_l2t0 | DEVICE_ATTR;
- level2_table_1[i] = section_l2t1 | DEVICE_ATTR;
-
[U-Boot] [PATCH v3 01/11] thunderx: Calculate TCR dynamically
Based on the memory map we can determine a lot of hard coded fields of
TCR, like the maximum VA and max PA we want to support. Calculate those
dynamically to reduce the chance for pit falls.
Signed-off-by: Alexander Graf
---
arch/arm/cpu/armv8/cache_v8.c| 59 +++-
arch/arm/include/asm/armv8/mmu.h | 6 +---
include/configs/thunderx_88xx.h | 3 --
3 files changed, 59 insertions(+), 9 deletions(-)
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 71f0020..9229532 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -38,6 +38,58 @@ static struct mm_region mem_map[] = CONFIG_SYS_MEM_MAP;
#define PTL1_ENTRIES CONFIG_SYS_PTL1_ENTRIES
#define PTL2_ENTRIES CONFIG_SYS_PTL2_ENTRIES
+static u64 get_tcr(int el, u64 *pips, u64 *pva_bits)
+{
+ u64 max_addr = 0;
+ u64 ips, va_bits;
+ u64 tcr;
+ int i;
+
+ /* Find the largest address we need to support */
+ for (i = 0; i < ARRAY_SIZE(mem_map); i++)
+ max_addr = max(max_addr, mem_map[i].base + mem_map[i].size);
+
+ /* Calculate the maximum physical (and thus virtual) address */
+ if (max_addr > (1ULL << 44)) {
+ ips = 5;
+ va_bits = 48;
+ } else if (max_addr > (1ULL << 42)) {
+ ips = 4;
+ va_bits = 44;
+ } else if (max_addr > (1ULL << 40)) {
+ ips = 3;
+ va_bits = 42;
+ } else if (max_addr > (1ULL << 36)) {
+ ips = 2;
+ va_bits = 40;
+ } else if (max_addr > (1ULL << 32)) {
+ ips = 1;
+ va_bits = 36;
+ } else {
+ ips = 0;
+ va_bits = 32;
+ }
+
+ if (el == 1) {
+ tcr = TCR_EL1_RSVD | (ips << 32);
+ } else if (el == 2) {
+ tcr = TCR_EL2_RSVD | (ips << 16);
+ } else {
+ tcr = TCR_EL3_RSVD | (ips << 16);
+ }
+
+ /* PTWs cacheable, inner/outer WBWA and inner shareable */
+ tcr |= TCR_TG0_64K | TCR_SHARED_INNER | TCR_ORGN_WBWA | TCR_IRGN_WBWA;
+ tcr |= TCR_T0SZ(VA_BITS);
+
+ if (pips)
+ *pips = ips;
+ if (pva_bits)
+ *pva_bits = va_bits;
+
+ return tcr;
+}
+
static void setup_pgtables(void)
{
int l1_e, l2_e;
@@ -110,6 +162,10 @@ __weak void mmu_setup(void)
/* Set up page tables only on BSP */
if (coreid == BSP_COREID)
setup_pgtables();
+
+ el = current_el();
+ set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
+ MEMORY_ATTRIBUTES);
#else
/* Setup an identity-mapping for all spaces */
for (i = 0; i < (PGTABLE_SIZE >> 3); i++) {
@@ -128,7 +184,6 @@ __weak void mmu_setup(void)
}
}
-#endif
/* load TTBR0 */
el = current_el();
if (el == 1) {
@@ -144,6 +199,8 @@ __weak void mmu_setup(void)
TCR_EL3_RSVD | TCR_FLAGS | TCR_EL3_IPS_BITS,
MEMORY_ATTRIBUTES);
}
+#endif
+
/* enable the mmu */
set_sctlr(get_sctlr() | CR_M);
}
diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index 897f010..39ff745 100644
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -159,11 +159,6 @@
#define TCR_EL1_IPS_BITS (UL(3) << 32) /* 42 bits physical address */
#define TCR_EL2_IPS_BITS (3 << 16) /* 42 bits physical address */
#define TCR_EL3_IPS_BITS (3 << 16) /* 42 bits physical address */
-#else
-#define TCR_EL1_IPS_BITS CONFIG_SYS_TCR_EL1_IPS_BITS
-#define TCR_EL2_IPS_BITS CONFIG_SYS_TCR_EL2_IPS_BITS
-#define TCR_EL3_IPS_BITS CONFIG_SYS_TCR_EL3_IPS_BITS
-#endif
/* PTWs cacheable, inner/outer WBWA and inner shareable */
#define TCR_FLAGS (TCR_TG0_64K | \
@@ -171,6 +166,7 @@
TCR_ORGN_WBWA | \
TCR_IRGN_WBWA | \
TCR_T0SZ(VA_BITS))
+#endif
#define TCR_EL1_RSVD (1 << 31)
#define TCR_EL2_RSVD (1 << 31 | 1 << 23)
diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h
index cece4dd..b9f93ad 100644
--- a/include/configs/thunderx_88xx.h
+++ b/include/configs/thunderx_88xx.h
@@ -50,9 +50,6 @@
#define CONFIG_SYS_PGTABLE_SIZE\
((CONFIG_SYS_PTL1_ENTRIES + \
CONFIG_SYS_MEM_MAP_SIZE * CONFIG_SYS_PTL2_ENTRIES) * 8)
-#define CONFIG_SYS_TCR_EL1_IPS_BITS(5UL << 32)
-#define CONFIG_SYS_TCR_EL2_IPS_BITS(5 << 16)
-#define CONFIG_SYS_TCR_EL3_IPS_BITS(5 << 16)
/* Link Definitions */
#define CONFIG_SYS_TEXT_BASE 0x0050
--
1.8.5.6
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[U-Boot] [PATCH v3 11/11] arm64: Only allow dcache disabled in SPL builds
Now that we have an easy way to describe memory regions and enable the MMU,
there really shouldn't be anything holding people back from running with
caches enabled on AArch64. To make sure people catch early if they're missing
on the caching fun, give them a compile error.
Signed-off-by: Alexander Graf
---
arch/arm/cpu/armv8/cache_v8.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 1c76a15..e8f2632 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -561,6 +561,15 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start,
size_t size,
#else /* CONFIG_SYS_DCACHE_OFF */
+/*
+ * For SPL builds, we may want to not have dcache enabled. Any real U-Boot
+ * running however really wants to have dcache and the MMU active. Check that
+ * everything is sane and give the developer a hint if it isn't.
+ */
+#ifndef CONFIG_SPL_BUILD
+#error Please describe your MMU layout in CONFIG_SYS_MEM_MAP and enable dcache.
+#endif
+
void invalidate_dcache_all(void)
{
}
--
1.8.5.6
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[U-Boot] [PATCH v3 02/11] arm64: Disable TTBR1 maps in EL1
When running in EL1, AArch64 knows two page table maps. One with addresses
that start with all zeros (TTBR0) and one with addresses that start with all
ones (TTBR1).
In U-Boot we don't care about the high up maps, so just disable them to ensure
we don't walk an invalid page table by accident.
Reported-by: Mark Rutland
Signed-off-by: Alexander Graf
---
arch/arm/cpu/armv8/cache_v8.c| 2 +-
arch/arm/include/asm/armv8/mmu.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 9229532..d92f2d1 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -71,7 +71,7 @@ static u64 get_tcr(int el, u64 *pips, u64 *pva_bits)
}
if (el == 1) {
- tcr = TCR_EL1_RSVD | (ips << 32);
+ tcr = TCR_EL1_RSVD | (ips << 32) | TCR_EPD1_DISABLE;
} else if (el == 2) {
tcr = TCR_EL2_RSVD | (ips << 16);
} else {
diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index 39ff745..0080ae6 100644
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -154,6 +154,7 @@
#define TCR_TG0_4K (0 << 14)
#define TCR_TG0_64K(1 << 14)
#define TCR_TG0_16K(2 << 14)
+#define TCR_EPD1_DISABLE (1 << 23)
#ifndef CONFIG_SYS_FULL_VA
#define TCR_EL1_IPS_BITS (UL(3) << 32) /* 42 bits physical address */
--
1.8.5.6
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Re: [U-Boot] dm: Remove ARM dcc from the list
Hi Tom, On 25.2.2016 16:27, Tom Rini wrote: > On Wed, Feb 24, 2016 at 08:34:16AM +0100, Michal Simek wrote: > >> Remove ARM Debug communication channel driver from the list >> of not converted drivers to DM. >> >> Signed-off-by: Michal Simek > > Applied to u-boot/master, thanks! > If you have applied this you should also applied These two. https://patchwork.ozlabs.org/patch/586759/ https://patchwork.ozlabs.org/patch/586758/ Thanks, Michal ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v2, 3/7] drivers: block: disk-uclass: implement scsi_init()
Hi Tom
On Thursday 25 February 2016 09:00 PM, Simon Glass wrote:
> Hi Mugunthan,
>
> On 25 February 2016 at 02:34, Mugunthan V N wrote:
>> On Wednesday 24 February 2016 09:50 PM, Tom Rini wrote:
>>> On Wed, Feb 03, 2016 at 05:29:36PM +0530, Mugunthan V N wrote:
>>>
Implement scsi_init() api to probe driver model based sata
devices.
Signed-off-by: Mugunthan V N
Reviewed-by: Simon Glass
---
drivers/block/disk-uclass.c | 39 +++
1 file changed, 39 insertions(+)
diff --git a/drivers/block/disk-uclass.c b/drivers/block/disk-uclass.c
index d665b35..4bd7b56 100644
--- a/drivers/block/disk-uclass.c
+++ b/drivers/block/disk-uclass.c
@@ -7,6 +7,45 @@
#include
#include
+#include
+#include
+#include
+
+int scsi_get_device(int index, struct udevice **devp)
+{
+struct udevice *dev;
+int ret;
+
+ret = uclass_find_device(UCLASS_DISK, index, &dev);
+if (ret || !dev) {
+printf("%d device not found\n", index);
+return ret;
+}
+
+ret = device_probe(dev);
+if (ret) {
+error("device probe error\n");
+return ret;
+}
+
+*devp = dev;
+
+return ret;
+}
+
+void scsi_init(void)
+{
+struct udevice *dev;
+int ret;
+
+ret = scsi_get_device(0, &dev);
+if (ret || !dev) {
+error("scsi device not found\n");
+return;
+}
+
+scsi_scan(1);
+}
UCLASS_DRIVER(disk) = {
.id = UCLASS_DISK,
>>>
>>> OK, this patch is a problem. Many platforms already define scsi_init()
>>> and aren't moved over so now fail to build. Mele_M5 is one of many
>>> examples here, thanks!
>>>
>>
>> Oops, sorry I didn't run buildman before submitting the patches, will
>> make sure running buildman before submitting patches in future.
>>
>> Issue is when a platform is converted to DM, by default CONFIG_DISK is
>> selected through Kconfig whether the platform has block device or not,
>> disk_uclass driver is compile which results in build break when the
>> platform has scsi_init already defined and not not converted to DM.
>>
>> The following diff solves the issue, and CONFIG_DISK has to be selected
>> for platforms which supports disk (sata, ide etc)
>>
>> Simon, Are you Okay with the patch, so that I can send it as a separate
>> fixup patch.
>
> It is OK, but please enable CONFIG_DISK in chromebook_link_defconfig.
> It is the only user at present.
>
> With driver model we actually don't want scsi_init() to be implemented
> in the end. It's fine for now. The driver-model block-device series
> will make some changes here down the track. We'll have UCLASS_SATA (or
> similar) rather than something as generic as UCLASS_DISK.
>
Will send a fixup patch by tomorrow.
Regards
Mugunthan V N
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Re: [U-Boot] Issue with USB mass storage (thumb drives)
On 02/25/2016 05:13 AM, Simon Glass wrote: > Hi, > > On 24 February 2016 at 10:43, Marek Vasut wrote: >> >> On 02/23/2016 07:38 AM, Hannes Schmelzer wrote: >>> On 22.02.2016 18:59, Fabio Estevam wrote: On Mon, Feb 22, 2016 at 2:51 PM, Maxime Jayat wrote: > Hello, > I was hit by the same problem, where my USB SD card reader would timeout > in U-boot when reading a large file (16 MB). Changing USB_MAX_XFER_BLK > to 32767 fixed the problem but I investigated a little more. > I was curious to see what the Linux kernel used, because it had no > problem reading the file. In Linux, USB_MAX_XFER_BLK corresponds to > max_sector in the scsiglue, which is set to 240 blocks per transfer by > default, and is tunable via sysfs. > There is also a list of unusual devices which needs no higher than 64 > blocks per transfer. > The linux USB FAQ has a very interesting entry about this which explains > the rationale for this value: > http://www.linux-usb.org/FAQ.html#i5 > > FWIW: my USB card reader is > 0bda:0119 Realtek Semiconductor Corp. Storage Device (SD card reader) > > I've benchmarked in U-boot the time impact of this change. > For reading my 16764395 bytes file: > USB_MAX_XFER_BLKRead duration (as reported by U-boot): > 64 3578 ms > 128 2221 ms > 240 1673 ms > 32767 1020 ms > 65535 974 ms > > So there is definitely a strong impact for lower values. Ok, so with a USB_MAX_XFER_BLK size of 32767 there is not so much of a performance impact. Looks like that changing USB_MAX_XFER_BLK from 65535 to 32767 is the way to go. >>> I have configured a value of 8191 some few weeks ago on my zynq board, >>> there was no negative feedback until yesterday :-( >>> >>> A colleague of mine told me, that his USB-stick doesn't work. I had a look. >>> >>> Vendor: 0x1307 Product 0x0165 Version 1.0 >>> I had to reduce the USB_MAX_XFER_BLK downto 2048 to make it work. >>> >>> I'm not the big usb-expert ... but would it be possible to move away >>> from this >>> #define to some variable which is adapted to the lowest value on the bus. >>> Is it possible at all to get to right value out of some register ? >> >> We will probably need a quirk table and for the crappy USB sticks, we >> will just have to use lower maximum xfer size. I would suggest to add >> an environment variable, which would allow to override the max xfer >> size. This would help in case the user had a device, which does need >> a quirk, but is not yet in a quirk table ; as a temporary work around of >> course. > > Yes. > > Even better if we can print a message telling the user about this when > we detect this error. Agreed. Can you prepare such patch please ? ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] serial: Move carriage return before line feed for some serial drivers
On 02/25/2016 03:41 AM, Alison Wang wrote: > In general, a carriage return needs to execute before a line feed. > The patch is to change some serial drivers based on this rule, such > as serial_mxc.c, serial_pxa.c, serial_s3c24x0.c and usbtty.c. > > Signed-off-by: Alison Wang Why isn't this CR-LF stuff handled in common code instead ? It'd be much better than having billion copies of the exact same logic (some of them more buggy than the others) in drivers. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 2/2] board:freescale:usb: Add device-tree fixup support for xhci controller
On 02/24/2016 05:44 AM, Sriram Dash wrote:
> Enables usb device-tree fixup code to incorporate xhci controller
>
> Signed-off-by: Ramneek Mehresh
> Signed-off-by: Sriram Dash
> ---
> board/freescale/common/Makefile | 4 +++-
> board/freescale/common/usb.c| 11 +--
> include/fdt_support.h | 4 ++--
> 3 files changed, 14 insertions(+), 5 deletions(-)
>
> diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
> index 62de45c..8388f47 100644
> --- a/board/freescale/common/Makefile
> +++ b/board/freescale/common/Makefile
> @@ -13,7 +13,9 @@ MINIMAL=y
> endif
> endif
>
> -obj-$(CONFIG_USB_EHCI_FSL) += usb.o
> +ifneq ($(filter y,$(CONFIG_USB_EHCI_FSL) $(CONFIG_USB_XHCI_FSL)),)
> +obj-y += usb.o
> +endif
Please just add:
obj-$(CONFIG_USB_XHCI_FSL) += usb.o
here. Kbuild takes care of duplicities.
> ifdef MINIMAL
> # necessary to create built-in.o
> diff --git a/board/freescale/common/usb.c b/board/freescale/common/usb.c
> index 7a35e92..b06daa0 100644
> --- a/board/freescale/common/usb.c
> +++ b/board/freescale/common/usb.c
> @@ -23,6 +23,7 @@ static const char *fdt_usb_get_node_type(void *blob, int
> start_offset,
> {
> const char *compat_dr = "fsl-usb2-dr";
> const char *compat_mph = "fsl-usb2-mph";
> + const char *compat_snps = "snps,dwc3";
Will you add more random variables here once you add another DT compat
string for another controller? You might want to learn about C arrays :)
> const char *node_type = NULL;
>
> *node_offset = fdt_node_offset_by_compatible(blob, start_offset,
> @@ -32,8 +33,14 @@ static const char *fdt_usb_get_node_type(void *blob, int
> start_offset,
>start_offset,
>compat_dr);
> if (*node_offset < 0) {
> - printf("ERROR: could not find compatible node: %s\n",
> -fdt_strerror(*node_offset));
> + *node_offset = fdt_node_offset_by_compatible
> +(blob, start_offset, compat_snps);
> + if (*node_offset < 0) {
> + printf("ERROR:could not find node:%s",
> +fdt_strerror(*node_offset));
> + } else {
> + node_type = compat_snps;
> + }
> } else {
> node_type = compat_dr;
> }
> diff --git a/include/fdt_support.h b/include/fdt_support.h
> index 296add0..d34e959 100644
> --- a/include/fdt_support.h
> +++ b/include/fdt_support.h
> @@ -113,11 +113,11 @@ void fdt_fixup_qe_firmware(void *fdt);
> */
> int fdt_fixup_display(void *blob, const char *path, const char *display);
>
> -#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
> +#if defined(CONFIG_USB_EHCI_FSL) || defined(CONFIG_USB_XHCI_FSL)
This change looks unrelated.
> void fdt_fixup_dr_usb(void *blob, bd_t *bd);
> #else
> static inline void fdt_fixup_dr_usb(void *blob, bd_t *bd) {}
> -#endif /* defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
> */
> +#endif /* defined(CONFIG_USB_EHCI_FSL) || defined(CONFIG_USB_XHCI_FSL) */
>
> #if defined(CONFIG_SYS_FSL_SEC_COMPAT)
> void fdt_fixup_crypto_node(void *blob, int sec_rev);
>
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Re: [U-Boot] [PATCH v2 1/2] board:freescale:common: Move device-tree fixup framework to common file
On 02/24/2016 05:44 AM, Sriram Dash wrote: > Move usb device-tree fixup framework from ehci-fsl.c to common place so > that it can be used by other drivers as well (xhci-fsl.c). > Also, call fdt_usb_get_node_type() from fdt_fixup_usb_mode_phy_type() to > avoid code duplication. > > Signed-off-by: Ramneek Mehresh > Signed-off-by: Sriram Dash Is this just moving the code ? If so, please resubmit and use git format-patch -M -C to generate the patches for the submission. It makes it much easier to detect moved files. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2 0/6] ARM: keystone: K2G: Add support for PMMC remoteproc load
Hi, Here is the series for supporting TI's PMMC - a Power Management co-processor in TI's K2G SoC. TI's SoC architecture requires the microcontroller for power management functionality which is excersized by various operating systems running on ARM, DSP and other compute engines in a centralized manner. Changes in V2: - Updated remoteproc driver to work with device tree - config env variable updates Series based on: master 52dd704bf8ed Merge branch 'master' of http://git.denx.de/u-boot-sunxi Test log: http://pastebin.ubuntu.com/15200102/ Nishanth Menon (6): ARM: keystone2: psc: redo doc in kernel-doc format ARM: keystone2: psc-defs: use adequate () for macros ARM: keystone2: psc: introduce function to hold and release module in reset. remoteproc: Add support for TI power processor ARM: dts: k2g: Add support for PMMC configs: k2g_evm: Add TI power processor support arch/arm/dts/k2g.dtsi | 7 + arch/arm/mach-keystone/include/mach/psc_defs.h | 10 +- arch/arm/mach-keystone/psc.c | 200 +++-- configs/k2g_evm_defconfig | 2 + drivers/remoteproc/Kconfig | 10 ++ drivers/remoteproc/Makefile| 1 + drivers/remoteproc/ti_power_proc.c | 180 ++ include/configs/k2g_evm.h | 7 + include/configs/ti_armv7_keystone2.h | 14 ++ 9 files changed, 384 insertions(+), 47 deletions(-) create mode 100644 drivers/remoteproc/ti_power_proc.c -- 2.7.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2 3/6] ARM: keystone2: psc: introduce function to hold and release module in reset.
These are useful for modules that need to be held in reset and are
enabled for data to be loaded on to them. Typically these are
microcontrollers or other processing entities in the system.
Signed-off-by: Nishanth Menon
---
V2: no change
V1: https://patchwork.ozlabs.org/patch/510209/
arch/arm/mach-keystone/include/mach/psc_defs.h | 4 +
arch/arm/mach-keystone/psc.c | 104 +
2 files changed, 108 insertions(+)
diff --git a/arch/arm/mach-keystone/include/mach/psc_defs.h
b/arch/arm/mach-keystone/include/mach/psc_defs.h
index 2202946be5ea..6e6e7fd433a1 100644
--- a/arch/arm/mach-keystone/include/mach/psc_defs.h
+++ b/arch/arm/mach-keystone/include/mach/psc_defs.h
@@ -56,6 +56,8 @@
#define PSC_REG_MDSTAT_GET_STATUS(x)BOOT_READ_BITFIELD((x), 5, 0)
#define PSC_REG_MDSTAT_GET_LRSTZ(x) BOOT_READ_BITFIELD((x), 8, 8)
#define PSC_REG_MDSTAT_GET_LRSTDONE(x) BOOT_READ_BITFIELD((x), 9, 9)
+#define PSC_REG_MDSTAT_GET_MRSTZ(x) BOOT_READ_BITFIELD((x), 10, 10)
+#define PSC_REG_MDSTAT_GET_MRSTDONE(x) BOOT_READ_BITFIELD((x), 11, 11)
/* PDCTL states */
#define PSC_REG_VAL_PDCTL_NEXT_ON 1
@@ -86,5 +88,7 @@ u32 psc_get_domain_num(u32 mod_num);
int psc_enable_module(u32 mod_num);
int psc_disable_module(u32 mod_num);
int psc_disable_domain(u32 domain_num);
+int psc_module_keep_in_reset_enabled(u32 mod_num, bool gate_clocks);
+int psc_module_release_from_reset(u32 mod_num);
#endif /* _PSC_DEFS_H_ */
diff --git a/arch/arm/mach-keystone/psc.c b/arch/arm/mach-keystone/psc.c
index 8991e237735e..ff042a6db2dd 100644
--- a/arch/arm/mach-keystone/psc.c
+++ b/arch/arm/mach-keystone/psc.c
@@ -233,3 +233,107 @@ int psc_disable_domain(u32 domain_num)
return psc_wait(domain_num);
}
+
+/**
+ * psc_module_keep_in_reset_enabled() - Keep module in enabled,in-reset state
+ * @mod_num: LPSC module number
+ * @gate_clocks: Can the clocks be gated on this module?
+ *
+ * Enable the module, but do not release the module from local reset. This is
+ * necessary for many processor systems on keystone SoCs to allow for system
+ * initialization from a master processor prior to releasing the processor
+ * from reset.
+ */
+int psc_module_keep_in_reset_enabled(u32 mod_num, bool gate_clocks)
+{
+ u32 mdctl, ptcmd, mdstat;
+ u32 next_state;
+ int domain_num = psc_get_domain_num(mod_num);
+ int timeout = 10;
+
+ /* Wait for any previous transitions to complete */
+ psc_wait(domain_num);
+ mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
+ /* Should be set 0 to assert Local reset */
+ if ((mdctl & PSC_REG_MDCTL_SET_LRSTZ(mdctl, 1))) {
+ mdctl = PSC_REG_MDCTL_SET_LRSTZ(mdctl, 0);
+ __raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
+ /* Wait for transition to take place */
+ psc_wait(domain_num);
+ }
+
+ /* Clear Module reset */
+ mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
+ next_state = gate_clocks ? PSC_REG_VAL_MDCTL_NEXT_OFF :
+ PSC_REG_VAL_MDCTL_NEXT_ON;
+ mdctl = PSC_REG_MDCTL_SET_NEXT(mdctl, next_state);
+ __raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
+ /* Trigger PD transition */
+ ptcmd = __raw_readl(KS2_PSC_BASE + PSC_REG_PTCMD);
+ ptcmd |= (u32)(1 << domain_num);
+ __raw_writel(ptcmd, KS2_PSC_BASE + PSC_REG_PTCMD);
+ psc_wait(domain_num);
+
+ mdstat = __raw_readl(KS2_PSC_BASE + PSC_REG_MDSTAT(mod_num));
+ while (timeout) {
+ mdstat = __raw_readl(KS2_PSC_BASE + PSC_REG_MDSTAT(mod_num));
+
+ if (!(PSC_REG_MDSTAT_GET_STATUS(mdstat) & 0x30) &&
+ PSC_REG_MDSTAT_GET_MRSTDONE(mdstat) &&
+ PSC_REG_MDSTAT_GET_LRSTDONE(mdstat))
+ break;
+ timeout--;
+ }
+
+ if (!timeout) {
+ printf("%s: Timedout waiting for mdstat(0x%08x) to change\n",
+ __func__, mdstat);
+ return -ETIMEDOUT;
+ }
+ return 0;
+}
+
+/**
+ * psc_module_release_from_reset() - Release the module from reset
+ * @mod_num: LPSC module number
+ *
+ * This is the follow through for the command
'psc_module_keep_in_reset_enabled'
+ * Allowing the module to be released from reset once all required inits are
+ * complete for the module. Typically, this allows the processor module to
start
+ * execution.
+ */
+int psc_module_release_from_reset(u32 mod_num)
+{
+ u32 mdctl, mdstat;
+ int domain_num = psc_get_domain_num(mod_num);
+ int timeout = 10;
+
+ /* Wait for any previous transitions to complete */
+ psc_wait(domain_num);
+ mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
+ /* Should be set to 1 to de-assert Local reset */
+ if ((mdctl & PSC_REG_MDCTL_SET_LRSTZ(mdctl, 0))) {
+ mdctl =
[U-Boot] [PATCH V2 4/6] remoteproc: Add support for TI power processor
Many TI System on Chip (SoC) solutions do have a dedicated
microcontroller for doing power management functionality. These include
the AM335x, AM437x, Keystone K2G SoCs. The functionality provided by
these microcontrollers and the communication mechanisms vary very
widely. However, we are able to consolidate some basic functionality to
be generic enough starting with K2G SoC family. Introduce a basic remote
proc driver to support these microcontrollers. In fact, on SoCs starting
with K2G, basic power management functions are primarily accessible for
the High Level Operating Systems(HLOS) via these microcontroller solutions.
Hence, having these started at a bootloader level is pretty much
mandatory.
Signed-off-by: Nishanth Menon
---
V2: - updated to be dt based and no support for older platform data style
drivers. we dont need it anymore.
- few minor functional bugfixes incorporated
V1: https://patchwork.ozlabs.org/patch/510212/
drivers/remoteproc/Kconfig | 10 +++
drivers/remoteproc/Makefile| 1 +
drivers/remoteproc/ti_power_proc.c | 180 +
3 files changed, 191 insertions(+)
create mode 100644 drivers/remoteproc/ti_power_proc.c
diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig
index 437224b5491f..d0b76be1188e 100644
--- a/drivers/remoteproc/Kconfig
+++ b/drivers/remoteproc/Kconfig
@@ -21,4 +21,14 @@ config REMOTEPROC_SANDBOX
help
Say 'y' here to add support for test processor which does dummy
operations for sandbox platform.
+
+config REMOTEPROC_TI_POWER
+ bool "Support for TI Power processor"
+ select REMOTEPROC
+ depends on DM
+ depends on ARCH_KEYSTONE
+ depends on OF_CONTROL
+ help
+ Say 'y' here to add support for TI power processors such as those
+ found on certain TI keystone and OMAP generation SoCs.
endmenu
diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile
index 720aa6e64701..65fc0613de89 100644
--- a/drivers/remoteproc/Makefile
+++ b/drivers/remoteproc/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_REMOTEPROC) += rproc-uclass.o
# Remote proc drivers - Please keep this list alphabetically sorted.
obj-$(CONFIG_REMOTEPROC_SANDBOX) += sandbox_testproc.o
+obj-$(CONFIG_REMOTEPROC_TI_POWER) += ti_power_proc.o
diff --git a/drivers/remoteproc/ti_power_proc.c
b/drivers/remoteproc/ti_power_proc.c
new file mode 100644
index ..76ac3be092e2
--- /dev/null
+++ b/drivers/remoteproc/ti_power_proc.c
@@ -0,0 +1,180 @@
+/*
+ * (C) Copyright 2015-2016
+ * Texas Instruments Incorporated - http://www.ti.com/
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#define pr_fmt(fmt) "%s: " fmt, __func__
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * struct ti_powerproc_privdata - power processor private data
+ * @loadaddr: base address for loading the power processor
+ * @psc_module:psc module address.
+ */
+struct ti_powerproc_privdata {
+ phys_addr_t loadaddr;
+ u32 psc_module;
+};
+
+/**
+ * ti_of_to_priv() - generate private data from device tree
+ * @dev: corresponding ti remote processor device
+ * @priv: pointer to driver specific private data
+ *
+ * Return: 0 if all went ok, else corresponding -ve error
+ */
+static int ti_of_to_priv(struct udevice *dev,
+struct ti_powerproc_privdata *priv)
+{
+ int node = dev->of_offset;
+ const void *blob = gd->fdt_blob;
+ int tmp;
+
+ if (!blob) {
+ debug("'%s' no dt?\n", dev->name);
+ return -EINVAL;
+ }
+
+ priv->loadaddr = fdtdec_get_addr(blob, node, "reg");
+ if (priv->loadaddr == FDT_ADDR_T_NONE) {
+ debug("'%s': no 'reg' property\n", dev->name);
+ return -EINVAL;
+ }
+
+ tmp = fdtdec_get_int(blob, node, "ti,lpsc_module", -EINVAL);
+ if (tmp < 0) {
+ debug("'%s': no 'ti,lpsc_module' property\n", dev->name);
+ return tmp;
+ }
+ priv->psc_module = tmp;
+
+ return 0;
+}
+
+/**
+ * ti_powerproc_probe() - Basic probe
+ * @dev: corresponding ti remote processor device
+ *
+ * Return: 0 if all went ok, else corresponding -ve error
+ */
+static int ti_powerproc_probe(struct udevice *dev)
+{
+ struct dm_rproc_uclass_pdata *uc_pdata;
+ struct ti_powerproc_privdata *priv;
+ int ret;
+
+ uc_pdata = dev_get_uclass_platdata(dev);
+ priv = dev_get_priv(dev);
+
+ ret = ti_of_to_priv(dev, priv);
+
+ debug("%s probed with slave_addr=0x%08lX module=%d(%d)\n",
+ uc_pdata->name, priv->loadaddr, priv->psc_module, ret);
+
+ return ret;
+}
+
+/**
+ * ti_powerproc_load() - Loadup the TI remote processor
+ * @dev: corresponding ti remote processor device
+ * @addr: Address in memory where image binary is stored
+ * @size: Size in bytes of the image binar
[U-Boot] [PATCH V2 1/6] ARM: keystone2: psc: redo doc in kernel-doc format
u-boot coding style guidance in
http://www.denx.de/wiki/U-Boot/CodingStyle clearly mentions that the
kernel doc style shall be followed for documentation in u-boot.
Current PSC documentation standard does not, so fix that.
Signed-off-by: Nishanth Menon
---
V2: no change
V1: https://patchwork.ozlabs.org/patch/510210/
arch/arm/mach-keystone/psc.c | 96
1 file changed, 52 insertions(+), 44 deletions(-)
diff --git a/arch/arm/mach-keystone/psc.c b/arch/arm/mach-keystone/psc.c
index 237e776e8790..8991e237735e 100644
--- a/arch/arm/mach-keystone/psc.c
+++ b/arch/arm/mach-keystone/psc.c
@@ -13,24 +13,27 @@
#include
#include
+/**
+ * psc_delay() - delay for psc
+ *
+ * Return: 10
+ */
int psc_delay(void)
{
udelay(10);
return 10;
}
-/*
- * FUNCTION PURPOSE: Wait for end of transitional state
- *
- * DESCRIPTION: Polls pstat for the selected domain and waits for transitions
- * to be complete.
+/**
+ * psc_wait() - Wait for end of transitional state
+ * @domain_num: GPSC domain number
*
- * Since this is boot loader code it is *ASSUMED* that interrupts
- * are disabled and no other core is mucking around with the psc
- * at the same time.
+ * Polls pstat for the selected domain and waits for transitions to be
complete.
+ * Since this is boot loader code it is *ASSUMED* that interrupts are disabled
+ * and no other core is mucking around with the psc at the same time.
*
- * Returns 0 when the domain is free. Returns -1 if a timeout
- * occurred waiting for the completion.
+ * Return: 0 when the domain is free. Returns -1 if a timeout occurred waiting
+ * for the completion.
*/
int psc_wait(u32 domain_num)
{
@@ -59,6 +62,10 @@ int psc_wait(u32 domain_num)
return 0;
}
+/**
+ * psc_get_domain_num() - Get the domain number
+ * @mod_num: LPSC module number
+ */
u32 psc_get_domain_num(u32 mod_num)
{
u32 domain_num;
@@ -70,20 +77,19 @@ u32 psc_get_domain_num(u32 mod_num)
return domain_num;
}
-/*
- * FUNCTION PURPOSE: Power up/down a module
+/**
+ * psc_set_state() - powers up/down a module
+ * @mod_num: LPSC module number
+ * @state: 1 to enable, 0 to disable.
*
- * DESCRIPTION: Powers up/down the requested module and the associated power
- * domain if required. No action is taken it the module is
- * already powered up/down.
+ * Powers up/down the requested module and the associated power domain if
+ * required. No action is taken it the module is already powered up/down.
+ * This only controls modules. The domain in which the module resides will
+ * be left in the power on state. Multiple modules can exist in a power
+ * domain, so powering down the domain based on a single module is not done.
*
- * This only controls modules. The domain in which the module
- * resides will be left in the power on state. Multiple modules
- * can exist in a power domain, so powering down the domain based
- * on a single module is not done.
- *
- * Returns 0 on success, -1 if the module can't be powered up, or
- * if there is a timeout waiting for the transition.
+ * Return: 0 on success, -1 if the module can't be powered up, or if there is a
+ * timeout waiting for the transition.
*/
int psc_set_state(u32 mod_num, u32 state)
{
@@ -136,15 +142,16 @@ int psc_set_state(u32 mod_num, u32 state)
return psc_wait(domain_num);
}
-/*
- * FUNCTION PURPOSE: Power up a module
+/**
+ * psc_enable_module() - power up a module
+ * @mod_num: LPSC module number
*
- * DESCRIPTION: Powers up the requested module and the associated power domain
- * if required. No action is taken it the module is already
- * powered up.
+ * Powers up the requested module and the associated power domain
+ * if required. No action is taken it the module is already powered up.
+ *
+ * Return: 0 on success, -1 if the module can't be powered up, or
+ * if there is a timeout waiting for the transition.
*
- * Returns 0 on success, -1 if the module can't be powered up, or
- * if there is a timeout waiting for the transition.
*/
int psc_enable_module(u32 mod_num)
{
@@ -158,12 +165,11 @@ int psc_enable_module(u32 mod_num)
return psc_set_state(mod_num, PSC_REG_VAL_MDCTL_NEXT_ON);
}
-/*
- * FUNCTION PURPOSE: Power down a module
+/**
+ * psc_disable_module() - Power down a module
+ * @mod_num: LPSC module number
*
- * DESCRIPTION: Powers down the requested module.
- *
- * Returns 0 on success, -1 on failure or timeout.
+ * Return: 0 on success, -1 on failure or timeout.
*/
int psc_disable_module(u32 mod_num)
{
@@ -179,13 +185,16 @@ int psc_disable_module(u32 mod_num)
return psc_set_state(mod_num, PSC_REG_VAL_MDCTL_NEXT_SWRSTDISABLE);
}
-/*
- * FUNCTION PURPOSE: Set the
[U-Boot] [PATCH V2 2/6] ARM: keystone2: psc-defs: use adequate () for macros
'#define X a | b' is better defined as '#define X (a | b)' for obvious reasons. Signed-off-by: Nishanth Menon --- V2: No change V1: https://patchwork.ozlabs.org/patch/510211/ arch/arm/mach-keystone/include/mach/psc_defs.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-keystone/include/mach/psc_defs.h b/arch/arm/mach-keystone/include/mach/psc_defs.h index 70d22cf21787..2202946be5ea 100644 --- a/arch/arm/mach-keystone/include/mach/psc_defs.h +++ b/arch/arm/mach-keystone/include/mach/psc_defs.h @@ -30,9 +30,9 @@ #define BOOTBITMASK(x, y) ((u32)1 << (((u32)x) - ((u32)y) + (u32)1)) - \ (u32)1)) << ((u32)y))) -#define BOOT_READ_BITFIELD(z, x, y)(((u32)z) & BOOTBITMASK(x, y)) >> (y) -#define BOOT_SET_BITFIELD(z, f, x, y) (((u32)z) & ~BOOTBITMASK(x, y)) | \ -u32)f) << (y)) & BOOTBITMASK(x, y)) +#define BOOT_READ_BITFIELD(z, x, y)u32)z) & BOOTBITMASK(x, y)) >> (y)) +#define BOOT_SET_BITFIELD(z, f, x, y) u32)z) & ~BOOTBITMASK(x, y)) | \ + u32)f) << (y)) & BOOTBITMASK(x, y))) /* PDCTL */ #define PSC_REG_PDCTL_SET_NEXT(x, y)BOOT_SET_BITFIELD((x), (y), 0, 0) -- 2.7.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2 5/6] ARM: dts: k2g: Add support for PMMC
Enable support for PMMC the TI power processor on K2G. This processor
manages all power management related activities on the SoC and and
allows the Operating Systems on compute processors such as ARM, DSP to
offload the power logic away into the power processor. U-boot just has a
load responsibility, hence the view of the hardware from a bootloader
perspective is different from the view of hardware from a Operating
System perspective. While bootloader just loads up the firmware,
Operating Systems look at the resultant system as "hardware".
Signed-off-by: Nishanth Menon
---
V1: did not exist
arch/arm/dts/k2g.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/dts/k2g.dtsi b/arch/arm/dts/k2g.dtsi
index bbc2cf91b95f..a3ed444d3c31 100644
--- a/arch/arm/dts/k2g.dtsi
+++ b/arch/arm/dts/k2g.dtsi
@@ -81,5 +81,12 @@
};
#include "k2g-netcp.dtsi"
+
+ pmmc: pmmc@290 {
+ compatible = "ti,power-processor";
+ reg = <0x0290 0x4>;
+ ti,lpsc_module = <1>;
+ };
+
};
};
--
2.7.0
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[U-Boot] [PATCH V2 6/6] configs: k2g_evm: Add TI power processor support
Enable support for PMMC the TI power processor on K2G. This processor
manages all power management related activities on the SoC and and
allows the Operating Systems on compute processors such as ARM, DSP to
offload the power logic away into the power processor.
Signed-off-by: Nishanth Menon
---
V1: did not exist.
configs/k2g_evm_defconfig| 2 ++
include/configs/k2g_evm.h| 7 +++
include/configs/ti_armv7_keystone2.h | 14 ++
3 files changed, 23 insertions(+)
diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig
index 7cebacd035c9..a66d75fde15a 100644
--- a/configs/k2g_evm_defconfig
+++ b/configs/k2g_evm_defconfig
@@ -4,6 +4,8 @@ CONFIG_TARGET_K2G_EVM=y
CONFIG_DM_SERIAL=y
CONFIG_DEFAULT_DEVICE_TREE="k2g-evm"
CONFIG_SPL=y
+CONFIG_CMD_REMOTEPROC=y
+CONFIG_REMOTEPROC_TI_POWER=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h
index d9ad8cf4b4d8..ca1e368aa010 100644
--- a/include/configs/k2g_evm.h
+++ b/include/configs/k2g_evm.h
@@ -17,6 +17,7 @@
/* U-Boot general configuration */
#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS\
DEFAULT_MMC_TI_ARGS \
+ DEFAULT_PMMC_BOOT_ENV \
"console=ttyS0,115200n8\0" \
"bootpart=0:2\0"\
"bootdir=/boot\0" \
@@ -28,11 +29,17 @@
"name_ubi=k2g-evm-ubifs.ubi\0" \
"name_uboot=u-boot-spi-k2g-evm.gph\0" \
"init_mmc=run args_all args_mmc\0" \
+ "soc_variant=k2g\0" \
"get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}\0"\
"get_kern_mmc=load mmc ${bootpart} ${loadaddr} "\
"${bootdir}/${name_kern}\0" \
"get_mon_mmc=load mmc ${bootpart} ${addr_mon} ${bootdir}/${name_mon}\0"\
+#define CONFIG_BOOTCOMMAND \
+ "run set_name_pmmc init_${boot} get_pmmc_${boot} run_pmmc " \
+ "get_fdt_${boot} get_mon_${boot} get_kern_${boot} " \
+ "run_mon run_kern"
+
#include
/* SPL SPI Loader Configuration */
diff --git a/include/configs/ti_armv7_keystone2.h
b/include/configs/ti_armv7_keystone2.h
index a7206f4beab0..70a484e4222b 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -223,6 +223,18 @@
/* EDMA3 */
#define CONFIG_TI_EDMA3
+#define DEFAULT_PMMC_BOOT_ENV \
+ "set_name_pmmc=setenv name_pmmc ti-sci-firmware-${soc_variant}.bin\0" \
+ "dev_pmmc=0\0" \
+ "get_pmmc_net=dhcp ${loadaddr} ${tftp_root}/${name_pmmc}\0" \
+ "get_pmmc_ramfs=run get_pmmc_net\0" \
+ "get_pmmc_mmc=load mmc ${bootpart} ${loadaddr} "\
+ "${bootdir}/${name_pmmc}\0" \
+ "get_pmmc_ubi=ubifsload ${loadaddr} ${bootdir}/${name_pmmc}\0" \
+ "run_pmmc=rproc init; rproc list; " \
+ "rproc load ${dev_pmmc} ${loadaddr} 0x${filesize}; "\
+ "rproc start ${dev_pmmc}\0" \
+
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \
@@ -271,9 +283,11 @@
"mtdparts=mtdparts=davinci_nand.0:" \
"1024k(bootloader)ro,512k(params)ro,-(ubifs)\0"
+#ifndef CONFIG_BOOTCOMMAND
#define CONFIG_BOOTCOMMAND \
"run init_${boot} get_fdt_${boot} get_mon_${boot} " \
"get_kern_${boot} run_mon run_kern"
+#endif
#define CONFIG_BOOTARGS
\
--
2.7.0
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Re: [U-Boot] dm: Remove ARM dcc from the list
On Thu, Feb 25, 2016 at 06:30:06PM +0100, Michal Simek wrote: > Hi Tom, > > On 25.2.2016 16:27, Tom Rini wrote: > > On Wed, Feb 24, 2016 at 08:34:16AM +0100, Michal Simek wrote: > > > >> Remove ARM Debug communication channel driver from the list > >> of not converted drivers to DM. > >> > >> Signed-off-by: Michal Simek > > > > Applied to u-boot/master, thanks! > > > > If you have applied this you should also applied > These two. > https://patchwork.ozlabs.org/patch/586759/ > https://patchwork.ozlabs.org/patch/586758/ *facepalm*. They look simple enough so I'll take 'em shortly. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] dm: Remove ARM dcc from the list
On 25.2.2016 21:05, Tom Rini wrote: > On Thu, Feb 25, 2016 at 06:30:06PM +0100, Michal Simek wrote: >> Hi Tom, >> >> On 25.2.2016 16:27, Tom Rini wrote: >>> On Wed, Feb 24, 2016 at 08:34:16AM +0100, Michal Simek wrote: >>> Remove ARM Debug communication channel driver from the list of not converted drivers to DM. Signed-off-by: Michal Simek >>> >>> Applied to u-boot/master, thanks! >>> >> >> If you have applied this you should also applied >> These two. >> https://patchwork.ozlabs.org/patch/586759/ >> https://patchwork.ozlabs.org/patch/586758/ > > *facepalm*. They look simple enough so I'll take 'em shortly. They were reviewed by Simon that's why I expect low risk to apply them. I will look at my others pending patches tmr. Thanks, Michal ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RFC PATCH v5 2/4] sandbox: Fix compiling warning
Fix the following compiling warning. Some only occur on 32-bit hosts
disk/part_efi.c: In function 'alloc_read_gpt_entries':
disk/part_efi.c:894:2: warning: format '%zu' expects argument of
type 'size_t', but argument 5 has type 'long unsigned int'
[-Wformat]
disk/part_efi.c:907:4: warning: format '%zX' expects argument of
type 'size_t', but argument 3 has type 'long unsigned int'
[-Wformat]
cmd/lzmadec.c: In function 'do_lzmadec':
cmd/lzmadec.c:39:12: warning: passing argument 2 of
'lzmaBuffToBuffDecompress' from incompatible pointer type
[enabled by default]
include/lzma/../../lib/lzma/LzmaTools.h:17:12: note: expected
'SizeT *' but argument is of type 'long unsigned int *'
lib/hashtable.c: In function 'hexport_r':
lib/hashtable.c:605:2: warning: format '%zu' expects argument of
type 'size_t', but argument 5 has type 'long unsigned int'
[-Wformat]
lib/hashtable.c:661:5: warning: format '%zu' expects argument of
type 'size_t', but argument 2 has type 'long unsigned int'
[-Wformat]
lib/hashtable.c:661:5: warning: format '%zu' expects argument of
type 'size_t', but argument 3 has type 'long unsigned int'
[-Wformat]
lib/hashtable.c: In function 'himport_r':
lib/hashtable.c:793:3: warning: format '%zu' expects argument of
type 'size_t', but argument 2 has type 'long unsigned int'
[-Wformat]
Signed-off-by: York Sun
---
Changes in v5:
Revise commit message
Drop % sign in PRIpa macro
Use %#08llx instead of %08llx when applicable
Changes in v4:
New patch to fix compiling warnings for sandbox built on 32-bit host
Still need to change CONFIG_SANDBOX_BITS_PER_LONG to 32 to avoid
these warnings
include/asm-generic/bitops/__fls.h:17:2: warning: left shift
count >= width of type [enabled by default]
include/asm-generic/bitops/__fls.h:19:3: warning: left shift
count >= width of type [enabled by default]
include/asm-generic/bitops/__fls.h:22:2: warning: left shift
count >= width of type [enabled by default]
include/asm-generic/bitops/__fls.h:26:2: warning: left shift
count >= width of type [enabled by default]
include/asm-generic/bitops/__fls.h:30:2: warning: left shift
count >= width of type [enabled by default]
include/asm-generic/bitops/__fls.h:34:2: warning: left shift
count >= width of type [enabled by default]
include/asm-generic/bitops/__fls.h:38:2: warning: left shift
count >= width of type [enabled by default]
Changes in v3: None
Changes in v2: None
arch/sandbox/cpu/cpu.c |3 ++-
arch/sandbox/include/asm/types.h |9 +++--
arch/sandbox/lib/bootm.c |3 ++-
arch/sandbox/lib/pci_io.c|2 +-
cmd/lzmadec.c|5 +++--
disk/part_efi.c |2 +-
lib/hashtable.c |2 +-
7 files changed, 17 insertions(+), 9 deletions(-)
diff --git a/arch/sandbox/cpu/cpu.c b/arch/sandbox/cpu/cpu.c
index 196f3e1..5220b08 100644
--- a/arch/sandbox/cpu/cpu.c
+++ b/arch/sandbox/cpu/cpu.c
@@ -62,7 +62,8 @@ void *map_physmem(phys_addr_t paddr, unsigned long len,
unsigned long flags)
map_dev = NULL;
if (enable_pci_map && !pci_map_physmem(paddr, &len, &map_dev, &ptr)) {
if (plen != len) {
- printf("%s: Warning: partial map at %x, wanted %lx, got
%lx\n",
+ printf("%s: Warning: partial map at %" PRIpa
+ ", wanted %lx, got %lx\n",
__func__, paddr, len, plen);
}
map_len = len;
diff --git a/arch/sandbox/include/asm/types.h b/arch/sandbox/include/asm/types.h
index 42c09e2..11b521d 100644
--- a/arch/sandbox/include/asm/types.h
+++ b/arch/sandbox/include/asm/types.h
@@ -53,8 +53,13 @@ typedef __UINT64_TYPE__ u64;
#define BITS_PER_LONG CONFIG_SANDBOX_BITS_PER_LONG
typedef unsigned long dma_addr_t;
-typedef u32 phys_addr_t;
-typedef u32 phys_size_t;
+#if defined(CONFIG_PHYS_64BIT) || (BITS_PER_LONG > 32)
+/* To be consistent with print format %llx */
+typedef unsigned long long phys_addr_t;
+#else
+typedef unsigned long phys_addr_t;
+#endif
+typedef unsigned long phys_size_t;
#endif /* __KERNEL__ */
diff --git a/arch/sandbox/lib/bootm.c b/arch/sandbox/lib/bootm.c
index d49c927..2c15883 100644
--- a/arch/sandbox/lib/bootm.c
+++ b/arch/sandbox/lib/bootm.c
@@ -54,7 +54,8 @@ int do_bootm_linux(int flag, int argc, char *argv[],
bootm_headers_t *images)
{
if (flag & (BOOTM_STATE_OS_GO | BOOTM_STATE_OS_FAKE_GO)) {
bootstage_mark(BOOTSTAGE_ID_RUN_OS);
- printf("## Transferring control to Linux (at address
%08lx)...\n",
+ printf("## Transferring control to Linux (at address %#08" PRIpa
+ ")...\n",
images->ep);
reset_cpu(0);
}
diff --git a/arch/sandbox/lib/pci_io.c b/arch/sandbox/lib/pci_io.c
index 0de124f..f79ea0a 100644
--- a/arch/sandbox/lib/pci_io.c
+++ b/arch/sandbox/lib/pci_io.c
@@ -35,7 +35,
[U-Boot] [RFC PATCH v5 3/4] common: image-fit: Use a common function to get address
FIT image supports load address and entry address. Getting these
addresses can use a common function.
Signed-off-by: York Sun
---
Changes in v5:
New patch split from fixing load and entry address patch
Changes in v4: None
Changes in v3: None
Changes in v2: None
common/image-fit.c | 42 +++---
1 file changed, 19 insertions(+), 23 deletions(-)
diff --git a/common/image-fit.c b/common/image-fit.c
index eec0ded..2d29e88 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -433,7 +433,7 @@ void fit_image_print(const void *fit, int image_noffset,
const char *p)
if ((type == IH_TYPE_KERNEL) || (type == IH_TYPE_STANDALONE) ||
(type == IH_TYPE_RAMDISK)) {
- fit_image_get_entry(fit, image_noffset, &entry);
+ ret = fit_image_get_entry(fit, image_noffset, &entry);
printf("%s Entry Point: ", p);
if (ret)
printf("unavailable\n");
@@ -675,6 +675,22 @@ int fit_image_get_comp(const void *fit, int noffset,
uint8_t *comp)
return 0;
}
+static int fit_image_get_address(const void *fit, int noffset, char *name,
+ phys_addr_t *load)
+{
+ int len;
+ const uint32_t *data;
+
+ data = fdt_getprop(fit, noffset, name, &len);
+ if (data == NULL) {
+ fit_get_debug(fit, noffset, name, len);
+ return -1;
+ }
+
+ *load = uimage_to_cpu(*data);
+
+ return 0;
+}
/**
* fit_image_get_load() - get load addr property for given component image node
* @fit: pointer to the FIT format image header
@@ -690,17 +706,7 @@ int fit_image_get_comp(const void *fit, int noffset,
uint8_t *comp)
*/
int fit_image_get_load(const void *fit, int noffset, phys_addr_t *load)
{
- int len;
- const uint32_t *data;
-
- data = fdt_getprop(fit, noffset, FIT_LOAD_PROP, &len);
- if (data == NULL) {
- fit_get_debug(fit, noffset, FIT_LOAD_PROP, len);
- return -1;
- }
-
- *load = uimage_to_cpu(*data);
- return 0;
+ return fit_image_get_address(fit, noffset, FIT_LOAD_PROP, load);
}
/**
@@ -722,17 +728,7 @@ int fit_image_get_load(const void *fit, int noffset,
phys_addr_t *load)
*/
int fit_image_get_entry(const void *fit, int noffset, phys_addr_t *entry)
{
- int len;
- const uint32_t *data;
-
- data = fdt_getprop(fit, noffset, FIT_ENTRY_PROP, &len);
- if (data == NULL) {
- fit_get_debug(fit, noffset, FIT_ENTRY_PROP, len);
- return -1;
- }
-
- *entry = uimage_to_cpu(*data);
- return 0;
+ return fit_image_get_address(fit, noffset, FIT_ENTRY_PROP, entry);
}
/**
--
1.7.9.5
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[U-Boot] [RFC PATCH v5 4/4] common: image-fit: Fix load and entry addresses in FIT image
FIT image supports more than 32 bits in addresses by using #address-cell
field. Fixing 64-bit support by using this field.
Signed-off-by: York Sun
---
Changes in v5:
Split the common function into another patch.
Revise commit subject.
Update commit message as suggested by Simon.
Updated cover letter with testing report.
Changes in v4:
Separate ulong to phys_addr_t change to another patch.
Changes in v3:
Define PRIpa for host and target in common/image-fit.c so printf works
properly for 32-, 64-bit targets and host tools.
Changes in v2:
Make a common function for both load and entry addresses.
Simplify calculation of addresses in a similar way as fdtdec_get_number()
fdtdec_get_number() is not used, or too many files need to be included
and/or twisted for host tool
Continue to use %08llx for print format for load and entry addresses
because %pa does not always work for host tool (mkimage)
common/image-fit.c | 22 +-
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/common/image-fit.c b/common/image-fit.c
index 2d29e88..69cf598 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -678,16 +678,28 @@ int fit_image_get_comp(const void *fit, int noffset,
uint8_t *comp)
static int fit_image_get_address(const void *fit, int noffset, char *name,
phys_addr_t *load)
{
- int len;
- const uint32_t *data;
+ int len, cell_len;
+ const fdt32_t *cell;
+ unsigned long long load64 = 0;
- data = fdt_getprop(fit, noffset, name, &len);
- if (data == NULL) {
+ cell = fdt_getprop(fit, noffset, name, &len);
+ if (cell == NULL) {
fit_get_debug(fit, noffset, name, len);
return -1;
}
- *load = uimage_to_cpu(*data);
+ if (len > sizeof(phys_addr_t)) {
+ printf("Unsupported %s address size\n", name);
+ return -1;
+ }
+
+ cell_len = len >> 2;
+ /* Use load64 to avoid compiling warning for 32-bit target */
+ while (cell_len--) {
+ load64 = (load64 << 32) | uimage_to_cpu(*cell);
+ cell++;
+ }
+ *load = (phys_addr_t)load64;
return 0;
}
--
1.7.9.5
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[U-Boot] [PATCH 6/7 v2] pci/layerscape: fdt: function to set msi-map entries
From: Stuart Yoder
msi-map properties are used to tell an OS how PCI requester
IDs are mapped to ARM SMMU stream IDs. This patch defines a
function to append a single msi-map entry to a given PCI controller
device tree node.
Signed-off-by: Stuart Yoder
---
-v2
-no changes
drivers/pci/pcie_layerscape.c | 43 -
1 file changed, 42 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index f96a08c..dfafaf2 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -490,7 +490,6 @@ static void ls_pcie_setup_ep(struct ls_pcie *pcie, struct
ls_pcie_info *info)
}
}
-
/*
* Return next available LUT index.
*/
@@ -528,6 +527,48 @@ static u32 ls_pcie_next_streamid(void)
return next_stream_id++;
}
+/*
+ * An msi-map is a property to be added to the pci controller
+ * node. It is a table, where each entry consists of 4 fields
+ * e.g.:
+ *
+ * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
+ * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
+ */
+static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie,
+ u32 devid, u32 streamid)
+{
+ char pcie_path[19];
+ u32 *prop;
+ u32 phandle;
+ int nodeoffset;
+
+ /* find pci controller node */
+ snprintf(pcie_path, sizeof(pcie_path), "/soc/pcie@%llx",
+(u64)pcie->dbi);
+ nodeoffset = fdt_path_offset(blob, pcie_path);
+ if (nodeoffset < 0) {
+ printf("\n%s: ERROR: unable to update PCIe node: %s\n",
+ __func__, pcie_path);
+ return;
+ }
+
+ /* get phandle to MSI controller */
+ prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0);
+ if (prop == NULL) {
+ printf("\n%s: ERROR: missing msi-parent: %s\n", __func__,
+ pcie_path);
+ return;
+ }
+ phandle = be32_to_cpu(*prop);
+
+ /* set one msi-map row */
+ fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid);
+ fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle);
+ fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid);
+ fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1);
+}
+
int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, struct ls_pcie_info
*info)
{
struct ls_pcie *pcie;
--
1.7.9.5
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