Re: [U-Boot] [ANN] U-Boot v2015.10-rc5 released
Dear Tom, In message <20151015004002.GX23893@bill-the-cat> you wrote: > > I'm just not sure what to do about CONFIG_API some days. I know one use > case is for GRUB but I'd like to move away from that if possible > (distros should be doing the generic distro bits and extlinux.conf). > After that, I'm only hazily aware of the real use-cases. The major use case (as I understand it) are the FreeBSD users who need this API for booting. I'm adding Rafal and Bartek to Cc: as they should know best if this interface is still in wide use. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Software entities are more complex for their size than perhaps any other human construct because no two parts are alike. If they are, we make the two similar parts into a subroutine -- open or closed. In this respect, software systems differ profoundly from computers, buildings, or automobiles, where repeated elements abound. - Fred Brooks, Jr. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] configs: ls1021atwr: Enable ID EEPROM for SD boot
Hi york, The earlier SoC is just LS1021a rev1.0, but rev1.0 haven't delivery to the customer. Also the rev1.0 has since gone out of production. So we don't have necessary to support rev1.0 because no one will or possibly to use rev1.0. Best Regards, Yuan Yao > -Original Message- > From: York Sun [mailto:york...@freescale.com] > Sent: Thursday, October 15, 2015 5:22 AM > To: Yuan Yao-B46683 ; Wang Huan-B18965 > > Cc: u-boot@lists.denx.de > Subject: Re: [PATCH] configs: ls1021atwr: Enable ID EEPROM for SD boot > > On 09/23/2015 12:48 AM, Yuan Yao wrote: > > I2C1 can work on ls102xa rev2.0 SD boot, so add ID EEPROM for SD boot. > > > > Signed-off-by: Yuan Yao > > --- > > include/configs/ls1021atwr.h | 2 -- > > 1 file changed, 2 deletions(-) > > > > diff --git a/include/configs/ls1021atwr.h > > b/include/configs/ls1021atwr.h index 7dcb719..59e704e 100644 > > --- a/include/configs/ls1021atwr.h > > +++ b/include/configs/ls1021atwr.h > > @@ -278,7 +278,6 @@ > > #define CONFIG_SYS_I2C_MXC_I2C3/* enable I2C bus 3 */ > > > > /* EEPROM */ > > -#ifndef CONFIG_SD_BOOT > > #define CONFIG_ID_EEPROM > > #define CONFIG_SYS_I2C_EEPROM_NXID > > #define CONFIG_SYS_EEPROM_BUS_NUM 1 > > @@ -286,7 +285,6 @@ > > #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 > > #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 > > #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 > > -#endif > > > > /* > > * MMC > > > > What would happen if you run the new u-boot image on earlier SoC? Do you > need to check SVR in function mac_read_from_eeprom()? > > York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] mtd: nand: vf610_nfc: resync with upstream Linux version
On 15/10/2015 06:00, Scott Wood wrote: > On Wed, 2015-10-14 at 13:27 +0200, Albert ARIBAUD wrote: >> On Wed, 14 Oct 2015 13:21:41 +0200, Albert ARIBAUD (3ADEV) >> wrote: >>> Hello Stefan, >>> >>> On Tue, 13 Oct 2015 22:11:42 -0700, Stefan Agner >>> wrote: This resyncs the driver changes with the Linux version of the driver. The driver received some feedback in the LKML and got recently acceppted, the latest version can be found here: https://lkml.org/lkml/2015/9/2/678 Notable changes are: - On ECC error, reread OOB and count bit flips in OOB too. If flipped bits are below threshold, also return an empty OOB buffer. - Return the amount of bit flips in vf610_nfc_read_page. - Use endianness aware vf610_nfc_read to read ECC status. - Do not enable IDLE IRQ (since we do not operate with an interrupt service routine). - Use type safe struct for buffer variants (vf610_nfc_alt_buf). - Renamed variables in struct vf610_nfc (column and page_sz) to reflect better what they really representing. The U-Boot version currently does not support RAW NAND write when using the HW ECC engine. Signed-off-by: Bhuvanchandra DV Signed-off-by: Stefan Agner >>> >>> Tested-by: Albert ARIBAUD (3ADEV) >> >> Putting Stefano Babic in To: list since this is IMX-like stuff. >> >> Stefano, >> >> I can pick this plus Stefan's other two and Anthony's vf610-related >> patches if you want, or you can. Either way, Tom will take them as they >> are essentially bugfixes. > > Acked-by: Scott Wood > Thanks Scott. I am picking this one and a couple of other patches and I will send my PR to Tom. Best regards, Stefano -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 01/16] spi: Add zynq qspi controller driver
Hi Jagan,
during bringing up QSPI within SPL on my ZYNQ ZC702 board i made some
review of your code.
Have a look.
On 01.09.2015 08:11, Jagan Teki wrote:
Added zynq qspi controller driver for Xilinx Zynq APSOC,
this driver is driver-model driven with devicetree support.
(...)
+
+/* zynq qspi priv */
+struct zynq_qspi_priv {
+ struct zynq_qspi_regs *regs;
+ u8 cs;
+ u8 mode;
+ u8 fifo_depth;
+ u32 freq; /* required frequency */
+ const void *tx_buf;
+ void *rx_buf;
+ unsigned len;
+ int bytes_to_transfer;
+ int bytes_to_receive;
+ unsigned int is_inst;
+ unsigned cs_change:1;
+};
why not use "u32" for len ?
+static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv)
+{
+ struct zynq_qspi_regs *regs = priv->regs;
+ u32 confr;
During bring up this driver within SPL i've figured out, that it is very
important to do a clear reset to the QSPI unit.
Initially the ROM codes fetches our SPL-binary from the flash into the
OCM and executes.
We don't know at this point how ROM-code has left the QSPI unit, and
have to reset the Unit using responsible Bits in sclr area.
Otherwise we can see strange behaviours like hang on reading RxFIFO
sometimes and sometimes not.
+
+ /* Disable QSPI */
+ writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr);
+
+ /* Disable Interrupts */
+ writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->idr);
+
+ /* Clear the TX and RX threshold reg */
+ writel(ZYNQ_QSPI_TXFIFO_THRESHOLD, ®s->txftr);
+ writel(ZYNQ_QSPI_RXFIFO_THRESHOLD, ®s->rxftr);
+
+ /* Clear the RX FIFO */
+ while (readl(®s->isr) & ZYNQ_QSPI_IXR_RXNEMPTY_MASK)
+ readl(®s->drxr);
+
+ /* Clear Interrupts */
+ writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->isr);
+
+ /* Manual slave select and Auto start */
+ confr = readl(®s->cr);
+ confr &= ~ZYNQ_QSPI_CR_MSA_MASK;
+ confr |= ZYNQ_QSPI_CR_IFMODE_MASK | ZYNQ_QSPI_CR_MCS_MASK |
+ ZYNQ_QSPI_CR_PCS_MASK | ZYNQ_QSPI_CR_FW_MASK |
+ ZYNQ_QSPI_CR_MSTREN_MASK;
+ writel(confr, ®s->cr);
+
+ /* Enable SPI */
+ writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr);
+}
(...)
+
+/*
+ * zynq_qspi_read_data - Copy data to RX buffer
+ * @zqspi: Pointer to the zynq_qspi structure
+ * @data: The 32 bit variable where data is stored
+ * @size: Number of bytes to be copied from data to RX buffer
+ */
+static void zynq_qspi_read_data(struct zynq_qspi_priv *priv, u32 data, u8 size)
+{
+ u8 byte3;
+
+ debug("%s: data 0x%04x rx_buf addr: 0x%08x size %d\n", __func__ ,
+ data, (unsigned)(priv->rx_buf), size);
use 0x%p instead 0x%08x to display pointer addresses, with the advantage
that no cast is necessary.
+
+ if (priv->rx_buf) {
+ switch (size) {
+ case 1:
+ *((u8 *)priv->rx_buf) = data;
+ priv->rx_buf += 1;
+ break;
+ case 2:
+ *((u16 *)priv->rx_buf) = data;
+ priv->rx_buf += 2;
+ break;
+ case 3:
+ *((u16 *)priv->rx_buf) = data;
+ priv->rx_buf += 2;
+ byte3 = (u8)(data >> 16);
+ *((u8 *)priv->rx_buf) = byte3;
+ priv->rx_buf += 1;
+ break;
+ case 4:
+ /* Can not assume word aligned buffer */
+ memcpy(priv->rx_buf, &data, size);
+ priv->rx_buf += 4;
+ break;
+ default:
+ /* This will never execute */
+ break;
+ }
+ }
+ priv->bytes_to_receive -= size;
+ if (priv->bytes_to_receive < 0)
+ priv->bytes_to_receive = 0;
+}
wouldn't it be good enough using always "memcpy" ?
maybe we can drop this function completely ?
+
+/*
+ * zynq_qspi_write_data - Copy data from TX buffer
+ * @zqspi: Pointer to the zynq_qspi structure
+ * @data: Pointer to the 32 bit variable where data is to be copied
+ * @size: Number of bytes to be copied from TX buffer to data
+ */
+static void zynq_qspi_write_data(struct zynq_qspi_priv *priv,
+ u32 *data, u8 size)
+{
+ if (priv->tx_buf) {
+ switch (size) {
+ case 1:
+ *data = *((u8 *)priv->tx_buf);
+ priv->tx_buf += 1;
+ *data |= 0xFF00;
+ break;
+ case 2:
+ *data = *((u16 *)priv->tx_buf);
+ priv->tx_buf += 2;
+ *data |= 0x;
+ break;
+ case 3:
+ *data = *((u16 *)priv->tx_buf);
+ priv->tx_buf += 2;
+
Re: [U-Boot] [PATCH v4] pci: pcie_imx: Fix hang on mx6qp
On 13/10/2015 16:01, Fabio Estevam wrote:
> PCI driver currently hangs on mx6qp.
>
> Toggle the reset bit with the appropriate timings to fix the issue.
>
> Based on the FSL kernel driver implementation.
>
> Signed-off-by: Fabio Estevam
> ---
> Changes since v3:
> - Remove blank line from commit log
> Changes since v2:
> - Remove unneeded blank line (Bin)
>
> arch/arm/include/asm/arch-mx6/iomux.h | 2 ++
> drivers/pci/pcie_imx.c| 8
> 2 files changed, 10 insertions(+)
>
> diff --git a/arch/arm/include/asm/arch-mx6/iomux.h
> b/arch/arm/include/asm/arch-mx6/iomux.h
> index 9b3a91f..907cb40 100644
> --- a/arch/arm/include/asm/arch-mx6/iomux.h
> +++ b/arch/arm/include/asm/arch-mx6/iomux.h
> @@ -18,6 +18,8 @@
> #define IOMUXC_GPR1_REF_SSP_EN (1 << 16)
> #define IOMUXC_GPR1_TEST_POWERDOWN (1 << 18)
>
> +#define IOMUXC_GPR1_PCIE_SW_RST (1 << 29)
> +
> /*
> * IOMUXC_GPR5 bit fields
> */
> diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c
> index 1568f20..f1e189e 100644
> --- a/drivers/pci/pcie_imx.c
> +++ b/drivers/pci/pcie_imx.c
> @@ -19,6 +19,7 @@
> #include
> #include
> #include
> +#include
>
> #define PCI_ACCESS_READ 0
> #define PCI_ACCESS_WRITE 1
> @@ -430,6 +431,10 @@ static int imx_pcie_write_config(struct pci_controller
> *hose, pci_dev_t d,
> static int imx6_pcie_assert_core_reset(void)
> {
> struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
> +
> + if (is_mx6dqp())
> + setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
> +
> #if defined(CONFIG_MX6SX)
> struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
>
> @@ -536,6 +541,9 @@ static int imx6_pcie_deassert_core_reset(void)
>
> enable_pcie_clock();
>
> + if (is_mx6dqp())
> + clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
> +
> /*
>* Wait for the clock to settle a bit, when the clock are sourced
>* from the CPU, we need about 30 ms to settle.
>
Thanks Fabio - as fix, I pick it up for the release.
Acked-by: Stefano Babic
Best regards,
Stefano Babic
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Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
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[U-Boot] [PATCH 2/2] armv8: ls2085a: Add support of LS2085A SoC
From: Pratiyush Mohan Srivastava
Freescale's LS2085A is a another personality of LS2080A SoC with
support of AIOP and DP-DDR.
This Patch adds support of LS2085A Personality.
Signed-off-by: Pratiyush Mohan Srivastava
---
arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 4 +++-
arch/arm/cpu/armv8/fsl-lsch3/ls2080a_serdes.c | 5 +
arch/arm/include/asm/arch-fsl-lsch3/config.h| 8 ++--
configs/ls2080a_emu_defconfig | 3 +--
configs/ls2080a_simu_defconfig | 3 +--
configs/ls2080aqds_defconfig| 3 +--
configs/ls2080aqds_nand_defconfig | 3 +--
configs/ls2080ardb_defconfig| 3 +--
configs/ls2080ardb_nand_defconfig | 3 +--
configs/{ls2080a_emu_defconfig => ls2085a_emu_defconfig}| 3 +--
configs/{ls2080a_simu_defconfig => ls2085a_simu_defconfig} | 3 +--
configs/{ls2080aqds_defconfig => ls2085aqds_defconfig} | 3 +--
...{ls2080aqds_nand_defconfig => ls2085aqds_nand_defconfig} | 3 +--
configs/{ls2080ardb_defconfig => ls2085ardb_defconfig} | 3 +--
...{ls2080ardb_nand_defconfig => ls2085ardb_nand_defconfig} | 3 +--
drivers/ddr/fsl/fsl_ddr_gen4.c | 4 ++--
drivers/mmc/fsl_esdhc.c | 13 +++--
drivers/pci/pcie_layerscape.c | 2 +-
include/fsl_esdhc.h | 2 +-
include/linux/usb/xhci-fsl.h| 2 +-
20 files changed, 38 insertions(+), 38 deletions(-)
copy configs/{ls2080a_emu_defconfig => ls2085a_emu_defconfig} (86%)
copy configs/{ls2080a_simu_defconfig => ls2085a_simu_defconfig} (88%)
copy configs/{ls2080aqds_defconfig => ls2085aqds_defconfig} (82%)
copy configs/{ls2080aqds_nand_defconfig => ls2085aqds_nand_defconfig} (65%)
copy configs/{ls2080ardb_defconfig => ls2085ardb_defconfig} (82%)
copy configs/{ls2080ardb_nand_defconfig => ls2085ardb_nand_defconfig} (65%)
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
index b219c76..c9cc112 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
@@ -28,8 +28,10 @@ static struct cpu_type cpu_type_list[] = {
#ifdef CONFIG_LS2080A
CPU_TYPE_ENTRY(LS2080, LS2080, 8),
#endif
+#ifdef CONFIG_LS2085A
CPU_TYPE_ENTRY(LS2085, LS2085, 8),
CPU_TYPE_ENTRY(LS2045, LS2045, 4),
+#endif
};
void cpu_name(char *name)
@@ -174,7 +176,7 @@ static const struct sys_mmu_table lsch3_final_mmu_table[] =
{
CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
-#ifdef CONFIG_LS2080A
+#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
{ CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
#endif
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/ls2080a_serdes.c
b/arch/arm/cpu/armv8/fsl-lsch3/ls2080a_serdes.c
index 64da31c..6256721 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/ls2080a_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/ls2080a_serdes.c
@@ -29,7 +29,12 @@ static struct serdes_config serdes1_cfg_tbl[] = {
SGMII1 } },
{0x26, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, XFI2, XFI1 } },
{0x28, {SGMII8, SGMII7, SGMII6, SGMII5, XFI4, XFI3, XFI2, XFI1 } },
+#ifdef CONFIG_LS2080A
{0x2A, {NONE, NONE, NONE, XFI5, XFI4, XFI3, XFI2, XFI1 } },
+#endif
+#ifdef CONFIG_LS2085A
+ {0x2A, {XFI8, XFI7, XFI6, XFI5, XFI4, XFI3, XFI2, XFI1 } },
+#endif
{0x2B, {SGMII8, SGMII7, SGMII6, SGMII5, XAUI1, XAUI1, XAUI1, XAUI1 } },
{0x32, {XAUI2, XAUI2, XAUI2, XAUI2, XAUI1, XAUI1, XAUI1, XAUI1 } },
{0x33, {PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_C, QSGMII_D, QSGMII_A,
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h
b/arch/arm/include/asm/arch-fsl-lsch3/config.h
index 78562ea..0733852 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/config.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h
@@ -163,7 +163,11 @@
#define SCFG_BASE 0x01fc
#define SCFG_USB3PRM1CR0x000
-#ifdef CONFIG_LS2080A
+#ifdef CONFIG_LS2085A
+#define CONFIG_SYS_FSL_HAS_DP_DDR
+#endif
+
+#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
#define CONFIG_MAX_CPUS16
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_NUM_DDR_CONTROLLERS 3
@@ -174,7 +178,7 @@
#error SoC not defined
#endif
-#ifdef CONFIG_LS2080A
+#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
#define CONFIG_SYS_FSL_ERRATUM_A008336
#define CONFIG_SYS_FSL_ERRATUM_A008511
#define CONFIG_SYS_FSL_ERRATUM_A008514
diff --git a/c
Re: [U-Boot] [PATCH] colibri_vf: Fix bstlen field
On 14/10/2015 04:54, Fabio Estevam wrote:
> From: Fabio Estevam
>
> Commit 3f353cecc ("vf610: refactor DDRMC code") changed the original
> bstlen field from 3 to 0.
>
> Restore the original value for proper behaviour.
>
> Based on the patch from Anthony Felice
> for the vf610twr board.
>
> Reported-by: Stefan Agner
> Signed-off-by: Fabio Estevam
> ---
> board/toradex/colibri_vf/colibri_vf.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/board/toradex/colibri_vf/colibri_vf.c
> b/board/toradex/colibri_vf/colibri_vf.c
> index 39bf0ac..a6d1c5b 100644
> --- a/board/toradex/colibri_vf/colibri_vf.c
> +++ b/board/toradex/colibri_vf/colibri_vf.c
> @@ -119,7 +119,7 @@ int dram_init(void)
> .trcd_int = 6,
> .tras_lockout = 0,
> .tdal = 12,
> - .bstlen= 0,
> + .bstlen= 3,
> .tdll = 512,
> .trp_ab= 6,
> .tref = 3120,
>
As result from previous thread "vf610twr: Fix typo in DRAM init"
Applied as fix to u-boot-imx, thanks !
Best regards,
Stefano Babic
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Re: [U-Boot] [ANN] U-Boot v2015.10-rc5 released
Hi Wolfgang, Tom, On Thu, Oct 15, 2015 at 9:28 AM, Wolfgang Denk wrote: > Dear Tom, > > In message <20151015004002.GX23893@bill-the-cat> you wrote: >> >> I'm just not sure what to do about CONFIG_API some days. I know one use >> case is for GRUB but I'd like to move away from that if possible >> (distros should be doing the generic distro bits and extlinux.conf). >> After that, I'm only hazily aware of the real use-cases. > > The major use case (as I understand it) are the FreeBSD users > who need this API for booting. I'm adding Rafal and Bartek to Cc: > as they should know best if this interface is still in wide use. Indeed, it's actively and widely used by the FreeBSD [last stage] bootloader. Thanks, Rafal ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] arm: vf610twr: improve memory layout
Hi Stefan, On 14/10/2015 19:58, Stefan Agner wrote: > Currently, the device tree relocation is disabled, likely to > keep some DDR3 RAM at the end for Cortex-M4 firmwares. This > can be archived using bootm_size, which limits the image > processing range of the boot commands. > > Move the device tree standard load address to a higher address > which aligns better with what we are doing on other boards. > > Signed-off-by: Stefan Agner > --- > So this is the second version of the patch "arm: vf610: move > device tree after kernel image" which makes use of bootm_size. > I also added an appropriate comment, added variables for > RAM disk, and added kernel_addr_r/fdt_addr_r. > > -- > Stefan > > include/configs/vf610twr.h | 27 +-- > 1 file changed, 21 insertions(+), 6 deletions(-) > > diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h > index 324ba8f..7f4260a 100644 > --- a/include/configs/vf610twr.h > +++ b/include/configs/vf610twr.h > @@ -116,20 +116,37 @@ > > #define CONFIG_BOOTDELAY 3 > > -#define CONFIG_LOADADDR 0x8200 > +#define CONFIG_SYS_LOAD_ADDR 0x8200 > > /* We boot from the gfxRAM area of the OCRAM. */ > #define CONFIG_SYS_TEXT_BASE 0x3f408000 > #define CONFIG_BOARD_SIZE_LIMIT 524288 > > +/* > + * We do have 128MB of memory on the Vybrid Tower board. Leave the last > + * 16MB alone to avoid conflicts with Cortex-M4 firmwares running from > + * DDR3. Hence, limit the memory range for image processing to 112MB > + * using bootm_size. All of the following must be within this range. > + * We have the default load at 32MB into DDR (for the kernel), FDT at > + * 64MB and the ramdisk 512KB above that (allowing for hopefully never > + * seen large trees). This allows a reasonable split between ramdisk > + * and kernel size, where the ram disk can be a bit larger. > + */ > +#define MEM_LAYOUT_ENV_SETTINGS \ > + "bootm_size=0x0700\0" \ > + "loadaddr=0x8200\0" \ > + "kernel_addr_r=0x8200\0" \ > + "fdt_addr=0x8400\0" \ > + "fdt_addr_r=0x8400\0" \ > + "rdaddr=0x8408\0" \ > + "ramdisk_addr_r=0x8408\0" > + > #define CONFIG_EXTRA_ENV_SETTINGS \ > + MEM_LAYOUT_ENV_SETTINGS \ > "script=boot.scr\0" \ > "image=zImage\0" \ > "console=ttyLP1\0" \ > - "fdt_high=0x\0" \ > - "initrd_high=0x\0" \ > "fdt_file=vf610-twr.dtb\0" \ > - "fdt_addr=0x8100\0" \ > "boot_fdt=try\0" \ > "ip_dyn=yes\0" \ > "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ > @@ -224,8 +241,6 @@ > #define CONFIG_SYS_MEMTEST_START 0x8001 > #define CONFIG_SYS_MEMTEST_END 0x87C0 > > -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR > - > /* > * Stack sizes > * The stack sizes are set up in start.S using the settings below > I can still push it into release. Applied (fix) to u-boot-imx, thanks ! Best regards, Stefano Babic -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] armv8: LS2080A: Rename LS2085A to reflect LS2080A
From: Pratiyush Mohan Srivastava
LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP
personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc.
So renaming existing LS2085A code base to reflect LS2080A (Prime personality)
Signed-off-by: Pratiyush Mohan Srivastava
---
README | 3 +
arch/arm/Kconfig | 44 +++
arch/arm/cpu/armv8/fsl-lsch3/Makefile | 2 +-
arch/arm/cpu/armv8/fsl-lsch3/README| 4 +-
arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 10 ++-
arch/arm/cpu/armv8/fsl-lsch3/fdt.c | 2 +-
.../{ls2085a_serdes.c => ls2080a_serdes.c} | 2 +-
arch/arm/cpu/armv8/fsl-lsch3/speed.c | 10 +++
arch/arm/dts/Makefile | 4 +-
.../{fsl-ls2085a-qds.dts => fsl-ls2080a-qds.dts} | 8 +-
.../{fsl-ls2085a-rdb.dts => fsl-ls2080a-rdb.dts} | 8 +-
.../arm/dts/{fsl-ls2085a.dtsi => fsl-ls2080a.dtsi} | 4 +-
arch/arm/include/asm/arch-fsl-lsch3/config.h | 8 +-
arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h | 2 +
.../{ls2085a_stream_id.h => ls2080a_stream_id.h} | 4 +-
arch/arm/include/asm/global_data.h | 2 +-
board/freescale/{ls2085a => ls2080a}/Kconfig | 12 +--
board/freescale/ls2080a/MAINTAINERS| 8 ++
board/freescale/{ls2085a => ls2080a}/Makefile | 2 +-
board/freescale/{ls2085a => ls2080a}/README| 2 +-
board/freescale/{ls2085a => ls2080a}/ddr.c | 3 +-
board/freescale/{ls2085a => ls2080a}/ddr.h | 0
.../{ls2085a/ls2085a.c => ls2080a/ls2080a.c} | 4 +-
board/freescale/{ls2085aqds => ls2080aqds}/Kconfig | 6 +-
board/freescale/ls2080aqds/MAINTAINERS | 8 ++
.../freescale/{ls2085aqds => ls2080aqds}/Makefile | 2 +-
board/freescale/{ls2085aqds => ls2080aqds}/README | 16 ++--
board/freescale/{ls2085aqds => ls2080aqds}/ddr.c | 5 +-
board/freescale/{ls2085aqds => ls2080aqds}/ddr.h | 0
board/freescale/{ls2085aqds => ls2080aqds}/eth.c | 92 +++---
.../ls2085aqds.c => ls2080aqds/ls2080aqds.c} | 6 +-
.../ls2080aqds_qixis.h}| 0
board/freescale/{ls2085ardb => ls2080ardb}/Kconfig | 6 +-
board/freescale/ls2080ardb/MAINTAINERS | 8 ++
.../freescale/{ls2085ardb => ls2080ardb}/Makefile | 2 +-
board/freescale/{ls2085ardb => ls2080ardb}/README | 12 +--
board/freescale/{ls2085ardb => ls2080ardb}/ddr.c | 5 +-
board/freescale/{ls2085ardb => ls2080ardb}/ddr.h | 0
.../eth_ls2085rdb.c => ls2080ardb/eth_ls2080rdb.c} | 2 +-
.../ls2085ardb.c => ls2080ardb/ls2080ardb.c} | 6 +-
.../ls2080ardb_qixis.h}| 0
board/freescale/ls2085a/MAINTAINERS| 8 --
board/freescale/ls2085aqds/MAINTAINERS | 8 --
board/freescale/ls2085ardb/MAINTAINERS | 8 --
...ls2085a_emu_defconfig => ls2080a_emu_defconfig} | 3 +-
...2085a_simu_defconfig => ls2080a_simu_defconfig} | 3 +-
.../{ls2085ardb_defconfig => ls2080aqds_defconfig} | 5 +-
...ds_nand_defconfig => ls2080aqds_nand_defconfig} | 3 +-
.../{ls2085aqds_defconfig => ls2080ardb_defconfig} | 5 +-
...db_nand_defconfig => ls2080ardb_nand_defconfig} | 3 +-
doc/README.fsl-trustzone-components| 4 +-
drivers/ddr/fsl/fsl_ddr_gen4.c | 4 +-
drivers/mmc/fsl_esdhc.c| 12 +--
drivers/net/ldpaa_eth/Makefile | 2 +-
drivers/net/ldpaa_eth/{ls2085a.c => ls2080a.c} | 0
drivers/pci/pcie_layerscape.c | 2 +-
.../configs/{ls2085a_common.h => ls2080a_common.h} | 7 +-
include/configs/{ls2085a_emu.h => ls2080a_emu.h} | 8 +-
include/configs/{ls2085a_simu.h => ls2080a_simu.h} | 8 +-
include/configs/{ls2085aqds.h => ls2080aqds.h} | 4 +-
include/configs/{ls2085ardb.h => ls2080ardb.h} | 4 +-
include/fsl_esdhc.h| 2 +-
include/linux/usb/xhci-fsl.h | 6 +-
63 files changed, 241 insertions(+), 192 deletions(-)
rename arch/arm/cpu/armv8/fsl-lsch3/{ls2085a_serdes.c => ls2080a_serdes.c}
(98%)
rename arch/arm/dts/{fsl-ls2085a-qds.dts => fsl-ls2080a-qds.dts} (80%)
rename arch/arm/dts/{fsl-ls2085a-rdb.dts => fsl-ls2080a-rdb.dts} (67%)
rename arch/arm/dts/{fsl-ls2085a.dtsi => fsl-ls2080a.dtsi} (97%)
rename arch/arm/include/asm/arch-fsl-lsch3/{ls2085a_stream_id.h =>
ls2080a_stream_id.h} (93%)
rename board/freescale/{ls2085a => ls2080a}/Kconfig (66%)
create mode 100644 board/freescale/ls2080a/MAINTAINERS
rename board/freescale/{ls2085a => ls2080a}/Makefile (83%)
rename board/freescale/{ls2085a => ls2080a}/README (97%)
rename board/freescale/{ls2085a => ls2080a}/ddr.c (99%)
rename board/freescale/{ls2085a => ls2080a}/ddr.h (100%)
rename board/freescale/{ls2085a/ls2085a.c => ls2080a/ls2080a.c} (98%)
rename board/freescale/{ls2085
[U-Boot] [PULL] Please pull u-boot-imx
Hi Tom, I have a couple of last-minute fixes for the vfr610twr. Please pull them from u-boot-imx, thanks ! The following changes since commit 61903b759aa336d798da49d884467219796817ff: imximage: fix commands other than write_data (2015-10-07 13:43:15 +0200) are available in the git repository at: git://www.denx.de/git/u-boot-imx.git master for you to fetch changes up to cf04ad3219260c3c39ec3dbfe2427e3463e8dbd5: arm: vf610twr: improve memory layout (2015-10-15 11:22:07 +0200) Fabio Estevam (1): colibri_vf: Fix bstlen field Stefan Agner (2): mtd: nand: vf610_nfc: resync with upstream Linux version arm: vf610twr: improve memory layout board/toradex/colibri_vf/colibri_vf.c | 2 +- drivers/mtd/nand/vf610_nfc.c | 247 +++--- include/configs/vf610twr.h| 27 +++- 3 files changed, 160 insertions(+), 116 deletions(-) -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/1] imx: mx6sabresd: add i.MX6DQP Sabresd support
Add i.MX6DQP-Sabresd board support:
1. set fdt_file according to board_rev which is set at runtime.
2. Add mx6dqp_ddr_ioregs and calibration value for this board.
Signed-off-by: Peng Fan
Cc: Stefano Babic
Cc: Fabio Estevam
---
Before this patch needs to apply "pci: pcie_imx: Fix hang on mx6qp" from Fabio.
http://lists.denx.de/pipermail/u-boot/2015-October/230018.html.
board/freescale/mx6sabresd/mx6sabresd.c | 69 ++---
include/configs/mx6sabre_common.h | 2 +
2 files changed, 65 insertions(+), 6 deletions(-)
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c
b/board/freescale/mx6sabresd/mx6sabresd.c
index 5644167..5b0b83e 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -684,7 +684,9 @@ int board_late_init(void)
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
setenv("board_name", "SABRESD");
- if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+ if (is_mx6dqp())
+ setenv("board_rev", "MX6QP");
+ else if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
setenv("board_rev", "MX6Q");
else if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO))
setenv("board_rev", "MX6DL");
@@ -732,6 +734,35 @@ const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
.dram_dqm7 = 0x00020030,
};
+const struct mx6dq_iomux_ddr_regs mx6dqp_ddr_ioregs = {
+ .dram_sdclk_0 = 0x0030,
+ .dram_sdclk_1 = 0x0030,
+ .dram_cas = 0x0030,
+ .dram_ras = 0x0030,
+ .dram_reset = 0x0030,
+ .dram_sdcke0 = 0x3000,
+ .dram_sdcke1 = 0x3000,
+ .dram_sdba2 = 0x,
+ .dram_sdodt0 = 0x3030,
+ .dram_sdodt1 = 0x3030,
+ .dram_sdqs0 = 0x0030,
+ .dram_sdqs1 = 0x0030,
+ .dram_sdqs2 = 0x0030,
+ .dram_sdqs3 = 0x0030,
+ .dram_sdqs4 = 0x0030,
+ .dram_sdqs5 = 0x0030,
+ .dram_sdqs6 = 0x0030,
+ .dram_sdqs7 = 0x0030,
+ .dram_dqm0 = 0x0030,
+ .dram_dqm1 = 0x0030,
+ .dram_dqm2 = 0x0030,
+ .dram_dqm3 = 0x0030,
+ .dram_dqm4 = 0x0030,
+ .dram_dqm5 = 0x0030,
+ .dram_dqm6 = 0x0030,
+ .dram_dqm7 = 0x0030,
+};
+
const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
.grp_ddr_type = 0x000C,
.grp_ddrmode_ctl = 0x0002,
@@ -764,6 +795,21 @@ const struct mx6_mmdc_calibration mx6_mmcd_calib = {
.p1_mpwrdlctl = 0x48254A36,
};
+const struct mx6_mmdc_calibration mx6dqp_mmcd_calib = {
+ .p0_mpwldectrl0 = 0x001B001E,
+ .p0_mpwldectrl1 = 0x002E0029,
+ .p1_mpwldectrl0 = 0x001B002A,
+ .p1_mpwldectrl1 = 0x0019002C,
+ .p0_mpdgctrl0 = 0x43240334,
+ .p0_mpdgctrl1 = 0x0324031A,
+ .p1_mpdgctrl0 = 0x43340344,
+ .p1_mpdgctrl1 = 0x03280276,
+ .p0_mprddlctl = 0x44383A3E,
+ .p1_mprddlctl = 0x3C3C3846,
+ .p0_mpwrdlctl = 0x2E303230,
+ .p1_mpwrdlctl = 0x38283E34,
+};
+
/* MT41K128M16JT-125 */
static struct mx6_ddr3_cfg mem_ddr = {
.mem_speed = 1600,
@@ -797,9 +843,15 @@ static void gpr_init(void)
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF0CF, &iomux->gpr[4]);
- /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
- writel(0x007F007F, &iomux->gpr[6]);
- writel(0x007F007F, &iomux->gpr[7]);
+ if (is_mx6dqp()) {
+ /* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
+ writel(0x007F007F, &iomux->gpr[6]);
+ writel(0x007F007F, &iomux->gpr[7]);
+ } else {
+ /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+ writel(0x007F007F, &iomux->gpr[6]);
+ writel(0x007F007F, &iomux->gpr[7]);
+ }
}
/*
@@ -827,8 +879,13 @@ static void spl_dram_init(void)
.ddr_type = DDR_TYPE_DDR3,
};
- mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
- mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
+ if (is_mx6dqp()) {
+ mx6dq_dram_iocfg(64, &mx6dqp_ddr_ioregs, &mx6_grp_ioregs);
+ mx6_dram_cfg(&sysinfo, &mx6dqp_mmcd_calib, &mem_ddr);
+ } else {
+ mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+ mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
+ }
}
void board_init_f(ulong dummy)
diff --git a/include/configs/mx6sabre_common.h
b/include/configs/mx6sabre_common.h
index 9dcc64e..3e045ef 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -158,6 +158,8 @@
"setenv fdt_file imx6q-sabreauto.dtb;
fi; " \
"if test $board_name = SABREAUTO && test
$board_rev = MX6DL; then " \
"setenv fdt_file imx6d
[U-Boot] [PATCH 1/1] imx: mx6sabresd discard PHYS_SDRAM_SIZE
This macro is not needed, since gd->ram_size is assigned value using function imx_ddr_size(). Signed-off-by: Peng Fan Cc: Stefano Babic Cc: Fabio Estevam --- include/configs/mx6sabresd.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index e9e3b27..bfc4f61 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -19,7 +19,6 @@ #define CONFIG_MXC_UART_BASE UART1_BASE #define CONFIG_CONSOLE_DEV "ttymxc0" #define CONFIG_MMCROOT "/dev/mmcblk1p2" -#define PHYS_SDRAM_SIZE(1u * 1024 * 1024 * 1024) #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ -- 1.8.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/1] imx: ddr: drop duplicated debug info
Drop duplicated debug info for tcl.
Signed-off-by: Peng Fan
Cc: Stefano Babic
---
arch/arm/cpu/armv7/mx6/ddr.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index 6b039e4..567ddc4 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -796,7 +796,6 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
debug("Rtt_wr=%d\n", sysinfo->rtt_wr);
debug("Rtt_nom=%d\n", sysinfo->rtt_nom);
debug("SRT=%d\n", ddr3_cfg->SRT);
- debug("tcl=%d\n", tcl);
debug("twr=%d\n", twr);
/*
--
1.8.4
___
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[U-Boot] [PATCH v2] arm: ls1021a: Add QSPI or IFC support in SD boot
As QSPI and IFC are pin-multiplexed on LS1021A, only IFC is supported in
SD boot now. For the customer's demand, QSPI needs to be supported in SD
boot too.
This patch adds QSPI or IFC support in SD boot according to the
corresponding defconfig. For detail, ls1021atwr_sdcard_ifc_defconfig is
used to support IFC in SD boot and ls1021atwr_sdcard_qspi_defconfig is
used to support QSPI in SD boot.
Signed-off-by: Alison Wang
---
Changes in v2:
- Fix checkpatch warnings about line over 80 characters.
Makefile | 4
board/freescale/ls1021atwr/MAINTAINERS | 3 ++-
board/freescale/ls1021atwr/ls1021atwr.c| 14 +++---
board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg | 14 --
board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg | 8
board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg | 8
configs/ls1021atwr_sdcard_defconfig| 7 ---
configs/ls1021atwr_sdcard_ifc_defconfig| 6 ++
configs/ls1021atwr_sdcard_qspi_defconfig | 11 +++
include/configs/ls1021atwr.h | 19 ---
10 files changed, 62 insertions(+), 32 deletions(-)
delete mode 100644 board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg
create mode 100644 board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
create mode 100644 board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
delete mode 100644 configs/ls1021atwr_sdcard_defconfig
create mode 100644 configs/ls1021atwr_sdcard_ifc_defconfig
create mode 100644 configs/ls1021atwr_sdcard_qspi_defconfig
diff --git a/Makefile b/Makefile
index 8c0ca1b..b12a7e8 100644
--- a/Makefile
+++ b/Makefile
@@ -1120,7 +1120,11 @@ spl/u-boot-spl.pbl: spl/u-boot-spl.bin FORCE
$(call if_changed,mkimage)
ifeq ($(ARCH),arm)
+ifdef CONFIG_DM
+UBOOT_BINLOAD := u-boot-dtb.img
+else
UBOOT_BINLOAD := u-boot.img
+endif
else
UBOOT_BINLOAD := u-boot.bin
endif
diff --git a/board/freescale/ls1021atwr/MAINTAINERS
b/board/freescale/ls1021atwr/MAINTAINERS
index e9f6f0a..b997bb0 100644
--- a/board/freescale/ls1021atwr/MAINTAINERS
+++ b/board/freescale/ls1021atwr/MAINTAINERS
@@ -6,5 +6,6 @@ F: include/configs/ls1021atwr.h
F: configs/ls1021atwr_nor_defconfig
F: configs/ls1021atwr_nor_SECURE_BOOT_defconfig
F: configs/ls1021atwr_nor_lpuart_defconfig
-F: configs/ls1021atwr_sdcard_defconfig
+F: configs/ls1021atwr_sdcard_ifc_defconfig
+F: configs/ls1021atwr_sdcard_qspi_defconfig
F: configs/ls1021atwr_qspi_defconfig
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c
b/board/freescale/ls1021atwr/ls1021atwr.c
index 228dbf8..9d3457b 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -175,7 +175,7 @@ struct cpld_data {
u8 rev2;/* Reserved */
};
-#ifndef CONFIG_QSPI_BOOT
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
static void convert_serdes_mux(int type, int need_reset);
void cpld_show(void)
@@ -216,7 +216,7 @@ void cpld_show(void)
int checkboard(void)
{
puts("Board: LS1021ATWR\n");
-#ifndef CONFIG_QSPI_BOOT
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
cpld_show();
#endif
@@ -380,7 +380,7 @@ int board_eth_init(bd_t *bis)
}
#endif
-#ifndef CONFIG_QSPI_BOOT
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
int config_serdes_mux(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -414,7 +414,7 @@ int config_serdes_mux(void)
}
#endif
-#ifndef CONFIG_QSPI_BOOT
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
int config_board_mux(void)
{
struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
@@ -627,7 +627,7 @@ int board_init(void)
{
#ifndef CONFIG_SYS_FSL_NO_SERDES
fsl_serdes_init();
-#ifndef CONFIG_QSPI_BOOT
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
config_serdes_mux();
#endif
#endif
@@ -657,7 +657,7 @@ int misc_init_r(void)
#ifdef CONFIG_FSL_DEVICE_DISABLE
device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
#endif
-#ifndef CONFIG_QSPI_BOOT
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
config_board_mux();
#endif
@@ -706,7 +706,7 @@ u16 flash_read16(void *addr)
return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
}
-#ifndef CONFIG_QSPI_BOOT
+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
static void convert_flash_bank(char bank)
{
struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
diff --git a/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg
b/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg
deleted file mode 100644
index 9c3e3b0..000
--- a/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg
+++ /dev/null
@@ -1,14 +0,0 @@
-#PBL preamble and RCW header
-aa55aa55 01ee0100
-
-#enable IFC, disable QSPI and DSPI
-0608000a
-2000 004
Re: [U-Boot] [PATCH] arm: ls102xa: enable snooping for CAAM transactions
On 10/14/2015 11:54 PM, York Sun wrote:
>
>
> On 09/16/2015 03:22 AM, Horia Geantă wrote:
>> Enable snooping for CAAM read & write transactions by
>> programming the SCFG snoop configuration register:
>> SCFG_SNPCNFGCR[SECRDSNP]
>> SCFG_SNPCNFGCR[SECWRSNP]
>>
>> Signed-off-by: Horia Geantă
>> Reviewed-by: Zhengxiong Jin
>
> The Reviewed-by signature should be added by reviewer or maintainer.
It was added by Jason during an internal review.
Sorry for not adding him in Cc.
>> ---
>> arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 1 +
>> board/freescale/ls1021aqds/ls1021aqds.c | 2 ++
>> board/freescale/ls1021atwr/ls1021atwr.c | 2 ++
>> 3 files changed, 5 insertions(+)
>>
>> diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
>> b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
>> index 60aa0d3b6f43..fbd06bafce31 100644
>> --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
>> +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
>> @@ -144,6 +144,7 @@ struct ccsr_gur {
>> };
>>
>> #define SCFG_ETSECDMAMCR_LE_BD_FR 0x0c00
>> +#define SCFG_SNPCNFGCR_SEC_RD_WR0xc000
>> #define SCFG_ETSECCMCR_GE2_CLK125 0x0400
>> #define SCFG_ETSECCMCR_GE0_CLK125 0x
>> #define SCFG_ETSECCMCR_GE1_CLK125 0x0800
>> diff --git a/board/freescale/ls1021aqds/ls1021aqds.c
>> b/board/freescale/ls1021aqds/ls1021aqds.c
>> index 655fc644fe90..e7c25a5012f0 100644
>> --- a/board/freescale/ls1021aqds/ls1021aqds.c
>> +++ b/board/freescale/ls1021aqds/ls1021aqds.c
>> @@ -281,6 +281,8 @@ int board_early_init_f(void)
>> struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
>> unsigned int major;
>>
>> +setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR);
>> +
>> #ifdef CONFIG_TSEC_ENET
>> /* clear BD & FR bits for BE BD's and frame data */
>> clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
>> diff --git a/board/freescale/ls1021atwr/ls1021atwr.c
>> b/board/freescale/ls1021atwr/ls1021atwr.c
>> index 228dbf81bb25..e15999e42165 100644
>> --- a/board/freescale/ls1021atwr/ls1021atwr.c
>> +++ b/board/freescale/ls1021atwr/ls1021atwr.c
>> @@ -482,6 +482,8 @@ int board_early_init_f(void)
>> struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
>> unsigned int major;
>>
>> +setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR);
>> +
>> #ifdef CONFIG_TSEC_ENET
>> /* clear BD & FR bits for BE BD's and frame data */
>> clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
>>
>
> Why wasn't the change put into arch_cpu_init?
Good point.
I'll make the update in v2.
Thanks,
Horia
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[U-Boot] [PATCH 1/2] armv8: LS2080A: Rename LS2085A to reflect LS2080A
LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP
personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc.
So renaming existing LS2085A code base to reflect LS2080A (Prime personality)
Signed-off-by: Pratiyush Mohan Srivastava
---
README | 3 +
arch/arm/Kconfig | 44 +++
arch/arm/cpu/armv8/fsl-lsch3/Makefile | 2 +-
arch/arm/cpu/armv8/fsl-lsch3/README| 4 +-
arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 10 ++-
arch/arm/cpu/armv8/fsl-lsch3/fdt.c | 2 +-
.../{ls2085a_serdes.c => ls2080a_serdes.c} | 2 +-
arch/arm/cpu/armv8/fsl-lsch3/speed.c | 10 +++
arch/arm/dts/Makefile | 4 +-
.../{fsl-ls2085a-qds.dts => fsl-ls2080a-qds.dts} | 8 +-
.../{fsl-ls2085a-rdb.dts => fsl-ls2080a-rdb.dts} | 8 +-
.../arm/dts/{fsl-ls2085a.dtsi => fsl-ls2080a.dtsi} | 4 +-
arch/arm/include/asm/arch-fsl-lsch3/config.h | 8 +-
arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h | 2 +
.../{ls2085a_stream_id.h => ls2080a_stream_id.h} | 4 +-
arch/arm/include/asm/global_data.h | 2 +-
board/freescale/{ls2085a => ls2080a}/Kconfig | 12 +--
board/freescale/ls2080a/MAINTAINERS| 8 ++
board/freescale/{ls2085a => ls2080a}/Makefile | 2 +-
board/freescale/{ls2085a => ls2080a}/README| 2 +-
board/freescale/{ls2085a => ls2080a}/ddr.c | 3 +-
board/freescale/{ls2085a => ls2080a}/ddr.h | 0
.../{ls2085a/ls2085a.c => ls2080a/ls2080a.c} | 4 +-
board/freescale/{ls2085aqds => ls2080aqds}/Kconfig | 6 +-
board/freescale/ls2080aqds/MAINTAINERS | 8 ++
.../freescale/{ls2085aqds => ls2080aqds}/Makefile | 2 +-
board/freescale/{ls2085aqds => ls2080aqds}/README | 16 ++--
board/freescale/{ls2085aqds => ls2080aqds}/ddr.c | 5 +-
board/freescale/{ls2085aqds => ls2080aqds}/ddr.h | 0
board/freescale/{ls2085aqds => ls2080aqds}/eth.c | 92 +++---
.../ls2085aqds.c => ls2080aqds/ls2080aqds.c} | 6 +-
.../ls2080aqds_qixis.h}| 0
board/freescale/{ls2085ardb => ls2080ardb}/Kconfig | 6 +-
board/freescale/ls2080ardb/MAINTAINERS | 8 ++
.../freescale/{ls2085ardb => ls2080ardb}/Makefile | 2 +-
board/freescale/{ls2085ardb => ls2080ardb}/README | 12 +--
board/freescale/{ls2085ardb => ls2080ardb}/ddr.c | 5 +-
board/freescale/{ls2085ardb => ls2080ardb}/ddr.h | 0
.../eth_ls2085rdb.c => ls2080ardb/eth_ls2080rdb.c} | 2 +-
.../ls2085ardb.c => ls2080ardb/ls2080ardb.c} | 6 +-
.../ls2080ardb_qixis.h}| 0
board/freescale/ls2085a/MAINTAINERS| 8 --
board/freescale/ls2085aqds/MAINTAINERS | 8 --
board/freescale/ls2085ardb/MAINTAINERS | 8 --
...ls2085a_emu_defconfig => ls2080a_emu_defconfig} | 3 +-
...2085a_simu_defconfig => ls2080a_simu_defconfig} | 3 +-
.../{ls2085ardb_defconfig => ls2080aqds_defconfig} | 5 +-
...ds_nand_defconfig => ls2080aqds_nand_defconfig} | 3 +-
.../{ls2085aqds_defconfig => ls2080ardb_defconfig} | 5 +-
...db_nand_defconfig => ls2080ardb_nand_defconfig} | 3 +-
doc/README.fsl-trustzone-components| 4 +-
drivers/ddr/fsl/fsl_ddr_gen4.c | 4 +-
drivers/mmc/fsl_esdhc.c| 12 +--
drivers/net/ldpaa_eth/Makefile | 2 +-
drivers/net/ldpaa_eth/{ls2085a.c => ls2080a.c} | 0
drivers/pci/pcie_layerscape.c | 2 +-
.../configs/{ls2085a_common.h => ls2080a_common.h} | 7 +-
include/configs/{ls2085a_emu.h => ls2080a_emu.h} | 8 +-
include/configs/{ls2085a_simu.h => ls2080a_simu.h} | 8 +-
include/configs/{ls2085aqds.h => ls2080aqds.h} | 4 +-
include/configs/{ls2085ardb.h => ls2080ardb.h} | 4 +-
include/fsl_esdhc.h| 2 +-
include/linux/usb/xhci-fsl.h | 6 +-
63 files changed, 241 insertions(+), 192 deletions(-)
rename arch/arm/cpu/armv8/fsl-lsch3/{ls2085a_serdes.c => ls2080a_serdes.c}
(98%)
rename arch/arm/dts/{fsl-ls2085a-qds.dts => fsl-ls2080a-qds.dts} (80%)
rename arch/arm/dts/{fsl-ls2085a-rdb.dts => fsl-ls2080a-rdb.dts} (67%)
rename arch/arm/dts/{fsl-ls2085a.dtsi => fsl-ls2080a.dtsi} (97%)
rename arch/arm/include/asm/arch-fsl-lsch3/{ls2085a_stream_id.h =>
ls2080a_stream_id.h} (93%)
rename board/freescale/{ls2085a => ls2080a}/Kconfig (66%)
create mode 100644 board/freescale/ls2080a/MAINTAINERS
rename board/freescale/{ls2085a => ls2080a}/Makefile (83%)
rename board/freescale/{ls2085a => ls2080a}/README (97%)
rename board/freescale/{ls2085a => ls2080a}/ddr.c (99%)
rename board/freescale/{ls2085a => ls2080a}/ddr.h (100%)
rename board/freescale/{ls2085a/ls2085a.c => ls2080a/ls2080a.c} (98%)
rename board/freescale/{ls2085aqds => ls2080aqds}/Kconfig (66%)
[U-Boot] [PATCH v2] arm: ls102xa: enable snooping for CAAM transactions
Enable snooping for CAAM read & write transactions by
programming the SCFG snoop configuration register:
SCFG_SNPCNFGCR[SECRDSNP]
SCFG_SNPCNFGCR[SECWRSNP]
Signed-off-by: Horia Geantă
Reviewed-by: Zhengxiong Jin
---
v2 - moved initialization in arch_cpu_init (instead of board_early_init_f),
as suggested by York.
arch/arm/cpu/armv7/ls102xa/cpu.c | 3 +++
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index 8dd95d98791d..0f10ed656af8 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -299,6 +299,7 @@ int arch_cpu_init(void)
void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
void *rcpm2_base =
(void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
+ struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
u32 state;
/*
@@ -326,6 +327,8 @@ int arch_cpu_init(void)
*/
fsl_epu_clean(epu_base);
+ setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR);
+
return 0;
}
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 60aa0d3b6f43..fbd06bafce31 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -144,6 +144,7 @@ struct ccsr_gur {
};
#define SCFG_ETSECDMAMCR_LE_BD_FR 0x0c00
+#define SCFG_SNPCNFGCR_SEC_RD_WR 0xc000
#define SCFG_ETSECCMCR_GE2_CLK125 0x0400
#define SCFG_ETSECCMCR_GE0_CLK125 0x
#define SCFG_ETSECCMCR_GE1_CLK125 0x0800
--
2.4.4
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Re: [U-Boot] [PATCH] x86: Pass correct cpu_index to ap_init()
Hi Bin, On 14 October 2015 at 03:01, Bin Meng wrote: > > In sipi_vector.S, cpu_index (passed as %eax) is wrongly overwritten > by the ap_init() function address. Correct it. > > Signed-off-by: Bin Meng > --- > > arch/x86/cpu/sipi_vector.S | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Acked-by: Simon Glass I wonder if this value is even useful, but we do use it for debug output. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4] pci: pcie_imx: Fix hang on mx6qp
Hi Stefano, On Thu, Oct 15, 2015 at 5:50 AM, Stefano Babic wrote: > Thanks Fabio - as fix, I pick it up for the release. I don't see this one included in your pull request for Tom. Thanks ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/1] imx: mx6sabresd discard PHYS_SDRAM_SIZE
On Thu, Oct 15, 2015 at 7:05 AM, Peng Fan wrote: > This macro is not needed, since gd->ram_size is assigned value using > function imx_ddr_size(). > > Signed-off-by: Peng Fan > Cc: Stefano Babic > Cc: Fabio Estevam Reviewed-by: Fabio Estevam ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 02/14] sparse: Move main header parsing to a function of its own
The current sparse image format parser is quite tangled, with a lot of
code duplication.
Start refactoring it by moving the header parsing function to a function
of its own.
Signed-off-by: Maxime Ripard
Reviewed-by: Tom Rini
---
common/aboot.c | 45 -
1 file changed, 24 insertions(+), 21 deletions(-)
diff --git a/common/aboot.c b/common/aboot.c
index fba8e3e683e7..cd1b6a6ac8e0 100644
--- a/common/aboot.c
+++ b/common/aboot.c
@@ -41,6 +41,26 @@
#include
#include
+static sparse_header_t *sparse_parse_header(void **data)
+{
+ /* Read and skip over sparse image header */
+ sparse_header_t *sparse_header = (sparse_header_t *) *data;
+
+ *data += sparse_header->file_hdr_sz;
+
+ debug("=== Sparse Image Header ===\n");
+ debug("magic: 0x%x\n", sparse_header->magic);
+ debug("major_version: 0x%x\n", sparse_header->major_version);
+ debug("minor_version: 0x%x\n", sparse_header->minor_version);
+ debug("file_hdr_sz: %d\n", sparse_header->file_hdr_sz);
+ debug("chunk_hdr_sz: %d\n", sparse_header->chunk_hdr_sz);
+ debug("blk_sz: %d\n", sparse_header->blk_sz);
+ debug("total_blks: %d\n", sparse_header->total_blks);
+ debug("total_chunks: %d\n", sparse_header->total_chunks);
+
+ return sparse_header;
+}
+
void write_sparse_image(block_dev_desc_t *dev_desc,
disk_partition_t *info, const char *part_name,
void *data, unsigned sz)
@@ -58,29 +78,12 @@ void write_sparse_image(block_dev_desc_t *dev_desc,
uint32_t total_blocks = 0;
int i;
- /* Read and skip over sparse image header */
- sparse_header = (sparse_header_t *) data;
-
- data += sparse_header->file_hdr_sz;
- if (sparse_header->file_hdr_sz > sizeof(sparse_header_t))
- {
- /*
-* Skip the remaining bytes in a header that is longer than
-* we expected.
-*/
- data += (sparse_header->file_hdr_sz - sizeof(sparse_header_t));
+ sparse_header = sparse_parse_header(&data);
+ if (!sparse_header) {
+ fastboot_fail("sparse header issue\n");
+ return;
}
- debug("=== Sparse Image Header ===\n");
- debug("magic: 0x%x\n", sparse_header->magic);
- debug("major_version: 0x%x\n", sparse_header->major_version);
- debug("minor_version: 0x%x\n", sparse_header->minor_version);
- debug("file_hdr_sz: %d\n", sparse_header->file_hdr_sz);
- debug("chunk_hdr_sz: %d\n", sparse_header->chunk_hdr_sz);
- debug("blk_sz: %d\n", sparse_header->blk_sz);
- debug("total_blks: %d\n", sparse_header->total_blks);
- debug("total_chunks: %d\n", sparse_header->total_chunks);
-
/* verify sparse_header->blk_sz is an exact multiple of info->blksz */
if (sparse_header->blk_sz !=
(sparse_header->blk_sz & ~(info->blksz - 1))) {
--
2.5.3
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[U-Boot] [PATCH v2 06/14] sparse: Implement storage abstraction
The current sparse image parser relies heavily on the MMC layer, and
doesn't allow any other kind of storage medium to be used.
Rework the parser to support any kind of storage medium, as long as there
is an implementation for it.
Signed-off-by: Maxime Ripard
Reviewed-by: Tom Rini
---
common/aboot.c | 77 +
common/fb_mmc.c | 45 ++---
include/aboot.h | 16 +---
3 files changed, 104 insertions(+), 34 deletions(-)
diff --git a/common/aboot.c b/common/aboot.c
index 5f5fb6b62bfa..6c35d8226903 100644
--- a/common/aboot.c
+++ b/common/aboot.c
@@ -58,6 +58,13 @@ static unsigned int
sparse_get_chunk_data_size(sparse_header_t *sparse,
return chunk->total_sz - sparse->chunk_hdr_sz;
}
+static unsigned int sparse_block_size_to_storage(unsigned int size,
+sparse_storage_t *storage,
+sparse_header_t *sparse)
+{
+ return size * sparse->blk_sz / storage->block_sz;
+}
+
static bool sparse_chunk_has_buffer(chunk_header_t *chunk)
{
switch (chunk->chunk_type) {
@@ -257,20 +264,26 @@ static void sparse_put_data_buffer(sparse_buffer_t
*buffer)
free(buffer);
}
-int write_sparse_image(block_dev_desc_t *dev_desc,
- disk_partition_t *info, const char *part_name,
- void *data, unsigned sz)
+int store_sparse_image(sparse_storage_t *storage,
+ void *storage_priv, void *data)
{
- lbaint_t start;
- lbaint_t blkcnt;
unsigned int chunk, offset;
sparse_header_t *sparse_header;
chunk_header_t *chunk_header;
sparse_buffer_t *buffer;
+ uint32_t start;
uint32_t total_blocks = 0;
uint32_t skipped = 0;
int i;
+ debug("=== Storage ===\n");
+ debug("name: %s\n", storage->name);
+ debug("block_size: 0x%x\n", storage->block_sz);
+ debug("start: 0x%x\n", storage->start);
+ debug("size: 0x%x\n", storage->size);
+ debug("write: 0x%p\n", storage->write);
+ debug("priv: 0x%p\n", storage_priv);
+
sparse_header = sparse_parse_header(&data);
if (!sparse_header) {
printf("sparse header issue\n");
@@ -281,7 +294,7 @@ int write_sparse_image(block_dev_desc_t *dev_desc,
* Verify that the sparse block size is a multiple of our
* storage backend block size
*/
- div_u64_rem(sparse_header->blk_sz, info->blksz, &offset);
+ div_u64_rem(sparse_header->blk_sz, storage->block_sz, &offset);
if (offset) {
printf("%s: Sparse image block size issue [%u]\n",
__func__, sparse_header->blk_sz);
@@ -291,8 +304,10 @@ int write_sparse_image(block_dev_desc_t *dev_desc,
puts("Flashing Sparse Image\n");
/* Start processing chunks */
- start = info->start;
+ start = storage->start;
for (chunk = 0; chunk < sparse_header->total_chunks; chunk++) {
+ uint32_t blkcnt;
+
chunk_header = sparse_parse_chunk(sparse_header, &data);
if (!chunk_header) {
printf("Unknown chunk type");
@@ -304,20 +319,22 @@ int write_sparse_image(block_dev_desc_t *dev_desc,
* and go on parsing the rest of the chunks
*/
if (chunk_header->chunk_type == CHUNK_TYPE_DONT_CARE) {
- skipped += chunk_header->chunk_sz;
+ skipped +=
sparse_block_size_to_storage(chunk_header->chunk_sz,
+ storage,
+ sparse_header);
continue;
}
/* Retrieve the buffer we're going to write */
buffer = sparse_get_data_buffer(sparse_header, chunk_header,
- info->blksz, &data);
+ storage->block_sz, &data);
if (!buffer)
continue;
- blkcnt = (buffer->length / info->blksz) * buffer->repeat;
+ blkcnt = (buffer->length / storage->block_sz) * buffer->repeat;
if ((start + total_blocks + blkcnt) >
- (info->start + info->size)) {
+ (storage->start + storage->size)) {
printf("%s: Request would exceed partition size!\n",
__func__);
return -EINVAL;
@@ -325,30 +342,36 @@ int write_sparse_image(block_dev_desc_t *dev_desc,
for (i = 0; i < buffer->repeat; i++) {
unsigned long buffer_blk_cnt;
- unsigned long buffer_blks;
-
- buffer_blk_cnt = buffer->length / info->blksz;
-
-
[U-Boot] [PATCH v2 05/14] fastboot: Move fastboot response functions to fastboot core
The functions and a few define to generate a fastboot message to be sent
back to the host were so far duplicated among the users.
Move them all to a common place.
Signed-off-by: Maxime Ripard
---
common/aboot.c | 32 ++---
common/fb_mmc.c | 45 -
drivers/usb/gadget/f_fastboot.c | 27 +
include/aboot.h | 9 +++--
include/fastboot.h | 22
5 files changed, 76 insertions(+), 59 deletions(-)
create mode 100644 include/fastboot.h
diff --git a/common/aboot.c b/common/aboot.c
index 2775254c742e..5f5fb6b62bfa 100644
--- a/common/aboot.c
+++ b/common/aboot.c
@@ -257,9 +257,9 @@ static void sparse_put_data_buffer(sparse_buffer_t *buffer)
free(buffer);
}
-void write_sparse_image(block_dev_desc_t *dev_desc,
- disk_partition_t *info, const char *part_name,
- void *data, unsigned sz)
+int write_sparse_image(block_dev_desc_t *dev_desc,
+ disk_partition_t *info, const char *part_name,
+ void *data, unsigned sz)
{
lbaint_t start;
lbaint_t blkcnt;
@@ -273,8 +273,8 @@ void write_sparse_image(block_dev_desc_t *dev_desc,
sparse_header = sparse_parse_header(&data);
if (!sparse_header) {
- fastboot_fail("sparse header issue\n");
- return;
+ printf("sparse header issue\n");
+ return -EINVAL;
}
/*
@@ -285,8 +285,7 @@ void write_sparse_image(block_dev_desc_t *dev_desc,
if (offset) {
printf("%s: Sparse image block size issue [%u]\n",
__func__, sparse_header->blk_sz);
- fastboot_fail("sparse image block size issue");
- return;
+ return -EINVAL;
}
puts("Flashing Sparse Image\n");
@@ -296,8 +295,8 @@ void write_sparse_image(block_dev_desc_t *dev_desc,
for (chunk = 0; chunk < sparse_header->total_chunks; chunk++) {
chunk_header = sparse_parse_chunk(sparse_header, &data);
if (!chunk_header) {
- fastboot_fail("Unknown chunk type");
- return;
+ printf("Unknown chunk type");
+ return -EINVAL;
}
/*
@@ -321,8 +320,7 @@ void write_sparse_image(block_dev_desc_t *dev_desc,
(info->start + info->size)) {
printf("%s: Request would exceed partition size!\n",
__func__);
- fastboot_fail("Request would exceed partition size!");
- return;
+ return -EINVAL;
}
for (i = 0; i < buffer->repeat; i++) {
@@ -337,8 +335,7 @@ void write_sparse_image(block_dev_desc_t *dev_desc,
if (buffer_blks != buffer_blk_cnt) {
printf("%s: Write %d failed " LBAFU "\n",
__func__, i, buffer_blks);
- fastboot_fail("flash write failure");
- return;
+ return -EIO;
}
total_blocks += buffer_blk_cnt;
@@ -351,9 +348,10 @@ void write_sparse_image(block_dev_desc_t *dev_desc,
total_blocks, skipped, sparse_header->total_blks);
printf(" wrote %d blocks to '%s'\n", total_blocks, part_name);
- if (total_blocks != sparse_header->total_blks)
- fastboot_fail("sparse image write failure");
+ if (total_blocks != sparse_header->total_blks) {
+ printf("sparse image write failure\n");
+ return -EIO;
+ }
- fastboot_okay("");
- return;
+ return 0;
}
diff --git a/common/fb_mmc.c b/common/fb_mmc.c
index 0c48cf929f8f..b31a9fb929c5 100644
--- a/common/fb_mmc.c
+++ b/common/fb_mmc.c
@@ -6,6 +6,7 @@
#include
#include
+#include
#include
#include
#include
@@ -16,23 +17,8 @@
#define CONFIG_FASTBOOT_GPT_NAME GPT_ENTRY_NAME
#endif
-/* The 64 defined bytes plus the '\0' */
-#define RESPONSE_LEN (64 + 1)
-
static char *response_str;
-void fastboot_fail(const char *s)
-{
- strncpy(response_str, "FAIL\0", 5);
- strncat(response_str, s, RESPONSE_LEN - 4 - 1);
-}
-
-void fastboot_okay(const char *s)
-{
- strncpy(response_str, "OKAY\0", 5);
- strncat(response_str, s, RESPONSE_LEN - 4 - 1);
-}
-
static int get_partition_info_efi_by_name_or_alias(block_dev_desc_t *dev_desc,
const char *name, disk_partition_t *info)
{
@@ -68,7 +54,7 @@ static void write_raw_image(block_dev_desc_t *dev_desc,
disk_partition_t *info,
if (blkcnt > info->size) {
error("too large for partition: '%s'\n", part_name);
-
[U-Boot] [PATCH v2 00/14] Implement fastboot over NAND and sparse transfers
Hi everyone,
Here is the second attempt at getting fastboot flashing functions
working on top of a NAND, for arbitraly large images.
While the NAND support itself was quite easy to do, the support for
the Android sparse images was quite difficult to add, and ended up
being a quite huge refactoring of the sparse parse already in tree,
that was tied to the MMC layer.
This serie has been tested on a CHIP and an A13-Olinuxino, two
Allwinner devices, the CHIP for the NAND, and the Cubietruck to test
the MMC.
Let me know what you think,
Maxime
Changes from v1:
- Added support for multiple chunks transfers
- fixed a bug in the image parsing block counts
- Take the flashing errors into account now, instead of ignoring
them.
- Changed the name of the sparse images file to image-sparse.*
- Fixed the floating point computations issues
- Added the CONFIG_MUSB_GADGET option
- Take NAND bad blocks into account now
Maxime Ripard (14):
mtd: uboot: Add meaningful error message
sparse: Move main header parsing to a function of its own
sparse: Refactor chunk parsing function
sparse: Simplify multiple logic
fastboot: Move fastboot response functions to fastboot core
sparse: Implement storage abstraction
fastboot: Implement flashing session counter
sparse: Implement several chunks flashing
fastboot: Implement NAND backend
fastboot: nand: Add pre erase and write hooks
sparse: Rename the file and header
sunxi: Add support for android boot image
sunxi: A13-Olinuxino: Enable the USB OTG controller
sunxi: cubietruck: Enable the USB OTG controller
common/Makefile | 7 +-
common/aboot.c | 244 --
common/fb_mmc.c | 96 +
common/fb_nand.c| 213 +++
common/image-sparse.c | 393
configs/A13-OLinuXino_defconfig | 3 +
configs/Cubietruck_defconfig| 5 +
drivers/mtd/mtd_uboot.c | 2 +-
drivers/usb/gadget/f_fastboot.c | 54 -
include/configs/sunxi-common.h | 1 +
include/fastboot.h | 22 ++
include/fb_mmc.h| 5 +-
include/fb_nand.h | 11 +
include/{aboot.h => image-sparse.h} | 17 +-
14 files changed, 776 insertions(+), 297 deletions(-)
delete mode 100644 common/aboot.c
create mode 100644 common/fb_nand.c
create mode 100644 common/image-sparse.c
create mode 100644 include/fastboot.h
create mode 100644 include/fb_nand.h
rename include/{aboot.h => image-sparse.h} (53%)
--
2.5.3
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[U-Boot] [PATCH v2 01/14] mtd: uboot: Add meaningful error message
The current error message in get_part if CONFIG_MTDPARTS is disabled is
"offset is not a number" which is confusing and doesn't help at all.
Change that for something that might give a hint on what's going on.
Signed-off-by: Maxime Ripard
Reviewed-by: Tom Rini
---
drivers/mtd/mtd_uboot.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/mtd_uboot.c b/drivers/mtd/mtd_uboot.c
index c517b9c65d68..21386951efd5 100644
--- a/drivers/mtd/mtd_uboot.c
+++ b/drivers/mtd/mtd_uboot.c
@@ -37,7 +37,7 @@ static int get_part(const char *partname, int *idx, loff_t
*off, loff_t *size,
return 0;
#else
- puts("offset is not a number\n");
+ puts("mtdparts support missing.\n");
return -1;
#endif
}
--
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[U-Boot] [PATCH v2 08/14] sparse: Implement several chunks flashing
The fastboot client will split the sparse images into several chunks if the
image that it tries to flash is bigger than what the device can handle.
In such a case, the bootloader is supposed to retain the last offset to
which it wrote to, so that it can resume the writes at the right offset
when flashing the next chunk.
Retain the last offset we used, and use the session ID to know if we need
it or not.
Signed-off-by: Maxime Ripard
---
common/aboot.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/common/aboot.c b/common/aboot.c
index 7f412ac0ad4f..6d76c1e758f9 100644
--- a/common/aboot.c
+++ b/common/aboot.c
@@ -52,6 +52,8 @@ typedef struct sparse_buffer {
u16 type;
} sparse_buffer_t;
+static uint32_t last_offset;
+
static unsigned int sparse_get_chunk_data_size(sparse_header_t *sparse,
chunk_header_t *chunk)
{
@@ -301,10 +303,19 @@ int store_sparse_image(sparse_storage_t *storage, void
*storage_priv,
return -EINVAL;
}
- puts("Flashing Sparse Image\n");
+ /*
+* If it's a new flashing session, start at the beginning of
+* the partition. If not, then simply resume where we were.
+*/
+ if (session_id > 0)
+ start = last_offset;
+ else
+ start = storage->start;
+
+ printf("Flashing sparse image on partition %s at offset 0x%x (ID:
%d)\n",
+ storage->name, start * storage->block_sz, session_id);
/* Start processing chunks */
- start = storage->start;
for (chunk = 0; chunk < sparse_header->total_chunks; chunk++) {
uint32_t blkcnt;
@@ -376,5 +387,7 @@ int store_sparse_image(sparse_storage_t *storage, void
*storage_priv,
return -EIO;
}
+ last_offset = start + total_blocks;
+
return 0;
}
--
2.5.3
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[U-Boot] [PATCH v2 07/14] fastboot: Implement flashing session counter
The fastboot flash command that writes an image to a partition works in
several steps:
1 - Retrieve the maximum size the device can download through the
"max-download-size" variable
2 - Retrieve the partition type through the "partition-type:%s" variable,
that indicates whether or not the partition needs to be erased (even
though the fastboot client has minimal support for that)
3a - If the image is smaller than what the device can handle, send the image
and flash it.
3b - If the image is larger than what the device can handle, create a
sparse image, and split it in several chunks that would fit. Send the
chunk, flash it, repeat until we have no more data to send.
However, in the 3b case, the subsequent transfers have no particular
identifiers, the protocol just assumes that you would resume the writes
where you left it.
While doing so works well, it also means that flashing two subsequent
images on the same partition (for example because the user made a mistake)
would not work withouth flashing another partition or rebooting the board,
which is not really intuitive.
Since we have always the same pattern, we can however maintain a counter
that will be reset every time the client will retrieve max-download-size,
and incremented after each buffer will be flashed, that will allow us to
tell whether we should simply resume the flashing where we were, or start
back at the beginning of the partition.
Signed-off-by: Maxime Ripard
---
common/aboot.c | 4 ++--
common/fb_mmc.c | 8 +---
drivers/usb/gadget/f_fastboot.c | 14 +-
include/aboot.h | 2 +-
include/fb_mmc.h| 5 +++--
5 files changed, 24 insertions(+), 9 deletions(-)
diff --git a/common/aboot.c b/common/aboot.c
index 6c35d8226903..7f412ac0ad4f 100644
--- a/common/aboot.c
+++ b/common/aboot.c
@@ -264,8 +264,8 @@ static void sparse_put_data_buffer(sparse_buffer_t *buffer)
free(buffer);
}
-int store_sparse_image(sparse_storage_t *storage,
- void *storage_priv, void *data)
+int store_sparse_image(sparse_storage_t *storage, void *storage_priv,
+ unsigned int session_id, void *data)
{
unsigned int chunk, offset;
sparse_header_t *sparse_header;
diff --git a/common/fb_mmc.c b/common/fb_mmc.c
index c9f2ed6b5863..c6989668ae5b 100644
--- a/common/fb_mmc.c
+++ b/common/fb_mmc.c
@@ -96,8 +96,9 @@ static void write_raw_image(block_dev_desc_t *dev_desc,
disk_partition_t *info,
fastboot_okay(response_str, "");
}
-void fb_mmc_flash_write(const char *cmd, void *download_buffer,
- unsigned int download_bytes, char *response)
+void fb_mmc_flash_write(const char *cmd, unsigned int session_id,
+ void *download_buffer, unsigned int download_bytes,
+ char *response)
{
block_dev_desc_t *dev_desc;
disk_partition_t info;
@@ -151,7 +152,8 @@ void fb_mmc_flash_write(const char *cmd, void
*download_buffer,
printf("Flashing sparse image at offset " LBAFU "\n",
info.start);
- store_sparse_image(&sparse, &sparse_priv, download_buffer);
+ store_sparse_image(&sparse, &sparse_priv, session_id,
+ download_buffer);
} else {
write_raw_image(dev_desc, &info, cmd, download_buffer,
download_bytes);
diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c
index 5703decfd360..9af0372007bb 100644
--- a/drivers/usb/gadget/f_fastboot.c
+++ b/drivers/usb/gadget/f_fastboot.c
@@ -51,6 +51,7 @@ static inline struct f_fastboot *func_to_fastboot(struct
usb_function *f)
}
static struct f_fastboot *fastboot_func;
+static unsigned int fastboot_flash_session_id;
static unsigned int download_size;
static unsigned int download_bytes;
static bool is_high_speed;
@@ -393,6 +394,15 @@ static void cb_getvar(struct usb_ep *ep, struct
usb_request *req)
sprintf(str_num, "0x%08x", CONFIG_FASTBOOT_BUF_SIZE);
strncat(response, str_num, chars_left);
+
+ /*
+* This also indicates the start of a new flashing
+* "session", in which we could have 1-N buffers to
+* write to a partition.
+*
+* Reset our session counter.
+*/
+ fastboot_flash_session_id = 0;
} else if (!strcmp_l1("serialno", cmd)) {
s = getenv("serial#");
if (s)
@@ -555,9 +565,11 @@ static void cb_flash(struct usb_ep *ep, struct usb_request
*req)
strcpy(response, "FAILno flash device defined");
#ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV
- fb_mmc_flash_write(cmd, (void *)CONFIG_FASTBOOT_BUF_ADDR,
+ fb_mmc_flash_write(cmd, fastboot_flash_session_id,
+ (void *)CONFI
[U-Boot] [PATCH v2 09/14] fastboot: Implement NAND backend
So far the fastboot code was only supporting MMC-backed devices for its
flashing operations (flash and erase).
Add a storage backend for NAND-backed devices.
Signed-off-by: Maxime Ripard
---
common/Makefile | 7 +-
common/fb_nand.c| 195
drivers/usb/gadget/f_fastboot.c | 13 ++-
include/fb_nand.h | 11 +++
4 files changed, 224 insertions(+), 2 deletions(-)
create mode 100644 common/fb_nand.c
create mode 100644 include/fb_nand.h
diff --git a/common/Makefile b/common/Makefile
index 491c56552f40..4f6e6cea596b 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -274,10 +274,15 @@ obj-y += memsize.o
obj-y += stdio.o
# This option is not just y/n - it can have a numeric value
-ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV
+ifdef CONFIG_FASTBOOT_FLASH
obj-y += aboot.o
+ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV
obj-y += fb_mmc.o
endif
+ifdef CONFIG_FASTBOOT_FLASH_NAND_DEV
+obj-y += fb_nand.o
+endif
+endif
obj-$(CONFIG_CMD_BLOB) += cmd_blob.o
diff --git a/common/fb_nand.c b/common/fb_nand.c
new file mode 100644
index ..1c80ba9edabc
--- /dev/null
+++ b/common/fb_nand.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2014 Broadcom Corporation.
+ * Copyright 2015 Free Electrons.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+static char *response_str;
+
+struct fb_nand_sparse {
+ nand_info_t *nand;
+ struct part_info*part;
+};
+
+static int fb_nand_lookup(const char *partname, char *response,
+ nand_info_t **nand,
+ struct part_info **part)
+{
+ struct mtd_device *dev;
+ int ret;
+ u8 pnum;
+
+ ret = mtdparts_init();
+ if (ret) {
+ error("Cannot initialize MTD partitions\n");
+ fastboot_fail(response_str, "cannot init mtdparts");
+ return ret;
+ }
+
+ ret = find_dev_and_part(partname, &dev, &pnum, part);
+ if (ret) {
+ error("cannot find partition: '%s'", partname);
+ fastboot_fail(response_str, "cannot find partition");
+ return ret;
+ }
+
+ if (dev->id->type != MTD_DEV_TYPE_NAND) {
+ error("partition '%s' is not stored on a NAND device",
+ partname);
+ fastboot_fail(response_str, "not a NAND device");
+ return -EINVAL;
+ }
+
+ *nand = &nand_info[dev->id->num];
+
+ return 0;
+}
+
+static int _fb_nand_erase(nand_info_t *nand, struct part_info *part)
+{
+ nand_erase_options_t opts;
+ int ret;
+
+ memset(&opts, 0, sizeof(opts));
+ opts.offset = part->offset;
+ opts.length = part->size;
+ opts.quiet = 1;
+
+ printf("Erasing blocks 0x%llx to 0x%llx\n",
+ part->offset, part->offset + part->size);
+
+ ret = nand_erase_opts(nand, &opts);
+ if (ret)
+ return ret;
+
+ printf(" erased 0x%llx bytes from '%s'\n",
+ part->size, part->name);
+
+ return 0;
+}
+
+static int _fb_nand_write(nand_info_t *nand, struct part_info *part,
+ void *buffer, unsigned int offset,
+ unsigned int length, size_t *written)
+{
+ int flags = WITH_WR_VERIFY;
+
+#ifdef CONFIG_FASTBOOT_FLASH_NAND_TRIMFFS
+ flags |= WITH_DROP_FFS;
+#endif
+
+ return nand_write_skip_bad(nand, offset, &length, written,
+ part->size - (offset - part->offset),
+ buffer, flags);
+}
+
+static int fb_nand_sparse_write(struct sparse_storage *storage,
+ void *priv,
+ unsigned int offset,
+ unsigned int size,
+ char *data)
+{
+ struct fb_nand_sparse *sparse = priv;
+ size_t written;
+ int ret;
+
+ ret = _fb_nand_write(sparse->nand, sparse->part, data,
+offset * storage->block_sz,
+size * storage->block_sz, &written);
+ if (ret < 0) {
+ printf("Failed to write sparse chunk\n");
+ return ret;
+ }
+
+ return written / storage->block_sz;
+}
+
+void fb_nand_flash_write(const char *partname, unsigned int session_id,
+void *download_buffer, unsigned int download_bytes,
+char *response)
+{
+ struct part_info *part;
+ nand_info_t *nand = NULL;
+ int ret;
+
+ /* initialize the response buffer */
+ response_str = response;
+
+ ret = fb_nand_lookup(partname, response, &nand, &part);
+ if (ret) {
+ error("invalid NAND device");
+ fastboot_fail(response_str, "invalid NAND device");
+ return;
+
[U-Boot] [PATCH v2 04/14] sparse: Simplify multiple logic
To check the alignment of the image blocks to the storage blocks, the
current code uses a convoluted syntax, while a simple mod also does the
work.
Signed-off-by: Maxime Ripard
---
common/aboot.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/common/aboot.c b/common/aboot.c
index 243b330d9126..2775254c742e 100644
--- a/common/aboot.c
+++ b/common/aboot.c
@@ -37,11 +37,14 @@
#include
#include
#include
+#include
#include
#include
#include
#include
+#include
+
typedef struct sparse_buffer {
void*data;
u32 length;
@@ -260,7 +263,7 @@ void write_sparse_image(block_dev_desc_t *dev_desc,
{
lbaint_t start;
lbaint_t blkcnt;
- unsigned int chunk;
+ unsigned int chunk, offset;
sparse_header_t *sparse_header;
chunk_header_t *chunk_header;
sparse_buffer_t *buffer;
@@ -274,9 +277,12 @@ void write_sparse_image(block_dev_desc_t *dev_desc,
return;
}
- /* verify sparse_header->blk_sz is an exact multiple of info->blksz */
- if (sparse_header->blk_sz !=
- (sparse_header->blk_sz & ~(info->blksz - 1))) {
+ /*
+* Verify that the sparse block size is a multiple of our
+* storage backend block size
+*/
+ div_u64_rem(sparse_header->blk_sz, info->blksz, &offset);
+ if (offset) {
printf("%s: Sparse image block size issue [%u]\n",
__func__, sparse_header->blk_sz);
fastboot_fail("sparse image block size issue");
--
2.5.3
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[U-Boot] [PATCH v2 10/14] fastboot: nand: Add pre erase and write hooks
Some devices might need to do some per-partition initialization
(ECC/Randomizer settings change for example) before actually accessing it.
Add some hooks before the write and erase operations to let the boards
define what they need to do if needed.
Signed-off-by: Maxime Ripard
Reviewed-by: Tom Rini
---
common/fb_nand.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/common/fb_nand.c b/common/fb_nand.c
index 1c80ba9edabc..57cbde078340 100644
--- a/common/fb_nand.c
+++ b/common/fb_nand.c
@@ -23,6 +23,16 @@ struct fb_nand_sparse {
struct part_info*part;
};
+__weak int board_fastboot_erase_partition_setup(char *name)
+{
+ return 0;
+}
+
+__weak int board_fastboot_write_partition_setup(char *name)
+{
+ return 0;
+}
+
static int fb_nand_lookup(const char *partname, char *response,
nand_info_t **nand,
struct part_info **part)
@@ -134,6 +144,10 @@ void fb_nand_flash_write(const char *partname, unsigned
int session_id,
return;
}
+ ret = board_fastboot_write_partition_setup(part->name);
+ if (ret)
+ return;
+
if (is_sparse_image(download_buffer)) {
struct fb_nand_sparse sparse_priv;
sparse_storage_t sparse;
@@ -184,6 +198,10 @@ void fb_nand_erase(const char *partname, char *response)
return;
}
+ ret = board_fastboot_erase_partition_setup(part->name);
+ if (ret)
+ return;
+
ret = _fb_nand_erase(nand, part);
if (ret) {
error("failed erasing from device %s", nand->name);
--
2.5.3
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[U-Boot] [PATCH v2 03/14] sparse: Refactor chunk parsing function
The chunk parsing code was duplicating a lot of code among the various
chunk types, while all of them could be covered by generic and simple
functions.
Refactor the current code to reuse as much code as possible and hopefully
make the chunk parsing loop more readable and concise.
Signed-off-by: Maxime Ripard
Reviewed-by: Tom Rini
---
common/aboot.c | 372 -
1 file changed, 239 insertions(+), 133 deletions(-)
diff --git a/common/aboot.c b/common/aboot.c
index cd1b6a6ac8e0..243b330d9126 100644
--- a/common/aboot.c
+++ b/common/aboot.c
@@ -37,10 +37,36 @@
#include
#include
#include
+#include
#include
#include
#include
+typedef struct sparse_buffer {
+ void*data;
+ u32 length;
+ u32 repeat;
+ u16 type;
+} sparse_buffer_t;
+
+static unsigned int sparse_get_chunk_data_size(sparse_header_t *sparse,
+ chunk_header_t *chunk)
+{
+ return chunk->total_sz - sparse->chunk_hdr_sz;
+}
+
+static bool sparse_chunk_has_buffer(chunk_header_t *chunk)
+{
+ switch (chunk->chunk_type) {
+ case CHUNK_TYPE_RAW:
+ case CHUNK_TYPE_FILL:
+ return true;
+
+ default:
+ return false;
+ }
+}
+
static sparse_header_t *sparse_parse_header(void **data)
{
/* Read and skip over sparse image header */
@@ -61,21 +87,185 @@ static sparse_header_t *sparse_parse_header(void **data)
return sparse_header;
}
+static int sparse_parse_fill_chunk(sparse_header_t *sparse,
+ chunk_header_t *chunk)
+{
+ unsigned int chunk_data_sz = sparse_get_chunk_data_size(sparse, chunk);
+
+ if (chunk_data_sz != sizeof(uint32_t))
+ return -EINVAL;
+
+ return 0;
+}
+
+static int sparse_parse_raw_chunk(sparse_header_t *sparse,
+ chunk_header_t *chunk)
+{
+ unsigned int chunk_data_sz = sparse_get_chunk_data_size(sparse, chunk);
+
+ /* Check if the data size is a multiple of the main block size */
+ if (chunk_data_sz % sparse->blk_sz)
+ return -EINVAL;
+
+ /* Check that the chunk size is consistent */
+ if ((chunk_data_sz / sparse->blk_sz) != chunk->chunk_sz)
+ return -EINVAL;
+
+ return 0;
+}
+
+static chunk_header_t *sparse_parse_chunk(sparse_header_t *sparse,
+ void **image)
+{
+ chunk_header_t *chunk = (chunk_header_t *) *image;
+ int ret;
+
+ debug("=== Chunk Header ===\n");
+ debug("chunk_type: 0x%x\n", chunk->chunk_type);
+ debug("chunk_data_sz: 0x%x\n", chunk->chunk_sz);
+ debug("total_size: 0x%x\n", chunk->total_sz);
+
+ switch (chunk->chunk_type) {
+ case CHUNK_TYPE_RAW:
+ ret = sparse_parse_raw_chunk(sparse, chunk);
+ if (ret)
+ return NULL;
+ break;
+
+ case CHUNK_TYPE_FILL:
+ ret = sparse_parse_fill_chunk(sparse, chunk);
+ if (ret)
+ return NULL;
+ break;
+
+ case CHUNK_TYPE_DONT_CARE:
+ case CHUNK_TYPE_CRC32:
+ debug("Ignoring chunk\n");
+ break;
+
+ default:
+ printf("%s: Unknown chunk type: %x\n", __func__,
+ chunk->chunk_type);
+ return NULL;
+ }
+
+ *image += sparse->chunk_hdr_sz;
+
+ return chunk;
+}
+
+static int sparse_get_fill_buffer(sparse_header_t *sparse,
+ chunk_header_t *chunk,
+ sparse_buffer_t *buffer,
+ unsigned int blk_sz,
+ void *data)
+{
+ int i;
+
+ buffer->type = CHUNK_TYPE_FILL;
+
+ /*
+* We create a buffer of one block, and ask it to be
+* repeated as many times as needed.
+*/
+ buffer->length = blk_sz;
+ buffer->repeat = (chunk->chunk_sz * sparse->blk_sz) / blk_sz;
+
+ buffer->data = memalign(ARCH_DMA_MINALIGN,
+ ROUNDUP(blk_sz,
+ ARCH_DMA_MINALIGN));
+ if (!buffer->data)
+ return -ENOMEM;
+
+ for (i = 0; i < (buffer->length / sizeof(uint32_t)); i++)
+ ((uint32_t *)buffer->data)[i] = *(uint32_t *)(data);
+
+ return 0;
+}
+
+static int sparse_get_raw_buffer(sparse_header_t *sparse,
+chunk_header_t *chunk,
+sparse_buffer_t *buffer,
+unsigned int blk_sz,
+void *data)
+{
+ unsigned int chunk_data_sz = sparse_get_chunk_data_size(sparse, chunk);
+
+ buffer->type = CHUNK_TYPE_RAW;
+ buffer->length = chunk_data_sz;
+ buffer->data = data;
+ buffer->repeat = 1;
+
+
[U-Boot] [PATCH v2 14/14] sunxi: cubietruck: Enable the USB OTG controller
The Cubietruck has a mini-USB connector that can be used to power up the board and as an OTG connector. Since we have already some USB host-only ports right beside this one, enable it in gadget mode Signed-off-by: Maxime Ripard --- configs/Cubietruck_defconfig | 5 + 1 file changed, 5 insertions(+) diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig index e1b76ce78c8f..cf64bac353fe 100644 --- a/configs/Cubietruck_defconfig +++ b/configs/Cubietruck_defconfig @@ -14,3 +14,8 @@ CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(1 # CONFIG_CMD_FPGA is not set CONFIG_ETH_DESIGNWARE=y CONFIG_USB_EHCI_HCD=y +CONFIG_USB0_ID_DET="PH19" +CONFIG_USB0_VBUS_DET="PH22" +CONFIG_USB0_VBUS_PIN="PH17" +CONFIG_USB_MUSB_SUNXI=y +CONFIG_USB_MUSB_GADGET=y -- 2.5.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 13/14] sunxi: A13-Olinuxino: Enable the USB OTG controller
The A13-Olinuxino has a mini-USB connector that can be used to power up the board and as an OTG connector. Since we have already some USB host-only ports right beside this one, enable it in gadget mode Signed-off-by: Maxime Ripard --- configs/A13-OLinuXino_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig index 1f68d98cbab4..85eb6f06170e 100644 --- a/configs/A13-OLinuXino_defconfig +++ b/configs/A13-OLinuXino_defconfig @@ -4,6 +4,7 @@ CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=408 CONFIG_DRAM_EMR1=0 CONFIG_MMC0_CD_PIN="PG0" +CONFIG_USB0_VBUS_DET="PG1" CONFIG_USB1_VBUS_PIN="PG11" CONFIG_AXP_GPIO=y # CONFIG_VIDEO_HDMI is not set @@ -11,6 +12,8 @@ CONFIG_VIDEO_VGA_VIA_LCD=y CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_PWM="PB2" +CONFIG_USB_MUSB_SUNXI=y +CONFIG_USB_MUSB_GADGET=y CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y -- 2.5.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 11/14] sparse: Rename the file and header
The Android sparse image format is currently supported through a file
called aboot, which isn't really such a great name, since the sparse image
format is only used for transferring data with fastboot.
Rename the file and header to a file called "sparse", which also makes it
consistent with the header defining the image structures.
Signed-off-by: Maxime Ripard
---
common/Makefile | 2 +-
common/fb_mmc.c | 2 +-
common/fb_nand.c| 2 +-
common/{aboot.c => image-sparse.c} | 2 +-
include/{aboot.h => image-sparse.h} | 0
5 files changed, 4 insertions(+), 4 deletions(-)
rename common/{aboot.c => image-sparse.c} (99%)
rename include/{aboot.h => image-sparse.h} (100%)
diff --git a/common/Makefile b/common/Makefile
index 4f6e6cea596b..9398942932fd 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -275,7 +275,7 @@ obj-y += stdio.o
# This option is not just y/n - it can have a numeric value
ifdef CONFIG_FASTBOOT_FLASH
-obj-y += aboot.o
+obj-y += image-sparse.o
ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV
obj-y += fb_mmc.o
endif
diff --git a/common/fb_mmc.c b/common/fb_mmc.c
index c6989668ae5b..e4fbd8dfa756 100644
--- a/common/fb_mmc.c
+++ b/common/fb_mmc.c
@@ -9,8 +9,8 @@
#include
#include
#include
+#include
#include
-#include
#include
#include
diff --git a/common/fb_nand.c b/common/fb_nand.c
index 57cbde078340..9ca8602a73ec 100644
--- a/common/fb_nand.c
+++ b/common/fb_nand.c
@@ -8,8 +8,8 @@
#include
#include
-#include
#include
+#include
#include
#include
diff --git a/common/aboot.c b/common/image-sparse.c
similarity index 99%
rename from common/aboot.c
rename to common/image-sparse.c
index 6d76c1e758f9..dffe844d548a 100644
--- a/common/aboot.c
+++ b/common/image-sparse.c
@@ -36,9 +36,9 @@
#include
#include
-#include
#include
#include
+#include
#include
#include
#include
diff --git a/include/aboot.h b/include/image-sparse.h
similarity index 100%
rename from include/aboot.h
rename to include/image-sparse.h
--
2.5.3
___
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[U-Boot] [PATCH v2 12/14] sunxi: Add support for android boot image
When using the fastboot boot command, the image sent to U-Boot will be an Android boot image. If the support is missing, that won't obviously work, so we need it in our configuration. Signed-off-by: Maxime Ripard --- include/configs/sunxi-common.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index e1ba7914cda1..d7fc9ea7d099 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -347,6 +347,7 @@ extern int soft_i2c_gpio_scl; #define CONFIG_CMD_FASTBOOT #define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR #define CONFIG_FASTBOOT_BUF_SIZE 0x200 +#define CONFIG_ANDROID_BOOT_IMAGE #define CONFIG_FASTBOOT_FLASH #define CONFIG_FASTBOOT_FLASH_MMC_DEV 0 -- 2.5.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4] pci: pcie_imx: Fix hang on mx6qp
On 15/10/2015 14:23, Fabio Estevam wrote: > Hi Stefano, > > On Thu, Oct 15, 2015 at 5:50 AM, Stefano Babic wrote: > >> Thanks Fabio - as fix, I pick it up for the release. > > I don't see this one included in your pull request for Tom. > Aargh ! Thanks for noting this, I am fixing it. Regards, Stefano -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] ARM: uniphier: fix address mapping in README.uniphier
On Wed, Sep 30, 2015 at 09:15:58PM +0900, Masahiro Yamada wrote: > Signed-off-by: Masahiro Yamada Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PULL] Please pull u-boot-imx
On Thu, Oct 15, 2015 at 11:32:51AM +0200, Stefano Babic wrote: > Hi Tom, > > I have a couple of last-minute fixes for the vfr610twr. Please pull them > from u-boot-imx, thanks ! > > The following changes since commit 61903b759aa336d798da49d884467219796817ff: > > imximage: fix commands other than write_data (2015-10-07 13:43:15 +0200) > > are available in the git repository at: > > git://www.denx.de/git/u-boot-imx.git master > > for you to fetch changes up to cf04ad3219260c3c39ec3dbfe2427e3463e8dbd5: > > arm: vf610twr: improve memory layout (2015-10-15 11:22:07 +0200) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PULL] Please pull u-boot-imx
Hi Tom, On 15/10/2015 14:43, Tom Rini wrote: > On Thu, Oct 15, 2015 at 11:32:51AM +0200, Stefano Babic wrote: > >> Hi Tom, >> >> I have a couple of last-minute fixes for the vfr610twr. Please pull them >> from u-boot-imx, thanks ! >> >> The following changes since commit 61903b759aa336d798da49d884467219796817ff: >> >> imximage: fix commands other than write_data (2015-10-07 13:43:15 +0200) >> >> are available in the git repository at: >> >> git://www.denx.de/git/u-boot-imx.git master >> >> for you to fetch changes up to cf04ad3219260c3c39ec3dbfe2427e3463e8dbd5: >> >> arm: vf610twr: improve memory layout (2015-10-15 11:22:07 +0200) >> > > Applied to u-boot/master, thanks! > I have missed the following Fabio's patch fixing PCIe on mx6q: http://patchwork.ozlabs.org/patch/529768/ Do you prefer I send to you another PR including it or do you pick it up yourself ? Regards, Stefano -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] armv8/mmu: Clean up TCR programming
Hello Thierry, On Thu, 20 Aug 2015 11:52:13 +0200, Thierry Reding wrote: > From: Thierry Reding > > Use the inner shareable attribute for memory, which makes more sense > considering that this code is called when caches are being enabled. > > Cc: Albert Aribaud > Cc: Marc Zyngier > Signed-off-by: Thierry Reding Series applied to u-boot-arm/master as a bugfix. Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PULL] Please pull u-boot-imx
On Thu, Oct 15, 2015 at 02:49:29PM +0200, Stefano Babic wrote: > Hi Tom, > > On 15/10/2015 14:43, Tom Rini wrote: > > On Thu, Oct 15, 2015 at 11:32:51AM +0200, Stefano Babic wrote: > > > >> Hi Tom, > >> > >> I have a couple of last-minute fixes for the vfr610twr. Please pull them > >> from u-boot-imx, thanks ! > >> > >> The following changes since commit > >> 61903b759aa336d798da49d884467219796817ff: > >> > >> imximage: fix commands other than write_data (2015-10-07 13:43:15 +0200) > >> > >> are available in the git repository at: > >> > >> git://www.denx.de/git/u-boot-imx.git master > >> > >> for you to fetch changes up to cf04ad3219260c3c39ec3dbfe2427e3463e8dbd5: > >> > >> arm: vf610twr: improve memory layout (2015-10-15 11:22:07 +0200) > >> > > > > Applied to u-boot/master, thanks! > > > > I have missed the following Fabio's patch fixing PCIe on mx6q: > > http://patchwork.ozlabs.org/patch/529768/ > > Do you prefer I send to you another PR including it or do you pick it up > yourself ? I'll just grab it. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot,v4] pci: pcie_imx: Fix hang on mx6qp
On Tue, Oct 13, 2015 at 11:01:27AM -0300, Fabio Estevam wrote: > PCI driver currently hangs on mx6qp. > > Toggle the reset bit with the appropriate timings to fix the issue. > > Based on the FSL kernel driver implementation. > > Signed-off-by: Fabio Estevam > Acked-by: Stefano Babic Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] drivers: gpio: omap: add support for parsing additional gpio parameters
On Tue, Oct 13, 2015 at 01:57:16PM +0530, Mugunthan V N wrote: > With DM_GPIO, gpio parameters like ACTIVE_(LOW/HIGH) are to be > parsed in xlate gpio drivers-ops. Since xlate is not implemented > in omap_gpio driver, the driver considers all gpio to be > ACTIVE_HIGH which is the default case and fails to return actual > gpio status for ACTIVE_LOW gpios. So adding .xlate ops to > omap_gpio. > > Signed-off-by: Mugunthan V N Reviewed-by: Tom Rini -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: AM335x: mux: change mmc0 cd pinmux from mmc0_sdcd to gpio
On Tue, Oct 13, 2015 at 02:02:29PM +0530, Mugunthan V N wrote: > Currently omap_hsmmc driver doesn't use sdcd pin to detect > whether the card is present or not. Instead the same pin is used > as GPIO to detect card presence. So change the pin mux mode from > mmc0_sdcd to gpio0_6. > > Signed-off-by: Mugunthan V N Reviewed-by: Tom Rini -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch V5 01/17] armv7/ls1021a: move ns_access to common file
From: Mingkai Hu
Config Security Level Register is different between different SoCs,
so put the CSL register definition into the arch specific directory.
Signed-off-by: Mingkai Hu
Signed-off-by: Gong Qianyu
---
V5:
- No change.
V4:
- No change.
V3:
- No change.
V2:
- Create include/fsl_csu.h instead of board/freescale/common/ns_access.h
arch/arm/include/asm/arch-ls102xa/ns_access.h | 103 --
board/freescale/common/Makefile | 2 +-
board/freescale/common/ns_access.c| 8 +-
board/freescale/ls1021aqds/ls1021aqds.c | 101 ++---
board/freescale/ls1021atwr/ls1021atwr.c | 92 +--
include/configs/ls1021aqds.h | 2 +-
include/configs/ls1021atwr.h | 2 +-
include/fsl_csu.h | 34 +
8 files changed, 136 insertions(+), 208 deletions(-)
diff --git a/arch/arm/include/asm/arch-ls102xa/ns_access.h
b/arch/arm/include/asm/arch-ls102xa/ns_access.h
index b53f699..a921fb6 100644
--- a/arch/arm/include/asm/arch-ls102xa/ns_access.h
+++ b/arch/arm/include/asm/arch-ls102xa/ns_access.h
@@ -7,22 +7,6 @@
#ifndef __FSL_NS_ACCESS_H_
#define __FSL_NS_ACCESS_H_
-enum csu_cslx_access {
- CSU_NS_SUP_R = 0x08,
- CSU_NS_SUP_W = 0x80,
- CSU_NS_SUP_RW = 0x88,
- CSU_NS_USER_R = 0x04,
- CSU_NS_USER_W = 0x40,
- CSU_NS_USER_RW = 0x44,
- CSU_S_SUP_R = 0x02,
- CSU_S_SUP_W = 0x20,
- CSU_S_SUP_RW = 0x22,
- CSU_S_USER_R = 0x01,
- CSU_S_USER_W = 0x10,
- CSU_S_USER_RW = 0x11,
- CSU_ALL_RW = 0xff,
-};
-
enum csu_cslx_ind {
CSU_CSLX_PCIE2_IO = 0,
CSU_CSLX_PCIE1_IO,
@@ -108,11 +92,88 @@ enum csu_cslx_ind {
CSU_CSLX_MAX,
};
-struct csu_ns_dev {
- unsigned long ind;
- uint32_t val;
+static struct csu_ns_dev ns_dev[] = {
+ { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
+ { CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
+ { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
+ { CSU_CSLX_IFC_MEM, CSU_ALL_RW },
+ { CSU_CSLX_OCRAM, CSU_ALL_RW },
+ { CSU_CSLX_GIC, CSU_ALL_RW },
+ { CSU_CSLX_PCIE1, CSU_ALL_RW },
+ { CSU_CSLX_OCRAM2, CSU_ALL_RW },
+ { CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
+ { CSU_CSLX_PCIE2, CSU_ALL_RW },
+ { CSU_CSLX_SATA, CSU_ALL_RW },
+ { CSU_CSLX_USB3, CSU_ALL_RW },
+ { CSU_CSLX_SERDES, CSU_ALL_RW },
+ { CSU_CSLX_QDMA, CSU_ALL_RW },
+ { CSU_CSLX_LPUART2, CSU_ALL_RW },
+ { CSU_CSLX_LPUART1, CSU_ALL_RW },
+ { CSU_CSLX_LPUART4, CSU_ALL_RW },
+ { CSU_CSLX_LPUART3, CSU_ALL_RW },
+ { CSU_CSLX_LPUART6, CSU_ALL_RW },
+ { CSU_CSLX_LPUART5, CSU_ALL_RW },
+ { CSU_CSLX_DSPI2, CSU_ALL_RW },
+ { CSU_CSLX_DSPI1, CSU_ALL_RW },
+ { CSU_CSLX_QSPI, CSU_ALL_RW },
+ { CSU_CSLX_ESDHC, CSU_ALL_RW },
+ { CSU_CSLX_2D_ACE, CSU_ALL_RW },
+ { CSU_CSLX_IFC, CSU_ALL_RW },
+ { CSU_CSLX_I2C1, CSU_ALL_RW },
+ { CSU_CSLX_USB2, CSU_ALL_RW },
+ { CSU_CSLX_I2C3, CSU_ALL_RW },
+ { CSU_CSLX_I2C2, CSU_ALL_RW },
+ { CSU_CSLX_DUART2, CSU_ALL_RW },
+ { CSU_CSLX_DUART1, CSU_ALL_RW },
+ { CSU_CSLX_WDT2, CSU_ALL_RW },
+ { CSU_CSLX_WDT1, CSU_ALL_RW },
+ { CSU_CSLX_EDMA, CSU_ALL_RW },
+ { CSU_CSLX_SYS_CNT, CSU_ALL_RW },
+ { CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
+ { CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
+ { CSU_CSLX_DDR, CSU_ALL_RW },
+ { CSU_CSLX_QUICC, CSU_ALL_RW },
+ { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
+ { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
+ { CSU_CSLX_SFP, CSU_ALL_RW },
+ { CSU_CSLX_TMU, CSU_ALL_RW },
+ { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
+ { CSU_CSLX_RESERVED0, CSU_ALL_RW },
+ { CSU_CSLX_ETSEC1, CSU_ALL_RW },
+ { CSU_CSLX_SEC5_5, CSU_ALL_RW },
+ { CSU_CSLX_ETSEC3, CSU_ALL_RW },
+ { CSU_CSLX_ETSEC2, CSU_ALL_RW },
+ { CSU_CSLX_GPIO2, CSU_ALL_RW },
+ { CSU_CSLX_GPIO1, CSU_ALL_RW },
+ { CSU_CSLX_GPIO4, CSU_ALL_RW },
+ { CSU_CSLX_GPIO3, CSU_ALL_RW },
+ { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
+ { CSU_CSLX_CSU, CSU_ALL_RW },
+ { CSU_CSLX_ASRC, CSU_ALL_RW },
+ { CSU_CSLX_SPDIF, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
+ { CSU_CSLX_SAI2, CSU_ALL_RW },
+ { CSU_CSLX_SAI1, CSU_ALL_RW },
+ { CSU_CSLX_SAI4, CSU_ALL_RW },
+ { CSU_CSLX_SAI3, CSU_ALL_RW },
+ { CSU_CSLX_FTM2, CSU_ALL_RW },
+ { CSU_CSLX_FTM1, CSU_ALL_RW },
+ { CSU_CSLX_FTM4, CSU_ALL_RW },
+ { CSU_CSLX_FTM3, CSU_ALL_RW },
+ { CSU_CSLX_FTM6, CSU_ALL_RW },
+ { CSU_CSLX_FTM5, CSU_ALL_RW },
+ { CSU_CSLX_FTM8, CSU_ALL_RW },
+ { CSU_CSLX_FTM7, CSU_ALL_RW },
+ { CSU_CSLX_COP_DCSR, CSU_ALL_RW },
+ { CSU_CSLX_EPU, CSU_
[U-Boot] [Patch V5 02/17] common/board_f.c: modify the macro to use get_clocks() more common
get_clocks() should not be limited by ESDHC.
Signed-off-by: Gong Qianyu
---
V5:
- No change.
V4:
- No change.
V3:
- Removed defines in PPC configs that have no need to use.
V2:
- No change.
common/board_f.c | 2 +-
include/configs/colibri_vf.h | 1 +
include/configs/ls1021aqds.h | 1 +
include/configs/ls1021atwr.h | 1 +
include/configs/ls2085aqds.h | 1 +
include/configs/ls2085ardb.h | 1 +
include/configs/m53evk.h | 1 +
include/configs/mx25pdk.h | 1 +
include/configs/mx35pdk.h | 1 +
include/configs/mx51evk.h | 1 +
include/configs/mx53ard.h | 1 +
include/configs/mx53evk.h | 1 +
include/configs/mx53loco.h| 1 +
include/configs/mx53smd.h | 1 +
include/configs/mx6_common.h | 1 +
include/configs/mx7_common.h | 1 +
include/configs/usbarmory.h | 1 +
include/configs/vf610twr.h| 1 +
include/configs/woodburn_common.h | 1 +
19 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/common/board_f.c b/common/board_f.c
index 613332e..1bb84b3 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -806,7 +806,7 @@ static init_fnc_t init_sequence_f[] = {
#if defined(CONFIG_BOARD_POSTCLK_INIT)
board_postclk_init,
#endif
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_CLK
get_clocks,
#endif
#ifdef CONFIG_M68K
diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index 2583155..5bd742d 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -18,6 +18,7 @@
#define CONFIG_SYS_THUMB_BUILD
#define CONFIG_USE_ARCH_MEMCPY
#define CONFIG_USE_ARCH_MEMSET
+#define CONFIG_FSL_CLK
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_ARCH_MISC_INIT
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 9b8b001..42b66b3 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -12,6 +12,7 @@
#define CONFIG_ARMV7_PSCI
#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_FSL_CLK
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 676c096..8a86473 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -12,6 +12,7 @@
#define CONFIG_ARMV7_PSCI
#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_FSL_CLK
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
diff --git a/include/configs/ls2085aqds.h b/include/configs/ls2085aqds.h
index f7f3870..4cfcf98 100644
--- a/include/configs/ls2085aqds.h
+++ b/include/configs/ls2085aqds.h
@@ -16,6 +16,7 @@ unsigned long get_board_sys_clk(void);
unsigned long get_board_ddr_clk(void);
#endif
+#define CONFIG_FSL_CLK
#define CONFIG_SYS_CLK_FREQget_board_sys_clk()
#define CONFIG_DDR_CLK_FREQget_board_ddr_clk()
#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2085ardb.h
index a190bc7..583fed5 100644
--- a/include/configs/ls2085ardb.h
+++ b/include/configs/ls2085ardb.h
@@ -18,6 +18,7 @@
unsigned long get_board_sys_clk(void);
#endif
+#define CONFIG_FSL_CLK
#define CONFIG_SYS_CLK_FREQget_board_sys_clk()
#define CONFIG_DDR_CLK_FREQ1
#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h
index 8853d8f..456e5b4 100644
--- a/include/configs/m53evk.h
+++ b/include/configs/m53evk.h
@@ -18,6 +18,7 @@
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_REVISION_TAG
#define CONFIG_SYS_NO_FLASH
+#define CONFIG_FSL_CLK
#define CONFIG_FIT
diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h
index 0414086..afe2a02 100644
--- a/include/configs/mx25pdk.h
+++ b/include/configs/mx25pdk.h
@@ -15,6 +15,7 @@
#define CONFIG_SYS_TEXT_BASE 0x8120
#define CONFIG_MXC_GPIO
#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_FSL_CLK
#define CONFIG_SYS_TIMER_RATE 32768
#define CONFIG_SYS_TIMER_COUNTER \
diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h
index 6bfdaa6..dca2f86 100644
--- a/include/configs/mx35pdk.h
+++ b/include/configs/mx35pdk.h
@@ -20,6 +20,7 @@
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_FSL_CLK
/* Set TEXT at the beginning of the NOR flash */
#define CONFIG_SYS_TEXT_BASE 0xA000
diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
index 2203c15..e3763c1 100644
--- a/include/configs/mx51evk.h
+++ b/include/configs/mx51evk.h
@@ -18,6 +18,7 @@
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_FSL_CLK
#define CONFIG_SYS_TEXT_BASE 0x9780
#include
diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h
index b889c25..9ef973d 100644
--- a/include/configs/mx53ard.h
+++ b/include/configs/mx53ard.h
@@ -24,6 +24,7 @@
#define CONFIG_REVISION_
[U-Boot] [Patch V5 00/17] Add LS1043A platform support
Hi all, Here are the main changes for v5, please help to review. - Wrap up the in_be32 and in_le32 to gur_in32/scfg_in32 for GUR/SCFG block - Move DDR related macros moved out of #ifdef in config.h - Move the mmu table to cpu.h - Change commit message for patch: armv8/fsl_lsch3: Change arch to fsl-layerscape [Patch V5 01/17] armv7/ls1021a: move ns_access to common file [Patch V5 02/17] common/board_f.c: modify the macro to use [Patch V5 03/17] net/fm: Fix the endian issue to support both [Patch V5 04/17] net/fm/eth: Use mb() to be compatible for both ARM [Patch V5 05/17] net/fm: Add support for 64-bit platforms [Patch V5 06/17] net/fm: Make the return value logic consistent with [Patch V5 07/17] net/fm: bug fix when CONFIG_PHYLIB not defined [Patch V5 08/17] net: Move some header files to include/ [Patch V5 09/17] net/fm: Add QSGMII PCS init [Patch V5 10/17] net/fm: fix MDIO controller base on FMAN2 [Patch V5 11/17] armv8/fsl_lsch3: Change arch to fsl-layerscape [Patch V5 12/17] armv8/fsl_lsch2: Add fsl_lsch2 SoC [Patch V5 13/17] armv8/ls1043ardb: Add LS1043ARDB board support [Patch V5 14/17] armv8/ls1043ardb: Add nand boot support [Patch V5 15/17] armv8/ls1043a: Add Fman support [Patch V5 16/17] armv8/ls1043ardb: esdhc: Add esdhc support for [Patch V5 17/17] armv8/ls1043ardb: Add sd boot support Thanks, Qianyu ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch V5 03/17] net/fm: Fix the endian issue to support both endianness platforms
From: Hou Zhiqiang
The Frame Manager(FMan) is a big-endian peripheral, so the
registers, internal MURAM and BDs, which are allocated in main
memory and used to communication between core and FMan, should
be accessed in big-endian. The big-endian platforms can access
them directly as the code implemented so far, while for the
little-endian platforms it need to swap the byte-order.
Signed-off-by: Hou Zhiqiang
Signed-off-by: Shaohui Xie
Signed-off-by: Mingkai Hu
Signed-off-by: Gong Qianyu
---
V5:
- No change.
V4:
- No change.
V3:
- Modify the subject to make the aim clear.
V2:
- No change.
drivers/net/fm/eth.c | 70 +++-
drivers/net/fm/fm.c | 11 +
2 files changed, 43 insertions(+), 38 deletions(-)
diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index 6702f5a..368d554 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -109,7 +109,7 @@ static int tgec_is_fibre(struct eth_device *dev)
static u16 muram_readw(u16 *addr)
{
u32 base = (u32)addr & ~0x3;
- u32 val32 = *(u32 *)base;
+ u32 val32 = in_be32((u32 *)base);
int byte_pos;
u16 ret;
@@ -125,7 +125,7 @@ static u16 muram_readw(u16 *addr)
static void muram_writew(u16 *addr, u16 val)
{
u32 base = (u32)addr & ~0x3;
- u32 org32 = *(u32 *)base;
+ u32 org32 = in_be32((u32 *)base);
u32 val32;
int byte_pos;
@@ -135,7 +135,7 @@ static void muram_writew(u16 *addr, u16 val)
else
val32 = (org32 & 0x) | ((u32)val << 16);
- *(u32 *)base = val32;
+ out_be32((u32 *)base, val32);
}
static void bmi_rx_port_disable(struct fm_bmi_rx_port *rx_port)
@@ -213,10 +213,10 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth
*fm_eth)
pram_page_offset = (u32)pram - fm_muram_base(fm_eth->fm_index);
/* enable global mode- snooping data buffers and BDs */
- pram->mode = PRAM_MODE_GLOBAL;
+ out_be32(&pram->mode, PRAM_MODE_GLOBAL);
/* init the Rx queue descriptor pionter */
- pram->rxqd_ptr = pram_page_offset + 0x20;
+ out_be32(&pram->rxqd_ptr, pram_page_offset + 0x20);
/* set the max receive buffer length, power of 2 */
muram_writew(&pram->mrblr, MAX_RXBUF_LOG2);
@@ -243,10 +243,11 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth
*fm_eth)
/* init Rx BDs ring */
rxbd = (struct fm_port_bd *)rx_bd_ring_base;
for (i = 0; i < RX_BD_RING_SIZE; i++) {
- rxbd->status = RxBD_EMPTY;
- rxbd->len = 0;
- rxbd->buf_ptr_hi = 0;
- rxbd->buf_ptr_lo = (u32)rx_buf_pool + i * MAX_RXBUF_LEN;
+ muram_writew(&rxbd->status, RxBD_EMPTY);
+ muram_writew(&rxbd->len, 0);
+ muram_writew(&rxbd->buf_ptr_hi, 0);
+ out_be32(&rxbd->buf_ptr_lo, (u32)rx_buf_pool +
+ i * MAX_RXBUF_LEN);
rxbd++;
}
@@ -254,7 +255,7 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth
*fm_eth)
rxqd = &pram->rxqd;
muram_writew(&rxqd->gen, 0);
muram_writew(&rxqd->bd_ring_base_hi, 0);
- rxqd->bd_ring_base_lo = (u32)rx_bd_ring_base;
+ out_be32(&rxqd->bd_ring_base_lo, (u32)rx_bd_ring_base);
muram_writew(&rxqd->bd_ring_size, sizeof(struct fm_port_bd)
* RX_BD_RING_SIZE);
muram_writew(&rxqd->offset_in, 0);
@@ -285,10 +286,10 @@ static int fm_eth_tx_port_parameter_init(struct fm_eth
*fm_eth)
pram_page_offset = (u32)pram - fm_muram_base(fm_eth->fm_index);
/* enable global mode- snooping data buffers and BDs */
- pram->mode = PRAM_MODE_GLOBAL;
+ out_be32(&pram->mode, PRAM_MODE_GLOBAL);
/* init the Tx queue descriptor pionter */
- pram->txqd_ptr = pram_page_offset + 0x40;
+ out_be32(&pram->txqd_ptr, pram_page_offset + 0x40);
/* alloc Tx buffer descriptors from main memory */
tx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
@@ -304,16 +305,17 @@ static int fm_eth_tx_port_parameter_init(struct fm_eth
*fm_eth)
/* init Tx BDs ring */
txbd = (struct fm_port_bd *)tx_bd_ring_base;
for (i = 0; i < TX_BD_RING_SIZE; i++) {
- txbd->status = TxBD_LAST;
- txbd->len = 0;
- txbd->buf_ptr_hi = 0;
- txbd->buf_ptr_lo = 0;
+ muram_writew(&txbd->status, TxBD_LAST);
+ muram_writew(&txbd->len, 0);
+ muram_writew(&txbd->buf_ptr_hi, 0);
+ out_be32(&txbd->buf_ptr_lo, 0);
+ txbd++;
}
/* set the Tx queue decriptor */
txqd = &pram->txqd;
muram_writew(&txqd->bd_ring_base_hi, 0);
- txqd->bd_ring_base_lo = (u32)tx_bd_ring_base;
+ out_be32(&txqd->bd_ring_base_lo, (u32)tx_bd_ring_base);
muram_writew(&txqd->bd_ring_size, sizeof(struct fm_port_bd)
[U-Boot] [Patch V5 04/17] net/fm/eth: Use mb() to be compatible for both ARM and PowerPC
From: Shaohui Xie
Use mb() instead of sync() to be compatible for both ARM and PowerPC.
Signed-off-by: Shaohui Xie
Signed-off-by: Mingkai Hu
Signed-off-by: Gong Qianyu
---
V5:
- No change.
V4:
- No change.
V3:
- New patch. Separated from patch 'net: Move some header files to include/'
drivers/net/fm/eth.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index 368d554..ad02c66 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -371,7 +371,7 @@ static void fmc_tx_port_graceful_stop_enable(struct fm_eth
*fm_eth)
pram = fm_eth->tx_pram;
/* graceful stop transmission of frames */
setbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP);
- sync();
+ mb();
}
static void fmc_tx_port_graceful_stop_disable(struct fm_eth *fm_eth)
@@ -381,7 +381,7 @@ static void fmc_tx_port_graceful_stop_disable(struct fm_eth
*fm_eth)
pram = fm_eth->tx_pram;
/* re-enable transmission of frames */
clrbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP);
- sync();
+ mb();
}
static int fm_eth_open(struct eth_device *dev, bd_t *bd)
@@ -483,9 +483,9 @@ static int fm_eth_send(struct eth_device *dev, void *buf,
int len)
muram_writew(&txbd->buf_ptr_hi, 0);
out_be32(&txbd->buf_ptr_lo, (u32)buf);
muram_writew(&txbd->len, len);
- sync();
+ mb();
muram_writew(&txbd->status, TxBD_READY | TxBD_LAST);
- sync();
+ mb();
/* update TxQD, let RISC to send the packet */
offset_in = muram_readw(&pram->txqd.offset_in);
@@ -493,7 +493,7 @@ static int fm_eth_send(struct eth_device *dev, void *buf,
int len)
if (offset_in >= muram_readw(&pram->txqd.bd_ring_size))
offset_in = 0;
muram_writew(&pram->txqd.offset_in, offset_in);
- sync();
+ mb();
/* wait for buffer to be transmitted */
for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) {
@@ -544,7 +544,7 @@ static int fm_eth_recv(struct eth_device *dev)
/* clear the RxBDs */
muram_writew(&rxbd->status, RxBD_EMPTY);
muram_writew(&rxbd->len, 0);
- sync();
+ mb();
/* advance RxBD */
rxbd++;
@@ -560,7 +560,7 @@ static int fm_eth_recv(struct eth_device *dev)
if (offset_out >= muram_readw(&pram->rxqd.bd_ring_size))
offset_out = 0;
muram_writew(&pram->rxqd.offset_out, offset_out);
- sync();
+ mb();
}
fm_eth->cur_rxbd = (void *)rxbd;
--
2.1.0.27.g96db324
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch V5 06/17] net/fm: Make the return value logic consistent with convention
From: Hou Zhiqiang
In convention, the '0' is a normal return value indicating there isn't
an error. While some functions of FMan IM driver treat '0' as an error
return value.
Signed-off-by: Hou Zhiqiang
Signed-off-by: Gong Qianyu
---
V5:
- No change.
V4:
- No change.
V3:
- New patch.
drivers/net/fm/eth.c | 60 +++-
1 file changed, 36 insertions(+), 24 deletions(-)
diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index 6451dce..d7d064b 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -211,7 +211,7 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth
*fm_eth)
FM_PRAM_SIZE, FM_PRAM_ALIGN);
if (!pram) {
printf("%s: No muram for Rx global parameter\n", __func__);
- return 0;
+ return -ENOMEM;
}
fm_eth->rx_pram = pram;
@@ -232,14 +232,16 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth
*fm_eth)
rx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
* RX_BD_RING_SIZE);
if (!rx_bd_ring_base)
- return 0;
+ return -ENOMEM;
+
memset(rx_bd_ring_base, 0, sizeof(struct fm_port_bd)
* RX_BD_RING_SIZE);
/* alloc Rx buffer from main memory */
rx_buf_pool = malloc(MAX_RXBUF_LEN * RX_BD_RING_SIZE);
if (!rx_buf_pool)
- return 0;
+ return -ENOMEM;
+
memset(rx_buf_pool, 0, MAX_RXBUF_LEN * RX_BD_RING_SIZE);
debug("%s: rx_buf_pool = %p\n", __func__, rx_buf_pool);
@@ -277,7 +279,7 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth
*fm_eth)
/* set IM parameter ram pointer to Rx Frame Queue ID */
out_be32(&bmi_rx_port->fmbm_rfqid, pram_page_offset);
- return 1;
+ return 0;
}
static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth)
@@ -296,7 +298,7 @@ static int fm_eth_tx_port_parameter_init(struct fm_eth
*fm_eth)
FM_PRAM_SIZE, FM_PRAM_ALIGN);
if (!pram) {
printf("%s: No muram for Tx global parameter\n", __func__);
- return 0;
+ return -ENOMEM;
}
fm_eth->tx_pram = pram;
@@ -313,7 +315,8 @@ static int fm_eth_tx_port_parameter_init(struct fm_eth
*fm_eth)
tx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
* TX_BD_RING_SIZE);
if (!tx_bd_ring_base)
- return 0;
+ return -ENOMEM;
+
memset(tx_bd_ring_base, 0, sizeof(struct fm_port_bd)
* TX_BD_RING_SIZE);
/* save it to fm_eth */
@@ -344,29 +347,35 @@ static int fm_eth_tx_port_parameter_init(struct fm_eth
*fm_eth)
/* set IM parameter ram pointer to Tx Confirmation Frame Queue ID */
out_be32(&bmi_tx_port->fmbm_tcfqid, pram_page_offset);
- return 1;
+ return 0;
}
static int fm_eth_init(struct fm_eth *fm_eth)
{
+ int ret;
- if (!fm_eth_rx_port_parameter_init(fm_eth))
- return 0;
+ ret = fm_eth_rx_port_parameter_init(fm_eth);
+ if (ret)
+ return ret;
- if (!fm_eth_tx_port_parameter_init(fm_eth))
- return 0;
+ ret = fm_eth_tx_port_parameter_init(fm_eth);
+ if (ret)
+ return ret;
- return 1;
+ return 0;
}
static int fm_eth_startup(struct fm_eth *fm_eth)
{
struct fsl_enet_mac *mac;
+ int ret;
+
mac = fm_eth->mac;
/* Rx/TxBDs, Rx/TxQDs, Rx buff and parameter ram init */
- if (!fm_eth_init(fm_eth))
- return 0;
+ ret = fm_eth_init(fm_eth);
+ if (ret)
+ return ret;
/* setup the MAC controller */
mac->init_mac(mac);
@@ -381,7 +390,7 @@ static int fm_eth_startup(struct fm_eth *fm_eth)
/* init bmi tx port, IM mode and disable */
bmi_tx_port_init(fm_eth->tx_port);
- return 1;
+ return 0;
}
static void fmc_tx_port_graceful_stop_enable(struct fm_eth *fm_eth)
@@ -628,7 +637,7 @@ static int fm_eth_init_mac(struct fm_eth *fm_eth, struct
ccsr_fman *reg)
/* alloc mac controller */
mac = malloc(sizeof(struct fsl_enet_mac));
if (!mac)
- return 0;
+ return -ENOMEM;
memset(mac, 0, sizeof(struct fsl_enet_mac));
/* save the mac to fm_eth struct */
@@ -643,7 +652,7 @@ static int fm_eth_init_mac(struct fm_eth *fm_eth, struct
ccsr_fman *reg)
init_tgec(mac, base, phyregs, MAX_RXBUF_LEN);
#endif
- return 1;
+ return 0;
}
static int init_phy(struct eth_device *dev)
@@ -696,17 +705,18 @@ int fm_eth_initialize(struct ccsr_fman *reg, struct
fm_eth_info *info)
struct eth_device *dev;
struct fm_eth *fm_eth;
int i, num = info->num;
+ int ret;
/* alloc eth device */
dev = (struct eth_device *)malloc(sizeof(struct e
[U-Boot] [Patch V5 05/17] net/fm: Add support for 64-bit platforms
From: Hou Zhiqiang
The FMan IM driver is developed for 32-bit platfroms and isn't
friendly to 64-bit platforms, so do the minimal refactor:
1. Refine the MURAM management and access.
2. Correct the initialization and operations for QDs and BDs.
Signed-off-by: Hou Zhiqiang
Signed-off-by: Gong Qianyu
---
V5:
- No change.
V4:
- No change.
V3:
- New patch.
drivers/net/fm/eth.c | 61
drivers/net/fm/fm.c | 20 ++---
drivers/net/fm/fm.h | 12 +--
3 files changed, 60 insertions(+), 33 deletions(-)
diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index ad02c66..6451dce 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -108,12 +108,12 @@ static int tgec_is_fibre(struct eth_device *dev)
static u16 muram_readw(u16 *addr)
{
- u32 base = (u32)addr & ~0x3;
- u32 val32 = in_be32((u32 *)base);
+ ulong base = (ulong)addr & ~0x3UL;
+ u32 val32 = in_be32((void *)base);
int byte_pos;
u16 ret;
- byte_pos = (u32)addr & 0x3;
+ byte_pos = (ulong)addr & 0x3UL;
if (byte_pos)
ret = (u16)(val32 & 0x);
else
@@ -124,18 +124,18 @@ static u16 muram_readw(u16 *addr)
static void muram_writew(u16 *addr, u16 val)
{
- u32 base = (u32)addr & ~0x3;
- u32 org32 = in_be32((u32 *)base);
+ ulong base = (ulong)addr & ~0x3UL;
+ u32 org32 = in_be32((void *)base);
u32 val32;
int byte_pos;
- byte_pos = (u32)addr & 0x3;
+ byte_pos = (ulong)addr & 0x3UL;
if (byte_pos)
val32 = (org32 & 0x) | val;
else
val32 = (org32 & 0x) | ((u32)val << 16);
- out_be32((u32 *)base, val32);
+ out_be32((void *)base, val32);
}
static void bmi_rx_port_disable(struct fm_bmi_rx_port *rx_port)
@@ -199,6 +199,8 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth
*fm_eth)
u32 pram_page_offset;
void *rx_bd_ring_base;
void *rx_buf_pool;
+ u32 bd_ring_base_lo, bd_ring_base_hi;
+ u32 buf_lo, buf_hi;
struct fm_port_bd *rxbd;
struct fm_port_qd *rxqd;
struct fm_bmi_rx_port *bmi_rx_port = fm_eth->rx_port;
@@ -207,10 +209,15 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth
*fm_eth)
/* alloc global parameter ram at MURAM */
pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
FM_PRAM_SIZE, FM_PRAM_ALIGN);
+ if (!pram) {
+ printf("%s: No muram for Rx global parameter\n", __func__);
+ return 0;
+ }
+
fm_eth->rx_pram = pram;
/* parameter page offset to MURAM */
- pram_page_offset = (u32)pram - fm_muram_base(fm_eth->fm_index);
+ pram_page_offset = (void *)pram - fm_muram_base(fm_eth->fm_index);
/* enable global mode- snooping data buffers and BDs */
out_be32(&pram->mode, PRAM_MODE_GLOBAL);
@@ -234,6 +241,7 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth
*fm_eth)
if (!rx_buf_pool)
return 0;
memset(rx_buf_pool, 0, MAX_RXBUF_LEN * RX_BD_RING_SIZE);
+ debug("%s: rx_buf_pool = %p\n", __func__, rx_buf_pool);
/* save them to fm_eth */
fm_eth->rx_bd_ring = rx_bd_ring_base;
@@ -245,17 +253,22 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth
*fm_eth)
for (i = 0; i < RX_BD_RING_SIZE; i++) {
muram_writew(&rxbd->status, RxBD_EMPTY);
muram_writew(&rxbd->len, 0);
- muram_writew(&rxbd->buf_ptr_hi, 0);
- out_be32(&rxbd->buf_ptr_lo, (u32)rx_buf_pool +
- i * MAX_RXBUF_LEN);
+ buf_hi = upper_32_bits(virt_to_phys(rx_buf_pool +
+ i * MAX_RXBUF_LEN));
+ buf_lo = lower_32_bits(virt_to_phys(rx_buf_pool +
+ i * MAX_RXBUF_LEN));
+ muram_writew(&rxbd->buf_ptr_hi, (u16)buf_hi);
+ out_be32(&rxbd->buf_ptr_lo, buf_lo);
rxbd++;
}
/* set the Rx queue descriptor */
rxqd = &pram->rxqd;
muram_writew(&rxqd->gen, 0);
- muram_writew(&rxqd->bd_ring_base_hi, 0);
- out_be32(&rxqd->bd_ring_base_lo, (u32)rx_bd_ring_base);
+ bd_ring_base_hi = upper_32_bits(virt_to_phys(rx_bd_ring_base));
+ bd_ring_base_lo = lower_32_bits(virt_to_phys(rx_bd_ring_base));
+ muram_writew(&rxqd->bd_ring_base_hi, (u16)bd_ring_base_hi);
+ out_be32(&rxqd->bd_ring_base_lo, bd_ring_base_lo);
muram_writew(&rxqd->bd_ring_size, sizeof(struct fm_port_bd)
* RX_BD_RING_SIZE);
muram_writew(&rxqd->offset_in, 0);
@@ -272,6 +285,7 @@ static int fm_eth_tx_port_parameter_init(struct fm_eth
*fm_eth)
struct fm_port_global_pram *pram;
u32 pram_page_offset;
void *tx_bd_ring_base;
+
[U-Boot] [Patch V5 07/17] net/fm: bug fix when CONFIG_PHYLIB not defined
From: Shaohui Xie phy_shutdown should be wrapped by CONFIG_PHYLIB. Signed-off-by: Shaohui Xie Signed-off-by: Mingkai Hu Signed-off-by: Gong Qianyu --- V5: - No change. V4: - No change. V3: - New patch. drivers/net/fm/eth.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index d7d064b..1b62fd8 100644 --- a/drivers/net/fm/eth.c +++ b/drivers/net/fm/eth.c @@ -483,8 +483,10 @@ static void fm_eth_halt(struct eth_device *dev) /* disable bmi Rx port */ bmi_rx_port_disable(fm_eth->rx_port); +#ifdef CONFIG_PHYLIB if (fm_eth->phydev) phy_shutdown(fm_eth->phydev); +#endif } static int fm_eth_send(struct eth_device *dev, void *buf, int len) -- 2.1.0.27.g96db324 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch V5 08/17] net: Move some header files to include/
From: Shaohui Xie
The fsl_dtsec.h & fsl_tgec.h & fsl_fman.h can be shared on both ARM
and PPC, move it out of ppc to include/, and change the path in
drivers accordingly.
Signed-off-by: Shaohui Xie
Signed-off-by: Gong Qianyu
---
V5:
- No change.
V4:
- No change.
V3:
- No change.
V2:
- No change.
arch/powerpc/include/asm/immap_85xx.h | 2 +-
board/freescale/b4860qds/eth_b4860qds.c | 2 +-
board/freescale/corenet_ds/eth_hydra.c| 2 +-
board/freescale/corenet_ds/eth_p4080.c| 2 +-
board/freescale/corenet_ds/eth_superhydra.c | 2 +-
board/freescale/p1023rdb/p1023rdb.c | 2 +-
board/freescale/p2041rdb/eth.c| 2 +-
board/freescale/t102xqds/eth_t102xqds.c | 2 +-
board/freescale/t102xrdb/eth_t102xrdb.c | 2 +-
board/freescale/t1040qds/eth.c| 2 +-
board/freescale/t104xrdb/eth.c| 2 +-
board/freescale/t208xqds/eth_t208xqds.c | 2 +-
board/freescale/t208xrdb/eth_t208xrdb.c | 2 +-
board/freescale/t4qds/eth.c | 2 +-
board/freescale/t4rdb/eth.c | 2 +-
drivers/net/fm/dtsec.c| 2 +-
drivers/net/fm/eth.c | 4 ++--
drivers/net/fm/fm.h | 2 +-
drivers/net/fm/tgec.c | 2 +-
drivers/net/fm/tgec_phy.c | 2 +-
{arch/powerpc/include/asm => include}/fsl_dtsec.h | 0
{arch/powerpc/include/asm => include}/fsl_fman.h | 0
{arch/powerpc/include/asm => include}/fsl_tgec.h | 0
23 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 0c9d85e..101b8db 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -19,7 +19,7 @@
#include
#include
#include
-#include
+#include
#include
typedef struct ccsr_local {
diff --git a/board/freescale/b4860qds/eth_b4860qds.c
b/board/freescale/b4860qds/eth_b4860qds.c
index 501d4b3..df90476 100644
--- a/board/freescale/b4860qds/eth_b4860qds.c
+++ b/board/freescale/b4860qds/eth_b4860qds.c
@@ -26,7 +26,7 @@
#include
#include
#include
-#include
+#include
#include "../common/ngpixis.h"
#include "../common/fman.h"
diff --git a/board/freescale/corenet_ds/eth_hydra.c
b/board/freescale/corenet_ds/eth_hydra.c
index 396103f..172a55b 100644
--- a/board/freescale/corenet_ds/eth_hydra.c
+++ b/board/freescale/corenet_ds/eth_hydra.c
@@ -55,7 +55,7 @@
#include
#include
#include
-#include
+#include
#include "../common/ngpixis.h"
#include "../common/fman.h"
diff --git a/board/freescale/corenet_ds/eth_p4080.c
b/board/freescale/corenet_ds/eth_p4080.c
index 5cbec7f..c68dc2c 100644
--- a/board/freescale/corenet_ds/eth_p4080.c
+++ b/board/freescale/corenet_ds/eth_p4080.c
@@ -24,7 +24,7 @@
#include "../common/ngpixis.h"
#include "../common/fman.h"
-#include
+#include
#define EMI_NONE 0x
#define EMI_MASK 0xf000
diff --git a/board/freescale/corenet_ds/eth_superhydra.c
b/board/freescale/corenet_ds/eth_superhydra.c
index ad1bffd..62b1635 100644
--- a/board/freescale/corenet_ds/eth_superhydra.c
+++ b/board/freescale/corenet_ds/eth_superhydra.c
@@ -55,7 +55,7 @@
#include
#include
#include
-#include
+#include
#include "../common/ngpixis.h"
#include "../common/fman.h"
diff --git a/board/freescale/p1023rdb/p1023rdb.c
b/board/freescale/p1023rdb/p1023rdb.c
index 56f561a..074b713 100644
--- a/board/freescale/p1023rdb/p1023rdb.c
+++ b/board/freescale/p1023rdb/p1023rdb.c
@@ -26,7 +26,7 @@
#include
#include
#include
-#include
+#include
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/freescale/p2041rdb/eth.c b/board/freescale/p2041rdb/eth.c
index 532eeac..95fe85b 100644
--- a/board/freescale/p2041rdb/eth.c
+++ b/board/freescale/p2041rdb/eth.c
@@ -19,7 +19,7 @@
#include
#include
#include
-#include
+#include
#include "cpld.h"
#include "../common/fman.h"
diff --git a/board/freescale/t102xqds/eth_t102xqds.c
b/board/freescale/t102xqds/eth_t102xqds.c
index 441d6a3..99c23f7 100644
--- a/board/freescale/t102xqds/eth_t102xqds.c
+++ b/board/freescale/t102xqds/eth_t102xqds.c
@@ -21,7 +21,7 @@
#include
#include
#include
-#include
+#include
#include
#include "../common/qixis.h"
#include "../common/fman.h"
diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c
b/board/freescale/t102xrdb/eth_t102xrdb.c
index 856ec6e..02b283d 100644
--- a/board/freescale/t102xrdb/eth_t102xrdb.c
+++ b/board/freescale/t102xrdb/eth_t102xrdb.c
@@ -21,7 +21,7 @@
#include
#include
#include
-#include
+#include
#include
#include "../common/fman.h"
diff --git a/board/freescale/t1040qds/eth.c b/board/freescale/t1040qds/eth.c
index 8c82934..8bf34fa 100644
--- a/board/freescale/t1040qds/eth.c
+++ b/board/freescale/t1040qds/eth.c
@@ -17,7 +17,7 @@
#include
#include
[U-Boot] [Patch V5 09/17] net/fm: Add QSGMII PCS init
From: Shaohui Xie
QSGMII PCS needed to be programmed same as SGMII PCS, and there are
four ports in QSGMII PCS, port 0, 1, 2, 3, all the four ports shared
port 0's MDIO controller, so when programming port 0, we continue to
program other three ports.
Signed-off-by: Shaohui Xie
Signed-off-by: Mingkai Hu
Signed-off-by: Gong Qianyu
---
V5:
- No change.
V4:
- Remove the "if(priv->phyaddr%4 != 0)" condition in qsgmii_loop.
V3:
- No change.
V2:
- No change.
drivers/net/fm/eth.c | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index 38828c8..3220ae6 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -41,28 +41,35 @@ static void dtsec_configure_serdes(struct fm_eth *priv)
bus.priv = priv->mac->phyregs;
bool sgmii_2500 = (priv->enet_if ==
PHY_INTERFACE_MODE_SGMII_2500) ? true : false;
+ int i = 0;
+qsgmii_loop:
/* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
value = PHY_SGMII_IF_MODE_SGMII;
if (!sgmii_2500)
value |= PHY_SGMII_IF_MODE_AN;
- memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x14, value);
+ memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x14, value);
/* Dev ability according to SGMII specification */
value = PHY_SGMII_DEV_ABILITY_SGMII;
- memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x4, value);
+ memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x4, value);
/* Adjust link timer for SGMII -
1.6 ms in units of 8 ns = 2 * 10^5 = 0x30d40 */
- memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x13, 0x3);
- memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0xd40);
+ memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x3);
+ memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0xd40);
/* Restart AN */
value = PHY_SGMII_CR_DEF_VAL;
if (!sgmii_2500)
value |= PHY_SGMII_CR_RESET_AN;
- memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0, value);
+ memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0, value);
+
+ if ((priv->enet_if == PHY_INTERFACE_MODE_QSGMII) && (i < 3)) {
+ i++;
+ goto qsgmii_loop;
+ }
#else
struct dtsec *regs = priv->mac->base;
struct tsec_mii_mng *phyregs = priv->mac->phyregs;
@@ -91,6 +98,7 @@ static void dtsec_init_phy(struct eth_device *dev)
#endif
if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII ||
+ fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII ||
fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
dtsec_configure_serdes(fm_eth);
}
--
2.1.0.27.g96db324
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch V5 11/17] armv8/fsl_lsch3: Change arch to fsl-layerscape
From: Mingkai Hu
There are two LS series processors are built on ARMv8 Layersacpe
architecture currently, LS2085A and LS1043A. They are based on
ARMv8 core although use different chassis, so create fsl-layerscape
to refactor the common code for the LS series processors which also
paves the way for adding LS1043A platform.
Signed-off-by: Mingkai Hu
Signed-off-by: Gong Qianyu
---
V5:
- Move LS2085A ddr macros out of soc #ifdef.
- Move macros and structs from cpu.c to cpu.h.
- Wrap le32 and be32 functions for ccsr gur and scfg. Defined in soc.h
- Modify fsl-layerscape/Makefile.
V4:
- New patch.
arch/arm/cpu/armv8/Makefile| 2 +-
arch/arm/cpu/armv8/fsl-layerscape/Makefile | 21 ++
.../README => fsl-layerscape/README.lsch3} | 0
.../cpu/armv8/{fsl-lsch3 => fsl-layerscape}/cpu.c | 249 ++---
.../cpu/armv8/{fsl-lsch3 => fsl-layerscape}/cpu.h | 2 +-
.../cpu/armv8/{fsl-lsch3 => fsl-layerscape}/fdt.c | 17 +-
.../fsl_lsch3_serdes.c | 8 +-
.../speed.c => fsl-layerscape/fsl_lsch3_speed.c} | 12 +-
.../armv8/{fsl-lsch3 => fsl-layerscape}/lowlevel.S | 14 +-
.../{fsl-lsch3 => fsl-layerscape}/ls2085a_serdes.c | 3 +-
.../cpu/armv8/{fsl-lsch3 => fsl-layerscape}/mp.c | 15 +-
.../cpu/armv8/{fsl-lsch3 => fsl-layerscape}/soc.c | 35 +--
arch/arm/cpu/armv8/fsl-layerscape/spl.c| 76 +++
arch/arm/cpu/armv8/fsl-lsch3/Makefile | 13 --
arch/arm/cpu/armv8/fsl-lsch3/speed.h | 7 -
.../clock.h| 8 +-
arch/arm/include/asm/arch-fsl-layerscape/config.h | 59 +
arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 165 ++
.../{arch-fsl-lsch3 => arch-fsl-layerscape}/fdt.h | 4 +
.../fsl_serdes.h | 11 +-
.../immap_lsch3.h | 119 --
.../arm/include/asm/arch-fsl-layerscape/imx-regs.h | 55 +
.../ls2085a_stream_id.h| 0
arch/arm/include/asm/arch-fsl-layerscape/mmu.h | 10 +
.../asm/arch-fsl-layerscape}/mp.h | 10 +-
.../{arch-fsl-lsch3 => arch-fsl-layerscape}/soc.h | 21 +-
arch/arm/include/asm/arch-fsl-layerscape/speed.h | 10 +
arch/arm/include/asm/arch-fsl-lsch3/config.h | 185 ---
arch/arm/include/asm/arch-fsl-lsch3/gpio.h | 9 -
arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h | 13 --
arch/arm/include/asm/config.h | 7 +-
arch/arm/include/asm/global_data.h | 2 +-
board/freescale/ls2085aqds/Kconfig | 2 +-
board/freescale/ls2085aqds/eth.c | 1 -
board/freescale/ls2085aqds/ls2085aqds.c| 2 +-
board/freescale/ls2085ardb/Kconfig | 2 +-
board/freescale/ls2085ardb/eth_ls2085rdb.c | 1 -
board/freescale/ls2085ardb/ls2085ardb.c| 2 +-
drivers/i2c/mxc_i2c.c | 4 +-
drivers/misc/fsl_debug_server.c| 1 -
drivers/net/ldpaa_eth/ls2085a.c| 2 -
drivers/pci/pcie_layerscape.c | 4 +-
include/common.h | 3 +
include/configs/ls2085a_common.h | 47 +++-
44 files changed, 712 insertions(+), 521 deletions(-)
diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index adb11b3..48c041b 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -15,6 +15,6 @@ obj-y += cache.o
obj-y += tlb.o
obj-y += transition.o
-obj-$(CONFIG_FSL_LSCH3) += fsl-lsch3/
+obj-$(CONFIG_FSL_LAYERSCAPE) += fsl-layerscape/
obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/
obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
new file mode 100644
index 000..ccb3aa5
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -0,0 +1,21 @@
+#
+# Copyright 2014-2015, Freescale Semiconductor
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += cpu.o
+obj-y += lowlevel.o
+obj-y += soc.o
+obj-$(CONFIG_MP) += mp.o
+obj-$(CONFIG_OF_LIBFDT) += fdt.o
+obj-$(CONFIG_SPL) += spl.o
+
+ifneq ($(CONFIG_FSL_LSCH3),)
+obj-y += fsl_lsch3_speed.o
+obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch3_serdes.o
+endif
+
+ifneq ($(CONFIG_LS2085A),)
+obj-$(CONFIG_SYS_HAS_SERDES) += ls2085a_serdes.o
+endif
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/README
b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3
similarity index 100%
rename from arch/arm/cpu/armv8/fsl-lsch3/README
rename to arch/arm/cpu/armv8/fsl-layerscape/README.lsch3
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
similarity index 59%
rename from arch/arm/cpu/armv8/fsl-lsch3/cpu.c
rename to arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index eb1213e..c847a7b 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
+++ b
[U-Boot] [Patch V5 10/17] net/fm: fix MDIO controller base on FMAN2
From: Shaohui Xie
MDIO controller base on FMAN2 was defined as CONFIG_SYS_FSL_FM2_ADDR
plus offset, but CONFIG_SYS_FSL_FM2_ADDR only defined when there are two
FMANs, so we should only define MDIO controller base on FMAN2 when there
is FMAN2.
Signed-off-by: Shaohui Xie
Signed-off-by: Mingkai Hu
Signed-off-by: Gong Qianyu
---
V5:
- No change.
V4:
- No change.
V3:
- No change.
V2:
- No change.
include/fm_eth.h | 17 +
1 file changed, 17 insertions(+)
diff --git a/include/fm_eth.h b/include/fm_eth.h
index 3e1b9f4..d43f801 100644
--- a/include/fm_eth.h
+++ b/include/fm_eth.h
@@ -45,8 +45,10 @@ enum fm_eth_type {
#ifdef CONFIG_SYS_FMAN_V3
#define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfc000)
#define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000)
+#if (CONFIG_SYS_NUM_FMAN == 2)
#define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfc000)
#define CONFIG_SYS_FM2_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfd000)
+#endif
#else
#define CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR(CONFIG_SYS_FSL_FM1_ADDR +
0xe1120)
#define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xf1000)
@@ -89,6 +91,7 @@ enum fm_eth_type {
offsetof(struct ccsr_fman, memac[n-1]),\
}
#else
+#if (CONFIG_SYS_NUM_FMAN == 2)
#define FM_TGEC_INFO_INITIALIZER(idx, n) \
{ \
FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM2_TGEC_MDIO_ADDR) \
@@ -101,6 +104,20 @@ enum fm_eth_type {
.compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
offsetof(struct ccsr_fman, memac[n-1+8]),\
}
+#else
+#define FM_TGEC_INFO_INITIALIZER(idx, n) \
+{ \
+ FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \
+ .index = idx, \
+ .num= n - 1,\
+ .type = FM_ETH_10G_E, \
+ .port = FM##idx##_10GEC##n, \
+ .rx_port_id = RX_PORT_10G_BASE + n - 1, \
+ .tx_port_id = TX_PORT_10G_BASE + n - 1, \
+ .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
+ offsetof(struct ccsr_fman, memac[n-1+8]),\
+}
+#endif
#endif
#if (CONFIG_SYS_NUM_FM1_10GEC >= 3)
--
2.1.0.27.g96db324
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch V5 13/17] armv8/ls1043ardb: Add LS1043ARDB board support
From: Mingkai Hu
LS1043ARDB Specification:
-
Memory subsystem:
* 2GByte DDR4 SDRAM (32bit bus)
* 128 Mbyte NOR flash single-chip memory
* 512 Mbyte NAND flash
* 16 Mbyte high-speed SPI flash
* SD connector to interface with the SD memory card
Ethernet:
* XFI 10G port
* QSGMII with 4x 1G ports
* Two RGMII ports
PCIe:
* PCIe2 (Lanes C) to mini-PCIe slot
* PCIe3 (Lanes D) to PCIe slot
USB 3.0: two super speed USB 3.0 type A ports
UART: supports two UARTs up to 115200 bps for console
Signed-off-by: Hou Zhiqiang
Signed-off-by: Li Yang
Signed-off-by: Mingkai Hu
Signed-off-by: York Sun
Signed-off-by: Gong Qianyu
---
V5:
- No change.
V4:
- Change arch to layerscape.
- Add PCIe support.
- Move SMMU_BASE, GICC_BASE, GICD_BASE to ls1043a_common.h.
V3:
- Fix message typos.
- Add ddr model number in comments.
- Fix boot options in README.
- Remove some dead code.
V2:
- Replaced ns_access.h with fsl_csu.h.
arch/arm/Kconfig | 7 +
arch/arm/cpu/armv8/fsl-layerscape/Makefile | 4 +
arch/arm/cpu/armv8/fsl-layerscape/ls1043a_serdes.c | 86 ++
board/freescale/ls1043ardb/Kconfig | 16 ++
board/freescale/ls1043ardb/MAINTAINERS | 7 +
board/freescale/ls1043ardb/Makefile| 9 +
board/freescale/ls1043ardb/README | 85 +
board/freescale/ls1043ardb/cpld.c | 115 +
board/freescale/ls1043ardb/cpld.h | 43 +
board/freescale/ls1043ardb/ddr.c | 191 +
board/freescale/ls1043ardb/ddr.h | 45 +
board/freescale/ls1043ardb/ls1043ardb.c| 131 ++
configs/ls1043ardb_defconfig | 4 +
include/configs/ls1043a_common.h | 181 +++
include/configs/ls1043ardb.h | 191 +
15 files changed, 1115 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7981355..bd99bfb 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -631,6 +631,12 @@ config TARGET_LS1021ATWR
select CPU_V7
select SUPPORT_SPL
+config TARGET_LS1043ARDB
+ bool "Support ls1043ardb"
+ select ARM64
+ help
+ Support for Freescale LS1043ARDB platform.
+
config TARGET_H2200
bool "Support h2200"
select CPU_PXA
@@ -745,6 +751,7 @@ source "board/freescale/ls2085aqds/Kconfig"
source "board/freescale/ls2085ardb/Kconfig"
source "board/freescale/ls1021aqds/Kconfig"
source "board/freescale/ls1021atwr/Kconfig"
+source "board/freescale/ls1043ardb/Kconfig"
source "board/freescale/mx23evk/Kconfig"
source "board/freescale/mx25pdk/Kconfig"
source "board/freescale/mx28evk/Kconfig"
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index 4754e59..6fa08c8 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -23,4 +23,8 @@ endif
ifneq ($(CONFIG_LS2085A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls2085a_serdes.o
+else
+ifneq ($(CONFIG_LS1043A),)
+obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
+endif
endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_serdes.c
b/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_serdes.c
new file mode 100644
index 000..e54d389
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_serdes.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+
+struct serdes_config {
+ u32 protocol;
+ u8 lanes[SRDS_MAX_LANES];
+};
+
+static struct serdes_config serdes1_cfg_tbl[] = {
+ /* SerDes 1 */
+ {0x1555, {XFI_FM1_MAC9, PCIE1, PCIE2, PCIE3} },
+ {0x2555, {SGMII_2500_FM1_DTSEC9, PCIE1, PCIE2, PCIE3} },
+ {0x4555, {QSGMII_FM1_A, PCIE1, PCIE2, PCIE3} },
+ {0x4558, {QSGMII_FM1_A, PCIE1, PCIE2, SATA1} },
+ {0x1355, {XFI_FM1_MAC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3} },
+ {0x2355, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3} },
+ {0x3335, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5,
+ PCIE3} },
+ {0x3355, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3} },
+ {0x3358, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, SATA1} },
+ {0x3555, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, PCIE3} },
+ {0x3558, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, SATA1} },
+ {0x7000, {PCIE1, PCIE1, PCIE1, PCIE1} },
+ {0x9998, {PCIE1, PCIE2, PCIE3, SATA1} },
+ {0x6058, {PCIE1, PCIE1, PCIE2, SATA1} },
+ {0x1455, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE2, PCIE3} },
+ {0x2455, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3} },
+ {0x2255, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC2, PCIE2, PCIE3} },
+ {0x, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5,
+ S
[U-Boot] [Patch V5 14/17] armv8/ls1043ardb: Add nand boot support
Signed-off-by: Gong Qianyu
Signed-off-by: Hou Zhiqiang
Signed-off-by: Shaohui Xie
Signed-off-by: Mingkai Hu
---
V5:
- No change.
V4:
- Add enable_layerscape_ns_access() in fsl-layerscape/spl.c
V3:
- No change.
V2:
- Removed unecessary NAND_PAGE_SIZE in ls1043a_common.h.
- Fixed "select SUPPORT_SPL" in arch/arm/Kconfig.
- Used CONFIG_FSL_IFC instead of SPL_NAND_SUPPORT for init_early_memctl_regs()
- Replaced ns_access.h with fsl_csu.h.
arch/arm/Kconfig | 1 +
arch/arm/cpu/armv8/fsl-layerscape/spl.c| 3 ++
board/freescale/ls1043ardb/README | 1 +
board/freescale/ls1043ardb/cpld.c | 19 +
board/freescale/ls1043ardb/cpld.h | 1 +
board/freescale/ls1043ardb/ls1043ardb_pbi.cfg | 14 +++
board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg | 7
configs/ls1043ardb_nand_defconfig | 4 ++
include/configs/ls1043a_common.h | 27 +
include/configs/ls1043ardb.h | 46 ++
10 files changed, 123 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index bd99bfb..6584e85 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -634,6 +634,7 @@ config TARGET_LS1021ATWR
config TARGET_LS1043ARDB
bool "Support ls1043ardb"
select ARM64
+ select SUPPORT_SPL
help
Support for Freescale LS1043ARDB platform.
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c
b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
index 2f30d4b..ba551aa 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
@@ -71,6 +71,9 @@ void board_init_f(ulong dummy)
/* Clear the BSS */
memset(__bss_start, 0, __bss_end - __bss_start);
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+ enable_layerscape_ns_access();
+#endif
board_init_r(NULL, 0);
}
#endif
diff --git a/board/freescale/ls1043ardb/README
b/board/freescale/ls1043ardb/README
index d5925a9..4f15557 100644
--- a/board/freescale/ls1043ardb/README
+++ b/board/freescale/ls1043ardb/README
@@ -83,3 +83,4 @@ Start Address End Address Description Size
Booting Options
---
a) NOR boot
+b) NAND boot
diff --git a/board/freescale/ls1043ardb/cpld.c
b/board/freescale/ls1043ardb/cpld.c
index 3f1101e..f29383d 100644
--- a/board/freescale/ls1043ardb/cpld.c
+++ b/board/freescale/ls1043ardb/cpld.c
@@ -45,6 +45,22 @@ void cpld_set_defbank(void)
CPLD_WRITE(global_rst, 1);
}
+void cpld_set_nand(void)
+{
+ u16 reg = CPLD_CFG_RCW_SRC_NAND;
+ u8 reg5 = (u8)(reg >> 1);
+ u8 reg6 = (u8)(reg & 1);
+
+ cpld_rev_bit(®5);
+
+ CPLD_WRITE(soft_mux_on, 1);
+
+ CPLD_WRITE(cfg_rcw_src1, reg5);
+ CPLD_WRITE(cfg_rcw_src2, reg6);
+
+ CPLD_WRITE(system_rst, 1);
+}
+
#ifdef DEBUG
static void cpld_dump_regs(void)
{
@@ -91,6 +107,8 @@ int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char *
const argv[])
if (strcmp(argv[1], "reset") == 0) {
if (strcmp(argv[2], "altbank") == 0)
cpld_set_altbank();
+ else if (strcmp(argv[2], "nand") == 0)
+ cpld_set_nand();
else
cpld_set_defbank();
#ifdef DEBUG
@@ -109,6 +127,7 @@ U_BOOT_CMD(
"Reset the board or alternate bank",
"reset: reset to default bank\n"
"cpld reset altbank: reset to alternate bank\n"
+ "cpld reset nand: reset to boot from NAND flash\n"
#ifdef DEBUG
"cpld dump - display the CPLD registers\n"
#endif
diff --git a/board/freescale/ls1043ardb/cpld.h
b/board/freescale/ls1043ardb/cpld.h
index ea4efd8..5f43a8a 100644
--- a/board/freescale/ls1043ardb/cpld.h
+++ b/board/freescale/ls1043ardb/cpld.h
@@ -40,4 +40,5 @@ void cpld_rev_bit(unsigned char *value);
#define CPLD_SW_MUX_BANK_SEL 0x40
#define CPLD_BANK_SEL_MASK 0x07
#define CPLD_BANK_SEL_ALTBANK 0x04
+#define CPLD_CFG_RCW_SRC_NAND 0x106
#endif
diff --git a/board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
b/board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
new file mode 100644
index 000..f072274
--- /dev/null
+++ b/board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
@@ -0,0 +1,14 @@
+#Configure Scratch register
+09570600
+09570604 1000
+#Alt base register
+09570158 1000
+#Disable CCI barrier tranaction
+09570178 e010
+0918 0008
+#USB PHY frequency sel
+09570418 009e
+0957041c 009e
+09570420 009e
+#flush PBI data
+096100c0 000f
diff --git a/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
b/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
new file mode 100644
index 000..935ffc0
--- /dev/null
+++ b/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# serdes protocol
+081f 0c00
+14550002 80004012 e0106000 61002000
+000
[U-Boot] [Patch V5 12/17] armv8/fsl_lsch2: Add fsl_lsch2 SoC
From: Mingkai Hu
Freescale LayerScape with Chassis Generation 2 is a set of SoCs with
ARMv8 cores and 2rd generation of Chassis.
Signed-off-by: Li Yang
Signed-off-by: Hou Zhiqiang
Signed-off-by: Mingkai Hu
Signed-off-by: Gong Qianyu
---
V5:
- Move LS1043A ddr macros out of soc #ifdef.
- Move macros and structs from cpu.c to cpu.h.
- Wrap le32 and be32 functions for ccsr gur and scfg. Defined in soc.h
- Modify fsl-layerscape/Makefile.
V4:
- Add fsl_lsch2 to fsl-layerscape framework.
V3:
- Update MMU table initialization to match the latest code.
- Remove some dead code
- Rename #include to #include
V2:
- remove FSL_LS102xA_DEVDISR3_PCIE from immap_lsch2.h
arch/arm/cpu/armv8/fsl-layerscape/Makefile | 5 +
arch/arm/cpu/armv8/fsl-layerscape/README.lsch2 | 10 +
arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 13 +
.../cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c| 117 +
.../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 137 +
arch/arm/cpu/armv8/fsl-layerscape/soc.c| 17 +
arch/arm/include/asm/arch-fsl-layerscape/config.h | 40 ++
arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 64 +++
.../include/asm/arch-fsl-layerscape/fsl_serdes.h | 91
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 555 +
.../include/asm/arch-fsl-layerscape/ns_access.h| 158 ++
arch/arm/include/asm/arch-fsl-layerscape/soc.h | 6 +
arch/arm/include/asm/armv8/mmu.h | 1 +
include/common.h | 3 +
14 files changed, 1217 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index ccb3aa5..4754e59 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -14,6 +14,11 @@ obj-$(CONFIG_SPL) += spl.o
ifneq ($(CONFIG_FSL_LSCH3),)
obj-y += fsl_lsch3_speed.o
obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch3_serdes.o
+else
+ifneq ($(CONFIG_FSL_LSCH2),)
+obj-y += fsl_lsch2_speed.o
+obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch2_serdes.o
+endif
endif
ifneq ($(CONFIG_LS2085A),)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch2
b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch2
new file mode 100644
index 000..a6ef830
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch2
@@ -0,0 +1,10 @@
+#
+# Copyright 2015 Freescale Semiconductor
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+Freescale LayerScape with Chassis Generation 2
+
+This architecture supports Freescale ARMv8 SoCs with Chassis generation 2,
+for example LS1043A.
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index c847a7b..5a2d40f 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -180,6 +180,8 @@ static inline void early_mmu_setup(void)
set_pgtable_table(level1_table0,
CONFIG_SYS_FLASH_BASE >> SECTION_SHIFT_L1,
level2_table1);
+#elif defined(CONFIG_FSL_LSCH2)
+ set_pgtable_table(level1_table0, 1, level2_table1);
#endif
/* Find the table and fill in the block entries */
for (i = 0; i < ARRAY_SIZE(early_mmu_table); i++) {
@@ -215,6 +217,9 @@ static inline void early_mmu_setup(void)
*
* For LSCH3:
* Level 2 table 1 contains 512 entries for each 2MB from 32GB to 33GB.
+ * For LSCH2:
+ * Level 2 table 1 contains 512 entries for each 2MB from 1GB to 2GB.
+ * Level 2 table 2 contains 512 entries for each 2MB from 20GB to 21GB.
*/
static inline void final_mmu_setup(void)
{
@@ -225,6 +230,9 @@ static inline void final_mmu_setup(void)
u64 *level2_table0 = (u64 *)(gd->arch.tlb_addr + 0x3000);
#ifdef CONFIG_FSL_LSCH3
u64 *level2_table1 = (u64 *)(gd->arch.tlb_addr + 0x4000);
+#elif defined(CONFIG_FSL_LSCH2)
+ u64 *level2_table1 = (u64 *)(gd->arch.tlb_addr + 0x4000);
+ u64 *level2_table2 = (u64 *)(gd->arch.tlb_addr + 0x5000);
#endif
struct table_info table = {level0_table, 0, BLOCK_SIZE_L0};
@@ -239,6 +247,11 @@ static inline void final_mmu_setup(void)
set_pgtable_table(level1_table0,
CONFIG_SYS_FSL_QBMAN_BASE >> SECTION_SHIFT_L1,
level2_table1);
+#elif defined(CONFIG_FSL_LSCH2)
+ set_pgtable_table(level1_table0, 1, level2_table1);
+ set_pgtable_table(level1_table0,
+ CONFIG_SYS_FSL_QBMAN_BASE >> SECTION_SHIFT_L1,
+ level2_table2);
#endif
/* Find the table and fill in the block entries */
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
new file mode 100644
index 000..f7178d1
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#
[U-Boot] [Patch V5 16/17] armv8/ls1043ardb: esdhc: Add esdhc support for ls1043ardb
From: Yangbo Lu
This patch adds esdhc support for ls1043ardb.
Signed-off-by: Yangbo Lu
Signed-off-by: Gong Qianyu
---
V5:
- No change.
V4:
- Use CONFIG_FSL_ESDHC to enable get_sdhc_freq().
- Merge lsch2 and lsch3 into layerscape.
V3:
- No change.
V2:
- No change.
.../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 22 +-
board/freescale/ls1043ardb/ls1043ardb.c| 1 +
drivers/mmc/fsl_esdhc.c| 12 ++--
include/configs/ls1043a_common.h | 11 +++
include/fsl_esdhc.h| 2 +-
5 files changed, 40 insertions(+), 8 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
index 9d5bbe7..6f6a588 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -25,7 +25,7 @@ void get_sys_info(struct sys_info *sys_info)
struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
u32 ccr;
#endif
-#ifdef CONFIG_SYS_DPAA_FMAN
+#if defined(CONFIG_FSL_ESDHC) || defined(CONFIG_SYS_DPAA_FMAN)
u32 rcw_tmp;
#endif
struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
@@ -105,6 +105,11 @@ void get_sys_info(struct sys_info *sys_info)
#define HWA_CGA_M2_CLK_SEL 0x0007
#define HWA_CGA_M2_CLK_SHIFT 0
+#ifdef CONFIG_FSL_ESDHC
+ rcw_tmp = in_be32(&gur->rcwsr[15]);
+ rcw_tmp = (rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT;
+ sys_info->freq_sdhc = freq_c_pll[1] / rcw_tmp;
+#endif
#if defined(CONFIG_FSL_IFC)
ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
@@ -123,6 +128,10 @@ int get_clocks(void)
gd->bus_clk = sys_info.freq_systembus;
gd->mem_clk = sys_info.freq_ddrbus;
+#ifdef CONFIG_FSL_ESDHC
+ gd->arch.sdhc_clk = sys_info.freq_sdhc;
+#endif
+
if (gd->cpu_clk != 0)
return 0;
else
@@ -139,6 +148,13 @@ ulong get_ddr_freq(ulong dummy)
return gd->mem_clk;
}
+#ifdef CONFIG_FSL_ESDHC
+int get_sdhc_freq(ulong dummy)
+{
+ return gd->arch.sdhc_clk;
+}
+#endif
+
int get_serial_clock(void)
{
return gd->bus_clk;
@@ -149,6 +165,10 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
switch (clk) {
case MXC_I2C_CLK:
return get_bus_freq(0);
+#if defined(CONFIG_FSL_ESDHC)
+ case MXC_ESDHC_CLK:
+ return get_sdhc_freq(0);
+#endif
case MXC_DSPI_CLK:
return get_bus_freq(0);
case MXC_UART_CLK:
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c
b/board/freescale/ls1043ardb/ls1043ardb.c
index 6c0dd3f..461a195 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
#include
#include
#include
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 0b37002..471d6ee 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -106,7 +106,7 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct
mmc_data *data)
xfertyp |= XFERTYP_RSPTYP_48;
#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || \
- defined(CONFIG_LS102XA) || defined(CONFIG_LS2085A)
+ defined(CONFIG_LS102XA) || defined(CONFIG_FSL_LAYERSCAPE)
if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
xfertyp |= XFERTYP_CMDTYP_ABORT;
#endif
@@ -184,7 +184,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct
mmc_data *data)
int timeout;
struct fsl_esdhc_cfg *cfg = mmc->priv;
struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
-#ifdef CONFIG_LS2085A
+#ifdef CONFIG_FSL_LAYERSCAPE
dma_addr_t addr;
#endif
uint wml_value;
@@ -197,7 +197,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct
mmc_data *data)
esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
-#ifdef CONFIG_LS2085A
+#ifdef CONFIG_FSL_LAYERSCAPE
addr = virt_to_phys((void *)(data->dest));
if (upper_32_bits(addr))
printf("Error found for upper 32 bits\n");
@@ -223,7 +223,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct
mmc_data *data)
esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
wml_value << 16);
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
-#ifdef CONFIG_LS2085A
+#ifdef CONFIG_FSL_LAYERSCAPE
addr = virt_to_phys((void *)(data->src));
if (upper_32_bits(addr))
printf("Error found for upper 32 bits\n");
@@ -277,7 +277,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct
mmc_data *data)
static void check_and_invalidate_dcache_range
(struct mmc_cmd *cmd,
struct mmc_data *data) {
-#ifdef CONFIG_LS2085A
+#ifdef CONFIG_FSL_LAYERSCAPE
[U-Boot] [Patch V5 17/17] armv8/ls1043ardb: Add sd boot support
Signed-off-by: Gong Qianyu
---
V5:
- No change.
V4:
- No change.
V3:
- Squash the add cpld command patch to it.
V2:
- No change.
board/freescale/ls1043ardb/README| 1 +
board/freescale/ls1043ardb/cpld.c| 18 ++
board/freescale/ls1043ardb/cpld.h| 1 +
board/freescale/ls1043ardb/ls1043ardb.c | 6 +
board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg | 7 ++
configs/ls1043ardb_sdcard_defconfig | 4
include/configs/ls1043a_common.h | 30
include/configs/ls1043ardb.h | 11 -
8 files changed, 77 insertions(+), 1 deletion(-)
diff --git a/board/freescale/ls1043ardb/README
b/board/freescale/ls1043ardb/README
index 4f15557..0556e73 100644
--- a/board/freescale/ls1043ardb/README
+++ b/board/freescale/ls1043ardb/README
@@ -84,3 +84,4 @@ Booting Options
---
a) NOR boot
b) NAND boot
+c) SD boot
diff --git a/board/freescale/ls1043ardb/cpld.c
b/board/freescale/ls1043ardb/cpld.c
index f29383d..78c2824 100644
--- a/board/freescale/ls1043ardb/cpld.c
+++ b/board/freescale/ls1043ardb/cpld.c
@@ -61,6 +61,21 @@ void cpld_set_nand(void)
CPLD_WRITE(system_rst, 1);
}
+void cpld_set_sd(void)
+{
+ u16 reg = CPLD_CFG_RCW_SRC_SD;
+ u8 reg5 = (u8)(reg >> 1);
+ u8 reg6 = (u8)(reg & 1);
+
+ cpld_rev_bit(®5);
+
+ CPLD_WRITE(soft_mux_on, 1);
+
+ CPLD_WRITE(cfg_rcw_src1, reg5);
+ CPLD_WRITE(cfg_rcw_src2, reg6);
+
+ CPLD_WRITE(system_rst, 1);
+}
#ifdef DEBUG
static void cpld_dump_regs(void)
{
@@ -109,6 +124,8 @@ int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char *
const argv[])
cpld_set_altbank();
else if (strcmp(argv[2], "nand") == 0)
cpld_set_nand();
+ else if (strcmp(argv[2], "sd") == 0)
+ cpld_set_sd();
else
cpld_set_defbank();
#ifdef DEBUG
@@ -128,6 +145,7 @@ U_BOOT_CMD(
"reset: reset to default bank\n"
"cpld reset altbank: reset to alternate bank\n"
"cpld reset nand: reset to boot from NAND flash\n"
+ "cpld reset sd: reset to boot from SD card\n"
#ifdef DEBUG
"cpld dump - display the CPLD registers\n"
#endif
diff --git a/board/freescale/ls1043ardb/cpld.h
b/board/freescale/ls1043ardb/cpld.h
index 5f43a8a..bd59c0e 100644
--- a/board/freescale/ls1043ardb/cpld.h
+++ b/board/freescale/ls1043ardb/cpld.h
@@ -41,4 +41,5 @@ void cpld_rev_bit(unsigned char *value);
#define CPLD_BANK_SEL_MASK 0x07
#define CPLD_BANK_SEL_ALTBANK 0x04
#define CPLD_CFG_RCW_SRC_NAND 0x106
+#define CPLD_CFG_RCW_SRC_SD0x040
#endif
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c
b/board/freescale/ls1043ardb/ls1043ardb.c
index b0bdebb..8b6181f 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -25,12 +25,17 @@ DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
static const char *freq[3] = {"100.00MHZ", "156.25MHZ"};
+#ifndef CONFIG_SD_BOOT
u8 cfg_rcw_src1, cfg_rcw_src2;
u32 cfg_rcw_src;
+#endif
u32 sd1refclk_sel;
printf("Board: LS1043ARDB, boot from ");
+#ifdef CONFIG_SD_BOOT
+ puts("SD\n");
+#else
cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
cpld_rev_bit(&cfg_rcw_src1);
@@ -43,6 +48,7 @@ int checkboard(void)
puts("NAND\n");
else
printf("Invalid setting of SW4\n");
+#endif
printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver),
CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
diff --git a/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
b/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
new file mode 100644
index 000..28cd958
--- /dev/null
+++ b/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# RCW
+081f 0c00
+14550002 80004012 6004 61002000
+ 00038800
+ 1100 0096 0001
diff --git a/configs/ls1043ardb_sdcard_defconfig
b/configs/ls1043ardb_sdcard_defconfig
new file mode 100644
index 000..5fe0470
--- /dev/null
+++ b/configs/ls1043ardb_sdcard_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SYS_FSL_DDR4"
+CONFIG_ARM=y
+CONFIG_TARGET_LS1043ARDB=y
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index bdd852d..7c78403 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -69,6 +69,36 @@
#define CONFIG_BAUDRATE115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+/* SD boot SPL */
+#ifdef CONFIG_SD_BOOT
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_LDSCRIPT"arch/arm/cp
[U-Boot] [Patch V5 15/17] armv8/ls1043a: Add Fman support
From: Shaohui Xie
Signed-off-by: Hou Zhiqiang
Signed-off-by: Shaohui Xie
Signed-off-by: Mingkai Hu
Signed-off-by: Gong Qianyu
---
V5:
- No change.
V4:
- Change arch to layerscape.
V3:
- No change.
V2:
- No change.
arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 12 +++
arch/arm/cpu/armv8/fsl-layerscape/fdt.c| 6 ++
.../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 23
board/freescale/common/fman.c | 6 +-
board/freescale/ls1043ardb/Makefile| 1 +
board/freescale/ls1043ardb/eth.c | 77 +
board/freescale/ls1043ardb/ls1043ardb.c| 4 +
doc/README.fsl-dpaa| 4 +-
drivers/net/fm/Makefile| 1 +
drivers/net/fm/init.c | 10 +-
drivers/net/fm/ls1043.c| 119 +
include/configs/ls1043a_common.h | 12 +++
include/configs/ls1043ardb.h | 25 +
13 files changed, 295 insertions(+), 5 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 5a2d40f..d8c01a8 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -274,6 +274,9 @@ static inline void final_mmu_setup(void)
flush_dcache_range(gd->arch.tlb_addr,
gd->arch.tlb_addr + gd->arch.tlb_size);
+#ifdef CONFIG_SYS_DPAA_FMAN
+ flush_dcache_all();
+#endif
/* point TTBR to the new table */
el = current_el();
@@ -432,6 +435,9 @@ int print_cpuinfo(void)
printf("\n Bus: %-4s MHz ",
strmhz(buf, sysinfo.freq_systembus));
printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
+#ifdef CONFIG_SYS_DPAA_FMAN
+ printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
+#endif
#ifdef CONFIG_FSL_LSCH3
printf(" DP-DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus2));
#endif
@@ -468,6 +474,9 @@ int cpu_eth_init(bd_t *bis)
#ifdef CONFIG_FSL_MC_ENET
error = fsl_mc_ldpaa_init(bis);
#endif
+#ifdef CONFIG_FMAN_ENET
+ fm_standard_init(bis);
+#endif
return error;
}
@@ -485,6 +494,9 @@ int arch_early_init_r(void)
#ifdef CONFIG_SYS_HAS_SERDES
fsl_serdes_init();
#endif
+#ifdef CONFIG_FMAN_ENET
+ fman_enet_init();
+#endif
return 0;
}
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index aa88d34..9c841c2 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -18,6 +18,12 @@
#include
#endif
+int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
+{
+ return fdt_setprop_string(blob, offset, "phy-connection-type",
+phy_string_for_interface(phyc));
+}
+
#ifdef CONFIG_MP
void ft_fixup_cpu(void *blob)
{
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
index ea3723f..9d5bbe7 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -25,6 +25,9 @@ void get_sys_info(struct sys_info *sys_info)
struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
u32 ccr;
#endif
+#ifdef CONFIG_SYS_DPAA_FMAN
+ u32 rcw_tmp;
+#endif
struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
unsigned int cpu;
const u8 core_cplx_pll[8] = {
@@ -79,6 +82,26 @@ void get_sys_info(struct sys_info *sys_info)
#define HWA_CGA_M1_CLK_SEL 0xe000
#define HWA_CGA_M1_CLK_SHIFT 29
+#ifdef CONFIG_SYS_DPAA_FMAN
+ rcw_tmp = in_be32(&gur->rcwsr[7]);
+ switch ((rcw_tmp & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) {
+ case 2:
+ sys_info->freq_fman[0] = freq_c_pll[0] / 2;
+ break;
+ case 3:
+ sys_info->freq_fman[0] = freq_c_pll[0] / 3;
+ break;
+ case 6:
+ sys_info->freq_fman[0] = freq_c_pll[1] / 2;
+ break;
+ case 7:
+ sys_info->freq_fman[0] = freq_c_pll[1] / 3;
+ break;
+ default:
+ printf("Error: Unknown FMan1 clock select!\n");
+ break;
+ }
+#endif
#define HWA_CGA_M2_CLK_SEL 0x0007
#define HWA_CGA_M2_CLK_SHIFT 0
diff --git a/board/freescale/common/fman.c b/board/freescale/common/fman.c
index 9dc5402..26cf517 100644
--- a/board/freescale/common/fman.c
+++ b/board/freescale/common/fman.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011-2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier:GPL-2.0+
*/
@@ -10,7 +10,11 @@
#include
#include
+#ifdef CONFIG_FSL_LAYERSCAPE
+#include
+#else
#include
+#endif
/*
Re: [U-Boot] [PATCH] drivers: gpio: omap: add support for parsing additional gpio parameters
On 13 October 2015 at 02:27, Mugunthan V N wrote: > With DM_GPIO, gpio parameters like ACTIVE_(LOW/HIGH) are to be > parsed in xlate gpio drivers-ops. Since xlate is not implemented > in omap_gpio driver, the driver considers all gpio to be > ACTIVE_HIGH which is the default case and fails to return actual > gpio status for ACTIVE_LOW gpios. So adding .xlate ops to > omap_gpio. > > Signed-off-by: Mugunthan V N > --- > drivers/gpio/omap_gpio.c | 11 +++ > 1 file changed, 11 insertions(+) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] env: export fdt_blob to the environment variable
Hi,
On Monday, 12 October 2015, Thomas Chou wrote:
>
> Export fdt_blob to the environment variable. So that we may
> use it to boot Linux.
>
> Signed-off-by: Thomas Chou
> ---
> v2
> move the code to per board, nios2-generic.c.
> v3
> move the code to generic, board_r.c.
>
> common/board_r.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/common/board_r.c b/common/board_r.c
> index a4facf8..6f10a31 100644
> --- a/common/board_r.c
> +++ b/common/board_r.c
> @@ -449,6 +449,7 @@ static int initr_env(void)
> env_relocate();
> else
> set_default_env(NULL);
> + setenv_addr("fdt_blob", gd->fdt_blob);
>
> /* Initialize from environment */
> load_addr = getenv_ulong("loadaddr", 16, load_addr);
> --
> 2.1.4
>
We already have fdtcontroladdr, so how about using that instead?
Also please can you add docs to README.fdt-control? Also note that it
is read-only and cannot be changed. In fact changing it will be
ignored.
Regards,
Simon
___
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U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] arm: mmu: Add missing volatile for reading SCTLR register
Hello Alison, Sorry for the late comment. On Wed, 9 Sep 2015 10:22:02 +0800, Alison Wang wrote: > When building u-boot with the latest Linaro toolchain, such as > gcc-linaro-4.9, u-boot will hang at PCIE init on LS1021A platform. > The issue is reported on > http://comments.gmane.org/gmane.linux.linaro.toolchain/5163. > > As volatile is missing when reading SCTLR register and SCTLR is set > according to the value read from SCTLR, it causes CR_M bit is not set. > Then MMU is not enabled, the access to VA for PCIE fails. This comment seems misleading to me: it appears to imply that the "volatile" qualifier is added to alter the semantics of the mrc statement, whereas it is added only to prevent the compiler from optimizing out the whole asm statement and making get_cr() return garbage. I would prefer a commit message such as: Add 'volatile' qualifier to the asm statement in get_cr() so that the statement is not optimized out by the compiler. Without the 'volatile', get_cr() returns a wrong value which prevents enabling the MMU and later causes a PCIE VA access failure. If this is fine with you, I'll apply the patch with the comment altered as above. Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] vexpress64: Juno: Declare all 8GB of RAM and make them visible to the kernel.
On Fri, Oct 9, 2015 at 3:09 PM, Liviu Dudau wrote: > Juno comes with 8GB RAM, but U-Boot only passes 2GB to the kernel. > Declare a secondary memory bank and set the sizes correctly. > > Signed-off-by: Liviu Dudau Reviewed-by: Linus Walleij Yours, Linus Walleij ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] arm: socfpga: enable data/inst prefetch and shared override in the L2
On Wednesday, October 14, 2015 at 06:32:42 PM, Pavel Machek wrote: > On Mon 2015-10-12 09:59:57, dingu...@opensource.altera.com wrote: > > From: Dinh Nguyen > > > > Update the L2 AUX CTRL settings for the SoCFPGA. > > > > Enabling D and I prefetch bits helps improve SDRAM performance on the > > platform. > > > > Also, we need to enable bit 22 of the L2. By not having bit 22 set in the > > PL310 Auxiliary Control register (shared attribute override enable) has > > the side effect of transforming Normal Shared Non-cacheable reads into > > Cacheable no-allocate reads. > > > > Coherent DMA buffers in Linux always have a Cacheable alias via the > > kernel linear mapping and the processor can speculatively load cache > > lines into the PL310 controller. With bit 22 cleared, Non-cacheable > > reads would unexpectedly hit such cache lines leading to buffer > > corruption. > > > > Signed-off-by: Dinh Nguyen > > --- > > > > arch/arm/include/asm/pl310.h | 2 ++ > > arch/arm/mach-socfpga/misc.c | 12 > > 2 files changed, 14 insertions(+) > > > > diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h > > index 18b90b7..7a11405 100644 > > --- a/arch/arm/include/asm/pl310.h > > +++ b/arch/arm/include/asm/pl310.h > > @@ -17,6 +17,8 @@ > > > > #define L2X0_CTRL_EN 1 > > > > #define PL310_SHARED_ATT_OVERRIDE_ENABLE (1 << 22) > > > > +#define PL310_AUX_CTRL_DATA_PREFETCH_MASK (1 << 28) > > +#define PL310_AUX_CTRL_INST_PREFETCH_MASK (1 << 29) > > These would be > > arch/arm/include/asm/hardware/cache-l2x0.h:#define > L310_PREFETCH_CTRL_DATA_PREFETCH BIT(28) > arch/arm/include/asm/hardware/cache-l2x0.h:#define > L310_PREFETCH_CTRL_INSTR_PREFETCHBIT(29) > > ...in kernel. So maybe staying with L310_ prefix makes sense? > Otherwise it looks ok. Why is it L... in one and PL... in the other one ? What does the "PL" prefix stand for anyway ? Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 2/2] sunxi: Add defconfig for the Sinovoip BPI-M2 board
The Sinovoip BPI-M2 is a SBC board based on the A31s SoC it features
1G RAM, a microsd slot, Gbit ethernet, 4 usb-a USB-2 ports, ir receiver,
stereo headphone jack and hdmi video output.
The dts changes are identical to the dts files submitted upstream.
A few notes on the use if dldo and aldo regulators. DLDO1 is used
for Vdd for the ethernet phy, ALDO2 is used for AVdd for the ethernet
phy. ALDO1 is used to power the sdio wifi module.
Signed-off-by: Hans de Goede
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/sun6i-a31.dtsi | 18 +++
arch/arm/dts/sun6i-a31s-sinovoip-bpi-m2.dts | 194
board/sunxi/MAINTAINERS | 1 +
configs/Sinovoip_BPI_M2_defconfig | 18 +++
5 files changed, 233 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/sun6i-a31s-sinovoip-bpi-m2.dts
create mode 100644 configs/Sinovoip_BPI_M2_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 3538553..8b656e9 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -124,7 +124,8 @@ dtb-$(CONFIG_MACH_SUN6I) += \
sun6i-a31-mele-a1000g-quad.dtb \
sun6i-a31-mixtile-loftq.dtb \
sun6i-a31s-cs908.dtb \
- sun6i-a31s-primo81.dtb
+ sun6i-a31s-primo81.dtb \
+ sun6i-a31s-sinovoip-bpi-m2.dtb
dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-ainol-aw1.dtb \
sun7i-a20-bananapi.dtb \
diff --git a/arch/arm/dts/sun6i-a31.dtsi b/arch/arm/dts/sun6i-a31.dtsi
index 39953e7..44f889f 100644
--- a/arch/arm/dts/sun6i-a31.dtsi
+++ b/arch/arm/dts/sun6i-a31.dtsi
@@ -659,6 +659,24 @@
allwinner,pull = ;
};
+ mmc2_pins_a: mmc2@0 {
+ allwinner,pins = "PC6", "PC7", "PC8", "PC9",
+"PC10", "PC11";
+ allwinner,function = "mmc2";
+ allwinner,drive = ;
+ allwinner,pull = ;
+ };
+
+ mmc2_8bit_emmc_pins: mmc2@1 {
+ allwinner,pins = "PC6", "PC7", "PC8", "PC9",
+"PC10", "PC11", "PC12",
+"PC13", "PC14", "PC15",
+"PC24";
+ allwinner,function = "mmc2";
+ allwinner,drive = ;
+ allwinner,pull = ;
+ };
+
gmac_pins_mii_a: gmac_mii@0 {
allwinner,pins = "PA0", "PA1", "PA2", "PA3",
"PA8", "PA9", "PA11",
diff --git a/arch/arm/dts/sun6i-a31s-sinovoip-bpi-m2.dts
b/arch/arm/dts/sun6i-a31s-sinovoip-bpi-m2.dts
new file mode 100644
index 000..db7fa13
--- /dev/null
+++ b/arch/arm/dts/sun6i-a31s-sinovoip-bpi-m2.dts
@@ -0,0 +1,194 @@
+/*
+ * Copyright 2015 Hans de Goede
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION W
[U-Boot] [PATCH v2 1/2] sunxi: Fix sorting of boards in MAINTAINERS
Signed-off-by: Hans de Goede --- board/sunxi/MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index c6371ea..dd27487 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -29,11 +29,11 @@ F: configs/mk802_a10s_defconfig F: configs/q8_a13_tablet_defconfig F: configs/r7-tv-dongle_defconfig F: configs/UTOO_P66_defconfig +F: configs/Wobo_i5_defconfig F: include/configs/sun6i.h F: configs/CSQ_CS908_defconfig F: configs/Mele_A1000G_quad_defconfig F: configs/Mele_M9_defconfig -F: configs/Wobo_i5_defconfig F: include/configs/sun7i.h F: configs/A20-OLinuXino_MICRO_defconfig F: configs/Bananapi_defconfig -- 2.5.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] vexpress64: Juno: Add initialisation code for Juno R1 PCIe host bridge.
On Fri, Oct 9, 2015 at 3:09 PM, Liviu Dudau wrote:
> Juno R1 has an XpressRICH3 PCIe host bridge that needs to be initialised
> in order for the Linux kernel to be able to enumerate the bus. Add
> support code here that enables the host bridge, trains the links and
> sets up the Address Translation Tables.
>
> Signed-off-by: Liviu Dudau
Very nice! Now we (soon) have PCIe on the Juno.
Did you:
- Test with compiling in e.g. network cards and booting off of
ethernet on PCIe?
- Test what happens with a simple VGA card on PCIe?
Sometimes the VGA card BIOS need to be initialized using
an emulator running the x86 ROM and I never got that working
on anything ARM :( (Maybe PCIe doesn't suffer from this? Just
vanilla PCI has this problem? What do I know.)
> +#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
> +void xr3pci_set_atr_entry(unsigned long base, unsigned long src_addr,
> + unsigned long trsl_addr, int window_size,
> + int trsl_param)
> +{
(...)
> int board_init(void)
> {
> +#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
(...)
> +#endif
> return 0;
> }
> +++ b/board/armltd/vexpress64/vexpress64.h
> @@ -0,0 +1,60 @@
> +#ifndef __VEXPRESS64_H__
> +#define __VEXPRESS64_H__
Instead of peppering with #ifdefs I suggest you do like this:
- Create two new files named
board/armltd/vexpress64/pcie.c
board/armltd/vexpress64/pcie.h
- Move all the #defines from the vexpress64.h file into
the top of the pcie.c file.
- Use the pcie.h file for prototypes + stubs like this:
#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
void vexpress64_pcie_init(void);
#else
static inline void vexpress64_pcie_init(void)
{
}
#endif
Then board_init() can unconditionallt call these functions and
they will be stubbed out if compiled for anything else than Juno.
Yours,
Linus Walleij
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[U-Boot] [PATCHv2] arm: socfpga: enable data/inst prefetch and shared override in the L2
From: Dinh Nguyen
Update the L2 AUX CTRL settings for the SoCFPGA.
Enabling D and I prefetch bits helps improve SDRAM performance on the
platform.
Also, we need to enable bit 22 of the L2. By not having bit 22 set in the
PL310 Auxiliary Control register (shared attribute override enable) has the
side effect of transforming Normal Shared Non-cacheable reads into Cacheable
no-allocate reads.
Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.
Signed-off-by: Dinh Nguyen
---
v2: s/PL310_/L310_
---
arch/arm/include/asm/pl310.h | 2 ++
arch/arm/mach-socfpga/misc.c | 12
2 files changed, 14 insertions(+)
diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h
index de7650e..d588f94 100644
--- a/arch/arm/include/asm/pl310.h
+++ b/arch/arm/include/asm/pl310.h
@@ -17,6 +17,8 @@
#define L2X0_CTRL_EN 1
#define L310_SHARED_ATT_OVERRIDE_ENABLE(1 << 22)
+#define L310_AUX_CTRL_DATA_PREFETCH_MASK (1 << 28)
+#define L310_AUX_CTRL_INST_PREFETCH_MASK (1 << 29)
struct pl310_regs {
u32 pl310_cache_id;
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 0940cc5..bbd31ef 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -52,6 +52,18 @@ void enable_caches(void)
#endif
}
+void v7_outer_cache_enable(void)
+{
+ /* disable the L2 cache */
+ writel(0, &pl310->pl310_ctrl);
+
+ /* enable BRESP, instruction and data prefetch, full line of zeroes */
+ setbits_le32(&pl310->pl310_aux_ctrl,
+L310_AUX_CTRL_DATA_PREFETCH_MASK |
+L310_AUX_CTRL_INST_PREFETCH_MASK |
+L310_SHARED_ATT_OVERRIDE_ENABLE);
+}
+
/*
* DesignWare Ethernet initialization
*/
--
2.4.5
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Re: [U-Boot] [PATCH 1/2] pl310: arm: fix up define typo for the share override bit
On Wed, Oct 14, 2015 at 11:31 AM, Pavel Machek wrote: > On Mon 2015-10-12 09:59:56, dingu...@opensource.altera.com wrote: >> From: Dinh Nguyen >> >> s/L310_SHARED_ATT_OVERRIDE_ENABLE/PL310_SHARED_ATT_OVERRIDE_ENABLE >> >> Signed-off-by: Dinh Nguyen > > Well, in kernel, pl310 -related registers also have L310 prefix (no > PL), so I'm not sure it was a typo... > You're right. Sorry for the noise. Dinh ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] arm: socfpga: enable data/inst prefetch and shared override in the L2
On 10/15/2015 09:32 AM, Marek Vasut wrote: > On Wednesday, October 14, 2015 at 06:32:42 PM, Pavel Machek wrote: >> On Mon 2015-10-12 09:59:57, dingu...@opensource.altera.com wrote: >>> From: Dinh Nguyen >>> >>> Update the L2 AUX CTRL settings for the SoCFPGA. >>> >>> Enabling D and I prefetch bits helps improve SDRAM performance on the >>> platform. >>> >>> Also, we need to enable bit 22 of the L2. By not having bit 22 set in the >>> PL310 Auxiliary Control register (shared attribute override enable) has >>> the side effect of transforming Normal Shared Non-cacheable reads into >>> Cacheable no-allocate reads. >>> >>> Coherent DMA buffers in Linux always have a Cacheable alias via the >>> kernel linear mapping and the processor can speculatively load cache >>> lines into the PL310 controller. With bit 22 cleared, Non-cacheable >>> reads would unexpectedly hit such cache lines leading to buffer >>> corruption. >>> >>> Signed-off-by: Dinh Nguyen >>> --- >>> >>> arch/arm/include/asm/pl310.h | 2 ++ >>> arch/arm/mach-socfpga/misc.c | 12 >>> 2 files changed, 14 insertions(+) >>> >>> diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h >>> index 18b90b7..7a11405 100644 >>> --- a/arch/arm/include/asm/pl310.h >>> +++ b/arch/arm/include/asm/pl310.h >>> @@ -17,6 +17,8 @@ >>> >>> #define L2X0_CTRL_EN 1 >>> >>> #define PL310_SHARED_ATT_OVERRIDE_ENABLE (1 << 22) >>> >>> +#define PL310_AUX_CTRL_DATA_PREFETCH_MASK (1 << 28) >>> +#define PL310_AUX_CTRL_INST_PREFETCH_MASK (1 << 29) >> >> These would be >> >> arch/arm/include/asm/hardware/cache-l2x0.h:#define >> L310_PREFETCH_CTRL_DATA_PREFETCH BIT(28) >> arch/arm/include/asm/hardware/cache-l2x0.h:#define >> L310_PREFETCH_CTRL_INSTR_PREFETCHBIT(29) >> >> ...in kernel. So maybe staying with L310_ prefix makes sense? >> Otherwise it looks ok. > > Why is it L... in one and PL... in the other one ? What does the "PL" > prefix stand for anyway ? > As Pavel pointed out, it should be L310_x as this is how the Linux kernel is defining it. It's my mistake in the previous patch to change the define to PL310. I'll respin this patch with L310_PREFETCH_CTRL_DATA_PREFETCH and L310_PREFETCH_CTRL_INSTR_PREFETCH. Dinh ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Relocation issue - need help!
On Tue, 2015-10-06 at 11:17 +, Joakim Tjernlund wrote:
> On Thu, 2015-10-01 at 08:57 +, Joakim Tjernlund wrote:
> > On Wed, 2015-09-30 at 21:35 +0200, Marek Vasut wrote:
> > > On Wednesday, September 30, 2015 at 08:24:10 PM, Andy Fleming wrote:
> > >
> > > Hi!
> > >
> > > > On Thu, Oct 23, 2014 at 8:10 AM, Wolfgang Denk wrote:
> > > > > Dear Joakim, dear Dirk,
> > > > >
> > > > > In message > > c1257d7a.0024d...@transmode.se> you wrote:
> > > > > > Ouch, that was a nasty surprise.
> > > > >
> > > > > Indeed.
> > > > >
> > > > > > > In my original mail I referenced this potential solution, at
> > > > > > > least it
> > > > > > > worked for me:
> > > > > > > https://gcc.gnu.org/ml/gcc-help/2014-02/msg00054.html
> > > > > >
> > > > > > That looks like the correct fix but I presume both .data.rel.ro and
> > > > > > data.rel.ro.local should be added?
> > > > >
> > > > > I can confirm:
> > > > >
> > > > > 1) The problem was observed with gcc 4.8.1 [as in Yocto 1.5.x / ELDK
> > > > >
> > > > >5.5.x].
> > > > >
> > > > > 2) Switching back to gcc 4.7.2 [as in Yocto 1.4 / ELDK 5.4] makes the
> > > > >
> > > > >problem go away.
> > > > >
> > > > > 3) Switching forward to gcc 4.9.1 [as in Yocto 1.7 / ELDK 5.7] makes
> > > > >
> > > > >the problem go away.
> > > > >
> > > > > 4) For the problemativ 4.8.x versions of GCC, the following patch
> > > > >
> > > > >apparently solves the problem for my (MPC5200 based) board - guess
> > > > >this would have to be applied to all .lds files...
> > > > >
> > > > > diff --git a/arch/powerpc/cpu/mpc5xxx/u-boot.lds
> > > > > b/arch/powerpc/cpu/mpc5xxx/u-boot.lds index cd9e23f..82c86d7 100644
> > > > > --- a/arch/powerpc/cpu/mpc5xxx/u-boot.lds
> > > > > +++ b/arch/powerpc/cpu/mpc5xxx/u-boot.lds
> > > > > @@ -27,6 +27,8 @@ SECTIONS
> > > > >
> > > > >{
> > > > >
> > > > > _GOT2_TABLE_ = .;
> > > > > KEEP(*(.got2))
> > > > >
> > > > > +KEEP(*(.data.rel.ro))
> > > > > +KEEP(*(.data.rel.ro.local))
> > > > >
> > > > > KEEP(*(.got))
> > > > > PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
> > > > > _FIXUP_TABLE_ = .;
> > > > >
> > > > > Given that GCC 4.9.1 apparently solves this issue I wonder which
> > > > > approach we should take?
> > > > >
> > > > > Should we blacklist GCC 4.8.x (and 4.9.0) like the kernel folks are
> > > > > doing [1] ?
> > > > >
> > > > > [1] https://lkml.org/lkml/2014/10/10/272
> > > >
> > > > Was there a resolution to this thread? I just spent a bunch of time
> > > > trying to figure out why u-boot was crashing, and eventually
> > > > determined that switching from 4.9.0 to 4.6.3 solved the problem.
> > > > Should I submit a patch to do what was suggested above? Or add the
> > > > "blacklist" patch? If so, it should be noted that 4.9.0 is the current
> > > > default installed when you ask buildman to install a powerpc cross
> > > > compiler...
> > >
> > > Blacklist patch please, thank you!
> >
> > Yes, but all gcc 4.8.x versions?
> >
> > There is a fix here
> > https://gcc.gnu.org/ml/gcc-patches/2014-04/msg01679.html
> > but I don't know if it got committed or not or which version.
> >
> > I am using gcc 4.8.4 and it works but I have one problem, if I erase uboot
> > after relocation, u-boot misbehavex or crashes so there is something off
> > still.
> >
> > Does it work for all but me to erase u-boot after relocation?
> > Using T1040(mpc85xx family)
>
> Here is a better URL:
> http://patchwork.ozlabs.org/patch/342888/
>
> From what I can tell the above bug has been fixed in gcc 4.8.5(4.8.4 has the
> error)
> and 4.9.3 (by looking at varasm.c).
>
> Adding KEEP(*(.data.rel.ro.local)) i u-boot.lds does not seem to be the
> correct fix as it is not an .fixup entry?
After upgrading to gcc 4.9.3 I still see this bug(there is no .fixup entry)
The bug can be avoided with -fno-ira-hoist-pressure and while you are it,
throw in -mbss-plt to reduce size
Jocke
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Re: [U-Boot] [PATCH 1/2] armv8: LS2080A: Rename LS2085A to reflect LS2080A
On 10/15/2015 02:14 AM, Prabhakar Kushwaha wrote:
> From: Pratiyush Mohan Srivastava
>
> LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP
> personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc.
>
> So renaming existing LS2085A code base to reflect LS2080A (Prime personality)
>
> Signed-off-by: Pratiyush Mohan Srivastava
> ---
> diff --git a/arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c
> b/arch/arm/cpu/armv8/fsl-lsch3/ls2080a_serdes.c
> similarity index 98%
> rename from arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c
> rename to arch/arm/cpu/armv8/fsl-lsch3/ls2080a_serdes.c
> index 0b79a50..64da31c 100644
> --- a/arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c
> +++ b/arch/arm/cpu/armv8/fsl-lsch3/ls2080a_serdes.c
> @@ -29,7 +29,7 @@ static struct serdes_config serdes1_cfg_tbl[] = {
> SGMII1 } },
> {0x26, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, XFI2, XFI1 } },
> {0x28, {SGMII8, SGMII7, SGMII6, SGMII5, XFI4, XFI3, XFI2, XFI1 } },
> - {0x2A, {XFI8, XFI7, XFI6, XFI5, XFI4, XFI3, XFI2, XFI1 } },
> + {0x2A, {NONE, NONE, NONE, XFI5, XFI4, XFI3, XFI2, XFI1 } },
Is this change related for LS2080 only? Does LS2085 use the first four lanes?
With this patch, target LS2080AQDS/RDB will support both LS2080 and LS2085,
correct?
York
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Re: [U-Boot] [PATCH 1/2] armv8: LS2080A: Rename LS2085A to reflect LS2080A
On 10/15/2015 09:25 AM, York Sun wrote:
>
>
> On 10/15/2015 02:14 AM, Prabhakar Kushwaha wrote:
>> From: Pratiyush Mohan Srivastava
>>
>> LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP
>> personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc.
>>
>> So renaming existing LS2085A code base to reflect LS2080A (Prime personality)
>>
>> Signed-off-by: Pratiyush Mohan Srivastava
>>
>> ---
>
>
>
>> diff --git a/arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c
>> b/arch/arm/cpu/armv8/fsl-lsch3/ls2080a_serdes.c
>> similarity index 98%
>> rename from arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c
>> rename to arch/arm/cpu/armv8/fsl-lsch3/ls2080a_serdes.c
>> index 0b79a50..64da31c 100644
>> --- a/arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c
>> +++ b/arch/arm/cpu/armv8/fsl-lsch3/ls2080a_serdes.c
>> @@ -29,7 +29,7 @@ static struct serdes_config serdes1_cfg_tbl[] = {
>> SGMII1 } },
>> {0x26, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, XFI2, XFI1 } },
>> {0x28, {SGMII8, SGMII7, SGMII6, SGMII5, XFI4, XFI3, XFI2, XFI1 } },
>> -{0x2A, {XFI8, XFI7, XFI6, XFI5, XFI4, XFI3, XFI2, XFI1 } },
>> +{0x2A, {NONE, NONE, NONE, XFI5, XFI4, XFI3, XFI2, XFI1 } },
>
> Is this change related for LS2080 only? Does LS2085 use the first four lanes?
>
> With this patch, target LS2080AQDS/RDB will support both LS2080 and LS2085,
> correct?
Please ignore this comment. I see my answer in your second patch.
York
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Re: [U-Boot] [PATCH] arm: ls1021atwr: optimize the deep sleep latency
>> Yuantian, >> >> Please explain more why the second stage u-boot is reserved? Wouldn't >> Linux overwrite the memory? >> > If both CONFIG_DEEP_SLEEP and CONFIG_SD_BOOT are defined, > The DDR memory the second stage uboot occupied whould be reserved. > It is achieved in commit: 41ba57d0c which is the first patch to add the deep > sleep support. > > This patch doesn't reserve any memory, it just utilized the fact that the > second stage uboot has been reserved already if deep sleep is enabled. > Thanks for explanation. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] configs: ls1021atwr: Enable ID EEPROM for SD boot
On 10/15/2015 12:55 AM, Yuan Yao-B46683 wrote: > Hi york, > > The earlier SoC is just LS1021a rev1.0, but rev1.0 haven't delivery to the > customer. > Also the rev1.0 has since gone out of production. > So we don't have necessary to support rev1.0 because no one will or possibly > to use rev1.0. > OK. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/3][v3] crypto/fsl: SEC driver cleanup for 64 bit and endianness
On 09/17/2015 03:46 AM, Aneesh Bansal wrote:
> The SEC driver code has been cleaned up to work for 64 bit
> physical addresses and systems where endianess of SEC block
> is different from the Core.
> Changes:
> 1. Descriptor created on Core is modified as per SEC block
>endianness before the job is submitted.
> 2. The read/write of physical addresses to Job Rings will
>be depend on endianness of SEC block as 32 bit low and
>high part of the 64 bit address will vary.
> 3. The 32 bit low and high part of the 64 bit address in
>descriptor will vary depending on endianness of SEC.
>
> Signed-off-by: Aneesh Bansal
> ---
> Changes in v3:sec_out_phys and sec_in_phys
> The rwad/write for 64 bit address is done using 32 bit
> aadr_lo and addr_hi. There is no need to define wrapper
> functions sec_out_phys and sec_in_phys.
>
> drivers/crypto/fsl/desc_constr.h | 26 +
> drivers/crypto/fsl/fsl_hash.c| 8 ++--
> drivers/crypto/fsl/jr.c | 83
> ++--
> drivers/crypto/fsl/jr.h | 7 ++--
> include/fsl_sec.h| 6 +--
> 5 files changed, 106 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
> index 17392c9..c88c727 100644
> --- a/drivers/crypto/fsl/jr.c
> +++ b/drivers/crypto/fsl/jr.c
> @@ -11,6 +11,7 @@
> #include "fsl_sec.h"
> #include "jr.h"
> #include "jobdesc.h"
> +#include "desc_constr.h"
>
> #define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1))
> #define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), (head) + 1, (size))
> @@ -154,19 +155,35 @@ static int jr_hw_reset(void)
>
> /* -1 --- error, can't enqueue -- no space available */
> static int jr_enqueue(uint32_t *desc_addr,
> -void (*callback)(uint32_t desc, uint32_t status, void *arg),
> +void (*callback)(uint32_t status, void *arg),
> void *arg)
> {
> struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
> int head = jr.head;
> - dma_addr_t desc_phys_addr = virt_to_phys(desc_addr);
> + uint32_t desc_word;
> + int length = desc_len(desc_addr);
> + int i;
> +#ifdef CONFIG_PHYS_64BIT
> + uint32_t *addr_hi, *addr_lo;
> +#endif
> +
> + /* The descriptor must be submitted to SEC block as per endianness
> + * of the SEC Block.
> + * So, if the endianness of Core and SEC block is different, each word
> + * of the descriptor will be byte-swapped.
> + */
> + for (i = 0; i < length; i++) {
> + desc_word = desc_addr[i];
> + sec_out32((uint32_t *)&desc_addr[i], desc_word);
> + }
> +
> + phys_addr_t desc_phys_addr = virt_to_phys(desc_addr);
>
> if (sec_in32(®s->irsa) == 0 ||
> CIRC_SPACE(jr.head, jr.tail, jr.size) <= 0)
> return -1;
>
> jr.info[head].desc_phys_addr = desc_phys_addr;
> - jr.info[head].desc_addr = (uint32_t)desc_addr;
> jr.info[head].callback = (void *)callback;
> jr.info[head].arg = arg;
> jr.info[head].op_done = 0;
> @@ -177,9 +194,29 @@ static int jr_enqueue(uint32_t *desc_addr,
> ARCH_DMA_MINALIGN);
> flush_dcache_range(start, end);
>
> - jr.input_ring[head] = desc_phys_addr;
> +#ifdef CONFIG_PHYS_64BIT
> + /* Write the 64 bit Descriptor address on Input Ring.
> + * The 32 bit hign and low part of the address will
> + * depend on endianness of SEC block.
> + */
> +#ifdef CONFIG_SYS_FSL_SEC_LE
> + addr_lo = (uint32_t *)(&jr.input_ring[head]);
> + addr_hi = (uint32_t *)(&jr.input_ring[head]) + 1;
> +#elif defined(CONFIG_SYS_FSL_SEC_BE)
> + addr_hi = (uint32_t *)(&jr.input_ring[head]);
> + addr_lo = (uint32_t *)(&jr.input_ring[head]) + 1;
> +#endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
> +
> + sec_out32(addr_hi, (uint32_t)(desc_phys_addr >> 32));
> + sec_out32(addr_lo, (uint32_t)(desc_phys_addr));
> +
> +#else
> + /* Write the 32 bit Descriptor address on Input Ring. */
> + sec_out32(&jr.input_ring[head], desc_phys_addr);
> +#endif /* ifdef CONFIG_PHYS_64BIT */
> +
> start = (unsigned long)&jr.input_ring[head] & ~(ARCH_DMA_MINALIGN - 1);
> - end = ALIGN(start + sizeof(dma_addr_t), ARCH_DMA_MINALIGN);
> + end = ALIGN(start + sizeof(phys_addr_t), ARCH_DMA_MINALIGN);
> flush_dcache_range(start, end);
>
> jr.head = (head + 1) & (jr.size - 1);
> @@ -195,8 +232,11 @@ static int jr_dequeue(void)
> int head = jr.head;
> int tail = jr.tail;
> int idx, i, found;
> - void (*callback)(uint32_t desc, uint32_t status, void *arg);
> + void (*callback)(uint32_t status, void *arg);
> void *arg = NULL;
> +#ifdef CONFIG_PHYS_64BIT
> + uint32_t *addr_hi, *addr_lo;
> +#endif
>
> while (sec_in32(®s->orsf) && CIRC_CNT(jr.head, jr.tail, jr.size)) {
> unsigned long start = (unsigned long)jr.output_ring &
> @@ -208,14 +248,
Re: [U-Boot] [PATCH 2/2] vexpress64: Juno: Add initialisation code for Juno R1 PCIe host bridge.
On Thu, 15 Oct 2015 16:42:19 +0200
Linus Walleij wrote:
> On Fri, Oct 9, 2015 at 3:09 PM, Liviu Dudau wrote:
>
> > Juno R1 has an XpressRICH3 PCIe host bridge that needs to be initialised
> > in order for the Linux kernel to be able to enumerate the bus. Add
> > support code here that enables the host bridge, trains the links and
> > sets up the Address Translation Tables.
> >
> > Signed-off-by: Liviu Dudau
>
> Very nice! Now we (soon) have PCIe on the Juno.
>
> Did you:
>
> - Test with compiling in e.g. network cards and booting off of
> ethernet on PCIe?
>
> - Test what happens with a simple VGA card on PCIe?
> Sometimes the VGA card BIOS need to be initialized using
> an emulator running the x86 ROM and I never got that working
> on anything ARM :( (Maybe PCIe doesn't suffer from this? Just
> vanilla PCI has this problem? What do I know.)
Hi Linus,
Please note that this patchset does not enable enough functionality in
U-Boot to allow for PCIe testing.
However, together with my Linux patchset series[1] I have tested U-Boot
plus mainline Linux v4.3-rc5 on Juno r1 with 3x USB-to-PCIe cards and
a Radeon HD6400 card. I have even got framebuffer out of the Radeon
card :)
>
> > +#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
> > +void xr3pci_set_atr_entry(unsigned long base, unsigned long src_addr,
> > + unsigned long trsl_addr, int window_size,
> > + int trsl_param)
> > +{
> (...)
> > int board_init(void)
> > {
> > +#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
> (...)
> > +#endif
> > return 0;
> > }
>
> > +++ b/board/armltd/vexpress64/vexpress64.h
> > @@ -0,0 +1,60 @@
> > +#ifndef __VEXPRESS64_H__
> > +#define __VEXPRESS64_H__
>
> Instead of peppering with #ifdefs I suggest you do like this:
>
> - Create two new files named
> board/armltd/vexpress64/pcie.c
> board/armltd/vexpress64/pcie.h
>
> - Move all the #defines from the vexpress64.h file into
> the top of the pcie.c file.
>
> - Use the pcie.h file for prototypes + stubs like this:
>
> #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
> void vexpress64_pcie_init(void);
> #else
> static inline void vexpress64_pcie_init(void)
> {
> }
> #endif
>
> Then board_init() can unconditionallt call these functions and
> they will be stubbed out if compiled for anything else than Juno.
>
> Yours,
> Linus Walleij
OK, I will do that. I'm waiting on some feedback from Ryan Harkin that
wanted to test the patchset with some Linaro kernels and I will post
a v2.
Best regards,
Liviu
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| I would like to |
| fix the world, |
| but they're not |
| giving me the |
\ source code! /
---
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Re: [U-Boot] [PATCH 2/2] arm: socfpga: enable data/inst prefetch and shared override in the L2
On Thursday, October 15, 2015 at 05:04:38 PM, Dinh Nguyen wrote: Hi! > >>> diff --git a/arch/arm/include/asm/pl310.h > >>> b/arch/arm/include/asm/pl310.h index 18b90b7..7a11405 100644 > >>> --- a/arch/arm/include/asm/pl310.h > >>> +++ b/arch/arm/include/asm/pl310.h > >>> @@ -17,6 +17,8 @@ > >>> > >>> #define L2X0_CTRL_EN 1 > >>> > >>> #define PL310_SHARED_ATT_OVERRIDE_ENABLE (1 << 22) > >>> > >>> +#define PL310_AUX_CTRL_DATA_PREFETCH_MASK(1 << 28) > >>> +#define PL310_AUX_CTRL_INST_PREFETCH_MASK(1 << 29) > >> > >> These would be > >> > >> arch/arm/include/asm/hardware/cache-l2x0.h:#define > >> L310_PREFETCH_CTRL_DATA_PREFETCH BIT(28) > >> arch/arm/include/asm/hardware/cache-l2x0.h:#define > >> L310_PREFETCH_CTRL_INSTR_PREFETCHBIT(29) > >> > >> ...in kernel. So maybe staying with L310_ prefix makes sense? > >> Otherwise it looks ok. > > > > Why is it L... in one and PL... in the other one ? What does the "PL" > > prefix stand for anyway ? > > As Pavel pointed out, it should be L310_x as this is how the Linux > kernel is defining it. It's my mistake in the previous patch to change > the define to PL310. > > I'll respin this patch with L310_PREFETCH_CTRL_DATA_PREFETCH and > L310_PREFETCH_CTRL_INSTR_PREFETCH. Well that didn't answer either of my questions ;-) Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] arm: socfpga: enable data/inst prefetch and shared override in the L2
On Thu, Oct 15, 2015 at 1:08 PM, Marek Vasut wrote: > On Thursday, October 15, 2015 at 05:04:38 PM, Dinh Nguyen wrote: > > Hi! > >> >>> diff --git a/arch/arm/include/asm/pl310.h >> >>> b/arch/arm/include/asm/pl310.h index 18b90b7..7a11405 100644 >> >>> --- a/arch/arm/include/asm/pl310.h >> >>> +++ b/arch/arm/include/asm/pl310.h >> >>> @@ -17,6 +17,8 @@ >> >>> >> >>> #define L2X0_CTRL_EN 1 >> >>> >> >>> #define PL310_SHARED_ATT_OVERRIDE_ENABLE (1 << 22) >> >>> >> >>> +#define PL310_AUX_CTRL_DATA_PREFETCH_MASK(1 << 28) >> >>> +#define PL310_AUX_CTRL_INST_PREFETCH_MASK(1 << 29) >> >> >> >> These would be >> >> >> >> arch/arm/include/asm/hardware/cache-l2x0.h:#define >> >> L310_PREFETCH_CTRL_DATA_PREFETCH BIT(28) >> >> arch/arm/include/asm/hardware/cache-l2x0.h:#define >> >> L310_PREFETCH_CTRL_INSTR_PREFETCHBIT(29) >> >> >> >> ...in kernel. So maybe staying with L310_ prefix makes sense? >> >> Otherwise it looks ok. >> > >> > Why is it L... in one and PL... in the other one ? What does the "PL" >> > prefix stand for anyway ? >> >> As Pavel pointed out, it should be L310_x as this is how the Linux >> kernel is defining it. It's my mistake in the previous patch to change >> the define to PL310. >> >> I'll respin this patch with L310_PREFETCH_CTRL_DATA_PREFETCH and >> L310_PREFETCH_CTRL_INSTR_PREFETCH. > > Well that didn't answer either of my questions ;-) It should have been just 'L" and not "PL" at all. Dinh ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 2/2] sunxi: Add defconfig for the Sinovoip BPI-M2 board
On Thu, 2015-10-15 at 16:33 +0200, Hans de Goede wrote: > The Sinovoip BPI-M2 is a SBC board based on the A31s SoC it features > 1G RAM, a microsd slot, Gbit ethernet, 4 usb-a USB-2 ports, ir > receiver, > stereo headphone jack and hdmi video output. > > The dts changes are identical to the dts files submitted upstream. > > A few notes on the use if dldo and aldo regulators. DLDO1 is used > for Vdd for the ethernet phy, ALDO2 is used for AVdd for the ethernet > phy. ALDO1 is used to power the sdio wifi module. > > Signed-off-by: Hans de Goede Acked-by: Ian Campbell and for the 1/2 as well, which hardly needs an ack IMHO. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 12/14] sunxi: Add support for android boot image
On Thu, 2015-10-15 at 14:34 +0200, Maxime Ripard wrote: > When using the fastboot boot command, the image sent to U-Boot will be an > Android boot image. If the support is missing, that won't obviously work, obviously won't ?? > so we need it in our configuration. > > Signed-off-by: Maxime Ripard Acked-by: Ian Campbell > --- > include/configs/sunxi-common.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi > -common.h > index e1ba7914cda1..d7fc9ea7d099 100644 > --- a/include/configs/sunxi-common.h > +++ b/include/configs/sunxi-common.h > @@ -347,6 +347,7 @@ extern int soft_i2c_gpio_scl; > #define CONFIG_CMD_FASTBOOT > #define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR > #define CONFIG_FASTBOOT_BUF_SIZE 0x200 > +#define CONFIG_ANDROID_BOOT_IMAGE > > #define CONFIG_FASTBOOT_FLASH > #define CONFIG_FASTBOOT_FLASH_MMC_DEV0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Patch V5 11/17] armv8/fsl_lsch3: Change arch to fsl-layerscape
On 10/15/2015 06:02 AM, Gong Qianyu wrote:
> From: Mingkai Hu
>
> There are two LS series processors are built on ARMv8 Layersacpe
> architecture currently, LS2085A and LS1043A. They are based on
> ARMv8 core although use different chassis, so create fsl-layerscape
> to refactor the common code for the LS series processors which also
> paves the way for adding LS1043A platform.
>
> Signed-off-by: Mingkai Hu
> Signed-off-by: Gong Qianyu
> ---
> V5:
> - Move LS2085A ddr macros out of soc #ifdef.
> - Move macros and structs from cpu.c to cpu.h.
> - Wrap le32 and be32 functions for ccsr gur and scfg. Defined in soc.h
> - Modify fsl-layerscape/Makefile.
> V4:
> - New patch.
>
> arch/arm/cpu/armv8/Makefile| 2 +-
> arch/arm/cpu/armv8/fsl-layerscape/Makefile | 21 ++
> .../README => fsl-layerscape/README.lsch3} | 0
> .../cpu/armv8/{fsl-lsch3 => fsl-layerscape}/cpu.c | 249
> ++---
> .../cpu/armv8/{fsl-lsch3 => fsl-layerscape}/cpu.h | 2 +-
> .../cpu/armv8/{fsl-lsch3 => fsl-layerscape}/fdt.c | 17 +-
> .../fsl_lsch3_serdes.c | 8 +-
> .../speed.c => fsl-layerscape/fsl_lsch3_speed.c} | 12 +-
> .../armv8/{fsl-lsch3 => fsl-layerscape}/lowlevel.S | 14 +-
> .../{fsl-lsch3 => fsl-layerscape}/ls2085a_serdes.c | 3 +-
> .../cpu/armv8/{fsl-lsch3 => fsl-layerscape}/mp.c | 15 +-
> .../cpu/armv8/{fsl-lsch3 => fsl-layerscape}/soc.c | 35 +--
> arch/arm/cpu/armv8/fsl-layerscape/spl.c| 76 +++
> arch/arm/cpu/armv8/fsl-lsch3/Makefile | 13 --
> arch/arm/cpu/armv8/fsl-lsch3/speed.h | 7 -
> .../clock.h| 8 +-
> arch/arm/include/asm/arch-fsl-layerscape/config.h | 59 +
> arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 165 ++
> .../{arch-fsl-lsch3 => arch-fsl-layerscape}/fdt.h | 4 +
> .../fsl_serdes.h | 11 +-
> .../immap_lsch3.h | 119 --
> .../arm/include/asm/arch-fsl-layerscape/imx-regs.h | 55 +
> .../ls2085a_stream_id.h| 0
> arch/arm/include/asm/arch-fsl-layerscape/mmu.h | 10 +
> .../asm/arch-fsl-layerscape}/mp.h | 10 +-
> .../{arch-fsl-lsch3 => arch-fsl-layerscape}/soc.h | 21 +-
> arch/arm/include/asm/arch-fsl-layerscape/speed.h | 10 +
> arch/arm/include/asm/arch-fsl-lsch3/config.h | 185 ---
> arch/arm/include/asm/arch-fsl-lsch3/gpio.h | 9 -
> arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h | 13 --
> arch/arm/include/asm/config.h | 7 +-
> arch/arm/include/asm/global_data.h | 2 +-
> board/freescale/ls2085aqds/Kconfig | 2 +-
> board/freescale/ls2085aqds/eth.c | 1 -
> board/freescale/ls2085aqds/ls2085aqds.c| 2 +-
> board/freescale/ls2085ardb/Kconfig | 2 +-
> board/freescale/ls2085ardb/eth_ls2085rdb.c | 1 -
> board/freescale/ls2085ardb/ls2085ardb.c| 2 +-
> drivers/i2c/mxc_i2c.c | 4 +-
> drivers/misc/fsl_debug_server.c| 1 -
> drivers/net/ldpaa_eth/ls2085a.c| 2 -
> drivers/pci/pcie_layerscape.c | 4 +-
> include/common.h | 3 +
> include/configs/ls2085a_common.h | 47 +++-
> 44 files changed, 712 insertions(+), 521 deletions(-)
>
You missed board/freescale/ls2085a/Kconfig and
board/freescale/ls2085a/ls2085a.c.
York
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[U-Boot] [PATCH v2 1/7] fastboot: Implement OEM format only when we have MMC support
The current fastboot support assumes that CONFIG_FASTBOOT_FLASH implies
that we have an MMC in our system, which might not be the case if we have
some other storage device.
Change the configuration option protecting that call to
FASTBOOT_FLASH_MMC_DEV, that makes much more sense.
Signed-off-by: Maxime Ripard
Reviewed-by: Tom Rini
---
drivers/usb/gadget/f_fastboot.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c
index ca01a018b5d1..ece48e668c96 100644
--- a/drivers/usb/gadget/f_fastboot.c
+++ b/drivers/usb/gadget/f_fastboot.c
@@ -554,7 +554,7 @@ static void cb_flash(struct usb_ep *ep, struct usb_request
*req)
static void cb_oem(struct usb_ep *ep, struct usb_request *req)
{
char *cmd = req->buf;
-#ifdef CONFIG_FASTBOOT_FLASH
+#ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV
if (strncmp("format", cmd + 4, 6) == 0) {
char cmdbuf[32];
sprintf(cmdbuf, "gpt write mmc %x $partitions",
--
2.5.3
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[U-Boot] [PATCH v2 4/7] sunxi: Use Kconfig CONFIG_MMC
Not all sunxi boards have an MMC embedded. Switching to the Kconfig option will allow to enable or disable the support in each boards' defconfig. Signed-off-by: Maxime Ripard --- board/sunxi/Kconfig| 4 drivers/mmc/Kconfig| 2 +- include/configs/sunxi-common.h | 8 +--- 3 files changed, 10 insertions(+), 4 deletions(-) diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index b3367779af9b..f6f2a605eca3 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -227,6 +227,10 @@ config OLD_SUNXI_KERNEL_COMPAT Set this to enable various workarounds for old kernels, this results in sub-optimal settings for newer kernels, only enable if needed. +config MMC + depends on !UART0_PORT_F + default y if ARCH_SUNXI + config MMC0_CD_PIN string "Card detect pin for mmc0" default "" diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index d3d7d911e484..ceae7bcaec6a 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -2,7 +2,7 @@ menu "MMC Host controller Support" config MMC bool "Enable MMC support" - depends on UNUSED + depends on ARCH_SUNXI help TODO: Move all architectures to use this option diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 879d0f42385f..dd314468be45 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -140,8 +140,7 @@ #endif /* mmc config */ -#if !defined(CONFIG_UART0_PORT_F) -#define CONFIG_MMC +#if defined(CONFIG_MMC) #define CONFIG_GENERIC_MMC #define CONFIG_CMD_MMC #define CONFIG_MMC_SUNXI @@ -197,7 +196,7 @@ #define CONFIG_SPL_LIBDISK_SUPPORT -#if !defined(CONFIG_UART0_PORT_F) +#if defined(CONFIG_MMC) #define CONFIG_SPL_MMC_SUPPORT #endif @@ -354,9 +353,12 @@ extern int soft_i2c_gpio_scl; #define CONFIG_FASTBOOT_BUF_SIZE 0x200 #define CONFIG_FASTBOOT_FLASH + +#ifdef CONFIG_MMC #define CONFIG_FASTBOOT_FLASH_MMC_DEV 0 #define CONFIG_EFI_PARTITION #endif +#endif #ifdef CONFIG_USB_FUNCTION_MASS_STORAGE #define CONFIG_CMD_USB_MASS_STORAGE -- 2.5.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 5/7] sun5i: Sync the DTSI with the kernel
Add the latest kernel changes to the sun5i family DTSI.
Signed-off-by: Maxime Ripard
---
arch/arm/dts/sun5i-a10s.dtsi | 47 ---
arch/arm/dts/sun5i-a13.dtsi | 28 -
arch/arm/dts/sun5i-r8.dtsi | 59
arch/arm/dts/sun5i.dtsi | 22 +
4 files changed, 146 insertions(+), 10 deletions(-)
create mode 100644 arch/arm/dts/sun5i-r8.dtsi
diff --git a/arch/arm/dts/sun5i-a10s.dtsi b/arch/arm/dts/sun5i-a10s.dtsi
index 4173e1e59713..bddd0de88af6 100644
--- a/arch/arm/dts/sun5i-a10s.dtsi
+++ b/arch/arm/dts/sun5i-a10s.dtsi
@@ -77,6 +77,15 @@
clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
status = "disabled";
};
+
+ framebuffer@2 {
+ compatible = "allwinner,simple-framebuffer",
+"simple-framebuffer";
+ allwinner,pipeline = "de_be0-lcd0-tve0";
+ clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
+<&ahb_gates 44>;
+ status = "disabled";
+ };
};
clocks {
@@ -85,6 +94,17 @@
compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb>;
+ clock-indices = <0>, <1>,
+ <2>, <5>, <6>,
+ <7>, <8>, <9>,
+ <10>, <13>,
+ <14>, <17>, <18>,
+ <20>, <21>, <22>,
+ <26>, <28>, <32>,
+ <34>, <36>, <40>,
+ <43>, <44>,
+ <46>, <51>,
+ <52>;
clock-output-names = "ahb_usbotg", "ahb_ehci",
"ahb_ohci", "ahb_ss", "ahb_dma",
"ahb_bist", "ahb_mmc0", "ahb_mmc1",
@@ -103,6 +123,9 @@
compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
reg = <0x01c20068 0x4>;
clocks = <&apb0>;
+ clock-indices = <0>, <3>,
+ <5>, <6>,
+ <10>;
clock-output-names = "apb0_codec", "apb0_iis",
"apb0_pio", "apb0_ir",
"apb0_keypad";
@@ -113,9 +136,14 @@
compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
reg = <0x01c2006c 0x4>;
clocks = <&apb1>;
+ clock-indices = <0>, <1>,
+ <2>, <16>,
+ <17>, <18>,
+ <19>;
clock-output-names = "apb1_i2c0", "apb1_i2c1",
- "apb1_i2c2", "apb1_uart0", "apb1_uart1",
- "apb1_uart2", "apb1_uart3";
+"apb1_i2c2", "apb1_uart0",
+"apb1_uart1", "apb1_uart2",
+"apb1_uart3";
};
};
@@ -137,6 +165,14 @@
#size-cells = <0>;
};
+ pwm: pwm@01c20e00 {
+ compatible = "allwinner,sun5i-a10s-pwm";
+ reg = <0x01c20e00 0xc>;
+ clocks = <&osc24M>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
uart0: serial@01c28000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
@@ -176,13 +212,6 @@
allwinner,pull = ;
};
- uart3_pins_a: uart3@0 {
- allwinner,pins = "PG9", "PG10";
- allwinner,function = "uart3";
- allwinner,drive = ;
- allwinner,pull = ;
- };
-
emac_pins_a: emac0@0 {
allwinner,pins = "PA0", "PA1", "PA2",
"PA3", "PA4", "PA5", "PA6",
diff --git a/arch/arm/dts/sun5i-a13.dtsi b/arch/arm/dts/sun5i-a13.dtsi
index 976d4faa2179..d910d3a6c41c 100644
--- a/arch/arm/dts/sun5i-a13.dtsi
+++ b/arch/arm/dts/sun5i-a13.dtsi
@@ -104,6 +104,16 @@
compatible = "allwinner,sun5i-a13-ahb-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb>;
+ clock-indices = <0>, <1>,
+
[U-Boot] [PATCH v2 0/7] ARM: sunxi: Introduce CHIP support
Hi, Here is a serie introducing the support for the Allwinner R8 and the Nextthing's CHIP. The only missing parts for now are the display on the composite output and the NAND support that will come in due time. Everything else should work just fine, including the USB gadget and host support. Let me know what you think, Maxime Changes from v1: - Rebased on top of current sunxi next branch - Added regulators voltage - Synced the DTS with what has been accepted in the kernel - Added CONFIG_MMC rework Maxime Ripard (7): fastboot: Implement OEM format only when we have MMC support mmc: Add generic Kconfig option sunxi: board: Only try to use the MMC related functions if enabled sunxi: Use Kconfig CONFIG_MMC sun5i: Sync the DTSI with the kernel axp209: Sync the DTSI with the kernel sunxi: Add CHIP support arch/arm/cpu/armv7/sunxi/board.c | 6 +- arch/arm/dts/Makefile| 3 +- arch/arm/dts/axp209.dtsi | 5 + arch/arm/dts/sun5i-a10s.dtsi | 47 +++-- arch/arm/dts/sun5i-a13.dtsi | 28 - arch/arm/dts/sun5i-r8-chip.dts | 214 +++ arch/arm/dts/sun5i-r8.dtsi | 59 +++ arch/arm/dts/sun5i.dtsi | 22 board/sunxi/Kconfig | 4 + configs/CHIP_defconfig | 14 +++ drivers/mmc/Kconfig | 6 ++ drivers/usb/gadget/f_fastboot.c | 2 +- include/configs/sunxi-common.h | 8 +- 13 files changed, 402 insertions(+), 16 deletions(-) create mode 100644 arch/arm/dts/sun5i-r8-chip.dts create mode 100644 arch/arm/dts/sun5i-r8.dtsi create mode 100644 configs/CHIP_defconfig -- 2.5.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 2/7] mmc: Add generic Kconfig option
Add a generic Kconfig option for the CONFIG_MMC option that was used before in the configuration headers. Since all the architectures need to be converted to that first, depend on an non-existent config option that will be extended with architectures that use that option. Signed-off-by: Maxime Ripard --- drivers/mmc/Kconfig | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 6277f92ef5b7..d3d7d911e484 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -1,5 +1,11 @@ menu "MMC Host controller Support" +config MMC + bool "Enable MMC support" + depends on UNUSED + help + TODO: Move all architectures to use this option + config DM_MMC bool "Enable MMC controllers using Driver Model" depends on DM -- 2.5.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 7/7] sunxi: Add CHIP support
The C.H.I.P. is a small SBC with an Allwinner R8, 8GB of NAND, 512MB of
RAM, USB host and OTG, a wifi / bluetooth combo chip, an audio/video jack
and two connectors to plug additional boards on top of it.
The DT is identical to the DT submitted to the upstream kernel.
Signed-off-by: Maxime Ripard
Reviewed-by: Tom Rini
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/sun5i-r8-chip.dts | 214 +
configs/CHIP_defconfig | 14 +++
3 files changed, 230 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/sun5i-r8-chip.dts
create mode 100644 configs/CHIP_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index fb953ebd53ee..353855317fe0 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -113,7 +113,8 @@ dtb-$(CONFIG_MACH_SUN5I) += \
sun5i-a13-olinuxino.dtb \
sun5i-a13-olinuxino-micro.dtb \
sun5i-a13-q8-tablet.dtb \
- sun5i-a13-utoo-p66.dtb
+ sun5i-a13-utoo-p66.dtb \
+ sun5i-r8-chip.dtb
dtb-$(CONFIG_MACH_SUN6I) += \
sun6i-a31-app4-evb1.dtb \
sun6i-a31-colombus.dtb \
diff --git a/arch/arm/dts/sun5i-r8-chip.dts b/arch/arm/dts/sun5i-r8-chip.dts
new file mode 100644
index ..abf3ccb1a82c
--- /dev/null
+++ b/arch/arm/dts/sun5i-r8-chip.dts
@@ -0,0 +1,214 @@
+/*
+ * Copyright 2015 Free Electrons
+ * Copyright 2015 NextThing Co
+ *
+ * Maxime Ripard
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun5i-r8.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include
+#include
+
+/ {
+ model = "NextThing C.H.I.P.";
+ compatible = "nextthing,chip", "allwinner,sun5i-r8";
+
+ aliases {
+ i2c0 = &i2c0;
+ i2c2 = &i2c2;
+ serial0 = &uart1;
+ serial1 = &uart3;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ reg = <0x34>;
+
+ /*
+* The interrupt is routed through the "External Fast
+* Interrupt Request" pin (ball G13 of the module)
+* directly to the main interrupt controller, without
+* any other controller interfering.
+*/
+ interrupts = <0>;
+ };
+};
+
+#include "axp209.dtsi"
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ status = "okay";
+
+ xio: gpio@38 {
+ compatible = "nxp,pcf8574a";
+ reg = <0x38>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-parent = <&pio>;
+ interrupts = <6 0 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>;
+
[U-Boot] [PATCH v2 3/7] sunxi: board: Only try to use the MMC related functions if enabled
So far, even if CONFIG_MMC was not enabled the board code was trying to use
the MMC-related functions, resulting in linker errors.
Protect those calls by an ifdef.
Signed-off-by: Maxime Ripard
---
arch/arm/cpu/armv7/sunxi/board.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 1d79ba1126ae..4785ac68a9a2 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -136,7 +136,7 @@ DECLARE_GLOBAL_DATA_PTR;
*/
u32 spl_boot_device(void)
{
- struct mmc *mmc0, *mmc1;
+ __maybe_unused struct mmc *mmc0, *mmc1;
/*
* When booting from the SD card or NAND memory, the "eGON.BT0"
* signature is expected to be found in memory at the address 0x0004
@@ -157,15 +157,18 @@ u32 spl_boot_device(void)
return BOOT_DEVICE_BOARD;
/* The BROM will try to boot from mmc0 first, so try that first. */
+#ifdef CONFIG_MMC
mmc_initialize(gd->bd);
mmc0 = find_mmc_device(0);
if (sunxi_mmc_has_egon_boot_signature(mmc0))
return BOOT_DEVICE_MMC1;
+#endif
/* Fallback to booting NAND if enabled. */
if (IS_ENABLED(CONFIG_SPL_NAND_SUPPORT))
return BOOT_DEVICE_NAND;
+#ifdef CONFIG_MMC
if (CONFIG_MMC_SUNXI_SLOT_EXTRA == 2) {
mmc1 = find_mmc_device(1);
if (sunxi_mmc_has_egon_boot_signature(mmc1)) {
@@ -179,6 +182,7 @@ u32 spl_boot_device(void)
return BOOT_DEVICE_MMC2;
}
}
+#endif
panic("Could not determine boot source\n");
return -1; /* Never reached */
--
2.5.3
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[U-Boot] [PATCH v2 6/7] axp209: Sync the DTSI with the kernel
Linux had a number of changes to the AXP209 DTSI. Sync ours.
Signed-off-by: Maxime Ripard
---
arch/arm/dts/axp209.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/dts/axp209.dtsi b/arch/arm/dts/axp209.dtsi
index 24c935c72e5e..051ab3ba9a65 100644
--- a/arch/arm/dts/axp209.dtsi
+++ b/arch/arm/dts/axp209.dtsi
@@ -89,4 +89,9 @@
regulator-name = "ldo5";
};
};
+
+ usb_power_supply: usb_power_supply {
+ compatible = "x-powers,axp202-usb-power-supply";
+ status = "disabled";
+ };
};
--
2.5.3
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Re: [U-Boot] [PATCH] configs: ls1021atwr: Enable ID EEPROM for SD boot
Hi Yuan On 15/10/15 12:40 PM, York Sun wrote: On 10/15/2015 12:55 AM, Yuan Yao-B46683 wrote: Hi york, The earlier SoC is just LS1021a rev1.0, but rev1.0 haven't delivery to the customer. Also the rev1.0 has since gone out of production. So we don't have necessary to support rev1.0 because no one will or possibly to use rev1.0. Just to make this clear, the boards we bought all show : CPU: Freescale LayerScape LS1021E, Version: 1.0, (0x87081110) When you mention "rev1.0 haven't delivery to the customer" are you not referring to Rev 1.0 silicon ? Regards Sinan Akman OK. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [ANN] U-Boot v2015.10-rc5 released
On Thu, Oct 15, 2015 at 03:52:08AM +0200, Andreas Färber wrote: > Am 15.10.2015 um 02:40 schrieb Tom Rini: > > On Thu, Oct 15, 2015 at 02:28:34AM +0200, Andreas Färber wrote: > >> Am 12.10.2015 um 17:18 schrieb Tom Rini: > >>> If you have a regression, speak up. > >> > >> For -rc4 I had reported that CONFIG_API is broken for sunxi among > >> others. I was told this was fallout of the new Driver Model. Has anyone > >> thought about how to fix this? Is that already a lost cause for 2015.10? > >> > >> Improving test coverage for such off-by-default features will also be > >> helpful going forward. For instance, Simon's brand-new rk3288 code was > >> lacking some MMC define for CONFIG_API to build iirc - that part is > >> trivial to fix when actually build-testing. I'll see if I can polish > >> some of my fixes in time. > > > > I'm just not sure what to do about CONFIG_API some days. I know one use > > case is for GRUB but I'd like to move away from that if possible > > (distros should be doing the generic distro bits and extlinux.conf). > > After that, I'm only hazily aware of the real use-cases. > > The problem is that no other platform uses those. On x86_64, ppc64le, > s390x, aarch64, etc. we always use GRUB2. Whether it's boot.scr, > extlinux.conf or anything else, it'll require changes to distro tools > that end up being special-cased to 32-bit arm. With more and more server > vendors adopting UEFI and aarch64, that seems a waste of effort. That's a thing to ponder, yes. There's nothing ARM32 centric about the generic distro framework and it's on my TODO list now to poke Fedora about enabling the extlinux.conf knob on x86 because there's a growing number of platforms using U-Boot there. And hikey does (and Juno should/will) be doing it as well. > A boot.scr is easy to generate once for an installation image, and I see > Guillaume has been helping to make it usable where necessary, but as > long as that points to a single zImage / initrd / dtb (ext4 symlinks > pointing to the latest), after the user installs a new kernel package, > things might simply become unbootable for the average user. That's where > GRUB is handy in offering a selection of multiple kernels to go back to > a previously working state. I'm not particularly attached to CONFIG_API > myself - if the same can be achieved either in GRUB without CONFIG_API > or inside U-Boot with scripts and without GRUB, I'd be happy to hear > about it. :) Well, that roughly is the point of the whole config_distro_defaults / config_distro_bootcmd stuff is that the distro doesn't have to care what board it's on, it can just boot. > Regarding GRUB, I've mainly tested it on jetson-tk1 (adjusting grub's > hardcoded RAM offsets), and I've found it to load unreliably, as if > there's garbage in memory. Might be our 2.02~beta2 is missing some > backports. bootz works fine, so I guess bootm is not to blame there. > > Anyway, I think it's valid to say that we should either fix CONFIG_API > to build okay, or drop it completely, but not carry it around in > decaying state. ;) So as Wolfgang brought up, FreeBSD uses CONFIG_API so some care must be taken here, but we need to cover things a lot better than we do today. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Pull request: u-boot-arm/master
Hello, The following changes since commit 297faccca2235e359012118495b9b73451d54bb9: Merge branch 'master' of git://www.denx.de/git/u-boot-imx (2015-10-13 08:37:38 -0400) are available in the git repository at: git://git.denx.de/u-boot-arm master for you to fetch changes up to b1964c72bdb9ca44de3a56d40927409b8cab2a76: armv8/gic: Fix GIC v2 initialization (2015-10-15 14:47:03 +0200) These are all trivial changes or bugfixes. Albert ARIBAUD (1): Merge remote-tracking branch 'u-boot/master' Peng Fan (1): arm: armv8 correct value passed to __asm_dcache_all Simon Glass (1): arm: Correct comments in crt0.S for the recent SPL improvements Thierry Reding (3): armv8/mmu: Clean up TCR programming armv8/mmu: Set bits marked RES1 in TCR armv8/gic: Fix GIC v2 initialization arch/arm/cpu/armv8/cache.S | 2 +- arch/arm/cpu/armv8/cache_v8.c| 6 +++--- arch/arm/include/asm/armv8/mmu.h | 8 ++-- arch/arm/lib/crt0.S | 26 -- arch/arm/lib/crt0_64.S | 30 -- arch/arm/lib/gic_64.S| 10 +- 6 files changed, 55 insertions(+), 27 deletions(-) Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/3] gpt: add optional parameter guid in gpt command
On Tue, Oct 13, 2015 at 9:23 AM, Patrick Delaunay
wrote:
> code under flag CONFIG_PARTITION_TYPE_GUID
> add parameter guid to select partition type guid
>
> example of use with gpt command :
>
> partitions = uuid_disk=${uuid_gpt_disk};name=boot,start=0x4400,
> size=0x6bc00,uuid=${uuid_gpt_boot};name=root,start=0x7,
> size=0x7538ba00,uuid=${uuid_gpt_root},
> guid=0fc63daf-8483-4772-8e79-3d69d8477de4;
The mixture of UUID and GUID is confusing. What we want are the
GUIDs/UUIDs for unique ID and the partition type. I would just call
the partition type "type". This would allow the same format to be used
for MBR partitions if someone wanted to do support for that.
Rob
>
> gpt write mmc 0 $partitions
>
> Signed-off-by: Patrick Delaunay
> ---
>
> common/cmd_gpt.c | 17 +
> disk/part.c | 9 +
> disk/part_efi.c | 25 +
> include/part.h | 3 +++
> 4 files changed, 54 insertions(+)
>
> diff --git a/common/cmd_gpt.c b/common/cmd_gpt.c
> index c56fe15..1e8f927 100644
> --- a/common/cmd_gpt.c
> +++ b/common/cmd_gpt.c
> @@ -218,6 +218,23 @@ static int set_gpt_info(block_dev_desc_t *dev_desc,
> strcpy((char *)parts[i].uuid, p);
> free(val);
> }
> +#ifdef CONFIG_PARTITION_TYPE_GUID
> +/* guid */
> +val = extract_val(tok, "guid");
> +if (val) {
> +/* 'guid' is optional */
> +if (extract_env(val, &p))
> +p = val;
> +if (strlen(p) >= sizeof(parts[i].guid)) {
> +printf("Wrong guid format for partition %d\n",
> + i);
> +errno = -4;
> +goto err;
> +}
> +strcpy((char *)parts[i].guid, p);
> +free(val);
> +}
> +#endif
> /* name */
> val = extract_val(tok, "name");
> if (!val) { /* name is mandatory */
> diff --git a/disk/part.c b/disk/part.c
> index 43485c9..316454d 100644
> --- a/disk/part.c
> +++ b/disk/part.c
> @@ -391,6 +391,9 @@ int get_partition_info(block_dev_desc_t *dev_desc, int
> part,
> /* The common case is no UUID support */
> info->uuid[0] = 0;
> #endif
> +#ifdef CONFIG_PARTITION_TYPE_GUIDS
> +info->guid[0] = 0;
> +#endif
>
> switch (dev_desc->part_type) {
> #ifdef CONFIG_MAC_PARTITION
> @@ -526,6 +529,9 @@ int get_device_and_partition(const char *ifname, const
> char *dev_part_str,
> #ifdef CONFIG_PARTITION_UUIDS
> info->uuid[0] = 0;
> #endif
> +#ifdef CONFIG_PARTITION_TYPE_GUIDS
> +info->guid[0] = 0;
> +#endif
>
> return 0;
> }
> @@ -610,6 +616,9 @@ int get_device_and_partition(const char *ifname, const
> char *dev_part_str,
> #ifdef CONFIG_PARTITION_UUIDS
> info->uuid[0] = 0;
> #endif
> +#ifdef CONFIG_PARTITION_TYPE_GUIDS
> +info->guid[0] = 0;
> +#endif
>
> ret = 0;
> goto cleanup;
> diff --git a/disk/part_efi.c b/disk/part_efi.c
> index 15627f2..25bf8f9 100644
> --- a/disk/part_efi.c
> +++ b/disk/part_efi.c
> @@ -283,6 +283,10 @@ int get_partition_info_efi(block_dev_desc_t * dev_desc,
> int part,
> uuid_bin_to_str(gpt_pte[part - 1].unique_partition_guid.b, info->uuid,
> UUID_STR_FORMAT_GUID);
> #endif
> +#ifdef CONFIG_PARTITION_TYPE_GUID
> +uuid_bin_to_str(gpt_pte[part - 1].partition_type_guid.b, info->guid,
> +UUID_STR_FORMAT_GUID);
> +#endif
>
> debug("%s: start 0x" LBAF ", size 0x" LBAF ", name %s\n", __func__,
>info->start, info->size, info->name);
> @@ -419,6 +423,10 @@ int gpt_fill_pte(gpt_header *gpt_h, gpt_entry *gpt_e,
> char *str_uuid;
> unsigned char *bin_uuid;
> #endif
> +#ifdef CONFIG_PARTITION_TYPE_GUID
> +char *str_guid;
> +unsigned char *bin_guid;
> +#endif
>
> for (i = 0; i < parts; i++) {
> /* partition starting lba */
> @@ -445,9 +453,26 @@ int gpt_fill_pte(gpt_header *gpt_h, gpt_entry *gpt_e,
> else
> gpt_e[i].ending_lba = cpu_to_le64(offset - 1);
>
> +#ifdef CONFIG_PARTITION_TYPE_GUID
> +str_guid = partitions[i].guid;
> +bin_guid = gpt_e[i].partition_type_guid.b;
> +if (strlen(str_guid)) {
> +if (uuid_str_to_bin(str_guid, bin_guid,
> +UUID_STR_FORMAT_GUID)) {
> +printf("Partition no. %d: invalid type guid: %s\n",
> + i, str_guid);
> +return -1;
> +}
> +} else {
> +/* default partition type GUID */
> +memcpy(bin_guid,
> + &PARTITION_BASIC_DATA_GUID, 16);
> +}
> +#else
> /* partition type GUID */
> memcpy(gpt_e[i].partition_type_guid.b,
> &PARTITION_BASIC_DATA_GUID, 16);
> +#endif
>
> #ifdef CONFIG_PARTITION_UUIDS
> str_uuid = partitions[i].uuid;
> diff --git a/include/part.h b/include/part.h
> index 8ea9b30..d57d284 100644
> --- a/include/part.h
> +++ b/inc
Re: [U-Boot] [PATCH 2/3] gpt: add optional parameter guid in gpt command
On Thu, Oct 15, 2015 at 03:58:24PM -0500, Rob Herring wrote:
> On Tue, Oct 13, 2015 at 9:23 AM, Patrick Delaunay
> wrote:
> > code under flag CONFIG_PARTITION_TYPE_GUID
> > add parameter guid to select partition type guid
> >
> > example of use with gpt command :
> >
> > partitions = uuid_disk=${uuid_gpt_disk};name=boot,start=0x4400,
> > size=0x6bc00,uuid=${uuid_gpt_boot};name=root,start=0x7,
> > size=0x7538ba00,uuid=${uuid_gpt_root},
> > guid=0fc63daf-8483-4772-8e79-3d69d8477de4;
>
> The mixture of UUID and GUID is confusing. What we want are the
> GUIDs/UUIDs for unique ID and the partition type. I would just call
> the partition type "type". This would allow the same format to be used
> for MBR partitions if someone wanted to do support for that.
... and if someone wants to add MBR support, there's enough use cases
for it (mainly around flashing/factory stuff) that I wouldn't object.
So yes, lets do this with that kind of thing in mind.
--
Tom
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Re: [U-Boot] Relocation issue - need help!
On Thu, Oct 15, 2015 at 03:56:09PM +, Joakim Tjernlund wrote:
> On Tue, 2015-10-06 at 11:17 +, Joakim Tjernlund wrote:
> > On Thu, 2015-10-01 at 08:57 +, Joakim Tjernlund wrote:
> > > On Wed, 2015-09-30 at 21:35 +0200, Marek Vasut wrote:
> > > > On Wednesday, September 30, 2015 at 08:24:10 PM, Andy Fleming wrote:
> > > >
> > > > Hi!
> > > >
> > > > > On Thu, Oct 23, 2014 at 8:10 AM, Wolfgang Denk wrote:
> > > > > > Dear Joakim, dear Dirk,
> > > > > >
> > > > > > In message > > > c1257d7a.0024d...@transmode.se> you wrote:
> > > > > > > Ouch, that was a nasty surprise.
> > > > > >
> > > > > > Indeed.
> > > > > >
> > > > > > > > In my original mail I referenced this potential solution, at
> > > > > > > > least it
> > > > > > > > worked for me:
> > > > > > > > https://gcc.gnu.org/ml/gcc-help/2014-02/msg00054.html
> > > > > > >
> > > > > > > That looks like the correct fix but I presume both .data.rel.ro
> > > > > > > and
> > > > > > > data.rel.ro.local should be added?
> > > > > >
> > > > > > I can confirm:
> > > > > >
> > > > > > 1) The problem was observed with gcc 4.8.1 [as in Yocto 1.5.x / ELDK
> > > > > >
> > > > > >5.5.x].
> > > > > >
> > > > > > 2) Switching back to gcc 4.7.2 [as in Yocto 1.4 / ELDK 5.4] makes
> > > > > > the
> > > > > >
> > > > > >problem go away.
> > > > > >
> > > > > > 3) Switching forward to gcc 4.9.1 [as in Yocto 1.7 / ELDK 5.7] makes
> > > > > >
> > > > > >the problem go away.
> > > > > >
> > > > > > 4) For the problemativ 4.8.x versions of GCC, the following patch
> > > > > >
> > > > > >apparently solves the problem for my (MPC5200 based) board -
> > > > > > guess
> > > > > >this would have to be applied to all .lds files...
> > > > > >
> > > > > > diff --git a/arch/powerpc/cpu/mpc5xxx/u-boot.lds
> > > > > > b/arch/powerpc/cpu/mpc5xxx/u-boot.lds index cd9e23f..82c86d7 100644
> > > > > > --- a/arch/powerpc/cpu/mpc5xxx/u-boot.lds
> > > > > > +++ b/arch/powerpc/cpu/mpc5xxx/u-boot.lds
> > > > > > @@ -27,6 +27,8 @@ SECTIONS
> > > > > >
> > > > > >{
> > > > > >
> > > > > > _GOT2_TABLE_ = .;
> > > > > > KEEP(*(.got2))
> > > > > >
> > > > > > +KEEP(*(.data.rel.ro))
> > > > > > +KEEP(*(.data.rel.ro.local))
> > > > > >
> > > > > > KEEP(*(.got))
> > > > > > PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
> > > > > > _FIXUP_TABLE_ = .;
> > > > > >
> > > > > > Given that GCC 4.9.1 apparently solves this issue I wonder which
> > > > > > approach we should take?
> > > > > >
> > > > > > Should we blacklist GCC 4.8.x (and 4.9.0) like the kernel folks are
> > > > > > doing [1] ?
> > > > > >
> > > > > > [1] https://lkml.org/lkml/2014/10/10/272
> > > > >
> > > > > Was there a resolution to this thread? I just spent a bunch of time
> > > > > trying to figure out why u-boot was crashing, and eventually
> > > > > determined that switching from 4.9.0 to 4.6.3 solved the problem.
> > > > > Should I submit a patch to do what was suggested above? Or add the
> > > > > "blacklist" patch? If so, it should be noted that 4.9.0 is the current
> > > > > default installed when you ask buildman to install a powerpc cross
> > > > > compiler...
> > > >
> > > > Blacklist patch please, thank you!
> > >
> > > Yes, but all gcc 4.8.x versions?
> > >
> > > There is a fix here
> > > https://gcc.gnu.org/ml/gcc-patches/2014-04/msg01679.html
> > > but I don't know if it got committed or not or which version.
> > >
> > > I am using gcc 4.8.4 and it works but I have one problem, if I erase uboot
> > > after relocation, u-boot misbehavex or crashes so there is something off
> > > still.
> > >
> > > Does it work for all but me to erase u-boot after relocation?
> > > Using T1040(mpc85xx family)
> >
> > Here is a better URL:
> > http://patchwork.ozlabs.org/patch/342888/
> >
> > From what I can tell the above bug has been fixed in gcc 4.8.5(4.8.4 has
> > the error)
> > and 4.9.3 (by looking at varasm.c).
> >
> > Adding KEEP(*(.data.rel.ro.local)) i u-boot.lds does not seem to be the
> > correct fix as it is not an .fixup entry?
>
> After upgrading to gcc 4.9.3 I still see this bug(there is no .fixup entry)
> The bug can be avoided with -fno-ira-hoist-pressure and while you are it,
> throw in -mbss-plt to reduce size
Would something like this fix it then? Or at least work-around in-field
toolchains?
diff --git a/arch/powerpc/config.mk b/arch/powerpc/config.mk
index 83b49b5..2be5b46 100644
--- a/arch/powerpc/config.mk
+++ b/arch/powerpc/config.mk
@@ -13,7 +13,7 @@ CONFIG_STANDALONE_LOAD_ADDR ?= 0x4
LDFLAGS_FINAL += --gc-sections
LDFLAGS_FINAL += --bss-plt
PLATFORM_RELFLAGS += -fpic -mrelocatable -ffunction-sections \
--fdata-sections -mcall-linux
+-fdata-sections -mcall-linux $(call cc-option,-fno-ira-hoist-pressure,)
PLATFORM_CPPFLAGS += -D__powerpc__ -ffixed-r2 -m32
PLATFORM_LDFLAGS += -m32 -melf32ppclinux
--
Tom
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