Re: [U-Boot] [RFC PATCH 6/7] arm: Show relocated PC/LR in the register dump
Hello Simon, On Fri, 30 Jan 2015 12:04:56 -0700, Simon Glass wrote: > If we don't know the relocation address, the raw values are not very useful. > Show the pre-relocation values as well as these can be looked up in > System.map, etc. > > Signed-off-by: Simon Glass Acked-by: Albert ARIBAUD Simon, I think this one go straight into the ARM tree despite being an RFC patch in a series -- it's useful, pretty much standalone and it won't prevent any target from booting. Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/1] fix ARM DCC support for ARMv7 based cores (e.g. CortexA)
Hello Alexander, On Mon, 26 Jan 2015 14:13:16 +0100, Alexander Merkle wrote: > > arm_dcc.c supported ARMv4 (ARM7) to ARMv6 (ARM11) correctly. All recent > CortexA/ARMv7 based cores share the mrc/mcr coprocessor calls of ARMv6. > Due to the missing #ifdef the ARM7/ARMv4 calls are used as soon as > CONFIG_CPU_V7 is defined. This results in an undefined instruction exception. IIUC, the only board that uses ARM DCC serial is the Zynq, and it gets it to work by #define'ing CONFIG_CPU_V6 in its include config file despite being ARMv7. Am I right in assuming this #define was actually a hack to get around the issue you're fixing here, and that it can and should be removed from the Zinq include? If so, can you please post a v2 of your patch which does the removal too? (BTW, no need for a cover letter when there's only one patch in the "series" IMO) Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] edminiv2: drop CONFIG_CFI_LEGACY
Nowadays generic CFI code properly detects the ED Mini V2's
Macronix MC29LV400CB flash chip, therefore we can drop the
CONFIG_FLASH_CFI_LEGACY option and associated settings and code.
Signed-off-by: Albert ARIBAUD
---
board/LaCie/edminiv2/edminiv2.c | 50 -
include/configs/edminiv2.h | 4
2 files changed, 54 deletions(-)
diff --git a/board/LaCie/edminiv2/edminiv2.c b/board/LaCie/edminiv2/edminiv2.c
index 80ec7fa..690038e 100644
--- a/board/LaCie/edminiv2/edminiv2.c
+++ b/board/LaCie/edminiv2/edminiv2.c
@@ -15,56 +15,6 @@
DECLARE_GLOBAL_DATA_PTR;
-/*
- * The ED Mini V2 is equipped with a Macronix MXLV400CB FLASH
- * which CFI does not properly detect, hence the LEGACY config.
- */
-#if defined(CONFIG_FLASH_CFI_LEGACY)
-#include
-ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
-{
- int sectsz[] = CONFIG_SYS_FLASH_SECTSZ;
- int sect;
-
- if (base != CONFIG_SYS_FLASH_BASE)
- return 0;
-
- info->size = 0;
- info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- /* set each sector's start address and size based */
- for (sect = 0; sect < CONFIG_SYS_MAX_FLASH_SECT; sect++) {
- info->start[sect] = base+info->size;
- info->size += sectsz[sect];
- }
- /* This flash must be accessed in 8-bits mode, no buffer. */
- info->flash_id = 0x0100;
- info->portwidth = FLASH_CFI_8BIT;
- info->chipwidth = FLASH_CFI_BY8;
- info->buffer_size = 0;
- /* timings are derived from the Macronix datasheet. */
- info->erase_blk_tout = 1000;
- info->write_tout = 10;
- info->buffer_write_tout = 300;
- /* Commands and addresses are for AMD mode 8-bit access. */
- info->vendor = CFI_CMDSET_AMD_LEGACY;
- info->cmd_reset = 0xF0;
- info->interface = FLASH_CFI_X8;
- info->legacy_unlock = 0;
- info->ext_addr = 0;
- info->addr_unlock1 = 0x0aaa;
- info->addr_unlock2 = 0x0555;
- /* Manufacturer Macronix, device MX29LV400CB, CFI 1.3. */
- info->manufacturer_id = 0x22;
- info->device_id = 0xBA;
- info->device_id2 = 0;
- info->cfi_version = 0x3133;
- info->cfi_offset = 0x;
- info->name = "MX29LV400CB";
-
- return 1;
-}
-#endif /* CONFIG_SYS_FLASH_CFI */
-
int board_init(void)
{
/* arch number of board */
diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h
index 70a698a..f1e8cb0 100644
--- a/include/configs/edminiv2.h
+++ b/include/configs/edminiv2.h
@@ -89,13 +89,9 @@
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_FLASH_CFI_LEGACY
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */
#define CONFIG_SYS_FLASH_BASE 0xfff8
-#define CONFIG_SYS_FLASH_SECTSZ \
- {16384, 8192, 8192, 32768, \
-65536, 65536, 65536, 65536, 65536, 65536, 65536}
/* auto boot */
#define CONFIG_BOOTDELAY 3 /* default enable autoboot */
--
2.1.0
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[U-Boot] [PATCH v2] edminiv2: drop CONFIG_CFI_LEGACY
Nowadays generic CFI code properly detects the ED Mini V2's
Macronix MX29LV400CB flash chip, therefore we can drop the
CONFIG_FLASH_CFI_LEGACY option and associated settings and code.
Signed-off-by: Albert ARIBAUD
---
Changes in v2:
- Fix typo in flash part name (MC29LV400CB... -> MX29LV400CB)
- Add Kconfig settings
board/LaCie/edminiv2/edminiv2.c | 50 -
include/configs/edminiv2.h | 4
2 files changed, 54 deletions(-)
diff --git a/board/LaCie/edminiv2/edminiv2.c b/board/LaCie/edminiv2/edminiv2.c
index 80ec7fa..690038e 100644
--- a/board/LaCie/edminiv2/edminiv2.c
+++ b/board/LaCie/edminiv2/edminiv2.c
@@ -15,56 +15,6 @@
DECLARE_GLOBAL_DATA_PTR;
-/*
- * The ED Mini V2 is equipped with a Macronix MXLV400CB FLASH
- * which CFI does not properly detect, hence the LEGACY config.
- */
-#if defined(CONFIG_FLASH_CFI_LEGACY)
-#include
-ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
-{
- int sectsz[] = CONFIG_SYS_FLASH_SECTSZ;
- int sect;
-
- if (base != CONFIG_SYS_FLASH_BASE)
- return 0;
-
- info->size = 0;
- info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- /* set each sector's start address and size based */
- for (sect = 0; sect < CONFIG_SYS_MAX_FLASH_SECT; sect++) {
- info->start[sect] = base+info->size;
- info->size += sectsz[sect];
- }
- /* This flash must be accessed in 8-bits mode, no buffer. */
- info->flash_id = 0x0100;
- info->portwidth = FLASH_CFI_8BIT;
- info->chipwidth = FLASH_CFI_BY8;
- info->buffer_size = 0;
- /* timings are derived from the Macronix datasheet. */
- info->erase_blk_tout = 1000;
- info->write_tout = 10;
- info->buffer_write_tout = 300;
- /* Commands and addresses are for AMD mode 8-bit access. */
- info->vendor = CFI_CMDSET_AMD_LEGACY;
- info->cmd_reset = 0xF0;
- info->interface = FLASH_CFI_X8;
- info->legacy_unlock = 0;
- info->ext_addr = 0;
- info->addr_unlock1 = 0x0aaa;
- info->addr_unlock2 = 0x0555;
- /* Manufacturer Macronix, device MX29LV400CB, CFI 1.3. */
- info->manufacturer_id = 0x22;
- info->device_id = 0xBA;
- info->device_id2 = 0;
- info->cfi_version = 0x3133;
- info->cfi_offset = 0x;
- info->name = "MX29LV400CB";
-
- return 1;
-}
-#endif /* CONFIG_SYS_FLASH_CFI */
-
int board_init(void)
{
/* arch number of board */
diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h
index 70a698a..f1e8cb0 100644
--- a/include/configs/edminiv2.h
+++ b/include/configs/edminiv2.h
@@ -89,13 +89,9 @@
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_FLASH_CFI_LEGACY
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */
#define CONFIG_SYS_FLASH_BASE 0xfff8
-#define CONFIG_SYS_FLASH_SECTSZ \
- {16384, 8192, 8192, 32768, \
-65536, 65536, 65536, 65536, 65536, 65536, 65536}
/* auto boot */
#define CONFIG_BOOTDELAY 3 /* default enable autoboot */
--
2.1.0
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Re: [U-Boot] [PATCH 12/13] lcd: dt: extract simplefb support
Hi Simon, On 01/31/2015 02:25 AM, Simon Glass wrote: On 29 January 2015 at 04:21, Nikita Kiryanov wrote: We now have api functions that can support compiling simplefb code as its own module. Since this code is not part of the display functionality, extract it to its own file. Raspberry Pi config file is updated to compile the new file. Signed-off-by: Nikita Kiryanov Cc: Simon Glass Cc: Anatolij Gustschin Cc: Stephen Warren Reviewed-by: Simon Glass Could even go in fdtdec.c if you like. Hmm... I'm a little torn, but in the long term I think it's better to keep subsystem-specific fdt code in separate files, because otherwise fdtdec.c will eventually grow to enormous proportions. --- board/raspberrypi/rpi/rpi.c | 1 + common/Makefile | 1 + common/lcd.c| 50 -- common/lcd_simplefb.c | 59 + include/fdt_simplefb.h | 14 +++ include/lcd.h | 3 --- 6 files changed, 75 insertions(+), 53 deletions(-) create mode 100644 common/lcd_simplefb.c create mode 100644 include/fdt_simplefb.h -- Regards, Nikita Kiryanov ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 12/13] lcd: dt: extract simplefb support
Hi Stephen, On 01/29/2015 07:14 PM, Stephen Warren wrote: On 01/29/2015 04:21 AM, Nikita Kiryanov wrote: We now have api functions that can support compiling simplefb code as its own module. Since this code is not part of the display functionality, extract it to its own file. Raspberry Pi config file is updated to compile the new file. I don't see any config file updates. I think one isn't needed, since the config file must already have CONFIG_LCD_DT_SIMPLEFB enabled, since the existing code is under that ifdef. Yes that was a poor choice of words on my part. Should have been something like "...is updated to accommodate the changes". I'll fix it in a V2. Acked-by: Stephen Warren -- Regards, Nikita Kiryanov ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 13/13] lcd: split splash code into its own function
Hi Simon,
On 01/31/2015 02:25 AM, Simon Glass wrote:
Hi Nikita,
On 29 January 2015 at 04:21, Nikita Kiryanov wrote:
lcd_logo() currently performs tasks well beyond just displaying the logo.
It has code which displays splash image, it has logic which determines
when the different display features are displayed, and it is coupled with
the lcd console because it holds the responsibility of returning the
lcd console base address.
Make lcd_logo() just about the logo by:
* Moving splash image display code into a dedicated function
* Moving the logic regarding when various features are displayed to
lcd_clear() (which is arguably not the correct name for housing such
code either, but it is currently the most fitting location code wise)
* Move the responsibility of setting the console base address to
lcd_clear() too.
Signed-off-by: Nikita Kiryanov
Cc: Bo Shen
Cc: Simon Glass
Cc: Anatolij Gustschin
---
common/lcd.c | 52 ++--
common/splash.c | 16
include/splash.h | 11 ++-
3 files changed, 48 insertions(+), 31 deletions(-)
diff --git a/common/lcd.c b/common/lcd.c
index d0c0aff..f33942c 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -46,7 +46,7 @@
DECLARE_GLOBAL_DATA_PTR;
static int lcd_init(void *lcdbase);
-static void *lcd_logo(void);
+static void lcd_logo(void);
static void lcd_setfgcolor(int color);
static void lcd_setbgcolor(int color);
@@ -169,6 +169,9 @@ void lcd_clear(void)
{
short console_rows, console_cols;
int bg_color;
+ char *s;
+ ulong addr;
+ static int do_splash = 1;
#if LCD_BPP == LCD_COLOR8
/* Setting the palette */
lcd_setcolreg(CONSOLE_COLOR_BLACK, 0, 0, 0);
@@ -218,7 +221,23 @@ void lcd_clear(void)
#endif
console_cols = panel_info.vl_col / VIDEO_FONT_WIDTH;
lcd_init_console(lcd_base, console_rows, console_cols);
- lcd_init_console(lcd_logo(), console_rows, console_cols);
+ if (do_splash) {
+ s = getenv("splashimage");
+ if (s) {
+ do_splash = 0;
+ addr = simple_strtoul(s, NULL, 16);
+ if (lcd_splash(addr) == 0) {
+ lcd_sync();
+ return;
+ }
+ }
+ }
+
+ lcd_logo();
+#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO)
+ addr = (ulong)lcd_base + BMP_LOGO_HEIGHT * lcd_line_length;
+ lcd_init_console((void *)addr, console_rows, console_cols);
I'm just a bit unsure about this - before this function was always
called. I have some idea but can you explain why it is now in an
#ifidef?
The only time when the base address of the console is defined as anything other
than lcd_base, is when we get to the very end of the original lcd_logo() and
the above #defines apply. In all other cases, the address of lcd_base is used,
and that is set as default at the start of lcd_clear().
--
Regards,
Nikita Kiryanov
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Re: [U-Boot] [PATCH 2/4] usb: add 'bcm_udc_otg' support
On Sat, 31 Jan 2015 15:15:24 +0100 Marek Vasut wrote: > On Saturday, January 31, 2015 at 02:26:16 PM, Lukasz Majewski wrote: > > On Fri, 30 Jan 2015 23:16:57 +0100 > > > > Marek Vasut wrote: > > > On Monday, January 26, 2015 at 01:31:39 PM, Lukasz Majewski wrote: > > > > Hi Marek, > > > > > > > > > On Monday, January 26, 2015 at 09:38:28 AM, Lukasz Majewski > > > > > wrote: > > > > > > Hi Marek, > > > > > > > > > > Hi! > > > > > > > > > > [...] > > > > > > > > > > > > No, unless there's a convincing technical argument that > > > > > > > the currently mainline DWC2 gadget driver (the s3c one) > > > > > > > can absolutelly not be used for the broadcom SoC, I want > > > > > > > to avoid having two drivers for the same IP core in > > > > > > > mainline, sorry. > > > > > > > > > > > > Maybe it is a highest time to think about renaming s3c_* to > > > > > > dwc2_* and avoid further confusion. > > > > > > > > > > The time was ripe for a while now ;-) Do you want to do it or > > > > > shall I send a patch ? > > > > > > > > I do know that I will test it :-), so feel free to send the > > > > patch. > > > > > > Hi! > > > > > > I'm dead busy until end of next week. Do you mind cooking such > > > patch please? > > > > I will try to find some time slack to prepare patch. > > Thanks! Shall I pick it then ? For technical (testing) point of view it would be better for me to place it -dfu tree, and then send a PR to you. Best regards, LUkasz Majewski > > Best regards, > Marek Vasut pgpGQTi43YQwK.pgp Description: OpenPGP digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 02/21] common/lcd: Add command for setting cursor within lcd-framework
Hi Hannes,
On 01/30/2015 03:25 PM, Hannes Petermaier wrote:
We need this function if we want to make some outputs i.e position the writing
cursor out of u-boot scripts.
This commit message is inaccurate. Positioning the writing cursor is not in
itself output.
Also, what is the use case for such a command?
Signed-off-by: Hannes Petermaier
---
common/lcd.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/common/lcd.c b/common/lcd.c
index cc34b8a..f418da9 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -279,12 +279,33 @@ static int do_lcd_clear(cmd_tbl_t *cmdtp, int flag, int
argc,
return 0;
}
+static int do_lcd_setcursor(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ unsigned int col, row;
+
+ if (argc != 3)
+ return CMD_RET_USAGE;
+
+ col = simple_strtoul(argv[1], NULL, 10);
+ row = simple_strtoul(argv[2], NULL, 10);
+ lcd_position_cursor(col, row);
+
+ return 0;
+}
+
U_BOOT_CMD(
cls,1, 1, do_lcd_clear,
"clear screen",
""
);
+U_BOOT_CMD(
+ setcurs, 3, 1, do_lcd_setcursor,
+ "sets cursor for 'puts'",
+ " in character"
+);
+
I think it would be better if the U_BOOT_CMD macros were adjacent to the
functions they
use. Also, I think this command is better suited for the lcd_console.c file.
/*--*/
static int lcd_init(void *lcdbase)
--
Regards,
Nikita Kiryanov
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Re: [U-Boot] [PATCH 03/21] common/lcd: Add command for writing to lcd-display
Hi Hannes,
On 01/30/2015 03:25 PM, Hannes Petermaier wrote:
We need this function if we want to make some outputs out of u-boot scripts.
I think this commit message is missing information. What makes this necessary?
Why can't your script use regular echo commands with the lcd console enabled?
Signed-off-by: Hannes Petermaier
---
common/lcd.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/common/lcd.c b/common/lcd.c
index f418da9..755388f 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -279,6 +279,17 @@ static int do_lcd_clear(cmd_tbl_t *cmdtp, int flag, int
argc,
return 0;
}
+static int do_lcd_puts(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ if (argc != 2)
+ return CMD_RET_USAGE;
+
+ lcd_puts(argv[1]);
+
+ return 0;
+}
+
static int do_lcd_setcursor(cmd_tbl_t *cmdtp, int flag, int argc,
char *const argv[])
{
@@ -306,6 +317,12 @@ U_BOOT_CMD(
" in character"
);
+U_BOOT_CMD(
+ puts, 2, 1, do_lcd_puts,
"puts" is too generic for an lcd specific function. I would expect to see
something
with an "lcd" prefix. Also, this code seems better suited for lcd_console.c
+ "print string on lcd-framebuffer",
+ ""
+);
+
/*--*/
static int lcd_init(void *lcdbase)
--
Regards,
Nikita Kiryanov
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Re: [U-Boot] [PATCH 2/4] usb: add 'bcm_udc_otg' support
On Sunday, February 01, 2015 at 02:15:45 PM, Lukasz Majewski wrote: > On Sat, 31 Jan 2015 15:15:24 +0100 > > Marek Vasut wrote: > > On Saturday, January 31, 2015 at 02:26:16 PM, Lukasz Majewski wrote: > > > On Fri, 30 Jan 2015 23:16:57 +0100 > > > > > > Marek Vasut wrote: > > > > On Monday, January 26, 2015 at 01:31:39 PM, Lukasz Majewski wrote: > > > > > Hi Marek, > > > > > > > > > > > On Monday, January 26, 2015 at 09:38:28 AM, Lukasz Majewski > > > > > > > > > > > > wrote: > > > > > > > Hi Marek, > > > > > > > > > > > > Hi! > > > > > > > > > > > > [...] > > > > > > > > > > > > > > No, unless there's a convincing technical argument that > > > > > > > > the currently mainline DWC2 gadget driver (the s3c one) > > > > > > > > can absolutelly not be used for the broadcom SoC, I want > > > > > > > > to avoid having two drivers for the same IP core in > > > > > > > > mainline, sorry. > > > > > > > > > > > > > > Maybe it is a highest time to think about renaming s3c_* to > > > > > > > dwc2_* and avoid further confusion. > > > > > > > > > > > > The time was ripe for a while now ;-) Do you want to do it or > > > > > > shall I send a patch ? > > > > > > > > > > I do know that I will test it :-), so feel free to send the > > > > > patch. > > > > > > > > Hi! > > > > > > > > I'm dead busy until end of next week. Do you mind cooking such > > > > patch please? > > > > > > I will try to find some time slack to prepare patch. > > > > Thanks! Shall I pick it then ? > > For technical (testing) point of view it would be better for me to > place it -dfu tree, and then send a PR to you. Roger :) Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 13/13] lcd: split splash code into its own function
Hi NIkita,
On 1 February 2015 at 06:59, Nikita Kiryanov wrote:
> Hi Simon,
>
>
> On 01/31/2015 02:25 AM, Simon Glass wrote:
>>
>> Hi Nikita,
>>
>> On 29 January 2015 at 04:21, Nikita Kiryanov
>> wrote:
>>>
>>> lcd_logo() currently performs tasks well beyond just displaying the logo.
>>> It has code which displays splash image, it has logic which determines
>>> when the different display features are displayed, and it is coupled with
>>> the lcd console because it holds the responsibility of returning the
>>> lcd console base address.
>>>
>>> Make lcd_logo() just about the logo by:
>>> * Moving splash image display code into a dedicated function
>>> * Moving the logic regarding when various features are displayed to
>>>lcd_clear() (which is arguably not the correct name for housing such
>>>code either, but it is currently the most fitting location code wise)
>>> * Move the responsibility of setting the console base address to
>>>lcd_clear() too.
>>>
>>> Signed-off-by: Nikita Kiryanov
>>> Cc: Bo Shen
>>> Cc: Simon Glass
>>> Cc: Anatolij Gustschin
>>> ---
>>> common/lcd.c | 52
>>> ++--
>>> common/splash.c | 16
>>> include/splash.h | 11 ++-
>>> 3 files changed, 48 insertions(+), 31 deletions(-)
>>>
>>> diff --git a/common/lcd.c b/common/lcd.c
>>> index d0c0aff..f33942c 100644
>>> --- a/common/lcd.c
>>> +++ b/common/lcd.c
>>> @@ -46,7 +46,7 @@
>>> DECLARE_GLOBAL_DATA_PTR;
>>>
>>> static int lcd_init(void *lcdbase);
>>> -static void *lcd_logo(void);
>>> +static void lcd_logo(void);
>>> static void lcd_setfgcolor(int color);
>>> static void lcd_setbgcolor(int color);
>>>
>>> @@ -169,6 +169,9 @@ void lcd_clear(void)
>>> {
>>> short console_rows, console_cols;
>>> int bg_color;
>>> + char *s;
>>> + ulong addr;
>>> + static int do_splash = 1;
>>> #if LCD_BPP == LCD_COLOR8
>>> /* Setting the palette */
>>> lcd_setcolreg(CONSOLE_COLOR_BLACK, 0, 0, 0);
>>> @@ -218,7 +221,23 @@ void lcd_clear(void)
>>> #endif
>>> console_cols = panel_info.vl_col / VIDEO_FONT_WIDTH;
>>> lcd_init_console(lcd_base, console_rows, console_cols);
>>> - lcd_init_console(lcd_logo(), console_rows, console_cols);
>>> + if (do_splash) {
>>> + s = getenv("splashimage");
>>> + if (s) {
>>> + do_splash = 0;
>>> + addr = simple_strtoul(s, NULL, 16);
>>> + if (lcd_splash(addr) == 0) {
>>> + lcd_sync();
>>> + return;
>>> + }
>>> + }
>>> + }
>>> +
>>> + lcd_logo();
>>> +#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO)
>>> + addr = (ulong)lcd_base + BMP_LOGO_HEIGHT * lcd_line_length;
>>> + lcd_init_console((void *)addr, console_rows, console_cols);
>>
>>
>> I'm just a bit unsure about this - before this function was always
>> called. I have some idea but can you explain why it is now in an
>> #ifidef?
>
>
> The only time when the base address of the console is defined as anything
> other
> than lcd_base, is when we get to the very end of the original lcd_logo() and
> the above #defines apply. In all other cases, the address of lcd_base is
> used,
> and that is set as default at the start of lcd_clear().
OK I see, thanks.
Reviewed-by: Simon Glass
Regards,
Simon
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Re: [U-Boot] [RFC PATCH v2 1/6] x86: Add header files for Intel Quark SoC defines
Hi Bin, On 29 January 2015 at 02:18, Bin Meng wrote: > device.h for integrated pci devices' bdf on Quark SoC and quark.h for > various memory-mapped and i/o-mapped base addresses within SoC. > > Signed-off-by: Bin Meng > > --- > > Changes in v2: > - Move vairous components' base addresses within Quark SoC to Kconfig > > arch/x86/include/asm/arch-quark/device.h | 28 > arch/x86/include/asm/arch-quark/quark.h | 27 +++ > 2 files changed, 55 insertions(+) > create mode 100644 arch/x86/include/asm/arch-quark/device.h > create mode 100644 arch/x86/include/asm/arch-quark/quark.h Acked-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/4] sunxi: Make FEL mode usable again
Hi,
On 30 January 2015 at 04:58, Siarhei Siamashka
wrote:
> The commit f630974ccb3ce93e9607a3354e9acb266a8b7e95
> 'sunxi: Move SPL s_init() code to board_init_f()'
> broke the FEL boot mode.
>
> This patch moves the DRAM initialization back to s_init() and
> introduces an assembly entry point for FEL in order to provide
> guaranteed initialization of the gdata pointer (r9). The assembly
> entry point is also needed to ensure that the SPL code starts
> executing in ARM mode.
>
> Because the sunxi board_init_f() does not contain anything that
> is not already done by the default board_init_f(), it is removed
> too.
>
> Signed-off-by: Siarhei Siamashka
> ---
> arch/arm/cpu/armv7/sunxi/Makefile | 1 +
> arch/arm/cpu/armv7/sunxi/board.c| 26 ++
> arch/arm/cpu/armv7/sunxi/start_fel.S| 16
> arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds | 3 ++-
> 4 files changed, 29 insertions(+), 17 deletions(-)
> create mode 100644 arch/arm/cpu/armv7/sunxi/start_fel.S
>
> diff --git a/arch/arm/cpu/armv7/sunxi/Makefile
> b/arch/arm/cpu/armv7/sunxi/Makefile
> index 48db744..e0d413d 100644
> --- a/arch/arm/cpu/armv7/sunxi/Makefile
> +++ b/arch/arm/cpu/armv7/sunxi/Makefile
> @@ -40,5 +40,6 @@ obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o
> obj-$(CONFIG_MACH_SUN8I) += dram_sun8i.o
> ifdef CONFIG_SPL_FEL
> obj-y += start.o
> +extra-y+= start_fel.o
> endif
> endif
> diff --git a/arch/arm/cpu/armv7/sunxi/board.c
> b/arch/arm/cpu/armv7/sunxi/board.c
> index 6e28bcd..ea6cb60 100644
> --- a/arch/arm/cpu/armv7/sunxi/board.c
> +++ b/arch/arm/cpu/armv7/sunxi/board.c
> @@ -85,6 +85,16 @@ void s_init(void)
> timer_init();
> gpio_init();
> i2c_init_board();
> +
> +#ifdef CONFIG_SPL_BUILD
> + preloader_console_init();
s_init() is called before we have global_data, so you can't use a console.
> +
> +#ifdef CONFIG_SPL_I2C_SUPPORT
> + /* Needed early by sunxi_board_init if PMU is enabled */
> + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
> +#endif
> + sunxi_board_init();
> +#endif
Why do you need this code here? Can it not go in board_init_f()?
> }
>
> #ifdef CONFIG_SPL_BUILD
> @@ -103,22 +113,6 @@ u32 spl_boot_mode(void)
> {
> return MMCSD_MODE_RAW;
> }
> -
> -void board_init_f(ulong dummy)
> -{
> - preloader_console_init();
> -
> -#ifdef CONFIG_SPL_I2C_SUPPORT
> - /* Needed early by sunxi_board_init if PMU is enabled */
> - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
> -#endif
> - sunxi_board_init();
> -
> - /* Clear the BSS. */
> - memset(__bss_start, 0, __bss_end - __bss_start);
> -
> - board_init_r(NULL, 0);
> -}
> #endif
>
> void reset_cpu(ulong addr)
> diff --git a/arch/arm/cpu/armv7/sunxi/start_fel.S
> b/arch/arm/cpu/armv7/sunxi/start_fel.S
> new file mode 100644
> index 000..e1c7cd4
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/sunxi/start_fel.S
> @@ -0,0 +1,16 @@
> +/*
> + * Entry point of the FEL mode SPL.
> + *
> + * Copyright (c) 2015 Siarhei Siamashka
> + *
> + * SPDX-License-Identifier:GPL-2.0+
> + */
> +
> +#include
> +#include
> +#include
> +
> +ENTRY(_start_fel)
> + ldr r9, =gdata
> + b s_init
No we don't want global data here, and need to get rid of gdata so we
can use driver model, etc.
> +ENDPROC(_start_fel)
> diff --git a/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds
> b/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds
> index 928b7c1..beb8900 100644
> --- a/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds
> +++ b/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds
> @@ -6,7 +6,7 @@
> */
> OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
> OUTPUT_ARCH(arm)
> -ENTRY(s_init)
> +ENTRY(_start_fel)
> SECTIONS
> {
> . = 0x2000;
> @@ -14,6 +14,7 @@ SECTIONS
> . = ALIGN(4);
> .text :
> {
> + arch/arm/cpu/armv7/sunxi/start_fel.o(.text)
> *(.text.s_init)
Why does this have to jump to a special s_init? Can it not just start
SPL normally as it does on Tegra, Exynos, etc?
> *(.text*)
> }
There has to be a better way of making this work. Also do you have
instructions on how I can try this out on a pcduino3 or other low-cost
board?
I understand that we need to fix this, but other archs deal with this
within the existing framework, so I'd really like to get sunxi into
the same state.
Regards,
Simon
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Re: [U-Boot] [RFC PATCH v2 3/6] x86: quark: Add Cache-As-RAM initialization
Hi Bin, On 29 January 2015 at 02:18, Bin Meng wrote: > Quark SoC contains an embedded 512KiB SRAM (eSRAM) that is > initialized by hardware. eSRAM is the ideal place to be used > for Cache-As-RAM (CAR) before system memory is available. > > Signed-off-by: Bin Meng > > --- > > Changes in v2: > - Replace upper case register names (EAX etc.) with lower case > - Use some macros from and > > arch/x86/cpu/quark/car.S | 104 > +++ > 1 file changed, 104 insertions(+) > create mode 100644 arch/x86/cpu/quark/car.S > > diff --git a/arch/x86/cpu/quark/car.S b/arch/x86/cpu/quark/car.S > new file mode 100644 > index 000..f32f9b1 > --- /dev/null > +++ b/arch/x86/cpu/quark/car.S > @@ -0,0 +1,104 @@ > +/* > + * Copyright (C) 2015, Bin Meng > + * > + * SPDX-License-Identifier:GPL-2.0+ > + */ > + > +#include > +#include > +#include > +#include > + > +.globl car_init > +car_init: > + post_code(POST_CAR_START) > + > + /* > +* Quark SoC contains an embedded 512KiB SRAM (eSRAM) that is > +* initialized by hardware. eSRAM is the ideal place to be used > +* for Cache-As-RAM (CAR) before system memory is available. > +* > +* Relocate this eSRAM to a suitable location in the physical > +* memory map and enable it. > +*/ > + > + /* Host Memory Bound Register P03h:R08h */ > + mov $((0x03 << 16) | (0x08 << 8)), %eax Do you have #defines for these to? > + mov $(DRAM_BASE + DRAM_MAX_SIZE + ESRAM_SIZE), %edx > + lea 1f, %esp > + jmp msg_port_write > +1: > + > + /* eSRAM Block Page Control Register P05h:R82h */ > + mov $((0x05 << 16) | (0x82 << 8)), %eax > + mov $(ESRAM_BLOCK_MODE | (CONFIG_ESRAM_BASE >> 24)), %edx > + lea 2f, %esp > + jmp msg_port_write > +2: > + > + post_code(POST_CAR_CPU_CACHE) > + jmp car_init_ret > + > +msg_port_read: > + /* > +* Parameter: > +* eax[23:16] - Message Port ID > +* eax[15:08] - Register Address > +* > +* Return Value: > +* eax - Message Port Register value > +* > +* Return Address: esp > +*/ > + > + or $((MSG_OP_READ << 24) | MSG_BYTE_ENABLE), %eax > + mov %eax, %ebx > + > + /* Write MCR B0:D0:F0:RD0 */ > + mov $((1 << 31) | MSG_CTRL_REG), %eax And this 1 << 31 ? > + mov $0xcf8, %dx > + out %eax, %dx > + mov $0xcfc, %dx > + mov %ebx, %eax > + out %eax, %dx > + > + /* Read MDR B0:D0:F0:RD4 */ > + mov $((1 << 31) | MSG_DATA_REG), %eax > + mov $0xcf8, %dx > + out %eax, %dx > + mov $0xcfc, %dx > + in %dx, %eax > + > + jmp *%esp > + > +msg_port_write: > + /* > +* Parameter: > +* eax[23:16] - Message Port ID > +* eax[15:08] - Register Address > +* edx- Message Port Register value to write > +* > +* Return Address: esp > +*/ > + > + or $((MSG_OP_WRITE << 24) | MSG_BYTE_ENABLE), %eax > + mov %eax, %esi > + mov %edx, %edi > + > + /* Write MDR B0:D0:F0:RD4 */ > + mov $((1 << 31) | MSG_DATA_REG), %eax > + mov $0xcf8, %dx > + out %eax, %dx > + mov $0xcfc, %dx > + mov %edi, %eax > + out %eax, %dx > + > + /* Write MCR B0:D0:F0:RD0 */ > + mov $((1 << 31) | MSG_CTRL_REG), %eax > + mov $0xcf8, %dx > + out %eax, %dx > + mov $0xcfc, %dx > + mov %esi, %eax > + out %eax, %dx > + > + jmp *%esp > -- > 1.8.2.1 > Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC PATCH v2 2/6] x86: quark: Add routines to access message bus registers
On 29 January 2015 at 02:18, Bin Meng wrote: > In the Quark SoC, some chipset commands are accomplished by utilizing > the internal message network within the host bridge (D0:F0). Accesses > to this network are accomplished by populating the message control > register (MCR), Message Control Register eXtension (MCRX) and the > message data register (MDR). > > Signed-off-by: Bin Meng > > --- > > Changes in v2: > - Add msg_port_setup() and remove MCR_FILL > - Add MSG_BYTE_ENABLE define > - Wrap function declaraion with __ASSEMBLY__ > > arch/x86/cpu/quark/msg_port.c | 77 + > arch/x86/include/asm/arch-quark/msg_port.h | 106 > + > 2 files changed, 183 insertions(+) > create mode 100644 arch/x86/cpu/quark/msg_port.c > create mode 100644 arch/x86/include/asm/arch-quark/msg_port.h > Acked-by: Simon Glass I'd still prefer lower case hex. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/9] sunxi: Move SPL s_init() code to board_init_f()
Hi,
On 30 January 2015 at 10:53, Siarhei Siamashka
wrote:
> On Mon, 29 Dec 2014 09:15:36 -0700
> Simon Glass wrote:
>
>> Hi Ian,
>>
>> On 28 December 2014 at 02:19, Ian Campbell wrote:
>> > On Tue, 2014-12-23 at 12:04 -0700, Simon Glass wrote:
>> >
>> >> +void board_init_f(ulong dummy)
>> >> +{
>> > [...]
>> >> + /* Clear the BSS. */
>> >> + memset(__bss_start, 0, __bss_end - __bss_start);
>> >> +
>> >> + board_init_r(NULL, 0);
>> >
>> > The previous (__weak) version of board_init_f also sets gd, which you've
>> > also removed from s_init here and not added back anywhere (indeed, this
>> > is the point...). But where is gd initialised now?
>>
>> It's still in start.S, I've just removed this duplicate.
>>
>> >
>> > The patch generally looks good, two quick questions: has it been tested
>> > in both FEL and regular mode, and has it been tested with a "legacy" as
>> > well as a driver model system? (I might be able to find time in a day or
>> > two to answer these myself, but for now I'll just ask).
>>
>> I haven't tried FEL, I only just heard of it in your email. I'll see
>> if I can figure out how to test that.
>
> Just like Ian suspected, this patch has messed up the FEL boot mode
> support.
>
> In a nutshell, FEL is a special USB protocol (accessible on a USB OTG
> connector), which is implemented by the boot ROM and activated by
> holding a special hardware button pressed and rebooting the device.
> FEL supports commands to read/write device RAM and execute code on
> the device. It is designed for device unbricking and firmware recovery.
If I understand it correctly, this is the same function that is
available on Exynos5, Tegra, MX6 and probably others.
>
> In particular, the FEL boot mode support is very useful for debugging
> u-boot and kernel problems on tablets (the SD card slot can be used
> for the UART console, while the system is booted over a micro-USB cable
> with the help of FEL):
> http://linux-sunxi.org/File:MSI_Primo81_and_MicroSD_breakout.jpg
>
> In u-boot it is used in the following way:
> 1. The SPL code is uploaded from the linux PC to the device SRAM via
> a FEL command (using the 'fel' program from sunxi-tools).
> 2. The SPL code is executed via a FEL command and expected to
> initialize the DRAM controller. The code is executed as a
> normal C or assembly function, which needs to return control
> back to the BROM code when it is done. Right now this
> function is s_init().
Isn't this just another way of loading SPL then? What is so special /
different about FEL?
> 3. As the DRAM is initialized and available now, the main u-boot
> binary is now uploaded to DRAM via FEL. Together with boot.scr,
> the kernel, the dtb file and optionally initramfs as needed.
> 4. The main u-boot binary is executed via a FEL command, but never
> returns back to BROM anymore.
>
> More details are available in the linux-sunxi wiki:
> http://linux-sunxi.org/FEL
> http://linux-sunxi.org/FEL/Protocol
> http://linux-sunxi.org/FEL/USBBoot
>
> I have submitted a patch to fix this regression:
> https://patchwork.ozlabs.org/patch/434826/
>
> If you encounter problems and/or need help when testing FEL, please
> let me know.
OK I commented on that patch.
Regards,
Simon
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Re: [U-Boot] [RFC PATCH v2 5/6] x86: Add basic Intel Galileo board support
On 29 January 2015 at 02:18, Bin Meng wrote: > New board/intel/galileo board directory with minimum codes, plus > board dts, defconfig and configuration files. > > Signed-off-by: Bin Meng > Reviewed-by: Simon Glass > --- > > Changes in v2: None > > arch/x86/dts/Makefile | 1 + > arch/x86/dts/galileo.dts| 43 + > board/intel/galileo/Kconfig | 21 > board/intel/galileo/MAINTAINERS | 6 + > board/intel/galileo/Makefile| 7 ++ > board/intel/galileo/galileo.c | 19 +++ > board/intel/galileo/start.S | 9 +++ > configs/galileo_defconfig | 6 + > include/configs/galileo.h | 53 > + > 9 files changed, 165 insertions(+) > create mode 100644 arch/x86/dts/galileo.dts > create mode 100644 board/intel/galileo/Kconfig > create mode 100644 board/intel/galileo/MAINTAINERS > create mode 100644 board/intel/galileo/Makefile > create mode 100644 board/intel/galileo/galileo.c > create mode 100644 board/intel/galileo/start.S > create mode 100644 configs/galileo_defconfig > create mode 100644 include/configs/galileo.h > Acked-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC PATCH v2 6/6] x86: Enable the Intel quark/galileo build
On 29 January 2015 at 02:18, Bin Meng wrote: > Make the Intel quark/galileo support avaiable in Kconfig and Makefile. > With this patch, we can generate u-boot.rom for Intel galileo board. > > Signed-off-by: Bin Meng > Reviewed-by: Simon Glass > > --- > > Changes in v2: > - Use Arduino-certified > > arch/x86/Kconfig | 17 + > arch/x86/cpu/Makefile | 1 + > 2 files changed, 18 insertions(+) Acked-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC PATCH v2 4/6] x86: Add basic Intel Quark processor support
Hi Bin, On 29 January 2015 at 02:18, Bin Meng wrote: > Add minimum codes to support Intel Quark SoC. DRAM initialization > is not ready yet so a hardcoded gd->ram_size is assigned. > > Signed-off-by: Bin Meng > > --- > > Changes in v2: > - Use machine-specific > - Move vairous components' base addresses within Quark SoC to Kconfig > - Rebase to u-boot-86/master > All looks OK but for a few nits. > arch/x86/cpu/quark/Kconfig | 118 > + > arch/x86/cpu/quark/Makefile| 8 +++ > arch/x86/cpu/quark/dram.c | 39 +++ > arch/x86/cpu/quark/pci.c | 70 +++ > arch/x86/cpu/quark/quark.c | 44 > arch/x86/include/asm/arch-quark/gpio.h | 13 > 6 files changed, 292 insertions(+) > create mode 100644 arch/x86/cpu/quark/Kconfig > create mode 100644 arch/x86/cpu/quark/Makefile > create mode 100644 arch/x86/cpu/quark/dram.c > create mode 100644 arch/x86/cpu/quark/pci.c > create mode 100644 arch/x86/cpu/quark/quark.c > create mode 100644 arch/x86/include/asm/arch-quark/gpio.h > > diff --git a/arch/x86/cpu/quark/Kconfig b/arch/x86/cpu/quark/Kconfig > new file mode 100644 > index 000..8bccf09 > --- /dev/null > +++ b/arch/x86/cpu/quark/Kconfig > @@ -0,0 +1,118 @@ > +# > +# Copyright (C) 2015, Bin Meng > +# > +# SPDX-License-Identifier: GPL-2.0+ > +# > + > +config INTEL_QUARK > + bool > + select HAVE_RMU > + > +if INTEL_QUARK > + > +config HAVE_RMU > + bool "Add a Remote Management Unit (RMU) binary" > + help > + Select this option to add a Remote Management Unit (RMU) binary > + to the resulting U-Boot image. It is a data block (up to 64K) of > + machine-specific code which must be put in the flash for the RMU > + within the Quark SoC processor to access when powered up before > + system BIOS is executed. > + > +config RMU_FILE > + string "Remote Management Unit (RMU) binary filename" > + depends on HAVE_RMU > + default "rmu.bin" > + help > + The filename of the file to use as Remote Management Unit (RMU) > + binary in the board directory. > + > +config RMU_ADDR > + hex "Remote Management Unit (RMU) binary location" > + depends on HAVE_RMU > + default 0xfff0 > + help > + The location of the RMU binary is determined by a strap. It must be > + put in flash at a location matching the strap-determined base > address. > + > + The default base address of 0xfff0 indicates that the binary > must > + be located at offset 0 from the beginning of a 1MB flash device. > + > +config HAVE_CMC > + bool > + default HAVE_RMU > + > +config CMC_FILE > + string > + depends on HAVE_CMC > + default RMU_FILE > + > +config CMC_ADDR > + hex > + depends on HAVE_CMC > + default RMU_ADDR > + > +config ESRAM_BASE > + hex > + default 0x8000 > + help > + Embedded SRAM (eSRAM) memory-mapped base address. > + > +config PCIE_ECAM_BASE > + hex > + default 0xe000 > + > +config RCBA_BASE > + hex > + default 0xfed1c000 > + help > + Root Complex register block memory-mapped base address. > + > +config ACPI_PM1_BASE > + hex > + default 0x1000 > + help > + ACPI PM1 i/o-mapped base address. What is PM1? > + > +config ACPI_P_BASE > + hex > + default 0x1010 > + help > + ACPI PBLK i/o-mapped base address. What is PBLK? > + > +config SPI_DMA_BASE > + hex > + default 0x1020 > + help > + SPI DMA i/o-mapped base address. > + > +config GPIO_BASE > + hex > + default 0x1080 > + help > + GPIO i/o-mapped base address. > + > +config GPE0_BASE > + hex > + default 0x1100 > + help > + GPE0 i/o-mapped base address. What is GPE0? > + > +config WDT_BASE > + hex > + default 0x1140 > + help > + Watchdog timer i/o-mapped base address. > + > +config SYS_CAR_ADDR > + hex > + default ESRAM_BASE > + > +config SYS_CAR_SIZE > + hex > + default 0x8000 > + help > + Space in bytes in eSRAM used as Cache-As-ARM (CAR). > + Note this size must not exceed eSRAM's total size. > + > +endif > diff --git a/arch/x86/cpu/quark/Makefile b/arch/x86/cpu/quark/Makefile > new file mode 100644 > index 000..168c1e6 > --- /dev/null > +++ b/arch/x86/cpu/quark/Makefile > @@ -0,0 +1,8 @@ > +# > +# Copyright (C) 2015, Bin Meng > +# > +# SPDX-License-Identifier: GPL-2.0+ > +# > + > +obj-y += car.o dram.o msg_port.o quark.o > +obj-$(CONFIG_PCI) += pci.o > diff --git a/arch/x86/cpu/quark/dram.c b/arch/x86/cpu/quark/dram.c > new file mode 100644 > index 000..fbdc3cd > --- /dev/null > +++ b/arch/x86/cpu/quark/dram.c > @@ -0,0 +1,39 @@ > +/* > + * Copyright (C) 2015,
Re: [U-Boot] [PATCH 2/9] sunxi: Move SPL s_init() code to board_init_f()
On Sun, 1 Feb 2015 09:29:53 -0700
Simon Glass wrote:
> Hi,
>
> On 30 January 2015 at 10:53, Siarhei Siamashka
> wrote:
> > On Mon, 29 Dec 2014 09:15:36 -0700
> > Simon Glass wrote:
> >
> >> Hi Ian,
> >>
> >> On 28 December 2014 at 02:19, Ian Campbell wrote:
> >> > On Tue, 2014-12-23 at 12:04 -0700, Simon Glass wrote:
> >> >
> >> >> +void board_init_f(ulong dummy)
> >> >> +{
> >> > [...]
> >> >> + /* Clear the BSS. */
> >> >> + memset(__bss_start, 0, __bss_end - __bss_start);
> >> >> +
> >> >> + board_init_r(NULL, 0);
> >> >
> >> > The previous (__weak) version of board_init_f also sets gd, which you've
> >> > also removed from s_init here and not added back anywhere (indeed, this
> >> > is the point...). But where is gd initialised now?
> >>
> >> It's still in start.S, I've just removed this duplicate.
> >>
> >> >
> >> > The patch generally looks good, two quick questions: has it been tested
> >> > in both FEL and regular mode, and has it been tested with a "legacy" as
> >> > well as a driver model system? (I might be able to find time in a day or
> >> > two to answer these myself, but for now I'll just ask).
> >>
> >> I haven't tried FEL, I only just heard of it in your email. I'll see
> >> if I can figure out how to test that.
> >
> > Just like Ian suspected, this patch has messed up the FEL boot mode
> > support.
> >
> > In a nutshell, FEL is a special USB protocol (accessible on a USB OTG
> > connector), which is implemented by the boot ROM and activated by
> > holding a special hardware button pressed and rebooting the device.
> > FEL supports commands to read/write device RAM and execute code on
> > the device. It is designed for device unbricking and firmware recovery.
>
> If I understand it correctly, this is the same function that is
> available on Exynos5, Tegra, MX6 and probably others.
>
> >
> > In particular, the FEL boot mode support is very useful for debugging
> > u-boot and kernel problems on tablets (the SD card slot can be used
> > for the UART console, while the system is booted over a micro-USB cable
> > with the help of FEL):
> > http://linux-sunxi.org/File:MSI_Primo81_and_MicroSD_breakout.jpg
> >
> > In u-boot it is used in the following way:
> > 1. The SPL code is uploaded from the linux PC to the device SRAM via
> > a FEL command (using the 'fel' program from sunxi-tools).
> > 2. The SPL code is executed via a FEL command and expected to
> > initialize the DRAM controller. The code is executed as a
> > normal C or assembly function, which needs to return control
> > back to the BROM code when it is done. Right now this
> > function is s_init().
>
> Isn't this just another way of loading SPL then? What is so special /
> different about FEL?
I'm not very familiar with the other platforms, but the special part
here is "needs to return control back to the BROM code when it is done".
We are relying on the FEL USB protocol implementation, which is
hardcoded in BROM. FEL is used to upload data over USB to the device
memory. And FEL needs to be used twice. Once for uploading data to SRAM
and running the SPL. And one more time for uploading the rest of the
data to DRAM.
As we naturally can't modify the Allwinner code in BROM, here u-boot
needs to play according to the FEL rules and not the other way around.
As I see it, an alternative solution would be to implement USB OTG
support and the FEL protocol (or some other protocol) in the u-boot
SPL and stop relying on BROM code for uploading data to DRAM. Until
this is done, the sunxi FEL variant of SPL needs to return control to
the BROM code nicely after it has initialized DRAM and abstain from
doing anything else.
I hope that this clarifies the situation.
> > 3. As the DRAM is initialized and available now, the main u-boot
> > binary is now uploaded to DRAM via FEL. Together with boot.scr,
> > the kernel, the dtb file and optionally initramfs as needed.
> > 4. The main u-boot binary is executed via a FEL command, but never
> > returns back to BROM anymore.
> >
> > More details are available in the linux-sunxi wiki:
> > http://linux-sunxi.org/FEL
> > http://linux-sunxi.org/FEL/Protocol
> > http://linux-sunxi.org/FEL/USBBoot
> >
> > I have submitted a patch to fix this regression:
> > https://patchwork.ozlabs.org/patch/434826/
> >
> > If you encounter problems and/or need help when testing FEL, please
> > let me know.
>
> OK I commented on that patch.
Thanks.
--
Best regards,
Siarhei Siamashka
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[U-Boot] [PATCH v2 02/26] dm: tegra: config: Increase pre-reloc malloc() to 6KB
If we enable GPIOs as well as everything else, we need just over 4KB of space. Enlarge it a little. Signed-off-by: Simon Glass --- Changes in v2: None include/configs/tegra-common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 8f1e370..182458f 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -47,7 +47,7 @@ * Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */ -#define CONFIG_SYS_MALLOC_F_LEN(1 << 10) +#define CONFIG_SYS_MALLOC_F_LEN(6 << 10) #define CONFIG_SYS_NONCACHED_MEMORY(1 << 20) /* 1 MiB */ -- 2.2.0.rc0.207.ga3a616c ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 03/26] fdt: Add binding decode function for display-timings
This is useful for display parameters. Add a simple decode function to read
from this device tree node.
Signed-off-by: Simon Glass
---
Changes in v2: None
doc/device-tree-bindings/video/display-timing.txt | 110 ++
include/fdtdec.h | 80
lib/fdtdec.c | 92 ++
3 files changed, 282 insertions(+)
create mode 100644 doc/device-tree-bindings/video/display-timing.txt
diff --git a/doc/device-tree-bindings/video/display-timing.txt
b/doc/device-tree-bindings/video/display-timing.txt
new file mode 100644
index 000..e1d4a0b
--- /dev/null
+++ b/doc/device-tree-bindings/video/display-timing.txt
@@ -0,0 +1,110 @@
+display-timing bindings
+===
+
+display-timings node
+
+
+required properties:
+ - none
+
+optional properties:
+ - native-mode: The native mode for the display, in case multiple modes are
+ provided. When omitted, assume the first node is the native.
+
+timing subnode
+--
+
+required properties:
+ - hactive, vactive: display resolution
+ - hfront-porch, hback-porch, hsync-len: horizontal display timing parameters
+ in pixels
+ vfront-porch, vback-porch, vsync-len: vertical display timing parameters in
+ lines
+ - clock-frequency: display clock in Hz
+
+optional properties:
+ - hsync-active: hsync pulse is active low/high/ignored
+ - vsync-active: vsync pulse is active low/high/ignored
+ - de-active: data-enable pulse is active low/high/ignored
+ - pixelclk-active: with
+ - active high = drive pixel data on rising edge/
+ sample data on falling edge
+ - active low = drive pixel data on falling edge/
+ sample data on rising edge
+ - ignored = ignored
+ - interlaced (bool): boolean to enable interlaced mode
+ - doublescan (bool): boolean to enable doublescan mode
+ - doubleclk (bool): boolean to enable doubleclock mode
+
+All the optional properties that are not bool follow the following logic:
+<1>: high active
+<0>: low active
+omitted: not used on hardware
+
+There are different ways of describing the capabilities of a display. The
+devicetree representation corresponds to the one commonly found in datasheets
+for displays. If a display supports multiple signal timings, the native-mode
+can be specified.
+
+The parameters are defined as:
+
+ +--+-+--+---+
+ | |↑| | |
+ | ||vback_porch | | |
+ | |↓| | |
+ +--###--+---+
+ | #↑# | |
+ | #|# | |
+ | hback #|# hfront | hsync |
+ | porch #| hactive # porch | len |
+ |<>#<---+--->#<>|<->|
+ | #|# | |
+ | #|vactive # | |
+ | #|# | |
+ | #↓# | |
+ +--###--+---+
+ | |↑| | |
+ | ||vfront_porch| | |
+ | |↓| | |
+ +--+-+--+---+
+ | |↑| | |
+ | ||vsync_len | | |
+ | |↓| | |
+ +--+-+--+---+
+
+Example:
+
+ display-timings {
+ native-mode = <&timing0>;
+ timing0: 1080p24 {
+ /* 1920x1080p24 */
+ clock-frequency = <5200>;
+ hactive = <1920>;
+ vactive = <1080>;
+ hfront-porch = <25>;
+ hback-porch = <25>;
+ hsync-len = <25>;
+ vback-porch = <2>;
+ vfront-porch = <2>;
+ vsync-len = <2>;
+ hsync-active = <1>;
+ };
+ };
+
+Every required property also supports the use of ranges, so the commonly used
+datasheet description with minimum, typical and maximum values c
[U-Boot] [PATCH v2 0/26] tegra: Add eDP support for nyan-big
This series adds eDP support for nyan-big so that the display works.
Nyan-big is based on tegra124.
Some support is added for new clocks to make this work. The drm_dp_helper.h
file is brought in from Linux since many of the DisplayPort constants are
generic. A very simple uclass is added for DisplayPort, and the Tegra
driver makes use of that. The U-Boot EDID support is enhanced to read some
additional information (detailed timings).
There is existing video support for Tegra20, but I don't think it works for
Tegra30/114 (is this correct?). This series relies on detecting the display
at run-time as I cannot find a good device tree binding for things like
display depth. But if we could resolve that then it might be possible to
move Tegra20 over to use the same driver, etc. There is clearly a lot in
common with the display controllers - I have exploited this with the header
file but not with the C file.
HDMI is not supported at present. If this is easy and there is an existing
driver to follow along with then I might be able to incorporate it later.
This series is available at u-boot-dm/nyan-working
Changes in v2:
- Rebase on top of u-boot-dm
Simon Glass (26):
dm: gpio: Add error handling and a function to claim vector GPIOs
dm: tegra: config: Increase pre-reloc malloc() to 6KB
fdt: Add binding decode function for display-timings
tegra: Move the pww into tegra-common
tegra: pwm: Allow the clock rate to be left as is
tegra: Move checkboard() into the board code
tegra: Add a board ID function
power: Export register access functions from as3722
tegra: Provide a function to allow LCD PMIC setup
tegra: Add support for setting up a as3722 PMIC
tegra: nyan-big: Add LCD PMIC init and board ID
tegra124: dts: Add host1x node to provide display information
tegra: config: Use CONFIG_LCD to detect LCD presence
tegra: clock: Add checking for invalid clock IDs
tegra: clock: Split the clock source code into a separate function
tegra124: clock: Add display clocks and functions
tegra: Move display controller header into common
video: Add drm_dp_helper.h
edid: Add a function to read detailed monitor timings
dm: video: Add a uclass for display port
tegra: dts: nyan-big: Add definitions for eDP display
tegra: video: Support serial output resource (SOR) on tegra124
tegra: video: Add Embedded DisplayPort driver
tegra: video: support eDP displays on Tegra124 devices
tegra: config: nyan-big: Enable LCD
tegra124: video: Add full link training for eDP
arch/arm/cpu/armv7/tegra-common/Makefile |1 +
arch/arm/cpu/armv7/{tegra20 => tegra-common}/pwm.c |5 +-
arch/arm/cpu/armv7/tegra20/Makefile|1 -
arch/arm/cpu/armv7/tegra20/display.c |2 +-
arch/arm/cpu/tegra-common/board.c |8 -
arch/arm/cpu/tegra-common/clock.c | 83 +-
arch/arm/cpu/tegra124-common/clock.c | 141 +-
arch/arm/dts/tegra124-nyan-big.dts | 47 +
arch/arm/dts/tegra124.dtsi | 84 ++
arch/arm/include/asm/arch-tegra/clk_rst.h | 15 +-
arch/arm/include/asm/arch-tegra/clock.h| 14 +
.../include/asm/{arch-tegra20 => arch-tegra}/dc.h | 63 +-
arch/arm/include/asm/arch-tegra/pwm.h | 60 +
arch/arm/include/asm/arch-tegra/sys_proto.h| 19 +-
arch/arm/include/asm/arch-tegra124/clock-tables.h |3 +-
arch/arm/include/asm/arch-tegra124/clock.h | 21 +
arch/arm/include/asm/arch-tegra124/display.h | 58 +
arch/arm/include/asm/arch-tegra124/pwm.h | 14 +
arch/arm/include/asm/arch-tegra20/display.h|2 +-
arch/arm/include/asm/arch-tegra20/pwm.h| 54 +-
board/nvidia/common/board.c| 40 +-
board/nvidia/nyan-big/nyan-big.c | 34 +-
common/edid.c | 105 ++
configs/nyan-big_defconfig |2 +
.../gpu/nvidia,tegra20-host1x.txt | 372 +
doc/device-tree-bindings/video/display-timing.txt | 110 ++
drivers/gpio/gpio-uclass.c | 38 +-
drivers/power/as3722.c | 16 +-
drivers/video/Kconfig | 15 +
drivers/video/Makefile |6 +
drivers/video/dp-uclass.c | 34 +
drivers/video/tegra124/Makefile| 10 +
drivers/video/tegra124/display.c | 358 +
drivers/video/tegra124/displayport.h | 412 ++
drivers/video/tegra124/dp.c| 1500
drivers/video/tegra124/sor.c | 951 +
drivers/video/tegra124/sor.h | 913
drivers/video/tegra124/tegra124-lcd.c | 94 ++
include/asm-generic/gpio.h | 15 +-
include/configs/nya
[U-Boot] [PATCH v2 09/26] tegra: Provide a function to allow LCD PMIC setup
Some LCDs require a PMIC to be set up - add a function for this.
Signed-off-by: Simon Glass
---
Changes in v2: None
arch/arm/include/asm/arch-tegra/sys_proto.h | 8
board/nvidia/common/board.c | 10 ++
2 files changed, 18 insertions(+)
diff --git a/arch/arm/include/asm/arch-tegra/sys_proto.h
b/arch/arm/include/asm/arch-tegra/sys_proto.h
index 914d8b9..83f9f47 100644
--- a/arch/arm/include/asm/arch-tegra/sys_proto.h
+++ b/arch/arm/include/asm/arch-tegra/sys_proto.h
@@ -17,4 +17,12 @@ void invalidate_dcache(void);
*/
int tegra_board_id(void);
+/**
+ * tegra_lcd_pmic_init() - Set up the PMIC for a board
+ *
+ * @board_id: Board ID which may be used to select LCD type
+ * @return 0 if OK, -ve on error
+ */
+int tegra_lcd_pmic_init(int board_id);
+
#endif
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index 2ee9b6d..0a33bc5 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -99,6 +99,11 @@ int checkboard(void)
}
#endif /* CONFIG_DISPLAY_BOARDINFO */
+__weak int tegra_lcd_pmic_init(int board_it)
+{
+ return 0;
+}
+
/*
* Routine: board_init
* Description: Early hardware init.
@@ -106,6 +111,7 @@ int checkboard(void)
int board_init(void)
{
__maybe_unused int err;
+ __maybe_unused int board_id;
/* Do clocks and UART first so that printf() works */
clock_init();
@@ -146,6 +152,10 @@ int board_init(void)
#endif
#ifdef CONFIG_LCD
+ board_id = tegra_board_id();
+ err = tegra_lcd_pmic_init(board_id);
+ if (err)
+ return err;
tegra_lcd_check_next_stage(gd->fdt_blob, 0);
#endif
--
2.2.0.rc0.207.ga3a616c
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[U-Boot] [PATCH v2 07/26] tegra: Add a board ID function
Add a way of displaying a numeric board ID on start-up.
Signed-off-by: Simon Glass
---
Changes in v2: None
arch/arm/include/asm/arch-tegra/sys_proto.h | 11 ++-
board/nvidia/common/board.c | 12 +++-
2 files changed, 17 insertions(+), 6 deletions(-)
diff --git a/arch/arm/include/asm/arch-tegra/sys_proto.h
b/arch/arm/include/asm/arch-tegra/sys_proto.h
index 8b3fbe1..914d8b9 100644
--- a/arch/arm/include/asm/arch-tegra/sys_proto.h
+++ b/arch/arm/include/asm/arch-tegra/sys_proto.h
@@ -8,12 +8,13 @@
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
-struct tegra_sysinfo {
- char *board_string;
-};
-
void invalidate_dcache(void);
-extern const struct tegra_sysinfo sysinfo;
+/**
+ * tegra_board_id() - Get the board iD
+ *
+ * @return a board ID, or -ve on error
+ */
+int tegra_board_id(void);
#endif
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index 128b5fb..2ee9b6d 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -80,10 +80,20 @@ static void power_det_init(void)
#endif
}
+__weak int tegra_board_id(void)
+{
+ return -1;
+}
+
#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard(void)
{
- printf("Board: %s\n", CONFIG_TEGRA_BOARD_STRING);
+ int board_id = tegra_board_id();
+
+ printf("Board: %s", CONFIG_TEGRA_BOARD_STRING);
+ if (board_id != -1)
+ printf(", ID: %d\n", board_id);
+ printf("\n");
return 0;
}
--
2.2.0.rc0.207.ga3a616c
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[U-Boot] [PATCH v2 11/26] tegra: nyan-big: Add LCD PMIC init and board ID
Add required setup for the LCD display, and a function to provide the
board ID. This requires GPIOs to be available prior to relocation.
Signed-off-by: Simon Glass
---
Changes in v2: None
arch/arm/dts/tegra124-nyan-big.dts | 4
board/nvidia/nyan-big/nyan-big.c | 34 +-
2 files changed, 37 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/tegra124-nyan-big.dts
b/arch/arm/dts/tegra124-nyan-big.dts
index c1f35a0..10e1914 100644
--- a/arch/arm/dts/tegra124-nyan-big.dts
+++ b/arch/arm/dts/tegra124-nyan-big.dts
@@ -308,6 +308,10 @@
};
};
+ gpio@6000d000 {
+ u-boot,dm-pre-reloc;
+ };
+
gpio-keys {
compatible = "gpio-keys";
diff --git a/board/nvidia/nyan-big/nyan-big.c b/board/nvidia/nyan-big/nyan-big.c
index d4d2496..ae8874b 100644
--- a/board/nvidia/nyan-big/nyan-big.c
+++ b/board/nvidia/nyan-big/nyan-big.c
@@ -6,8 +6,11 @@
*/
#include
-#include
+#include
+#include
#include
+#include
+#include
#include "pinmux-config-nyan-big.h"
/*
@@ -25,3 +28,32 @@ void pinmux_init(void)
pinmux_config_drvgrp_table(nyan_big_drvgrps,
ARRAY_SIZE(nyan_big_drvgrps));
}
+
+int tegra_board_id(void)
+{
+ static const int vector[] = {GPIO_PQ3, GPIO_PT1, GPIO_PX1,
+ GPIO_PX4, -1};
+
+ gpio_claim_vector(vector, "board_id%d");
+ return gpio_get_values_as_int(vector);
+}
+
+int tegra_lcd_pmic_init(int board_id)
+{
+ struct udevice *pmic;
+ int ret;
+
+ ret = as3722_get(&pmic);
+ if (ret)
+ return -ENOENT;
+
+ if (board_id == 0)
+ as3722_write(pmic, 0x00, 0x3c);
+ else
+ as3722_write(pmic, 0x00, 0x50);
+ as3722_write(pmic, 0x12, 0x10);
+ as3722_write(pmic, 0x0c, 0x07);
+ as3722_write(pmic, 0x20, 0x10);
+
+ return 0;
+}
--
2.2.0.rc0.207.ga3a616c
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[U-Boot] [PATCH v2 01/26] dm: gpio: Add error handling and a function to claim vector GPIOs
gpio_get_values_as_int() should return an error if something goes wrong.
Also provide gpio_claim_vector(), a function to request the GPIOs and set
them to input mode. Otherwise callers have to do this themselves.
Signed-off-by: Simon Glass
---
Changes in v2: None
drivers/gpio/gpio-uclass.c | 38 +++---
include/asm-generic/gpio.h | 15 ---
2 files changed, 47 insertions(+), 6 deletions(-)
diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c
index a69bbd2..6e05c54 100644
--- a/drivers/gpio/gpio-uclass.c
+++ b/drivers/gpio/gpio-uclass.c
@@ -495,22 +495,54 @@ int gpio_get_status(struct udevice *dev, int offset, char
*buf, int buffsize)
return 0;
}
+int gpio_claim_vector(const int *gpio_num_array, const char *fmt)
+{
+ int i, ret;
+ int gpio;
+
+ for (i = 0; i < 32; i++) {
+ gpio = gpio_num_array[i];
+ if (gpio == -1)
+ break;
+ ret = gpio_requestf(gpio, fmt, i);
+ if (ret)
+ goto err;
+ ret = gpio_direction_input(gpio);
+ if (ret) {
+ gpio_free(gpio);
+ goto err;
+ }
+ }
+
+ return 0;
+err:
+ for (i--; i >= 0; i--)
+ gpio_free(gpio_num_array[i]);
+
+ return ret;
+}
+
/*
* get a number comprised of multiple GPIO values. gpio_num_array points to
* the array of gpio pin numbers to scan, terminated by -1.
*/
-unsigned gpio_get_values_as_int(const int *gpio_num_array)
+int gpio_get_values_as_int(const int *gpio_list)
{
int gpio;
unsigned bitmask = 1;
unsigned vector = 0;
+ int ret;
while (bitmask &&
- ((gpio = *gpio_num_array++) != -1)) {
- if (gpio_get_value(gpio))
+ ((gpio = *gpio_list++) != -1)) {
+ ret = gpio_get_value(gpio);
+ if (ret < 0)
+ return ret;
+ else if (ret)
vector |= bitmask;
bitmask <<= 1;
}
+
return vector;
}
diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h
index 3b96b82..4752ea4 100644
--- a/include/asm-generic/gpio.h
+++ b/include/asm-generic/gpio.h
@@ -336,15 +336,24 @@ int gpio_lookup_name(const char *name, struct udevice
**devp,
unsigned int *offsetp, unsigned int *gpiop);
/**
- * get_gpios() - Turn the values of a list of GPIOs into an integer
+ * gpio_get_values_as_int() - Turn the values of a list of GPIOs into an int
*
* This puts the value of the first GPIO into bit 0, the second into bit 1,
* etc. then returns the resulting integer.
*
* @gpio_list: List of GPIOs to collect
- * @return resulting integer value
+ * @return resulting integer value, or -ve on error
*/
-unsigned gpio_get_values_as_int(const int *gpio_list);
+int gpio_get_values_as_int(const int *gpio_list);
+
+/**
+ * gpio_claim_vector() - claim a number of GPIOs for input
+ *
+ * @gpio_num_array:array of gpios to claim, terminated by -1
+ * @fmt: format string for GPIO names, e.g. "board_id%d"
+ * @return 0 if OK, -ve on error
+ */
+int gpio_claim_vector(const int *gpio_num_array, const char *fmt);
/**
* gpio_request_by_name() - Locate and request a GPIO by name
--
2.2.0.rc0.207.ga3a616c
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[U-Boot] [PATCH v2 05/26] tegra: pwm: Allow the clock rate to be left as is
When enabling a PWM, allow the existing clock rate and source to stand
unchanged.
Signed-off-by: Simon Glass
---
Changes in v2: None
arch/arm/cpu/armv7/tegra-common/pwm.c | 5 -
arch/arm/include/asm/arch-tegra/pwm.h | 2 +-
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/tegra-common/pwm.c
b/arch/arm/cpu/armv7/tegra-common/pwm.c
index 5b88636..06a0f86 100644
--- a/arch/arm/cpu/armv7/tegra-common/pwm.c
+++ b/arch/arm/cpu/armv7/tegra-common/pwm.c
@@ -24,7 +24,10 @@ void pwm_enable(unsigned channel, int rate, int pulse_width,
int freq_divider)
assert(channel < PWM_NUM_CHANNELS);
/* TODO: Can we use clock_adjust_periph_pll_div() here? */
- clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ, rate);
+ if (rate) {
+ clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ,
+ rate);
+ }
reg = PWM_ENABLE_MASK;
reg |= pulse_width << PWM_WIDTH_SHIFT;
diff --git a/arch/arm/include/asm/arch-tegra/pwm.h
b/arch/arm/include/asm/arch-tegra/pwm.h
index 8e7397d..92dced4 100644
--- a/arch/arm/include/asm/arch-tegra/pwm.h
+++ b/arch/arm/include/asm/arch-tegra/pwm.h
@@ -31,7 +31,7 @@ struct pwm_ctlr {
* Program the PWM with the given parameters.
*
* @param channel PWM channel to update
- * @param rate Clock rate to use for PWM
+ * @param rate Clock rate to use for PWM, or 0 to leave alone
* @param pulse_width high pulse width: 0=always low, 1=1/256 pulse high,
* n = n/256 pulse high
* @param freq_divider frequency divider value (1 to use rate as is)
--
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[U-Boot] [PATCH v2 04/26] tegra: Move the pww into tegra-common
This is needed for tegra124 also, so make it common and add a header file
for tegra124.
Signed-off-by: Simon Glass
---
Changes in v2: None
arch/arm/cpu/armv7/tegra-common/Makefile | 1 +
arch/arm/cpu/armv7/{tegra20 => tegra-common}/pwm.c | 0
arch/arm/cpu/armv7/tegra20/Makefile| 1 -
arch/arm/include/asm/arch-tegra/pwm.h | 60 ++
arch/arm/include/asm/arch-tegra124/pwm.h | 14 +
arch/arm/include/asm/arch-tegra20/pwm.h| 54 ++-
6 files changed, 79 insertions(+), 51 deletions(-)
rename arch/arm/cpu/armv7/{tegra20 => tegra-common}/pwm.c (100%)
create mode 100644 arch/arm/include/asm/arch-tegra/pwm.h
create mode 100644 arch/arm/include/asm/arch-tegra124/pwm.h
diff --git a/arch/arm/cpu/armv7/tegra-common/Makefile
b/arch/arm/cpu/armv7/tegra-common/Makefile
index 463c260..91feb81 100644
--- a/arch/arm/cpu/armv7/tegra-common/Makefile
+++ b/arch/arm/cpu/armv7/tegra-common/Makefile
@@ -8,3 +8,4 @@
#
obj-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o
+obj-$(CONFIG_PWM_TEGRA) += pwm.o
diff --git a/arch/arm/cpu/armv7/tegra20/pwm.c
b/arch/arm/cpu/armv7/tegra-common/pwm.c
similarity index 100%
rename from arch/arm/cpu/armv7/tegra20/pwm.c
rename to arch/arm/cpu/armv7/tegra-common/pwm.c
diff --git a/arch/arm/cpu/armv7/tegra20/Makefile
b/arch/arm/cpu/armv7/tegra20/Makefile
index 9b4295c..56e54d0 100644
--- a/arch/arm/cpu/armv7/tegra20/Makefile
+++ b/arch/arm/cpu/armv7/tegra20/Makefile
@@ -7,5 +7,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_PWM_TEGRA) += pwm.o
obj-$(CONFIG_VIDEO_TEGRA) += display.o
diff --git a/arch/arm/include/asm/arch-tegra/pwm.h
b/arch/arm/include/asm/arch-tegra/pwm.h
new file mode 100644
index 000..8e7397d
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/pwm.h
@@ -0,0 +1,60 @@
+/*
+ * Tegra pulse width frequency modulator definitions
+ *
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_TEGRA_PWM_H
+#define __ASM_ARCH_TEGRA_PWM_H
+
+/* This is a single PWM channel */
+struct pwm_ctlr {
+ uint control; /* Control register */
+ uint reserved[3]; /* Space space */
+};
+
+#define PWM_NUM_CHANNELS 4
+
+/* PWM_CONTROLLER_PWM_CSR_0/1/2/3_0 */
+#define PWM_ENABLE_SHIFT 31
+#define PWM_ENABLE_MASK(0x1 << PWM_ENABLE_SHIFT)
+
+#define PWM_WIDTH_SHIFT16
+#define PWM_WIDTH_MASK (0x7FFF << PWM_WIDTH_SHIFT)
+
+#define PWM_DIVIDER_SHIFT 0
+#define PWM_DIVIDER_MASK (0x1FFF << PWM_DIVIDER_SHIFT)
+
+/**
+ * Program the PWM with the given parameters.
+ *
+ * @param channel PWM channel to update
+ * @param rate Clock rate to use for PWM
+ * @param pulse_width high pulse width: 0=always low, 1=1/256 pulse high,
+ * n = n/256 pulse high
+ * @param freq_divider frequency divider value (1 to use rate as is)
+ */
+void pwm_enable(unsigned channel, int rate, int pulse_width, int freq_divider);
+
+/**
+ * Request a pwm channel as referenced by a device tree node.
+ *
+ * This channel can then be passed to pwm_enable().
+ *
+ * @param blob Device tree blob
+ * @param node Node containing reference to pwm
+ * @param prop_nameProperty name of pwm reference
+ * @return channel number, if ok, else -1
+ */
+int pwm_request(const void *blob, int node, const char *prop_name);
+
+/**
+ * Set up the pwm controller, by looking it up in the fdt.
+ *
+ * @return 0 if ok, -1 if the device tree node was not found or invalid.
+ */
+int pwm_init(const void *blob);
+
+#endif /* __ASM_ARCH_TEGRA_PWM_H */
diff --git a/arch/arm/include/asm/arch-tegra124/pwm.h
b/arch/arm/include/asm/arch-tegra124/pwm.h
new file mode 100644
index 000..3d2c432
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/pwm.h
@@ -0,0 +1,14 @@
+/*
+ * Tegra pulse width frequency modulator definitions
+ *
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_TEGRA124_PWM_H
+#define __ASM_ARCH_TEGRA124_PWM_H
+
+#include
+
+#endif /* __ASM_ARCH_TEGRA124_PWM_H */
diff --git a/arch/arm/include/asm/arch-tegra20/pwm.h
b/arch/arm/include/asm/arch-tegra20/pwm.h
index 8e7397d..2207d9c 100644
--- a/arch/arm/include/asm/arch-tegra20/pwm.h
+++ b/arch/arm/include/asm/arch-tegra20/pwm.h
@@ -6,55 +6,9 @@
* SPDX-License-Identifier:GPL-2.0+
*/
-#ifndef __ASM_ARCH_TEGRA_PWM_H
-#define __ASM_ARCH_TEGRA_PWM_H
+#ifndef __ASM_ARCH_TEGRA20_PWM_H
+#define __ASM_ARCH_TEGRA20_PWM_H
-/* This is a single PWM channel */
-struct pwm_ctlr {
- uint control; /* Control register */
- uint reserved[3]; /* Space space */
-};
+#include
-#define PWM_NUM_CHANNELS 4
-
-/* PWM_CONTROLLER_PWM_CSR_0/1/2/3_0 */
-#define PWM_ENABLE_SHIFT 31
-#define PWM_ENABLE_MASK(0x1 << PWM_ENABLE_SHIFT)
-
-#define PWM_WIDTH_SHIFT16
-#define PWM_WIDTH_MASK
[U-Boot] [PATCH v2 06/26] tegra: Move checkboard() into the board code
This is only used by Nvidia boards, so move it into nvidia/common to
simplify things.
Signed-off-by: Simon Glass
---
Changes in v2: None
arch/arm/cpu/tegra-common/board.c | 8
board/nvidia/common/board.c | 13 +
2 files changed, 9 insertions(+), 12 deletions(-)
diff --git a/arch/arm/cpu/tegra-common/board.c
b/arch/arm/cpu/tegra-common/board.c
index b6a84a5..67ee8c4 100644
--- a/arch/arm/cpu/tegra-common/board.c
+++ b/arch/arm/cpu/tegra-common/board.c
@@ -58,14 +58,6 @@ int dram_init(void)
return 0;
}
-#ifdef CONFIG_DISPLAY_BOARDINFO
-int checkboard(void)
-{
- printf("Board: %s\n", sysinfo.board_string);
- return 0;
-}
-#endif /* CONFIG_DISPLAY_BOARDINFO */
-
static int uart_configs[] = {
#if defined(CONFIG_TEGRA20)
#if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index 80ef8fd..128b5fb 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -52,10 +52,6 @@ U_BOOT_DEVICE(tegra_gpios) = {
};
#endif
-const struct tegra_sysinfo sysinfo = {
- CONFIG_TEGRA_BOARD_STRING
-};
-
__weak void pinmux_init(void) {}
__weak void pin_mux_usb(void) {}
__weak void pin_mux_spi(void) {}
@@ -84,6 +80,15 @@ static void power_det_init(void)
#endif
}
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+ printf("Board: %s\n", CONFIG_TEGRA_BOARD_STRING);
+
+ return 0;
+}
+#endif /* CONFIG_DISPLAY_BOARDINFO */
+
/*
* Routine: board_init
* Description: Early hardware init.
--
2.2.0.rc0.207.ga3a616c
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[U-Boot] [PATCH v2 12/26] tegra124: dts: Add host1x node to provide display information
This peripheral is required to get the LCD display running. Add it to
tegra124 and also bring in the binding file from Linux 3.18
Signed-off-by: Simon Glass
---
Changes in v2: None
arch/arm/dts/tegra124.dtsi | 84 +
.../gpu/nvidia,tegra20-host1x.txt | 372 +
2 files changed, 456 insertions(+)
create mode 100644 doc/device-tree-bindings/gpu/nvidia,tegra20-host1x.txt
diff --git a/arch/arm/dts/tegra124.dtsi b/arch/arm/dts/tegra124.dtsi
index 9fa141d..43b7f22 100644
--- a/arch/arm/dts/tegra124.dtsi
+++ b/arch/arm/dts/tegra124.dtsi
@@ -76,6 +76,85 @@
};
};
+ host1x@5000 {
+ compatible = "nvidia,tegra124-host1x", "simple-bus";
+ reg = <0x5000 0x00034000>;
+ interrupts = , /* syncpt */
+; /* general */
+ clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
+ resets = <&tegra_car 28>;
+ reset-names = "host1x";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ranges = <0x5400 0x5400 0x0100>;
+
+ dc@5420 {
+ compatible = "nvidia,tegra124-dc";
+ reg = <0x5420 0x0004>;
+ interrupts = ;
+ clocks = <&tegra_car TEGRA124_CLK_DISP1>,
+<&tegra_car TEGRA124_CLK_PLL_P>;
+ clock-names = "dc", "parent";
+ resets = <&tegra_car 27>;
+ reset-names = "dc";
+
+ nvidia,head = <0>;
+ };
+
+ dc@5424 {
+ compatible = "nvidia,tegra124-dc";
+ reg = <0x5424 0x0004>;
+ interrupts = ;
+ clocks = <&tegra_car TEGRA124_CLK_DISP2>,
+<&tegra_car TEGRA124_CLK_PLL_P>;
+ clock-names = "dc", "parent";
+ resets = <&tegra_car 26>;
+ reset-names = "dc";
+
+ nvidia,head = <1>;
+ };
+
+ hdmi@5428 {
+ compatible = "nvidia,tegra124-hdmi";
+ reg = <0x5428 0x0004>;
+ interrupts = ;
+ clocks = <&tegra_car TEGRA124_CLK_HDMI>,
+<&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
+ clock-names = "hdmi", "parent";
+ resets = <&tegra_car 51>;
+ reset-names = "hdmi";
+ status = "disabled";
+ };
+
+ sor@5454 {
+ compatible = "nvidia,tegra124-sor";
+ reg = <0x5454 0x0004>;
+ interrupts = ;
+ clocks = <&tegra_car TEGRA124_CLK_SOR0>,
+<&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
+<&tegra_car TEGRA124_CLK_PLL_DP>,
+<&tegra_car TEGRA124_CLK_CLK_M>;
+ clock-names = "sor", "parent", "dp", "safe";
+ resets = <&tegra_car 182>;
+ reset-names = "sor";
+ status = "disabled";
+ };
+
+ dpaux: dpaux@545c {
+ compatible = "nvidia,tegra124-dpaux";
+ reg = <0x545c 0x0004>;
+ interrupts = ;
+ clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
+<&tegra_car TEGRA124_CLK_PLL_DP>;
+ clock-names = "dpaux", "parent";
+ resets = <&tegra_car 181>;
+ reset-names = "dpaux";
+ status = "disabled";
+ };
+ };
+
gic: interrupt-controller@50041000 {
compatible = "arm,cortex-a15-gic";
#interrupt-cells = <3>;
@@ -349,6 +428,11 @@
clocks = <&tegra_car 105>;
};
+ pmc@7000e400 {
+ compatible = "nvidia,tegra124-pmc";
+ reg = <0x7000e400 0x400>;
+ };
+
padctl: padctl@7009f000 {
compatible = "nvidia,tegra124-xusb-padctl";
reg = <0x7009f000 0x1000>;
diff --git a/doc/device-tree-bindings/gpu/nvidia,tegra20-host1x.txt
b/doc/device-tree-bindings/gpu/nvidia,tegra20-host1x.txt
new file mode 100644
index 000..b48f4ef
--- /dev/null
+++ b/doc/device-tree-bindings/gpu/nvidia,tegra20-host1x.txt
@@ -0,0 +1,372 @@
+NVIDIA Tegra host1x
+
+Required properties:
+- compatible: "nvidia,tegra-host1x"
+- reg: Physical base address and length of the controller's registers.
+- interrupts: The interrupt outputs from the controller.
+- #address-cells: The number
[U-Boot] [PATCH v2 20/26] dm: video: Add a uclass for display port
eDP (Embedded DisplayPort) is a standard widely used in laptops to drive
LCD panels. Add a uclass for this which supports a few simple operations.
Signed-off-by: Simon Glass
---
Changes in v2: None
drivers/video/Kconfig | 7 ++
drivers/video/Makefile| 4
drivers/video/dp-uclass.c | 34 +++
include/displayport.h | 60 +++
include/dm/uclass-id.h| 1 +
5 files changed, 106 insertions(+)
create mode 100644 drivers/video/dp-uclass.c
create mode 100644 include/displayport.h
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 51728b3..62af63a 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -88,3 +88,10 @@ config VIDEO_LCD_SPI_MISO
hardware and LCD panel id retrieval (if the panel can report it). The
option takes a string in the format understood by 'name_to_gpio'
function, e.g. PH1 for pin 1 of port H.
+
+config DISPLAY_PORT
+ bool "Enable DisplayPort support"
+ help
+ eDP (Embedded DisplayPort) is a standard widely used in laptops
+ to drive LCD panels. This framework provides support for enabling
+ these displays where supported by the video hardware.
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index af2d47b..8f83fdb 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -5,6 +5,10 @@
# SPDX-License-Identifier: GPL-2.0+
#
+ifdef CONFIG_DM
+obj-$(CONFIG_DISPLAY_PORT) += dp-uclass.o
+endif
+
obj-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o videomodes.o
obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o
obj-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o
diff --git a/drivers/video/dp-uclass.c b/drivers/video/dp-uclass.c
new file mode 100644
index 000..17f5de9
--- /dev/null
+++ b/drivers/video/dp-uclass.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2014 Google Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+
+int display_port_read_edid(struct udevice *dev, u8 *buf, int buf_size)
+{
+ struct dm_display_port_ops *ops = display_port_get_ops(dev);
+
+ if (!ops || !ops->read_edid)
+ return -ENOSYS;
+ return ops->read_edid(dev, buf, buf_size);
+}
+
+int display_port_enable(struct udevice *dev, int panel_bpp,
+ const struct display_timing *timing)
+{
+ struct dm_display_port_ops *ops = display_port_get_ops(dev);
+
+ if (!ops || !ops->enable)
+ return -ENOSYS;
+ return ops->enable(dev, panel_bpp, timing);
+}
+
+UCLASS_DRIVER(display_port) = {
+ .id = UCLASS_DISPLAY_PORT,
+ .name = "display_port",
+};
diff --git a/include/displayport.h b/include/displayport.h
new file mode 100644
index 000..f7c7e25
--- /dev/null
+++ b/include/displayport.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright 2014 Google Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _DISPLAYPORT_H
+#define _DISPLAYPORT_H
+
+struct udevice;
+struct display_timing;
+
+/**
+ * display_port_read_edid() - Read information from EDID
+ *
+ * @dev: Device to read from
+ * @buf: Buffer to read into (should be EDID_SIZE bytes)
+ * @buf_size: Buffer size (should be EDID_SIZE)
+ * @return number of bytes read, <=0 for error
+ */
+int display_port_read_edid(struct udevice *dev, u8 *buf, int buf_size);
+
+/**
+ * display_port_enable() - Enable a display port device
+ *
+ * @dev: Device to enable
+ * @panel_bpp: Number of bits per pixel for panel
+ * @timing:Display timings
+ * @return 0 if OK, -ve on error
+ */
+int display_port_enable(struct udevice *dev, int panel_bpp,
+ const struct display_timing *timing);
+
+struct dm_display_port_ops {
+ /**
+* read_edid() - Read information from EDID
+*
+* @dev:Device to read from
+* @buf:Buffer to read into (should be EDID_SIZE bytes)
+* @buf_size: Buffer size (should be EDID_SIZE)
+* @return number of bytes read, <=0 for error
+*/
+ int (*read_edid)(struct udevice *dev, u8 *buf, int buf_size);
+
+ /**
+* enable() - Enable the display port device
+*
+* @dev:Device to enable
+* @panel_bpp: Number of bits per pixel for panel
+* @timing: Display timings
+* @return 0 if OK, -ve on error
+*/
+ int (*enable)(struct udevice *dev, int panel_bpp,
+ const struct display_timing *timing);
+};
+
+#define display_port_get_ops(dev) \
+ ((struct dm_display_port_ops *)(dev)->driver->ops)
+
+#endif
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 91bb90d..24eefbe 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -34,6 +34,7 @@ enum uclass_id {
UCLASS_I2C_GENERIC, /* Generic I2C device */
UCLASS_I2C_EEPROM, /* I2C EEPROM device */
UCLASS_MOD_EXP, /
[U-Boot] [PATCH v2 08/26] power: Export register access functions from as3722
With the full PMIC framework we may be able to avoid this. But for now
we need access to the PMIC.
Signed-off-by: Simon Glass
---
Changes in v2: None
drivers/power/as3722.c | 16 +---
include/power/as3722.h | 3 +++
2 files changed, 16 insertions(+), 3 deletions(-)
diff --git a/drivers/power/as3722.c b/drivers/power/as3722.c
index a60bb5f..c09e1de 100644
--- a/drivers/power/as3722.c
+++ b/drivers/power/as3722.c
@@ -27,7 +27,7 @@
#define AS3722_DEVICE_ID 0x0c
#define AS3722_ASIC_ID2 0x91
-static int as3722_read(struct udevice *pmic, u8 reg, u8 *value)
+int as3722_read(struct udevice *pmic, u8 reg, u8 *value)
{
int err;
@@ -38,7 +38,7 @@ static int as3722_read(struct udevice *pmic, u8 reg, u8
*value)
return 0;
}
-static int as3722_write(struct udevice *pmic, u8 reg, u8 value)
+int as3722_write(struct udevice *pmic, u8 reg, u8 value)
{
int err;
@@ -234,6 +234,15 @@ int as3722_gpio_direction_output(struct udevice *pmic,
unsigned int gpio,
return 0;
}
+/* Temporary function until we get the pmic framework */
+int as3722_get(struct udevice **devp)
+{
+ int bus = 0;
+ int address = 0x40;
+
+ return i2c_get_chip_for_busnum(bus, address, 1, devp);
+}
+
int as3722_init(struct udevice **devp)
{
struct udevice *pmic;
@@ -258,7 +267,8 @@ int as3722_init(struct udevice **devp)
debug("AS3722 revision %#x found on I2C bus %u, address %#x\n",
revision, bus, address);
- *devp = pmic;
+ if (devp)
+ *devp = pmic;
return 0;
}
diff --git a/include/power/as3722.h b/include/power/as3722.h
index aa966d2..0f22482 100644
--- a/include/power/as3722.h
+++ b/include/power/as3722.h
@@ -23,5 +23,8 @@ int as3722_gpio_configure(struct udevice *pmic, unsigned int
gpio,
unsigned long flags);
int as3722_gpio_direction_output(struct udevice *pmic, unsigned int gpio,
unsigned int level);
+int as3722_read(struct udevice *pmic, u8 reg, u8 *value);
+int as3722_write(struct udevice *pmic, u8 reg, u8 value);
+int as3722_get(struct udevice **devp);
#endif /* __POWER_AS3722_H__ */
--
2.2.0.rc0.207.ga3a616c
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[U-Boot] [PATCH v2 21/26] tegra: dts: nyan-big: Add definitions for eDP display
Add the various host1x peripherals to allow an eDP display to be connected.
Signed-off-by: Simon Glass
---
Changes in v2: None
arch/arm/dts/tegra124-nyan-big.dts | 43 ++
1 file changed, 43 insertions(+)
diff --git a/arch/arm/dts/tegra124-nyan-big.dts
b/arch/arm/dts/tegra124-nyan-big.dts
index 10e1914..8ac770b 100644
--- a/arch/arm/dts/tegra124-nyan-big.dts
+++ b/arch/arm/dts/tegra124-nyan-big.dts
@@ -29,6 +29,35 @@
reg = <0x8000 0x8000>;
};
+ host1x@5000 {
+ dc@5420 {
+ display-timings {
+ timing@0 {
+ clock-frequency = <6950>;
+ hactive = <1366>;
+ vactive = <768>;
+ hsync-len = <32>;
+ hfront-porch = <48>;
+ hback-porch = <20>;
+ vfront-porch = <3>;
+ vback-porch = <13>;
+ vsync-len = <6>;
+ };
+ };
+ };
+
+ sor@5454 {
+ status = "okay";
+
+ nvidia,dpaux = <&dpaux>;
+ nvidia,panel = <&panel>;
+ };
+
+ dpaux@545c {
+ status = "okay";
+ };
+ };
+
serial@70006000 {
/* Debug connector on the bottom of the board near SD card. */
status = "okay";
@@ -256,6 +285,7 @@
compatible = "pwm-backlight";
enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
+ power-supply = <&vdd_led>;
pwms = <&pwm 1 100>;
default-brightness-level = <224>;
@@ -339,6 +369,19 @@
backlight = <&backlight>;
};
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ vdd_led: regulator@5 {
+ compatible = "regulator-fixed";
+ reg = <5>;
+ regulator-name = "+VDD_LED";
+ gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+ };
+
sound {
compatible = "nvidia,tegra-audio-max98090-nyan-big",
"nvidia,tegra-audio-max98090";
--
2.2.0.rc0.207.ga3a616c
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[U-Boot] [PATCH v2 16/26] tegra124: clock: Add display clocks and functions
Add functions to provide access to the display clocks on Tegra124 including
setting the clock rate for an EDP display.
Signed-off-by: Simon Glass
---
Changes in v2: None
arch/arm/cpu/tegra-common/clock.c | 2 +
arch/arm/cpu/tegra124-common/clock.c | 141 +-
arch/arm/include/asm/arch-tegra/clk_rst.h | 15 ++-
arch/arm/include/asm/arch-tegra124/clock-tables.h | 3 +-
arch/arm/include/asm/arch-tegra124/clock.h| 21
5 files changed, 173 insertions(+), 9 deletions(-)
diff --git a/arch/arm/cpu/tegra-common/clock.c
b/arch/arm/cpu/tegra-common/clock.c
index 495cde3..0d36b02 100644
--- a/arch/arm/cpu/tegra-common/clock.c
+++ b/arch/arm/cpu/tegra-common/clock.c
@@ -592,6 +592,7 @@ void clock_init(void)
pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY);
pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH);
pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL);
+ pll_rate[CLOCK_ID_DISPLAY] = clock_get_rate(CLOCK_ID_DISPLAY);
pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC);
pll_rate[CLOCK_ID_SFROM32KHZ] = 32768;
pll_rate[CLOCK_ID_XCPU] = clock_get_rate(CLOCK_ID_XCPU);
@@ -599,6 +600,7 @@ void clock_init(void)
debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]);
debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]);
debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]);
+ debug("PLLD = %d\n", pll_rate[CLOCK_ID_DISPLAY]);
debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]);
/* Do any special system timer/TSC setup */
diff --git a/arch/arm/cpu/tegra124-common/clock.c
b/arch/arm/cpu/tegra124-common/clock.c
index fc8bd19..2d17550 100644
--- a/arch/arm/cpu/tegra124-common/clock.c
+++ b/arch/arm/cpu/tegra124-common/clock.c
@@ -42,6 +42,7 @@ enum clock_type_id {
CLOCK_TYPE_ASPTE,
CLOCK_TYPE_PMDACD2T,
CLOCK_TYPE_PCST,
+ CLOCK_TYPE_DP,
CLOCK_TYPE_PC2CC3M,
CLOCK_TYPE_PC2CC3S_T,
@@ -101,6 +102,10 @@ static enum clock_id
clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
{ CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ),CLK(OSC),
CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
MASK_BITS_31_28},
+ /* CLOCK_TYPE_DP */
+ { CLK(NONE),CLK(NONE), CLK(NONE), CLK(NONE),
+ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
+ MASK_BITS_31_28},
/* Additional clock types on Tegra114+ */
/* CLOCK_TYPE_PC2CC3M */
@@ -259,7 +264,7 @@ static enum clock_type_id clock_periph_type[PERIPHC_COUNT]
= {
/* 0x58 */
TYPE(PERIPHC_58h, CLOCK_TYPE_NONE),
- TYPE(PERIPHC_59h, CLOCK_TYPE_NONE),
+ TYPE(PERIPHC_SOR, CLOCK_TYPE_NONE),
TYPE(PERIPHC_5ah, CLOCK_TYPE_NONE),
TYPE(PERIPHC_5bh, CLOCK_TYPE_NONE),
TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT),
@@ -546,7 +551,7 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
NONE(X_RESERVED19),
NONE(ADX1),
NONE(DPAUX),
- NONE(SOR0),
+ PERIPHC_SOR,
NONE(X_RESERVED23),
/* 184 */
@@ -594,7 +599,10 @@ u32 *get_periph_source_reg(enum periph_id periph_id)
assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
internal_id = periph_id_to_internal_id[periph_id];
assert(internal_id != -1);
- if (internal_id >= PERIPHC_VW_FIRST) {
+ if (internal_id >= PERIPHC_X_FIRST) {
+ internal_id -= PERIPHC_X_FIRST;
+ return &clkrst->crc_clk_src_x[internal_id];
+ } else if (internal_id >= PERIPHC_VW_FIRST) {
internal_id -= PERIPHC_VW_FIRST;
return &clkrst->crc_clk_src_vw[internal_id];
} else {
@@ -657,8 +665,10 @@ void clock_set_enable(enum periph_id periph_id, int enable)
assert(clock_periph_id_isvalid(periph_id));
if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
- else
+ else if ((int)periph_id < PERIPH_ID_X_FIRST)
clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
+ else
+ clk = &clkrst->crc_clk_out_enb_x;
reg = readl(clk);
if (enable)
reg |= PERIPH_MASK(periph_id);
@@ -678,8 +688,10 @@ void reset_set_enable(enum periph_id periph_id, int enable)
assert(clock_periph_id_isvalid(periph_id));
if (periph_id < PERIPH_ID_VW_FIRST)
reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
- else
+ else if ((int)periph_id < PERIPH_ID_X_FIRST)
reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
+ else
+ reset = &clkrst->crc_rst_devices_x;
reg = readl(reset);
if (enable)
reg |= PERIPH_MASK(periph_id);
@@ -933,3 +945,122 @@ int tegra_plle
[U-Boot] [PATCH v2 26/26] tegra124: video: Add full link training for eDP
Add full link training as a fallback in case the fast link training
fails.
Signed-off-by: Simon Glass
---
Changes in v2:
- Rebase on top of u-boot-dm
drivers/video/tegra124/displayport.h | 228 +++
drivers/video/tegra124/dp.c | 527 +++
drivers/video/tegra124/sor.c | 86 --
drivers/video/tegra124/sor.h | 10 +
4 files changed, 784 insertions(+), 67 deletions(-)
diff --git a/drivers/video/tegra124/displayport.h
b/drivers/video/tegra124/displayport.h
index c70bbe3..ace6ab0 100644
--- a/drivers/video/tegra124/displayport.h
+++ b/drivers/video/tegra124/displayport.h
@@ -128,6 +128,183 @@ struct dpaux_ctlr {
#define DP_AUX_TIMEOUT_MS 40
#define DP_DPCP_RETRY_SLEEP_NS 400
+static const u32 tegra_dp_vs_regs[][4][4] = {
+ /* postcursor2 L0 */
+ {
+ /* pre-emphasis: L0, L1, L2, L3 */
+ {0x13, 0x19, 0x1e, 0x28}, /* voltage swing: L0 */
+ {0x1e, 0x25, 0x2d}, /* L1 */
+ {0x28, 0x32}, /* L2 */
+ {0x3c}, /* L3 */
+ },
+
+ /* postcursor2 L1 */
+ {
+ {0x12, 0x17, 0x1b, 0x25},
+ {0x1c, 0x23, 0x2a},
+ {0x25, 0x2f},
+ {0x39},
+ },
+
+ /* postcursor2 L2 */
+ {
+ {0x12, 0x16, 0x1a, 0x22},
+ {0x1b, 0x20, 0x27},
+ {0x24, 0x2d},
+ {0x36},
+ },
+
+ /* postcursor2 L3 */
+ {
+ {0x11, 0x14, 0x17, 0x1f},
+ {0x19, 0x1e, 0x24},
+ {0x22, 0x2a},
+ {0x32},
+ },
+};
+
+static const u32 tegra_dp_pe_regs[][4][4] = {
+ /* postcursor2 L0 */
+ {
+ /* pre-emphasis: L0, L1, L2, L3 */
+ {0x00, 0x09, 0x13, 0x25}, /* voltage swing: L0 */
+ {0x00, 0x0f, 0x1e}, /* L1 */
+ {0x00, 0x14}, /* L2 */
+ {0x00}, /* L3 */
+ },
+
+ /* postcursor2 L1 */
+ {
+ {0x00, 0x0a, 0x14, 0x28},
+ {0x00, 0x0f, 0x1e},
+ {0x00, 0x14},
+ {0x00},
+ },
+
+ /* postcursor2 L2 */
+ {
+ {0x00, 0x0a, 0x14, 0x28},
+ {0x00, 0x0f, 0x1e},
+ {0x00, 0x14},
+ {0x00},
+ },
+
+ /* postcursor2 L3 */
+ {
+ {0x00, 0x0a, 0x14, 0x28},
+ {0x00, 0x0f, 0x1e},
+ {0x00, 0x14},
+ {0x00},
+ },
+};
+
+static const u32 tegra_dp_pc_regs[][4][4] = {
+ /* postcursor2 L0 */
+ {
+ /* pre-emphasis: L0, L1, L2, L3 */
+ {0x00, 0x00, 0x00, 0x00}, /* voltage swing: L0 */
+ {0x00, 0x00, 0x00}, /* L1 */
+ {0x00, 0x00}, /* L2 */
+ {0x00}, /* L3 */
+ },
+
+ /* postcursor2 L1 */
+ {
+ {0x02, 0x02, 0x04, 0x05},
+ {0x02, 0x04, 0x05},
+ {0x04, 0x05},
+ {0x05},
+ },
+
+ /* postcursor2 L2 */
+ {
+ {0x04, 0x05, 0x08, 0x0b},
+ {0x05, 0x09, 0x0b},
+ {0x08, 0x0a},
+ {0x0b},
+ },
+
+ /* postcursor2 L3 */
+ {
+ {0x05, 0x09, 0x0b, 0x12},
+ {0x09, 0x0d, 0x12},
+ {0x0b, 0x0f},
+ {0x12},
+ },
+};
+
+static const u32 tegra_dp_tx_pu[][4][4] = {
+ /* postcursor2 L0 */
+ {
+ /* pre-emphasis: L0, L1, L2, L3 */
+ {0x20, 0x30, 0x40, 0x60}, /* voltage swing: L0 */
+ {0x30, 0x40, 0x60}, /* L1 */
+ {0x40, 0x60}, /* L2 */
+ {0x60}, /* L3 */
+ },
+
+ /* postcursor2 L1 */
+ {
+ {0x20, 0x20, 0x30, 0x50},
+ {0x30, 0x40, 0x50},
+ {0x40, 0x50},
+ {0x60},
+ },
+
+ /* postcursor2 L2 */
+ {
+ {0x20, 0x20, 0x30, 0x40},
+ {0x30, 0x30, 0x40},
+ {0x40, 0x50},
+ {0x60},
+ },
+
+ /* postcursor2 L3 */
+ {
+ {0x20, 0x20, 0x20, 0x40},
+ {0x30, 0x30, 0x40},
+ {0x40, 0x40},
+ {0x60},
+ },
+};
+
+enum {
+ DRIVECURRENT_LEVEL0 = 0,
+ DRIVECURRENT_LEVEL1 = 1,
+ DRIVECURRENT_LEVEL2 = 2,
+ DRIVECURRENT_LEVEL3 = 3,
+};
+
+enum {
+ PREEMPHASIS_DISABLED = 0,
+ PREEMPHASIS_LEVEL1 = 1,
+ PREEMPHASIS_LEVEL2 = 2,
+ PREEMPHASIS_LEVEL3 = 3,
+};
+
+enum {
+ POSTCURSOR2_LEVEL0 = 0,
+ POSTCURSOR2_LEVEL1 = 1,
+ POSTCURSOR2_LEVEL2 = 2,
+ POSTCURSOR2_LEVEL3 = 3,
+ POSTCURSOR2_SUPPORTED
+};
+
+static inline int tegra_dp_is_max_vs(u32 pe, u32 vs)
+{
+ return (vs < (DRIVECURRENT_LEVEL3 - pe)) ? 0 : 1;
+}
+
+static inline int tegra_dp_is_max_pe(u32 pe, u32 vs)
+{
+ return (pe
[U-Boot] [PATCH v2 19/26] edid: Add a function to read detailed monitor timings
For digital displays (such as EDP LCDs) we would like to read the EDID
information and use that to set display timings. Provide a function to do
this.
Signed-off-by: Simon Glass
---
Changes in v2: None
common/edid.c | 105 +
include/edid.h | 19 +++
2 files changed, 124 insertions(+)
diff --git a/common/edid.c b/common/edid.c
index df797fc..e08e420 100644
--- a/common/edid.c
+++ b/common/edid.c
@@ -13,6 +13,7 @@
#include
#include
#include
+#include
#include
#include
@@ -65,6 +66,110 @@ int edid_get_ranges(struct edid1_info *edid, unsigned int
*hmin,
return -1;
}
+/* Set all parts of a timing entry to the same value */
+static void set_entry(struct timing_entry *entry, u32 value)
+{
+ entry->min = value;
+ entry->typ = value;
+ entry->max = value;
+}
+
+/**
+ * decode_timing() - Decoding an 18-byte detailed timing record
+ *
+ * @buf: Pointer to EDID detailed timing record
+ * @timing:Place to put timing
+ */
+static void decode_timing(u8 *buf, struct display_timing *timing)
+{
+ uint x_mm, y_mm;
+ unsigned int ha, hbl, hso, hspw, hborder;
+ unsigned int va, vbl, vso, vspw, vborder;
+
+ /* Edid contains pixel clock in terms of 10KHz */
+ set_entry(&timing->pixelclock, (buf[0] + (buf[1] << 8)) * 1);
+ x_mm = (buf[12] + ((buf[14] & 0xf0) << 4));
+ y_mm = (buf[13] + ((buf[14] & 0x0f) << 8));
+ ha = (buf[2] + ((buf[4] & 0xf0) << 4));
+ hbl = (buf[3] + ((buf[4] & 0x0f) << 8));
+ hso = (buf[8] + ((buf[11] & 0xc0) << 2));
+ hspw = (buf[9] + ((buf[11] & 0x30) << 4));
+ hborder = buf[15];
+ va = (buf[5] + ((buf[7] & 0xf0) << 4));
+ vbl = (buf[6] + ((buf[7] & 0x0f) << 8));
+ vso = ((buf[10] >> 4) + ((buf[11] & 0x0c) << 2));
+ vspw = ((buf[10] & 0x0f) + ((buf[11] & 0x03) << 4));
+ vborder = buf[16];
+
+ set_entry(&timing->hactive, ha);
+ set_entry(&timing->hfront_porch, hso);
+ set_entry(&timing->hback_porch, hbl - hso - hspw);
+ set_entry(&timing->hsync_len, hspw);
+
+ set_entry(&timing->vactive, va);
+ set_entry(&timing->vfront_porch, vso);
+ set_entry(&timing->vback_porch, vbl - vso - vspw);
+ set_entry(&timing->vsync_len, vspw);
+
+ debug("Detailed mode clock %u Hz, %d mm x %d mm\n"
+ " %04x %04x %04x %04x hborder %x\n"
+ " %04x %04x %04x %04x vborder %x\n",
+ timing->pixelclock.typ,
+ x_mm, y_mm,
+ ha, ha + hso, ha + hso + hspw,
+ ha + hbl, hborder,
+ va, va + vso, va + vso + vspw,
+ va + vbl, vborder);
+}
+
+int edid_get_timing(u8 *buf, int buf_size, struct display_timing *timing,
+ int *panel_bits_per_colourp)
+{
+ struct edid1_info *edid = (struct edid1_info *)buf;
+ bool timing_done;
+ int i;
+
+ if (buf_size < sizeof(*edid) || edid_check_info(edid)) {
+ debug("%s: Invalid buffer\n", __func__);
+ return -EINVAL;
+ }
+
+ if (!EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(*edid)) {
+ debug("%s: No preferred timing\n", __func__);
+ return -ENOENT;
+ }
+
+ /* Look for detailed timing */
+ timing_done = false;
+ for (i = 0; i < 4; i++) {
+ struct edid_monitor_descriptor *desc;
+
+ desc = &edid->monitor_details.descriptor[i];
+ if (desc->zero_flag_1 != 0) {
+ decode_timing((u8 *)desc, timing);
+ timing_done = true;
+ break;
+ }
+ }
+ if (!timing_done)
+ return -EINVAL;
+
+ if (!EDID1_INFO_VIDEO_INPUT_DIGITAL(*edid)) {
+ debug("%s: Not a digital display\n", __func__);
+ return -ENOSYS;
+ }
+ if (edid->version != 1 || edid->revision < 4) {
+ debug("%s: EDID version %d.%d does not have required info\n",
+ __func__, edid->version, edid->revision);
+ *panel_bits_per_colourp = -1;
+ } else {
+ *panel_bits_per_colourp =
+ ((edid->video_input_definition & 0x70) >> 3) + 4;
+ }
+
+ return 0;
+}
+
/**
* Snip the tailing whitespace/return of a string.
*
diff --git a/include/edid.h b/include/edid.h
index 18ec1d5..88b4b7d 100644
--- a/include/edid.h
+++ b/include/edid.h
@@ -15,6 +15,9 @@
#include
+/* Size of the EDID data */
+#define EDID_SIZE 128
+
#define GET_BIT(_x, _pos) \
(((_x) >> (_pos)) & 1)
#define GET_BITS(_x, _pos_msb, _pos_lsb) \
@@ -287,4 +290,20 @@ int edid_get_ranges(struct edid1_info *edid, unsigned int
*hmin,
unsigned int *hmax, unsigned int *vmin,
unsigned int *vmax);
+struct display_timing;
+
+/**
+ * edid_get_timing() - Ge
[U-Boot] [PATCH v2 17/26] tegra: Move display controller header into common
Allow this to be used by other Tegra SoCs.
Signed-off-by: Simon Glass
---
Changes in v2: None
arch/arm/cpu/armv7/tegra20/display.c | 2 +-
.../include/asm/{arch-tegra20 => arch-tegra}/dc.h | 63 ++
arch/arm/include/asm/arch-tegra20/display.h| 2 +-
3 files changed, 55 insertions(+), 12 deletions(-)
rename arch/arm/include/asm/{arch-tegra20 => arch-tegra}/dc.h (89%)
diff --git a/arch/arm/cpu/armv7/tegra20/display.c
b/arch/arm/cpu/armv7/tegra20/display.c
index 61efed6..b7605ff 100644
--- a/arch/arm/cpu/armv7/tegra20/display.c
+++ b/arch/arm/cpu/armv7/tegra20/display.c
@@ -10,7 +10,7 @@
#include
#include
#include
-#include
+#include
#include
#include
diff --git a/arch/arm/include/asm/arch-tegra20/dc.h
b/arch/arm/include/asm/arch-tegra/dc.h
similarity index 89%
rename from arch/arm/include/asm/arch-tegra20/dc.h
rename to arch/arm/include/asm/arch-tegra/dc.h
index 20790b6..8803c11 100644
--- a/arch/arm/include/asm/arch-tegra20/dc.h
+++ b/arch/arm/include/asm/arch-tegra/dc.h
@@ -234,7 +234,7 @@ struct dc_disp_reg {
uint cursor_pos_ns; /* _DISP_CURSOR_POSITION_NS_0 */
uint seq_ctrl; /* _DISP_INIT_SEQ_CONTROL_0 */
- /* Address 0x442 ~ 0x446 */
+ /* Address 0x443 ~ 0x446 */
uint spi_init_seq_data_a; /* _DISP_SPI_INIT_SEQ_DATA_A_0 */
uint spi_init_seq_data_b; /* _DISP_SPI_INIT_SEQ_DATA_B_0 */
uint spi_init_seq_data_c; /* _DISP_SPI_INIT_SEQ_DATA_C_0 */
@@ -254,6 +254,11 @@ struct dc_disp_reg {
/* Address 0x4c0 ~ 0x4c1 */
uint dac_crt_ctrl; /* _DISP_DAC_CRT_CTRL_0 */
uint disp_misc_ctrl;/* _DISP_DISP_MISC_CONTROL_0 */
+
+ u32 rsvd_4c2[34]; /* 4c2 - 4e3 */
+
+ /* Address 0x4e4 */
+ u32 blend_background_color; /* _DISP_BLEND_BACKGROUND_COLOR_0 */
};
enum dc_winc_filter_p {
@@ -289,9 +294,9 @@ struct dc_winc_reg {
uint v_filter_p[WINC_FILTER_COUNT];
};
-/* WIN A/B/C Register 0x700 ~ 0x714*/
+/* WIN A/B/C Register 0x700 ~ 0x719*/
struct dc_win_reg {
- /* Address 0x700 ~ 0x714 */
+ /* Address 0x700 ~ 0x719 */
uint win_opt; /* _WIN_WIN_OPTIONS_0 */
uint byte_swap; /* _WIN_BYTE_SWAP_0 */
uint buffer_ctrl; /* _WIN_BUFFER_CONTROL_0 */
@@ -313,11 +318,16 @@ struct dc_win_reg {
uint blend_2win_y; /* _WIN_BLEND_2WIN_Y_0 */
uint blend_3win_xy; /* _WIN_BLEND_3WIN_XY_0 */
uint hp_fetch_ctrl; /* _WIN_HP_FETCH_CONTROL_0 */
+ uint global_alpha; /* _WIN_GLOBAL_ALPHA */
+ uint blend_layer_ctrl; /* _WINBUF_BLEND_LAYER_CONTROL_0 */
+ uint blend_match_select;/* _WINBUF_BLEND_MATCH_SELECT_0 */
+ uint blend_nomatch_select; /* _WINBUF_BLEND_NOMATCH_SELECT_0 */
+ uint blend_alpha_1bit; /* _WINBUF_BLEND_ALPHA_1BIT_0 */
};
-/* WINBUF A/B/C Register 0x800 ~ 0x80a */
+/* WINBUF A/B/C Register 0x800 ~ 0x80d */
struct dc_winbuf_reg {
- /* Address 0x800 ~ 0x80a */
+ /* Address 0x800 ~ 0x80d */
uint start_addr;/* _WINBUF_START_ADDR_0 */
uint start_addr_ns; /* _WINBUF_START_ADDR_NS_0 */
uint start_addr_u; /* _WINBUF_START_ADDR_U_0 */
@@ -329,6 +339,9 @@ struct dc_winbuf_reg {
uint addr_v_offset; /* _WINBUF_ADDR_V_OFFSET_0 */
uint addr_v_offset_ns; /* _WINBUF_ADDR_V_OFFSET_NS_0 */
uint uflow_status; /* _WINBUF_UFLOW_STATUS_0 */
+ uint buffer_surface_kind; /* DC_WIN_BUFFER_SURFACE_KIND */
+ uint rsvd_80c;
+ uint start_addr_hi; /* DC_WINBUF_START_ADDR_HI_0 */
};
/* Display Controller (DC_) regs */
@@ -339,16 +352,16 @@ struct dc_ctlr {
struct dc_com_reg com; /* COM register 0x300 ~ 0x329 */
uint reserved1[0xd6];
- struct dc_disp_reg disp;/* DISP register 0x400 ~ 0x4c1 */
- uint reserved2[0x3e];
+ struct dc_disp_reg disp;/* DISP register 0x400 ~ 0x4e4 */
+ uint reserved2[0x1b];
struct dc_winc_reg winc;/* Window A/B/C 0x500 ~ 0x628 */
uint reserved3[0xd7];
- struct dc_win_reg win; /* WIN A/B/C 0x700 ~ 0x714*/
- uint reserved4[0xeb];
+ struct dc_win_reg win; /* WIN A/B/C 0x700 ~ 0x719*/
+ uint reserved4[0xe6];
- struct dc_winbuf_reg winbuf;/* WINBUF A/B/C 0x800 ~ 0x80a */
+ struct dc_winbuf_reg winbuf;/* WINBUF A/B/C 0x800 ~ 0x80d */
};
#define BIT(pos) (1U << pos)
@@ -399,20 +412,45 @@ enum win_color_depth_id {
#define SPI_ENABLE BIT(24)
#define HSPI_ENABLEBIT(25)
+/* DC_CMD_STATE_ACCESS 0x040 */
+#define READ_MUX_ASSEMBLY (0 << 0)
+#define READ_MUX_ACTIVE (1 << 0)
+#define WRITE_MUX_ASSEMBLY(
[U-Boot] [PATCH v2 23/26] tegra: video: Add Embedded DisplayPort driver
This interface is used on laptop devices based on Tegra. Add a driver which
provides access to the eDP interface. The driver uses the display port
uclass.
Signed-off-by: Simon Glass
---
Changes in v2: None
drivers/video/tegra124/Makefile |1 +
drivers/video/tegra124/displayport.h | 184 ++
drivers/video/tegra124/dp.c | 1075 ++
3 files changed, 1260 insertions(+)
create mode 100644 drivers/video/tegra124/displayport.h
create mode 100644 drivers/video/tegra124/dp.c
diff --git a/drivers/video/tegra124/Makefile b/drivers/video/tegra124/Makefile
index 9aa81a5..7e08ee9 100644
--- a/drivers/video/tegra124/Makefile
+++ b/drivers/video/tegra124/Makefile
@@ -4,4 +4,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
+obj-y += dp.o
obj-y += sor.o
diff --git a/drivers/video/tegra124/displayport.h
b/drivers/video/tegra124/displayport.h
new file mode 100644
index 000..c70bbe3
--- /dev/null
+++ b/drivers/video/tegra124/displayport.h
@@ -0,0 +1,184 @@
+/*
+ * Copyright (c) 2014, NVIDIA Corporation.
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _TEGRA_DISPLAYPORT_H
+#define _TEGRA_DISPLAYPORT_H
+
+#include
+
+struct dpaux_ctlr {
+ u32 reserved0;
+ u32 intr_en_aux;
+ u32 reserved2_4;
+ u32 intr_aux;
+};
+
+#define DPAUX_INTR_EN_AUX 0x1
+#define DPAUX_INTR_AUX 0x5
+#define DPAUX_DP_AUXDATA_WRITE_W(i)(0x9 + 4 * (i))
+#define DPAUX_DP_AUXDATA_READ_W(i) (0x19 + 4 * (i))
+#define DPAUX_DP_AUXADDR 0x29
+#define DPAUX_DP_AUXCTL0x2d
+#define DPAUX_DP_AUXCTL_CMDLEN_SHIFT 0
+#define DPAUX_DP_AUXCTL_CMDLEN_FIELD 0xff
+#define DPAUX_DP_AUXCTL_CMD_SHIFT 12
+#define DPAUX_DP_AUXCTL_CMD_MASK (0xf << 12)
+#define DPAUX_DP_AUXCTL_CMD_I2CWR (0 << 12)
+#define DPAUX_DP_AUXCTL_CMD_I2CRD (1 << 12)
+#define DPAUX_DP_AUXCTL_CMD_I2CREQWSTAT(2 << 12)
+#define DPAUX_DP_AUXCTL_CMD_MOTWR (4 << 12)
+#define DPAUX_DP_AUXCTL_CMD_MOTRD (5 << 12)
+#define DPAUX_DP_AUXCTL_CMD_MOTREQWSTAT(6 << 12)
+#define DPAUX_DP_AUXCTL_CMD_AUXWR (8 << 12)
+#define DPAUX_DP_AUXCTL_CMD_AUXRD (9 << 12)
+#define DPAUX_DP_AUXCTL_TRANSACTREQ_SHIFT 16
+#define DPAUX_DP_AUXCTL_TRANSACTREQ_MASK (0x1 << 16)
+#define DPAUX_DP_AUXCTL_TRANSACTREQ_DONE (0 << 16)
+#define DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING(1 << 16)
+#define DPAUX_DP_AUXCTL_RST_SHIFT 31
+#define DPAUX_DP_AUXCTL_RST_DEASSERT (0 << 31)
+#define DPAUX_DP_AUXCTL_RST_ASSERT (1 << 31)
+#define DPAUX_DP_AUXSTAT 0x31
+#define DPAUX_DP_AUXSTAT_HPD_STATUS_SHIFT 28
+#define DPAUX_DP_AUXSTAT_HPD_STATUS_UNPLUG (0 << 28)
+#define DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED(1 << 28)
+#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_SHIFT20
+#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_MASK (0xf << 20)
+#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_IDLE (0 << 20)
+#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_SYNC (1 << 20)
+#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_START1 (2 << 20)
+#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_COMMAND (3 << 20)
+#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_ADDRESS (4 << 20)
+#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_LENGTH (5 << 20)
+#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_WRITE1 (6 << 20)
+#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_READ1(7 << 20)
+#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_GET_M(8 << 20)
+#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_STOP1(9 << 20)
+#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_STOP2(10 << 20)
+#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_REPLY(11 << 20)
+#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_CLEANUP (12 << 20)
+#define DPAUX_DP_AUXSTAT_REPLYTYPE_SHIFT 16
+#define DPAUX_DP_AUXSTAT_REPLYTYPE_MASK(0xf << 16)
+#define DPAUX_DP_AUXSTAT_REPLYTYPE_ACK (0 << 16)
+#define DPAUX_DP_AUXSTAT_REPLYTYPE_NACK(1 << 16)
+#define DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER (2 << 16)
+#define DPAUX_DP_AUXSTAT_REPLYTYPE_I2CNACK (4 << 16)
+#define DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER(8 << 16)
+#define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_SHIFT 11
+#define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_NOT_PENDING (0 << 11)
+#define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING (1 << 11)
+#define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_SHIFT 10
+#define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_NOT_PENDING(0 << 10)
+#define DPAUX_DP_A
[U-Boot] [PATCH v2 25/26] tegra: config: nyan-big: Enable LCD
Add the PMIC, LCD settings, PWM and also show the board info at the top of the LCD when starting up. Signed-off-by: Simon Glass --- Changes in v2: None configs/nyan-big_defconfig | 2 ++ include/configs/nyan-big.h | 13 + 2 files changed, 15 insertions(+) diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig index ec79b5b..41de8e6 100644 --- a/configs/nyan-big_defconfig +++ b/configs/nyan-big_defconfig @@ -3,3 +3,5 @@ +S:CONFIG_TEGRA124=y +S:CONFIG_TARGET_NYAN_BIG=y CONFIG_DEFAULT_DEVICE_TREE="tegra124-nyan-big" +CONFIG_DISPLAY_PORT=y +CONFIG_VIDEO_TEGRA124=y diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h index cf331ab..f46f8dc 100644 --- a/include/configs/nyan-big.h +++ b/include/configs/nyan-big.h @@ -22,6 +22,7 @@ #define CONFIG_SYS_NS16550_COM1NV_PA_APB_UARTA_BASE #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_DISPLAY_BOARDINFO_LATE /* I2C */ #define CONFIG_SYS_I2C_TEGRA @@ -39,6 +40,18 @@ #define CONFIG_SYS_MMC_ENV_PART2 #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) +#define CONFIG_I2C_EDID + +/* LCD support */ +#define CONFIG_LCD +#define CONFIG_PWM_TEGRA +#define CONFIG_AS3722_POWER +#define LCD_BPPLCD_COLOR16 +#define CONFIG_SYS_WHITE_ON_BLACK + +/* Align LCD to 1MB boundary */ +#define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE + /* SPI */ #define CONFIG_TEGRA114_SPI/* Compatible w/ Tegra114 SPI */ #define CONFIG_TEGRA114_SPI_CTRLS 6 -- 2.2.0.rc0.207.ga3a616c ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 22/26] tegra: video: Support serial output resource (SOR) on tegra124
The SOR is required for talking to eDP LCD panels. Add a driver for this
which will be used by the DisplayPort driver.
Signed-off-by: Simon Glass
---
Changes in v2: None
drivers/video/Makefile | 2 +
drivers/video/tegra124/Makefile | 7 +
drivers/video/tegra124/sor.c| 897 +++
drivers/video/tegra124/sor.h| 903
include/fdtdec.h| 3 +
lib/fdtdec.c| 3 +
6 files changed, 1815 insertions(+)
create mode 100644 drivers/video/tegra124/Makefile
create mode 100644 drivers/video/tegra124/sor.c
create mode 100644 drivers/video/tegra124/sor.h
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 8f83fdb..fc33a90 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -52,3 +52,5 @@ obj-$(CONFIG_VIDEO_VESA) += vesa_fb.o
obj-$(CONFIG_FORMIKE) += formike.o
obj-$(CONFIG_AM335X_LCD) += am335x-fb.o
obj-$(CONFIG_VIDEO_PARADE) += parade.o
+
+obj-${CONFIG_VIDEO_TEGRA124} += tegra124/
diff --git a/drivers/video/tegra124/Makefile b/drivers/video/tegra124/Makefile
new file mode 100644
index 000..9aa81a5
--- /dev/null
+++ b/drivers/video/tegra124/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2014 Google, Inc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += sor.o
diff --git a/drivers/video/tegra124/sor.c b/drivers/video/tegra124/sor.c
new file mode 100644
index 000..8d9204a
--- /dev/null
+++ b/drivers/video/tegra124/sor.c
@@ -0,0 +1,897 @@
+/*
+ * Copyright (c) 2011-2013, NVIDIA Corporation.
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "displayport.h"
+#include "sor.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DEBUG_SOR 0
+
+#define APBDEV_PMC_DPD_SAMPLE (0x20)
+#define APBDEV_PMC_DPD_SAMPLE_ON_DISABLE (0)
+#define APBDEV_PMC_DPD_SAMPLE_ON_ENABLE(1)
+#define APBDEV_PMC_SEL_DPD_TIM (0x1c8)
+#define APBDEV_PMC_SEL_DPD_TIM_SEL_DPD_TIM_DEFAULT (0x7f)
+#define APBDEV_PMC_IO_DPD2_REQ (0x1c0)
+#define APBDEV_PMC_IO_DPD2_REQ_LVDS_SHIFT (25)
+#define APBDEV_PMC_IO_DPD2_REQ_LVDS_OFF(0 << 25)
+#define APBDEV_PMC_IO_DPD2_REQ_LVDS_ON (1 << 25)
+#define APBDEV_PMC_IO_DPD2_REQ_CODE_SHIFT (30)
+#define APBDEV_PMC_IO_DPD2_REQ_CODE_DEFAULT_MASK(0x3 << 30)
+#define APBDEV_PMC_IO_DPD2_REQ_CODE_IDLE(0 << 30)
+#define APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_OFF (1 << 30)
+#define APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_ON (2 << 30)
+#define APBDEV_PMC_IO_DPD2_STATUS (0x1c4)
+#define APBDEV_PMC_IO_DPD2_STATUS_LVDS_SHIFT (25)
+#define APBDEV_PMC_IO_DPD2_STATUS_LVDS_OFF (0 << 25)
+#define APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON (1 << 25)
+
+static inline u32 tegra_sor_readl(struct tegra_dc_sor_data *sor, u32 reg)
+{
+ return readl((u32 *)sor->base + reg);
+}
+
+static inline void tegra_sor_writel(struct tegra_dc_sor_data *sor, u32 reg,
+ u32 val)
+{
+ writel(val, (u32 *)sor->base + reg);
+}
+
+static inline void tegra_sor_write_field(struct tegra_dc_sor_data *sor,
+ u32 reg, u32 mask, u32 val)
+{
+ u32 reg_val = tegra_sor_readl(sor, reg);
+ reg_val &= ~mask;
+ reg_val |= val;
+ tegra_sor_writel(sor, reg, reg_val);
+}
+
+static u32 tegra_dc_sor_poll_register(struct tegra_dc_sor_data *sor, u32 reg,
+ u32 mask, u32 exp_val,
+ u32 poll_interval_us, u32 timeout_us)
+{
+ u32 temp = timeout_us;
+ u32 reg_val = 0;
+
+ do {
+ udelay(poll_interval_us);
+ reg_val = tegra_sor_readl(sor, reg);
+ if (timeout_us > poll_interval_us)
+ timeout_us -= poll_interval_us;
+ else
+ break;
+ } while ((reg_val & mask) != exp_val);
+
+ if ((reg_val & mask) == exp_val)
+ return 0; /* success */
+ debug("sor_poll_register 0x%x: timeout, (reg_val)0x%08x & (mask)0x%08x
!= (exp_val)0x%08x\n",
+ reg, reg_val, mask, exp_val);
+
+ return temp;
+}
+
+int tegra_dc_sor_set_power_state(struct tegra_dc_sor_data *sor, int pu_pd)
+{
+ u32 reg_val;
+ u32 orig_val;
+
+ orig_val = tegra_sor_readl(sor, PWR);
+
+ reg_val = pu_pd ? PWR_NORMAL_STATE_PU :
+ PWR_NORMAL_STATE_PD; /* normal state only */
+
+ if (reg_val == orig_val)
+ return 0; /* No update needed */
+
+ reg_val |= PWR_SETTING_NEW_TRIGGER;
+ tegra_sor_writel(sor, PWR, reg_val);
+
+ /* Poll to confirm it is done */
+ if (tegra_dc_sor_poll_register(sor, PWR,
+ PWR_
Re: [U-Boot] [PATCH 2/9] sunxi: Move SPL s_init() code to board_init_f()
Hi Siarhei,
On 1 February 2015 at 09:45, Siarhei Siamashka
wrote:
> On Sun, 1 Feb 2015 09:29:53 -0700
> Simon Glass wrote:
>
>> Hi,
>>
>> On 30 January 2015 at 10:53, Siarhei Siamashka
>> wrote:
>> > On Mon, 29 Dec 2014 09:15:36 -0700
>> > Simon Glass wrote:
>> >
>> >> Hi Ian,
>> >>
>> >> On 28 December 2014 at 02:19, Ian Campbell wrote:
>> >> > On Tue, 2014-12-23 at 12:04 -0700, Simon Glass wrote:
>> >> >
>> >> >> +void board_init_f(ulong dummy)
>> >> >> +{
>> >> > [...]
>> >> >> + /* Clear the BSS. */
>> >> >> + memset(__bss_start, 0, __bss_end - __bss_start);
>> >> >> +
>> >> >> + board_init_r(NULL, 0);
>> >> >
>> >> > The previous (__weak) version of board_init_f also sets gd, which you've
>> >> > also removed from s_init here and not added back anywhere (indeed, this
>> >> > is the point...). But where is gd initialised now?
>> >>
>> >> It's still in start.S, I've just removed this duplicate.
>> >>
>> >> >
>> >> > The patch generally looks good, two quick questions: has it been tested
>> >> > in both FEL and regular mode, and has it been tested with a "legacy" as
>> >> > well as a driver model system? (I might be able to find time in a day or
>> >> > two to answer these myself, but for now I'll just ask).
>> >>
>> >> I haven't tried FEL, I only just heard of it in your email. I'll see
>> >> if I can figure out how to test that.
>> >
>> > Just like Ian suspected, this patch has messed up the FEL boot mode
>> > support.
>> >
>> > In a nutshell, FEL is a special USB protocol (accessible on a USB OTG
>> > connector), which is implemented by the boot ROM and activated by
>> > holding a special hardware button pressed and rebooting the device.
>> > FEL supports commands to read/write device RAM and execute code on
>> > the device. It is designed for device unbricking and firmware recovery.
>>
>> If I understand it correctly, this is the same function that is
>> available on Exynos5, Tegra, MX6 and probably others.
>>
>> >
>> > In particular, the FEL boot mode support is very useful for debugging
>> > u-boot and kernel problems on tablets (the SD card slot can be used
>> > for the UART console, while the system is booted over a micro-USB cable
>> > with the help of FEL):
>> > http://linux-sunxi.org/File:MSI_Primo81_and_MicroSD_breakout.jpg
>> >
>> > In u-boot it is used in the following way:
>> > 1. The SPL code is uploaded from the linux PC to the device SRAM via
>> > a FEL command (using the 'fel' program from sunxi-tools).
>> > 2. The SPL code is executed via a FEL command and expected to
>> > initialize the DRAM controller. The code is executed as a
>> > normal C or assembly function, which needs to return control
>> > back to the BROM code when it is done. Right now this
>> > function is s_init().
>>
>> Isn't this just another way of loading SPL then? What is so special /
>> different about FEL?
>
> I'm not very familiar with the other platforms, but the special part
> here is "needs to return control back to the BROM code when it is done".
>
> We are relying on the FEL USB protocol implementation, which is
> hardcoded in BROM. FEL is used to upload data over USB to the device
> memory. And FEL needs to be used twice. Once for uploading data to SRAM
> and running the SPL. And one more time for uploading the rest of the
> data to DRAM.
>
> As we naturally can't modify the Allwinner code in BROM, here u-boot
> needs to play according to the FEL rules and not the other way around.
>
> As I see it, an alternative solution would be to implement USB OTG
> support and the FEL protocol (or some other protocol) in the u-boot
> SPL and stop relying on BROM code for uploading data to DRAM. Until
> this is done, the sunxi FEL variant of SPL needs to return control to
> the BROM code nicely after it has initialized DRAM and abstain from
> doing anything else.
>
> I hope that this clarifies the situation.
Exynos calls back into its IROM also from SPL, when it sees that it is
in USB A-A mode. See arch/arm/cpu/armv7/exynos/spl_boot.c where you
will find a table of IROM entry points.
I think it is fine to use the BROM and FEL, I am just concerned that
we need to stop using gdata and make FEL fit within the existing SPL
sequence. We need to avoid an SOC-specific hack, and if such a hack is
needed, it should be localised to sunxi and not rely on gdata, etc.
When you say 'return back to BROM', what exactly is a 'return'? Does
it mean that you need to jump to a return address in one of the
registers, or something else? Can you point me to the code that does
this and instructions on how to use it? Then I could try it out and
try to understand it better.
>
>> > 3. As the DRAM is initialized and available now, the main u-boot
>> > binary is now uploaded to DRAM via FEL. Together with boot.scr,
>> > the kernel, the dtb file and optionally initramfs as needed.
>> > 4. The main u-boot binary is executed via a FEL command, but never
>> > returns back to BROM anymore.
>>
[U-Boot] [PATCH v2 14/26] tegra: clock: Add checking for invalid clock IDs
The get_pll() function can do the wrong thing if passed values that are
out of range. Add checks for this and add a function which can return
a 'simple' PLL. This can be defined by SoCs with their own clocks.
Signed-off-by: Simon Glass
---
Changes in v2: None
arch/arm/cpu/tegra-common/clock.c | 30 ++
arch/arm/include/asm/arch-tegra/clock.h | 3 +++
2 files changed, 29 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/tegra-common/clock.c
b/arch/arm/cpu/tegra-common/clock.c
index 11c7435..87c2950 100644
--- a/arch/arm/cpu/tegra-common/clock.c
+++ b/arch/arm/cpu/tegra-common/clock.c
@@ -80,9 +80,18 @@ static struct clk_pll *get_pll(enum clock_id clkid)
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
assert(clock_id_is_pll(clkid));
+ if (clkid >= (enum clock_id)TEGRA_CLK_PLLS) {
+ debug("%s: Invalid PLL\n", __func__);
+ return NULL;
+ }
return &clkrst->crc_pll[clkid];
}
+__weak struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid)
+{
+ return NULL;
+}
+
int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
u32 *divp, u32 *cpcon, u32 *lfcon)
{
@@ -109,7 +118,7 @@ unsigned long clock_start_pll(enum clock_id clkid, u32
divm, u32 divn,
u32 divp, u32 cpcon, u32 lfcon)
{
struct clk_pll *pll = get_pll(clkid);
- u32 data;
+ u32 misc_data, data;
/*
* We cheat by treating all PLL (except PLLU) in the same fashion.
@@ -118,8 +127,7 @@ unsigned long clock_start_pll(enum clock_id clkid, u32
divm, u32 divn,
* - DCCON is always 0, doesn't conflict
* - M,N, P of PLLP values are ignored for PLLP
*/
- data = (cpcon << PLL_CPCON_SHIFT) | (lfcon << PLL_LFCON_SHIFT);
- writel(data, &pll->pll_misc);
+ misc_data = (cpcon << PLL_CPCON_SHIFT) | (lfcon << PLL_LFCON_SHIFT);
data = (divm << PLL_DIVM_SHIFT) | (divn << PLL_DIVN_SHIFT) |
(0 << PLL_BYPASS_SHIFT) | (1 << PLL_ENABLE_SHIFT);
@@ -128,7 +136,19 @@ unsigned long clock_start_pll(enum clock_id clkid, u32
divm, u32 divn,
data |= divp << PLLU_VCO_FREQ_SHIFT;
else
data |= divp << PLL_DIVP_SHIFT;
- writel(data, &pll->pll_base);
+ if (pll) {
+ writel(misc_data, &pll->pll_misc);
+ writel(data, &pll->pll_base);
+ } else {
+ struct clk_pll_simple *pll = clock_get_simple_pll(clkid);
+
+ if (!pll) {
+ debug("%s: Uknown simple PLL %d\n", __func__, clkid);
+ return 0;
+ }
+ writel(misc_data, &pll->pll_misc);
+ writel(data, &pll->pll_base);
+ }
/* calculate the stable time */
return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US;
@@ -430,6 +450,8 @@ unsigned clock_get_rate(enum clock_id clkid)
return parent_rate;
pll = get_pll(clkid);
+ if (!pll)
+ return 0;
base = readl(&pll->pll_base);
/* Oh for bf_unpack()... */
diff --git a/arch/arm/include/asm/arch-tegra/clock.h
b/arch/arm/include/asm/arch-tegra/clock.h
index 9d8114c..a641a16 100644
--- a/arch/arm/include/asm/arch-tegra/clock.h
+++ b/arch/arm/include/asm/arch-tegra/clock.h
@@ -265,6 +265,9 @@ void clock_early_init(void);
/* Returns a pointer to the clock source register for a peripheral */
u32 *get_periph_source_reg(enum periph_id periph_id);
+/* Returns a pointer to the given 'simple' PLL */
+struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid);
+
/**
* Given a peripheral ID and the required source clock, this returns which
* value should be programmed into the source mux for that peripheral.
--
2.2.0.rc0.207.ga3a616c
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[U-Boot] [PATCH v2 10/26] tegra: Add support for setting up a as3722 PMIC
Add support for this PMIC which is used on some Tegra124 boards.
Signed-off-by: Simon Glass
---
Changes in v2: None
board/nvidia/common/board.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index 0a33bc5..18e1709 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -7,6 +7,7 @@
#include
#include
+#include
#include
#include
#include
@@ -39,6 +40,7 @@
#include
#endif
#include
+#include
#include
#include
#include "emc.h"
@@ -144,6 +146,11 @@ int board_init(void)
debug("Memory controller init failed: %d\n", err);
# endif
# endif /* CONFIG_TEGRA_PMU */
+#ifdef CONFIG_AS3722_POWER
+ err = as3722_init(NULL);
+ if (err && err != -ENODEV)
+ return err;
+#endif
#endif /* CONFIG_SYS_I2C_TEGRA */
#ifdef CONFIG_USB_EHCI_TEGRA
--
2.2.0.rc0.207.ga3a616c
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[U-Boot] [PATCH v2 24/26] tegra: video: support eDP displays on Tegra124 devices
Connect up the clocks and the eDP driver to make these displays work with
Tegra124-based devices.
Signed-off-by: Simon Glass
---
Changes in v2:
- Rebase on top of u-boot-dm
arch/arm/include/asm/arch-tegra124/display.h | 58 +
drivers/video/Kconfig| 8 +
drivers/video/tegra124/Makefile | 2 +
drivers/video/tegra124/display.c | 358 +++
drivers/video/tegra124/tegra124-lcd.c| 94 +++
5 files changed, 520 insertions(+)
create mode 100644 arch/arm/include/asm/arch-tegra124/display.h
create mode 100644 drivers/video/tegra124/display.c
create mode 100644 drivers/video/tegra124/tegra124-lcd.c
diff --git a/arch/arm/include/asm/arch-tegra124/display.h
b/arch/arm/include/asm/arch-tegra124/display.h
new file mode 100644
index 000..ca6644a
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra124/display.h
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2010
+ * NVIDIA Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_TEGRA_DISPLAY_H
+#define __ASM_ARCH_TEGRA_DISPLAY_H
+
+/**
+ * Register a new display based on device tree configuration.
+ *
+ * The frame buffer can be positioned by U-Boot or overriden by the fdt.
+ * You should pass in the U-Boot address here, and check the contents of
+ * struct fdt_disp_config to see what was actually chosen.
+ *
+ * @param blob Device tree blob
+ * @param default_lcd_base Default address of LCD frame buffer
+ * @return 0 if ok, -1 on error (unsupported bits per pixel)
+ */
+int tegra_display_probe(const void *blob, void *default_lcd_base);
+
+/**
+ * Return the current display configuration
+ *
+ * @return pointer to display configuration, or NULL if there is no valid
+ * config
+ */
+struct fdt_disp_config *tegra_display_get_config(void);
+
+/**
+ * Perform the next stage of the LCD init if it is time to do so.
+ *
+ * LCD init can be time-consuming because of the number of delays we need
+ * while waiting for the backlight power supply, etc. This function can
+ * be called at various times during U-Boot operation to advance the
+ * initialization of the LCD to the next stage if sufficient time has
+ * passed since the last stage. It keeps track of what stage it is up to
+ * and the time that it is permitted to move to the next stage.
+ *
+ * The final call should have wait=1 to complete the init.
+ *
+ * @param blob fdt blob containing LCD information
+ * @param wait 1 to wait until all init is complete, and then return
+ * 0 to return immediately, potentially doing nothing if it is
+ * not yet time for the next init.
+ */
+int tegra_lcd_check_next_stage(const void *blob, int wait);
+
+/**
+ * Set up the maximum LCD size so we can size the frame buffer.
+ *
+ * @param blob fdt blob containing LCD information
+ */
+void tegra_lcd_early_init(const void *blob);
+
+#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 62af63a..2544301 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -95,3 +95,11 @@ config DISPLAY_PORT
eDP (Embedded DisplayPort) is a standard widely used in laptops
to drive LCD panels. This framework provides support for enabling
these displays where supported by the video hardware.
+
+config VIDEO_TEGRA124
+ bool "Enable video support on Tegra124"
+ help
+ Tegra124 supports many video output options including eDP and
+ HDMI. At present only eDP is supported by U-Boot. This option
+ enables this support which can be used on devices which
+ have an eDP display connected.
diff --git a/drivers/video/tegra124/Makefile b/drivers/video/tegra124/Makefile
index 7e08ee9..52eedb0 100644
--- a/drivers/video/tegra124/Makefile
+++ b/drivers/video/tegra124/Makefile
@@ -4,5 +4,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
+obj-y += display.o
obj-y += dp.o
obj-y += sor.o
+obj-y += tegra124-lcd.o
diff --git a/drivers/video/tegra124/display.c b/drivers/video/tegra124/display.c
new file mode 100644
index 000..d36a6a8
--- /dev/null
+++ b/drivers/video/tegra124/display.c
@@ -0,0 +1,358 @@
+/*
+ * Copyright 2014 Google Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Extracted from Chromium coreboot commit 3f59b13d
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "displayport.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* return in 1000ths of a Hertz */
+static int tegra_dc_calc_refresh(const struct display_timing *timing)
+{
+ int h_total, v_total, refresh;
+ int pclk = timing->pixelclock.typ;
+
+ h_total = timing->hactive.typ + timing->hfront_porch.typ +
+ timing->hback_porch.typ + timing->hsync_len.typ;
+ v_total = timing->vactive.typ + timing->vfront_porch.typ +
+ timing->vback_p
[U-Boot] [PATCH v2 18/26] video: Add drm_dp_helper.h
This file (from Linux 3.17) provides defines for display port. Use it so that our naming is consistent with Linux. Signed-off-by: Simon Glass --- Changes in v2: None include/linux/drm_dp_helper.h | 405 ++ 1 file changed, 405 insertions(+) create mode 100644 include/linux/drm_dp_helper.h diff --git a/include/linux/drm_dp_helper.h b/include/linux/drm_dp_helper.h new file mode 100644 index 000..86b06e1 --- /dev/null +++ b/include/linux/drm_dp_helper.h @@ -0,0 +1,405 @@ +/* + * Copyright © 2008 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ + +#ifndef _DRM_DP_HELPER_H_ +#define _DRM_DP_HELPER_H_ + +/* + * Unless otherwise noted, all values are from the DP 1.1a spec. Note that + * DP and DPCD versions are independent. Differences from 1.0 are not noted, + * 1.0 devices basically don't exist in the wild. + * + * Abbreviations, in chronological order: + * + * eDP: Embedded DisplayPort version 1 + * DPI: DisplayPort Interoperability Guideline v1.1a + * 1.2: DisplayPort 1.2 + * MST: Multistream Transport - part of DP 1.2a + * + * 1.2 formally includes both eDP and DPI definitions. + */ + +#define DP_AUX_I2C_WRITE 0x0 +#define DP_AUX_I2C_READ0x1 +#define DP_AUX_I2C_STATUS 0x2 +#define DP_AUX_I2C_MOT 0x4 +#define DP_AUX_NATIVE_WRITE0x8 +#define DP_AUX_NATIVE_READ 0x9 + +#define DP_AUX_NATIVE_REPLY_ACK(0x0 << 0) +#define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0) +#define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0) +#define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0) + +#define DP_AUX_I2C_REPLY_ACK (0x0 << 2) +#define DP_AUX_I2C_REPLY_NACK (0x1 << 2) +#define DP_AUX_I2C_REPLY_DEFER (0x2 << 2) +#define DP_AUX_I2C_REPLY_MASK (0x3 << 2) + +/* AUX CH addresses */ +/* DPCD */ +#define DP_DPCD_REV 0x000 + +#define DP_MAX_LINK_RATE0x001 + +#define DP_MAX_LANE_COUNT 0x002 +# define DP_MAX_LANE_COUNT_MASK0x1f +# define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */ +# define DP_ENHANCED_FRAME_CAP (1 << 7) + +#define DP_MAX_DOWNSPREAD 0x003 +# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) + +#define DP_NORP 0x004 + +#define DP_DOWNSTREAMPORT_PRESENT 0x005 +# define DP_DWN_STRM_PORT_PRESENT (1 << 0) +# define DP_DWN_STRM_PORT_TYPE_MASK 0x06 +# define DP_DWN_STRM_PORT_TYPE_DP (0 << 1) +# define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1) +# define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1) +# define DP_DWN_STRM_PORT_TYPE_OTHER(3 << 1) +# define DP_FORMAT_CONVERSION (1 << 3) +# define DP_DETAILED_CAP_INFO_AVAILABLE(1 << 4) /* DPI */ + +#define DP_MAIN_LINK_CHANNEL_CODING 0x006 + +#define DP_DOWN_STREAM_PORT_COUNT 0x007 +# define DP_PORT_COUNT_MASK0x0f +# define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */ +# define DP_OUI_SUPPORT(1 << 7) + +#define DP_I2C_SPEED_CAP 0x00c/* DPI */ +# define DP_I2C_SPEED_1K 0x01 +# define DP_I2C_SPEED_5K 0x02 +# define DP_I2C_SPEED_10K 0x04 +# define DP_I2C_SPEED_100K 0x08 +# define DP_I2C_SPEED_400K 0x10 +# define DP_I2C_SPEED_1M 0x20 + +#define DP_EDP_CONFIGURATION_CAP0x00d /* XXX 1.2? */ +#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */ + +/* Multiple stream transport */ +#define DP_FAUX_CAP0x020 /* 1.2 */ +# define DP_FAUX_CAP_1 (1 << 0) + +#define DP_MSTM_CAP0x021 /* 1.2 */ +# d
[U-Boot] [PATCH v2 13/26] tegra: config: Use CONFIG_LCD to detect LCD presence
Instead of CONFIG_VIDEO_TEGRA, use CONFIG_LCD to determine whether an LCD is present. Tegra124 uses a different driver. Signed-off-by: Simon Glass --- Changes in v2: None include/configs/tegra-common-post.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index c3ad8be..46a155d 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -34,7 +34,7 @@ #define STDIN_KBD_USB "" #endif -#ifdef CONFIG_VIDEO_TEGRA +#ifdef CONFIG_LCD #define STDOUT_LCD ",lcd" #else #define STDOUT_LCD "" -- 2.2.0.rc0.207.ga3a616c ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 02/13] lcd: split configuration_get_cmap
Hi Simon,
On 01/31/2015 02:24 AM, Simon Glass wrote:
Hi Nikita,
On 29 January 2015 at 04:21, Nikita Kiryanov wrote:
configuration_get_cmap() is multiple platform specific functions stuffed into
one function. Split it into multiple versions, and move each version to the
appropriate driver to reduce the #ifdef complexity.
Signed-off-by: Nikita Kiryanov
Cc: Bo Shen
Cc: Simon Glass
Cc: Anatolij Gustschin
---
common/lcd.c | 19 ---
drivers/video/atmel_hlcdfb.c | 13 +
drivers/video/atmel_lcdfb.c | 5 +
drivers/video/exynos_fb.c| 9 +
drivers/video/mpc8xx_lcd.c | 7 +++
drivers/video/pxa_lcd.c | 6 ++
include/lcd.h| 9 +
7 files changed, 49 insertions(+), 19 deletions(-)
Reviewed-by: Simon Glass
See suggestion below.
[snip]
diff --git a/include/lcd.h b/include/lcd.h
index fbba6a2..838f645 100644
--- a/include/lcd.h
+++ b/include/lcd.h
@@ -42,13 +42,17 @@ void lcd_set_flush_dcache(int flush);
#if defined CONFIG_MPC823
#include
+ushort *configuration_get_cmap(void);
#elif defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \
defined CONFIG_CPU_MONAHANS
#include
+ushort *configuration_get_cmap(void);
#elif defined(CONFIG_ATMEL_LCD) || defined(CONFIG_ATMEL_HLCD)
#include
+ushort *configuration_get_cmap(void);
#elif defined(CONFIG_EXYNOS_FB)
#include
+ushort *configuration_get_cmap(void);
#else
typedef struct vidinfo {
ushort vl_col; /* Number of columns (i.e. 160) */
@@ -60,6 +64,11 @@ typedef struct vidinfo {
void*priv; /* Pointer to driver-specific data */
} vidinfo_t;
+
+static inline ushort *configuration_get_cmap(void)
+{
+ return panel_info.cmap;
+}
#endif
I'd argue for dropping the inline version and just having the same
prototype in each case.
Are you suggesting something along the lines of:
static ushort *configuration_get_cmap(void)
{
return panel_info.cmap;
}
#endif
ushort *configuration_get_cmap(void);
?
This is something I considered while preparing this, but I was under the
impression
that this isn't well defined by the standard. However, I actually have
confirmation
now that it is in fact defined behavior[1], so I will submit a V2 for this
(even though
I expect all of the above to disappear from lcd.h in the next refactor series).
[1]
http://stackoverflow.com/questions/28264874/non-static-function-prototype-follows-static-function-declaration
Regards,
Simon
--
Regards,
Nikita Kiryanov
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[U-Boot] [PATCH v2 15/26] tegra: clock: Split the clock source code into a separate function
Create a function which sets the source clock for a peripheral, given
the number of mux bits to adjust. This can then be used more generally.
For now, don't export it.
Signed-off-by: Simon Glass
---
Changes in v2: None
arch/arm/cpu/tegra-common/clock.c | 51 +++--
arch/arm/include/asm/arch-tegra/clock.h | 11 +++
2 files changed, 40 insertions(+), 22 deletions(-)
diff --git a/arch/arm/cpu/tegra-common/clock.c
b/arch/arm/cpu/tegra-common/clock.c
index 87c2950..495cde3 100644
--- a/arch/arm/cpu/tegra-common/clock.c
+++ b/arch/arm/cpu/tegra-common/clock.c
@@ -171,12 +171,37 @@ void clock_ll_set_source_divisor(enum periph_id
periph_id, unsigned source,
writel(value, reg);
}
-void clock_ll_set_source(enum periph_id periph_id, unsigned source)
+int clock_ll_set_source_bits(enum periph_id periph_id, int mux_bits,
+unsigned source)
{
u32 *reg = get_periph_source_reg(periph_id);
- clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
- source << OUT_CLK_SOURCE_31_30_SHIFT);
+ switch (mux_bits) {
+ case MASK_BITS_31_30:
+ clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
+ source << OUT_CLK_SOURCE_31_30_SHIFT);
+ break;
+
+ case MASK_BITS_31_29:
+ clrsetbits_le32(reg, OUT_CLK_SOURCE_31_29_MASK,
+ source << OUT_CLK_SOURCE_31_29_SHIFT);
+ break;
+
+ case MASK_BITS_31_28:
+ clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK,
+ source << OUT_CLK_SOURCE_31_28_SHIFT);
+ break;
+
+ default:
+ return -1;
+ }
+
+ return 0;
+}
+
+void clock_ll_set_source(enum periph_id periph_id, unsigned source)
+{
+ clock_ll_set_source_bits(periph_id, MASK_BITS_31_30, source);
}
/**
@@ -325,25 +350,7 @@ static int adjust_periph_pll(enum periph_id periph_id, int
source,
if (source < 0)
return -1;
- switch (mux_bits) {
- case MASK_BITS_31_30:
- clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
- source << OUT_CLK_SOURCE_31_30_SHIFT);
- break;
-
- case MASK_BITS_31_29:
- clrsetbits_le32(reg, OUT_CLK_SOURCE_31_29_MASK,
- source << OUT_CLK_SOURCE_31_29_SHIFT);
- break;
-
- case MASK_BITS_31_28:
- clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK,
- source << OUT_CLK_SOURCE_31_28_SHIFT);
- break;
-
- default:
- return -1;
- }
+ clock_ll_set_source_bits(periph_id, mux_bits, source);
udelay(2);
return 0;
diff --git a/arch/arm/include/asm/arch-tegra/clock.h
b/arch/arm/include/asm/arch-tegra/clock.h
index a641a16..04011ae 100644
--- a/arch/arm/include/asm/arch-tegra/clock.h
+++ b/arch/arm/include/asm/arch-tegra/clock.h
@@ -156,6 +156,17 @@ void reset_cmplx_set_enable(int cpu, int which, int reset);
void clock_ll_set_source(enum periph_id periph_id, unsigned source);
/**
+ * This function is similar to clock_ll_set_source() except that it can be
+ * used for clocks with more than 2 mux bits.
+ *
+ * @param periph_idperipheral to adjust
+ * @param mux_bits number of mux bits for the clock
+ * @param source source clock (0-15 depending on mux_bits)
+ */
+int clock_ll_set_source_bits(enum periph_id periph_id, int mux_bits,
+unsigned source);
+
+/**
* Set the source and divisor for a peripheral clock. This sets the
* clock rate. You need to look up the datasheet to see the meaning of the
* source parameter as it changes for each peripheral.
--
2.2.0.rc0.207.ga3a616c
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Re: [U-Boot] [PATCH 02/13] lcd: split configuration_get_cmap
Hi Nikita,
On 1 February 2015 at 10:02, Nikita Kiryanov wrote:
> Hi Simon,
>
>
> On 01/31/2015 02:24 AM, Simon Glass wrote:
>>
>> Hi Nikita,
>>
>> On 29 January 2015 at 04:21, Nikita Kiryanov
>> wrote:
>>>
>>> configuration_get_cmap() is multiple platform specific functions stuffed
>>> into
>>> one function. Split it into multiple versions, and move each version to
>>> the
>>> appropriate driver to reduce the #ifdef complexity.
>>>
>>> Signed-off-by: Nikita Kiryanov
>>> Cc: Bo Shen
>>> Cc: Simon Glass
>>> Cc: Anatolij Gustschin
>>> ---
>>> common/lcd.c | 19 ---
>>> drivers/video/atmel_hlcdfb.c | 13 +
>>> drivers/video/atmel_lcdfb.c | 5 +
>>> drivers/video/exynos_fb.c| 9 +
>>> drivers/video/mpc8xx_lcd.c | 7 +++
>>> drivers/video/pxa_lcd.c | 6 ++
>>> include/lcd.h| 9 +
>>> 7 files changed, 49 insertions(+), 19 deletions(-)
>>
>>
>> Reviewed-by: Simon Glass
>>
>> See suggestion below.
>>
>> [snip]
>>>
>>> diff --git a/include/lcd.h b/include/lcd.h
>>> index fbba6a2..838f645 100644
>>> --- a/include/lcd.h
>>> +++ b/include/lcd.h
>>> @@ -42,13 +42,17 @@ void lcd_set_flush_dcache(int flush);
>>>
>>> #if defined CONFIG_MPC823
>>> #include
>>> +ushort *configuration_get_cmap(void);
>>> #elif defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \
>>> defined CONFIG_CPU_MONAHANS
>>> #include
>>> +ushort *configuration_get_cmap(void);
>>> #elif defined(CONFIG_ATMEL_LCD) || defined(CONFIG_ATMEL_HLCD)
>>> #include
>>> +ushort *configuration_get_cmap(void);
>>> #elif defined(CONFIG_EXYNOS_FB)
>>> #include
>>> +ushort *configuration_get_cmap(void);
>>> #else
>>> typedef struct vidinfo {
>>> ushort vl_col; /* Number of columns (i.e. 160) */
>>> @@ -60,6 +64,11 @@ typedef struct vidinfo {
>>>
>>> void*priv; /* Pointer to driver-specific data */
>>> } vidinfo_t;
>>> +
>>> +static inline ushort *configuration_get_cmap(void)
>>> +{
>>> + return panel_info.cmap;
>>> +}
>>> #endif
>>
>>
>> I'd argue for dropping the inline version and just having the same
>> prototype in each case.
>
>
> Are you suggesting something along the lines of:
>
> static ushort *configuration_get_cmap(void)
> {
>return panel_info.cmap;
> }
> #endif
>
> ushort *configuration_get_cmap(void);
>
> ?
>
> This is something I considered while preparing this, but I was under the
> impression
> that this isn't well defined by the standard. However, I actually have
> confirmation
> now that it is in fact defined behavior[1], so I will submit a V2 for this
> (even though
> I expect all of the above to disappear from lcd.h in the next refactor
> series).
>
> [1]
> http://stackoverflow.com/questions/28264874/non-static-function-prototype-follows-static-function-declaration
OK, although if you are planning to get rid of this code in the next
refactor, it's fine just as you have it in v1.
Regards,
Simon
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[U-Boot] Using u-boot for Powerpc P2041
Hi, I have a powerpc P2041 board which runs a u-boot successfuly when the u-boot is located at the 0xFFF8 address of the flash. I want to place the u-boot in 0xF000 address as 0xFFF8 will already be used by another software. I changed the address in the config file. Then I connect the board with a debugger and change the program counter (PC) to 0xF000. I expected to see the u-boot messages in the serial port but saw nothing. I thought this could be due to a tlb problem. So, I first added the 0xF000 address in the tlb range with another little program then jumped to the 0xF000, but the result is still failure. So, how come can I configure the u-boot so that it will be able to run at 0xF000 address. Any help is really appreciated. Thank you. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] armv8/vexpress64: make multientry conditional
hi Linus: > While the Freescale ARMv8 board LS2085A will enter U-Boot both > on a master and a secondary (slave) CPU, this is not the common > behaviour on ARMv8 platforms. The norm is that U-Boot is entered > from the master CPU only, while the other CPUs are kept in > WFI (wait for interrupt) state. According to fsl-lsch3 source code, Freescale LS2085A master cpu enter u-boot first, then it kick slaves up. That's right? There's ATF in Juno, so all slaves are held up. > > The code determining which CPU we are running on is using the > MPIDR register, but the definition of that register varies with > platform to some extent, and handling multi-cluster platforms > (such as the Juno) will become cumbersome. It is better to only > enable the multiple entry code on machines that actually need > it and disable it by default. > > Make the single entry default and add a special > ARMV8_MULTIENTRY KConfig option to be used by the > platforms that need multientry and set it for the LS2085A. > Delete all use of the CPU_RELEASE_ADDR from the Vexpress64 > boards as it is just totally unused and misleading, and > make it conditional in the generic start.S code. It's better to retain CPU_RELEASE_ADDR usage with CONFIG_ARMV8_MULTIENTRY. It still useful when ATF or other PSCI service do not exist. > > This makes the Juno platform start U-Boot properly. > > Signed-off-by: Linus Walleij > --- > ChangeLog v1->v2: > - Move configuration of ARMV8_MULTIENTRY over to Kconfig > as requested by Tom Rini. > > This patch applied on top of the other patch series send, > ending with > [PATCH 4/4] vexpress64: support the Juno Development Platform > Please apply it on top of these if the patch seems OK. > --- > arch/arm/Kconfig | 4 > arch/arm/cpu/armv8/Kconfig | 6 ++ > arch/arm/cpu/armv8/start.S | 8 > arch/arm/include/asm/macro.h | 8 > board/armltd/vexpress64/vexpress64.c | 6 -- > include/configs/vexpress_aemv8a.h| 8 > 6 files changed, 22 insertions(+), 18 deletions(-) > create mode 100644 arch/arm/cpu/armv8/Kconfig > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index 986b4c5d81db..75dd9bb60d6b 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -743,10 +743,12 @@ config TARGET_VEXPRESS64_JUNO > config TARGET_LS2085A_EMU > bool "Support ls2085a_emu" > select ARM64 > + select ARMV8_MULTIENTRY > > config TARGET_LS2085A_SIMU > bool "Support ls2085a_simu" > select ARM64 > + select ARMV8_MULTIENTRY > > config TARGET_LS1021AQDS > bool "Support ls1021aqds" > @@ -855,6 +857,8 @@ source "arch/arm/cpu/armv7/zynq/Kconfig" > > source "arch/arm/cpu/armv7/Kconfig" > > +source "arch/arm/cpu/armv8/Kconfig" > + > source "board/aristainetos/Kconfig" > source "board/BuR/kwb/Kconfig" > source "board/BuR/tseries/Kconfig" > diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig > new file mode 100644 > index ..4cd84b031114 > --- /dev/null > +++ b/arch/arm/cpu/armv8/Kconfig > @@ -0,0 +1,6 @@ > +if ARM64 > + > +config ARMV8_MULTIENTRY > +boolean "Enable multiple CPUs to enter into U-boot" > + > +endif > diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S > index 4b11aa4f2227..9b439f30b779 100644 > --- a/arch/arm/cpu/armv8/start.S > +++ b/arch/arm/cpu/armv8/start.S > @@ -77,6 +77,7 @@ reset: > /* Processor specific initialization */ > bl lowlevel_init > > +#ifdef CONFIG_ARMV8_MULTIENTRY > branch_if_master x0, x1, master_cpu > > /* > @@ -88,11 +89,10 @@ slave_cpu: > ldr x0, [x1] > cbz x0, slave_cpu > br x0 /* branch to the given address */ > - > - /* > - * Master CPU > - */ > master_cpu: > + /* On the master CPU */ > +#endif /* CONFIG_ARMV8_MULTIENTRY */ > + > bl _main > > /*---*/ > diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h > index 1c8c4251ee0c..3b3146ab2239 100644 > --- a/arch/arm/include/asm/macro.h > +++ b/arch/arm/include/asm/macro.h > @@ -78,6 +78,8 @@ lr .reqx30 > * choose processor with all zero affinity value as the master. > */ > .macro branch_if_slave, xreg, slave_label > +#ifdef CONFIG_ARMV8_MULTIENTRY > + /* NOTE: MPIDR handling will be erroneous on multi-cluster machines */ > mrs \xreg, mpidr_el1 > tst \xreg, #0xff/* Test Affinity 0 */ > b.ne\slave_label > @@ -90,6 +92,7 @@ lr .reqx30 > lsr \xreg, \xreg, #16 > tst \xreg, #0xff/* Test Affinity 3 */ > b.ne\slave_label > +#endif > .endm > > /* > @@ -97,12 +100,17 @@ lr .reqx30 > * choose processor with all zero affinity value as the master. > */ > .macro branch_if_master, xreg1, xreg2, master_label > +#ifdef CONFIG_ARMV8_M
[U-Boot] [RFC PATCH] ARM: Merge v7 and v8 outer cache operations
From: David Feng
Armv7 and Armv8 allow outer cache exist, it is outside of the architecture
defined cache hierarchy and can not be manipulated by architecture defined
instructions. It's processor specific.
This patch merge v7_outer_cache_* and v8 l3_cache_*.
Signed-off-by: David Feng
---
arch/arm/cpu/armv7/cache_v7.c| 22 +++---
arch/arm/cpu/armv7/cpu.c |2 +-
arch/arm/cpu/armv7/exynos/soc.c |2 +-
arch/arm/cpu/armv7/mx6/soc.c |4 ++--
arch/arm/cpu/armv7/omap3/board.c |2 +-
arch/arm/cpu/armv7/omap4/hwinit.c|4 ++--
arch/arm/cpu/armv7/s5pc1xx/cache.c |4 ++--
arch/arm/cpu/armv7/uniphier/cache_uniphier.c | 14 +++---
arch/arm/cpu/armv8/cache_v8.c| 21 -
arch/arm/cpu/armv8/fsl-lsch3/cpu.c |2 +-
arch/arm/include/asm/armv7.h |7 ---
arch/arm/include/asm/cache.h |7 +++
arch/arm/include/asm/system.h|2 --
arch/arm/lib/cache-pl310.c | 12 ++--
14 files changed, 57 insertions(+), 48 deletions(-)
diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
index 0f9d837..7d4d5d3 100644
--- a/arch/arm/cpu/armv7/cache_v7.c
+++ b/arch/arm/cpu/armv7/cache_v7.c
@@ -237,7 +237,7 @@ void invalidate_dcache_all(void)
{
v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL);
- v7_outer_cache_inval_all();
+ outer_cache_inval_all();
}
/*
@@ -248,7 +248,7 @@ void flush_dcache_all(void)
{
v7_maint_dcache_all(ARMV7_DCACHE_CLEAN_INVAL_ALL);
- v7_outer_cache_flush_all();
+ outer_cache_flush_all();
}
/*
@@ -259,7 +259,7 @@ void invalidate_dcache_range(unsigned long start, unsigned
long stop)
{
v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE);
- v7_outer_cache_inval_range(start, stop);
+ outer_cache_inval_range(start, stop);
}
/*
@@ -271,12 +271,12 @@ void flush_dcache_range(unsigned long start, unsigned
long stop)
{
v7_dcache_maint_range(start, stop, ARMV7_DCACHE_CLEAN_INVAL_RANGE);
- v7_outer_cache_flush_range(start, stop);
+ outer_cache_flush_range(start, stop);
}
void arm_init_before_mmu(void)
{
- v7_outer_cache_enable();
+ outer_cache_enable();
invalidate_dcache_all();
v7_inval_tlb();
}
@@ -355,9 +355,9 @@ void invalidate_icache_all(void)
#endif
/* Stub implementations for outer cache operations */
-__weak void v7_outer_cache_enable(void) {}
-__weak void v7_outer_cache_disable(void) {}
-__weak void v7_outer_cache_flush_all(void) {}
-__weak void v7_outer_cache_inval_all(void) {}
-__weak void v7_outer_cache_flush_range(u32 start, u32 end) {}
-__weak void v7_outer_cache_inval_range(u32 start, u32 end) {}
+__weak void outer_cache_enable(void) {}
+__weak void outer_cache_disable(void) {}
+__weak void outer_cache_flush_all(void) {}
+__weak void outer_cache_inval_all(void) {}
+__weak void outer_cache_flush_range(unsigned long start, unsigned long end) {}
+__weak void outer_cache_inval_range(unsigned long start, unsigned long end) {}
diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c
index 01cdb7e..07ad549 100644
--- a/arch/arm/cpu/armv7/cpu.c
+++ b/arch/arm/cpu/armv7/cpu.c
@@ -47,7 +47,7 @@ int cleanup_before_linux(void)
* dcache_disable() in turn flushes the d-cache and disables MMU
*/
dcache_disable();
- v7_outer_cache_disable();
+ outer_cache_disable();
/*
* After D-cache is flushed and before it is disabled there may
diff --git a/arch/arm/cpu/armv7/exynos/soc.c b/arch/arm/cpu/armv7/exynos/soc.c
index 8c7d7d8..3813c6c 100644
--- a/arch/arm/cpu/armv7/exynos/soc.c
+++ b/arch/arm/cpu/armv7/exynos/soc.c
@@ -50,7 +50,7 @@ static void exynos5_set_l2cache_params(void)
/*
* Sets L2 cache related parameters before enabling data cache
*/
-void v7_outer_cache_enable(void)
+void outer_cache_enable(void)
{
if (cpu_is_exynos5())
exynos5_set_l2cache_params();
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 5f5f497..e3f0fdd 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -472,7 +472,7 @@ void imx_setup_hdmi(void)
#ifndef CONFIG_SYS_L2CACHE_OFF
#define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x0002
-void v7_outer_cache_enable(void)
+void outer_cache_enable(void)
{
struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
unsigned int val;
@@ -521,7 +521,7 @@ void v7_outer_cache_enable(void)
setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
}
-void v7_outer_cache_disable(void)
+void outer_cache_disable(void)
{
struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index 90d6ae7..d5e215d 100644
Re: [U-Boot] [PATCH v2 06/11] common/board_f: factor out reserve_stacks
Hi Andreas,
On 29 January 2015 at 16:07, Andreas Bießmann
wrote:
> Require each architecture to provide an arch_reserve_stacks() function to
> setup the required stacks for the architecture.
>
> Signed-off-by: Andreas Bießmann
> ---
> This patch is _not_ fully compile tested for all ppc/arm boards!
>
> Changes in v2:
> - new since v1
>
> Changes in v1: None
>
> arch/arm/lib/Makefile |1 +
> arch/arm/lib/stack.c | 44 +++
> arch/powerpc/lib/Makefile |1 +
> arch/powerpc/lib/stack.c | 33
> common/board_f.c | 46
> +
> include/common.h |9 +
> 6 files changed, 89 insertions(+), 45 deletions(-)
> create mode 100644 arch/arm/lib/stack.c
> create mode 100644 arch/powerpc/lib/stack.c
>
> diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
> index d74e4b8..da8ed72 100644
> --- a/arch/arm/lib/Makefile
> +++ b/arch/arm/lib/Makefile
> @@ -35,6 +35,7 @@ endif
> obj-$(CONFIG_SEMIHOSTING) += semihosting.o
>
> obj-y += sections.o
> +obj-y += stack.o
> ifdef CONFIG_ARM64
> obj-y += gic_64.o
> obj-y += interrupts_64.o
> diff --git a/arch/arm/lib/stack.c b/arch/arm/lib/stack.c
> new file mode 100644
> index 000..b1050a5
> --- /dev/null
> +++ b/arch/arm/lib/stack.c
> @@ -0,0 +1,44 @@
> +/*
> + * Copyright (c) 2015 Andreas Bießmann
> + *
> + * Copyright (c) 2011 The Chromium OS Authors.
> + * (C) Copyright 2002-2006
> + * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
> + *
> + * (C) Copyright 2002
> + * Sysgo Real-Time Solutions, GmbH
> + * Marius Groeger
> + *
> + * SPDX-License-Identifier:GPL-2.0+
> + */
> +#include
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int arch_reserve_stacks(void)
> +{
> +#ifdef CONFIG_SPL_BUILD
> + gd->start_addr_sp -= 128; /* leave 32 words for abort-stack */
> + gd->irq_sp = gd->start_addr_sp;
> +#else
> + /* setup stack pointer for exceptions */
> + gd->start_addr_sp -= 16;
> + gd->start_addr_sp &= ~0xf;
> + gd->irq_sp = gd->start_addr_sp;
> +
> +# if !defined(CONFIG_ARM64)
> +# ifdef CONFIG_USE_IRQ
> + gd->start_addr_sp -= (CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ);
> + debug("Reserving %zu Bytes for IRQ stack at: %08lx\n",
> + CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ, gd->start_addr_sp);
> +
> + /* 8-byte alignment for ARM ABI compliance */
> + gd->start_addr_sp &= ~0x07;
> +# endif
> + /* leave 3 words for abort-stack, plus 1 for alignment */
> + gd->start_addr_sp -= 16;
> +# endif
> +#endif
> +
> + return 0;
> +}
> diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile
> index 0f62982..05b22bb 100644
> --- a/arch/powerpc/lib/Makefile
> +++ b/arch/powerpc/lib/Makefile
> @@ -40,6 +40,7 @@ obj-y += extable.o
> obj-y += interrupts.o
> obj-$(CONFIG_CMD_KGDB) += kgdb.o
> obj-$(CONFIG_CMD_IDE) += ide.o
> +obj-y += stack.o
> obj-y += time.o
>
> # Don't include the MPC5xxx special memcpy into the
> diff --git a/arch/powerpc/lib/stack.c b/arch/powerpc/lib/stack.c
> new file mode 100644
> index 000..3a6c91a
> --- /dev/null
> +++ b/arch/powerpc/lib/stack.c
> @@ -0,0 +1,33 @@
> +/*
> + * Copyright (c) 2015 Andreas Bießmann
> + *
> + * Copyright (c) 2011 The Chromium OS Authors.
> + * (C) Copyright 2002-2006
> + * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
> + *
> + * (C) Copyright 2002
> + * Sysgo Real-Time Solutions, GmbH
> + * Marius Groeger
> + *
> + * SPDX-License-Identifier:GPL-2.0+
> + */
> +#include
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int arch_reserve_stacks(void)
> +{
> + ulong *s;
> +
> + /* setup stack pointer for exceptions */
> + gd->start_addr_sp -= 16;
> + gd->start_addr_sp &= ~0xf;
> + gd->irq_sp = gd->start_addr_sp;
> +
> + /* Clear initial stack frame */
> + s = (ulong *)gd->start_addr_sp;
> + *s = 0; /* Terminate back chain */
> + *++s = 0; /* NULL return address */
> +
> + return 0;
> +}
> diff --git a/common/board_f.c b/common/board_f.c
> index 215108b..03f1529 100644
> --- a/common/board_f.c
> +++ b/common/board_f.c
> @@ -573,50 +573,6 @@ static int reserve_fdt(void)
> return 0;
> }
>
> -static int reserve_stacks(void)
> -{
> -#ifdef CONFIG_SPL_BUILD
> -# ifdef CONFIG_ARM
> - gd->start_addr_sp -= 128; /* leave 32 words for abort-stack */
> - gd->irq_sp = gd->start_addr_sp;
> -# endif
> -#else
> -# ifdef CONFIG_PPC
> - ulong *s;
> -# endif
> -
> - /* setup stack pointer for exceptions */
> - gd->start_addr_sp -= 16;
> - gd->start_addr_sp &= ~0xf;
> - gd->irq_sp = gd->start_addr_sp;
> -
> - /*
> -* Handle architecture-specific things here
> -* TODO(s...@chromium.org): Perhaps create arch_reserve_stack()
> -* to handle this and put in arch/xxx/lib/stack.c
> -*/
> -# if defined(
Re: [U-Boot] [PATCH 12/14] microblaze: Move architecture to use generic board init
Hi Michal,
On 30 January 2015 at 03:13, Michal Simek wrote:
> Hi Simon,
>
> On 01/29/2015 04:45 PM, Simon Glass wrote:
>> Hi Michal,
>>
>>
>> On 29 January 2015 at 07:20, Michal Simek wrote:
>>> Hi Simon,
>>>
>>> On 01/29/2015 03:15 AM, Simon Glass wrote:
Hi Michal,
On 27 January 2015 at 08:20, Michal Simek wrote:
> Compile code with -fPIC to get GOT. Do not build SPL
> with fPIC because it increasing SPL size for nothing.
>
> Signed-off-by: Michal Simek
> ---
>
>>>
>>> ...
>>>
> -#if defined(CONFIG_MIPS) || defined(CONFIG_PPC)
> +#if defined(CONFIG_MIPS) || defined(CONFIG_PPC) ||
> defined(CONFIG_MICROBLAZE)
> static int init_func_ram(void)
> {
Can you use dram_init() instead?
>>>
>>> No problem will do it in v2.
>>>
>>> Where dram_init(void) should be declared?
>>> I see that others have it in arch header. Maybe better to have
>>> it in any shared location.
>>
>> Yes a shared location makes sense.
>
> I have sent patch for it. Please review.
>
>>
>>>
> --- a/common/board_r.c
> +++ b/common/board_r.c
> @@ -829,7 +829,7 @@ init_fnc_t init_sequence_r[] = {
> #if defined(CONFIG_ARM)
> initr_enable_interrupts,
> #endif
> -#ifdef CONFIG_X86
> +#if defined(CONFIG_X86) || defined(CONFIG_MICROBLAZE)
> timer_init, /* initialize timer */
> #endif
Could you use interrupt_init() immediately before?
>>>
>>> What do you mean by that?
>>> Do you want to do timer_init in interrupt_init()?
>>
>> Yes, then if we remove it from x86 also we can drop both #ifdefs. Do
>> you see any drawback with that?
>
> timer_init looks like standard function which is used by x86 (board_r), arm,
> mips, blackfin.
> (board_f)
>
> Based on board_r.c PPC is doing timer_init in cpu_init_r.
>
> For Microblaze my preference is to use this location because timer code is
> using
> interrupts which are initialized above.
>
> Adding timer_init to interrupt_init doesn't look right because then
> interrupt_init will hide
> one init step.
Fair enough, I agree they are different. One way or another we'll get
rid of the #ifdefs in those files one day...
Regards,
Simon
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[U-Boot] [PATCH 0/2] ARMv8: driver model enable
From: David Feng Currently serial_pl01x.c driver contain DM and non-DM mode, but it will access static varible in non-DM mode. So, u-boot using non-DM pl01x driver can not be placed in flash. This patch set enable pre-allocation malloc that is required by DM and enable DM in vexpress64 board. David Feng (2): ARMv8: enable pre-allocation malloc ARMv8: enable DM in vexpress64 board arch/arm/include/asm/config.h|4 arch/arm/lib/crt0_64.S | 13 +++-- board/armltd/vexpress64/vexpress64.c | 13 + include/configs/vexpress_aemv8a.h| 14 -- 4 files changed, 36 insertions(+), 8 deletions(-) -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] ARMv8: enable pre-allocation malloc
From: David Feng Allocate memory space for pre-allocation malloc and zero global data. This code is partly from crt0.S. Signed-off-by: David Feng --- arch/arm/include/asm/config.h |4 arch/arm/lib/crt0_64.S| 13 +++-- 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h index be80434..7a34a01 100644 --- a/arch/arm/include/asm/config.h +++ b/arch/arm/include/asm/config.h @@ -7,10 +7,6 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ -#ifdef __aarch64__ -#define CONFIG_SYS_GENERIC_GLOBAL_DATA -#endif - #define CONFIG_LMB #define CONFIG_SYS_BOOT_RAMDISK_HIGH diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S index 7756396..1654011 100644 --- a/arch/arm/lib/crt0_64.S +++ b/arch/arm/lib/crt0_64.S @@ -62,9 +62,18 @@ ENTRY(_main) * Set up initial C runtime environment and call board_init_f(0). */ ldr x0, =(CONFIG_SYS_INIT_SP_ADDR) - sub x0, x0, #GD_SIZE/* allocate one GD above SP */ + sub x18, x0, #GD_SIZE /* allocate one GD above SP */ + bic x18, x18, #0x7 /* 8-byte alignment for GD */ +zero_gd: + sub x0, x0, #0x8 + str xzr, [x0] + cmp x0, x18 + b.gtzero_gd +#if defined(CONFIG_SYS_MALLOC_F_LEN) + sub x0, x18, #CONFIG_SYS_MALLOC_F_LEN + str x0, [x18, #GD_MALLOC_BASE] +#endif bic sp, x0, #0xf/* 16-byte alignment for ABI compliance */ - mov x18, sp /* GD is above SP */ mov x0, #0 bl board_init_f -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2] ARMv8: enable DM in vexpress64 board
From: David Feng
Signed-off-by: David Feng
---
board/armltd/vexpress64/vexpress64.c | 13 +
include/configs/vexpress_aemv8a.h| 14 --
2 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/board/armltd/vexpress64/vexpress64.c
b/board/armltd/vexpress64/vexpress64.c
index 5897318..4171c6e 100644
--- a/board/armltd/vexpress64/vexpress64.c
+++ b/board/armltd/vexpress64/vexpress64.c
@@ -12,9 +12,22 @@
#include
#include
#include
+#include
+#include
DECLARE_GLOBAL_DATA_PTR;
+static const struct pl01x_serial_platdata serial_platdata = {
+ .base = V2M_UART0,
+ .type = TYPE_PL011,
+ .clock = 2400 * 1000,
+};
+
+U_BOOT_DEVICE(vexpress_serials) = {
+ .name = "serial_pl01x",
+ .platdata = &serial_platdata,
+};
+
int board_init(void)
{
return 0;
diff --git a/include/configs/vexpress_aemv8a.h
b/include/configs/vexpress_aemv8a.h
index 027d78b..9b31c2d 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -8,6 +8,8 @@
#ifndef __VEXPRESS_AEMV8A_H
#define __VEXPRESS_AEMV8A_H
+#define CONFIG_DM
+
/* We use generic board for v8 Versatile Express */
#define CONFIG_SYS_GENERIC_BOARD
@@ -52,7 +54,6 @@
/* Flat Device Tree Definitions */
#define CONFIG_OF_LIBFDT
-
/* SMP Spin Table Definitions */
#ifdef CONFIG_BASE_FVP
#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f0)
@@ -132,6 +133,7 @@
#define CONFIG_SYS_MEMTEST_END (V2M_BASE + 0x8000)
/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_F_LEN0x2000
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20))
/* SMSC91C111 Ethernet Configuration */
@@ -139,11 +141,19 @@
#define CONFIG_SMC9_BASE (0x01A00)
/* PL011 Serial Configuration */
+#define CONFIG_BAUDRATE115200
+#ifdef CONFIG_DM
+#define CONFIG_DM_SERIAL
+#define CONFIG_PL01X_SERIAL
+#else
+#define CONFIG_SYS_SERIAL0 V2M_UART0
+#define CONFIG_SYS_SERIAL1 V2M_UART1
+#define CONFIG_CONS_INDEX 0
#define CONFIG_PL011_SERIAL
#define CONFIG_PL011_CLOCK 2400
#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
(void *)CONFIG_SYS_SERIAL1}
-#define CONFIG_CONS_INDEX 0
+#endif
#define CONFIG_BAUDRATE115200
#define CONFIG_SYS_SERIAL0 V2M_UART0
--
1.7.9.5
___
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U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC PATCH 0/21] ARM: start to move SoC code into arch/arm/mach-*
Hi Albert, On 1 February 2015 at 03:11, Albert ARIBAUD wrote: > Hello Simon, > > On Sat, 31 Jan 2015 20:20:06 -0700, Simon Glass > wrote: >> Hi Albert, >> >> On 31 January 2015 at 20:02, Albert ARIBAUD >> wrote: >> > Hello Masahiro, >> > >> > On Sun, 25 Jan 2015 15:11:02 +0900, Masahiro Yamada >> > wrote: >> >> >> >> This series can be applied on the current u-boot/master >> >> (commit 37b608a52dcb133) >> > >> > I'd rather not have all mach-* directories just below arch/arm/. Can't >> > they be created under arch/arm/soc/ instead? That would give a cleaner >> > structure IMO. >> >> It does save a level and I am forever typing cpu/armv7 to get what >> feels like nowhere... > > That can easily be solved (and tuned to personal taste) with CDPATH, eg. > > uboot@lilith:~/src/u-boot-arm (master)$ export CDPATH=arch/arm/cpu:arch/arm > uboot@lilith:~/src/u-boot-arm (master)$ cd armv > armv7/ armv8/ > uboot@lilith:~/src/u-boot-arm (master)$ cd armv7 > /home/uboot/src/u-boot-arm/arch/arm/cpu/armv7 > uboot@lilith:~/src/u-boot-arm/arch/arm/cpu/armv7 (master)$ > > (the u-boot-friendly value of CDPATH can put in a u-boot_env.sh file to > be sourced along with other u-boot related settings) I almost never cd into these directories. Mostly I have an editor/IDE open and I use File->Open to find the files. So this does not help me. But also I'd say that if the extra levels have no value then why do we have them at all? > >> this is what the kernel does and it does seem convenient. > > Well, to me it does not really -- I'm ok with loads of mach-* subdirs > under a commin parent dir, but what's the benefit of mixing mach-* dirs > with non-mach-* ones? If you look at tegra it has its code split between armv7 and arm720t. This makes it harder to understand what is going on if you are trying to follow the SPL/U-Boot early boot sequence on tegra. It is nicer to have all the tegra code under a tegra/ directory regardless of the particular ARM core. I think the ARM core name is a convenient way of splitting things up and has served us well. But now the common elements are more at the SOC level. Yes the idea of arch/arm/soc/mach-... is more pure from a hierarchical point of view, but arch/arm/mach-... would be my preference. I feel that arch/arm is underused now, and U-Boot is growing so we should try to 'balance' the source tree, making sure each level of the hierarchy justifies itself with enough files/subdirs, etc. $ ls arch/arm config.mk cpu dts imx-common include Kconfig Kconfig.debug lib Makefile mvebu-common Note that there are two 'common' directories in there already - see for example this commit: commit ea00e59be08989dae905076f4acf3eb297fce552 Author: Stefano Babic Date: Wed Sep 5 20:16:36 2012 + MX: set a common place to share code for Freescale i.MX Up now only MX5 and MX6 can share code, because they have a common source directory in cpu/armv7. Other not armv7 i.MX can profit of the same shared code. Move these files into a directory accessible for all, similar to plat-mxc in linux. One more point is that there is some benefit to using a similar approach to Linux so long as it is reasonably sensible - familiarity, less confusing when switching projects. If we follow this approach then I suspect that arch/arm/cpu will be only for the 'ARM core' code, not the vendor-specific SOC code built up around it. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC PATCH 0/21] ARM: start to move SoC code into arch/arm/mach-*
Hello Simon, On Sat, 31 Jan 2015 20:20:06 -0700, Simon Glass wrote: > Hi Albert, > > On 31 January 2015 at 20:02, Albert ARIBAUD wrote: > > Hello Masahiro, > > > > On Sun, 25 Jan 2015 15:11:02 +0900, Masahiro Yamada > > wrote: > >> > >> This series can be applied on the current u-boot/master > >> (commit 37b608a52dcb133) > > > > I'd rather not have all mach-* directories just below arch/arm/. Can't > > they be created under arch/arm/soc/ instead? That would give a cleaner > > structure IMO. > > It does save a level and I am forever typing cpu/armv7 to get what > feels like nowhere... That can easily be solved (and tuned to personal taste) with CDPATH, eg. uboot@lilith:~/src/u-boot-arm (master)$ export CDPATH=arch/arm/cpu:arch/arm uboot@lilith:~/src/u-boot-arm (master)$ cd armv armv7/ armv8/ uboot@lilith:~/src/u-boot-arm (master)$ cd armv7 /home/uboot/src/u-boot-arm/arch/arm/cpu/armv7 uboot@lilith:~/src/u-boot-arm/arch/arm/cpu/armv7 (master)$ (the u-boot-friendly value of CDPATH can put in a u-boot_env.sh file to be sourced along with other u-boot related settings) > this is what the kernel does and it does seem convenient. Well, to me it does not really -- I'm ok with loads of mach-* subdirs under a commin parent dir, but what's the benefit of mixing mach-* dirs with non-mach-* ones? > Regards, > Simon Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3] sunxi: Add Linksprite_pcDuino3_Nano board / defconfig
This is a low-cost Allwinner A20 board with Arduino-style GPIO headers; it features 1G RAM, 4G NAND flash, 1 micro-SD, 2 USB sockets, 1 micro USB socket for OTG and another for power in, HDMI, SATA, 5V power for SATA devices, gigabit Ethernet, an IR receiver, 3.5mm audio out and a MIPI camera connector. Like the BananaPi, this board needs GMAC_TX_DELAY set to 3 in order for GMAC to work reliably at gigabit speeds. For more details, see: http://linux-sunxi.org/LinkSprite_pcDuino3_Nano Changed in v3: - add CONFIG_GMAC_TX_DELAY=3, which corresponds to a patch in LinkSprite's A20 kernel; testing shows the performance is now much better at 1000M Signed-off-by: Adam Sampson --- board/sunxi/MAINTAINERS| 5 + configs/Linksprite_pcDuino3_Nano_defconfig | 11 +++ 2 files changed, 16 insertions(+) create mode 100644 configs/Linksprite_pcDuino3_Nano_defconfig diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 9050059..44f57ad 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -81,6 +81,11 @@ M: Zoltan Herpai S: Maintained F: configs/Linksprite_pcDuino_defconfig +LINKSPRITE-PCDUINO3-NANO BOARD +M: Adam Sampson +S: Maintained +F: configs/Linksprite_pcDuino3_Nano_defconfig + MARSBOARD-A10 BOARD M: Aleksei Mamlin S: Maintained diff --git a/configs/Linksprite_pcDuino3_Nano_defconfig b/configs/Linksprite_pcDuino3_Nano_defconfig new file mode 100644 index 000..4baba14 --- /dev/null +++ b/configs/Linksprite_pcDuino3_Nano_defconfig @@ -0,0 +1,11 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(2),USB_EHCI" +CONFIG_FDTFILE="sun7i-a20-pcduino3-nano.dtb" +CONFIG_GMAC_TX_DELAY=3 +CONFIG_USB1_VBUS_PIN="PH11" ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN7I=y ++S:CONFIG_DRAM_CLK=408 ++S:CONFIG_DRAM_ZQ=122 ++S:CONFIG_DRAM_EMR1=4 -- 2.2.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] ARMv8: bug fix of mmu setup and code optimization
From: David Feng
1. Fix a bug of mmu_setup that variable i and j should be
type long instead of int.
2. Give mmu_setup weak attribute so that other implementation
can redfine it.
3. A more common set_pgtable_section().
4. Give device memory PXN and UXN attribute. CPU may speculatively
prefetch instructions from device memory, but the IO subsystem of
some implementation may not support this operation. The two
attributes prevent this behavior.
Signed-off-by: David Feng
---
arch/arm/cpu/armv8/cache_v8.c | 73 +++-
arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 22 +--
arch/arm/include/asm/armv8/mmu.h | 71 +++
3 files changed, 95 insertions(+), 71 deletions(-)
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index e4415e8..023dd23 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -22,55 +22,74 @@ __weak void outer_cache_flush_range(unsigned long start,
unsigned long end) {}
__weak void outer_cache_inval_range(unsigned long start, unsigned long end) {}
#ifndef CONFIG_SYS_DCACHE_OFF
-void set_pgtable_section(u64 *page_table, u64 index, u64 section,
-u64 memory_type)
-{
- u64 value;
- value = section | PMD_TYPE_SECT | PMD_SECT_AF;
- value |= PMD_ATTRINDX(memory_type);
- page_table[index] = value;
+/* 42 bits virtual address */
+#define VA_BITS(42)
+
+/* 42 bits physical address */
+#define TCR_EL1_IPS_BITS TCR_EL1_IPS_BITS_42
+#define TCR_EL2_IPS_BITS TCR_EL2_IPS_BITS_42
+#define TCR_EL3_IPS_BITS TCR_EL3_IPS_BITS_42
+
+/* PTWs cacheable, inner/outer WBWA and inner-shareable */
+#define TCR_FLAGS (TCR_TG0_64K | \
+ TCR_SHARED_INNER | \
+ TCR_ORGN_WBWA | \
+ TCR_IRGN_WBWA | \
+ TCR_T0SZ(VA_BITS))
+
+void set_pgtable_section(u64 *page_table, u64 index, u64 output_address,
+u64 memory_type, u64 extra_flags)
+{
+ page_table[index] = output_address | PMD_TYPE_SECT | PMD_SECT_AF |
+ PMD_SECT_SHARED_INNER | PMD_ATTRINDX(memory_type) |
+ extra_flags;
}
/* to activate the MMU we need to set up virtual memory */
-static void mmu_setup(void)
+void __weak mmu_setup(void)
{
- int i, j, el;
+ int el;
+ u64 i, j, tcr;
bd_t *bd = gd->bd;
u64 *page_table = (u64 *)gd->arch.tlb_addr;
/* Setup an identity-mapping for all spaces */
for (i = 0; i < (PGTABLE_SIZE >> 3); i++) {
set_pgtable_section(page_table, i, i << SECTION_SHIFT,
- MT_DEVICE_NGNRNE);
+ MT_DEVICE_NGNRNE,
+ PMD_SECT_PXN | PMD_SECT_UXN);
+
}
- /* Setup an identity-mapping for all RAM space */
+ /*
+* Setup an identity-mapping for all RAM space.
+* The secure or non-secure memory access make sense
+* when u-boot running at el3 and is mostly implementation
+* specific.
+*/
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- ulong start = bd->bi_dram[i].start;
- ulong end = bd->bi_dram[i].start + bd->bi_dram[i].size;
+ u64 start = bd->bi_dram[i].start;
+ u64 end = bd->bi_dram[i].start + bd->bi_dram[i].size;
for (j = start >> SECTION_SHIFT;
j < end >> SECTION_SHIFT; j++) {
set_pgtable_section(page_table, j, j << SECTION_SHIFT,
- MT_NORMAL);
+ MT_NORMAL, PMD_SECT_NS);
}
}
/* load TTBR0 */
+ tcr = TCR_FLAGS;
el = current_el();
- if (el == 1) {
- set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
- TCR_FLAGS | TCR_EL1_IPS_BITS,
- MEMORY_ATTRIBUTES);
- } else if (el == 2) {
- set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
- TCR_FLAGS | TCR_EL2_IPS_BITS,
- MEMORY_ATTRIBUTES);
- } else {
- set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
- TCR_FLAGS | TCR_EL3_IPS_BITS,
- MEMORY_ATTRIBUTES);
- }
+ if (el == 1)
+ tcr |= TCR_EL1_IPS_BITS;
+ else if (el == 2)
+ tcr |= TCR_EL2_IPS_BITS;
+ else
+ tcr |= TCR_EL3_IPS_BITS;
+
+ set_ttbr_tcr_mair(el, gd->arch.tlb_addr, tcr, MEMORY_ATTRIBUTES);
+
/* enable the mmu */
set_sctlr(get_sctlr() | CR_M);
}
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
b/arch/arm/cpu/ar
Re: [U-Boot] [RFC PATCH 0/21] ARM: start to move SoC code into arch/arm/mach-*
Hello Masahiro, On Sun, 25 Jan 2015 15:11:02 +0900, Masahiro Yamada wrote: > > This series can be applied on the current u-boot/master > (commit 37b608a52dcb133) I'd rather not have all mach-* directories just below arch/arm/. Can't they be created under arch/arm/soc/ instead? That would give a cleaner structure IMO. Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC PATCH 0/21] ARM: start to move SoC code into arch/arm/mach-*
Hi Albert, On 31 January 2015 at 20:02, Albert ARIBAUD wrote: > Hello Masahiro, > > On Sun, 25 Jan 2015 15:11:02 +0900, Masahiro Yamada > wrote: >> >> This series can be applied on the current u-boot/master >> (commit 37b608a52dcb133) > > I'd rather not have all mach-* directories just below arch/arm/. Can't > they be created under arch/arm/soc/ instead? That would give a cleaner > structure IMO. It does save a level and I am forever typing cpu/armv7 to get what feels like nowhere...this is what the kernel does and it does seem convenient. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] arm: spl: Allow board_init_r() to run with a larger stack
Hello Simon, On Mon, 26 Jan 2015 08:34:21 -0700, Simon Glass wrote: > At present SPL uses a single stack, either CONFIG_SPL_STACK or > CONFIG_SYS_INIT_SP_ADDR. Since some SPL features (such as MMC and > environment) require a lot of stack, some boards set CONFIG_SPL_STACK to > point into SDRAM. They then set up SDRAM very early, before board_init_f(), > so that the larger stack can be used. > > This is an abuse of lowlevel_init(). That function should only be used for > essential start-up code which cannot be delayed. An example of a valid use is > when only part of the SPL code is visible/executable, and the SoC must be set > up so that board_init_f() can be reached. It should not be used for SDRAM > init, console init, etc. > > Add a CONFIG_SPL_STACK_R option, which allows the stack to be moved to a new > address before board_init_r() is called in SPL. > > The expected SPL flow (for CONFIG_SPL_FRAMEWORK) is now: > > Execution starts with start.S. Two main functions can be provided by the > board implementation. The purpose and limitations of each is described below. > After that, the common board_init_r() is called to perform the SPL task. > > lowlevel_init(): > - purpose: essential init to permit execution to reach board_init_f() > - no global_data, but there is a stack lowlevel_init() does not have a stack for all ARM CPUs, e.g. for arm926ejs it has none; and I don't see any code in this patch that provides one. If we need lowlevel_init to have a stack, then this stack should be set up in crt0.S and lowlevel_init called from there (which I would be fine with, btw). > - must not set up SDRAM or use console > - must only do the bare minimum to allow execution to continue to > board_init_f() > - this is almost never needed > - return normally from this function > > board_init_f(): > - purpose: set up the machine ready for running board_init_r(): > i.e. SDRAM and serial UART > - global_data is available > - preloader_console_init() can be called here in extremis > - stack is in SRAM > - should set up SDRAM, and anything needed to make the UART work > - these is no need to clear BSS, it will be done by crt0.S > - must return normally from this function (don't call board_init_r() > directly) > > Here the BSS is cleared. If CONFIG_SPL_STACK_R is defined, then at this point > the stack and global_data are relocated to below that address. > > board_init_r(): > - purpose: main execution, common code > - global_data is available > - SDRAM is available > - stack is optionally in SDRAM, if CONFIG_SPL_STACK_R is defined and > points into SDRAM > - preloader_console_init() can be called here - typically this is > done by defining CONFIG_SPL_BOARD_INIT and then supplying a > spl_board_init() function containing this call > - loads U-Boot or (in falcon mode) Linux > > Signed-off-by: Simon Glass > For version 1: > Acked-by: Albert ARIBAUD > Reviewed-by: Stefan Roese > Tested-by: Bo Shen > Acked-by: Bo Shen > Acked-by: Heiko Schocher > Tested-by: Heiko Schocher > --- > > Changes in v2: > - Move docs to top-level README file and expand them to cover U-Boot proper > - Add Kconfig settings > > Kconfig | 18 ++ > README | 68 > + > arch/arm/lib/crt0.S | 13 +++--- > common/spl/spl.c| 35 +++ > 4 files changed, 131 insertions(+), 3 deletions(-) > > diff --git a/Kconfig b/Kconfig > index 4157da3..8398bcd 100644 > --- a/Kconfig > +++ b/Kconfig > @@ -92,6 +92,24 @@ config SPL > help > If you want to build SPL as well as the normal image, say Y. > > +config CONFIG_SPL_STACK_R > + depends on SPL > + bool "Enable SDRAM location for SPL stack" > + help > + SPL starts off execution in SRAM and thus typically has only a small > + stack available. Since SPL sets up DRAM while in its board_init_f() > + function, it is possible for the stack to move there before > + board_init_r() is reached. This option enables a special SDRAM > + location for the SPL stack. U-Boot SPL switches to this after > + board_init_f() completes, and before board_init_r() starts. > + > +config CONFIG_SPL_STACK_R_ADDR > + depends on CONFIG_SPL_STACK_R > + hex "SDRAM location for SPL stack" > + help > + Specify the address in SDRAM for the SPL stack. This will be set up > + before board_init_r() is called. > + > config TPL > bool > depends on SPL && SUPPORT_TPL > diff --git a/README b/README > index fefa71c..7b48cda 100644 > --- a/README > +++ b/README > @@ -273,6 +273,74 @@ run some of U-Boot's tests. > See board/sandbox/README.sandbox for more details. > > > +Board Initialisation Flow: > +-- > + >
Re: [U-Boot] [PATCH 2/9] sunxi: Move SPL s_init() code to board_init_f()
On Sun, 1 Feb 2015 10:00:43 -0700
Simon Glass wrote:
> Hi Siarhei,
>
> On 1 February 2015 at 09:45, Siarhei Siamashka
> wrote:
> > On Sun, 1 Feb 2015 09:29:53 -0700
> > Simon Glass wrote:
> >
> >> Hi,
> >>
> >> On 30 January 2015 at 10:53, Siarhei Siamashka
> >> wrote:
> >> > On Mon, 29 Dec 2014 09:15:36 -0700
> >> > Simon Glass wrote:
> >> >
> >> >> Hi Ian,
> >> >>
> >> >> On 28 December 2014 at 02:19, Ian Campbell wrote:
> >> >> > On Tue, 2014-12-23 at 12:04 -0700, Simon Glass wrote:
> >> >> >
> >> >> >> +void board_init_f(ulong dummy)
> >> >> >> +{
> >> >> > [...]
> >> >> >> + /* Clear the BSS. */
> >> >> >> + memset(__bss_start, 0, __bss_end - __bss_start);
> >> >> >> +
> >> >> >> + board_init_r(NULL, 0);
> >> >> >
> >> >> > The previous (__weak) version of board_init_f also sets gd, which
> >> >> > you've
> >> >> > also removed from s_init here and not added back anywhere (indeed,
> >> >> > this
> >> >> > is the point...). But where is gd initialised now?
> >> >>
> >> >> It's still in start.S, I've just removed this duplicate.
> >> >>
> >> >> >
> >> >> > The patch generally looks good, two quick questions: has it been
> >> >> > tested
> >> >> > in both FEL and regular mode, and has it been tested with a "legacy"
> >> >> > as
> >> >> > well as a driver model system? (I might be able to find time in a day
> >> >> > or
> >> >> > two to answer these myself, but for now I'll just ask).
> >> >>
> >> >> I haven't tried FEL, I only just heard of it in your email. I'll see
> >> >> if I can figure out how to test that.
> >> >
> >> > Just like Ian suspected, this patch has messed up the FEL boot mode
> >> > support.
> >> >
> >> > In a nutshell, FEL is a special USB protocol (accessible on a USB OTG
> >> > connector), which is implemented by the boot ROM and activated by
> >> > holding a special hardware button pressed and rebooting the device.
> >> > FEL supports commands to read/write device RAM and execute code on
> >> > the device. It is designed for device unbricking and firmware recovery.
> >>
> >> If I understand it correctly, this is the same function that is
> >> available on Exynos5, Tegra, MX6 and probably others.
> >>
> >> >
> >> > In particular, the FEL boot mode support is very useful for debugging
> >> > u-boot and kernel problems on tablets (the SD card slot can be used
> >> > for the UART console, while the system is booted over a micro-USB cable
> >> > with the help of FEL):
> >> > http://linux-sunxi.org/File:MSI_Primo81_and_MicroSD_breakout.jpg
> >> >
> >> > In u-boot it is used in the following way:
> >> > 1. The SPL code is uploaded from the linux PC to the device SRAM via
> >> > a FEL command (using the 'fel' program from sunxi-tools).
> >> > 2. The SPL code is executed via a FEL command and expected to
> >> > initialize the DRAM controller. The code is executed as a
> >> > normal C or assembly function, which needs to return control
> >> > back to the BROM code when it is done. Right now this
> >> > function is s_init().
> >>
> >> Isn't this just another way of loading SPL then? What is so special /
> >> different about FEL?
> >
> > I'm not very familiar with the other platforms, but the special part
> > here is "needs to return control back to the BROM code when it is done".
> >
> > We are relying on the FEL USB protocol implementation, which is
> > hardcoded in BROM. FEL is used to upload data over USB to the device
> > memory. And FEL needs to be used twice. Once for uploading data to SRAM
> > and running the SPL. And one more time for uploading the rest of the
> > data to DRAM.
> >
> > As we naturally can't modify the Allwinner code in BROM, here u-boot
> > needs to play according to the FEL rules and not the other way around.
> >
> > As I see it, an alternative solution would be to implement USB OTG
> > support and the FEL protocol (or some other protocol) in the u-boot
> > SPL and stop relying on BROM code for uploading data to DRAM. Until
> > this is done, the sunxi FEL variant of SPL needs to return control to
> > the BROM code nicely after it has initialized DRAM and abstain from
> > doing anything else.
> >
> > I hope that this clarifies the situation.
>
> Exynos calls back into its IROM also from SPL, when it sees that it is
> in USB A-A mode. See arch/arm/cpu/armv7/exynos/spl_boot.c where you
> will find a table of IROM entry points.
I think that the difference is a matter of who calls whom. In the
case of Exynos, the SPL can call iROM functions. But in the case of
Allwinner, the whole SPL works as a kind of plugin, which is called
from the BROM code.
I'm not sure if the Allwinner BROM can be used in the same way as
the Exynos iROM, because the Allwinner BROM is not documented at all
as far as I know. Exynos probably has a better documentation.
> I think it is fine to use the BROM and FEL, I am just concerned that
> we need to stop using gdata and make FEL fit within the existing SPL
> sequence. We need to avoid an SOC-speci
Re: [U-Boot] [PATCH 1/4] sunxi: Make FEL mode usable again
On Sun, 1 Feb 2015 09:28:36 -0700
Simon Glass wrote:
> Hi,
>
> On 30 January 2015 at 04:58, Siarhei Siamashka
> wrote:
> > The commit f630974ccb3ce93e9607a3354e9acb266a8b7e95
> > 'sunxi: Move SPL s_init() code to board_init_f()'
> > broke the FEL boot mode.
> >
> > This patch moves the DRAM initialization back to s_init() and
> > introduces an assembly entry point for FEL in order to provide
> > guaranteed initialization of the gdata pointer (r9). The assembly
> > entry point is also needed to ensure that the SPL code starts
> > executing in ARM mode.
> >
> > Because the sunxi board_init_f() does not contain anything that
> > is not already done by the default board_init_f(), it is removed
> > too.
> >
> > Signed-off-by: Siarhei Siamashka
> > ---
> > arch/arm/cpu/armv7/sunxi/Makefile | 1 +
> > arch/arm/cpu/armv7/sunxi/board.c| 26 ++
> > arch/arm/cpu/armv7/sunxi/start_fel.S| 16
> > arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds | 3 ++-
> > 4 files changed, 29 insertions(+), 17 deletions(-)
> > create mode 100644 arch/arm/cpu/armv7/sunxi/start_fel.S
> >
> > diff --git a/arch/arm/cpu/armv7/sunxi/Makefile
> > b/arch/arm/cpu/armv7/sunxi/Makefile
> > index 48db744..e0d413d 100644
> > --- a/arch/arm/cpu/armv7/sunxi/Makefile
> > +++ b/arch/arm/cpu/armv7/sunxi/Makefile
> > @@ -40,5 +40,6 @@ obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o
> > obj-$(CONFIG_MACH_SUN8I) += dram_sun8i.o
> > ifdef CONFIG_SPL_FEL
> > obj-y += start.o
> > +extra-y+= start_fel.o
> > endif
> > endif
> > diff --git a/arch/arm/cpu/armv7/sunxi/board.c
> > b/arch/arm/cpu/armv7/sunxi/board.c
> > index 6e28bcd..ea6cb60 100644
> > --- a/arch/arm/cpu/armv7/sunxi/board.c
> > +++ b/arch/arm/cpu/armv7/sunxi/board.c
> > @@ -85,6 +85,16 @@ void s_init(void)
> > timer_init();
> > gpio_init();
> > i2c_init_board();
> > +
> > +#ifdef CONFIG_SPL_BUILD
> > + preloader_console_init();
>
> s_init() is called before we have global_data, so you can't use a console.
Oh, but somehow it just works for me.
> > +
> > +#ifdef CONFIG_SPL_I2C_SUPPORT
> > + /* Needed early by sunxi_board_init if PMU is enabled */
> > + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
> > +#endif
> > + sunxi_board_init();
> > +#endif
>
> Why do you need this code here?
The i2c_init() call is needed to initialize the PMIC as the comment
says. The PMIC is needed to set correct voltages, necessary for
the DRAM controller.
And the sunxi_board_init() initializes DRAM.
> Can it not go in board_init_f()?
Then we probably would need a special stripped down FEL variant of
board_init_f(), which makes the code a bit more messy.
> > }
> >
> > #ifdef CONFIG_SPL_BUILD
> > @@ -103,22 +113,6 @@ u32 spl_boot_mode(void)
> > {
> > return MMCSD_MODE_RAW;
> > }
> > -
> > -void board_init_f(ulong dummy)
> > -{
> > - preloader_console_init();
> > -
> > -#ifdef CONFIG_SPL_I2C_SUPPORT
> > - /* Needed early by sunxi_board_init if PMU is enabled */
> > - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
> > -#endif
> > - sunxi_board_init();
> > -
> > - /* Clear the BSS. */
> > - memset(__bss_start, 0, __bss_end - __bss_start);
> > -
> > - board_init_r(NULL, 0);
> > -}
> > #endif
> >
> > void reset_cpu(ulong addr)
> > diff --git a/arch/arm/cpu/armv7/sunxi/start_fel.S
> > b/arch/arm/cpu/armv7/sunxi/start_fel.S
> > new file mode 100644
> > index 000..e1c7cd4
> > --- /dev/null
> > +++ b/arch/arm/cpu/armv7/sunxi/start_fel.S
> > @@ -0,0 +1,16 @@
> > +/*
> > + * Entry point of the FEL mode SPL.
> > + *
> > + * Copyright (c) 2015 Siarhei Siamashka
> > + *
> > + * SPDX-License-Identifier:GPL-2.0+
> > + */
> > +
> > +#include
> > +#include
> > +#include
> > +
> > +ENTRY(_start_fel)
> > + ldr r9, =gdata
> > + b s_init
>
> No we don't want global data here, and need to get rid of gdata so we
> can use driver model, etc.
Appears that I need to educate myself on the global data vs. gdata
differences.
Using driver model in the sunxi SPL is a bit challenging because
we don't have abundant amounts of SRAM there:
http://linux-sunxi.org/SRAM_Controller
Without relying on SoC-variant specific SRAM sections, we have 32 KiB
for normal SPL, and only ~15 KiB for FEL SPL (the rest is used by the
BROM FEL code). And SRAM is very much needed for the other important
features.
So far I can see that the pointer to gdata is stored in the r9 register.
And gdata resides in the ".data" section, which means that it is
initialized to 0 automatically. And this works now, unless I'm
misunderstanding something.
I would be more than happy to fix it in a future proof way. However it
is very much desired to have a properly functioning FEL boot mode in
u-boot 2015.04 and IMHO a quick hack relying on the legacy gdata feature
might be not the worst possible option today.
> > +ENDPROC(_start_fel)
>
Re: [U-Boot] [PATCH 2/9] sunxi: Move SPL s_init() code to board_init_f()
Hi Siarhei,
On 1 February 2015 at 11:37, Siarhei Siamashka
wrote:
> On Sun, 1 Feb 2015 10:00:43 -0700
> Simon Glass wrote:
>
>> Hi Siarhei,
>>
>> On 1 February 2015 at 09:45, Siarhei Siamashka
>> wrote:
>> > On Sun, 1 Feb 2015 09:29:53 -0700
>> > Simon Glass wrote:
>> >
>> >> Hi,
>> >>
>> >> On 30 January 2015 at 10:53, Siarhei Siamashka
>> >> wrote:
>> >> > On Mon, 29 Dec 2014 09:15:36 -0700
>> >> > Simon Glass wrote:
>> >> >
>> >> >> Hi Ian,
>> >> >>
>> >> >> On 28 December 2014 at 02:19, Ian Campbell
wrote:
>> >> >> > On Tue, 2014-12-23 at 12:04 -0700, Simon Glass wrote:
>> >> >> >
>> >> >> >> +void board_init_f(ulong dummy)
>> >> >> >> +{
>> >> >> > [...]
>> >> >> >> + /* Clear the BSS. */
>> >> >> >> + memset(__bss_start, 0, __bss_end - __bss_start);
>> >> >> >> +
>> >> >> >> + board_init_r(NULL, 0);
>> >> >> >
>> >> >> > The previous (__weak) version of board_init_f also sets gd,
which you've
>> >> >> > also removed from s_init here and not added back anywhere
(indeed, this
>> >> >> > is the point...). But where is gd initialised now?
>> >> >>
>> >> >> It's still in start.S, I've just removed this duplicate.
>> >> >>
>> >> >> >
>> >> >> > The patch generally looks good, two quick questions: has it been
tested
>> >> >> > in both FEL and regular mode, and has it been tested with a
"legacy" as
>> >> >> > well as a driver model system? (I might be able to find time in
a day or
>> >> >> > two to answer these myself, but for now I'll just ask).
>> >> >>
>> >> >> I haven't tried FEL, I only just heard of it in your email. I'll
see
>> >> >> if I can figure out how to test that.
>> >> >
>> >> > Just like Ian suspected, this patch has messed up the FEL boot mode
>> >> > support.
>> >> >
>> >> > In a nutshell, FEL is a special USB protocol (accessible on a USB
OTG
>> >> > connector), which is implemented by the boot ROM and activated by
>> >> > holding a special hardware button pressed and rebooting the device.
>> >> > FEL supports commands to read/write device RAM and execute code on
>> >> > the device. It is designed for device unbricking and firmware
recovery.
>> >>
>> >> If I understand it correctly, this is the same function that is
>> >> available on Exynos5, Tegra, MX6 and probably others.
>> >>
>> >> >
>> >> > In particular, the FEL boot mode support is very useful for
debugging
>> >> > u-boot and kernel problems on tablets (the SD card slot can be used
>> >> > for the UART console, while the system is booted over a micro-USB
cable
>> >> > with the help of FEL):
>> >> > http://linux-sunxi.org/File:MSI_Primo81_and_MicroSD_breakout.jpg
>> >> >
>> >> > In u-boot it is used in the following way:
>> >> > 1. The SPL code is uploaded from the linux PC to the device SRAM via
>> >> > a FEL command (using the 'fel' program from sunxi-tools).
>> >> > 2. The SPL code is executed via a FEL command and expected to
>> >> > initialize the DRAM controller. The code is executed as a
>> >> > normal C or assembly function, which needs to return control
>> >> > back to the BROM code when it is done. Right now this
>> >> > function is s_init().
>> >>
>> >> Isn't this just another way of loading SPL then? What is so special /
>> >> different about FEL?
>> >
>> > I'm not very familiar with the other platforms, but the special part
>> > here is "needs to return control back to the BROM code when it is
done".
>> >
>> > We are relying on the FEL USB protocol implementation, which is
>> > hardcoded in BROM. FEL is used to upload data over USB to the device
>> > memory. And FEL needs to be used twice. Once for uploading data to SRAM
>> > and running the SPL. And one more time for uploading the rest of the
>> > data to DRAM.
>> >
>> > As we naturally can't modify the Allwinner code in BROM, here u-boot
>> > needs to play according to the FEL rules and not the other way around.
>> >
>> > As I see it, an alternative solution would be to implement USB OTG
>> > support and the FEL protocol (or some other protocol) in the u-boot
>> > SPL and stop relying on BROM code for uploading data to DRAM. Until
>> > this is done, the sunxi FEL variant of SPL needs to return control to
>> > the BROM code nicely after it has initialized DRAM and abstain from
>> > doing anything else.
>> >
>> > I hope that this clarifies the situation.
>>
>> Exynos calls back into its IROM also from SPL, when it sees that it is
>> in USB A-A mode. See arch/arm/cpu/armv7/exynos/spl_boot.c where you
>> will find a table of IROM entry points.
>
> I think that the difference is a matter of who calls whom. In the
> case of Exynos, the SPL can call iROM functions. But in the case of
> Allwinner, the whole SPL works as a kind of plugin, which is called
> from the BROM code.
>
> I'm not sure if the Allwinner BROM can be used in the same way as
> the Exynos iROM, because the Allwinner BROM is not documented at all
> as far as I know. Exynos probably has a better documentation.
>
>> I think it is fine to use the BROM and FEL, I am just concerned that
>> we need to stop
Re: [U-Boot] [PATCH 1/4] sunxi: Make FEL mode usable again
Hi Siarhei,
On 1 February 2015 at 11:48, Siarhei Siamashka
wrote:
> On Sun, 1 Feb 2015 09:28:36 -0700
> Simon Glass wrote:
>
>> Hi,
>>
>> On 30 January 2015 at 04:58, Siarhei Siamashka
>> wrote:
>> > The commit f630974ccb3ce93e9607a3354e9acb266a8b7e95
>> > 'sunxi: Move SPL s_init() code to board_init_f()'
>> > broke the FEL boot mode.
>> >
>> > This patch moves the DRAM initialization back to s_init() and
>> > introduces an assembly entry point for FEL in order to provide
>> > guaranteed initialization of the gdata pointer (r9). The assembly
>> > entry point is also needed to ensure that the SPL code starts
>> > executing in ARM mode.
>> >
>> > Because the sunxi board_init_f() does not contain anything that
>> > is not already done by the default board_init_f(), it is removed
>> > too.
>> >
>> > Signed-off-by: Siarhei Siamashka
>> > ---
>> > arch/arm/cpu/armv7/sunxi/Makefile | 1 +
>> > arch/arm/cpu/armv7/sunxi/board.c | 26 ++
>> > arch/arm/cpu/armv7/sunxi/start_fel.S | 16
>> > arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds | 3 ++-
>> > 4 files changed, 29 insertions(+), 17 deletions(-)
>> > create mode 100644 arch/arm/cpu/armv7/sunxi/start_fel.S
>> >
>> > diff --git a/arch/arm/cpu/armv7/sunxi/Makefile
b/arch/arm/cpu/armv7/sunxi/Makefile
>> > index 48db744..e0d413d 100644
>> > --- a/arch/arm/cpu/armv7/sunxi/Makefile
>> > +++ b/arch/arm/cpu/armv7/sunxi/Makefile
>> > @@ -40,5 +40,6 @@ obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o
>> > obj-$(CONFIG_MACH_SUN8I) += dram_sun8i.o
>> > ifdef CONFIG_SPL_FEL
>> > obj-y += start.o
>> > +extra-y += start_fel.o
>> > endif
>> > endif
>> > diff --git a/arch/arm/cpu/armv7/sunxi/board.c
b/arch/arm/cpu/armv7/sunxi/board.c
>> > index 6e28bcd..ea6cb60 100644
>> > --- a/arch/arm/cpu/armv7/sunxi/board.c
>> > +++ b/arch/arm/cpu/armv7/sunxi/board.c
>> > @@ -85,6 +85,16 @@ void s_init(void)
>> > timer_init();
>> > gpio_init();
>> > i2c_init_board();
>> > +
>> > +#ifdef CONFIG_SPL_BUILD
>> > + preloader_console_init();
>>
>> s_init() is called before we have global_data, so you can't use a
console.
>
> Oh, but somehow it just works for me.
I should have said that there *should* be no global_data at this point,
i.e. we need to drop the hacks that add this. In fact global_data should be
set up once in crt0.S and not before.
>
>> > +
>> > +#ifdef CONFIG_SPL_I2C_SUPPORT
>> > + /* Needed early by sunxi_board_init if PMU is enabled */
>> > + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
>> > +#endif
>> > + sunxi_board_init();
>> > +#endif
>>
>> Why do you need this code here?
>
> The i2c_init() call is needed to initialize the PMIC as the comment
> says. The PMIC is needed to set correct voltages, necessary for
> the DRAM controller.
>
> And the sunxi_board_init() initializes DRAM.
>
>> Can it not go in board_init_f()?
>
> Then we probably would need a special stripped down FEL variant of
> board_init_f(), which makes the code a bit more messy.
Yes I think it is well worth figuring out the really differences are
between an SPL that boots from board storage and one that boots from FEL.
For Exynos is it just a single switch() to select the boot source. For
Tegra it essentially nothing.
Exynos has a flag that tells SPL when it is booting from USB A-A. Does
sunxi?
>
>> > }
>> >
>> > #ifdef CONFIG_SPL_BUILD
>> > @@ -103,22 +113,6 @@ u32 spl_boot_mode(void)
>> > {
>> > return MMCSD_MODE_RAW;
>> > }
>> > -
>> > -void board_init_f(ulong dummy)
>> > -{
>> > - preloader_console_init();
>> > -
>> > -#ifdef CONFIG_SPL_I2C_SUPPORT
>> > - /* Needed early by sunxi_board_init if PMU is enabled */
>> > - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
>> > -#endif
>> > - sunxi_board_init();
>> > -
>> > - /* Clear the BSS. */
>> > - memset(__bss_start, 0, __bss_end - __bss_start);
>> > -
>> > - board_init_r(NULL, 0);
>> > -}
>> > #endif
>> >
>> > void reset_cpu(ulong addr)
>> > diff --git a/arch/arm/cpu/armv7/sunxi/start_fel.S
b/arch/arm/cpu/armv7/sunxi/start_fel.S
>> > new file mode 100644
>> > index 000..e1c7cd4
>> > --- /dev/null
>> > +++ b/arch/arm/cpu/armv7/sunxi/start_fel.S
>> > @@ -0,0 +1,16 @@
>> > +/*
>> > + * Entry point of the FEL mode SPL.
>> > + *
>> > + * Copyright (c) 2015 Siarhei Siamashka
>> > + *
>> > + * SPDX-License-Identifier: GPL-2.0+
>> > + */
>> > +
>> > +#include
>> > +#include
>> > +#include
>> > +
>> > +ENTRY(_start_fel)
>> > + ldr r9, =gdata
>> > + b s_init
>>
>> No we don't want global data here, and need to get rid of gdata so we
>> can use driver model, etc.
>
> Appears that I need to educate myself on the global data vs. gdata
> differences.
>
> Using driver model in the sunxi SPL is a bit challenging because
> we don't have abundant amounts of SRAM there:
> http://linux-sunxi.org/SRAM_Controller
> Without relying on SoC-variant specific SRAM sections, we have 32 KiB
> for normal SPL, and only ~15 KiB for FEL SPL (the rest is used by the
> BROM FEL code). And SRAM is very much needed for the other important
> f
Re: [U-Boot] [PATCH 1/4] sunxi: Make FEL mode usable again
On Sun, 1 Feb 2015 13:59:41 -0700
Simon Glass wrote:
> Hi Siarhei,
>
> On 1 February 2015 at 11:48, Siarhei Siamashka
> wrote:
> > On Sun, 1 Feb 2015 09:28:36 -0700
> > Simon Glass wrote:
> >
> >> Hi,
> >>
> >> On 30 January 2015 at 04:58, Siarhei Siamashka
> >> wrote:
> >> > The commit f630974ccb3ce93e9607a3354e9acb266a8b7e95
> >> > 'sunxi: Move SPL s_init() code to board_init_f()'
> >> > broke the FEL boot mode.
> >> >
> >> > This patch moves the DRAM initialization back to s_init() and
> >> > introduces an assembly entry point for FEL in order to provide
> >> > guaranteed initialization of the gdata pointer (r9). The assembly
> >> > entry point is also needed to ensure that the SPL code starts
> >> > executing in ARM mode.
> >> >
> >> > Because the sunxi board_init_f() does not contain anything that
> >> > is not already done by the default board_init_f(), it is removed
> >> > too.
> >> >
> >> > Signed-off-by: Siarhei Siamashka
> >> > ---
> >> > arch/arm/cpu/armv7/sunxi/Makefile | 1 +
> >> > arch/arm/cpu/armv7/sunxi/board.c | 26 ++
> >> > arch/arm/cpu/armv7/sunxi/start_fel.S | 16
> >> > arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds | 3 ++-
> >> > 4 files changed, 29 insertions(+), 17 deletions(-)
> >> > create mode 100644 arch/arm/cpu/armv7/sunxi/start_fel.S
> >> >
> >> > diff --git a/arch/arm/cpu/armv7/sunxi/Makefile
> b/arch/arm/cpu/armv7/sunxi/Makefile
> >> > index 48db744..e0d413d 100644
> >> > --- a/arch/arm/cpu/armv7/sunxi/Makefile
> >> > +++ b/arch/arm/cpu/armv7/sunxi/Makefile
> >> > @@ -40,5 +40,6 @@ obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o
> >> > obj-$(CONFIG_MACH_SUN8I) += dram_sun8i.o
> >> > ifdef CONFIG_SPL_FEL
> >> > obj-y += start.o
> >> > +extra-y += start_fel.o
> >> > endif
> >> > endif
> >> > diff --git a/arch/arm/cpu/armv7/sunxi/board.c
> b/arch/arm/cpu/armv7/sunxi/board.c
> >> > index 6e28bcd..ea6cb60 100644
> >> > --- a/arch/arm/cpu/armv7/sunxi/board.c
> >> > +++ b/arch/arm/cpu/armv7/sunxi/board.c
> >> > @@ -85,6 +85,16 @@ void s_init(void)
> >> > timer_init();
> >> > gpio_init();
> >> > i2c_init_board();
> >> > +
> >> > +#ifdef CONFIG_SPL_BUILD
> >> > + preloader_console_init();
> >>
> >> s_init() is called before we have global_data, so you can't use a
> console.
> >
> > Oh, but somehow it just works for me.
>
> I should have said that there *should* be no global_data at this point,
> i.e. we need to drop the hacks that add this. In fact global_data should be
> set up once in crt0.S and not before.
OK, I understand.
However crt0.S does not seem to be particularly compatible with FEL.
It tries to override the stack pointer (in the FEL mode we need to
use the original stack pointer provided to us by the BROM). And
implies that 'board_init_f' needs to return control back to the
BROM, however doing return from multiple nested levels of function
calls is a tricky exercise, especially considering that the stack
has been already moved elsewhere.
On the other hand, I see that crt0.S just allocates global data on
stack, clears it and then sets all the same r9 register. So what
is the real difference compared to having global data defined in
the ".data" section?
I would say that right now an easy hack would be to remove gdata
globally in u-boot (that's an admirable goal), but keep it with a
different name under the CONFIG_SPL_FEL define just for sunxi.
We might just rework this patch by providing the following FEL
entry point:
push{r9, lr}
ldr r9, =sunxi_fel_gdata
bl s_init
bl board_init_f
pop {r9, pc}
Then hide the unneeded parts of board_init_f() under
!defined(CONFIG_SPL_FEL) check, so that it just returns
right after initializing DRAM.
I see that the rationale for gdata removal is to allow having an
early malloc pool for the driver model in SPL:
http://lists.denx.de/pipermail/u-boot/2014-December/199528.html
I think that you can keep experimenting with the driver model
on sunxi with the regular SPL build, but just leave the FEL mode
build alone for now. It is not like u-boot is going to ever switch
to the driver model in the SPL on every platform (there are platforms
where the SRAM size is extremely small, even smaller than on sunxi),
so the sunxi FEL mode is not going to be alone doing this.
> >> > +
> >> > +#ifdef CONFIG_SPL_I2C_SUPPORT
> >> > + /* Needed early by sunxi_board_init if PMU is enabled */
> >> > + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
> >> > +#endif
> >> > + sunxi_board_init();
> >> > +#endif
> >>
> >> Why do you need this code here?
> >
> > The i2c_init() call is needed to initialize the PMIC as the comment
> > says. The PMIC is needed to set correct voltages, necessary for
> > the DRAM controller.
> >
> > And the sunxi_board_init() initializes DRAM.
> >
> >> Can it not go in board_init_f()?
> >
> > Then we probably would need a special stripped down FEL variant of
> > board_init_f(), which makes the code a bit more messy.
>
> Yes I think it is well worth
Re: [U-Boot] [RFC PATCH v2 2/6] x86: quark: Add routines to access message bus registers
Hi Simon, On Mon, Feb 2, 2015 at 12:30 AM, Simon Glass wrote: > On 29 January 2015 at 02:18, Bin Meng wrote: >> In the Quark SoC, some chipset commands are accomplished by utilizing >> the internal message network within the host bridge (D0:F0). Accesses >> to this network are accomplished by populating the message control >> register (MCR), Message Control Register eXtension (MCRX) and the >> message data register (MDR). >> >> Signed-off-by: Bin Meng >> >> --- >> >> Changes in v2: >> - Add msg_port_setup() and remove MCR_FILL >> - Add MSG_BYTE_ENABLE define >> - Wrap function declaraion with __ASSEMBLY__ >> >> arch/x86/cpu/quark/msg_port.c | 77 + >> arch/x86/include/asm/arch-quark/msg_port.h | 106 >> + >> 2 files changed, 183 insertions(+) >> create mode 100644 arch/x86/cpu/quark/msg_port.c >> create mode 100644 arch/x86/include/asm/arch-quark/msg_port.h >> > > Acked-by: Simon Glass > > I'd still prefer lower case hex. > OK, will fix in v3. Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC PATCH v2 4/6] x86: Add basic Intel Quark processor support
Hi Simon, On Mon, Feb 2, 2015 at 12:30 AM, Simon Glass wrote: > Hi Bin, > > On 29 January 2015 at 02:18, Bin Meng wrote: >> Add minimum codes to support Intel Quark SoC. DRAM initialization >> is not ready yet so a hardcoded gd->ram_size is assigned. >> >> Signed-off-by: Bin Meng >> >> --- >> >> Changes in v2: >> - Use machine-specific >> - Move vairous components' base addresses within Quark SoC to Kconfig >> - Rebase to u-boot-86/master >> > > All looks OK but for a few nits. > >> arch/x86/cpu/quark/Kconfig | 118 >> + >> arch/x86/cpu/quark/Makefile| 8 +++ >> arch/x86/cpu/quark/dram.c | 39 +++ >> arch/x86/cpu/quark/pci.c | 70 +++ >> arch/x86/cpu/quark/quark.c | 44 >> arch/x86/include/asm/arch-quark/gpio.h | 13 >> 6 files changed, 292 insertions(+) >> create mode 100644 arch/x86/cpu/quark/Kconfig >> create mode 100644 arch/x86/cpu/quark/Makefile >> create mode 100644 arch/x86/cpu/quark/dram.c >> create mode 100644 arch/x86/cpu/quark/pci.c >> create mode 100644 arch/x86/cpu/quark/quark.c >> create mode 100644 arch/x86/include/asm/arch-quark/gpio.h >> >> diff --git a/arch/x86/cpu/quark/Kconfig b/arch/x86/cpu/quark/Kconfig >> new file mode 100644 >> index 000..8bccf09 >> --- /dev/null >> +++ b/arch/x86/cpu/quark/Kconfig >> @@ -0,0 +1,118 @@ >> +# >> +# Copyright (C) 2015, Bin Meng >> +# >> +# SPDX-License-Identifier: GPL-2.0+ >> +# >> + >> +config INTEL_QUARK >> + bool >> + select HAVE_RMU >> + >> +if INTEL_QUARK >> + >> +config HAVE_RMU >> + bool "Add a Remote Management Unit (RMU) binary" >> + help >> + Select this option to add a Remote Management Unit (RMU) binary >> + to the resulting U-Boot image. It is a data block (up to 64K) of >> + machine-specific code which must be put in the flash for the RMU >> + within the Quark SoC processor to access when powered up before >> + system BIOS is executed. >> + >> +config RMU_FILE >> + string "Remote Management Unit (RMU) binary filename" >> + depends on HAVE_RMU >> + default "rmu.bin" >> + help >> + The filename of the file to use as Remote Management Unit (RMU) >> + binary in the board directory. >> + >> +config RMU_ADDR >> + hex "Remote Management Unit (RMU) binary location" >> + depends on HAVE_RMU >> + default 0xfff0 >> + help >> + The location of the RMU binary is determined by a strap. It must be >> + put in flash at a location matching the strap-determined base >> address. >> + >> + The default base address of 0xfff0 indicates that the binary >> must >> + be located at offset 0 from the beginning of a 1MB flash device. >> + >> +config HAVE_CMC >> + bool >> + default HAVE_RMU >> + >> +config CMC_FILE >> + string >> + depends on HAVE_CMC >> + default RMU_FILE >> + >> +config CMC_ADDR >> + hex >> + depends on HAVE_CMC >> + default RMU_ADDR >> + >> +config ESRAM_BASE >> + hex >> + default 0x8000 >> + help >> + Embedded SRAM (eSRAM) memory-mapped base address. >> + >> +config PCIE_ECAM_BASE >> + hex >> + default 0xe000 >> + >> +config RCBA_BASE >> + hex >> + default 0xfed1c000 >> + help >> + Root Complex register block memory-mapped base address. >> + >> +config ACPI_PM1_BASE >> + hex >> + default 0x1000 >> + help >> + ACPI PM1 i/o-mapped base address. > > What is PM1? This is defined in ACPI spec. Given U-Boot does not support ACPI yet, and its full description is documented in the ACPI spec, I don't think we need describe what it actually does here as this help is not a user visible Kconfig option. >> + >> +config ACPI_P_BASE >> + hex >> + default 0x1010 >> + help >> + ACPI PBLK i/o-mapped base address. > > What is PBLK? Defined in ACPI spec. Maybe I should define this as ACPI_PBLK_BASE. >> + >> +config SPI_DMA_BASE >> + hex >> + default 0x1020 >> + help >> + SPI DMA i/o-mapped base address. >> + >> +config GPIO_BASE >> + hex >> + default 0x1080 >> + help >> + GPIO i/o-mapped base address. >> + >> +config GPE0_BASE >> + hex >> + default 0x1100 >> + help >> + GPE0 i/o-mapped base address. > > What is GPE0? Defined in ACPI spec. Maybe I should describe it as "ACPI GPE0", like above two. >> + >> +config WDT_BASE >> + hex >> + default 0x1140 >> + help >> + Watchdog timer i/o-mapped base address. >> + >> +config SYS_CAR_ADDR >> + hex >> + default ESRAM_BASE >> + >> +config SYS_CAR_SIZE >> + hex >> + default 0x8000 >> + help >> + Space in bytes in eSRAM used as Cache-As-ARM (CAR). >> + Note this size must not
Re: [U-Boot] [RFC PATCH v2 3/6] x86: quark: Add Cache-As-RAM initialization
Hi Simon, On Mon, Feb 2, 2015 at 12:30 AM, Simon Glass wrote: > Hi Bin, > > On 29 January 2015 at 02:18, Bin Meng wrote: >> Quark SoC contains an embedded 512KiB SRAM (eSRAM) that is >> initialized by hardware. eSRAM is the ideal place to be used >> for Cache-As-RAM (CAR) before system memory is available. >> >> Signed-off-by: Bin Meng >> >> --- >> >> Changes in v2: >> - Replace upper case register names (EAX etc.) with lower case >> - Use some macros from and >> >> arch/x86/cpu/quark/car.S | 104 >> +++ >> 1 file changed, 104 insertions(+) >> create mode 100644 arch/x86/cpu/quark/car.S >> >> diff --git a/arch/x86/cpu/quark/car.S b/arch/x86/cpu/quark/car.S >> new file mode 100644 >> index 000..f32f9b1 >> --- /dev/null >> +++ b/arch/x86/cpu/quark/car.S >> @@ -0,0 +1,104 @@ >> +/* >> + * Copyright (C) 2015, Bin Meng >> + * >> + * SPDX-License-Identifier:GPL-2.0+ >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> + >> +.globl car_init >> +car_init: >> + post_code(POST_CAR_START) >> + >> + /* >> +* Quark SoC contains an embedded 512KiB SRAM (eSRAM) that is >> +* initialized by hardware. eSRAM is the ideal place to be used >> +* for Cache-As-RAM (CAR) before system memory is available. >> +* >> +* Relocate this eSRAM to a suitable location in the physical >> +* memory map and enable it. >> +*/ >> + >> + /* Host Memory Bound Register P03h:R08h */ >> + mov $((0x03 << 16) | (0x08 << 8)), %eax > > Do you have #defines for these to? I can add it to asm/arch/quark.h. >> + mov $(DRAM_BASE + DRAM_MAX_SIZE + ESRAM_SIZE), %edx >> + lea 1f, %esp >> + jmp msg_port_write >> +1: >> + >> + /* eSRAM Block Page Control Register P05h:R82h */ >> + mov $((0x05 << 16) | (0x82 << 8)), %eax >> + mov $(ESRAM_BLOCK_MODE | (CONFIG_ESRAM_BASE >> 24)), %edx >> + lea 2f, %esp >> + jmp msg_port_write >> +2: >> + >> + post_code(POST_CAR_CPU_CACHE) >> + jmp car_init_ret >> + >> +msg_port_read: >> + /* >> +* Parameter: >> +* eax[23:16] - Message Port ID >> +* eax[15:08] - Register Address >> +* >> +* Return Value: >> +* eax - Message Port Register value >> +* >> +* Return Address: esp >> +*/ >> + >> + or $((MSG_OP_READ << 24) | MSG_BYTE_ENABLE), %eax >> + mov %eax, %ebx >> + >> + /* Write MCR B0:D0:F0:RD0 */ >> + mov $((1 << 31) | MSG_CTRL_REG), %eax > > And this 1 << 31 ? I may have to add such generic pci macros (and 0xcf8, 0xcfc) to some other place in v3. >> + mov $0xcf8, %dx >> + out %eax, %dx >> + mov $0xcfc, %dx >> + mov %ebx, %eax >> + out %eax, %dx >> + >> + /* Read MDR B0:D0:F0:RD4 */ >> + mov $((1 << 31) | MSG_DATA_REG), %eax >> + mov $0xcf8, %dx >> + out %eax, %dx >> + mov $0xcfc, %dx >> + in %dx, %eax >> + >> + jmp *%esp >> + >> +msg_port_write: >> + /* >> +* Parameter: >> +* eax[23:16] - Message Port ID >> +* eax[15:08] - Register Address >> +* edx- Message Port Register value to write >> +* >> +* Return Address: esp >> +*/ >> + >> + or $((MSG_OP_WRITE << 24) | MSG_BYTE_ENABLE), %eax >> + mov %eax, %esi >> + mov %edx, %edi >> + >> + /* Write MDR B0:D0:F0:RD4 */ >> + mov $((1 << 31) | MSG_DATA_REG), %eax >> + mov $0xcf8, %dx >> + out %eax, %dx >> + mov $0xcfc, %dx >> + mov %edi, %eax >> + out %eax, %dx >> + >> + /* Write MCR B0:D0:F0:RD0 */ >> + mov $((1 << 31) | MSG_CTRL_REG), %eax >> + mov $0xcf8, %dx >> + out %eax, %dx >> + mov $0xcfc, %dx >> + mov %esi, %eax >> + out %eax, %dx >> + >> + jmp *%esp >> -- Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] PCI: add 64-bit prefetchable memory support
From: David Feng
PCI specification allow prefetchable memory to be 32-bit or 64-bit.
PCI express specification states that all memmory bars for prefetchable
memory must be implemented as 64-bit. They all require that 64 bit
prefetchble memory are suported especially when u-boot is ported to
more and more 64bit processors.
Signed-off-by: David Feng
---
drivers/pci/pci_auto.c | 36 +++-
1 file changed, 35 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c
index ed92857..5ddb0b8 100644
--- a/drivers/pci/pci_auto.c
+++ b/drivers/pci/pci_auto.c
@@ -223,9 +223,12 @@ void pciauto_prescan_setup_bridge(struct pci_controller
*hose,
struct pci_region *pci_mem = hose->pci_mem;
struct pci_region *pci_prefetch = hose->pci_prefetch;
struct pci_region *pci_io = hose->pci_io;
- u16 cmdstat;
+ u16 cmdstat, prefechable_64;
pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
+ pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
+ &prefechable_64);
+ prefechable_64 &= 0x1;
/* Configure bus number registers */
pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
@@ -252,12 +255,26 @@ void pciauto_prescan_setup_bridge(struct pci_controller
*hose,
/* Set up memory and I/O filter limits, assume 32-bit I/O space
*/
pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
(pci_prefetch->bus_lower & 0xfff0)
>> 16);
+ if (prefechable_64)
+#ifdef CONFIG_SYS_PCI_64BIT
+ pci_hose_write_config_dword(hose, dev,
+ PCI_PREF_BASE_UPPER32,
+ pci_prefetch->bus_lower >> 32);
+#else
+ pci_hose_write_config_dword(hose, dev,
+ PCI_PREF_BASE_UPPER32,
+ 0x0);
+#endif
cmdstat |= PCI_COMMAND_MEMORY;
} else {
/* We don't support prefetchable memory for now, so disable */
pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
0x1000);
pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
0x0);
+ if (prefechable_64) {
+ pci_hose_write_config_word(hose, dev,
PCI_PREF_BASE_UPPER32, 0x0);
+ pci_hose_write_config_word(hose, dev,
PCI_PREF_LIMIT_UPPER32, 0x0);
+ }
}
if (pci_io) {
@@ -297,11 +314,28 @@ void pciauto_postscan_setup_bridge(struct pci_controller
*hose,
}
if (pci_prefetch) {
+ u16 prefechable_64;
+
+ pci_hose_read_config_word(hose, dev,
+ PCI_PREF_MEMORY_LIMIT,
+ &prefechable_64);
+ prefechable_64 &= 0x1;
+
/* Round memory allocator to 1MB boundary */
pciauto_region_align(pci_prefetch, 0x10);
pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
(pci_prefetch->bus_lower - 1) >> 16);
+ if (prefechable_64)
+#ifdef CONFIG_SYS_PCI_64BIT
+ pci_hose_write_config_dword(hose, dev,
+ PCI_PREF_LIMIT_UPPER32,
+ (pci_prefetch->bus_lower - 1) >> 32);
+#else
+ pci_hose_write_config_dword(hose, dev,
+ PCI_PREF_LIMIT_UPPER32,
+ 0x0);
+#endif
}
if (pci_io) {
--
1.7.9.5
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Re: [U-Boot] [PATCH v3 3/6] Exynos542x: Add and enable get_periph_rate support
Hi,
>Hi, All.
>
>On 01/28/2015 02:55 PM, Joonyoung Shim wrote:
>> Hi Simon,
>>
>> On 01/28/2015 02:15 PM, Simon Glass wrote:
>>> Hi Joonyoung,
>>>
>>> On 27 January 2015 at 22:12, Joonyoung Shim wrote:
Hi Simon,
On 01/28/2015 02:01 PM, Simon Glass wrote:
> Hi Joonyoung,
>
> On 27 January 2015 at 21:46, Joonyoung Shim
> wrote:
>> Hi Simon,
>>
>> On 01/28/2015 01:09 PM, Simon Glass wrote:
>>> Hi,
>>>
>>> On 15 January 2015 at 23:09, Joonyoung Shim
>>> wrote:
Hi,
On 01/16/2015 02:48 PM, Akshay Saraswat wrote:
> We planned to fetch peripheral rate through one generic API per
> peripheral. These generic peripheral functions are in turn
> expected to fetch apt values from a function refactored as
> per SoC versions. This patch adds support for fetching peripheral
> rates for Exynos5420 and Exynos5800.
>
> Signed-off-by: Akshay Saraswat
> ---
> Changes since v2:
> - Fixed enum and exynos542x_get_periph_rate switch.
> - Added checks for negative values in
> exynos542x_get_periph_rate.
>
> Changes since v1:
> - Changes suuport -> support in commit message.
> - Removed position change of exynos5420_get_pll_clk.
> - Removed #ifdef.
>
> arch/arm/cpu/armv7/exynos/clock.c | 151
> +++--
> arch/arm/include/asm/arch-exynos/clk.h | 3 +
> 2 files changed, 147 insertions(+), 7 deletions(-)
>>>
>>> What else needs to be done to get this applied, please?
>>>
>>
>> As i said, current this patch has some problem like mask bits, so eMMC
>> doesn't work normally.
>>
>
> diff --git a/arch/arm/cpu/armv7/exynos/clock.c
> b/arch/arm/cpu/armv7/exynos/clock.c
> index 5dc9ed2..ee6c13b 100644
> --- a/arch/arm/cpu/armv7/exynos/clock.c
> +++ b/arch/arm/cpu/armv7/exynos/clock.c
> @@ -27,7 +27,7 @@ struct clk_bit_info {
> };
>
> /* periph_id src_bit div_bit prediv_bit */
> -static struct clk_bit_info clk_bit_info[] = {
> +static struct clk_bit_info exynos5_bit_info[] = {
> {PERIPH_ID_UART0, 0, 0, -1},
> {PERIPH_ID_UART1, 4, 4, -1},
> {PERIPH_ID_UART2, 8, 8, -1},
> @@ -61,6 +61,42 @@ static struct clk_bit_info clk_bit_info[] = {
> {PERIPH_ID_NONE,-1, -1, -1},
> };
>
> +static struct clk_bit_info exynos542x_bit_info[] = {
> + {PERIPH_ID_UART0, 4, 8, -1},
> + {PERIPH_ID_UART1, 8, 12, -1},
> + {PERIPH_ID_UART2, 12, 16, -1},
> + {PERIPH_ID_UART3, 16, 20, -1},
> + {PERIPH_ID_I2C0,-1, 8, -1},
> + {PERIPH_ID_I2C1,-1, 8, -1},
> + {PERIPH_ID_I2C2,-1, 8, -1},
> + {PERIPH_ID_I2C3,-1, 8, -1},
> + {PERIPH_ID_I2C4,-1, 8, -1},
> + {PERIPH_ID_I2C5,-1, 8, -1},
> + {PERIPH_ID_I2C6,-1, 8, -1},
> + {PERIPH_ID_I2C7,-1, 8, -1},
> + {PERIPH_ID_SPI0,20, 20, 8},
> + {PERIPH_ID_SPI1,24, 24, 16},
> + {PERIPH_ID_SPI2,28, 28, 24},
> + {PERIPH_ID_SDMMC0, 0, 0, -1},
> + {PERIPH_ID_SDMMC1, 4, 10, -1},
> + {PERIPH_ID_SDMMC2, 8, 20, -1},
> + {PERIPH_ID_I2C8,-1, 8, -1},
> + {PERIPH_ID_I2C9,-1, 8, -1},
> + {PERIPH_ID_I2S0,0, 0, 4},
> + {PERIPH_ID_I2S1,4, 12, 16},
> + {PERIPH_ID_SPI3,12, 16, 0},
> + {PERIPH_ID_SPI4,16, 20, 8},
> + {PERIPH_ID_SDMMC4, 16, 0, 8},
> + {PERIPH_ID_PWM0,24, 28, -1},
> + {PERIPH_ID_PWM1,24, 28, -1},
> + {PERIPH_ID_PWM2,24, 28, -1},
> + {PERIPH_ID_PWM3,24, 28, -1},
> + {PERIPH_ID_PWM4,24, 28, -1},
> + {PERIPH_ID_I2C10, -1, 8, -1},
> +
> + {PERIPH_ID_NONE,-1, -1, -1},
> +};
> +
> /* Epll Clock division values to achive different frequency output */
> static struct set_epll_con_val exynos5_epll_div[] = {
> { 19200, 0, 48, 3, 1, 0 },
> @@ -306,16 +342,22 @@ static unsigned long exynos542x_get_pll_clk(int
Re: [U-Boot] [PATCH] PCI: add 64-bit prefetchable memory support
Hi David,
On Mon, Feb 2, 2015 at 11:30 AM, wrote:
> From: David Feng
>
> PCI specification allow prefetchable memory to be 32-bit or 64-bit.
> PCI express specification states that all memmory bars for prefetchable
> memory must be implemented as 64-bit. They all require that 64 bit
> prefetchble memory are suported especially when u-boot is ported to
> more and more 64bit processors.
>
> Signed-off-by: David Feng
> ---
This patch looks good to me, except a minor issue below.
> drivers/pci/pci_auto.c | 36 +++-
> 1 file changed, 35 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c
> index ed92857..5ddb0b8 100644
> --- a/drivers/pci/pci_auto.c
> +++ b/drivers/pci/pci_auto.c
> @@ -223,9 +223,12 @@ void pciauto_prescan_setup_bridge(struct pci_controller
> *hose,
> struct pci_region *pci_mem = hose->pci_mem;
> struct pci_region *pci_prefetch = hose->pci_prefetch;
> struct pci_region *pci_io = hose->pci_io;
> - u16 cmdstat;
> + u16 cmdstat, prefechable_64;
>
> pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
> + pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
> + &prefechable_64);
> + prefechable_64 &= 0x1;
Please use PCI_PREF_RANGE_TYPE_64.
>
> /* Configure bus number registers */
> pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
> @@ -252,12 +255,26 @@ void pciauto_prescan_setup_bridge(struct pci_controller
> *hose,
> /* Set up memory and I/O filter limits, assume 32-bit I/O
> space */
> pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
> (pci_prefetch->bus_lower &
> 0xfff0) >> 16);
> + if (prefechable_64)
> +#ifdef CONFIG_SYS_PCI_64BIT
> + pci_hose_write_config_dword(hose, dev,
> + PCI_PREF_BASE_UPPER32,
> + pci_prefetch->bus_lower >> 32);
> +#else
> + pci_hose_write_config_dword(hose, dev,
> + PCI_PREF_BASE_UPPER32,
> + 0x0);
> +#endif
>
> cmdstat |= PCI_COMMAND_MEMORY;
> } else {
> /* We don't support prefetchable memory for now, so disable */
> pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
> 0x1000);
> pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
> 0x0);
> + if (prefechable_64) {
> + pci_hose_write_config_word(hose, dev,
> PCI_PREF_BASE_UPPER32, 0x0);
> + pci_hose_write_config_word(hose, dev,
> PCI_PREF_LIMIT_UPPER32, 0x0);
> + }
> }
>
> if (pci_io) {
> @@ -297,11 +314,28 @@ void pciauto_postscan_setup_bridge(struct
> pci_controller *hose,
> }
>
> if (pci_prefetch) {
> + u16 prefechable_64;
> +
> + pci_hose_read_config_word(hose, dev,
> + PCI_PREF_MEMORY_LIMIT,
> + &prefechable_64);
>
> + prefechable_64 &= 0x1;
Ditto.
> /* Round memory allocator to 1MB boundary */
> pciauto_region_align(pci_prefetch, 0x10);
>
> pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
> (pci_prefetch->bus_lower - 1) >> 16);
> + if (prefechable_64)
> +#ifdef CONFIG_SYS_PCI_64BIT
> + pci_hose_write_config_dword(hose, dev,
> + PCI_PREF_LIMIT_UPPER32,
> + (pci_prefetch->bus_lower - 1) >> 32);
> +#else
> + pci_hose_write_config_dword(hose, dev,
> + PCI_PREF_LIMIT_UPPER32,
> + 0x0);
> +#endif
> }
>
> if (pci_io) {
> --
Regards,
Bin
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Re: [U-Boot] [RFC PATCH v2 4/6] x86: Add basic Intel Quark processor support
Hi Bin, On 1 February 2015 at 19:16, Bin Meng wrote: > Hi Simon, > > On Mon, Feb 2, 2015 at 12:30 AM, Simon Glass wrote: >> Hi Bin, >> >> On 29 January 2015 at 02:18, Bin Meng wrote: >>> Add minimum codes to support Intel Quark SoC. DRAM initialization >>> is not ready yet so a hardcoded gd->ram_size is assigned. >>> >>> Signed-off-by: Bin Meng >>> >>> --- >>> >>> Changes in v2: >>> - Use machine-specific >>> - Move vairous components' base addresses within Quark SoC to Kconfig >>> - Rebase to u-boot-86/master >>> >> >> All looks OK but for a few nits. >> >>> arch/x86/cpu/quark/Kconfig | 118 >>> + >>> arch/x86/cpu/quark/Makefile| 8 +++ >>> arch/x86/cpu/quark/dram.c | 39 +++ >>> arch/x86/cpu/quark/pci.c | 70 +++ >>> arch/x86/cpu/quark/quark.c | 44 >>> arch/x86/include/asm/arch-quark/gpio.h | 13 >>> 6 files changed, 292 insertions(+) >>> create mode 100644 arch/x86/cpu/quark/Kconfig >>> create mode 100644 arch/x86/cpu/quark/Makefile >>> create mode 100644 arch/x86/cpu/quark/dram.c >>> create mode 100644 arch/x86/cpu/quark/pci.c >>> create mode 100644 arch/x86/cpu/quark/quark.c >>> create mode 100644 arch/x86/include/asm/arch-quark/gpio.h >>> >>> diff --git a/arch/x86/cpu/quark/Kconfig b/arch/x86/cpu/quark/Kconfig >>> new file mode 100644 >>> index 000..8bccf09 >>> --- /dev/null >>> +++ b/arch/x86/cpu/quark/Kconfig >>> @@ -0,0 +1,118 @@ >>> +# >>> +# Copyright (C) 2015, Bin Meng >>> +# >>> +# SPDX-License-Identifier: GPL-2.0+ >>> +# >>> + >>> +config INTEL_QUARK >>> + bool >>> + select HAVE_RMU >>> + >>> +if INTEL_QUARK >>> + >>> +config HAVE_RMU >>> + bool "Add a Remote Management Unit (RMU) binary" >>> + help >>> + Select this option to add a Remote Management Unit (RMU) binary >>> + to the resulting U-Boot image. It is a data block (up to 64K) of >>> + machine-specific code which must be put in the flash for the RMU >>> + within the Quark SoC processor to access when powered up before >>> + system BIOS is executed. >>> + >>> +config RMU_FILE >>> + string "Remote Management Unit (RMU) binary filename" >>> + depends on HAVE_RMU >>> + default "rmu.bin" >>> + help >>> + The filename of the file to use as Remote Management Unit (RMU) >>> + binary in the board directory. >>> + >>> +config RMU_ADDR >>> + hex "Remote Management Unit (RMU) binary location" >>> + depends on HAVE_RMU >>> + default 0xfff0 >>> + help >>> + The location of the RMU binary is determined by a strap. It must >>> be >>> + put in flash at a location matching the strap-determined base >>> address. >>> + >>> + The default base address of 0xfff0 indicates that the binary >>> must >>> + be located at offset 0 from the beginning of a 1MB flash device. >>> + >>> +config HAVE_CMC >>> + bool >>> + default HAVE_RMU >>> + >>> +config CMC_FILE >>> + string >>> + depends on HAVE_CMC >>> + default RMU_FILE >>> + >>> +config CMC_ADDR >>> + hex >>> + depends on HAVE_CMC >>> + default RMU_ADDR >>> + >>> +config ESRAM_BASE >>> + hex >>> + default 0x8000 >>> + help >>> + Embedded SRAM (eSRAM) memory-mapped base address. >>> + >>> +config PCIE_ECAM_BASE >>> + hex >>> + default 0xe000 >>> + >>> +config RCBA_BASE >>> + hex >>> + default 0xfed1c000 >>> + help >>> + Root Complex register block memory-mapped base address. >>> + >>> +config ACPI_PM1_BASE >>> + hex >>> + default 0x1000 >>> + help >>> + ACPI PM1 i/o-mapped base address. >> >> What is PM1? > > This is defined in ACPI spec. Given U-Boot does not support ACPI yet, > and its full description is documented in the ACPI spec, I don't think > we need describe what it actually does here as this help is not a user > visible Kconfig option. OK, but perhaps you can put the abbreviated names in the help? > >>> + >>> +config ACPI_P_BASE >>> + hex >>> + default 0x1010 >>> + help >>> + ACPI PBLK i/o-mapped base address. >> >> What is PBLK? > > Defined in ACPI spec. Maybe I should define this as ACPI_PBLK_BASE. > >>> + >>> +config SPI_DMA_BASE >>> + hex >>> + default 0x1020 >>> + help >>> + SPI DMA i/o-mapped base address. >>> + >>> +config GPIO_BASE >>> + hex >>> + default 0x1080 >>> + help >>> + GPIO i/o-mapped base address. >>> + >>> +config GPE0_BASE >>> + hex >>> + default 0x1100 >>> + help >>> + GPE0 i/o-mapped base address. >> >> What is GPE0? > > Defined in ACPI spec. Maybe I should describe it as "ACPI GPE0", like above > two. Whatever you think is fine for the option, but please explain lots in the help message. > >>> + >>>
Re: [U-Boot] [RFC PATCH 0/21] ARM: start to move SoC code into arch/arm/mach-*
Hi Albert, (cc Simon) On Sun, 1 Feb 2015 11:11:44 +0100 Albert ARIBAUD wrote: > Hello Simon, > > On Sat, 31 Jan 2015 20:20:06 -0700, Simon Glass > wrote: > > Hi Albert, > > > > On 31 January 2015 at 20:02, Albert ARIBAUD > > wrote: > > > Hello Masahiro, > > > > > > On Sun, 25 Jan 2015 15:11:02 +0900, Masahiro Yamada > > > wrote: > > >> > > >> This series can be applied on the current u-boot/master > > >> (commit 37b608a52dcb133) > > > > > > I'd rather not have all mach-* directories just below arch/arm/. Can't > > > they be created under arch/arm/soc/ instead? That would give a cleaner > > > structure IMO. > > > > It does save a level and I am forever typing cpu/armv7 to get what > > feels like nowhere... > > That can easily be solved (and tuned to personal taste) with CDPATH, eg. > > uboot@lilith:~/src/u-boot-arm (master)$ export CDPATH=arch/arm/cpu:arch/arm > uboot@lilith:~/src/u-boot-arm (master)$ cd armv > armv7/ armv8/ > uboot@lilith:~/src/u-boot-arm (master)$ cd armv7 > /home/uboot/src/u-boot-arm/arch/arm/cpu/armv7 > uboot@lilith:~/src/u-boot-arm/arch/arm/cpu/armv7 (master)$ > > (the u-boot-friendly value of CDPATH can put in a u-boot_env.sh file to > be sourced along with other u-boot related settings) > > > this is what the kernel does and it does seem convenient. > > Well, to me it does not really -- I'm ok with loads of mach-* subdirs > under a commin parent dir, but what's the benefit of mixing mach-* dirs > with non-mach-* ones? Listing "machdirs" in arch/arm/Makefile has two meanings: [1] Descide which mach-* directory to descend in order to build SoC sources. [2] Add arch/arm/mach-*/include/mach to the header include path. (As I commented in 13/21, I do not prefer creating a symbolic link during the build.) As for [1], I'm OK with having SoC directories in arch/arm/soc/*. In that case, I am inclined to describe SoC stuff in arch/arm/soc/Makefile, which I think makes it difficult to achieve [2]. If you have a better idea, please let me know. Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] odroid: update link to X2/U3 proprietary binaries
>From f12af0fe43378f945de3eaa5acbca4e0a4d711b8 Mon Sep 17 00:00:00 2001 From: Tobias Jakobi Date: Sun, 1 Feb 2015 19:47:50 +0100 Subject: odroid: update link to X2/U3 proprietary binaries The old link was dead. Link to the Github repository which is probably a more long-term solution. --- doc/README.odroid | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/README.odroid b/doc/README.odroid index 528bb95..cc85348 100644 --- a/doc/README.odroid +++ b/doc/README.odroid @@ -19,7 +19,7 @@ iROM->BL1->(BL2 + TrustZone)->U-BOOT This version of U-BOOT doesn't implement SPL but it is required(BL2) and can be found in "boot.tar.gz" from here: -http://dev.odroid.com/projects/4412boot/wiki/FrontPage?action=download&value=boot.tar.gz +https://github.com/hardkernel/u-boot/tree/odroid-v2010.12/sd_fuse or here: http://odroid.in/guides/ubuntu-lfs/boot.tar.gz -- 2.0.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] mtd: atmel_nand: according to pmecc version to perform 0xff page correction
Hi, Scott
On 1/16/2015 4:24 PM, Andreas Bießmann wrote:
Hi Bo, Josh,
On 01/16/2015 07:50 AM, Josh Wu wrote:
Hi, Bo
On 1/16/2015 1:27 PM, Bo Shen wrote:
Hi Josh,
On 01/16/2015 11:54 AM, Josh Wu wrote:
As the PMECC hardware has different version. In SAMA5D4 chip, the
PMECC ip
can generate 0xff pmecc ECC value for all 0xff sector.
According to this, add PMECC version check, if it's SAMA5D4 then we
always
let PMECC hardware to correct it.
Signed-off-by: Josh Wu
except the nitpick.
Acked-by: Bo Shen
Acked-by: Andreas Bießmann
Would you pick this patch into your tree with Bo and Andreas's Acked-by?
Thanks.
Best Regards,
Josh Wu
Thanks for the quick review.
---
drivers/mtd/nand/atmel_nand.c | 9 +
drivers/mtd/nand/atmel_nand_ecc.h | 20
2 files changed, 29 insertions(+)
diff --git a/drivers/mtd/nand/atmel_nand.c
b/drivers/mtd/nand/atmel_nand.c
index 620b6e8..b16e3aa 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -44,6 +44,7 @@ struct atmel_nand_host {
u8pmecc_corr_cap;
u16pmecc_sector_size;
u32pmecc_index_table_offset;
+u32pmecc_version;
intpmecc_bytes_per_sector;
intpmecc_sector_number;
@@ -486,6 +487,10 @@ static int pmecc_correction(struct mtd_info
*mtd, u32 pmecc_stat, uint8_t *buf,
int i, err_nbr, eccbytes;
uint8_t *buf_pos;
+/* SAMA5D4 PMECC IP can correct errors for all 0xff page */
+if (host->pmecc_version >= PMECC_VERSION_SAMA5D4)
I think we can hard coded here, then we can drop the definition in
header file.
I don't like hard coded magic number in personly.
me too!
+goto normal_check;
+
eccbytes = nand_chip->ecc.bytes;
for (i = 0; i < eccbytes; i++)
if (ecc[i] != 0xff)
@@ -961,6 +966,10 @@ static int atmel_pmecc_nand_init_params(struct
nand_chip *nand,
nand->ecc.write_page = atmel_nand_pmecc_write_page;
nand->ecc.strength = cap;
+/* Check the PMECC ip version */
+host->pmecc_version = pmecc_readl(host->pmerrloc, version);
+dev_dbg(host->dev, "PMECC IP version is: %x\n",
host->pmecc_version);
+
atmel_pmecc_core_init(mtd);
return 0;
diff --git a/drivers/mtd/nand/atmel_nand_ecc.h
b/drivers/mtd/nand/atmel_nand_ecc.h
index eac860d..b2d2682 100644
--- a/drivers/mtd/nand/atmel_nand_ecc.h
+++ b/drivers/mtd/nand/atmel_nand_ecc.h
@@ -123,6 +123,20 @@ struct pmecc_errloc_regs {
u32 sigma[25];/* 0x28-0x88 Error Location Sigma Registers */
u32 el[24];/* 0x8C-0xE8 Error Location Registers */
u32 reserved1[5];/* 0xEC-0xFC Reserved */
+
+/*
+ * 0x100-0x1F8:
+ * Reserved for AT91SAM9X5, AT91SAM9N12.
+ * HSMC registers for SAMA5D3, SAMA5D4.
+ */
I think no need to add this.
actually, I would like to keep those comments.
As in the datasheet, sama5d3 and sama5d4's PMECC ERRLOC only have the
register range: 0x0~0xFF.
and the range 0x100-0x1F8 is for the HSMC.
So people will be confused if they find HSMC definitions in the
PMECC_ERRLOC structure.
I think list this comment would be cleaner.
This is reasonable, please let the comment in.
+u32 reserved2[63];
+
+/*
+ * 0x1FC:
+ * PMECC version for AT91SAM9X5, AT91SAM9N12.
+ * HSMC version for SAMA5D3, SAMA5D4. Can refer as PMECC version.
+ */
ditto.
Like mentioned above, I want avoid the confusion about PMECC_ERRLOC/HSMC.
+u32 version;
};
/* For Error Location Configuration Register */
@@ -137,6 +151,12 @@ struct pmecc_errloc_regs {
#definePMERRLOC_ERR_NUM_MASK(0x1f << 8)
#definePMERRLOC_CALC_DONE(1 << 0)
+/* PMECC IP version */
+#define PMECC_VERSION_SAMA5D40x113
+#define PMECC_VERSION_SAMA5D30x112
+#define PMECC_VERSION_AT91SAM9N120x102
No where will use the upper three definitions, we can drop them.
I don't have strong option about this. Just think the version
information is useful for other to reference.
Can someone else get this information from the datasheets? If not please
let this information there.
Best regards
Andreas Bießmann
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[U-Boot] mpc8308rdb generic board support
Hi Ilya MPC8308RDB BOARD M: Ilya Yanok S: Maintained F: board/freescale/mpc8308rdb/ F: include/configs/MPC8308RDB.h F: configs/MPC8308RDB_defconfig I am not sure what is your more uptodate e-mail but I noticed generic board support is not added to this board : make MPC8308RDB_defconfig [...] = WARNING == Please convert this board to generic board. I don't know if you are still maintaining this board but I am planning to order this board and keep an eye on it. Before this happens though it may get removed. If you still access to this board you can perhaps quickly enable the generic board support and once my board arrives I can help to keep an eye on the board further. Thanks Sinan Akman ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] U-Boot gitweb
Hi, I found U-Boot gitweb looks terrible since last week. http://git.denx.de/?p=u-boot.git;a=summary Looks the css is not working (?) Does anyone see the same issue here? Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Pull request: u-boot-blackfin
Hi Tom, Please pull the following patches for Blackfin from u-boot-blackfin into your tree. Thanks Sonic Zhang The following changes since commit 28c4dae114c9b94b2ad81d4da716e9fc2cba: Merge branch 'next' of git://git.denx.de/u-boot-video (2015-01-14 16:26:15 -0500) are available in the git repository at: git://git.denx.de/u-boot-blackfin.git master for you to fetch changes up to 0d3fd562c4977af4e992f3f73a441081ff8c60d0: bfin: make env offset sector aligned for bct-brettl2 and ibf-dsp561 boards (2015-01-16 13:31:35 +0800) Sonic Zhang (2): bfin: enlarge the monitor size for ip04 board to avoid oversize link error bfin: make env offset sector aligned for bct-brettl2 and ibf-dsp561 boards include/configs/bct-brettl2.h | 2 +- include/configs/ibf-dsp561.h | 2 +- include/configs/ip04.h| 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2 06/10] arm: socfpga: Zap checkboard()
On 30.01.2015 23:08, Marek Vasut wrote: Since all boards now have a DT, instead of hard-coding the board name into the U-Boot binary, read the board name from DT "model" property. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Pavel Machek Cc: Stefan Roese Cc: Vince Bridgers Acked-by: Stefan Roese Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] U-Boot gitweb
Hi! I can also see the same issue. It looks like some problem with permissions: """ Forbidden You don't have permission to access /gitweb.css on this server. Apache/2.2.22 (Debian) Server at git.denx.de Port 80 """ Error 403 is also returned for gitweb.js and git-logo.png ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2 08/10] arm: socfpga: Add Altera Arria V DK support
On 30.01.2015 23:08, Marek Vasut wrote:
Add support for the Altera Arria V development kit.
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Pavel Machek
Cc: Stefan Roese
Cc: Vince Bridgers
---
arch/arm/Kconfig | 5 +
board/altera/socfpga/Kconfig | 16 +
board/altera/socfpga/iocsr_config.c | 688 +++
board/altera/socfpga/iocsr_config.h | 9 +
board/altera/socfpga/pinmux_config.c | 215 +++
configs/socfpga_arria5_defconfig | 3 +
include/configs/socfpga_arria5.h | 107 ++
7 files changed, 1043 insertions(+)
create mode 100644 configs/socfpga_arria5_defconfig
create mode 100644 include/configs/socfpga_arria5.h
diff --git a/include/configs/socfpga_arria5.h b/include/configs/socfpga_arria5.h
new file mode 100644
index 000..668a91e
--- /dev/null
+++ b/include/configs/socfpga_arria5.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright (C) 2014 Marek Vasut
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#ifndef __CONFIG_SOCFPGA_ARRIA5_H__
+#define __CONFIG_SOCFPGA_ARRIA5_H__
+
+#include
+#include "../../board/altera/socfpga/pinmux_config.h"
+#include "../../board/altera/socfpga/iocsr_config.h"
+#include "../../board/altera/socfpga/pll_config.h"
+
+/* U-Boot Commands */
+#define CONFIG_SYS_NO_FLASH
+#include
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FAT_WRITE
+#define CONFIG_HW_WATCHDOG
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DFU
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_USB_MASS_STORAGE
+
+#define CONFIG_REGEX /* Enable regular expression support */
+
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE 0x4000 /* 1GiB on SoCDK */
+
+/* Booting Linux */
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTFILE"zImage"
+#define CONFIG_BOOTARGS"console=ttyS0,"
__stringify(CONFIG_BAUDRATE)
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_BOOTCOMMAND "run ramboot"
+#else
+#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
+#endif
+#define CONFIG_LOADADDR0x8000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+/* Ethernet on SoC (EMAC) */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_EMAC_BASE SOCFPGA_EMAC1_ADDRESS
+#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
+
+/* PHY */
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9021
+#define CONFIG_KSZ9021_CLK_SKEW_ENV"micrel-ksz9021-clk-skew"
+#define CONFIG_KSZ9021_CLK_SKEW_VAL0xf0f0
+#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew"
+#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0
+
+#endif
+
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
+#endif
+#define CONFIG_G_DNL_MANUFACTURER "Altera"
+
+/* Extra Environment */
+#define CONFIG_HOSTNAMEsocfpga_arria5
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "verify=n\0" \
+ "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
+ "bootm ${loadaddr} - ${fdt_addr}\0" \
+ "bootimage=zImage\0" \
+ "fdt_addr=100\0" \
+ "fdtimage=socfpga.dtb\0" \
+ "fsloadcmd=ext2load\0" \
+ "bootm ${loadaddr} - ${fdt_addr}\0" \
+ "mmcroot=/dev/mmcblk0p2\0" \
+ "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${mmcroot} rw rootwait;" \
+ "bootz ${loadaddr} - ${fdt_addr}\0" \
+ "mmcload=mmc rescan;" \
+ "load mmc 0:1 ${loadaddr} ${bootimage};" \
+ "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+ "qspiroot=/dev/mtdblock0\0" \
+ "qspirootfstype=jffs2\0" \
+ "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
+ "bootm ${loadaddr} - ${fdt_addr}\0"
+
+/* The rest of the configuration is shared */
+#include
+
+#endif /* __CONFIG_SOCFPGA_ARRIA5_H__ */
Without really diff'ing this file with socfpga_cyclone5.h, I'm pretty
sure that they share many lines. Wouldn't it make sense to move those
common defines / configs to a common file instead (socfpga_common.h)?
Thanks,
Stefan
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Re: [U-Boot] [PATCH 02/21] common/lcd: Add command for setting cursor within lcd-framework
"U-Boot" schrieb am 01.02.2015 15:48:51:
> From: Nikita Kiryanov
> To: Hannes Petermaier , u-boot@lists.denx.de
> Date: 01.02.2015 15:49
> Subject: Re: [U-Boot] [PATCH 02/21] common/lcd: Add command for setting
cursor
> within lcd-framework
> Sent by: "U-Boot"
>
> Hi Hannes,
Hi Nikita,
>
> On 01/30/2015 03:25 PM, Hannes Petermaier wrote:
> > We need this function if we want to make some outputs i.e position the
writing
> > cursor out of u-boot scripts.
>
> This commit message is inaccurate. Positioning the writing cursor is not
in
> itself output.
> Also, what is the use case for such a command?
>
I want to set the "cursor" on the screen to a specific position and write
there something
with "puts".
For example:
setcurs 1 9;sets the cursor to first column and 9th row
puts "Hello World!" writes the text to the cursor.
> >
> > Signed-off-by: Hannes Petermaier
> > ---
> > common/lcd.c | 21 +
> > 1 file changed, 21 insertions(+)
> >
> > diff --git a/common/lcd.c b/common/lcd.c
> > index cc34b8a..f418da9 100644
> > --- a/common/lcd.c
> > +++ b/common/lcd.c
> > @@ -279,12 +279,33 @@ static int do_lcd_clear(cmd_tbl_t *cmdtp, int
flag, int argc,
> > return 0;
> > }
> >
> > +static int do_lcd_setcursor(cmd_tbl_t *cmdtp, int flag, int argc,
> > + char *const argv[])
> > +{
> > + unsigned int col, row;
> > +
> > + if (argc != 3)
> > + return CMD_RET_USAGE;
> > +
> > + col = simple_strtoul(argv[1], NULL, 10);
> > + row = simple_strtoul(argv[2], NULL, 10);
> > + lcd_position_cursor(col, row);
> > +
> > + return 0;
> > +}
> > +
> > U_BOOT_CMD(
> > cls, 1, 1, do_lcd_clear,
> > "clear screen",
> > ""
> > );
> >
> > +U_BOOT_CMD(
> > + setcurs, 3, 1, do_lcd_setcursor,
> > + "sets cursor for 'puts'",
> > + " in character"
> > +);
> > +
>
> I think it would be better if the U_BOOT_CMD macros were adjacent to the
functions they
> use. Also, I think this command is better suited for the lcd_console.c
file.
You're maybe right. Only thing for decission was, that existing commands
are allready defined within
lcd.c. But i've no problem to move it. What do you say? let's move?
>
> >
/*--*/
> >
> > static int lcd_init(void *lcdbase)
> >
>
> --
> Regards,
> Nikita Kiryanov
best regards,
Hannes
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Re: [U-Boot] [PATCH 03/21] common/lcd: Add command for writing to lcd-display
> From: Nikita Kiryanov
> To: Hannes Petermaier , u-boot@lists.denx.de
> Date: 01.02.2015 15:53
> Subject: Re: [U-Boot] [PATCH 03/21] common/lcd: Add command for writing
to lcd-display
> Sent by: "U-Boot"
>
> Hi Hannes,
Hi Nikita,
>
> On 01/30/2015 03:25 PM, Hannes Petermaier wrote:
> > We need this function if we want to make some outputs out of u-boot
scripts.
> >
>
> I think this commit message is missing information. What makes this
necessary?
> Why can't your script use regular echo commands with the lcd console
enabled?
Since i don't want that stdout is redirected to LCD (customer isn't
interested in watching
all output of u-boot) i need something to write out of scripts to the
screen.
For example we write of script in which mode we are booting, maybe also
some default ip settings
in recovery mode.
>
> > Signed-off-by: Hannes Petermaier
> > ---
> > common/lcd.c | 17 +
> > 1 file changed, 17 insertions(+)
> >
> > diff --git a/common/lcd.c b/common/lcd.c
> > index f418da9..755388f 100644
> > --- a/common/lcd.c
> > +++ b/common/lcd.c
> > @@ -279,6 +279,17 @@ static int do_lcd_clear(cmd_tbl_t *cmdtp, int
flag, int argc,
> > return 0;
> > }
> >
> > +static int do_lcd_puts(cmd_tbl_t *cmdtp, int flag, int argc,
> > + char *const argv[])
> > +{
> > + if (argc != 2)
> > + return CMD_RET_USAGE;
> > +
> > + lcd_puts(argv[1]);
> > +
> > + return 0;
> > +}
> > +
> > static int do_lcd_setcursor(cmd_tbl_t *cmdtp, int flag, int argc,
> >char *const argv[])
> > {
> > @@ -306,6 +317,12 @@ U_BOOT_CMD(
> > " in character"
> > );
> >
> > +U_BOOT_CMD(
> > + puts, 2, 1, do_lcd_puts,
>
> "puts" is too generic for an lcd specific function. I would expect to
see something
> with an "lcd" prefix. Also, this code seems better suited for
lcd_console.c
Okay, thats right - should we rename it to "lcdputs" ?
Only thing for decission was, that existing commands are allready defined
within
lcd.c. But i've no problem to move it. What do you say? let's move?
>
> > + "print string on lcd-framebuffer",
> > + ""
> > +);
> > +
> >
/*--*/
> >
> > static int lcd_init(void *lcdbase)
> >
>
> --
> Regards,
> Nikita Kiryanov
best regards,
Hannes
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