Re: [U-Boot] [PATCH v2 07/10] dm: i2c: s3c24x0: adjust to dm-i2c api
Hello Simon, On 01/27/2015 04:13 AM, Simon Glass wrote: Hi Przemyslaw, On 26 January 2015 at 08:21, Przemyslaw Marczak wrote: This commit adjusts the s3c24x0 driver to new i2c api based on driver-model. The driver supports standard and high-speed i2c as previous. Tested on Trats2, Odroid U3, Arndale, Odroid XU3 Signed-off-by: Przemyslaw Marczak Cc: Simon Glass Cc: Heiko Schocher Cc: Minkyu Kang Tested on snow: Tested-by: Simon Glass This looks right to me, but I have a number of nits, mostly code that can be deleted, Please see below. If you can respin this I will pick it up. Thank you for the review, I will fix the issues and resend this today. Best regards, -- Przemyslaw Marczak Samsung R&D Institute Poland Samsung Electronics p.marc...@samsung.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Loading Linux Kernel without re-initializing hardware
Hi, I am working a customized PPC4040 board. One bootloader is running on this and loading QNX image. I am trying to load Linux Kernel on that board. Is it possible to use U-boot bootm command directly on different bootloader and load Linux? Board_info and cmdline struct can be populated on existing bootloader and pass to Kernel. Anything else do I need to take care, like TLB entry, fdt? Any pointer on this would help. Thanks in advance. -- Thanks & Regards; Rupam Kumar Sarma Mobile: 9008100955 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 22/23] x86: Add some documentation on how to port U-Boot on x86
Hi Simon, On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass wrote: > Some information has been gleaned on tools and procedures for porting > U-Boot to different x86 platforms. Add a few notes to start things off. > > Signed-off-by: Simon Glass > --- > Reviewed-by: Bin Meng A minor comment below. > doc/README.x86 | 63 > ++ > 1 file changed, 63 insertions(+) > > diff --git a/doc/README.x86 b/doc/README.x86 > index 809a291..0e4628a 100644 > --- a/doc/README.x86 > +++ b/doc/README.x86 > @@ -164,6 +164,69 @@ mtrr - List and set the Memory Type Range Registers > (MTRR). These are used to > mode to use. U-Boot sets up some reasonable values but you can > adjust then with this command. > > +Development Flow > + > + > +These notes are for those who want to port U-Boot to a new x86 platform. > + > +Since x86 CPUs boot from SPI flash, a SPI flash emulator is a good > investment. > +The Dediprog em100 can be used on Linux. The em100 tool is available here: > + > + http://review.coreboot.org/p/em100.git > + > +On Minnowboard Max the following command line can be used: > + > + sudo em100 -s -p LOW -d u-boot.rom -c W25Q64DW -r > + > +A suitable clip for connecting over the SPI flash chip is here: > + > + http://www.dediprog.com/pd/programmer-accessories/EM-TC-8 > + > +This allows you to override the SPI flash contents for development purposes. > +Typically you can write to the em100 in around 1200ms, considerably faster > +than programming the real flash device each time. The only important > +limitation of the em100 is that it only supports SPI bus speeds up to 20MHz. > +This means that images must be set to boot with that speed (Intel-specific > +feature). > + It would be better to document what this Intel-specific feature is in order to support this SPI bus frequency. > +If your chip/board uses an Intel Firmware Support Package (FSP) it is fairly > +easy to fit it in. You can follow the Minnowboard Max implementation, for > +example. Hopefully you will just need to create new files similar to those > +in arch/x86/cpu/baytrail which provide Bay Trail support. > + > +If you are not using an FSP you have more freedom and more responsibility. > +The ivybridge support works this way, although it still uses a ROM for > +graphics and still has binary blobs containing Intel code. You should aim to > +support all important peripherals on your platform including video and > storage. > +Use the device tree for configuration where possible. > + > +For the microcode you can create a suitable device tree file using the > +microcode tool: > + > + ./tools/microcode-tool -d microcode.dat create > + > +or if you only have header files and not the full Intel microcode.dat > database: > + > + ./tools/microcode-tool -H BAY_TRAIL_FSP_KIT/Microcode/M0130673322.h \ > + -H BAY_TRAIL_FSP_KIT/Microcode/M0130679901.h \ > + create all > + > +These are written to arch/x86/dts/microcode/ by default. > + > +Note that it is possible to just add the micrcode for your CPU if you know > its > +model. U-Boot prints this information when it starts > + > + CPU: x86_64, vendor Intel, device 30673h > + > +so here we can use the M0130673322 file. > + > +If you platform can display POST codes on two little 7-segment displays on > +the board, then you can use post_code() calls from C or assembler to monitor > +boot progress. This can be good for debugging. > + > +If not, you can try to get serial working as early as possible. The early > +debug serial port may be useful here. See setup_early_uart() for an example. > + > TODO List > - > - Audio > -- Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 01/23] x86: Enhance the microcode tool to support header files as input
Hi Simon,
On Tue, Jan 27, 2015 at 9:22 AM, Simon Glass wrote:
> Sometimes microcode is delivered as a header file. Allow the tool to
> support this as well as collecting multiple microcode blocks into a
> single update.
>
> Signed-off-by: Simon Glass
> ---
Tested-by: Bin Meng
But please see my comments below.
> tools/microcode-tool.py | 90
> ++---
> 1 file changed, 70 insertions(+), 20 deletions(-)
>
> diff --git a/tools/microcode-tool.py b/tools/microcode-tool.py
> index 003716d..71c2e91 100755
> --- a/tools/microcode-tool.py
> +++ b/tools/microcode-tool.py
> @@ -76,6 +76,35 @@ def ParseFile(fname):
> microcodes[name] = Microcode(name, data)
> return date, license_text, microcodes
>
> +def ParseHeaderFiles(fname_list):
> +"""Parse a list of header files and return the component parts
> +
> +Args:
> +fname_list: List of files to parse
> +Returns:
> +date: String containing date from the file's header
> +license_text: List of text lines for the license file
> +microcodes: List of Microcode objects from the file
> +"""
> +microcodes = {}
> +license_text = []
> +date = ''
> +name = None
> +for fname in fname_list:
> +name = os.path.basename(fname).lower()
> +name = os.path.splitext(name)[0]
> +data = []
> +with open(fname) as fd:
> +for line in fd:
> +line = line.rstrip()
> +
> +# Omit anything after the last comma
> +words = line.split(',')[:-1]
> +data += [word + ',' for word in words]
> +microcodes[name] = Microcode(name, data)
> +return date, license_text, microcodes
> +
> +
> def List(date, microcodes, model):
> """List the available microcode chunks
>
> @@ -129,13 +158,13 @@ def FindMicrocode(microcodes, model):
> break
> return found, tried
>
> -def CreateFile(date, license_text, mcode, outfile):
> +def CreateFile(date, license_text, mcodes, outfile):
> """Create a microcode file in U-Boot's .dtsi format
>
> Args:
> date: String containing date of original microcode file
> license:List of text lines for the license file
> -mcode: Microcode object to write
> +mcodes: Microcode objects to write (normally only 1)
> outfile:Filename to write to ('-' for stdout)
> """
> out = '''/*%s
> @@ -159,15 +188,22 @@ intel,processor-flags = <%#x>;
> data = <%s
> \t>;'''
> words = ''
> -for i in range(len(mcode.words)):
> -if not (i & 3):
> -words += '\n'
> -val = mcode.words[i]
> -# Change each word so it will be little-endian in the FDT
> -# This data is needed before RAM is available on some platforms so we
> -# cannot do an endianness swap on boot.
> -val = struct.unpack("I", val))[0]
> -words += '\t%#010x' % val
> +add_comments = len(mcodes) > 1
> +for mcode in mcodes:
> +if add_comments:
> +words += '\n/* %s */' % mcode.name
> +for i in range(len(mcode.words)):
> +if not (i & 3):
> +words += '\n'
> +val = mcode.words[i]
> +# Change each word so it will be little-endian in the FDT
> +# This data is needed before RAM is available on some platforms
> so
> +# we cannot do an endianness swap on boot.
> +val = struct.unpack("I", val))[0]
> +words += '\t%#010x' % val
> +
> +# Use the first microcode for the headers
> +mcode = mcodes[0]
>
> # Take care to avoid adding a space before a tab
> text = ''
> @@ -187,8 +223,8 @@ data = <%s
> print >> sys.stderr, "Creating directory '%s'" %
> MICROCODE_DIR
> os.makedirs(MICROCODE_DIR)
> outfile = os.path.join(MICROCODE_DIR, mcode.name + '.dtsi')
> -print >> sys.stderr, "Writing microcode for '%s' to '%s'" % (
> - mcode.name, outfile)
> +print >> sys.stderr, "Writing microcode for '%s' to '%s'" % (
> +', '.join([mcode.name for mcode in mcodes]), outfile)
> with open(outfile, 'w') as fd:
> print >> fd, out % tuple(args)
>
> @@ -198,8 +234,12 @@ def MicrocodeTool():
> parser = OptionParser()
> parser.add_option('-d', '--mcfile', type='string', action='store',
> help='Name of microcode.dat file')
> +parser.add_option('-H', '--headerfile', type='string', action='append',
> +help='Name of .h file containing microcode')
> parser.add_option('-m', '--model', type='string', action='store',
> -help='Model name to extract')
> +help="Model name to extract ('all' for all)")
> +parser.add_option('-M', '--multiple', type='string', action='store',
> +
Re: [U-Boot] [PATCH 04/23] x86: video: Enable video for Minnowboard Max
On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass wrote:
> This board uses a new PCI ID.
>
> Signed-off-by: Simon Glass
> ---
>
> drivers/video/vesa_fb.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/video/vesa_fb.c b/drivers/video/vesa_fb.c
> index 3dacafd..3a0fea2 100644
> --- a/drivers/video/vesa_fb.c
> +++ b/drivers/video/vesa_fb.c
> @@ -23,6 +23,7 @@ struct pci_device_id vesa_video_ids[] = {
> { .vendor = 0x1002, .device = 0x5159 },
> { .vendor = 0x1002, .device = 0x4752 },
> { .vendor = 0x1002, .device = 0x5452 },
> + { .vendor = 0x8086, .device = 0x0f31 },
> {},
> };
>
> --
Reviewed-by: Bin Meng
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Re: [U-Boot] [PATCH 03/23] x86: pci: Add PCI IDs for Minnowboard Max
On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass wrote: > This board includes a few IDs we have not seen before. > > Signed-off-by: Simon Glass > --- > > include/pci_ids.h | 5 + > 1 file changed, 5 insertions(+) > > diff --git a/include/pci_ids.h b/include/pci_ids.h > index 26f4748..1012abe 100644 > --- a/include/pci_ids.h > +++ b/include/pci_ids.h > @@ -1346,6 +1346,7 @@ > > #define PCI_VENDOR_ID_REALTEK 0x10ec > #define PCI_DEVICE_ID_REALTEK_8139 0x8139 > +#define PCI_DEVICE_ID_REALTEK_8168 0x8168 > > #define PCI_VENDOR_ID_XILINX 0x10ee > #define PCI_DEVICE_ID_RME_DIGI96 0x3fc0 > @@ -2594,6 +2595,10 @@ > #define PCI_DEVICE_ID_INTEL_I960 0x0960 > #define PCI_DEVICE_ID_INTEL_I960RM 0x0962 > #define PCI_DEVICE_ID_INTEL_CENTERTON_ILB 0x0c60 > +#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDIO0x0f15 > +#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDCARD 0x0f16 > +#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC 0x0f1c > +#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA0x0f23 > #define PCI_DEVICE_ID_INTEL_82541ER0x1078 > #define PCI_DEVICE_ID_INTEL_82541GI_LF 0x107c > #define PCI_DEVICE_ID_INTEL_82542 0x1000 > -- Reviewed-by: Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 02/23] pci: Add a function to find a device by class
Hi Simon,
On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass wrote:
> There is an existing function prototype in the header file but it is not
> implemented. Implement something similar.
>
> Signed-off-by: Simon Glass
> ---
>
> drivers/pci/pci.c | 38 ++
> include/pci.h | 3 +--
> 2 files changed, 39 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index 950a247..215a092 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -15,6 +15,7 @@
> #include
>
> #include
> +#include
> #include
> #include
> #include
> @@ -236,6 +237,43 @@ pci_dev_t pci_find_devices(struct pci_device_id *ids,
> int index)
> return -1;
> }
>
> +pci_dev_t pci_find_class(uint find_class, int index)
> +{
> + int bus;
> + int devnum;
> + pci_dev_t bdf;
> + uint32_t class;
> +
> + for (bus = 0; bus <= pci_last_busno(); bus++) {
> + for (devnum = 0; devnum < PCI_MAX_PCI_DEVICES-1; devnum++) {
space after PCI_MAX_PCI_DEVICES and before 1?
> + pci_read_config_dword(PCI_BDF(bus, devnum, 0),
> + PCI_CLASS_REVISION, &class);
> + if (class >> 16 == 0x)
> + continue;
> +
> + for (bdf = PCI_BDF(bus, devnum, 0);
> + bdf <= PCI_BDF(bus, devnum,
> + PCI_MAX_PCI_FUNCTIONS - 1);
> + bdf += PCI_BDF(0, 0, 1)) {
> + pci_read_config_dword(bdf, PCI_CLASS_REVISION,
> + &class);
> + class >>= 8;
> +
> + if (class != find_class)
> + continue;
> + if (index) {
> + index--;
> + continue;
It is worth to have a comment block to explain the 'index' logic here.
> + }
> + /* Return index'th controller. */
> + return bdf;
> + }
> + }
> + }
> +
> + return -ENODEV;
> +}
> +
> pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int
> index)
> {
> struct pci_device_id ids[2] = { {}, {0, 0} };
> diff --git a/include/pci.h b/include/pci.h
> index 4fbb8f6..004a048 100644
> --- a/include/pci.h
> +++ b/include/pci.h
> @@ -644,8 +644,7 @@ extern int pciauto_config_device(struct pci_controller
> *hose, pci_dev_t dev);
>
> extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device,
> int index);
> extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index);
> -extern pci_dev_t pci_find_class(int wanted_class, int wanted_sub_code,
> - int wanted_prog_if, int index);
> +pci_dev_t pci_find_class(unsigned int find_class, int index);
>
> extern int pci_hose_config_device(struct pci_controller *hose,
> pci_dev_t dev,
> --
Regards,
Bin
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Re: [U-Boot] [PATCH 05/23] usb: pci: Use pci_find_class() to find the device
On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass wrote:
> Use the new utility function instead of local code.
>
> Signed-off-by: Simon Glass
> ---
>
> drivers/usb/host/ehci-pci.c | 53
> +
> 1 file changed, 1 insertion(+), 52 deletions(-)
>
> diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c
> index 991b199..b9eabc5 100644
> --- a/drivers/usb/host/ehci-pci.c
> +++ b/drivers/usb/host/ehci-pci.c
> @@ -34,57 +34,6 @@ static struct pci_device_id ehci_pci_ids[] = {
> {0, 0}
> };
> #else
> -static pci_dev_t ehci_find_class(int index)
> -{
> - int bus;
> - int devnum;
> - pci_dev_t bdf;
> - uint32_t class;
> -
> - for (bus = 0; bus <= pci_last_busno(); bus++) {
> - for (devnum = 0; devnum < PCI_MAX_PCI_DEVICES-1; devnum++) {
> - pci_read_config_dword(PCI_BDF(bus, devnum, 0),
> - PCI_CLASS_REVISION, &class);
> - if (class >> 16 == 0x)
> - continue;
> -
> - for (bdf = PCI_BDF(bus, devnum, 0);
> - bdf <= PCI_BDF(bus, devnum,
> - PCI_MAX_PCI_FUNCTIONS - 1);
> - bdf += PCI_BDF(0, 0, 1)) {
> - pci_read_config_dword(bdf, PCI_CLASS_REVISION,
> - &class);
> - class >>= 8;
> - /*
> -* Here be dragons! In case we have multiple
> -* PCI EHCI controllers, this function will
> -* be called multiple times as well. This
> -* function will scan the PCI busses, always
> -* starting from bus 0, device 0, function 0,
> -* until it finds an USB controller. The USB
> -* stack gives us an 'index' of a controller
> -* that is currently being registered, which
> -* is a number, starting from 0 and growing
> -* in ascending order as controllers are
> added.
> -* To avoid probing the same controller in tne
> -* subsequent runs of this function, we will
> -* skip 'index - 1' detected controllers and
> -* report the index'th controller.
> -*/
> - if (class != PCI_CLASS_SERIAL_USB_EHCI)
> - continue;
> - if (index) {
> - index--;
> - continue;
> - }
> - /* Return index'th controller. */
> - return bdf;
> - }
> - }
> - }
> -
> - return -ENODEV;
> -}
> #endif
>
> /*
> @@ -102,7 +51,7 @@ int ehci_hcd_init(int index, enum usb_init_type init,
> #ifdef CONFIG_PCI_EHCI_DEVICE
> pdev = pci_find_devices(ehci_pci_ids, CONFIG_PCI_EHCI_DEVICE);
> #else
> - pdev = ehci_find_class(index);
> + pdev = pci_find_class(PCI_CLASS_SERIAL_USB_EHCI, index);
> #endif
> if (pdev < 0) {
> printf("EHCI host controller not found\n");
> --
Reviewed-by: Bin Meng
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Re: [U-Boot] [PATCH 06/23] usb: pci: Add XHCI driver for PCI
On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass wrote:
> Add a driver which locates the available XHCI controllers on the PCI bus
> and makes them available.
>
> Signed-off-by: Simon Glass
> ---
>
> drivers/usb/host/Makefile | 1 +
> drivers/usb/host/xhci-pci.c | 60
> +
> 2 files changed, 61 insertions(+)
> create mode 100644 drivers/usb/host/xhci-pci.c
>
> diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
> index c11b551..66d6e9a 100644
> --- a/drivers/usb/host/Makefile
> +++ b/drivers/usb/host/Makefile
> @@ -47,6 +47,7 @@ obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o
> obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
> obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
> obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
> +obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
>
> # designware
> obj-$(CONFIG_USB_DWC2) += dwc2.o
> diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c
> new file mode 100644
> index 000..361fcce
> --- /dev/null
> +++ b/drivers/usb/host/xhci-pci.c
> @@ -0,0 +1,60 @@
> +/*
> + * Copyright (c) 2015, Google, Inc
> + * Written by Simon Glass
> + * All rights reserved.
> + *
> + * SPDX-License-Identifier:GPL-2.0
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +
> +#include "xhci.h"
> +
> +/*
> + * Create the appropriate control structures to manage a new XHCI host
> + * controller.
> + */
> +int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr,
> + struct xhci_hcor **ret_hcor)
> +{
> + struct xhci_hccr *hccr;
> + struct xhci_hcor *hcor;
> + pci_dev_t pdev;
> + uint32_t cmd;
> + int len;
> +
> + pdev = pci_find_class(PCI_CLASS_SERIAL_USB_XHCI, index);
> + if (pdev < 0) {
> + printf("XHCI host controller not found\n");
> + return -1;
> + }
> +
> + hccr = (struct xhci_hccr *)pci_map_bar(pdev,
> + PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
> + len = HC_LENGTH(xhci_readl(&hccr->cr_capbase));
> + hcor = (struct xhci_hcor *)((uint32_t)hccr + len);
> +
> + debug("XHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d\n",
> + (uint32_t)hccr, (uint32_t)hcor, len);
> +
> + *ret_hccr = hccr;
> + *ret_hcor = hcor;
> +
> + /* enable busmaster */
> + pci_read_config_dword(pdev, PCI_COMMAND, &cmd);
> + cmd |= PCI_COMMAND_MASTER;
> + pci_write_config_dword(pdev, PCI_COMMAND, cmd);
> +
> + return 0;
> +}
> +
> +/*
> + * Destroy the appropriate control structures corresponding * to the XHCI
> host
> + * controller
> + */
> +void xhci_hcd_stop(int index)
> +{
> +}
> --
Reviewed-by: Bin Meng
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Re: [U-Boot] [PATCH 07/23] x86: Add an option to enabling building a ROM file
Hi Simon, On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass wrote: > Rather than requiring the Makefile to be modified, provide a build option to > enable the ROM to be built. > > We cannot do this by default since it requires binary blobs. Without these > the build will fail. > > Signed-off-by: Simon Glass > --- > > Makefile | 5 +++-- > doc/README.x86 | 10 ++ > 2 files changed, 9 insertions(+), 6 deletions(-) > > diff --git a/Makefile b/Makefile > index a876f1f..c6e4ad1 100644 > --- a/Makefile > +++ b/Makefile > @@ -729,8 +729,9 @@ ALL-$(CONFIG_SPL) += $(CONFIG_SPL_TARGET:"%"=%) > endif > ALL-$(CONFIG_REMAKE_ELF) += u-boot.elf > > -# We can't do this yet due to the need for binary blobs > -# ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom > +ifneq ($(BUILD_ROM),) > +ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom > +endif > > # enable combined SPL/u-boot/dtb rules for tegra > ifneq ($(CONFIG_TEGRA),) > diff --git a/doc/README.x86 b/doc/README.x86 > index 7df8cc5..809a291 100644 > --- a/doc/README.x86 > +++ b/doc/README.x86 > @@ -51,9 +51,11 @@ Building ROM version of U-Boot (hereafter referred to as > u-boot.rom) is a > little bit tricky, as generally it requires several binary blobs which are > not > shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build > is > not turned on by default in the U-Boot source tree. Firstly, you need turn it > -on by uncommenting the following line in the main U-Boot Makefile: > +on by enabling the ROM board: the ROM 'board', or the ROM 'build'? > > -# ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom > +$ export BUILD_ROM=y > + > +This tells the Makefile to build u-boot.rom as a target. > > Link-specific instructions: > > @@ -126,11 +128,11 @@ Make sure 0x111 matches CONFIG_SYS_TEXT_BASE and > 0x1110015 matches the > symbol address of _start (in arch/x86/cpu/start.S). > > If you want to use ELF as the coreboot payload, change U-Boot configuration > to > -use CONFIG_OF_EMBED. > +use CONFIG_OF_EMBED instead of CONFIG_OF_SEPARATE. > > CPU Microcode > - > -Modern CPU usually requires a special bit stream called microcode [5] to be > +Modern CPUs usually requires a special bit stream called microcode [5] to be I don't understand the changes. 'CPUs requires'? > loaded on the processor after power up in order to function properly. U-Boot > has already integrated these as hex dumps in the source tree. > > -- Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 08/23] x86: Make MMCONF_BASE_ADDRESS common across x86
Hi Simon, On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass wrote: > This setting will be used by more than just ivybridge so make it common. > > Signed-off-by: Simon Glass > --- > > arch/x86/Kconfig | 12 > board/google/chromebook_link/Kconfig | 1 - > 2 files changed, 12 insertions(+), 1 deletion(-) > > diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig > index 90e828a..1523c91 100644 > --- a/arch/x86/Kconfig > +++ b/arch/x86/Kconfig > @@ -356,4 +356,16 @@ source "board/google/chromebook_link/Kconfig" > > source "board/intel/crownbay/Kconfig" > > +config MMCONF_BASE_ADDRESS This name is sort of generic. How about PCIE_ECAM_BASE? > + hex > +default 0xe000 > + help > + This is the address of PCI configuration space. It can be set up Would it be better to write: This is the memory-mapped address of PCI configuration space, which is only available through Enhanced Configuration Access Mechanism (ECAM) with PCI Express. > + amost anywhere. Before it is set up, it is possible to access PCI Typo of 'almost'. How about it is 'only' possible? > + configuration space through I/O access, but memory access is more > + convenient. Using this, PCI can be scanned and configured. This > + should be set to a region that does not conflict with memory > + assigned to PCI devices - i.e. the memory and prefetch regions, as > + passed to pci_set_region(). > + > endmenu > diff --git a/board/google/chromebook_link/Kconfig > b/board/google/chromebook_link/Kconfig > index 33a31f3..948af59 100644 > --- a/board/google/chromebook_link/Kconfig > +++ b/board/google/chromebook_link/Kconfig > @@ -23,7 +23,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy > select BOARD_ROMSIZE_KB_8192 > > config MMCONF_BASE_ADDRESS > - hex > default 0xf000 > > config EARLY_POST_CROS_EC > -- Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] sunxi: rsb: Add sun9i (A80 support)
Add support for the A80 to the rsb code.
Signed-off-by: Hans de Goede
---
arch/arm/cpu/armv7/sunxi/Makefile | 2 ++
arch/arm/cpu/armv7/sunxi/rsb.c | 11 +++
arch/arm/include/asm/arch-sunxi/cpu_sun9i.h | 5 +++--
arch/arm/include/asm/arch-sunxi/gpio.h | 8
4 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile
b/arch/arm/cpu/armv7/sunxi/Makefile
index 6602cda..f8a6bea 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -18,8 +18,10 @@ obj-y+= usbc.o
endif
obj-$(CONFIG_MACH_SUN6I) += prcm.o
obj-$(CONFIG_MACH_SUN8I) += prcm.o
+obj-$(CONFIG_MACH_SUN9I) += prcm.o
obj-$(CONFIG_MACH_SUN6I) += p2wi.o
obj-$(CONFIG_MACH_SUN8I) += rsb.o
+obj-$(CONFIG_MACH_SUN9I) += rsb.o
obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o
diff --git a/arch/arm/cpu/armv7/sunxi/rsb.c b/arch/arm/cpu/armv7/sunxi/rsb.c
index b72bb9d..55e9433 100644
--- a/arch/arm/cpu/armv7/sunxi/rsb.c
+++ b/arch/arm/cpu/armv7/sunxi/rsb.c
@@ -18,12 +18,23 @@
static void rsb_cfg_io(void)
{
+#ifdef CONFIG_MACH_SUN8I
sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL0_R_RSB_SCK);
sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL1_R_RSB_SDA);
sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
+#elif defined CONFIG_MACH_SUN9I
+ sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN0_R_RSB_SCK);
+ sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN1_R_RSB_SDA);
+ sunxi_gpio_set_pull(SUNXI_GPN(0), 1);
+ sunxi_gpio_set_pull(SUNXI_GPN(1), 1);
+ sunxi_gpio_set_drv(SUNXI_GPN(0), 2);
+ sunxi_gpio_set_drv(SUNXI_GPN(1), 2);
+#else
+#error unsupported MACH_SUNXI
+#endif
}
static void rsb_set_clk(void)
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
index a2a7839..04889c5 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
@@ -73,7 +73,6 @@
#define SUNXI_CCM_BASE (REGS_APB0_BASE + 0x)
#define SUNXI_CCMMODULE_BASE (REGS_APB0_BASE + 0x0400)
#define SUNXI_PIO_BASE (REGS_APB0_BASE + 0x0800)
-#define SUNXI_R_PIO_BASE (0x08002C00)
#define SUNXI_TIMER_BASE (REGS_APB0_BASE + 0x0C00)
#define SUNXI_PWM_BASE (REGS_APB0_BASE + 0x1400)
#define SUNXI_LRADC_BASE (REGS_APB0_BASE + 0x1800)
@@ -92,8 +91,10 @@
#define SUNXI_TWI4_BASE(REGS_APB1_BASE + 0x3800)
/* RCPUS Module */
-#define SUNXI_RPRCM_BASE (REGS_RCPUS_BASE + 0x1400)
+#define SUNXI_PRCM_BASE(REGS_RCPUS_BASE + 0x1400)
#define SUNXI_R_UART_BASE (REGS_RCPUS_BASE + 0x2800)
+#define SUNXI_R_PIO_BASE (REGS_RCPUS_BASE + 0x2c00)
+#define SUNXI_RSB_BASE (REGS_RCPUS_BASE + 0x3400)
/* Misc. */
#define SUNXI_BROM_BASE0x /* 32K */
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h
b/arch/arm/include/asm/arch-sunxi/gpio.h
index 3db7fd3..d2d48de 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -45,9 +45,13 @@
*
* sun8i has 1 bank:
* PL0 - PL11
+ *
+ * sun9i has 3 banks:
+ * PL0 - PL9 | PM0 - PM15 | PN0 - PN1
*/
#define SUNXI_GPIO_L 11
#define SUNXI_GPIO_M 12
+#define SUNXI_GPIO_N 13
struct sunxi_gpio {
u32 cfg[4];
@@ -129,6 +133,7 @@ enum sunxi_gpio_number {
#define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr))
#define SUNXI_GPL(_nr) (SUNXI_GPIO_L_START + (_nr))
#define SUNXI_GPM(_nr) (SUNXI_GPIO_M_START + (_nr))
+#define SUNXI_GPN(_nr) (SUNXI_GPIO_L_START + (_nr))
#define SUNXI_GPAXP0(_nr) (SUNXI_GPIO_AXP0_START + (_nr))
@@ -190,6 +195,9 @@ enum sunxi_gpio_number {
#define SUN8I_GPL2_R_UART_TX 2
#define SUN8I_GPL3_R_UART_RX 2
+#define SUN9I_GPN0_R_RSB_SCK 3
+#define SUN9I_GPN1_R_RSB_SDA3
+
/* GPIO pin pull-up/down config */
#define SUNXI_GPIO_PULL_DISABLE0
#define SUNXI_GPIO_PULL_UP 1
--
2.1.0
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[U-Boot] [PATCH 2/2] sunxi: rsb: Move rsb_set_device_mode() call to rsb_init()
It turns out that the device_mode_data is rsn specific, rather then slave
specific, so integrate the rsb_set_device_mode() call into rsb_init().
Signed-off-by: Hans de Goede
---
arch/arm/cpu/armv7/sunxi/rsb.c| 11 ---
arch/arm/include/asm/arch-sunxi/rsb.h | 4 ++--
drivers/power/axp221.c| 4 +---
include/axp221.h | 1 -
4 files changed, 11 insertions(+), 9 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/rsb.c b/arch/arm/cpu/armv7/sunxi/rsb.c
index 55e9433..b00befb 100644
--- a/arch/arm/cpu/armv7/sunxi/rsb.c
+++ b/arch/arm/cpu/armv7/sunxi/rsb.c
@@ -16,6 +16,8 @@
#include
#include
+static int rsb_set_device_mode(void);
+
static void rsb_cfg_io(void)
{
#ifdef CONFIG_MACH_SUN8I
@@ -53,7 +55,7 @@ static void rsb_set_clk(void)
writel((cd_odly << 8) | div, &rsb->ccr);
}
-void rsb_init(void)
+int rsb_init(void)
{
struct sunxi_rsb_reg * const rsb =
(struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
@@ -65,6 +67,8 @@ void rsb_init(void)
writel(RSB_CTRL_SOFT_RST, &rsb->ctrl);
rsb_set_clk();
+
+ return rsb_set_device_mode();
}
static int rsb_await_trans(void)
@@ -99,13 +103,14 @@ static int rsb_await_trans(void)
return ret;
}
-int rsb_set_device_mode(u32 device_mode_data)
+static int rsb_set_device_mode(void)
{
struct sunxi_rsb_reg * const rsb =
(struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
unsigned long tmo = timer_get_us() + 100;
- writel(RSB_DMCR_DEVICE_MODE_START | device_mode_data, &rsb->dmcr);
+ writel(RSB_DMCR_DEVICE_MODE_START | RSB_DMCR_DEVICE_MODE_DATA,
+ &rsb->dmcr);
while (readl(&rsb->dmcr) & RSB_DMCR_DEVICE_MODE_START) {
if (timer_get_us() > tmo)
diff --git a/arch/arm/include/asm/arch-sunxi/rsb.h
b/arch/arm/include/asm/arch-sunxi/rsb.h
index 95a595a..a893466 100644
--- a/arch/arm/include/asm/arch-sunxi/rsb.h
+++ b/arch/arm/include/asm/arch-sunxi/rsb.h
@@ -37,6 +37,7 @@ struct sunxi_rsb_reg {
#define RSB_STAT_TERR_INT (1 << 1)
#define RSB_STAT_LBSY_INT (1 << 2)
+#define RSB_DMCR_DEVICE_MODE_DATA 0x7c3e00
#define RSB_DMCR_DEVICE_MODE_START (1 << 31)
#define RSB_CMD_BYTE_WRITE 0x4e
@@ -46,8 +47,7 @@ struct sunxi_rsb_reg {
#define RSB_DEVADDR_RUNTIME_ADDR(x)((x) << 16)
#define RSB_DEVADDR_DEVICE_ADDR(x) ((x) << 0)
-void rsb_init(void);
-int rsb_set_device_mode(u32 device_mode_data);
+int rsb_init(void);
int rsb_set_device_address(u16 device_addr, u16 runtime_addr);
int rsb_write(const u16 runtime_device_addr, const u8 reg_addr, u8 data);
int rsb_read(const u16 runtime_device_addr, const u8 reg_addr, u8 *data);
diff --git a/drivers/power/axp221.c b/drivers/power/axp221.c
index 58bbd45..3e07f23 100644
--- a/drivers/power/axp221.c
+++ b/drivers/power/axp221.c
@@ -29,9 +29,7 @@ static int pmic_bus_init(void)
#else
int ret;
- rsb_init();
-
- ret = rsb_set_device_mode(AXP223_DEVICE_MODE_DATA);
+ ret = rsb_init();
if (ret)
return ret;
diff --git a/include/axp221.h b/include/axp221.h
index 6f24a61..a20e25c 100644
--- a/include/axp221.h
+++ b/include/axp221.h
@@ -12,7 +12,6 @@
#define AXP223_DEVICE_ADDR 0x3a3
#define AXP223_RUNTIME_ADDR 0x2d
-#define AXP223_DEVICE_MODE_DATA 0x7c3e00
/* Page 0 addresses */
#define AXP221_CHIP_ID 0x03
--
2.1.0
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Re: [U-Boot] [PATCH 09/23] x86: video: Allow video ROM execution to fall back to the other method
Hi Simon,
On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass wrote:
> If the BIOS emulator is not available, allow use of native execution if
> available, and vice versa. This can be controlled by the caller.
>
> Signed-off-by: Simon Glass
> ---
>
Reviewed-by: Bin Meng
But please see a minor comment below.
> arch/x86/cpu/ivybridge/gma.c | 3 ++-
> drivers/pci/pci_rom.c| 32 +---
> drivers/video/vesa_fb.c | 6 +++---
> include/pci_rom.h| 15 +--
> 4 files changed, 43 insertions(+), 13 deletions(-)
>
> diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c
> index 6cf9654..821ea25 100644
> --- a/arch/x86/cpu/ivybridge/gma.c
> +++ b/arch/x86/cpu/ivybridge/gma.c
> @@ -758,7 +758,8 @@ int gma_func0_init(pci_dev_t dev, struct pci_controller
> *hose,
>
> #ifdef CONFIG_VIDEO
> start = get_timer(0);
> - ret = pci_run_vga_bios(dev, int15_handler, false);
> + ret = pci_run_vga_bios(dev, int15_handler, PCI_ROM_USE_NATIVE |
> + PCI_ROM_ALLOW_FALLBACK);
> debug("BIOS ran in %lums\n", get_timer(start));
> #endif
> /* Post VBIOS init */
> diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c
> index eb76591..0796179 100644
> --- a/drivers/pci/pci_rom.c
> +++ b/drivers/pci/pci_rom.c
> @@ -228,11 +228,12 @@ int vbe_get_video_info(struct graphic_device *gdev)
> #endif
> }
>
> -int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), bool emulate)
> +int pci_run_vga_bios(pci_dev_t dev, int (*int15_handler)(void), int
> exec_method)
> {
> struct pci_rom_header *rom, *ram;
> int vesa_mode = -1;
> uint16_t class;
> + bool emulate;
> int ret;
>
> /* Only execute VGA ROMs */
> @@ -262,6 +263,29 @@ int pci_run_vga_bios(pci_dev_t dev, int
> (*int15_handler)(void), bool emulate)
> vesa_mode = CONFIG_FRAMEBUFFER_VESA_MODE;
> #endif
> debug("Selected vesa mode %#x\n", vesa_mode);
> +
> + if (exec_method & PCI_ROM_USE_NATIVE) {
> +#ifdef CONFIG_X86
> + emulate = false;
> +#else
> + if (!(exec_method & PCI_ROM_ALLOW_FALLBACK)) {
> + printf("BIOS native execution is only available on
> x86\n");
> + return -ENOSYS;
> + }
> + emulate = true;
> +#endif
> + } else {
> +#ifdef CONFIG_BIOSEMU
> + emulate = true;
> +#else
> + if (!(exec_method & PCI_ROM_ALLOW_FALLBACK)) {
> + printf("BIOS emulation not available - see
> CONFIG_BIOSEMU\n");
> + return -ENOSYS;
> + }
> + emulate = false;
> +#endif
> + }
> +
> if (emulate) {
> #ifdef CONFIG_BIOSEMU
> BE_VGAInfo *info;
> @@ -274,9 +298,6 @@ int pci_run_vga_bios(pci_dev_t dev, int
> (*int15_handler)(void), bool emulate)
> vesa_mode, &mode_info);
> if (ret)
> return ret;
> -#else
> - printf("BIOS emulation not available - see CONFIG_BIOSEMU\n");
> - return -ENOSYS;
> #endif
> } else {
> #ifdef CONFIG_X86
> @@ -284,9 +305,6 @@ int pci_run_vga_bios(pci_dev_t dev, int
> (*int15_handler)(void), bool emulate)
>
> bios_run_on_x86(dev, (unsigned long)ram, vesa_mode,
> &mode_info);
> -#else
> - printf("BIOS native execution is only available on x86\n");
> - return -ENOSYS;
> #endif
> }
> debug("Final vesa mode %#x\n", mode_info.video_mode);
> diff --git a/drivers/video/vesa_fb.c b/drivers/video/vesa_fb.c
> index 3a0fea2..9164f8d 100644
> --- a/drivers/video/vesa_fb.c
> +++ b/drivers/video/vesa_fb.c
> @@ -42,8 +42,8 @@ void *video_hw_init(void)
> printf("no card detected\n");
> return NULL;
> }
> - printf("bdf %x\n", dev);
> - ret = pci_run_vga_bios(dev, NULL, true);
> + ret = pci_run_vga_bios(dev, NULL, PCI_ROM_USE_NATIVE |
> + PCI_ROM_ALLOW_FALLBACK);
> if (ret) {
> printf("failed to run video BIOS: %d\n", ret);
> return NULL;
> @@ -59,7 +59,7 @@ void *video_hw_init(void)
> sprintf(gdev->modeIdent, "%dx%dx%d", gdev->winSizeX, gdev->winSizeY,
> bits_per_pixel);
> printf("%s\n", gdev->modeIdent);
> - debug("Framex buffer at %x\n", gdev->pciBase);
> + debug("Frame buffer at %x\n", gdev->pciBase);
>
> return (void *)gdev;
> }
> diff --git a/include/pci_rom.h b/include/pci_rom.h
> index 4ba36eb..d24c52a 100644
> --- a/include/pci_rom.h
> +++ b/include/pci_rom.h
> @@ -33,14 +33,25 @@ struct pci_rom_data {
> uint16_t reserved_2;
> };
>
> +/*
> + * Determines which execution met
Re: [U-Boot] [PATCH 10/23] x86: bootstage: Add time measurement for vesa start-up
On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass wrote:
> Since we must run a PCI BIOS ROM, and this can take a calamitous amount of
> time, measure it using bootstage.
>
> Signed-off-by: Simon Glass
> ---
>
> drivers/video/vesa_fb.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/video/vesa_fb.c b/drivers/video/vesa_fb.c
> index 9164f8d..47f824a 100644
> --- a/drivers/video/vesa_fb.c
> +++ b/drivers/video/vesa_fb.c
> @@ -42,8 +42,10 @@ void *video_hw_init(void)
> printf("no card detected\n");
> return NULL;
> }
> + bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display");
> ret = pci_run_vga_bios(dev, NULL, PCI_ROM_USE_NATIVE |
>PCI_ROM_ALLOW_FALLBACK);
> + bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD);
> if (ret) {
> printf("failed to run video BIOS: %d\n", ret);
> return NULL;
> --
Reviewed-by: Bin Meng
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Re: [U-Boot] [PATCH 11/23] x86: Move common FSP code into a common location
Hi Simon,
On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass wrote:
> Signed-off-by: Simon Glass
> ---
>
Nice to see the existing FSP support codes are common for new platforms.
Reviewed-by: Bin Meng
Tested-by: Bin Meng
> arch/x86/cpu/queensbay/Makefile| 2 +-
> arch/x86/cpu/queensbay/fsp_configs.c | 2 +-
> arch/x86/cpu/queensbay/tnc.c | 2 +-
> arch/x86/cpu/queensbay/tnc_dram.c | 2 +-
> arch/x86/cpu/queensbay/tnc_pci.c | 2 +-
> arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_api.h| 0
> arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_bootmode.h | 0
> arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_ffs.h| 0
> arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_fv.h | 0
> arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_hob.h| 0
> arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_infoheader.h | 0
> arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_platform.h | 0
> arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_support.h| 2 +-
> arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_types.h | 0
> arch/x86/lib/Makefile | 1 +
> arch/x86/lib/cmd_hob.c | 2 +-
> arch/x86/lib/fsp/Makefile | 7 +++
> arch/x86/{cpu/queensbay => lib/fsp}/fsp_support.c | 2 +-
> 18 files changed, 16 insertions(+), 8 deletions(-)
> rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_api.h (100%)
> rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_bootmode.h (100%)
> rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_ffs.h (100%)
> rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_fv.h (100%)
> rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_hob.h (100%)
> rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_infoheader.h (100%)
> rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_platform.h (100%)
> rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_support.h (99%)
> rename arch/x86/include/asm/{arch-queensbay => }/fsp/fsp_types.h (100%)
> create mode 100644 arch/x86/lib/fsp/Makefile
> rename arch/x86/{cpu/queensbay => lib/fsp}/fsp_support.c (99%)
>
> diff --git a/arch/x86/cpu/queensbay/Makefile b/arch/x86/cpu/queensbay/Makefile
> index 2c2ec01..b3e7d87 100644
> --- a/arch/x86/cpu/queensbay/Makefile
> +++ b/arch/x86/cpu/queensbay/Makefile
> @@ -5,5 +5,5 @@
> #
>
> obj-y += tnc_car.o tnc_dram.o tnc.o topcliff.o
> -obj-y += fsp_configs.o fsp_support.o
> +obj-y += fsp_configs.o
> obj-$(CONFIG_PCI) += tnc_pci.o
> diff --git a/arch/x86/cpu/queensbay/fsp_configs.c
> b/arch/x86/cpu/queensbay/fsp_configs.c
> index af28e45..78bc966 100644
> --- a/arch/x86/cpu/queensbay/fsp_configs.c
> +++ b/arch/x86/cpu/queensbay/fsp_configs.c
> @@ -6,7 +6,7 @@
> */
>
> #include
> -#include
> +#include
>
> void update_fsp_upd(struct upd_region *fsp_upd)
> {
> diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
> index 8637cdc..f9b3bfa 100644
> --- a/arch/x86/cpu/queensbay/tnc.c
> +++ b/arch/x86/cpu/queensbay/tnc.c
> @@ -9,7 +9,7 @@
> #include
> #include
> #include
> -#include
> +#include
> #include
>
> static void unprotect_spi_flash(void)
> diff --git a/arch/x86/cpu/queensbay/tnc_dram.c
> b/arch/x86/cpu/queensbay/tnc_dram.c
> index df79a39..4c0a7c8 100644
> --- a/arch/x86/cpu/queensbay/tnc_dram.c
> +++ b/arch/x86/cpu/queensbay/tnc_dram.c
> @@ -5,7 +5,7 @@
> */
>
> #include
> -#include
> +#include
> #include
> #include
>
> diff --git a/arch/x86/cpu/queensbay/tnc_pci.c
> b/arch/x86/cpu/queensbay/tnc_pci.c
> index 39bff49..9b0b725 100644
> --- a/arch/x86/cpu/queensbay/tnc_pci.c
> +++ b/arch/x86/cpu/queensbay/tnc_pci.c
> @@ -7,7 +7,7 @@
> #include
> #include
> #include
> -#include
> +#include
>
> DECLARE_GLOBAL_DATA_PTR;
>
> diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_api.h
> b/arch/x86/include/asm/fsp/fsp_api.h
> similarity index 100%
> rename from arch/x86/include/asm/arch-queensbay/fsp/fsp_api.h
> rename to arch/x86/include/asm/fsp/fsp_api.h
> diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_bootmode.h
> b/arch/x86/include/asm/fsp/fsp_bootmode.h
> similarity index 100%
> rename from arch/x86/include/asm/arch-queensbay/fsp/fsp_bootmode.h
> rename to arch/x86/include/asm/fsp/fsp_bootmode.h
> diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_ffs.h
> b/arch/x86/include/asm/fsp/fsp_ffs.h
> similarity index 100%
> rename from arch/x86/include/asm/arch-queensbay/fsp/fsp_ffs.h
> rename to arch/x86/include/asm/fsp/fsp_ffs.h
> diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_fv.h
> b/arch/x86/include/asm/fsp/fsp_fv.h
> similarity index 100%
> rename from arch/x86/include/asm/arch-queensbay/fsp/fsp_fv.h
> rename to arch/x86/include/asm/fsp/fsp_fv.h
> diff --git a/arc
Re: [U-Boot] [GIT PULL] Zynq SoC changes v2
On Mon, Jan 26, 2015 at 09:09:11AM +0100, Michal Simek wrote: > Hi Tom, > > here is the second pull request for Zynq. > I have tested all patches by buildman(log below) with a kernel toolchain > > [u-boot]$ arm-unknown-linux-gnueabi-gcc --version > arm-unknown-linux-gnueabi-gcc (GCC) 4.6.3 > Copyright (C) 2011 Free Software Foundation, Inc. > > I have put together that config.mk patch and enabling neon instructions. > > I have also added that 2 patches for serial. Zynq is only platfrom > which is using this driver. > > Thanks, > Michal > > [u-boot]$ ./tools/buildman/buildman -b xnext/zynq zynq -sSe > boards.cfg is up to date. Nothing to do. > Summary of 15 commits for 7 boards (7 threads, 2 jobs per thread) > 01: Prepare v2015.01 > 02: ARM: zynq: Enable the Neon instructions >arm: (for 7/7 boards) all +51.4 bss -0.6 rodata +20.0 > spl/u-boot-spl:all +52.0 spl/u-boot-spl:rodata +20.0 spl/u-boot-spl:text > +32.0 text +32.0 > 03: ARM: zynq: Remove empty line > 04: ARM: zynq: ddrc: Setup half of memory only for ECC case >arm: (for 7/7 boards) all +12.6 bss +0.6 text +12.0 > 05: ARM: zynq: slcr: Dont modify the reserved bits > 06: ARM: zynq: List nand, qspi and jtag boot modes >arm: (for 7/7 boards) spl/u-boot-spl:all +47.4 spl/u-boot-spl:text > +47.4 > 07: ARM: zynq: List qspi, smc and nand baseaddresses > 08: ARM: zynq: Show board information by default >arm: (for 7/7 boards) all +66.3 bss +2.3 data +4.0 rodata +20.0 > text +40.0 > 09: ARM: zynq: Use CMD_FS_GENERIC >arm: (for 7/7 boards) all +972.0 bss -0.6 data +80.0 rodata +732.6 > text +160.0 > 10: ARM: zynq: Group ethernet configuration options together >arm: (for 7/7 boards) all +26.3 bss +0.6 rodata +2.3 text +23.4 > 11: ARM: zynq: provide config option to select emio > 12: ARM: zynq: Enable DFU functionality in zynq >arm: (for 7/7 boards) all +1804167.1 bss +1797574.9 data +181.7 > rodata +822.0 text +5588.6 > 13: ARM: zynq: Add USB lthor download protocol support >arm: (for 7/7 boards) all +2383.7 bss +148.6 data +54.9 rodata > +447.7 text +1732.6 > 14: serial: zynq: Use global baudrate instead of hardcoded one >arm: (for 7/7 boards) all -26.3 bss -2.3 rodata -8.0 > spl/u-boot-spl:all -16.0 spl/u-boot-spl:rodata -8.0 spl/u-boot-spl:text > -8.0 text -16.0 > 15: serial: Extend structure comments with register offset > (no errors to report) > > > The following changes since commit 92fa7f53f1f3f03296f8ffb14bdf1baefab83368: > > Prepare v2015.01 (2015-01-12 09:39:08 -0500) > > are available in the git repository at: > > git://www.denx.de/git/u-boot-microblaze.git zynq > > for you to fetch changes up to a2425e6207d7c75906a15410f4c8c0a5d0519349: > > serial: Extend structure comments with register offset (2015-01-26 08:55:59 > +0100) > Applied to u-boot/master, thanks! > ___ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Please pull u-boot-fsl-qoriq master
On Sat, Jan 24, 2015 at 09:44:14AM -0600, York Sun wrote: > Tom, > > The following changes since commit 37b608a52dcb13312a4f7ccea199cd6bac76d298: > > powerpc: remove icecube_5200, Lite5200, cpci5200, mecp5200, pf5200 > (2015-01-23 > 16:56:09 -0500) > > are available in the git repository at: > > git://git.denx.de/u-boot-fsl-qoriq.git master > > for you to fetch changes up to 41ba57d0c7968506ddcc71604bd39131acf6ee23: > > fsl/ls1021qds: Add deep sleep support (2015-01-24 09:12:32 -0600) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Please pull u-boot-marvell master
On Sun, Jan 25, 2015 at 11:42:24PM +, Luka Perkov wrote: > Hi Albert, > > this series contains pending kirkwood patches that have been posted on > the mailing list for some time now. > > > The following changes since commit 37b608a52dcb13312a4f7ccea199cd6bac76d298: > > powerpc: remove icecube_5200, Lite5200, cpci5200, mecp5200, pf5200 > (2015-01-23 16:56:09 -0500) > > are available in the git repository at: > > git://git.denx.de/u-boot-marvell.git master > > for you to fetch changes up to 361b3d8613f57e137a9048ef69e58e9bcaf51b78: > > marvell: kirkwood: guruplug refresh for newer kernel (2015-01-26 00:25:29 > +0100) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PULL] u-boot-atmel/master -> u-boot/master
On Mon, Jan 26, 2015 at 11:12:34AM +0100, Andreas Bießmann wrote: > The following changes since commit ab77f24119e80257de4ab017b877f92f96980562: > > Merge branch 'master' of git://git.denx.de/u-boot-ti (2015-01-16 10:25:01 > -0500) > > are available in the git repository at: > > > git://git.denx.de/u-boot-atmel.git master > > for you to fetch changes up to 52305a829cd927aca2eb4a15985c567e98f562b9: > > ARM: atmel: sama5d4_xplained: enable usb ethernet gadget (2015-01-19 > 15:02:48 +0100) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Please pull u-boot-x86
On Mon, Jan 26, 2015 at 12:51:40PM -0700, Simon Glass wrote: > Hi Tom, > > The following changes since commit 37b608a52dcb13312a4f7ccea199cd6bac76d298: > > powerpc: remove icecube_5200, Lite5200, cpci5200, mecp5200, pf5200 > (2015-01-23 16:56:09 -0500) > > are available in the git repository at: > > http://git.denx.de/u-boot-x86.git > > for you to fetch changes up to e43ade3749ff10bc313f33bf23705465e4163896: > > x86: config: chromebook_link: Enable environment (2015-01-24 06:13:46 -0700) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 14/23] x86: Move common FSP functions into a common file
Hi Simon,
On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass wrote:
> Since these board functions seem to be the same for all boards which use
> FSP, move them into a common file. We can adjust this later if future FSPs
> need more flexibility.
>
> Signed-off-by: Simon Glass
> ---
>
> arch/x86/cpu/queensbay/tnc.c | 27
> arch/x86/cpu/queensbay/tnc_pci.c | 15 ---
> arch/x86/cpu/queensbay/topcliff.c | 32 +-
> arch/x86/include/asm/u-boot-x86.h | 17
> arch/x86/lib/fsp/Makefile | 1 +
> arch/x86/lib/fsp/fsp_common.c | 88
> +++
> 6 files changed, 108 insertions(+), 72 deletions(-)
> create mode 100644 arch/x86/lib/fsp/fsp_common.c
>
> diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
> index f9b3bfa..30ab725 100644
> --- a/arch/x86/cpu/queensbay/tnc.c
> +++ b/arch/x86/cpu/queensbay/tnc.c
> @@ -43,30 +43,3 @@ int arch_cpu_init(void)
>
> return 0;
> }
> -
> -int print_cpuinfo(void)
> -{
> - post_code(POST_CPU_INFO);
> - return default_print_cpuinfo();
> -}
> -
> -void reset_cpu(ulong addr)
> -{
> - /* cold reset */
> - outb(0x06, PORT_RESET);
> -}
> -
> -void board_final_cleanup(void)
> -{
> - u32 status;
> -
> - /* call into FspNotify */
> - debug("Calling into FSP (notify phase INIT_PHASE_BOOT): ");
> - status = fsp_notify(NULL, INIT_PHASE_BOOT);
> - if (status != FSP_SUCCESS)
> - debug("fail, error code %x\n", status);
> - else
> - debug("OK\n");
> -
> - return;
> -}
> diff --git a/arch/x86/cpu/queensbay/tnc_pci.c
> b/arch/x86/cpu/queensbay/tnc_pci.c
> index 9b0b725..6c291f9 100644
> --- a/arch/x86/cpu/queensbay/tnc_pci.c
> +++ b/arch/x86/cpu/queensbay/tnc_pci.c
> @@ -44,18 +44,3 @@ void board_pci_setup_hose(struct pci_controller *hose)
>
> hose->region_count = 4;
> }
> -
> -int board_pci_post_scan(struct pci_controller *hose)
> -{
> - u32 status;
> -
> - /* call into FspNotify */
> - debug("Calling into FSP (notify phase INIT_PHASE_PCI): ");
> - status = fsp_notify(NULL, INIT_PHASE_PCI);
> - if (status != FSP_SUCCESS)
> - debug("fail, error code %x\n", status);
> - else
> - debug("OK\n");
> -
> - return 0;
> -}
> diff --git a/arch/x86/cpu/queensbay/topcliff.c
> b/arch/x86/cpu/queensbay/topcliff.c
> index b01422a..25032cc 100644
> --- a/arch/x86/cpu/queensbay/topcliff.c
> +++ b/arch/x86/cpu/queensbay/topcliff.c
> @@ -5,43 +5,15 @@
> */
>
> #include
> -#include
> -#include
> -#include
> #include
> -#include
>
> static struct pci_device_id mmc_supported[] = {
> { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_0 },
> { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_1 },
> - { }
> };
>
> int cpu_mmc_init(bd_t *bis)
> {
> - struct sdhci_host *mmc_host;
> - pci_dev_t devbusfn;
> - u32 iobase;
> - int ret;
> - int i;
> -
> - for (i = 0; i < ARRAY_SIZE(mmc_supported); i++) {
> - devbusfn = pci_find_devices(mmc_supported, i);
> - if (devbusfn == -1)
> - return -ENODEV;
> -
> - mmc_host = (struct sdhci_host *)malloc(sizeof(struct
> sdhci_host));
> - if (!mmc_host)
> - return -ENOMEM;
> -
> - mmc_host->name = "Topcliff SDHCI";
> - pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase);
> - mmc_host->ioaddr = (void *)iobase;
> - mmc_host->quirks = 0;
> - ret = add_sdhci(mmc_host, 0, 0);
> - if (ret)
> - return ret;
> - }
> -
> - return 0;
> + return fsp_cpu_mmc_init("Topcliff SDHCI", mmc_supported,
> + ARRAY_SIZE(mmc_supported));
> }
I don't think this function should be moved to fsp_common.c as it has
nothing related to FSP. We can move this whole function to
drivers/mmc/, something like intel_mmc.c or intel_sdhc.c.
> diff --git a/arch/x86/include/asm/u-boot-x86.h
> b/arch/x86/include/asm/u-boot-x86.h
> index b98afa8..44c24ff 100644
> --- a/arch/x86/include/asm/u-boot-x86.h
> +++ b/arch/x86/include/asm/u-boot-x86.h
> @@ -45,6 +45,23 @@ ulong board_get_usable_ram_top(ulong total_size);
> void dram_init_banksize(void);
> int default_print_cpuinfo(void);
>
> +struct pci_device_id;
> +
> +/**
> + * fsp_cpu_mmc_init() - set up PCI MMC devices
> + *
> + * This finds all the matching PCI IDs and sets them up as MMC devices.
> + *
> + * @name: Name to use for devices
> + * @mmc_supported: PCI IDs to search for
> + * @num_ids: Number of elements in @mmc_supported
> + */
> +int fsp_cpu_mmc_init(const char *name, struct pci_device_id mmc_supported[],
> +int num_ids);
> +
> +/* Set up a UART which can be used with printch(), printhex8(), etc. */
> +i
Re: [U-Boot] [PATCH 12/23] x86: Adjust the FSP types slightly
On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass wrote:
> To avoid casts, find_fsp_header() should return a pointer. Add asmlinkage
> to two API functions which use that convention. UPD_TERMINATOR is common
> so move it into a common file.
>
> Signed-off-by: Simon Glass
> ---
>
> arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h | 2 --
> arch/x86/include/asm/fsp/fsp_api.h| 6 --
> arch/x86/include/asm/fsp/fsp_support.h| 4 +++-
> arch/x86/lib/fsp/fsp_support.c| 4 ++--
> 4 files changed, 9 insertions(+), 7 deletions(-)
>
> diff --git a/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h
> b/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h
> index bce58b1..3c57558 100644
> --- a/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h
> +++ b/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h
> @@ -10,8 +10,6 @@
> #ifndef __VPDHEADER_H__
> #define __VPDHEADER_H__
>
> -#define UPD_TERMINATOR 0x55AA
> -
> struct __packed upd_region {
> u64 sign; /* Offset 0x */
> u64 reserved; /* Offset 0x0008 */
> diff --git a/arch/x86/include/asm/fsp/fsp_api.h
> b/arch/x86/include/asm/fsp/fsp_api.h
> index a9d7156..2d34d13 100644
> --- a/arch/x86/include/asm/fsp/fsp_api.h
> +++ b/arch/x86/include/asm/fsp/fsp_api.h
> @@ -8,6 +8,8 @@
> #ifndef __FSP_API_H__
> #define __FSP_API_H__
>
> +#include
> +
> /*
> * FspInit continuation function prototype.
> * Control will be returned to this callback function after FspInit API call.
> @@ -47,9 +49,9 @@ struct fsp_notify_params {
> };
>
> /* FspInit API function prototype */
> -typedef u32 (*fsp_init_f)(struct fsp_init_params *params);
> +typedef asmlinkage u32 (*fsp_init_f)(struct fsp_init_params *params);
>
> /* FspNotify API function prototype */
> -typedef u32 (*fsp_notify_f)(struct fsp_notify_params *params);
> +typedef asmlinkage u32 (*fsp_notify_f)(struct fsp_notify_params *params);
>
> #endif
> diff --git a/arch/x86/include/asm/fsp/fsp_support.h
> b/arch/x86/include/asm/fsp/fsp_support.h
> index 6329cfe..c6c7dc0 100644
> --- a/arch/x86/include/asm/fsp/fsp_support.h
> +++ b/arch/x86/include/asm/fsp/fsp_support.h
> @@ -26,6 +26,8 @@ struct shared_data {
>
> #define FSP_LOWMEM_BASE0x10UL
> #define FSP_HIGHMEM_BASE 0x1ULL
> +#define UPD_TERMINATOR 0x55AA
> +
>
> /**
> * FSP Continuation assembly helper routine
> @@ -61,7 +63,7 @@ void fsp_continue(struct shared_data *shared_data, u32
> status,
> *
> * @retval: the offset of FSP header. If signature is invalid, returns 0.
> */
> -u32 find_fsp_header(void);
> +struct fsp_header *find_fsp_header(void);
>
> /**
> * FSP initialization wrapper function.
> diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c
> index f6ae85a..bf37807 100644
> --- a/arch/x86/lib/fsp/fsp_support.c
> +++ b/arch/x86/lib/fsp/fsp_support.c
> @@ -30,7 +30,7 @@ static bool compare_guid(const struct efi_guid *guid1,
> return false;
> }
>
> -u32 __attribute__((optimize("O0"))) find_fsp_header(void)
> +struct fsp_header *__attribute__((optimize("O0"))) find_fsp_header(void)
> {
> /*
> * This function may be called before the a stack is established,
> @@ -84,7 +84,7 @@ u32 __attribute__((optimize("O0"))) find_fsp_header(void)
> fsp = 0;
> }
>
> - return (u32)fsp;
> + return (struct fsp_header *)fsp;
> }
>
> void fsp_continue(struct shared_data *shared_data, u32 status, void
> *hob_list)
> --
Reviewed-by: Bin Meng
Tested-by: Bin Meng
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Re: [U-Boot] [PATCH 13/23] x86: Make CAR and DRAM FSP code common
On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass wrote:
> For now this code seems to be the same for all FSP platforms. Make it
> common until we see what differences are required.
>
> Signed-off-by: Simon Glass
> ---
>
> arch/x86/cpu/queensbay/Makefile | 2 +-
> arch/x86/lib/fsp/Makefile | 2 ++
> arch/x86/{cpu/queensbay/tnc_car.S => lib/fsp/fsp_car.S} | 0
> arch/x86/{cpu/queensbay/tnc_dram.c => lib/fsp/fsp_dram.c} | 0
> 4 files changed, 3 insertions(+), 1 deletion(-)
> rename arch/x86/{cpu/queensbay/tnc_car.S => lib/fsp/fsp_car.S} (100%)
> rename arch/x86/{cpu/queensbay/tnc_dram.c => lib/fsp/fsp_dram.c} (100%)
>
> diff --git a/arch/x86/cpu/queensbay/Makefile b/arch/x86/cpu/queensbay/Makefile
> index b3e7d87..d8761fd 100644
> --- a/arch/x86/cpu/queensbay/Makefile
> +++ b/arch/x86/cpu/queensbay/Makefile
> @@ -4,6 +4,6 @@
> # SPDX-License-Identifier: GPL-2.0+
> #
>
> -obj-y += tnc_car.o tnc_dram.o tnc.o topcliff.o
> obj-y += fsp_configs.o
> +obj-y += tnc.o topcliff.o
> obj-$(CONFIG_PCI) += tnc_pci.o
> diff --git a/arch/x86/lib/fsp/Makefile b/arch/x86/lib/fsp/Makefile
> index 1b9b0e2..3a2bac0 100644
> --- a/arch/x86/lib/fsp/Makefile
> +++ b/arch/x86/lib/fsp/Makefile
> @@ -4,4 +4,6 @@
> # SPDX-License-Identifier: GPL-2.0+
> #
>
> +obj-y += fsp_car.o
> +obj-y += fsp_dram.o
> obj-y += fsp_support.o
> diff --git a/arch/x86/cpu/queensbay/tnc_car.S b/arch/x86/lib/fsp/fsp_car.S
> similarity index 100%
> rename from arch/x86/cpu/queensbay/tnc_car.S
> rename to arch/x86/lib/fsp/fsp_car.S
> diff --git a/arch/x86/cpu/queensbay/tnc_dram.c b/arch/x86/lib/fsp/fsp_dram.c
> similarity index 100%
> rename from arch/x86/cpu/queensbay/tnc_dram.c
> rename to arch/x86/lib/fsp/fsp_dram.c
> --
Reviewed-by: Bin Meng
Tested-by: Bin Meng
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Re: [U-Boot] [PATCH 15/23] x86: Remove unnecessary casts and fix comment typos
On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass wrote:
> Tidy up the FSP support code a little.
>
> Signed-off-by: Simon Glass
> ---
>
> arch/x86/lib/fsp/fsp_support.c | 10 +-
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c
> index bf37807..8b639f7 100644
> --- a/arch/x86/lib/fsp/fsp_support.c
> +++ b/arch/x86/lib/fsp/fsp_support.c
> @@ -124,25 +124,25 @@ void fsp_init(u32 stack_top, u32 boot_mode, void
> *nvs_buf)
> struct fsp_init_params *params_ptr;
> struct upd_region *fsp_upd;
>
> - fsp_hdr = (struct fsp_header *)find_fsp_header();
> + fsp_hdr = find_fsp_header();
> if (fsp_hdr == NULL) {
> /* No valid FSP info header was found */
> panic("Invalid FSP header");
> }
>
> - fsp_upd = (struct upd_region *)&shared_data.fsp_upd;
> + fsp_upd = &shared_data.fsp_upd;
> memset(&rt_buf, 0, sizeof(struct fspinit_rtbuf));
>
> /* Reserve a gap in stack top */
> rt_buf.common.stack_top = (u32 *)stack_top - 32;
> rt_buf.common.boot_mode = boot_mode;
> - rt_buf.common.upd_data = (struct upd_region *)fsp_upd;
> + rt_buf.common.upd_data = fsp_upd;
>
> /* Get VPD region start */
> fsp_vpd = (struct vpd_region *)(fsp_hdr->img_base +
> fsp_hdr->cfg_region_off);
>
> - /* Verifify the VPD data region is valid */
> + /* Verify the VPD data region is valid */
> assert((fsp_vpd->img_rev == VPD_IMAGE_REV) &&
>(fsp_vpd->sign == VPD_IMAGE_ID));
>
> @@ -150,7 +150,7 @@ void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf)
> memcpy(fsp_upd, (void *)(fsp_hdr->img_base + fsp_vpd->upd_offset),
>sizeof(struct upd_region));
>
> - /* Verifify the UPD data region is valid */
> + /* Verify the UPD data region is valid */
> assert(fsp_upd->terminator == UPD_TERMINATOR);
>
> /* Override any UPD setting if required */
> --
Reviewed-by: Bin Meng
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[U-Boot] [PATCH v3 02/12] arndale: config: disable max77686 support
There is no MAX77686 pmic on this board, so the driver support should be removed. Signed-off-by: Przemyslaw Marczak Cc: Minkyu Kang --- include/configs/arndale.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/configs/arndale.h b/include/configs/arndale.h index d68993b..3ad4a9b 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -51,8 +51,6 @@ /* PMIC */ #define CONFIG_PMIC #define CONFIG_POWER_I2C -#define CONFIG_POWER_MAX77686 - #define CONFIG_PREBOOT -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 00/12] exynos: enable dm i2c
This patchset adds support to driver model i2c api for Exynos i2c driver. Few boards are using this driver, but the board peripherals are not ported to the new api yet. So the CONFIG_DM_I2C_COMPAT is enabled. Switch to dm i2c is currentlly not possible for the few devices like Trats2, Universal C210, S5P Goni, because ir require soft i2c support. For Odroid U3, the compatiblility layer is enabled, because it uses only one pmic driver, which soon is going to be moved to dm i2c with the dm pmic framework. The i2c dm compatibility layer is also enabled for Exynos5 boards, which should be removed after moving the i2c drivers to driver model. The main change from the previous version is: - non-required code cleanup after Simon Glass comments - add new pinmux flag for Exynos - split commit with s3c i2c status timeout change - fix build error for u-boot-dm/master Przemyslaw Marczak (12): dm: i2c-uclass-compat: fix missed argument arndale: config: disable max77686 support exynos5250: config: disable max77686 driver smdk5250: config: enable max77686 driver support exynos4: dts: add missing i2c properties arndale: dts: add missing i2c aliases exynos5: pinmux: check flag for i2c config i2c: s3c24x0: reduce transmission status timeout dm: i2c: s3c24x0: adjust to dm-i2c api odroid u3: dts: add missing i2c aliases odroid u3: enable dm i2c support exynos5: enable dm i2c arch/arm/cpu/armv7/exynos/pinmux.c| 27 +++- arch/arm/dts/exynos4.dtsi | 24 ++- arch/arm/dts/exynos4412-odroid.dts| 7 + arch/arm/dts/exynos5250-arndale.dts | 8 + arch/arm/include/asm/arch-exynos/pinmux.h | 3 + board/samsung/odroid/odroid.c | 14 +- drivers/i2c/i2c-uclass-compat.c | 2 +- drivers/i2c/s3c24x0_i2c.c | 241 -- include/configs/arndale.h | 2 - include/configs/exynos5-common.h | 7 +- include/configs/exynos5250-common.h | 3 - include/configs/odroid.h | 5 +- include/configs/smdk5250.h| 2 + 13 files changed, 258 insertions(+), 87 deletions(-) -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 01/12] dm: i2c-uclass-compat: fix missed argument
This patch fixes build error for CONFIG_DM_I2C_COMPAT. In i2c_get_chip_for_busnum() call, one of argument was missed, which was offset_len. Now it is set to 'alen' as previous. Signed-off-by: Przemyslaw Marczak --- drivers/i2c/i2c-uclass-compat.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/i2c-uclass-compat.c b/drivers/i2c/i2c-uclass-compat.c index 11239da..841ce05 100644 --- a/drivers/i2c/i2c-uclass-compat.c +++ b/drivers/i2c/i2c-uclass-compat.c @@ -17,7 +17,7 @@ static int i2c_compat_get_device(uint chip_addr, int alen, struct dm_i2c_chip *chip; int ret; - ret = i2c_get_chip_for_busnum(cur_busnum, chip_addr, devp); + ret = i2c_get_chip_for_busnum(cur_busnum, chip_addr, alen, devp); if (ret) return ret; chip = dev_get_parent_platdata(*devp); -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 09/12] dm: i2c: s3c24x0: adjust to dm-i2c api
This commit adjusts the s3c24x0 driver to new i2c api
based on driver-model. The driver supports standard
and high-speed i2c as previous.
Tested on Trats2, Odroid U3, Arndale, Odroid XU3
Signed-off-by: Przemyslaw Marczak
Tested-by: Simon Glass
Cc: Simon Glass
Cc: Heiko Schocher
Cc: Minkyu Kang
---
Changes v2:
- use consistent return values on errors
- decrease transaction status timeout, because the previous one was too big
Changes v3:
- change of timeout move to new commit
- use pinmux hs mode flag
- remove unused code
---
drivers/i2c/s3c24x0_i2c.c | 237 +-
1 file changed, 194 insertions(+), 43 deletions(-)
diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c
index 3129c7f..b4ee33f 100644
--- a/drivers/i2c/s3c24x0_i2c.c
+++ b/drivers/i2c/s3c24x0_i2c.c
@@ -9,8 +9,9 @@
* as they seem to have the same I2C controller inside.
* The different address mapping is handled by the s3c24xx.h files below.
*/
-
#include
+#include
+#include
#include
#if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
#include
@@ -121,13 +122,23 @@
#define CONFIG_MAX_I2C_NUM 1
#endif
+DECLARE_GLOBAL_DATA_PTR;
+
/*
* For SPL boot some boards need i2c before SDRAM is initialised so force
* variables to live in SRAM
*/
+#ifdef CONFIG_SYS_I2C
static struct s3c24x0_i2c_bus i2c_bus[CONFIG_MAX_I2C_NUM]
__attribute__((section(".data")));
+#endif
+
+enum exynos_i2c_type {
+ EXYNOS_I2C_STD,
+ EXYNOS_I2C_HS,
+};
+#ifdef CONFIG_SYS_I2C
/**
* Get a pointer to the given bus index
*
@@ -147,6 +158,7 @@ static struct s3c24x0_i2c_bus *get_bus(unsigned int bus_idx)
debug("Undefined bus: %d\n", bus_idx);
return NULL;
}
+#endif
#if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
static int GetI2CSDA(void)
@@ -251,6 +263,7 @@ static void ReadWriteByte(struct s3c24x0_i2c *i2c)
writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon);
}
+#ifdef CONFIG_SYS_I2C
static struct s3c24x0_i2c *get_base_i2c(int bus)
{
#ifdef CONFIG_EXYNOS4
@@ -267,6 +280,7 @@ static struct s3c24x0_i2c *get_base_i2c(int bus)
return s3c24x0_get_base_i2c();
#endif
}
+#endif
static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
{
@@ -326,7 +340,7 @@ static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus
*i2c_bus)
return 0;
}
}
- return -1;
+ return -EINVAL;
}
static void hsi2c_ch_init(struct s3c24x0_i2c_bus *i2c_bus)
@@ -398,18 +412,20 @@ static void exynos5_i2c_reset(struct s3c24x0_i2c_bus
*i2c_bus)
hsi2c_ch_init(i2c_bus);
}
+#ifdef CONFIG_SYS_I2C
static void s3c24x0_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
{
struct s3c24x0_i2c *i2c;
struct s3c24x0_i2c_bus *bus;
-
#if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
#endif
ulong start_time = get_timer(0);
- /* By default i2c channel 0 is the current bus */
i2c = get_base_i2c(adap->hwadapnr);
+ bus = &i2c_bus[adap->hwadapnr];
+ if (!bus)
+ return;
/*
* In case the previous transfer is still going, wait to give it a
@@ -470,12 +486,13 @@ static void s3c24x0_i2c_init(struct i2c_adapter *adap,
int speed, int slaveadd)
#endif
}
#endif /* #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) */
+
i2c_ch_init(i2c, speed, slaveadd);
- bus = &i2c_bus[adap->hwadapnr];
bus->active = true;
bus->regs = i2c;
}
+#endif /* CONFIG_SYS_I2C */
/*
* Poll the appropriate bit of the fifo status register until the interface is
@@ -698,20 +715,27 @@ static int hsi2c_read(struct exynos5_hsi2c *i2c,
return rv;
}
+#ifdef CONFIG_SYS_I2C
static unsigned int s3c24x0_i2c_set_bus_speed(struct i2c_adapter *adap,
- unsigned int speed)
+ unsigned int speed)
+#else
+static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
+#endif
{
struct s3c24x0_i2c_bus *i2c_bus;
+#ifdef CONFIG_SYS_I2C
i2c_bus = get_bus(adap->hwadapnr);
if (!i2c_bus)
- return -1;
-
+ return -EFAULT;
+#else
+ i2c_bus = dev_get_priv(dev);
+#endif
i2c_bus->clock_frequency = speed;
if (i2c_bus->is_highspeed) {
if (hsi2c_get_clk_details(i2c_bus))
- return -1;
+ return -EFAULT;
hsi2c_ch_init(i2c_bus);
} else {
i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency,
@@ -721,17 +745,6 @@ static unsigned int s3c24x0_i2c_set_bus_speed(struct
i2c_adapter *adap,
return 0;
}
-#ifdef CONFIG_EXYNOS5
-static void exynos_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
-{
- /* This will override th
[U-Boot] [PATCH v3 11/12] odroid u3: enable dm i2c support
This patch enables CONFIG_DM_I2C and also CONFIG_DM_I2C_COMPAT.
The last one should be removed when the dm pmic framework will
be finished.
Signed-off-by: Przemyslaw Marczak
Acked-by: Simon Glass
Cc: Minkyu Kang
---
Changes v2:
- new patch
---
board/samsung/odroid/odroid.c | 14 +-
include/configs/odroid.h | 5 ++---
2 files changed, 3 insertions(+), 16 deletions(-)
diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c
index b7d2381..e3517f2 100644
--- a/board/samsung/odroid/odroid.c
+++ b/board/samsung/odroid/odroid.c
@@ -415,15 +415,6 @@ static int pmic_init_max77686(void)
return 0;
}
-#ifdef CONFIG_SYS_I2C_INIT_BOARD
-static void board_init_i2c(void)
-{
- /* I2C_0 */
- if (exynos_pinmux_config(PERIPH_ID_I2C0, PINMUX_FLAG_NONE))
- debug("I2C%d not configured\n", (I2C_0));
-}
-#endif
-
int exynos_early_init_f(void)
{
board_clock_init();
@@ -444,10 +435,7 @@ int exynos_init(void)
int exynos_power_init(void)
{
-#ifdef CONFIG_SYS_I2C_INIT_BOARD
- board_init_i2c();
-#endif
- pmic_init(I2C_0);
+ pmic_init(0);
pmic_init_max77686();
return 0;
diff --git a/include/configs/odroid.h b/include/configs/odroid.h
index 807e96b..9d5dbdc 100644
--- a/include/configs/odroid.h
+++ b/include/configs/odroid.h
@@ -177,12 +177,11 @@
/* I2C */
#define CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C
+#define CONFIG_DM_I2C
+#define CONFIG_DM_I2C_COMPAT
#define CONFIG_SYS_I2C_S3C24X0
#define CONFIG_SYS_I2C_S3C24X0_SPEED 10
#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0
-#define CONFIG_MAX_I2C_NUM 8
-#define CONFIG_SYS_I2C_INIT_BOARD
/* POWER */
#define CONFIG_POWER
--
1.9.1
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[U-Boot] [PATCH v3 04/12] smdk5250: config: enable max77686 driver support
This commit enable support for the above driver, which was disabled in common config. Signed-off-by: Przemyslaw Marczak Acked-by: Simon Glass Cc: Simon Glass Cc: Minkyu Kang --- include/configs/smdk5250.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h index 8395372..3b06d30 100644 --- a/include/configs/smdk5250.h +++ b/include/configs/smdk5250.h @@ -18,6 +18,8 @@ #include +/* PMIC */ +#define CONFIG_POWER_MAX77686 #define CONFIG_BOARD_COMMON #define CONFIG_ARCH_EARLY_INIT_R -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 07/12] exynos5: pinmux: check flag for i2c config
Some versions of Exynos5 supports High-Speed I2C,
on few interfaces, this change allows support this.
The new flag is: PINMUX_FLAG_HS_MODE
Signed-off-by: Przemyslaw Marczak
Cc: Simon Glass
Cc: Akshay Saraswat
Cc: Minkyu Kang
---
Changes v3:
- add new flag: PINMUX_FLAG_HS_MODE
---
arch/arm/cpu/armv7/exynos/pinmux.c| 27 +++
arch/arm/include/asm/arch-exynos/pinmux.h | 3 +++
2 files changed, 22 insertions(+), 8 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c
b/arch/arm/cpu/armv7/exynos/pinmux.c
index 94d0297..be43e22 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -266,22 +266,33 @@ static void exynos5_sromc_config(int flags)
static void exynos5_i2c_config(int peripheral, int flags)
{
+ int func01, func23;
+
+/* High-Speed I2C */
+ if (flags & PINMUX_FLAG_HS_MODE) {
+ func01 = 4;
+ func23 = 4;
+ } else {
+ func01 = 2;
+ func23 = 3;
+ }
+
switch (peripheral) {
case PERIPH_ID_I2C0:
- gpio_cfg_pin(EXYNOS5_GPIO_B30, S5P_GPIO_FUNC(0x2));
- gpio_cfg_pin(EXYNOS5_GPIO_B31, S5P_GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5_GPIO_B30, S5P_GPIO_FUNC(func01));
+ gpio_cfg_pin(EXYNOS5_GPIO_B31, S5P_GPIO_FUNC(func01));
break;
case PERIPH_ID_I2C1:
- gpio_cfg_pin(EXYNOS5_GPIO_B32, S5P_GPIO_FUNC(0x2));
- gpio_cfg_pin(EXYNOS5_GPIO_B33, S5P_GPIO_FUNC(0x2));
+ gpio_cfg_pin(EXYNOS5_GPIO_B32, S5P_GPIO_FUNC(func01));
+ gpio_cfg_pin(EXYNOS5_GPIO_B33, S5P_GPIO_FUNC(func01));
break;
case PERIPH_ID_I2C2:
- gpio_cfg_pin(EXYNOS5_GPIO_A06, S5P_GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS5_GPIO_A07, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5_GPIO_A06, S5P_GPIO_FUNC(func23));
+ gpio_cfg_pin(EXYNOS5_GPIO_A07, S5P_GPIO_FUNC(func23));
break;
case PERIPH_ID_I2C3:
- gpio_cfg_pin(EXYNOS5_GPIO_A12, S5P_GPIO_FUNC(0x3));
- gpio_cfg_pin(EXYNOS5_GPIO_A13, S5P_GPIO_FUNC(0x3));
+ gpio_cfg_pin(EXYNOS5_GPIO_A12, S5P_GPIO_FUNC(func23));
+ gpio_cfg_pin(EXYNOS5_GPIO_A13, S5P_GPIO_FUNC(func23));
break;
case PERIPH_ID_I2C4:
gpio_cfg_pin(EXYNOS5_GPIO_A20, S5P_GPIO_FUNC(0x3));
diff --git a/arch/arm/include/asm/arch-exynos/pinmux.h
b/arch/arm/include/asm/arch-exynos/pinmux.h
index 0b91ef6..d0ae757 100644
--- a/arch/arm/include/asm/arch-exynos/pinmux.h
+++ b/arch/arm/include/asm/arch-exynos/pinmux.h
@@ -23,6 +23,9 @@ enum {
/* Flags for SROM controller */
PINMUX_FLAG_BANK= 3 << 0, /* bank number (0-3) */
PINMUX_FLAG_16BIT = 1 << 2, /* 16-bit width */
+
+ /* Flags for I2C */
+ PINMUX_FLAG_HS_MODE = 1 << 1, /* I2C High Speed Mode */
};
/**
--
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[U-Boot] [PATCH v3 10/12] odroid u3: dts: add missing i2c aliases
This change fixes i2c bus numbering for Odroid U3.
Signed-off-by: Przemyslaw Marczak
Acked-by: Simon Glass
Cc: Minkyu Kang
---
Changes v2:
- new patch
---
arch/arm/dts/exynos4412-odroid.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/dts/exynos4412-odroid.dts
b/arch/arm/dts/exynos4412-odroid.dts
index 29ad6ab..00a2917 100644
--- a/arch/arm/dts/exynos4412-odroid.dts
+++ b/arch/arm/dts/exynos4412-odroid.dts
@@ -16,6 +16,13 @@
aliases {
i2c0 = "/i2c@1386";
+ i2c1 = "/i2c@1387";
+ i2c2 = "/i2c@1388";
+ i2c3 = "/i2c@1389";
+ i2c4 = "/i2c@138a";
+ i2c5 = "/i2c@138b";
+ i2c6 = "/i2c@138c";
+ i2c7 = "/i2c@138d";
serial0 = "/serial@1380";
console = "/serial@1381";
mmc2 = "sdhci@1253";
--
1.9.1
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[U-Boot] [PATCH v3 03/12] exynos5250: config: disable max77686 driver
This PMIC is not common for all Exynos5250 based boards, so should be romoved from common config. Signed-off-by: Przemyslaw Marczak Acked-by: Simon Glass Cc: Simon Glass Cc: Minkyu Kang --- include/configs/exynos5250-common.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/include/configs/exynos5250-common.h b/include/configs/exynos5250-common.h index 6714313..ae0e5ff 100644 --- a/include/configs/exynos5250-common.h +++ b/include/configs/exynos5250-common.h @@ -28,9 +28,6 @@ #define CONFIG_SYS_INIT_SP_ADDRCONFIG_IRAM_STACK -/* PMIC */ -#define CONFIG_POWER_MAX77686 - /* Sound */ #define CONFIG_CMD_SOUND #ifdef CONFIG_CMD_SOUND -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 06/12] arndale: dts: add missing i2c aliases
Without this alias setting, the seq numbers
of the i2c devices are wrong.
Signed-off-by: Przemyslaw Marczak
Acked-by: Simon Glass
Cc: Simon Glass
Cc: Minkyu Kang
---
arch/arm/dts/exynos5250-arndale.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/dts/exynos5250-arndale.dts
b/arch/arm/dts/exynos5250-arndale.dts
index 202f2ea..21c0a21 100644
--- a/arch/arm/dts/exynos5250-arndale.dts
+++ b/arch/arm/dts/exynos5250-arndale.dts
@@ -15,6 +15,14 @@
compatible = "samsung,arndale", "samsung,exynos5250";
aliases {
+ i2c0 = "/i2c@12c6";
+ i2c1 = "/i2c@12c7";
+ i2c2 = "/i2c@12c8";
+ i2c3 = "/i2c@12c9";
+ i2c4 = "/i2c@12ca";
+ i2c5 = "/i2c@12cb";
+ i2c6 = "/i2c@12cc";
+ i2c7 = "/i2c@12cd";
serial0 = "/serial@12C2";
console = "/serial@12C2";
};
--
1.9.1
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[U-Boot] [PATCH v3 12/12] exynos5: enable dm i2c
This patch enables CONFIG_DM_I2C and also CONFIG_DM_I2C_COMPAT. The last one should be removed when all the i2c peripheral drivers will use dm i2c framework. Signed-off-by: Przemyslaw Marczak Acked-by: Simon Glass Cc: Akshay Saraswat Cc: Minkyu Kang Cc: Simon Glass --- Changes v2: - new patch --- include/configs/exynos5-common.h | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index ad63f3c..0ba39a2 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -126,12 +126,11 @@ #define SPI_FLASH_UBOOT_POS(CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE) /* I2C */ -#define CONFIG_SYS_I2C_INIT_BOARD -#define CONFIG_SYS_I2C +#define CONFIG_DM_I2C +#define CONFIG_DM_I2C_COMPAT #define CONFIG_CMD_I2C -#define CONFIG_SYS_I2C_S3C24X0_SPEED 10 /* 100 Kbps */ #define CONFIG_SYS_I2C_S3C24X0 -#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_I2C_S3C24X0_SPEED 10 /* 100 Kbps */ #define CONFIG_SYS_I2C_S3C24X0_SLAVE0x0 #define CONFIG_I2C_EDID -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 05/12] exynos4: dts: add missing i2c properties
This patch modify i2c nodes in exynos4.dtsi with:
- adding proper interrupts arrays for each i2c node,
which allows to decode periph id
- add reg address for each i2c node for i2c driver internal use
Signed-off-by: Przemyslaw Marczak
Acked-by: Simon Glass
Cc: Minkyu Kang
Cc: Lukasz Majewski
---
arch/arm/dts/exynos4.dtsi | 24
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/arch/arm/dts/exynos4.dtsi b/arch/arm/dts/exynos4.dtsi
index 3c983ed..7de227c 100644
--- a/arch/arm/dts/exynos4.dtsi
+++ b/arch/arm/dts/exynos4.dtsi
@@ -51,56 +51,64 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
- interrupts = <0 0 0>;
+ reg = <0x1386 0x100>;
+ interrupts = <0 56 0>;
};
i2c@1387 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
- interrupts = <1 1 0>;
+ reg = <0x1387 0x100>;
+ interrupts = <1 57 0>;
};
i2c@1388 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
- interrupts = <2 2 0>;
+ reg = <0x1388 0x100>;
+ interrupts = <2 58 0>;
};
i2c@1389 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
- interrupts = <3 3 0>;
+ reg = <0x1389 0x100>;
+ interrupts = <3 59 0>;
};
i2c@138a {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
- interrupts = <4 4 0>;
+ reg = <0x138a 0x100>;
+ interrupts = <4 60 0>;
};
i2c@138b {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
- interrupts = <5 5 0>;
+ reg = <0x138b 0x100>;
+ interrupts = <5 61 0>;
};
i2c@138c {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
- interrupts = <6 6 0>;
+ reg = <0x138c 0x100>;
+ interrupts = <6 62 0>;
};
i2c@138d {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
- interrupts = <7 7 0>;
+ reg = <0x138d 0x100>;
+ interrupts = <7 63 0>;
};
sdhci@1251 {
--
1.9.1
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[U-Boot] [PATCH v3 08/12] i2c: s3c24x0: reduce transmission status timeout
If no device is connected to I2C bus, the i2c probe command can take a lot of time for probe each address. This commit reduces the busy timeout to 10ms for standard and high speed modes. This doesn't break the transmission an also allow for properly probe the devices. Signed-off-by: Przemyslaw Marczak Changes v3: - new commit, after split the next one --- drivers/i2c/s3c24x0_i2c.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c index fd328f0..3129c7f 100644 --- a/drivers/i2c/s3c24x0_i2c.c +++ b/drivers/i2c/s3c24x0_i2c.c @@ -111,9 +111,9 @@ #define I2C_START_STOP 0x20/* START / STOP */ #define I2C_TXRX_ENA 0x10/* I2C Tx/Rx enable */ -#define I2C_TIMEOUT_MS 1000/* 1 second */ +#define I2C_TIMEOUT_MS 10 /* 10 ms */ -#defineHSI2C_TIMEOUT_US 10 /* 100 ms, finer granularity */ +#defineHSI2C_TIMEOUT_US 1 /* 10 ms, finer granularity */ /* To support VCMA9 boards and other who dont define max_i2c_num */ -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 00/12] exynos: enable dm i2c
Hello Simon, On 01/27/2015 01:36 PM, Przemyslaw Marczak wrote: This patchset adds support to driver model i2c api for Exynos i2c driver. Few boards are using this driver, but the board peripherals are not ported to the new api yet. So the CONFIG_DM_I2C_COMPAT is enabled. Switch to dm i2c is currentlly not possible for the few devices like Trats2, Universal C210, S5P Goni, because ir require soft i2c support. For Odroid U3, the compatiblility layer is enabled, because it uses only one pmic driver, which soon is going to be moved to dm i2c with the dm pmic framework. The i2c dm compatibility layer is also enabled for Exynos5 boards, which should be removed after moving the i2c drivers to driver model. The main change from the previous version is: - non-required code cleanup after Simon Glass comments - add new pinmux flag for Exynos - split commit with s3c i2c status timeout change - fix build error for u-boot-dm/master Przemyslaw Marczak (12): dm: i2c-uclass-compat: fix missed argument arndale: config: disable max77686 support exynos5250: config: disable max77686 driver smdk5250: config: enable max77686 driver support exynos4: dts: add missing i2c properties arndale: dts: add missing i2c aliases exynos5: pinmux: check flag for i2c config i2c: s3c24x0: reduce transmission status timeout dm: i2c: s3c24x0: adjust to dm-i2c api odroid u3: dts: add missing i2c aliases odroid u3: enable dm i2c support exynos5: enable dm i2c arch/arm/cpu/armv7/exynos/pinmux.c| 27 +++- arch/arm/dts/exynos4.dtsi | 24 ++- arch/arm/dts/exynos4412-odroid.dts| 7 + arch/arm/dts/exynos5250-arndale.dts | 8 + arch/arm/include/asm/arch-exynos/pinmux.h | 3 + board/samsung/odroid/odroid.c | 14 +- drivers/i2c/i2c-uclass-compat.c | 2 +- drivers/i2c/s3c24x0_i2c.c | 241 -- include/configs/arndale.h | 2 - include/configs/exynos5-common.h | 7 +- include/configs/exynos5250-common.h | 3 - include/configs/odroid.h | 5 +- include/configs/smdk5250.h| 2 + 13 files changed, 258 insertions(+), 87 deletions(-) This version is available here: https://github.com/bobenstein/u-boot/tree/dm-i2c-exynos_v3 One additional fix to: i2c-uclass-compat.c, the same issue is on u-boot-dm/i2c-working Best regards, -- Przemyslaw Marczak Samsung R&D Institute Poland Samsung Electronics p.marc...@samsung.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 16/23] x86: Allow FSP Kconfig settings for all x86
On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass wrote: > While queensbay is the first chip with these settings, others will want to > use them too. Make them common. > > Signed-off-by: Simon Glass > --- > > arch/x86/Kconfig | 38 ++ > arch/x86/cpu/queensbay/Kconfig | 38 -- > 2 files changed, 38 insertions(+), 38 deletions(-) > > diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig > index 1523c91..73a7392 100644 > --- a/arch/x86/Kconfig > +++ b/arch/x86/Kconfig > @@ -344,6 +344,44 @@ config TSC_FREQ_IN_MHZ > help > The running frequency in MHz of Time-Stamp Counter (TSC). > > +config HAVE_FSP > + bool "Add an Firmware Support Package binary" > + help > + Select this option to add an Firmware Support Package binary to > + the resulting U-Boot image. It is a binary blob which U-Boot uses > + to set up SDRAM and other chipset specific initialization. > + > + Note: Without this binary U-Boot will not be able to set up its > + SDRAM so will not boot. > + > +config FSP_FILE > + string "Firmware Support Package binary filename" > + depends on HAVE_FSP > + default "fsp.bin" > + help > + The filename of the file to use as Firmware Support Package binary > + in the board directory. > + > +config FSP_ADDR > + hex "Firmware Support Package binary location" > + depends on HAVE_FSP > + default 0xfffc > + help > + FSP is not Position Independent Code (PIC) and the whole FSP has to > + be rebased if it is placed at a location which is different from the > + perferred base address specified during the FSP build. Use Intel's > + Binary Configuration Tool (BCT) to do the rebase. > + > + The default base address of 0xfffc indicates that the binary > must > + be located at offset 0xc from the beginning of a 1MB flash > device. > + > +config FSP_TEMP_RAM_ADDR > + hex > + default 0x200 > + help > + Stack top address which is used in FspInit after DRAM is ready and > + CAR is disabled. > + > source "arch/x86/cpu/coreboot/Kconfig" > > source "arch/x86/cpu/ivybridge/Kconfig" > diff --git a/arch/x86/cpu/queensbay/Kconfig b/arch/x86/cpu/queensbay/Kconfig > index f6b5201..397e599 100644 > --- a/arch/x86/cpu/queensbay/Kconfig > +++ b/arch/x86/cpu/queensbay/Kconfig > @@ -11,44 +11,6 @@ config INTEL_QUEENSBAY > > if INTEL_QUEENSBAY > > -config HAVE_FSP > - bool "Add an Firmware Support Package binary" > - help > - Select this option to add an Firmware Support Package binary to > - the resulting U-Boot image. It is a binary blob which U-Boot uses > - to set up SDRAM and other chipset specific initialization. > - > - Note: Without this binary U-Boot will not be able to set up its > - SDRAM so will not boot. > - > -config FSP_FILE > - string "Firmware Support Package binary filename" > - depends on HAVE_FSP > - default "fsp.bin" > - help > - The filename of the file to use as Firmware Support Package binary > - in the board directory. > - > -config FSP_ADDR > - hex "Firmware Support Package binary location" > - depends on HAVE_FSP > - default 0xfffc > - help > - FSP is not Position Independent Code (PIC) and the whole FSP has to > - be rebased if it is placed at a location which is different from the > - perferred base address specified during the FSP build. Use Intel's > - Binary Configuration Tool (BCT) to do the rebase. > - > - The default base address of 0xfffc indicates that the binary > must > - be located at offset 0xc from the beginning of a 1MB flash > device. > - > -config FSP_TEMP_RAM_ADDR > - hex > - default 0x200 > - help > - Stack top address which is used in FspInit after DRAM is ready and > - CAR is disabled. > - > config HAVE_CMC > bool "Add a Chipset Micro Code state machine binary" > help > -- Reviewed-by: Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] armv8/vexpress64: make multientry conditional
While the Freescale ARMv8 board LS2085A will enter U-Boot both
on a master and a secondary (slave) CPU, this is not the common
behaviour on ARMv8 platforms. The norm is that U-Boot is entered
from the master CPU only, while the other CPUs are kept in
WFI (wait for interrupt) state.
The code determining which CPU we are running on is using the
MPIDR register, but the definition of that register varies with
platform to some extent, and handling multi-cluster platforms
(such as the Juno) will become cumbersome. It is better to only
enable the multiple entry code on machines that actually need
it and disable it by default.
Make the single entry default and add a special
CONFIG_ARMV8_MULTIENTRY config option to be used by the
platforms that need multientry and set it for the LS2085A.
Delete all use of the CPU_RELEASE_ADDR from the Vexpress64
boards as it is just totally unused and misleading, and
make it conditional in the generic start.S code.
This makes the Juno platform start U-Boot properly.
Signed-off-by: Linus Walleij
---
This patch applied on top of the other patch series send,
ending with
[PATCH 4/4] vexpress64: support the Juno Development Platform
Please apply it on top of these if the patch seems OK.
---
arch/arm/cpu/armv8/start.S | 8
arch/arm/include/asm/macro.h | 8
board/armltd/vexpress64/vexpress64.c | 6 --
include/configs/ls2085a_common.h | 5 +
include/configs/vexpress_aemv8a.h| 8
5 files changed, 17 insertions(+), 18 deletions(-)
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index 4b11aa4f2227..9b439f30b779 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -77,6 +77,7 @@ reset:
/* Processor specific initialization */
bl lowlevel_init
+#ifdef CONFIG_ARMV8_MULTIENTRY
branch_if_master x0, x1, master_cpu
/*
@@ -88,11 +89,10 @@ slave_cpu:
ldr x0, [x1]
cbz x0, slave_cpu
br x0 /* branch to the given address */
-
- /*
-* Master CPU
-*/
master_cpu:
+ /* On the master CPU */
+#endif /* CONFIG_ARMV8_MULTIENTRY */
+
bl _main
/*---*/
diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h
index 1c8c4251ee0c..3b3146ab2239 100644
--- a/arch/arm/include/asm/macro.h
+++ b/arch/arm/include/asm/macro.h
@@ -78,6 +78,8 @@ lr.reqx30
* choose processor with all zero affinity value as the master.
*/
.macro branch_if_slave, xreg, slave_label
+#ifdef CONFIG_ARMV8_MULTIENTRY
+ /* NOTE: MPIDR handling will be erroneous on multi-cluster machines */
mrs \xreg, mpidr_el1
tst \xreg, #0xff/* Test Affinity 0 */
b.ne\slave_label
@@ -90,6 +92,7 @@ lr.reqx30
lsr \xreg, \xreg, #16
tst \xreg, #0xff/* Test Affinity 3 */
b.ne\slave_label
+#endif
.endm
/*
@@ -97,12 +100,17 @@ lr .reqx30
* choose processor with all zero affinity value as the master.
*/
.macro branch_if_master, xreg1, xreg2, master_label
+#ifdef CONFIG_ARMV8_MULTIENTRY
+ /* NOTE: MPIDR handling will be erroneous on multi-cluster machines */
mrs \xreg1, mpidr_el1
lsr \xreg2, \xreg1, #32
lsl \xreg1, \xreg1, #40
lsr \xreg1, \xreg1, #40
orr \xreg1, \xreg1, \xreg2
cbz \xreg1, \master_label
+#else
+ b \master_label
+#endif
.endm
.macro armv8_switch_to_el2_m, xreg1
diff --git a/board/armltd/vexpress64/vexpress64.c
b/board/armltd/vexpress64/vexpress64.c
index 58973185ecda..7ab000cca77b 100644
--- a/board/armltd/vexpress64/vexpress64.c
+++ b/board/armltd/vexpress64/vexpress64.c
@@ -22,12 +22,6 @@ int board_init(void)
int dram_init(void)
{
- /*
-* Clear spin table so that secondary processors
-* observe the correct value after waken up from wfe.
-*/
- *(unsigned long *)CPU_RELEASE_ADDR = 0;
-
gd->ram_size = PHYS_SDRAM_1_SIZE;
return 0;
}
diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h
index 6fe032c9ff64..7f6f6f34cfa4 100644
--- a/include/configs/ls2085a_common.h
+++ b/include/configs/ls2085a_common.h
@@ -8,6 +8,11 @@
#define __LS2_COMMON_H
#define CONFIG_SYS_GENERIC_BOARD
+/*
+ * These machines will enter U-Boot on the master CPU and also
+ * a secondary CPU, so we need to handle that.
+ */
+#define CONFIG_ARMV8_MULTIENTRY
#define CONFIG_REMAKE_ELF
#define CONFIG_FSL_LSCH3
diff --git a/include/configs/vexpress_aemv8a.h
b/include/configs/vexpress_aemv8a.h
index 7fb28a54ba17..e276fff7e442 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -56,14 +56,6 @@
/* Flat Device Tree Definitions */
#define CONFIG_OF_LIBFDT
-
-/* SMP Spin Table Definitions */
-#ifdef CONFIG_TARGET_VEX
Re: [U-Boot] [PATCH 17/23] x86: Define cache line size
Hi Simon, On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass wrote: > This avoids a warning in the Realtek Ethernet driver. The value may not > matter on x86. > > Signed-off-by: Simon Glass > --- > > arch/x86/include/asm/cache.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/x86/include/asm/cache.h b/arch/x86/include/asm/cache.h > index 508b63f..fff1edd 100644 > --- a/arch/x86/include/asm/cache.h > +++ b/arch/x86/include/asm/cache.h > @@ -7,6 +7,8 @@ > #ifndef __X86_CACHE_H__ > #define __X86_CACHE_H__ > > +#define CONFIG_SYS_CACHELINE_SIZE 16 I think we should either fix the Realtek ethernet driver, or just move this '#define CONFIG_SYS_CACHELINE_SIZE 16' to include/configs/board.h as a workaround. Simply defining cache line size to 16 to avoid the driver warning does not look good to me, esecially it is not a correct number in a generic arch header file. > + > /* > * If CONFIG_SYS_CACHELINE_SIZE is defined use it for DMA alignment. > Otherwise > * use 64-bytes, a safe default for x86. > -- Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 18/23] x86: Allow a UART to be set up before the FSP is ready
Hi Simon,
On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass wrote:
> Since the FSP is a black box it helps to have some sort of debugging
> available to check its inputs. If the debug UART is in use, set it up
> after CAR is available.
>
> Signed-off-by: Simon Glass
> ---
>
> arch/x86/include/asm/u-boot-x86.h | 3 +++
> arch/x86/lib/fsp/fsp_support.c| 4
> 2 files changed, 7 insertions(+)
>
> diff --git a/arch/x86/include/asm/u-boot-x86.h
> b/arch/x86/include/asm/u-boot-x86.h
> index 44c24ff..85fafc0 100644
> --- a/arch/x86/include/asm/u-boot-x86.h
> +++ b/arch/x86/include/asm/u-boot-x86.h
> @@ -62,6 +62,9 @@ int fsp_cpu_mmc_init(const char *name, struct pci_device_id
> mmc_supported[],
> /* Set up a UART which can be used with printch(), printhex8(), etc. */
> int setup_early_uart(void);
>
> +/* Set up a UART which can be used with printch(), printhex8(), etc. */
> +int setup_early_uart(void);
> +
Duplicated setup_early_uart() here .. The first one was wrongly
introduced in patch#14 in this series.
> void setup_pcat_compatibility(void);
>
> void isa_unmap_rom(u32 addr);
> diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c
> index 8b639f7..5f96da1 100644
> --- a/arch/x86/lib/fsp/fsp_support.c
> +++ b/arch/x86/lib/fsp/fsp_support.c
> @@ -124,6 +124,10 @@ void fsp_init(u32 stack_top, u32 boot_mode, void
> *nvs_buf)
> struct fsp_init_params *params_ptr;
> struct upd_region *fsp_upd;
>
> +#ifdef CONFIG_DEBUG_UART
> + setup_early_uart();
> +#endif
> +
> fsp_hdr = find_fsp_header();
> if (fsp_hdr == NULL) {
> /* No valid FSP info header was found */
> --
Regards,
Bin
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Re: [U-Boot] [PATCH 20/23] scsi: bootstage: Measure time taken to scan the bus
On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass wrote:
> On some hardware this time can be significant. Add bootstage support for
> measuring this. The result can be obtained using 'bootstage report' or
> passed on to the Linux via the device tree.
>
> Signed-off-by: Simon Glass
> ---
>
> common/cmd_scsi.c | 2 ++
> include/bootstage.h | 1 +
> 2 files changed, 3 insertions(+)
>
> diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c
> index cbc107e..a0a62eb 100644
> --- a/common/cmd_scsi.c
> +++ b/common/cmd_scsi.c
> @@ -217,8 +217,10 @@ void scsi_init(void)
>(busdevfunc >> 8) & 0x7);
> }
> #endif
> + bootstage_start(BOOTSTAGE_ID_ACCUM_SCSI, "ahci");
> scsi_low_level_init(busdevfunc);
> scsi_scan(1);
> + bootstage_accum(BOOTSTAGE_ID_ACCUM_SCSI);
> }
> #endif
>
> diff --git a/include/bootstage.h b/include/bootstage.h
> index df13ab2..6b7588d 100644
> --- a/include/bootstage.h
> +++ b/include/bootstage.h
> @@ -194,6 +194,7 @@ enum bootstage_id {
> BOOTSTAGE_ID_MAIN_CPU_READY,
>
> BOOTSTAGE_ID_ACCUM_LCD,
> + BOOTSTAGE_ID_ACCUM_SCSI,
>
> /* a few spare for the user, from here */
> BOOTSTAGE_ID_USER,
> --
Reviewed-by: Bin Meng
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Re: [U-Boot] [PATCH 21/23] x86: Enable bootstage features
On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass wrote: > Allow measuring of boot time using bootstage. > > Signed-off-by: Simon Glass > --- > > include/configs/x86-common.h | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h > index ecedfc3..66d4894 100644 > --- a/include/configs/x86-common.h > +++ b/include/configs/x86-common.h > @@ -245,6 +245,9 @@ > #define CONFIG_BOOTP_GATEWAY > #define CONFIG_BOOTP_HOSTNAME > > +#define CONFIG_BOOTSTAGE > +#define CONFIG_CMD_BOOTSTAGE > + > #define CONFIG_CMD_USB > > #define CONFIG_EXTRA_ENV_SETTINGS \ > -- Reviewed-by: Bin Meng Tested-by: Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] armv8/vexpress64: make multientry conditional
On Tue, Jan 27, 2015 at 01:46:11PM +0100, Linus Walleij wrote: > While the Freescale ARMv8 board LS2085A will enter U-Boot both > on a master and a secondary (slave) CPU, this is not the common > behaviour on ARMv8 platforms. The norm is that U-Boot is entered > from the master CPU only, while the other CPUs are kept in > WFI (wait for interrupt) state. > > The code determining which CPU we are running on is using the > MPIDR register, but the definition of that register varies with > platform to some extent, and handling multi-cluster platforms > (such as the Juno) will become cumbersome. It is better to only > enable the multiple entry code on machines that actually need > it and disable it by default. > > Make the single entry default and add a special > CONFIG_ARMV8_MULTIENTRY config option to be used by the > platforms that need multientry and set it for the LS2085A. > Delete all use of the CPU_RELEASE_ADDR from the Vexpress64 > boards as it is just totally unused and misleading, and > make it conditional in the generic start.S code. > > This makes the Juno platform start U-Boot properly. > > Signed-off-by: Linus Walleij This seems fine conceptually but can you add arch/arm/cpu/armv8/Kconfig to introduce the ARMV8_MULTIENTRY symbol and then just enable it for LS2085A there? Thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v2] spl: Change debug to printf for "Unsupported boot-device"
Hi guys, 2014-11-24 23:10 GMT+01:00 Tom Rini : > On Tue, Nov 11, 2014 at 07:03:55PM +0100, Stefan Roese wrote: > > > We had the problem on an AM33xx platform, that SPL detected an > > unsupported boot-device. But since this message is a debug message > > it took a bit of time to really know, where the hangup in SPL > > resulted from. So let's change this debug message to a printf > > and also print the detected boot-device that is not supported. > > This makes debugging of such cases much easier. > > > > Signed-off-by: Stefan Roese > > Cc: Wolfgang Denk > > Cc: Tom Rini > > Acked-by: Heiko Schocher > > Applied to u-boot/master, thanks! > > This patch is causing problem on Microblaze because SPL exceed 4k limit. It is only one printf which is called in entire SPL that's why this should be solved a little bit differently. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 0/9] sf: Update flash params for supported read commands and sector size
Hi Jagan, On Sat, Jan 24, 2015 at 6:34 PM, Bin Meng wrote: > Hi Jagan, > > On Mon, Jan 12, 2015 at 2:52 PM, Jagan Teki wrote: >> On 12 January 2015 at 09:12, Bin Meng wrote: >>> Hi Jagan, >>> >>> On Wed, Dec 17, 2014 at 4:39 PM, Jagan Teki >>> wrote: On 17 December 2014 at 13:32, Bin Meng wrote: > Hi Jagan, > > On Wed, Dec 17, 2014 at 3:59 PM, Jagan Teki > wrote: >> On 15 December 2014 at 19:21, Bin Meng wrote: >>> Hi Jagan, >>> >>> On Thu, Dec 11, 2014 at 3:40 PM, Bin Meng wrote: Hi Jagan, On Thu, Dec 11, 2014 at 3:26 PM, Jagan Teki wrote: > Hi Bin, > > On 11 December 2014 at 08:34, Bin Meng wrote: >> Hi Jagan, >> >> On Thu, Dec 11, 2014 at 2:41 AM, Jagan Teki >> wrote: >>> Hi Bin, >>> >>> On 10 December 2014 at 18:21, Bin Meng wrote: This series update SPI flash supported read commands per datasheet in the flash params table, and change flash sector size to 4KiB as long as flash supports sector erase (20h) command, to ensure 'sf erase offset +len' work on 4KiB boundary instead of 64KiB when given SECT_4K. Changes in v3: - Rebase with Jagan's patch series @ http://patchwork.ozlabs.org/patch/419154/ Bin Meng (9): sf: Update SST flash params sf: Update Atmel flash params sf: Update EON flash params sf: Update GigaDevice flash params sf: Update Macronix flash params sf: Update Spansion flash params sf: Update Micron flash params sf: Update Winbond flash params sf: Give proper spacing between flash table params >>> >>> Thanks for the updates - have you verified these changes? >> >> I verified some, but not all of these flash parts. The update is >> based >> on flash datasheet, so if something is broken, eg before this series >> the flash advertises only READ_NORM and after my series it is changed >> to READ_FULL, and let's say QUAD_IO_FAST is not working, it is very >> likely that the SPI controller driver has some bugs when supporting >> QUAD_IO_FAST. > > Since these updates were tested before, I will skip these for this PR. > Will test all the rest (except these) and send the PR soon. > > Let me know your inputs? I am fine, as long as this PR will not contains other commits which modify the same sf_params.c to introduce more flash support. We can test these updates and if everything looks fine, apply these first and ask other commits to rebase on this series to introduce more flash support. >>> >>> Do you have any additional comments about this patch series besides >>> the S25FL128S_64K and S25FL256S_64K sector size? If not, I can send >>> the v4. >> >> I'm thinking about the other flashes too, since these params were taken >> from >> previous working and Linux mtd. >> > > You mean 'thinking about' or 'testing'? I should say previously they > might not be 100% working as per datasheet some flash params currently > are apparently wrong. Yes - about testing. >>> >>> Ping? What about your test results about this patch series? >> >> Some were pending - Will comment, pls- wait. >> >> thanks! >> -- > > I still don't see any additional comments. Looking at the history this > patch series has been sitting there for months. Would you please let > me know what you think about this series? > Could you respond this? I wonder if this series could be merged in before MW is closed. Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 19/23] x86: spi: Support ValleyView in ICH SPI driver
Hi Simon,
On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass wrote:
> The base address is found in a different way and the protection bit is also
> in a different place. Otherwise it is very similar.
>
> Signed-off-by: Simon Glass
> ---
>
> drivers/spi/ich.c | 56
> ---
> drivers/spi/ich.h | 11 ++-
> 2 files changed, 47 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
> index fdff158..da85779 100644
> --- a/drivers/spi/ich.c
> +++ b/drivers/spi/ich.c
> @@ -7,6 +7,7 @@
> */
>
> #include
> +#include
> #include
> #include
> #include
> @@ -21,6 +22,7 @@
> struct ich_ctlr {
> pci_dev_t dev; /* PCI device number */
> int ich_version;/* Controller version, 7 or 9 */
> + bool use_sbase; /* Use SBASE instead of RCB */
> int ichspi_lock;
> int locked;
> uint8_t *opmenu;
> @@ -145,7 +147,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus,
> unsigned int cs,
> * ICH 7 SPI controller only supports array read command
> * and byte program command for SST flash
> */
> - if (ctlr.ich_version == 7) {
> + if (ctlr.ich_version == 7 || ctlr.use_sbase) {
> ich->slave.op_mode_rx = SPI_OPM_RX_AS;
> ich->slave.op_mode_tx = SPI_OPM_TX_BP;
> }
So the Valleyview SPI controller (version 9) has the same behavior
that was seen on Tunnel Creek (version 7). I wonder whether the same
behavior was seen on chromebook_link which is also version 9? Or is
this only because the Minnowmax board has the same SST flash mounted
on board, just like the Crown Bay so that we need set these RX/TX
flags. If SPI controller on chromebook_link also has the simliar
behavior, we should consider set these flags for all Intel SPI
controller variants. This way, the 'use_sbase' variable may not be
necessary (see below for more comments).
> @@ -181,7 +183,8 @@ static int get_ich_version(uint16_t device_id)
> if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN &&
> device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) ||
> (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN &&
> -device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX))
> +device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX) ||
> + device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC)
To avoid bigger and bigger test logic, should we consider using DT to
pass such information?
> return 9;
>
> return 0;
> @@ -204,14 +207,14 @@ static int ich9_can_do_33mhz(pci_dev_t dev)
> return speed == 1;
> }
>
> -static int ich_find_spi_controller(pci_dev_t *devp, int *ich_versionp)
> +static int ich_find_spi_controller(struct ich_ctlr *ich)
> {
> int last_bus = pci_last_busno();
> int bus;
>
> if (last_bus == -1) {
> debug("No PCI busses?\n");
> - return -1;
> + return -ENODEV;
> }
>
> for (bus = 0; bus <= last_bus; bus++) {
> @@ -225,24 +228,33 @@ static int ich_find_spi_controller(pci_dev_t *devp, int
> *ich_versionp)
> device_id = ids >> 16;
>
> if (vendor_id == PCI_VENDOR_ID_INTEL) {
> - *devp = dev;
> - *ich_versionp = get_ich_version(device_id);
> - return 0;
> + ich->dev = dev;
> + ich->ich_version = get_ich_version(device_id);
> + if (device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC)
> + ich->use_sbase = true;
> + return ich->ich_version == 0 ? -ENODEV : 0;
> }
> }
>
> debug("ICH SPI: No ICH found.\n");
> - return -1;
> + return -ENODEV;
> }
>
> static int ich_init_controller(struct ich_ctlr *ctlr)
> {
> uint8_t *rcrb; /* Root Complex Register Block */
> uint32_t rcba; /* Root Complex Base Address */
> + uint32_t sbase_addr;
> + uint8_t *sbase;
>
> pci_read_config_dword(ctlr->dev, 0xf0, &rcba);
> /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */
> rcrb = (uint8_t *)(rcba & 0xc000);
> +
> + /* SBASE is similar */
> + pci_read_config_dword(ctlr->dev, 0x54, &sbase_addr);
> + sbase = (uint8_t *)(sbase_addr & 0xfe00);
> +
Again, DT can be used to determine the base address.
> if (ctlr->ich_version == 7) {
> struct ich7_spi_regs *ich7_spi;
>
> @@ -262,7 +274,10 @@ static int ich_init_controller(struct ich_ctlr *ctlr)
> } else if (ctlr->ich_version == 9) {
> struct ich9_spi_regs *ich9_spi;
>
> - ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800);
> + if (ctlr->use_sbase)
> + ich9_spi = (struct ich9_spi_regs *)
Re: [U-Boot] [U-Boot, v2] spl: Change debug to printf for "Unsupported boot-device"
Hi Michal, On 27.01.2015 14:43, Michal Simek wrote: On Tue, Nov 11, 2014 at 07:03:55PM +0100, Stefan Roese wrote: > We had the problem on an AM33xx platform, that SPL detected an > unsupported boot-device. But since this message is a debug message > it took a bit of time to really know, where the hangup in SPL > resulted from. So let's change this debug message to a printf > and also print the detected boot-device that is not supported. > This makes debugging of such cases much easier. > > Signed-off-by: Stefan Roese mailto:s...@denx.de>> > Cc: Wolfgang Denk mailto:w...@denx.de>> > Cc: Tom Rini mailto:tr...@ti.com>> > Acked-by: Heiko Schocher mailto:h...@denx.de>> Applied to u-boot/master, thanks! This patch is causing problem on Microblaze because SPL exceed 4k limit. It is only one printf which is called in entire SPL that's why this should be solved a little bit differently. Ups. Yes, sorry. This one line definitely shouldn't cause all the printf stuff to be included. I'll try to address this quickly... Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v2] spl: Change debug to printf for "Unsupported boot-device"
On Tue, Jan 27, 2015 at 02:43:57PM +0100, Michal Simek wrote: > Hi guys, > > 2014-11-24 23:10 GMT+01:00 Tom Rini : > > > On Tue, Nov 11, 2014 at 07:03:55PM +0100, Stefan Roese wrote: > > > > > We had the problem on an AM33xx platform, that SPL detected an > > > unsupported boot-device. But since this message is a debug message > > > it took a bit of time to really know, where the hangup in SPL > > > resulted from. So let's change this debug message to a printf > > > and also print the detected boot-device that is not supported. > > > This makes debugging of such cases much easier. > > > > > > Signed-off-by: Stefan Roese > > > Cc: Wolfgang Denk > > > Cc: Tom Rini > > > Acked-by: Heiko Schocher > > > > Applied to u-boot/master, thanks! > > > > > This patch is causing problem on Microblaze because SPL exceed 4k limit. > It is only one printf which is called in entire SPL that's why this should > be solved a little bit differently. OK, but for clarity you need and are using both CONFIG_SPL_SERIAL_SUPPORT and CONFIG_SPL_LIBCOMMON_SUPPORT because you're using puts but not printf, yes? -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] ARmv7: Add a soc_init hook to start.S
On Mon, Jan 26, 2015 at 08:32:41PM +0100, Hans de Goede wrote: > Hi, > > On 26-01-15 16:18, Tom Rini wrote: > >On Fri, Jan 23, 2015 at 09:54:12AM +0100, Hans de Goede wrote: > >>Hi, > >> > >>On 22-01-15 22:03, Tom Rini wrote: > >>>On Thu, Jan 22, 2015 at 08:10:06PM +0100, Hans de Goede wrote: > Hi, > > On 22-01-15 17:20, Tom Rini wrote: > >On Wed, Jan 21, 2015 at 09:03:25PM +0100, Hans de Goede wrote: > > > >>On some SoCs / ARMv7 CPU cores we need to do some setup before enabling > >>the > >>icache, etc. Add a soc_init hook with a weak default which just calls > >>cpu_init_cp15. > >> > >>This way different implementations can be provided to do some extra work > >>before or after cpu_init_cp15, or completely replacing cpu_init_cp15. > >> > >>Signed-off-by: Hans de Goede > >>--- > >> arch/arm/cpu/armv7/start.S | 18 +- > >> 1 file changed, 17 insertions(+), 1 deletion(-) > >> > >>diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S > >>index fdc05b9..9882b20 100644 > >>--- a/arch/arm/cpu/armv7/start.S > >>+++ b/arch/arm/cpu/armv7/start.S > >>@@ -64,7 +64,7 @@ reset: > >> > >>/* the mask ROM code should have PLL and others stable */ > >> #ifndef CONFIG_SKIP_LOWLEVEL_INIT > >>- bl cpu_init_cp15 > >>+ bl soc_init > >>bl cpu_init_crit > >> #endif > > > >I like the direction here. And I want to make sure I get the sunxi > >direction right here too (as I agree with the need / desire for boot0 + > >U-Boot to be a valid combination). I think we can take this a step > >farther. cpu_init_crit (on armv7) is basically a call to s_init(). > > > >For am33xx (and I bet but need to do and test omap3+) we can, with > >Simon's patch to let us move stack to DDR a tiny bit later, in the SPL > >case make s_init empty, which just leaves us with (with your patch) > >soc_init. Is there some way we can put all of this together in a > >function? > > You mean essentially call s_init here and have s_init call cpu_init_cp15 > I guess we could do that, but it would require auditing all existing armv7 > users of s_init. This may require me to rethink how / when I do timer & > gpio init etc. for u-boot.bin on sunxi, but that should not be a (big) > problem. > >>> > >>>Basically. From my first pass audit of s_init, it's either empty > >>>(Kona), sunxi, or omap/etc so I get to deal with it. And the default > >>>soc_init would just be the call to cpu_init_cp15 as you have it and we > >>>drop the lowlevel_init hurdles. > >> > >>Ok, so what you're suggesting is a patch which: > >> > >>1) Changes: > >> > >>#ifndef CONFIG_SKIP_LOWLEVEL_INIT > >>bl cpu_init_cp15 > >>bl cpu_init_crit > >>#endif > >> > >>Into: > >> > >>#ifndef CONFIG_SKIP_LOWLEVEL_INIT > >>bl lowlevel_init > >>#endif > >> > >>Which will setup the stack and then call the s_init C function > >> > >>2) Adds a weak default s_init which calls cpu_init_cp15 > >> > >>3) Patch all existing s_init functions to call cpu_init_cp15 > >>before doing anything else. > > > >Pretty close. Simon's SPL DM series and related clean-ups got me > >thinking that yes, seemingly too much got shoved into "s_init" that > >really could have been done using an existing hook done slightly later. > > > >>And then in follow up patches we can: > >> > >>4) Drop cpu_init_crit > >> > >>5) Cleanup some s_init functions (this will be left to the individual > >>SoC maintainers) > >> > >>I think that is a good idea, Albert what do you think about this ? > > > >So I'd like to see 5 done "soon" afterwards as it's me (omap*) and > >sunxi. I think we can simplfy the call sequence too, to roughly: > >#ifndef CONFIG_SKIP_LOWLEVEL_INIT > > ... Set up stack for C, it's just a few instrs > > bl lowlevel_init > >#endif > > bl _main > > > >__weak asm > >lowlevel_init: > > bl cpu_init_cp15 > > return to caller > > > >And comment that anything called via lowlevel_init must be C-callable. > >I hope that once #5 is done no one actually has a lowlevel_init that's > >done in C but we've kept the door open should it be needed down the > >road (as I _think_ we can shuffle both the omap* and sunxi stuff to do > >their inits as needed in both SPL and full U-Boot from an early hook in > >board_init_r, top of my head is board_init calls some_other_func() in > >full U-Boot to ensure GPIOs, etc, on sunxi and spl_board_init() calls > >same func in SPL, and we can consolidate again further down the road as > >we get SPL and full U-Boot more in sync on the call chain). > > Sounds good to me, and I'm fine with working the sunxi side of things. > > Since you seem to have this all in your head can you do a patch for this > replacing my patchset ? I suppose that's what happens when you have a detailed plan, will do ;) -- Tom
Re: [U-Boot] [PATCH 0/23] x86: Add bare support for Intel Minnowboard Max
Hi Simon, On Tue, Jan 27, 2015 at 9:22 AM, Simon Glass wrote: > This series adds support for the Intel Minnowboard Max (called Minnowmax > for short). Along the way a few refactors and additions are made: > > - The Intel Firmware Support Package support is moved from queensbay to a > common location > - PCI support for XHCI is added > - A few tweaks are made to the PCI support > - Support for the debug UART (early debug output) is provided > - The microcode tool now also supports reading in header files > > This board has been lightly tested. The following seem to work: > > - USB2 on the blue port (not USB3), e.g. for keyboard > - Ethernet > - HDMI out and console > - UART > - uSD card > - SPI > > SATA is detected but I have not attached a drive to try it. USB3 shows signs > of life but does not detect a USB stick, and crashes when trying to use a > USB Ethernet adaptor. > > For SPI some parts cannot be read and others cannot be written. This seems > to be a feature of the Intel hardware configuration. It may be possible to > fix this using the SPI registers but I cannot work out how / lost interest > trying. So far, addresses from 50 to 70 can be used. > > I have not tried the ICH GPIO driver but it likely needs work before it will > function. I2C is not supported as there is currently no U-Boot driver for > this. > > The zboot command can be used to start a bzImage kernel. Verified boot is > supported - use mkimage to sign images as described in this walk-through: > doc/uImage.FIT/beaglebone_vboot.txt > > Boot time is grim: > - 1423ms to set up display (Intel FSP) > - 454ms to scan AHCI (when no devices are connected) > - ~1000ms to power up and start cache-as-RAM init (Intel FSP) > (this is not benchmarked, may be inaccurate) > - ~950ms to set up memory and initial machine configuration (Intel FSP) > (this is not benchmarked, may be inaccurate) > > So it takes over 4 seconds to get to booting a kernel. > > Implementing the Memory Reference Code (MRC) cache should improve this > slightly (perhaps a reduction of 500-1000ms). This cache is implemented for > ivybridge so that code needs to be moved into a generic x86 directory and > plumbed into the FSP code. This has not been done in this series. Also the > video and SATA/AHCI can be disabled if preferred. > > It is also possible to run as a coreboot payload. See the instructions in > README.x86 for this. In this case video does not work since coreboot does > not pass through the VESA display information. > > To support the single-core 1GB variant, changes would need to be made to > arch/x86/cpu/baytrail/fsp_configs.c to select different values for the > memory. The microcode update may need to change also. > > This series is available at u-boot-x86 branch minnow-working. > I have finished the review of this patch series. Generally they look pretty good. Glad to see we have another new Intel board supported running U-Boot 'bare'! [snip] Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v2] spl: Change debug to printf for "Unsupported boot-device"
On 27.01.2015 15:22, Tom Rini wrote: We had the problem on an AM33xx platform, that SPL detected an unsupported boot-device. But since this message is a debug message it took a bit of time to really know, where the hangup in SPL resulted from. So let's change this debug message to a printf and also print the detected boot-device that is not supported. This makes debugging of such cases much easier. Signed-off-by: Stefan Roese Cc: Wolfgang Denk Cc: Tom Rini Acked-by: Heiko Schocher Applied to u-boot/master, thanks! This patch is causing problem on Microblaze because SPL exceed 4k limit. It is only one printf which is called in entire SPL that's why this should be solved a little bit differently. OK, but for clarity you need and are using both CONFIG_SPL_SERIAL_SUPPORT and CONFIG_SPL_LIBCOMMON_SUPPORT because you're using puts but not printf, yes? Right. If this is the case (only puts usage on Microblaze), then its perhaps best that I change this line to puts as well. Okay? Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v2] spl: Change debug to printf for "Unsupported boot-device"
2015-01-27 15:38 GMT+01:00 Stefan Roese : > On 27.01.2015 15:22, Tom Rini wrote: > >> We had the problem on an AM33xx platform, that SPL detected an > unsupported boot-device. But since this message is a debug message > it took a bit of time to really know, where the hangup in SPL > resulted from. So let's change this debug message to a printf > and also print the detected boot-device that is not supported. > This makes debugging of such cases much easier. > > Signed-off-by: Stefan Roese > Cc: Wolfgang Denk > Cc: Tom Rini > Acked-by: Heiko Schocher > Applied to u-boot/master, thanks! This patch is causing problem on Microblaze because SPL exceed 4k >>> limit. >>> It is only one printf which is called in entire SPL that's why this >>> should >>> be solved a little bit differently. >>> >> >> OK, but for clarity you need and are using both >> CONFIG_SPL_SERIAL_SUPPORT and CONFIG_SPL_LIBCOMMON_SUPPORT because >> you're using puts but not printf, yes? >> > > Right. If this is the case (only puts usage on Microblaze), then its > perhaps best that I change this line to puts as well. Okay? > > Changing this to puts is definitely fine. Microblaze is using just puts. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] lcd: fix console address is not initialized
Hi Bo,
On 01/26/2015 07:55 AM, Bo Shen wrote:
Hi Nikita Kiryanov,
+ Andreas, Tom
On 01/23/2015 09:20 AM, Bo Shen wrote:
Hi Nikita Kiryanov,
On 01/22/2015 09:10 PM, Nikita Kiryanov wrote:
Hi Bo,
On 01/21/2015 06:37 AM, Bo Shen wrote:
This commit 904672e (lcd: refactor lcd console stuff into its
own file), which cause lcd console address is not initialized.
Based on your fix, I'm certain that the bug was introduced in a
previous patch, perhaps 140beb9 (lcd: expand console api).
Also, can you provide a more detailed explanation of when this
happens and how?
It will cause the system hang.
Before this patch, lcd_logo -> lcd_show_board_info (CONFIG_LCD_INFO) ->
.. -> lcd_drawchars. It has the following lines:
--->8---
dest = (uchar *)(lcd_base + y * lcd_line_length + x * NBITS(LCD_BPP)/8);
---8<---
while with the patch,
--->8---
dest = (uchar *)(lcd_console_address +
y * lcd_line_length + x * NBITS(LCD_BPP) / 8);
---8<---
As the lcd_console_address is initialized after lcd_logo return, so the
lcd_console_address is not initialized, it is 0. When try to write to
address 0, the system hang.
This patch split lcd console address initialize and lcd logo
display into two functions.
Signed-off-by: Bo Shen
---
common/lcd.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/common/lcd.c b/common/lcd.c
index cc34b8a..f435e2a 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -82,7 +82,8 @@ DECLARE_GLOBAL_DATA_PTR;
static int lcd_init(void *lcdbase);
-static void *lcd_logo(void);
+static void lcd_logo(void);
+static void *lcd_console_address(void);
static void lcd_setfgcolor(int color);
static void lcd_setbgcolor(int color);
@@ -268,7 +269,8 @@ void lcd_clear(void)
console_rows = panel_info.vl_row / VIDEO_FONT_HEIGHT;
#endif
console_cols = panel_info.vl_col / VIDEO_FONT_WIDTH;
-lcd_init_console(lcd_logo(), console_rows, console_cols);
+lcd_init_console(lcd_console_address(), console_rows,
console_cols);
+lcd_logo();
lcd_sync();
}
@@ -849,7 +851,7 @@ int lcd_display_bitmap(ulong bmp_image, int x,
int y)
}
#endif
-static void *lcd_logo(void)
+static void lcd_logo(void)
{
#ifdef CONFIG_SPLASH_SCREEN
char *s;
@@ -879,7 +881,10 @@ static void *lcd_logo(void)
lcd_set_row(LCD_INFO_Y / VIDEO_FONT_HEIGHT);
lcd_show_board_info();
#endif /* CONFIG_LCD_INFO */
+}
+static void *lcd_console_address(void)
+{
#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO)
return (void *)((ulong)lcd_base + BMP_LOGO_HEIGHT *
lcd_line_length);
#else
I would like to see some mention of why it's ok to redefine the console
address in such a way. At first glance it looks like there is a slight
change of
behavior (the value no longer depends on whether splash image was loaded
or not), but it seems to be ok if you go over the various cases. The only
instance where I see the difference could manifest itself is if lcd
console
would start writing to the frame buffer while the splash screen is still
on,
but that doesn't look good regardless of where the console starts, so
I'm ok
with that.
Thanks for reminder this, I will check whether this will break the
splash screen.
Can we use the following patch to fix this issue?
--->8---
diff --git a/common/lcd.c b/common/lcd.c
index cc34b8a..1195a54 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -268,6 +268,7 @@ void lcd_clear(void)
console_rows = panel_info.vl_row / VIDEO_FONT_HEIGHT;
#endif
console_cols = panel_info.vl_col / VIDEO_FONT_WIDTH;
+ lcd_init_console(lcd_base, console_rows, console_cols);
lcd_init_console(lcd_logo(), console_rows, console_cols);
lcd_sync();
}
---8<---
It first initializes the lcd console with LCD base, if the splash screen is
used, new address is updated.
I think this is the best approach. I am very close to posting the next step in
my refactor of lcd.c, and I can
incorporate it in the series. I will greatly appreciate your help in testing
this series, since it involves Atmel
related changes.
I need this kind of fix to be applied as soon as possible, or else, most Atmel
related board are broken on u-boot master branch.
Best Regards,
Bo Shen
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Re: [U-Boot] [PATCH 01/23] x86: Enhance the microcode tool to support header files as input
Hi Bin,
On 27 January 2015 at 01:59, Bin Meng wrote:
> Hi Simon,
>
> On Tue, Jan 27, 2015 at 9:22 AM, Simon Glass wrote:
>> Sometimes microcode is delivered as a header file. Allow the tool to
>> support this as well as collecting multiple microcode blocks into a
>> single update.
>>
>> Signed-off-by: Simon Glass
>> ---
>
> Tested-by: Bin Meng
>
> But please see my comments below.
>
>> tools/microcode-tool.py | 90
>> ++---
>> 1 file changed, 70 insertions(+), 20 deletions(-)
>>
>> diff --git a/tools/microcode-tool.py b/tools/microcode-tool.py
>> index 003716d..71c2e91 100755
>> --- a/tools/microcode-tool.py
>> +++ b/tools/microcode-tool.py
>> @@ -76,6 +76,35 @@ def ParseFile(fname):
>> microcodes[name] = Microcode(name, data)
>> return date, license_text, microcodes
>>
>> +def ParseHeaderFiles(fname_list):
>> +"""Parse a list of header files and return the component parts
>> +
>> +Args:
>> +fname_list: List of files to parse
>> +Returns:
>> +date: String containing date from the file's header
>> +license_text: List of text lines for the license file
>> +microcodes: List of Microcode objects from the file
>> +"""
>> +microcodes = {}
>> +license_text = []
>> +date = ''
>> +name = None
>> +for fname in fname_list:
>> +name = os.path.basename(fname).lower()
>> +name = os.path.splitext(name)[0]
>> +data = []
>> +with open(fname) as fd:
>> +for line in fd:
>> +line = line.rstrip()
>> +
>> +# Omit anything after the last comma
>> +words = line.split(',')[:-1]
>> +data += [word + ',' for word in words]
>> +microcodes[name] = Microcode(name, data)
>> +return date, license_text, microcodes
>> +
>> +
>> def List(date, microcodes, model):
>> """List the available microcode chunks
>>
>> @@ -129,13 +158,13 @@ def FindMicrocode(microcodes, model):
>> break
>> return found, tried
>>
>> -def CreateFile(date, license_text, mcode, outfile):
>> +def CreateFile(date, license_text, mcodes, outfile):
>> """Create a microcode file in U-Boot's .dtsi format
>>
>> Args:
>> date: String containing date of original microcode file
>> license:List of text lines for the license file
>> -mcode: Microcode object to write
>> +mcodes: Microcode objects to write (normally only 1)
>> outfile:Filename to write to ('-' for stdout)
>> """
>> out = '''/*%s
>> @@ -159,15 +188,22 @@ intel,processor-flags = <%#x>;
>> data = <%s
>> \t>;'''
>> words = ''
>> -for i in range(len(mcode.words)):
>> -if not (i & 3):
>> -words += '\n'
>> -val = mcode.words[i]
>> -# Change each word so it will be little-endian in the FDT
>> -# This data is needed before RAM is available on some platforms so
>> we
>> -# cannot do an endianness swap on boot.
>> -val = struct.unpack("I", val))[0]
>> -words += '\t%#010x' % val
>> +add_comments = len(mcodes) > 1
>> +for mcode in mcodes:
>> +if add_comments:
>> +words += '\n/* %s */' % mcode.name
>> +for i in range(len(mcode.words)):
>> +if not (i & 3):
>> +words += '\n'
>> +val = mcode.words[i]
>> +# Change each word so it will be little-endian in the FDT
>> +# This data is needed before RAM is available on some platforms
>> so
>> +# we cannot do an endianness swap on boot.
>> +val = struct.unpack("I", val))[0]
>> +words += '\t%#010x' % val
>> +
>> +# Use the first microcode for the headers
>> +mcode = mcodes[0]
>>
>> # Take care to avoid adding a space before a tab
>> text = ''
>> @@ -187,8 +223,8 @@ data = <%s
>> print >> sys.stderr, "Creating directory '%s'" %
>> MICROCODE_DIR
>> os.makedirs(MICROCODE_DIR)
>> outfile = os.path.join(MICROCODE_DIR, mcode.name + '.dtsi')
>> -print >> sys.stderr, "Writing microcode for '%s' to '%s'" % (
>> - mcode.name, outfile)
>> +print >> sys.stderr, "Writing microcode for '%s' to '%s'" % (
>> +', '.join([mcode.name for mcode in mcodes]), outfile)
>> with open(outfile, 'w') as fd:
>> print >> fd, out % tuple(args)
>>
>> @@ -198,8 +234,12 @@ def MicrocodeTool():
>> parser = OptionParser()
>> parser.add_option('-d', '--mcfile', type='string', action='store',
>> help='Name of microcode.dat file')
>> +parser.add_option('-H', '--headerfile', type='string', action='append',
>> +help='Name of .h file containing microcode')
>> parser.add_option('-m', '--model', type='string', action='store',
>> -
Re: [U-Boot] [PATCH 14/23] x86: Move common FSP functions into a common file
Hi Bin,
On 27 January 2015 at 05:20, Bin Meng wrote:
> Hi Simon,
>
> On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass wrote:
>> Since these board functions seem to be the same for all boards which use
>> FSP, move them into a common file. We can adjust this later if future FSPs
>> need more flexibility.
>>
>> Signed-off-by: Simon Glass
>> ---
>>
>> arch/x86/cpu/queensbay/tnc.c | 27
>> arch/x86/cpu/queensbay/tnc_pci.c | 15 ---
>> arch/x86/cpu/queensbay/topcliff.c | 32 +-
>> arch/x86/include/asm/u-boot-x86.h | 17
>> arch/x86/lib/fsp/Makefile | 1 +
>> arch/x86/lib/fsp/fsp_common.c | 88
>> +++
>> 6 files changed, 108 insertions(+), 72 deletions(-)
>> create mode 100644 arch/x86/lib/fsp/fsp_common.c
>>
>> diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
>> index f9b3bfa..30ab725 100644
>> --- a/arch/x86/cpu/queensbay/tnc.c
>> +++ b/arch/x86/cpu/queensbay/tnc.c
>> @@ -43,30 +43,3 @@ int arch_cpu_init(void)
>>
>> return 0;
>> }
>> -
>> -int print_cpuinfo(void)
>> -{
>> - post_code(POST_CPU_INFO);
>> - return default_print_cpuinfo();
>> -}
>> -
>> -void reset_cpu(ulong addr)
>> -{
>> - /* cold reset */
>> - outb(0x06, PORT_RESET);
>> -}
>> -
>> -void board_final_cleanup(void)
>> -{
>> - u32 status;
>> -
>> - /* call into FspNotify */
>> - debug("Calling into FSP (notify phase INIT_PHASE_BOOT): ");
>> - status = fsp_notify(NULL, INIT_PHASE_BOOT);
>> - if (status != FSP_SUCCESS)
>> - debug("fail, error code %x\n", status);
>> - else
>> - debug("OK\n");
>> -
>> - return;
>> -}
>> diff --git a/arch/x86/cpu/queensbay/tnc_pci.c
>> b/arch/x86/cpu/queensbay/tnc_pci.c
>> index 9b0b725..6c291f9 100644
>> --- a/arch/x86/cpu/queensbay/tnc_pci.c
>> +++ b/arch/x86/cpu/queensbay/tnc_pci.c
>> @@ -44,18 +44,3 @@ void board_pci_setup_hose(struct pci_controller *hose)
>>
>> hose->region_count = 4;
>> }
>> -
>> -int board_pci_post_scan(struct pci_controller *hose)
>> -{
>> - u32 status;
>> -
>> - /* call into FspNotify */
>> - debug("Calling into FSP (notify phase INIT_PHASE_PCI): ");
>> - status = fsp_notify(NULL, INIT_PHASE_PCI);
>> - if (status != FSP_SUCCESS)
>> - debug("fail, error code %x\n", status);
>> - else
>> - debug("OK\n");
>> -
>> - return 0;
>> -}
>> diff --git a/arch/x86/cpu/queensbay/topcliff.c
>> b/arch/x86/cpu/queensbay/topcliff.c
>> index b01422a..25032cc 100644
>> --- a/arch/x86/cpu/queensbay/topcliff.c
>> +++ b/arch/x86/cpu/queensbay/topcliff.c
>> @@ -5,43 +5,15 @@
>> */
>>
>> #include
>> -#include
>> -#include
>> -#include
>> #include
>> -#include
>>
>> static struct pci_device_id mmc_supported[] = {
>> { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_0 },
>> { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_1 },
>> - { }
>> };
>>
>> int cpu_mmc_init(bd_t *bis)
>> {
>> - struct sdhci_host *mmc_host;
>> - pci_dev_t devbusfn;
>> - u32 iobase;
>> - int ret;
>> - int i;
>> -
>> - for (i = 0; i < ARRAY_SIZE(mmc_supported); i++) {
>> - devbusfn = pci_find_devices(mmc_supported, i);
>> - if (devbusfn == -1)
>> - return -ENODEV;
>> -
>> - mmc_host = (struct sdhci_host *)malloc(sizeof(struct
>> sdhci_host));
>> - if (!mmc_host)
>> - return -ENOMEM;
>> -
>> - mmc_host->name = "Topcliff SDHCI";
>> - pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase);
>> - mmc_host->ioaddr = (void *)iobase;
>> - mmc_host->quirks = 0;
>> - ret = add_sdhci(mmc_host, 0, 0);
>> - if (ret)
>> - return ret;
>> - }
>> -
>> - return 0;
>> + return fsp_cpu_mmc_init("Topcliff SDHCI", mmc_supported,
>> + ARRAY_SIZE(mmc_supported));
>> }
>
> I don't think this function should be moved to fsp_common.c as it has
> nothing related to FSP. We can move this whole function to
> drivers/mmc/, something like intel_mmc.c or intel_sdhc.c.
How about pci_mmc.c if it is generic to PCI?
>
>> diff --git a/arch/x86/include/asm/u-boot-x86.h
>> b/arch/x86/include/asm/u-boot-x86.h
>> index b98afa8..44c24ff 100644
>> --- a/arch/x86/include/asm/u-boot-x86.h
>> +++ b/arch/x86/include/asm/u-boot-x86.h
>> @@ -45,6 +45,23 @@ ulong board_get_usable_ram_top(ulong total_size);
>> void dram_init_banksize(void);
>> int default_print_cpuinfo(void);
>>
>> +struct pci_device_id;
>> +
>> +/**
>> + * fsp_cpu_mmc_init() - set up PCI MMC devices
>> + *
>> + * This finds all the matching PCI IDs and sets them up as MMC devices.
>> + *
>> + * @name: Name to use for devices
>> + * @mmc_supported: PCI IDs to search for
>> + * @n
Re: [U-Boot] [RFC PATCH 3/5] common/board_r: manual relocation for cmd table
2015-01-20 0:34 GMT+01:00 Simon Glass :
> Hi Andreas,
>
> On 19 January 2015 at 16:29, Andreas Bießmann
> wrote:
> > This is required for architectures still need manual relocation like
> avr32, mk68
> > and others.
> >
> > Signed-off-by: Andreas Bießmann
> > ---
> >
> > common/board_r.c | 12
> > 1 file changed, 12 insertions(+)
> >
> > diff --git a/common/board_r.c b/common/board_r.c
> > index a301cc2..e712902 100644
> > --- a/common/board_r.c
> > +++ b/common/board_r.c
> > @@ -294,6 +294,15 @@ static int initr_announce(void)
> > return 0;
> > }
> >
> > +#ifdef CONFIG_NEEDS_MANUAL_RELOC
> > +static int initr_manual_reloc_cmdtable(void)
> > +{
> > + fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd),
> > + ll_entry_count(cmd_tbl_t, cmd));
> > + return 0;
> > +}
> > +#endif
> > +
> > #if !defined(CONFIG_SYS_NO_FLASH)
> > static int initr_flash(void)
> > {
> > @@ -718,6 +727,9 @@ init_fnc_t init_sequence_r[] = {
> > initr_serial,
> > initr_announce,
> > INIT_FUNC_WATCHDOG_RESET
> > +#ifdef CONFIG_NEEDS_MANUAL_RELOC
> > + initr_manual_reloc_cmdtable,
> > +#endif
> > #ifdef CONFIG_PPC
> > initr_trap,
> > #endif
> > --
>
> Reviewed-by: Simon Glass
>
Tested-by: Michal Simek
I need this patch for microblaze generic-board support.
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform
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[U-Boot] [PATCH 02/14] microblaze: Show return address from exception
Show also return address from exception which should
suggest where the problem is.
Signed-off-by: Michal Simek
---
arch/microblaze/cpu/exception.c | 2 ++
arch/microblaze/include/asm/asm.h | 4
2 files changed, 6 insertions(+)
diff --git a/arch/microblaze/cpu/exception.c b/arch/microblaze/cpu/exception.c
index 227842f6a483..45729331f3d3 100644
--- a/arch/microblaze/cpu/exception.c
+++ b/arch/microblaze/cpu/exception.c
@@ -18,6 +18,8 @@ void _hw_exception_handler (void)
/* loading excetpion state register ESR */
MFS (state, resr);
printf ("Hardware exception at 0x%x address\n", address);
+ R17(address);
+ printf("Return address from exception 0x%x\n", address);
switch (state & 0x1f) { /* mask on exception cause */
case 0x1:
puts ("Unaligned data access exception\n");
diff --git a/arch/microblaze/include/asm/asm.h
b/arch/microblaze/include/asm/asm.h
index c1c3b0398579..11f3dd0f0ec0 100644
--- a/arch/microblaze/include/asm/asm.h
+++ b/arch/microblaze/include/asm/asm.h
@@ -43,6 +43,10 @@
#define R14(val) \
__asm__ __volatile__ ("addi %0, r14, 0":"=r" (val));
+/* get return address from interrupt */
+#define R17(val) \
+ __asm__ __volatile__ ("addi %0, r17, 0" : "=r" (val));
+
#define NOP__asm__ __volatile__ ("nop");
/* use machine status registe USE_MSR_REG */
--
1.8.2.3
pgpjfmYqhJnpI.pgp
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[U-Boot] [PATCH 01/14] microblaze: Fix stack usage in interrupt handler
Do not save registers below r1 stack pointer because it is not checked by stack undeflow is not able to detect it. Signed-off-by: Michal Simek --- arch/microblaze/cpu/irq.S | 121 +++--- 1 file changed, 60 insertions(+), 61 deletions(-) diff --git a/arch/microblaze/cpu/irq.S b/arch/microblaze/cpu/irq.S index 24015898b0aa..5cfe1516bfcd 100644 --- a/arch/microblaze/cpu/irq.S +++ b/arch/microblaze/cpu/irq.S @@ -11,71 +11,70 @@ .text .global _interrupt_handler _interrupt_handler: - swi r2, r1, -4 - swi r3, r1, -8 - swi r4, r1, -12 - swi r5, r1, -16 - swi r6, r1, -20 - swi r7, r1, -24 - swi r8, r1, -28 - swi r9, r1, -32 - swi r10, r1, -36 - swi r11, r1, -40 - swi r12, r1, -44 - swi r13, r1, -48 - swi r14, r1, -52 - swi r15, r1, -56 - swi r16, r1, -60 - swi r17, r1, -64 - swi r18, r1, -68 - swi r19, r1, -72 - swi r20, r1, -76 - swi r21, r1, -80 - swi r22, r1, -84 - swi r23, r1, -88 - swi r24, r1, -92 - swi r25, r1, -96 - swi r26, r1, -100 - swi r27, r1, -104 - swi r28, r1, -108 - swi r29, r1, -112 - swi r30, r1, -116 - swi r31, r1, -120 addik r1, r1, -124 + swi r2, r1, 4 + swi r3, r1, 8 + swi r4, r1, 12 + swi r5, r1, 16 + swi r6, r1, 20 + swi r7, r1, 24 + swi r8, r1, 28 + swi r9, r1, 32 + swi r10, r1, 36 + swi r11, r1, 40 + swi r12, r1, 44 + swi r13, r1, 48 + swi r14, r1, 52 + swi r15, r1, 56 + swi r16, r1, 60 + swi r17, r1, 64 + swi r18, r1, 68 + swi r19, r1, 72 + swi r20, r1, 76 + swi r21, r1, 80 + swi r22, r1, 84 + swi r23, r1, 88 + swi r24, r1, 92 + swi r25, r1, 96 + swi r26, r1, 100 + swi r27, r1, 104 + swi r28, r1, 108 + swi r29, r1, 112 + swi r30, r1, 116 + swi r31, r1, 120 brlid r15, interrupt_handler nop + lwi r31, r1, 120 + lwi r30, r1, 116 + lwi r29, r1, 112 + lwi r28, r1, 108 + lwi r27, r1, 104 + lwi r26, r1, 100 + lwi r25, r1, 96 + lwi r24, r1, 92 + lwi r23, r1, 88 + lwi r22, r1, 84 + lwi r21, r1, 80 + lwi r20, r1, 76 + lwi r19, r1, 72 + lwi r18, r1, 68 + lwi r17, r1, 64 + lwi r16, r1, 60 + lwi r15, r1, 56 + lwi r14, r1, 52 + lwi r13, r1, 48 + lwi r12, r1, 44 + lwi r11, r1, 40 + lwi r10, r1, 36 + lwi r9, r1, 32 + lwi r8, r1, 28 + lwi r7, r1, 24 + lwi r6, r1, 20 + lwi r5, r1, 16 + lwi r4, r1, 12 + lwi r3, r1, 8 + lwi r2, r1, 4 addik r1, r1, 124 - lwi r31, r1, -120 - lwi r30, r1, -116 - lwi r29, r1, -112 - lwi r28, r1, -108 - lwi r27, r1, -104 - lwi r26, r1, -100 - lwi r25, r1, -96 - lwi r24, r1, -92 - lwi r23, r1, -88 - lwi r22, r1, -84 - lwi r21, r1, -80 - lwi r20, r1, -76 - lwi r19, r1, -72 - lwi r18, r1, -68 - lwi r17, r1, -64 - lwi r16, r1, -60 - lwi r15, r1, -56 - lwi r14, r1, -52 - lwi r13, r1, -48 - lwi r12, r1, -44 - lwi r11, r1, -40 - lwi r10, r1, -36 - lwi r9, r1, -32 - lwi r8, r1, -28 - lwi r7, r1, -24 - lwi r6, r1, -20 - lwi r5, r1, -16 - lwi r4, r1, -12 - lwi r3, r1, -8 - lwi r2, r1, -4 - rtidr14, 0 nop .size _interrupt_handler,.-_interrupt_handler -- 1.8.2.3 pgpLtmN2ZOnEh.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 03/14] microblaze: Fix coding style in exception.c
Just coding style cleanup - no functional changes.
Signed-off-by: Michal Simek
---
arch/microblaze/cpu/exception.c | 33 +
1 file changed, 17 insertions(+), 16 deletions(-)
diff --git a/arch/microblaze/cpu/exception.c b/arch/microblaze/cpu/exception.c
index 45729331f3d3..aa34f45befe1 100644
--- a/arch/microblaze/cpu/exception.c
+++ b/arch/microblaze/cpu/exception.c
@@ -13,51 +13,52 @@ void _hw_exception_handler (void)
{
int address = 0;
int state = 0;
+
/* loading address of exception EAR */
- MFS (address, rear);
+ MFS(address, rear);
/* loading excetpion state register ESR */
- MFS (state, resr);
- printf ("Hardware exception at 0x%x address\n", address);
+ MFS(state, resr);
+ printf("Hardware exception at 0x%x address\n", address);
R17(address);
printf("Return address from exception 0x%x\n", address);
switch (state & 0x1f) { /* mask on exception cause */
case 0x1:
- puts ("Unaligned data access exception\n");
+ puts("Unaligned data access exception\n");
break;
case 0x2:
- puts ("Illegal op-code exception\n");
+ puts("Illegal op-code exception\n");
break;
case 0x3:
- puts ("Instruction bus error exception\n");
+ puts("Instruction bus error exception\n");
break;
case 0x4:
- puts ("Data bus error exception\n");
+ puts("Data bus error exception\n");
break;
case 0x5:
- puts ("Divide by zero exception\n");
+ puts("Divide by zero exception\n");
break;
#ifdef MICROBLAZE_V5
case 0x7:
puts("Priviledged or stack protection violation exception\n");
break;
case 0x1000:
- puts ("Exception in delay slot\n");
+ puts("Exception in delay slot\n");
break;
#endif
default:
- puts ("Undefined cause\n");
+ puts("Undefined cause\n");
break;
}
- printf ("Unaligned %sword access\n", ((state & 0x800) ? "" : "half"));
- printf ("Unaligned %s access\n", ((state & 0x400) ? "store" : "load"));
- printf ("Register R%x\n", (state & 0x3E) >> 5);
- hang ();
+ printf("Unaligned %sword access\n", ((state & 0x800) ? "" : "half"));
+ printf("Unaligned %s access\n", ((state & 0x400) ? "store" : "load"));
+ printf("Register R%x\n", (state & 0x3E) >> 5);
+ hang();
}
#ifdef CONFIG_SYS_USR_EXCEP
void _exception_handler (void)
{
- puts ("User vector_exception\n");
- hang ();
+ puts("User vector_exception\n");
+ hang();
}
#endif
--
1.8.2.3
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[U-Boot] [PATCH 05/14] microblaze: Fix coding style
No functional changes just to pass checkpatch.pl.
Signed-off-by: Michal Simek
---
arch/microblaze/cpu/interrupts.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/microblaze/cpu/interrupts.c b/arch/microblaze/cpu/interrupts.c
index 030e9147dc40..771bbd0ca628 100644
--- a/arch/microblaze/cpu/interrupts.c
+++ b/arch/microblaze/cpu/interrupts.c
@@ -84,12 +84,12 @@ int install_interrupt_handler(int irq, interrupt_handler_t
*hdlr, void *arg)
act->handler = hdlr;
act->arg = arg;
act->count = 0;
- enable_one_interrupt (irq);
+ enable_one_interrupt(irq);
return 0;
}
/* Disable */
- act->handler = (interrupt_handler_t *) def_hdlr;
+ act->handler = (interrupt_handler_t *)def_hdlr;
act->arg = (void *)irq;
disable_one_interrupt(irq);
return 1;
@@ -113,7 +113,7 @@ int interrupts_init(void)
int i;
#if defined(CONFIG_SYS_INTC_0_ADDR) && defined(CONFIG_SYS_INTC_0_NUM)
- intc = (microblaze_intc_t *) (CONFIG_SYS_INTC_0_ADDR);
+ intc = (microblaze_intc_t *)CONFIG_SYS_INTC_0_ADDR;
irq_no = CONFIG_SYS_INTC_0_NUM;
#endif
if (irq_no) {
@@ -125,7 +125,7 @@ int interrupts_init(void)
/* initialize irq list */
for (i = 0; i < irq_no; i++) {
- vecs[i].handler = (interrupt_handler_t *) def_hdlr;
+ vecs[i].handler = (interrupt_handler_t *)def_hdlr;
vecs[i].arg = (void *)i;
vecs[i].count = 0;
}
@@ -154,7 +154,7 @@ void interrupt_handler(void)
debug("Jumping to interrupt handler rutine addr %x,count %x,arg %x\n",
(u32)act->handler, act->count, (u32)act->arg);
- act->handler (act->arg);
+ act->handler(act->arg);
act->count++;
intc->iar = mask << irqs;
@@ -179,10 +179,10 @@ int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc,
const char *argv[])
"-\n");
for (i = 0; i < irq_no; i++) {
- if (act->handler != (interrupt_handler_t *) def_hdlr) {
+ if (act->handler != (interrupt_handler_t *)def_hdlr) {
printf("%02d %08x %08x %d\n", i,
- (int)act->handler, (int)act->arg,
- act->count);
+ (int)act->handler, (int)act->arg,
+ act->count);
}
act++;
}
--
1.8.2.3
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[U-Boot] [PATCH 09/14] microblaze: Remove unused asm label
It is not used at all that's why remove it. Signed-off-by: Michal Simek --- arch/microblaze/cpu/start.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index 84c29e54091e..e0e3470a181a 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -129,7 +129,7 @@ _start: /* Flush cache before enable cache */ addik r5, r0, 0 addik r6, r0, XILINX_DCACHE_BYTE_SIZE -flush: bralid r15, flush_cache + bralid r15, flush_cache nop /* enable instruction and data cache */ -- 1.8.2.3 pgp4SIEPb1Lz8.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 07/14] microblaze: Remove unneeded data section adding from DTB
DTB is added to rodata section:
[ 2] .rodata PROGBITS84c5b60c 05c60c 00c618 00 A
0 0 4
[ 3] .dtb.init.rodata PROGBITS84c67c30 068c30 003c80 00 A
0 0 16
[ 4] .rela.dyn RELA84c6b8b0 06c8b0 000534 0c A
0 0 4
[ 5] .data PROGBITS84c6bde4 06cde4 001536 00 WA
0 0 16
Signed-off-by: Michal Simek
---
arch/microblaze/cpu/u-boot.lds | 3 ---
1 file changed, 3 deletions(-)
diff --git a/arch/microblaze/cpu/u-boot.lds b/arch/microblaze/cpu/u-boot.lds
index fdad20753d32..44bc036172f0 100644
--- a/arch/microblaze/cpu/u-boot.lds
+++ b/arch/microblaze/cpu/u-boot.lds
@@ -29,9 +29,6 @@ SECTIONS
.data ALIGN(0x4):
{
__data_start = .;
-#ifdef CONFIG_OF_EMBED
- dts/built-in.o (.data)
-#endif
*(.data)
__data_end = .;
}
--
1.8.2.3
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[U-Boot] [PATCH 04/14] microblaze: Remove DEBUG_INT macro and use debug() instead
Do not use specific macros for debugging.
Also remove compilation warning:
w+../arch/microblaze/cpu/interrupts.c: In function 'interrupt_handler':
w+../arch/microblaze/cpu/interrupts.c:153:2: warning: format '%x'
expects argument of type 'unsigned int', but argument 2 has type 'void
(*)(void *)' [-Wformat]
w+../arch/microblaze/cpu/interrupts.c:153:2: warning: format '%x'
expects argument of type 'unsigned int', but argument 4 has type 'void
*' [-Wformat]
Signed-off-by: Michal Simek
---
arch/microblaze/cpu/interrupts.c | 57 ++--
1 file changed, 25 insertions(+), 32 deletions(-)
diff --git a/arch/microblaze/cpu/interrupts.c b/arch/microblaze/cpu/interrupts.c
index 9364e2fa9c9b..030e9147dc40 100644
--- a/arch/microblaze/cpu/interrupts.c
+++ b/arch/microblaze/cpu/interrupts.c
@@ -14,8 +14,6 @@
#include
#include
-#undef DEBUG_INT
-
void enable_interrupts(void)
{
MSRSET(0x2);
@@ -50,12 +48,11 @@ static void enable_one_interrupt(int irq)
offset <<= irq;
mask = intc->ier;
intc->ier = (mask | offset);
-#ifdef DEBUG_INT
- printf("Enable one interrupt irq %x - mask %x,ier %x\n", offset, mask,
- intc->ier);
- printf("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
- intc->iar, intc->mer);
-#endif
+
+ debug("Enable one interrupt irq %x - mask %x,ier %x\n", offset, mask,
+ intc->ier);
+ debug("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
+ intc->iar, intc->mer);
}
static void disable_one_interrupt(int irq)
@@ -66,12 +63,11 @@ static void disable_one_interrupt(int irq)
offset <<= irq;
mask = intc->ier;
intc->ier = (mask & ~offset);
-#ifdef DEBUG_INT
- printf("Disable one interrupt irq %x - mask %x,ier %x\n", irq, mask,
- intc->ier);
- printf("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
- intc->iar, intc->mer);
-#endif
+
+ debug("Disable one interrupt irq %x - mask %x,ier %x\n", irq, mask,
+ intc->ier);
+ debug("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
+ intc->iar, intc->mer);
}
int install_interrupt_handler(int irq, interrupt_handler_t *hdlr, void *arg)
@@ -107,10 +103,9 @@ static void intc_init(void)
intc->iar = 0x;
/* XIntc_Start - hw_interrupt enable and all interrupt enable */
intc->mer = 0x3;
-#ifdef DEBUG_INT
- printf("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
- intc->iar, intc->mer);
-#endif
+
+ debug("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
+ intc->iar, intc->mer);
}
int interrupts_init(void)
@@ -147,31 +142,29 @@ void interrupt_handler(void)
{
int irqs = intc->ivr; /* find active interrupt */
int mask = 1;
-#ifdef DEBUG_INT
int value;
- printf ("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
- intc->iar, intc->mer);
- R14(value);
- printf ("Interrupt handler on %x line, r14 %x\n", irqs, value);
-#endif
struct irq_action *act = vecs + irqs;
-#ifdef DEBUG_INT
- printf
- ("Jumping to interrupt handler rutine addr %x,count %x,arg %x\n",
-act->handler, act->count, act->arg);
+ debug("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
+ intc->iar, intc->mer);
+#ifdef DEBUG
+ R14(value);
#endif
+ debug("Interrupt handler on %x line, r14 %x\n", irqs, value);
+
+ debug("Jumping to interrupt handler rutine addr %x,count %x,arg %x\n",
+ (u32)act->handler, act->count, (u32)act->arg);
act->handler (act->arg);
act->count++;
intc->iar = mask << irqs;
-#ifdef DEBUG_INT
- printf ("Dump INTC reg, isr %x, ier %x, iar %x, mer %x\n", intc->isr,
- intc->ier, intc->iar, intc->mer);
+ debug("Dump INTC reg, isr %x, ier %x, iar %x, mer %x\n", intc->isr,
+ intc->ier, intc->iar, intc->mer);
+#ifdef DEBUG
R14(value);
- printf ("Interrupt handler on %x line, r14 %x\n", irqs, value);
#endif
+ debug("Interrupt handler on %x line, r14 %x\n", irqs, value);
}
#if defined(CONFIG_CMD_IRQ)
--
1.8.2.3
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[U-Boot] [PATCH 08/14] microblaze: Use standard interrupt_init() function
Do not use microblaze specific interrupt init function.
Signed-off-by: Michal Simek
---
arch/microblaze/cpu/interrupts.c | 2 +-
arch/microblaze/include/asm/microblaze_intc.h | 2 --
arch/microblaze/lib/board.c | 2 +-
3 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/microblaze/cpu/interrupts.c b/arch/microblaze/cpu/interrupts.c
index f66ec69ee25e..b6d6610f2fd7 100644
--- a/arch/microblaze/cpu/interrupts.c
+++ b/arch/microblaze/cpu/interrupts.c
@@ -109,7 +109,7 @@ static void intc_init(void)
intc->iar, intc->mer);
}
-int interrupts_init(void)
+int interrupt_init(void)
{
int i;
diff --git a/arch/microblaze/include/asm/microblaze_intc.h
b/arch/microblaze/include/asm/microblaze_intc.h
index 0fb9207882fe..65868386b0d8 100644
--- a/arch/microblaze/include/asm/microblaze_intc.h
+++ b/arch/microblaze/include/asm/microblaze_intc.h
@@ -34,5 +34,3 @@ struct irq_action {
*/
int install_interrupt_handler(int irq, interrupt_handler_t *hdlr,
void *arg);
-
-int interrupts_init(void);
diff --git a/arch/microblaze/lib/board.c b/arch/microblaze/lib/board.c
index 600c80ab7666..bd028a63c078 100644
--- a/arch/microblaze/lib/board.c
+++ b/arch/microblaze/lib/board.c
@@ -55,7 +55,7 @@ init_fnc_t *init_sequence[] = {
#endif
display_banner,
#ifndef CONFIG_SPL_BUILD
- interrupts_init,
+ interrupt_init,
timer_init,
#endif
NULL,
--
1.8.2.3
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[U-Boot] [PATCH 06/14] microblaze: Add debug message about enabling interrupts
Add one more debug message about enabling global interrupts.
Signed-off-by: Michal Simek
---
arch/microblaze/cpu/interrupts.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/microblaze/cpu/interrupts.c b/arch/microblaze/cpu/interrupts.c
index 771bbd0ca628..f66ec69ee25e 100644
--- a/arch/microblaze/cpu/interrupts.c
+++ b/arch/microblaze/cpu/interrupts.c
@@ -16,6 +16,7 @@
void enable_interrupts(void)
{
+ debug("Enable interrupts for the whole CPU\n");
MSRSET(0x2);
}
--
1.8.2.3
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[U-Boot] [PATCH 14/14] bdinfo: Show information about fdt blob via bdinfo
Microblaze target supports both OF and !OF cases
and from log is not clear which version is running.
Signed-off-by: Michal Simek
---
common/cmd_bdinfo.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
index 4c51059c1ba4..e9eab232f961 100644
--- a/common/cmd_bdinfo.c
+++ b/common/cmd_bdinfo.c
@@ -204,6 +204,9 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *
const argv[])
printf("baudrate= %u bps\n", gd->baudrate);
print_num("relocaddr", gd->relocaddr);
print_num("reloc off", gd->reloc_off);
+ print_num("fdt_blob", (ulong)gd->fdt_blob);
+ print_num("new_fdt", (ulong)gd->new_fdt);
+ print_num("fdt_size", (ulong)gd->fdt_size);
return 0;
}
--
1.8.2.3
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[U-Boot] [PATCH 10/14] microblaze: Fix gd_t address which is placed at the end of BRAM
Setup gd from ASM to be availalbe for board_init_r.
Setting it up in spl_board_init is too late when
MALLOC is used.
Space for gd is located behind MALLOC area at the end of BRAM.
Signed-off-by: Michal Simek
---
arch/microblaze/cpu/spl.c | 2 --
arch/microblaze/cpu/start.S | 1 +
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/microblaze/cpu/spl.c b/arch/microblaze/cpu/spl.c
index 091226133e4f..2cc0a2da89e1 100644
--- a/arch/microblaze/cpu/spl.c
+++ b/arch/microblaze/cpu/spl.c
@@ -25,8 +25,6 @@ u32 spl_boot_device(void)
/* Board initialization after bss clearance */
void spl_board_init(void)
{
- gd = (gd_t *)CONFIG_SPL_STACK_ADDR;
-
/* enable console uart printing */
preloader_console_init();
}
diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S
index e0e3470a181a..14c2f12da06b 100644
--- a/arch/microblaze/cpu/start.S
+++ b/arch/microblaze/cpu/start.S
@@ -152,6 +152,7 @@ clear_bss:
#ifndef CONFIG_SPL_BUILD
braiboard_init_f
#else
+ addir31, r0, CONFIG_SYS_SPL_MALLOC_END
braiboard_init_r
#endif
1: bri 1b
--
1.8.2.3
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[U-Boot] [PATCH 13/14] microblaze: Speedup code copy
Remove one instruction in the loop which speedup code copying. Signed-off-by: Michal Simek --- arch/microblaze/cpu/start.S | 12 +++- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index 3de0e12090ea..4023ec067531 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -212,12 +212,14 @@ relocate_code: /* Relocate text and data - r12 temp value */ addir21, r0, _start addir22, r0, __end - 4 /* Include BSS too */ -1: lwi r12, r21, 0 /* Load u-boot data */ - swi r12, r23, 0 /* Write zero to loc */ - addir21, r21, 4 /* Increment to next loc - origin code */ - cmp r12, r21, r22 /* Check if we have reach the end */ + + rsubr6, r21, r22 + or r5, r0, r0 +1: lw r12, r21, r5 /* Load u-boot data */ + sw r12, r23, r5 /* Write zero to loc */ + cmp r12, r5, r6 /* Check if we have reach the end */ bneid r12, 1b - addir23, r23, 4 /* Increment to next loc - relocate code */ + addir5, r5, 4 /* Increment to next loc - relocate code */ /* R23 points to the base address. */ add r23, r0, r7 /* Move reloc addr to r23 */ -- 1.8.2.3 pgp_kvD0dYtVS.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 11/14] microblaze: Enable SPL_NOR support when FLASH_BASE is setup
Simplify SPL NOR init. Signed-off-by: Michal Simek --- include/configs/microblaze-generic.h | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index bb070600021b..2e1e64247fe0 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -452,7 +452,10 @@ #define CONFIG_SPL_LDSCRIPT"arch/microblaze/cpu/u-boot-spl.lds" #define CONFIG_SPL_RAM_DEVICE -#define CONFIG_SPL_NOR_SUPPORT +#ifdef CONFIG_SYS_FLASH_BASE +# define CONFIG_SPL_NOR_SUPPORT +# define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE +#endif /* for booting directly linux */ #define CONFIG_SPL_OS_BOOT @@ -491,7 +494,6 @@ /* Just for sure that there is a space for stack */ #define CONFIG_SPL_STACK_SIZE 0x100 -#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \ -- 1.8.2.3 pgp4Q_04kwXs9.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 00/12] exynos: enable dm i2c
+Minkyu Hi Przemyslaw, On 27 January 2015 at 05:36, Przemyslaw Marczak wrote: > This patchset adds support to driver model i2c api for Exynos i2c driver. > Few boards are using this driver, but the board peripherals are not ported > to the new api yet. So the CONFIG_DM_I2C_COMPAT is enabled. > > Switch to dm i2c is currentlly not possible for the few devices like > Trats2, Universal C210, S5P Goni, because ir require soft i2c support. > > For Odroid U3, the compatiblility layer is enabled, because it uses only > one pmic driver, which soon is going to be moved to dm i2c with the dm pmic > framework. > > The i2c dm compatibility layer is also enabled for Exynos5 boards, > which should be removed after moving the i2c drivers to driver model. I plan to pick this series up for the driver model tree and hopefully get it in in time for RC1. Minkyu is that OK with you? > > The main change from the previous version is: > - non-required code cleanup after Simon Glass comments > - add new pinmux flag for Exynos > - split commit with s3c i2c status timeout change > - fix build error for u-boot-dm/master If you use patman Series-changes tags it will automate the change logs for you. > > Przemyslaw Marczak (12): > dm: i2c-uclass-compat: fix missed argument > arndale: config: disable max77686 support > exynos5250: config: disable max77686 driver > smdk5250: config: enable max77686 driver support > exynos4: dts: add missing i2c properties > arndale: dts: add missing i2c aliases > exynos5: pinmux: check flag for i2c config > i2c: s3c24x0: reduce transmission status timeout > dm: i2c: s3c24x0: adjust to dm-i2c api > odroid u3: dts: add missing i2c aliases > odroid u3: enable dm i2c support > exynos5: enable dm i2c > > arch/arm/cpu/armv7/exynos/pinmux.c| 27 +++- > arch/arm/dts/exynos4.dtsi | 24 ++- > arch/arm/dts/exynos4412-odroid.dts| 7 + > arch/arm/dts/exynos5250-arndale.dts | 8 + > arch/arm/include/asm/arch-exynos/pinmux.h | 3 + > board/samsung/odroid/odroid.c | 14 +- > drivers/i2c/i2c-uclass-compat.c | 2 +- > drivers/i2c/s3c24x0_i2c.c | 241 > -- > include/configs/arndale.h | 2 - > include/configs/exynos5-common.h | 7 +- > include/configs/exynos5250-common.h | 3 - > include/configs/odroid.h | 5 +- > include/configs/smdk5250.h| 2 + > 13 files changed, 258 insertions(+), 87 deletions(-) > > -- > 1.9.1 Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 08/12] i2c: s3c24x0: reduce transmission status timeout
Hi, On 27 January 2015 at 05:36, Przemyslaw Marczak wrote: > If no device is connected to I2C bus, the i2c probe command > can take a lot of time for probe each address. This commit > reduces the busy timeout to 10ms for standard and high speed > modes. This doesn't break the transmission an also allow for > properly probe the devices. > > Signed-off-by: Przemyslaw Marczak Tested-by: Simon Glass This patch looks OK but I'd like to get other comments if possible. > > Changes v3: > - new commit, after split the next one > --- > drivers/i2c/s3c24x0_i2c.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c > index fd328f0..3129c7f 100644 > --- a/drivers/i2c/s3c24x0_i2c.c > +++ b/drivers/i2c/s3c24x0_i2c.c > @@ -111,9 +111,9 @@ > #define I2C_START_STOP 0x20/* START / STOP */ > #define I2C_TXRX_ENA 0x10/* I2C Tx/Rx enable */ > > -#define I2C_TIMEOUT_MS 1000/* 1 second */ > +#define I2C_TIMEOUT_MS 10 /* 10 ms */ > > -#defineHSI2C_TIMEOUT_US 10 /* 100 ms, finer granularity */ > +#defineHSI2C_TIMEOUT_US 1 /* 10 ms, finer granularity */ > > > /* To support VCMA9 boards and other who dont define max_i2c_num */ > -- > 1.9.1 > Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 07/12] exynos5: pinmux: check flag for i2c config
On 27 January 2015 at 05:36, Przemyslaw Marczak wrote:
> Some versions of Exynos5 supports High-Speed I2C,
> on few interfaces, this change allows support this.
> The new flag is: PINMUX_FLAG_HS_MODE
>
> Signed-off-by: Przemyslaw Marczak
> Cc: Simon Glass
> Cc: Akshay Saraswat
> Cc: Minkyu Kang
>
> ---
> Changes v3:
> - add new flag: PINMUX_FLAG_HS_MODE
> ---
> arch/arm/cpu/armv7/exynos/pinmux.c| 27 +++
> arch/arm/include/asm/arch-exynos/pinmux.h | 3 +++
> 2 files changed, 22 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c
> b/arch/arm/cpu/armv7/exynos/pinmux.c
> index 94d0297..be43e22 100644
> --- a/arch/arm/cpu/armv7/exynos/pinmux.c
> +++ b/arch/arm/cpu/armv7/exynos/pinmux.c
> @@ -266,22 +266,33 @@ static void exynos5_sromc_config(int flags)
>
> static void exynos5_i2c_config(int peripheral, int flags)
> {
> + int func01, func23;
> +
> +/* High-Speed I2C */
> + if (flags & PINMUX_FLAG_HS_MODE) {
> + func01 = 4;
> + func23 = 4;
> + } else {
> + func01 = 2;
> + func23 = 3;
> + }
> +
> switch (peripheral) {
> case PERIPH_ID_I2C0:
> - gpio_cfg_pin(EXYNOS5_GPIO_B30, S5P_GPIO_FUNC(0x2));
> - gpio_cfg_pin(EXYNOS5_GPIO_B31, S5P_GPIO_FUNC(0x2));
> + gpio_cfg_pin(EXYNOS5_GPIO_B30, S5P_GPIO_FUNC(func01));
> + gpio_cfg_pin(EXYNOS5_GPIO_B31, S5P_GPIO_FUNC(func01));
> break;
> case PERIPH_ID_I2C1:
> - gpio_cfg_pin(EXYNOS5_GPIO_B32, S5P_GPIO_FUNC(0x2));
> - gpio_cfg_pin(EXYNOS5_GPIO_B33, S5P_GPIO_FUNC(0x2));
> + gpio_cfg_pin(EXYNOS5_GPIO_B32, S5P_GPIO_FUNC(func01));
> + gpio_cfg_pin(EXYNOS5_GPIO_B33, S5P_GPIO_FUNC(func01));
> break;
> case PERIPH_ID_I2C2:
> - gpio_cfg_pin(EXYNOS5_GPIO_A06, S5P_GPIO_FUNC(0x3));
> - gpio_cfg_pin(EXYNOS5_GPIO_A07, S5P_GPIO_FUNC(0x3));
> + gpio_cfg_pin(EXYNOS5_GPIO_A06, S5P_GPIO_FUNC(func23));
> + gpio_cfg_pin(EXYNOS5_GPIO_A07, S5P_GPIO_FUNC(func23));
> break;
> case PERIPH_ID_I2C3:
> - gpio_cfg_pin(EXYNOS5_GPIO_A12, S5P_GPIO_FUNC(0x3));
> - gpio_cfg_pin(EXYNOS5_GPIO_A13, S5P_GPIO_FUNC(0x3));
> + gpio_cfg_pin(EXYNOS5_GPIO_A12, S5P_GPIO_FUNC(func23));
> + gpio_cfg_pin(EXYNOS5_GPIO_A13, S5P_GPIO_FUNC(func23));
> break;
> case PERIPH_ID_I2C4:
> gpio_cfg_pin(EXYNOS5_GPIO_A20, S5P_GPIO_FUNC(0x3));
> diff --git a/arch/arm/include/asm/arch-exynos/pinmux.h
> b/arch/arm/include/asm/arch-exynos/pinmux.h
> index 0b91ef6..d0ae757 100644
> --- a/arch/arm/include/asm/arch-exynos/pinmux.h
> +++ b/arch/arm/include/asm/arch-exynos/pinmux.h
> @@ -23,6 +23,9 @@ enum {
> /* Flags for SROM controller */
> PINMUX_FLAG_BANK= 3 << 0, /* bank number (0-3) */
> PINMUX_FLAG_16BIT = 1 << 2, /* 16-bit width */
> +
> + /* Flags for I2C */
> + PINMUX_FLAG_HS_MODE = 1 << 1, /* I2C High Speed Mode */
> };
>
> /**
Acked-by: Simon Glass
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Re: [U-Boot] [PATCH v3 09/12] dm: i2c: s3c24x0: adjust to dm-i2c api
On 27 January 2015 at 05:36, Przemyslaw Marczak wrote: > This commit adjusts the s3c24x0 driver to new i2c api > based on driver-model. The driver supports standard > and high-speed i2c as previous. > > Tested on Trats2, Odroid U3, Arndale, Odroid XU3 > > Signed-off-by: Przemyslaw Marczak > Tested-by: Simon Glass > Cc: Simon Glass > Cc: Heiko Schocher > Cc: Minkyu Kang Retested on snow. Acked-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 01/12] dm: i2c-uclass-compat: fix missed argument
Hi Przemyslaw, On 27 January 2015 at 05:36, Przemyslaw Marczak wrote: > This patch fixes build error for CONFIG_DM_I2C_COMPAT. > In i2c_get_chip_for_busnum() call, one of argument was missed, > which was offset_len. Now it is set to 'alen' as previous. > > Signed-off-by: Przemyslaw Marczak > --- > drivers/i2c/i2c-uclass-compat.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/i2c/i2c-uclass-compat.c b/drivers/i2c/i2c-uclass-compat.c > index 11239da..841ce05 100644 > --- a/drivers/i2c/i2c-uclass-compat.c > +++ b/drivers/i2c/i2c-uclass-compat.c > @@ -17,7 +17,7 @@ static int i2c_compat_get_device(uint chip_addr, int alen, > struct dm_i2c_chip *chip; > int ret; > > - ret = i2c_get_chip_for_busnum(cur_busnum, chip_addr, devp); > + ret = i2c_get_chip_for_busnum(cur_busnum, chip_addr, alen, devp); > if (ret) > return ret; > chip = dev_get_parent_platdata(*devp); > -- Thanks. I sent a patch which fixes this too but have not yet applied it. Acked-by: Simon Glass Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] patman: Make dry-run output match real functionality
On Mon, 2015-01-26 at 22:21 -0700, Simon Glass wrote: > Hi Peter, > > On 26 January 2015 at 10:42, Peter Tyser wrote: > > When run with the --dry-run argument patman prints out information > > showing what it would do. This information currently doesn't line up > > with what patman/git send-email really do. Some basic examples: > > - If an email address is addressed via "Series-cc" and "Patch-cc" patman > > shows that email address would be CC-ed two times. > > - If an email address is addressed via "Series-to" and "Patch-cc" patman > > shows that email address would be sent TO and CC-ed. > > - If an email address is addressed from a combination of tag aliases, > > get_maintainer.pl output, "Series-cc", "Patch-cc", etc patman shows > > that the email address would be CC-ed multiple times. > > > > Patman currently does try to send duplicate emails like the --dry-run > > output shows, but "git send-email" intelligently removes duplicate > > addresses so this patch shouldn't change the non-dry-run functionality. > > > > Change patman's output and email addressing to line up with the > > "git send-email" logic. This trims down patman's dry-run output and > > prevents confusion about what patman will do when emails are actually > > sent. > > Thanks for the patch, it's good to match up with git send-email. > > Are the rules that git send-email follows documented or obtained by > trial and error? Trial and error initially. The git source code lined up with what I saw (see the send_message function in git-send-email.perl). I didn't see the policy documented officially, but what git does makes sense to me: - remove any duplicate addresses in the to: field - remove all the to: addresses from the cc: addresses - remove any duplicate cc: addresses This makes sure each email is only sent to an address one time, with the to: field taking precedence over the cc: field. For a recent NAND patch series it looked like I was going to send Scott 2-4 emails per patch which is why I looked into it. Regards, Peter ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 08/12] i2c: s3c24x0: reduce transmission status timeout
Hello, On 01/27/2015 04:38 PM, Simon Glass wrote: Hi, On 27 January 2015 at 05:36, Przemyslaw Marczak wrote: If no device is connected to I2C bus, the i2c probe command can take a lot of time for probe each address. This commit reduces the busy timeout to 10ms for standard and high speed modes. This doesn't break the transmission an also allow for properly probe the devices. Signed-off-by: Przemyslaw Marczak Tested-by: Simon Glass This patch looks OK but I'd like to get other comments if possible. [cut] Ok, that's fine. I tested this on Trats2 and Odroid XU3 and it works fine. Best regards, -- Przemyslaw Marczak Samsung R&D Institute Poland Samsung Electronics p.marc...@samsung.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] spl: Change printf to puts for "Unsupported boot-device"
Microblaze currently doesn't use printf in SPL. So this one line was the only
reference to it and resulted in the printf functionality to be pulled in.
Exceeding the 4k size limit. Lets change the printf back to puts so that
Microblaze is fixed again. The only drawback is that the detected boot-device
number will not be printed. But this message alone should be helpful enough
to get an idea where the boot process is broken.
Signed-off-by: Stefan Roese
Cc: Tom Rini
Cc: Michal Simek
---
common/spl/spl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 1826c47..daaeb50 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -231,7 +231,7 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
#endif
default:
#if defined(CONFIG_SPL_SERIAL_SUPPORT) && defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
- printf("SPL: Unsupported Boot Device %d\n", boot_device);
+ puts("SPL: Unsupported Boot Device!\n");
#endif
hang();
}
--
2.2.2
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Re: [U-Boot] [PATCH] spl: Change printf to puts for "Unsupported boot-device"
On Tue, Jan 27, 2015 at 04:45:09PM +0100, Stefan Roese wrote: > Microblaze currently doesn't use printf in SPL. So this one line was the only > reference to it and resulted in the printf functionality to be pulled in. > Exceeding the 4k size limit. Lets change the printf back to puts so that > Microblaze is fixed again. The only drawback is that the detected boot-device > number will not be printed. But this message alone should be helpful enough > to get an idea where the boot process is broken. > > Signed-off-by: Stefan Roese > Cc: Tom Rini > Cc: Michal Simek Since we have a debug() higher up that will print out what the value is, I'm OK with this and I'll apply shortly, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 12/14] microblaze: Move architecture to use generic board init
Compile code with -fPIC to get GOT. Do not build SPL with fPIC because it increasing SPL size for nothing. Signed-off-by: Michal Simek --- This code requires "common/board_r: manual relocation for cmd table" http://lists.denx.de/pipermail/u-boot/2015-January/201965.html Not fully happy about it because compare to previous solution adds almost +60k on size for doing the same thing as before. 15: microblaze: Move architecture to use generic board init microblaze: (for 1/1 boards) all +52268.0 bss -4.0 data +11724.0 rodata -2676.0 spl/u-boot-spl:all +36.0 spl/u-boot-spl:data +36.0 text +43224.0 microblaze-generic: all +52268 bss -4 data +11724 rodata -2676 spl/u-boot-spl:all +36 spl/u-boot-spl:data +36 text +43224 --- arch/microblaze/config.mk | 5 + arch/microblaze/cpu/start.S| 103 +++ arch/microblaze/cpu/u-boot.lds | 9 + arch/microblaze/include/asm/config.h | 8 + arch/microblaze/include/asm/u-boot.h | 11 +- arch/microblaze/lib/Makefile | 1 - arch/microblaze/lib/board.c| 201 - .../xilinx/microblaze-generic/microblaze-generic.c | 46 + common/board_f.c | 6 +- common/board_r.c | 2 +- common/cmd_bdinfo.c| 13 +- include/configs/microblaze-generic.h | 64 +-- 12 files changed, 196 insertions(+), 273 deletions(-) delete mode 100644 arch/microblaze/lib/board.c diff --git a/arch/microblaze/config.mk b/arch/microblaze/config.mk index 98bbf794fa7d..2b817be61a5d 100644 --- a/arch/microblaze/config.mk +++ b/arch/microblaze/config.mk @@ -15,3 +15,8 @@ endif CONFIG_STANDALONE_LOAD_ADDR ?= 0x80F0 PLATFORM_CPPFLAGS += -ffixed-r31 -D__microblaze__ + +ifeq ($(CONFIG_SPL_BUILD),) +PLATFORM_CPPFLAGS += -fPIC +endif +__HAVE_ARCH_GENERIC_BOARD := y diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index 14c2f12da06b..3de0e12090ea 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -150,6 +150,7 @@ clear_bss: bneir6, 2b 3: /* jumping to board_init */ #ifndef CONFIG_SPL_BUILD + or r5, r0, r0 /* flags - empty */ braiboard_init_f #else addir31, r0, CONFIG_SYS_SPL_MALLOC_END @@ -190,4 +191,106 @@ out16:bslli r3, r6, 8 rtsdr15, 8 or r0, r0, r0 .endout16 + +/* + * Relocate u-boot + */ + .text + .global relocate_code + .entrelocate_code + .align 2 +relocate_code: + /* +* r5 - start_addr_sp +* r6 - new_gd +* r7 - reloc_addr +*/ + addir1, r5, 0 /* Start to use new SP */ + addir31, r6, 0 /* Start to use new GD */ + + add r23, r0, r7 /* Move reloc addr to r23 */ + /* Relocate text and data - r12 temp value */ + addir21, r0, _start + addir22, r0, __end - 4 /* Include BSS too */ +1: lwi r12, r21, 0 /* Load u-boot data */ + swi r12, r23, 0 /* Write zero to loc */ + addir21, r21, 4 /* Increment to next loc - origin code */ + cmp r12, r21, r22 /* Check if we have reach the end */ + bneid r12, 1b + addir23, r23, 4 /* Increment to next loc - relocate code */ + + /* R23 points to the base address. */ + add r23, r0, r7 /* Move reloc addr to r23 */ + addir24, r0, CONFIG_SYS_TEXT_BASE /* Get reloc offset */ + rsubr23, r24, r23 /* keep - this is already here gd->reloc_off */ + + addik r6, r0, 0x2 /* BIG/LITTLE endian offset */ + lwi r7, r0, 0x28 + swi r6, r0, 0x28 /* used first unused MB vector */ + lbuir10, r0, 0x28 /* used first unused MB vector */ + swi r7, r0, 0x28 + +#ifdef CONFIG_SYS_USR_EXCEP + addik r6, r0, _exception_handler + addkr6, r6, r23 /* add offset */ + sw r6, r1, r0 + lhu r7, r1, r10 + rsubi r8, r10, 0xa + sh r7, r0, r8 + rsubi r8, r10, 0xe + sh r6, r0, r8 +#endif + addik r6, r0, _hw_exception_handler + addkr6, r6, r23 /* add offset */ + sw r6, r1, r0 + lhu r7, r1, r10 + rsubi r8, r10, 0x22 + sh r7, r0, r8 + rsubi r8, r10, 0x26 + sh r6, r0, r8 + + addik r6, r0, _interrupt_handler + addkr6, r6, r23 /* add offset */ + sw r6, r1, r0 + lhu r7, r1, r10 + rsubi r8, r10, 0x12 + sh r7, r0, r8 + rsubi r8, r10, 0x16 + sh r6, r0, r8 + + /* Check if GOT exist */ + addik r21, r23, _got_start + addik r22, r23, _got_end + cmpur12, r21, r22 + beqir12, 2f /* No GOT table - jump over */ + + /* Skip last 3 entries plus 1 becau
Re: [U-Boot] [PATCH 20/23] scsi: bootstage: Measure time taken to scan the bus
On Mon, Jan 26, 2015 at 7:23 PM, Simon Glass wrote: > On some hardware this time can be significant. Add bootstage support for > measuring this. The result can be obtained using 'bootstage report' or > passed on to the Linux via the device tree. > > Signed-off-by: Simon Glass > --- > > common/cmd_scsi.c | 2 ++ > include/bootstage.h | 1 + > 2 files changed, 3 insertions(+) > > diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c > index cbc107e..a0a62eb 100644 > --- a/common/cmd_scsi.c > +++ b/common/cmd_scsi.c > @@ -217,8 +217,10 @@ void scsi_init(void) >(busdevfunc >> 8) & 0x7); > } > #endif > + bootstage_start(BOOTSTAGE_ID_ACCUM_SCSI, "ahci"); > scsi_low_level_init(busdevfunc); > scsi_scan(1); > + bootstage_accum(BOOTSTAGE_ID_ACCUM_SCSI); This does not cover the case if the platform calls scsi_scan at boot. The first time is the important one as that will include disk spin-up time. Perhaps they shouldn't be and "scsi scan" should always be in boot scripts. Rob ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 05/23] usb: pci: Use pci_find_class() to find the device
On Tuesday, January 27, 2015 at 02:23:03 AM, Simon Glass wrote: > Use the new utility function instead of local code. > > Signed-off-by: Simon Glass > --- > > drivers/usb/host/ehci-pci.c | 53 > + 1 file changed, 1 > insertion(+), 52 deletions(-) Nice! Acked-by: Marek Vasut Do you want to pick it through the x86 tree or shall I pick it through USB ? Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 06/23] usb: pci: Add XHCI driver for PCI
On Tuesday, January 27, 2015 at 02:23:04 AM, Simon Glass wrote: > Add a driver which locates the available XHCI controllers on the PCI bus > and makes them available. > > Signed-off-by: Simon Glass Hi! Which xhci controllers did you test with this patch and on which platform please? Is it just the minnow max + the integrated usb 3.0 controller on it? I recall I tried this, but had trouble getting the xhci-pci going on MX6 with a PCIe card with renesas controller. Thanks for working on this ! Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] spl: Change printf to puts for "Unsupported boot-device"
On 01/27/2015 05:02 PM, Tom Rini wrote: > On Tue, Jan 27, 2015 at 04:45:09PM +0100, Stefan Roese wrote: > >> Microblaze currently doesn't use printf in SPL. So this one line was the only >> reference to it and resulted in the printf functionality to be pulled in. >> Exceeding the 4k size limit. Lets change the printf back to puts so that >> Microblaze is fixed again. The only drawback is that the detected boot-device >> number will not be printed. But this message alone should be helpful enough >> to get an idea where the boot process is broken. >> >> Signed-off-by: Stefan Roese >> Cc: Tom Rini >> Cc: Michal Simek > > Since we have a debug() higher up that will print out what the value is, > I'm OK with this and I'll apply shortly, thanks! > Works for me. Acked-by: Michal Simek Thanks, Michal signature.asc Description: OpenPGP digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] sunxi: TZX-Q8-713B7 support
This patch adds support for the TZX-Q8-713B7 tablet as described at: http://linux-sunxi.org/TZX-Q8-713B7 All the things that are expected to work are going just fine, even host USB OTG with the MUSB driver worked with both storage and a USB keyboard. The DRAM configuration was not directly imported from the legacy u-boot-sunxi tree. Instead, this uses dram_sun5i_auto with appropriate configuration. The resulting DRAM config is not exactly the same, but things appear to work just fine with dram_sun5i_auto (when booting a kernel and a full graphical session). The LCD mode configuration (CONFIG_VIDEO_LCD_MODE) only has fields that could be determined reliably. Other fields (such as le,ri,up,lo and hs,vs) are left to default values. Despite this, the LCD appears to be working just fine. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] sunxi: TZX-Q8-713B7 support
Signed-off-by: Paul Kocialkowski --- board/sunxi/Kconfig| 4 board/sunxi/MAINTAINERS| 5 + board/sunxi/Makefile | 1 + configs/TZX-Q8-713B7_defconfig | 15 +++ 4 files changed, 25 insertions(+) create mode 100644 configs/TZX-Q8-713B7_defconfig diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 738b55e..5c78cdf 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -147,6 +147,10 @@ config TARGET_R7DONGLE bool "R7DONGLE" depends on MACH_SUN5I +config TARGET_TZX_Q8_713B7 + bool "TZX-Q8-713B7" + depends on MACH_SUN5I + endchoice config SYS_BOARD diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 743e7f5..da5419c 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -100,3 +100,8 @@ MELE M5 BOARD M: Ian Campbell S: Maintained F: configs/Mele_M5_defconfig + +TZX-Q8-713B7 BOARD +M: Paul Kocialkowski +S: Maintained +F: configs/TZX-Q8-713B7_defconfig diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile index 71edb83..b14a8b2 100644 --- a/board/sunxi/Makefile +++ b/board/sunxi/Makefile @@ -20,3 +20,4 @@ obj-$(CONFIG_TARGET_A13_OLINUXINOM) += dram_a13_oli_micro.o obj-$(CONFIG_TARGET_AUXTEK_T004) += dram_a10s_olinuxino_m.o obj-$(CONFIG_TARGET_MK802_A10S)+= dram_sun5i_auto.o obj-$(CONFIG_TARGET_R7DONGLE) += dram_r7dongle.o +obj-$(CONFIG_TARGET_TZX_Q8_713B7) += dram_sun5i_auto.o diff --git a/configs/TZX-Q8-713B7_defconfig b/configs/TZX-Q8-713B7_defconfig new file mode 100644 index 000..8696bdf --- /dev/null +++ b/configs/TZX-Q8-713B7_defconfig @@ -0,0 +1,15 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER" +CONFIG_USB_MUSB_SUNXI=y +CONFIG_USB0_VBUS_PIN="PG12" +CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:24,pclk_khz:33000,sync:3,vmode:0" +CONFIG_VIDEO_LCD_POWER="AXP0-0" +CONFIG_VIDEO_LCD_BL_EN="AXP0-1" +CONFIG_VIDEO_LCD_BL_PWM="PB2" ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_SUNXI=y ++S:CONFIG_MACH_SUN5I=y ++S:CONFIG_TARGET_TZX_Q8_713B7=y ++S:CONFIG_DRAM_CLK=408 ++S:CONFIG_DRAM_ZQ=123 ++S:CONFIG_DRAM_EMR1=4 -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RFC PATCH] ARM: Activate hypervisor mode for TI am5726 (OMAP5/dra7)
Hi, I was wondering if I could have any input on the patch below activating hypervisor mode on TI OMAP5-based SoC. The patch essentially uses the on-chip ROM code API to enable hypervisor mode on the primary A15 core and goes in tandem with a Linux kernel patch recently accepted into omap-for-v3.19/fixes that checks hypervisor mode on the primary A15 core and sets it accordingly on additional cores being activated. I am aware that there is some development going on for ARM's PSCI that amongst other things is supposed to deal with hypervisor activation in a more generic fashion and I am wondering if there is any preference on how to properly activate hypervisor mode for the TI SoCs mentioned above. Thanks, Frank --- u-boot patch: Enable hypervisor mode for AM5726 --- arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 13 + 1 file changed, 13 insertions(+) diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S index 86c0e42..696da4b 100644 --- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S @@ -19,7 +19,20 @@ ENTRY(save_boot_params) ldr r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS str r0, [r1] +/* + * Turn on hypervisor mode on CPU#0 + */ +#ifdef CONFIG_DRA7XX_HYPERVISOR_ON + mov r0, lr @ This is a great place to switch into hyp mode + @ only the r0 was needed from _start and is now + @ free; all other general purpose registers were + @ already free. + ldr r12, =0x102 @ Set PL310 control register - value in R0 + .word 0xe1600070 @ SMC #0 - hand assembled because -march=armv5 + @ call ROM Code API to set control register +#else bx lr +#endif /* CONFIG_DRA7XX_HYPERVISOR_ON */ ENDPROC(save_boot_params) ENTRY(set_pl310_ctrl_reg) --- Link to the corresponding Linux kernel patch: http://linux-kernel.2935.n7.nabble.com/PATCH-ARM-omap5-dra7xx-Enable-booting-secondary-CPU-in-HYP-mode-td1009407.html#a1014616 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC PATCH] ARM: Activate hypervisor mode for TI am5726 (OMAP5/dra7)
On Tue, Jan 27, 2015 at 01:56:12PM -0500, Frank Bormann wrote: > Hi, > > I was wondering if I could have any input on the patch below activating > hypervisor mode on TI OMAP5-based SoC. The patch essentially uses the > on-chip ROM code API to enable hypervisor mode on the primary A15 core > and goes in tandem with a Linux kernel patch recently accepted into > omap-for-v3.19/fixes that checks hypervisor mode on the primary A15 core > and sets it accordingly on additional cores being activated. > > I am aware that there is some development going on for ARM's PSCI that > amongst other things is supposed to deal with hypervisor activation in a > more generic fashion and I am wondering if there is any preference on > how to properly activate hypervisor mode for the TI SoCs mentioned above. > > Thanks, > Frank > > --- > > u-boot patch: > > Enable hypervisor mode for AM5726 Well it actually applies to AM57xx and OMAP54xx as far as I can tell. The DRA7XX (AM57xx) borrowed that part of the romcode from the OMAP5 as far as I know. Perhaps DRA7XX in the name should be something that applies to both TI Cortex-A15 designs. I don't know what the Keystone models do. > --- > arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 13 + > 1 file changed, 13 insertions(+) > > diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S > b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S > index 86c0e42..696da4b 100644 > --- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S > +++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S > @@ -19,7 +19,20 @@ > ENTRY(save_boot_params) > ldr r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS > str r0, [r1] > +/* > + * Turn on hypervisor mode on CPU#0 > + */ > +#ifdef CONFIG_DRA7XX_HYPERVISOR_ON > + mov r0, lr @ This is a great place to switch into hyp mode > + @ only the r0 was needed from _start and is now > + @ free; all other general purpose registers were > + @ already free. > + ldr r12, =0x102 @ Set PL310 control register - value in R0 > + .word 0xe1600070 @ SMC #0 - hand assembled because -march=armv5 > + @ call ROM Code API to set control register > +#else > bx lr > +#endif /* CONFIG_DRA7XX_HYPERVISOR_ON */ > ENDPROC(save_boot_params) > ENTRY(set_pl310_ctrl_reg) > > --- > > Link to the corresponding Linux kernel patch: > > http://linux-kernel.2935.n7.nabble.com/PATCH-ARM-omap5-dra7xx-Enable-booting-secondary-CPU-in-HYP-mode-td1009407.html#a1014616 -- Len Sorensen ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] net: configure DWMAC DMA by default AXI burst length
On Mon, Jan 26, 2015 at 8:54 PM, wrote:
>
> From: Sonic Zhang
>
> Board can define its own AXI burst length to improve DWMAC DMA
performance.
>
> Signed-off-by: Sonic Zhang
> ---
>
> drivers/net/designware.c |2 ++
> drivers/net/designware.h |5 +
> 2 files changed, 7 insertions(+)
>
> diff --git a/drivers/net/designware.c b/drivers/net/designware.c
> index 9ded895..d8d6792 100644
> --- a/drivers/net/designware.c
> +++ b/drivers/net/designware.c
> @@ -256,6 +256,8 @@ static int dw_eth_init(struct eth_device *dev, bd_t
*bis)
>
> writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode);
>
This should probably include:
+#if CONFIG_DW_AXI_BURST_LEN
so that this register is only accessed if configured.
> + writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus);
> +
> /* Start up the PHY */
> if (phy_startup(priv->phydev)) {
> printf("Could not initialize PHY %s\n",
> diff --git a/drivers/net/designware.h b/drivers/net/designware.h
> index ce51102..d8bd84d 100644
> --- a/drivers/net/designware.h
> +++ b/drivers/net/designware.h
> @@ -102,6 +102,11 @@ struct eth_dma_regs {
> #define TXSECONDFRAME (1 << 2)
> #define RXSTART(1 << 1)
>
> +/* Default AXI BUS Burst length */
> +#ifndef CONFIG_DW_AXI_BURST_LEN
> +#define CONFIG_DW_AXI_BURST_LEN 0
> +#endif
> +
> /* Descriptior related definitions */
> #define MAC_MAX_FRAME_SZ (1600)
>
> --
> 1.7.9.5
>
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Re: [U-Boot] [PATCH 06/23] usb: pci: Add XHCI driver for PCI
Hi Marek, On 27 January 2015 at 10:57, Marek Vasut wrote: > On Tuesday, January 27, 2015 at 02:23:04 AM, Simon Glass wrote: >> Add a driver which locates the available XHCI controllers on the PCI bus >> and makes them available. >> >> Signed-off-by: Simon Glass > > Hi! > > Which xhci controllers did you test with this patch and on which platform > please? Is it just the minnow max + the integrated usb 3.0 controller on > it? I recall I tried this, but had trouble getting the xhci-pci going on > MX6 with a PCIe card with renesas controller. > > Thanks for working on this ! I tested it on an Intel controller (MinnowMax board). As mentioned in the cover letter it doesn't actually work, but I suspect that could be an XHCI stack issue. Not 100% sure though. At least this is a starting point. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 05/23] usb: pci: Use pci_find_class() to find the device
Hi Marek, On 27 January 2015 at 10:50, Marek Vasut wrote: > On Tuesday, January 27, 2015 at 02:23:03 AM, Simon Glass wrote: >> Use the new utility function instead of local code. >> >> Signed-off-by: Simon Glass >> --- >> >> drivers/usb/host/ehci-pci.c | 53 >> + 1 file changed, 1 >> insertion(+), 52 deletions(-) > > Nice! > > Acked-by: Marek Vasut > > Do you want to pick it through the x86 tree or shall I pick it through USB ? > I think x86 is better since it is part of a series. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 05/23] usb: pci: Use pci_find_class() to find the device
On Tuesday, January 27, 2015 at 09:53:01 PM, Simon Glass wrote: > Hi Marek, Hi Simon, > On 27 January 2015 at 10:50, Marek Vasut wrote: > > On Tuesday, January 27, 2015 at 02:23:03 AM, Simon Glass wrote: > >> Use the new utility function instead of local code. > >> > >> Signed-off-by: Simon Glass > >> --- > >> > >> drivers/usb/host/ehci-pci.c | 53 > >> > >> + 1 file changed, 1 > >> insertion(+), 52 deletions(-) > > > > Nice! > > > > Acked-by: Marek Vasut > > > > Do you want to pick it through the x86 tree or shall I pick it through > > USB ? > > I think x86 is better since it is part of a series. I agree, thanks! Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 06/23] usb: pci: Add XHCI driver for PCI
On Tuesday, January 27, 2015 at 09:52:14 PM, Simon Glass wrote: > Hi Marek, Hi! > On 27 January 2015 at 10:57, Marek Vasut wrote: > > On Tuesday, January 27, 2015 at 02:23:04 AM, Simon Glass wrote: > >> Add a driver which locates the available XHCI controllers on the PCI bus > >> and makes them available. > >> > >> Signed-off-by: Simon Glass > > > > Hi! > > > > Which xhci controllers did you test with this patch and on which platform > > please? Is it just the minnow max + the integrated usb 3.0 controller on > > it? I recall I tried this, but had trouble getting the xhci-pci going on > > MX6 with a PCIe card with renesas controller. > > > > Thanks for working on this ! > > I tested it on an Intel controller (MinnowMax board). As mentioned in > the cover letter it doesn't actually work, but I suspect that could be > an XHCI stack issue. Not 100% sure though. At least this is a starting > point. Ah, I must have missed that, sorry. Good luck with this USB3 stuff! Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/4] usb: add 'bcm_udc_otg' support
On Monday, January 26, 2015 at 06:44:14 PM, Steve Rae wrote: [...] > > No, unless there's a convincing technical argument that the currently > > mainline DWC2 gadget driver (the s3c one) can absolutelly not be used > > for the broadcom SoC, I want to avoid having two drivers for the same > > IP core in mainline, sorry. > > > > [...] > > > > Sorry, at this point I have to push back a little. > > OK -- Thanks for this information Hi! do you plan to rework the series on top of the dwc2 (s3c) driver by any chance please ? Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] mtd:mxs:nand calculate ecc strength dynamically
On Fr, 2014-12-19 at 12:39 +0800, Peng Fan wrote:
> Calculate ecc strength according oobsize, but not hardcoded
> which is not aligned with kernel driver
>
> Signed-off-by: Peng Fan
> Signed-off-by: Ye.Li
> ---
> drivers/mtd/nand/mxs_nand.c | 22 --
> 1 file changed, 4 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c
> index 7a064ab..a45fcf9 100644
> --- a/drivers/mtd/nand/mxs_nand.c
> +++ b/drivers/mtd/nand/mxs_nand.c
> @@ -146,26 +146,12 @@ static uint32_t mxs_nand_aux_status_offset(void)
> static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size,
> uint32_t page_oob_size)
> {
> - if (page_data_size == 2048) {
> - if (page_oob_size == 64)
> - return 8;
> + int ecc_strength;
>
> - if (page_oob_size == 112)
> - return 14;
> - }
> -
> - if (page_data_size == 4096) {
> - if (page_oob_size == 128)
> - return 8;
> -
> - if (page_oob_size == 218)
> - return 16;
> + ecc_strength = ((page_oob_size - MXS_NAND_METADATA_SIZE) * 8)
> + / (13 * mxs_nand_ecc_chunk_cnt(page_data_size));
>
> - if (page_oob_size == 224)
> - return 16;
> - }
> -
> - return 0;
> + return round_down(ecc_strength, 2);
> }
>
> static inline uint32_t mxs_nand_get_mark_offset(uint32_t page_data_size,
Many thanks for the patch! But this patch affects mxsboot which is no
not aligned with the U-Boot mxs nand driver.
I was able to fix mxsboot, but I had difficulties with round_down, which
is a macro definition in linux/kernel.h. I've copied the macro
definition to mxsboot. I will submit the patch in a seperate mail.
I would like to see a comment or a macro for the magic number 13, which
is the value for the Galois Field, just for clarification
With fixing mxsboot, I was able to test the patch on a custom
i.MX28-based board assembled with a 1Gbit NAND flash (page size = 2048
bytes, oob size = 128 bytes).
U-Boot correctly reads the NAND info
=> nand info
Device 0: nand0, sector size 128 KiB
Page size 2048 b
OOB size128 b
Erase size 131072 b
Before the patch linux failed to read from the UBI device with an ECC
error:
UBI error: ubi_io_read: error -74 (ECC error)
This patch resolves the error. Linux can read the UBI device now. This
is kernel message:
nand: device found, Manufacturer ID: 0x98, Chip ID: 0xf1
[1.327810] nand: Toshiba NAND 128MiB 3,3V 8-bit
[1.332482] nand: 128MiB, SLC, page size: 2048, OOB size: 128
BCH Geometry :
[1.594658] GF length : 13
[1.594658] ECC Strength : 18
[1.594658] Page Size in Bytes : 2176
[1.594658] Metadata Size in Bytes : 10
[1.594658] ECC Chunk Size in Bytes: 512
[1.594658] ECC Chunk Count: 4
[1.594658] Payload Size in Bytes : 2048
[1.594658] Auxiliary Size in Bytes: 16
[1.594658] Auxiliary Status Offset: 12
[1.594658] Block Mark Byte Offset : 1950
[1.594658] Block Mark Bit Offset : 2
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[U-Boot] checkstack.pl
Masahiro, Do you mind to add aarch64 support for checkstack.pl? $ make checkstack /opt/linaro/gcc-linaro-aarch64-linux-gnu-4.8-2013.12_linux/bin/aarch64-linux-gnu-objdump -d u-boot $(find . -name u-boot-spl) | \ perl ./scripts/checkstack.pl aarch64 wrong or unknown architecture "aarch64" York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] RFC: dm: Kconfig: Move all driver model CONFIGs to Kconfig
On Tue, Dec 9, 2014 at 7:21 AM, Simon Glass wrote: > > Kconfig has been available for a while but there are still driver model > CONFIG options. Move all of these to Kconfig. > > This patch isn't final - I need to wait until the SPL series can be fully > applied, which is in turn waiting on some ARM SPL problems. So for now it > is just a placeholder. But it needs to be sent out otherwise we will never > move over. > > Signed-off-by: Simon Glass > --- > diff --git a/common/Kconfig b/common/Kconfig > index fd84fa0..174bf4f 100644 > --- a/common/Kconfig > +++ b/common/Kconfig > @@ -153,6 +153,29 @@ endmenu > > menu "Device access commands" > > +config CMD_DM > + bool "dm - Access to driver model information" > + depends on DM > + default y > + help > + Provides access to driver model data structures and information, > + such as a list of devices, list of uclasses and the state of each > + device (e.g. activated). This is not required for operation, but > + can be useful to see the state of driver model for debugging or > + interest. > + > +config CMD_DEMO > + bool "demo - Demonstration commands for driver model" > + depends on DM > + help > + Procides a 'demo' command which can be used to play around with Provides > + driver model. To use this properly you will need to enable one or > + both of the demo devices (DM_DEMO_SHAPE and DM_DEMO_SIMPLE). > + Otherwise you will always get an empty list of devices. The demo > + devices are defined in the sandbox device tree, so the easiest > + option is to use sandbox and pass the -d point to sandbox's > + u-boot.dtb file. > + > config CMD_LOADB > bool "loadb" > help ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/5] nand: Use common read function instead of verify_buf()
Hi Scott, > > I waffled about removing it, but leaned towards leaving it in because: > > - I didn't want to change the existing U-Boot behavior for other > > users. A google of 'u-boot "nand write"' shows a lot of examples that > > don't include verification of writes, and they should if we remove > > auto-verification. > > How many configs actually enable this option? I don't see many beyond > the FSL PPC boards (which are so full of copy-and-paste that it probably > wasn't deliberate). Yeah, the majority are FSL 83xx and 85xx, with 2 or so random ARM boards. > > - The reason it was removed in Linux was "Both UBI and JFFS2 are able > > to read verify what they wrote already. There are also MTD tests > > which do this verification." I thought U-Boot was more likely than > > Linux to use raw NAND writes without a filesystem, so leaving it in U- > > Boot made sense since the UBI/JFFS2 logic didn't apply as much here. > > Right, though raw writes ought to be limited to blocks that aren't > written often enough to fail. > > > - I didn't think a lot of people would know they have to explicitly > > verify NAND contents after a write, since they'd assume it was like > > other memories that aren't as lossy. > > > > - The penalty of slightly different code from Linux and a small > > performance hit was worth the gain of auto-verification to me. I > > viewed consolidating it into one small chunk of code as a happy medium. > > The davinci patches show that there can still be driver dependencies > depending on what the driver overrides. I'm not hugely opposed, but it > seems like it would be better to do it at a higher level (e.g. in > nand_util.c with a flag to enable, and either make support mandatory, or > if you try to use that command variant without support it fails rather > than silently not verifying). That seems like a good idea. How about: - Remove all CONFIG_MTD_NAND_VERIFY_WRITE references - Add a new flag WITH_WR_VERIFY and have nand_write_skip_bad() in nand_util.c verify writes only when it is set. - Update the calls to nand_write_skip_bad() in cmd_nand.c to include the new WITH_WR_VERIFY flag. I'd vote to enable it for all boards, but let me know if you disagree. That would make all "nand write" commands verify writes, with the exception of "nand write.raw". Any opinion on if this should also be verified? I only use it for development/testing, so don't have a strong opinion. Regards, Peter ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
