[U-Boot] [PATCH] cfi_flash: don't hide write/erase errors

[Baruch Siach]

Partially revert commit 0d01f66d235118 (CFI: cfi_flash write fix for AMD
legacy).

flash_full_status_check() used to skip status register parsing when
flash_status_check() returns OK. This is wrong since flash_status_check()
must return OK for other status bits to be valid.

Cc: Ed Swarthout 
Signed-off-by: Baruch Siach 
---
 drivers/mtd/cfi_flash.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index c4b5bc1de553..9b3175d87fbd 100644
--- a/drivers/mtd/cfi_flash.c
+++ b/drivers/mtd/cfi_flash.c
@@ -593,7 +593,7 @@ static int flash_full_status_check (flash_info_t * info, 
flash_sect_t sector,
case CFI_CMDSET_INTEL_PROG_REGIONS:
case CFI_CMDSET_INTEL_EXTENDED:
case CFI_CMDSET_INTEL_STANDARD:
-   if ((retcode != ERR_OK)
+   if ((retcode == ERR_OK)
&& !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) {
retcode = ERR_INVAL;
printf ("Flash %s error at address %lx\n", prompt,
-- 
2.1.0

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[U-Boot] [PATCH] dfu, usb: set usb descriptor to values defined in dfu spec 1.1

[Heiko Schocher]

set bDeviceClass, bDeviceSubClass and bcdUSB to the values
defined in dfu spec 1.1 chapter 4.2.1 found here:

http://www.usb.org/developers/devclass_docs/DFU_1.1.pdf

Signed-off-by: Heiko Schocher 
Cc: Lukasz Majewski 
Cc: Marek Vasut 
Cc: Roger Meier 

---

before this patch, "dfu-util -l" showed:

Bus 002 Device 114: ID 0908:02c5 Siemens AG
Device Descriptor:
  bLength18
  bDescriptorType 1
  bcdUSB   2.00
  bDeviceClass2 Communications
  bDeviceSubClass 2 Abstract (modem)
  bDeviceProtocol 0 None
  bMaxPacketSize064
  idVendor   0x0908 Siemens AG
  idProduct  0x02c5
  bcdDevice0.00
  iManufacturer   1 Siemens AG

with this patch:

Bus 002 Device 089: ID 0908:02c5 Siemens AG
Device Descriptor:
  bLength18
  bDescriptorType 1
  bcdUSB   1.10
  bDeviceClass0 (Defined at Interface level)
  bDeviceSubClass 0
  bDeviceProtocol 0
  bMaxPacketSize064
  idVendor   0x0908 Siemens AG
  idProduct  0x02c5
  bcdDevice0.00
  iManufacturer   1 Siemens AG
  iProduct2 USB download gadget

which fits for "bcdUSB", "bDeviceClass" and "bDeviceSubClass" with
the DFU spezifikation.
---
 drivers/usb/gadget/f_dfu.c | 5 +++--
 drivers/usb/gadget/g_dnl.c | 6 +++---
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/usb/gadget/f_dfu.c b/drivers/usb/gadget/f_dfu.c
index 9128add..9429e50 100644
--- a/drivers/usb/gadget/f_dfu.c
+++ b/drivers/usb/gadget/f_dfu.c
@@ -83,8 +83,9 @@ static struct usb_descriptor_header *dfu_runtime_descs[] = {
 static const struct usb_qualifier_descriptor dev_qualifier = {
.bLength =  sizeof dev_qualifier,
.bDescriptorType =  USB_DT_DEVICE_QUALIFIER,
-   .bcdUSB =   __constant_cpu_to_le16(0x0200),
-   .bDeviceClass = USB_CLASS_VENDOR_SPEC,
+   .bcdUSB =   __constant_cpu_to_le16(0x0110),
+   .bDeviceClass = USB_CLASS_PER_INTERFACE,
+   .bDeviceSubClass =  0x00,
.bNumConfigurations =   1,
 };
 
diff --git a/drivers/usb/gadget/g_dnl.c b/drivers/usb/gadget/g_dnl.c
index dd95afe..bcca965 100644
--- a/drivers/usb/gadget/g_dnl.c
+++ b/drivers/usb/gadget/g_dnl.c
@@ -57,9 +57,9 @@ static struct usb_device_descriptor device_desc = {
.bLength = sizeof device_desc,
.bDescriptorType = USB_DT_DEVICE,
 
-   .bcdUSB = __constant_cpu_to_le16(0x0200),
-   .bDeviceClass = USB_CLASS_COMM,
-   .bDeviceSubClass = 0x02, /*0x02:CDC-modem , 0x00:CDC-serial*/
+   .bcdUSB = __constant_cpu_to_le16(0x0110),
+   .bDeviceClass = USB_CLASS_PER_INTERFACE,
+   .bDeviceSubClass = 0x00, /*0x02:CDC-modem , 0x00:CDC-serial*/
 
.idVendor = __constant_cpu_to_le16(CONFIG_G_DNL_VENDOR_NUM),
.idProduct = __constant_cpu_to_le16(CONFIG_G_DNL_PRODUCT_NUM),
-- 
1.8.3.1

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[U-Boot] [PATCH] B4860QDS: Enable mac command support

[Shaveta Leekha]

One of the I2C EEPROM is used to store/save and edit mac
addresses of ports.
this patch add required CONFIG to support the same

Signed-off-by: Shaveta Leekha 
---
 include/configs/B4860QDS.h |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index 6deb784..9063c57 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -227,6 +227,7 @@ unsigned long get_board_ddr_clk(void);
 #endif
 
 /* EEPROM */
+#define CONFIG_ID_EEPROM
 #define CONFIG_SYS_I2C_EEPROM_NXID
 #define CONFIG_SYS_EEPROM_BUS_NUM  0
 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-- 
1.7.6.GIT

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[U-Boot] VxWorks Booting using U-boot as Bootloader

[Ashish Khetan]

Hi,
I was trying to boot vxworks using u-boot bootloader for learning purpose
on MPC8640DHPCN board. Previously I successfully ported QNX os along with
linux on same board using u-boot. while booting using bootvx command its
not booting and stucking after showing the following message:

tftp 0100 vxWorks
Speed: 1000, full duplex
Using eTSEC1 device
TFTP from server 192.168.10.2; our IP address is 192.168.10.4
Filename 'vxWorks'.
Load address: 0x100
Loading: *#
 #
 #
 12.3 MiB/s
done
Bytes transferred = 2392432 (248170 hex)
BOSSv2.0=> bootvx 0010   100
## Ethernet MAC address not copied to NV RAM
## Using bootline (@ 0x4200): root=/dev/nfs rw
nfsroot=192.168.10.2:/opt/eldk-5.3/powerpc/rootfs-basic
ip=192.168.10.4:192.168.10.2:192.168.10.1:255.255.255.0:Boss:eth0:off
panic=1 console=ttyS0,115200
## Starting vxWorks at 0x0010 ...


please somebody provide me some link or any pointer to help me get more
understanding about booting multiple os using uboot.
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Re: [U-Boot] [PATCH v3 0/4] introduce get_maintainer.pl

[Masahiro YAMADA]

Hi.



2014-09-04 15:05 GMT+09:00 Stefan Roese :
>>
>> Patman now picks this up which is great. But it does sometimes produce
>> a long list of maintainers. I wonder if we could have an option to
>> turn it off (perhaps -m)?
>
>
> Yes, that would be good. I just recently got a very long Cc list in my quite
> bit patchset. This definitely was too much and I had to send those patches
> manually instead of using patman. We need an option to disable this.
>

Me too.
I sometimes delete get_maintainer.pl before I use patman
to avoid a big Cc list.

$ rm scripts/get_maintainer.pl
$ tools/patman/patman  ...
$ git checkout scripts/get_maintainer.pl


I agree with '-m' option.


-- 
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Masahiro Yamada
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Re: [U-Boot] [PATCH v2 2/4] kconfig: fix whitespace handling bug of savedefconfig

[Masahiro YAMADA]

Hi Simon,

2014-09-04 8:49 GMT+09:00 Simon Glass :
> Hi Masahiro,
>
> On 3 September 2014 14:41, Masahiro Yamada  wrote:
>> Commit 3ff291f371fa9858426774f3732924bacb61ed1c
>> (kconfig: convert Kconfig helper script into a shell script)
>> introduced another regression.
>>
>> Shell usually handles whitespaces as separators,
>> so "make saveconfig" outputs
>>
>>   # CONFIG_FOO is not set
>>
>> into:
>>
>>   #
>>   CONFIG_FOO
>>   is
>>   not
>>   set
>>
>> Whitespaces should not be treated as separators here.
>
> Oh dear...python is so much better at dealing with parameters and strings.
>

Shell script is much more difficult than Python (and Perl)
for text processing.

This is really unfortunate...


-- 
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[U-Boot] [PATCH v2] kconfig: show an error message when defconfig is not found

[Masahiro Yamada]

When a non-existing defconfig is specified,
display an easy-to-understand message
(fake the error message on Linux Kernel):

  $ make foo_defconfig
  ***
  *** Can't find default configuration "confis/foo_defconfig"!
  ***

Signed-off-by: Masahiro Yamada 
---

Changes in v2:
  - Echo the error message to stderr

 scripts/multiconfig.sh | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/scripts/multiconfig.sh b/scripts/multiconfig.sh
index a579042..49fcfad 100644
--- a/scripts/multiconfig.sh
+++ b/scripts/multiconfig.sh
@@ -118,6 +118,13 @@ do_board_defconfig () {
defconfig_path=$srctree/configs/$1
tmp_defconfig_path=configs/.tmp_defconfig
 
+   if [ ! -r $defconfig_path ]; then
+   echo >&2 "***"
+   echo >&2 "*** Can't find default configuration \"confis/$1\"!"
+   echo >&2 "***"
+   exit 1
+   fi
+
mkdir -p arch configs
# defconfig for Normal:
#  pick lines without prefixes and lines starting '+' prefix
-- 
1.9.1

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Re: [U-Boot] [U-boot] [Patch 2/6] ARM: keystone2: clock: add K2E clock support

[Murali Karicheri]

On 07/15/2014 05:59 PM, Ivan Khoronzhuk wrote:

From: Hao Zhang

This patch adds clock definitions and commands to support Keystone2
K2E SOC.

Signed-off-by: Hao Zhang
Signed-off-by: Ivan Khoronzhuk
---
  arch/arm/cpu/armv7/keystone/Makefile   |   1 +
  arch/arm/cpu/armv7/keystone/clock-k2e.c| 101 +
  arch/arm/cpu/armv7/keystone/clock.c|   2 +
  arch/arm/cpu/armv7/keystone/cmd_clock.c|  31 ++--
  arch/arm/include/asm/arch-keystone/clock-k2e.h |  68 +
  arch/arm/include/asm/arch-keystone/clock.h |   4 +
  include/configs/ks2_evm.h  |   2 +-
  7 files changed, 203 insertions(+), 6 deletions(-)
  create mode 100644 arch/arm/cpu/armv7/keystone/clock-k2e.c
  create mode 100644 arch/arm/include/asm/arch-keystone/clock-k2e.h

diff --git a/arch/arm/cpu/armv7/keystone/Makefile 
b/arch/arm/cpu/armv7/keystone/Makefile
index 74c5160..f8519c0 100644
--- a/arch/arm/cpu/armv7/keystone/Makefile
+++ b/arch/arm/cpu/armv7/keystone/Makefile
@@ -9,6 +9,7 @@ obj-y   += init.o
  obj-y += psc.o
  obj-y += clock.o
  obj-$(CONFIG_SOC_K2HK) += clock-k2hk.o
+obj-$(CONFIG_SOC_K2E) += clock-k2e.o
  obj-y += cmd_clock.o
  obj-y += cmd_mon.o
  obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_nav.o
diff --git a/arch/arm/cpu/armv7/keystone/clock-k2e.c 
b/arch/arm/cpu/armv7/keystone/clock-k2e.c
new file mode 100644
index 000..42092e1
--- /dev/null
+++ b/arch/arm/cpu/armv7/keystone/clock-k2e.c
@@ -0,0 +1,101 @@
+/*
+ * Keystone2: get clk rate for K2E
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated,
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include
+#include
+#include
+
+const struct keystone_pll_regs keystone_pll_regs[] = {
+   [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
+   [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
+   [DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
+};
+
+/**
+ * pll_freq_get - get pll frequency
+ * Fout = Fref * NF(mult) / NR(prediv) / OD
+ * @pll:   pll identifier
+ */
+static unsigned long pll_freq_get(int pll)
+{
+   unsigned long mult = 1, prediv = 1, output_div = 2;
+   unsigned long ret;
+   u32 tmp, reg;
+
+   if (pll == CORE_PLL) {
+   ret = external_clk[sys_clk];
+   if (pllctl_reg_read(pll, ctl)&  PLLCTL_PLLEN) {
+   /* PLL mode */
+   tmp = __raw_readl(KS2_MAINPLLCTL0);
+   prediv = (tmp&  PLL_DIV_MASK) + 1;
+   mult = (((tmp&  PLLM_MULT_HI_SMASK)>>  6) |
+   (pllctl_reg_read(pll, mult)&
+   PLLM_MULT_LO_MASK)) + 1;
+   output_div = ((pllctl_reg_read(pll, secctl)>>
+  PLL_CLKOD_SHIFT)&  PLL_CLKOD_MASK) + 1;
+
+   ret = ret / prediv / output_div * mult;
+   }
+   } else {
+   switch (pll) {
+   case PASS_PLL:
+   ret = external_clk[pa_clk];
+   reg = KS2_PASSPLLCTL0;
+   break;
+   case DDR3_PLL:
+   ret = external_clk[ddr3_clk];
+   reg = KS2_DDR3APLLCTL0;
+   break;
+   default:
+   return 0;
+   }
+
+   tmp = __raw_readl(reg);
+
Please remove this line as below is part of this and should be in a 
block IMO. With this change,


Acked-by: Murali Karicheri 


+   if (!(tmp&  PLLCTL_BYPASS)) {
+   /* Bypass disabled */
+   prediv = (tmp&  PLL_DIV_MASK) + 1;
+   mult = ((tmp>>  PLL_MULT_SHIFT)&  PLL_MULT_MASK) + 1;
+   output_div = ((tmp>>  PLL_CLKOD_SHIFT)&
+ PLL_CLKOD_MASK) + 1;
+   ret = ((ret / prediv) * mult) / output_div;
+   }
+   }
+
+   return ret;
+}
+
+unsigned long clk_get_rate(unsigned int clk)
+{
+   switch (clk) {
+   case core_pll_clk:  return pll_freq_get(CORE_PLL);
+   case pass_pll_clk:  return pll_freq_get(PASS_PLL);
+   case ddr3_pll_clk:  return pll_freq_get(DDR3_PLL);
+   case sys_clk0_1_clk:
+   case sys_clk0_clk:  return pll_freq_get(CORE_PLL) / pll0div_read(1);
+   case sys_clk1_clk:  return pll_freq_get(CORE_PLL) / pll0div_read(2);
+   case sys_clk2_clk:  return pll_freq_get(CORE_PLL) / pll0div_read(3);
+   case sys_clk3_clk:  return pll_freq_get(CORE_PLL) / pll0div_read(4);
+   case sys_clk0_2_clk:return clk_get_rate(sys_clk0_clk) / 2;
+   case sys_clk0_3_clk:return clk_get_rate(sys_clk0_clk) / 3;
+   case sys_clk0_4_clk:return clk_get_rate(sys_clk0_clk) / 4;
+   case sys_clk0_6_clk:return clk_get_rate(sys_clk0_clk) / 6;
+   case sys_clk0_8_clk:return clk_get_rate(sys_clk0_clk

[U-Boot] [PATCH v2 3/5] iMX6DL:arm2: Add support for i.MX6DL arm2 DDR3 board

[Ye . Li]

This patch adds the i.MX6DL arm2 board support. The i.MX6DL ARM2
shared the same board with i.MX6Q ARM2 board since the i.MX6DL is
pin-pin compatible with i.MX6Q.

The patch also support the DDR 32-BIT mode option. Please define
CONFIG_DDR_32BIT in the board configure file to enable DDR 32-BIT
mode.But due to the board design, it's 64bit DDR buswidth physically,
so, if you CONFIG_DDR_32BIT, the DDR memory size will be half of it.

Signed-off-by: Ye.Li 
---
Changes since v1:
- None

 board/freescale/mx6qarm2/imximage_mx6dl.cfg |  143 +++
 board/freescale/mx6qarm2/mx6qarm2.c |4 +
 configs/mx6dlarm2_defconfig |3 +
 configs/mx6qarm2_defconfig  |2 +-
 include/configs/mx6qarm2.h  |5 +-
 5 files changed, 155 insertions(+), 2 deletions(-)
 create mode 100644 board/freescale/mx6qarm2/imximage_mx6dl.cfg
 create mode 100644 configs/mx6dlarm2_defconfig

diff --git a/board/freescale/mx6qarm2/imximage_mx6dl.cfg 
b/board/freescale/mx6qarm2/imximage_mx6dl.cfg
new file mode 100644
index 000..eef723c
--- /dev/null
+++ b/board/freescale/mx6qarm2/imximage_mx6dl.cfg
@@ -0,0 +1,143 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ * Jason Liu 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM  sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type   AddressValue
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address   absolute address of the register
+ * value value to be stored in the register
+ */
+DATA 4 0x020e0798 0x000c
+DATA 4 0x020e0758 0x
+DATA 4 0x020e0588 0x0030
+DATA 4 0x020e0594 0x0030
+DATA 4 0x020e056c 0x0030
+DATA 4 0x020e0578 0x0030
+DATA 4 0x020e074c 0x0030
+DATA 4 0x020e057c 0x0030
+DATA 4 0x020e0590 0x3000
+DATA 4 0x020e0598 0x3000
+DATA 4 0x020e058c 0x
+DATA 4 0x020e059c 0x3030
+DATA 4 0x020e05a0 0x3030
+DATA 4 0x020e078c 0x0030
+DATA 4 0x020e0750 0x0002
+DATA 4 0x020e05a8 0x0030
+DATA 4 0x020e05b0 0x0030
+DATA 4 0x020e0524 0x0030
+DATA 4 0x020e051c 0x0030
+DATA 4 0x020e0518 0x0030
+DATA 4 0x020e050c 0x0030
+DATA 4 0x020e05b8 0x0030
+DATA 4 0x020e05c0 0x0030
+DATA 4 0x020e0774 0x0002
+DATA 4 0x020e0784 0x0030
+DATA 4 0x020e0788 0x0030
+DATA 4 0x020e0794 0x0030
+DATA 4 0x020e079c 0x0030
+DATA 4 0x020e07a0 0x0030
+DATA 4 0x020e07a4 0x0030
+DATA 4 0x020e07a8 0x0030
+DATA 4 0x020e0748 0x0030
+DATA 4 0x020e05ac 0x0030
+DATA 4 0x020e05b4 0x0030
+DATA 4 0x020e0528 0x0030
+DATA 4 0x020e0520 0x0030
+DATA 4 0x020e0514 0x0030
+DATA 4 0x020e0510 0x0030
+DATA 4 0x020e05bc 0x0030
+DATA 4 0x020e05c4 0x0030
+
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b4800 0xa1390003
+DATA 4 0x021b080c 0x001F001F
+DATA 4 0x021b0810 0x001F001F
+DATA 4 0x021b480c 0x00370037
+DATA 4 0x021b4810 0x00370037
+DATA 4 0x021b083c 0x422f0220
+DATA 4 0x021b0840 0x021f0219
+DATA 4 0x021b483C 0x422f0220
+DATA 4 0x021b4840 0x022d022f
+DATA 4 0x021b0848 0x47494b49
+DATA 4 0x021b4848 0x48484c47
+DATA 4 0x021b0850 0x39382b2f
+DATA 4 0x021b4850 0x2f35312c
+DATA 4 0x021b081c 0x
+DATA 4 0x021b0820 0x
+DATA 4 0x021b0824 0x
+DATA 4 0x021b0828 0x
+DATA 4 0x021b481c 0x
+DATA 4 0x021b4820 0x
+DATA 4 0x021b4824 0x
+DATA 4 0x021b4828 0x
+DATA 4 0x021b08b8 0x0800
+DATA 4 0x021b48b8 0x0800
+DATA 4 0x021b0004 0x0002002d
+DATA 4 0x021b0008 0x00333030
+
+DATA 4 0x021b000c 0x40445323
+DATA 4 0x021b0010 0xb66e8c63
+
+DATA 4 0x021b0014 0x01ff00db
+DATA 4 0x021b0018 0x00081740
+DATA 4 0x021b001c 0x8000
+DATA 4 0x021b002c 0x26d2
+DATA 4 0x021b0030 0x00440e21
+#ifdef CONFIG_DDR_32BIT
+DATA 4 0x021b0040 0x0017
+DATA 4 0x021b 0xc319
+#else
+DATA 4 0x021b0040 0x0027
+DATA 4 0x021b 0xc31a
+#endif
+DATA 4 0x021b001c 0x04008032
+DATA 4 0x021b001c 0x0400803a
+DATA 4 0x021b001c 0x8033
+DATA 4 0x021b001c 0x803b
+DATA 4 0x021b001c 0x00428031
+DATA 4 0x021b001c 0x00428039
+DATA 4 0x021b001c 0x07208030
+DATA 4 0x021b001c 0x07208038
+DATA 4 0x021b001c 0x04008040
+DATA 4 0x021b001c 0x04008048
+DATA 4 0x021b0020 0x5800
+DATA 4 0x021b0818 0x0007
+DATA 4 0x021b4818 0x0007
+DATA 4 0x021b0004 0x0002556d
+DATA 4 0x021b4004 0x00011006
+DATA 4 0x021b001c 0x
+
+DATA 4 0x020c4068 0x00C03F3F
+DATA 4 0x020c406c 0x0030FC03
+DATA 4 0x020c4070 0x0FFFC000
+DATA 4 0x020c4074 0x3FF0
+DATA 4 0x020c4078 0x00FFF300
+DATA 4 0x020c407c 0x0FC3
+DATA 4 0x020c4080 0x03FF
+
+DATA 4 0x020e0010 0x

[U-Boot] [PATCH v2 1/5] iMX6Q:arm2: Add the kernel FDT Loading support

[Ye . Li]

To support loading FDT file for kernel, add the fdt address,
file and loading script to arm2 board default environment.

Signed-off-by: Ye.Li 
---
Changes since v1:
- None

 include/configs/mx6qarm2.h |   41 ++---
 1 files changed, 38 insertions(+), 3 deletions(-)

diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h
index fd651cf..f633525 100644
--- a/include/configs/mx6qarm2.h
+++ b/include/configs/mx6qarm2.h
@@ -67,15 +67,19 @@
 
 #define CONFIG_BOOTDELAY   3
 
-#define CONFIG_LOADADDR0x1080
+#define CONFIG_LOADADDR0x1200
 #define CONFIG_SYS_TEXT_BASE   0x1780
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"image=zImage\0" \
"console=ttymxc3\0" \
+   "fdt_file=imx6q-arm2.dtb\0" \
+   "fdt_addr=0x1800\0" \
"fdt_high=0x\0" \
"initrd_high=0x\0" \
+   "boot_fdt=try\0" \
+   "ip_dyn=yes\0" \
"mmcdev=1\0" \
"mmcpart=2\0" \
"mmcroot=/dev/mmcblk0p3 rootwait rw\0" \
@@ -86,15 +90,46 @@
"bootscript=echo Running bootscript from mmc ...; " \
"source\0" \
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+   "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
-   "bootz\0" \
+   "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+   "if run loadfdt; then " \
+   "bootz ${loadaddr} - ${fdt_addr}; " \
+   "else " \
+   "if test ${boot_fdt} = try; then " \
+   "bootz; " \
+   "else " \
+   "echo WARN: Cannot load the DT; " \
+   "fi; " \
+   "fi; " \
+   "else " \
+   "bootz; " \
+   "fi;\0" \
"netargs=setenv bootargs console=${console},${baudrate} " \
"root=/dev/nfs " \
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
"netboot=echo Booting from net ...; " \
"run netargs; " \
-   "dhcp ${image}; bootz\0" \
+   "if test ${ip_dyn} = yes; then " \
+   "setenv get_cmd dhcp; " \
+   "else " \
+   "setenv get_cmd tftp; " \
+   "fi; " \
+   "${get_cmd} ${image}; " \
+   "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+   "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+   "bootz ${loadaddr} - ${fdt_addr}; " \
+   "else " \
+   "if test ${boot_fdt} = try; then " \
+   "bootz; " \
+   "else " \
+   "echo WARN: Cannot load the DT; " \
+   "fi; " \
+   "fi; " \
+   "else " \
+   "bootz; " \
+   "fi;\0"
 
 #define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev};" \
-- 
1.7.4.1

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[U-Boot] [PATCH v2 5/5] iMX6Q/DL:arm2: Add support for i.MX6Q/DL arm2 LPDDR2 boards

[Ye . Li]

Update the ddr scripts for LPDDR2 and add two build configs for LPDDR2
arm2 board. Since the LPDDR2 arm2 board has different DDR size, use
CONFIG_DDR_MB in defconfig to replace the PHYS_SDRAM_SIZE.

Signed-off-by: Ye.Li 
---
Changes since v1:
- The (CONFIG_DDR_32BIT) is true only for mx6dlarm2

 board/freescale/mx6qarm2/imximage.cfg   |  189 +++-
 board/freescale/mx6qarm2/imximage_mx6dl.cfg |  319 +++
 board/freescale/mx6qarm2/mx6qarm2.c |7 +-
 configs/mx6dlarm2_defconfig |2 +-
 configs/mx6dlarm2_lpddr2_defconfig  |3 +
 configs/mx6qarm2_defconfig  |2 +-
 configs/mx6qarm2_lpddr2_defconfig   |3 +
 include/configs/mx6qarm2.h  |5 -
 8 files changed, 516 insertions(+), 14 deletions(-)
 create mode 100644 configs/mx6dlarm2_lpddr2_defconfig
 create mode 100644 configs/mx6qarm2_lpddr2_defconfig

diff --git a/board/freescale/mx6qarm2/imximage.cfg 
b/board/freescale/mx6qarm2/imximage.cfg
index 710f34d..c85bde5 100644
--- a/board/freescale/mx6qarm2/imximage.cfg
+++ b/board/freescale/mx6qarm2/imximage.cfg
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Copyright (C) 2011-2014 Freescale Semiconductor, Inc.
  * Jason Liu 
  *
  * SPDX-License-Identifier:GPL-2.0+
@@ -30,6 +30,185 @@ BOOT_FROM   sd
  * Address   absolute address of the register
  * value value to be stored in the register
  */
+#ifdef CONFIG_MX6DQ_LPDDR2
+/* DCD */
+DATA 4 0x020C4018 0x60324
+
+DATA 4 0x020E05a8 0x3038
+DATA 4 0x020E05b0 0x3038
+DATA 4 0x020E0524 0x3038
+DATA 4 0x020E051c 0x3038
+
+DATA 4 0x020E0518 0x3038
+DATA 4 0x020E050c 0x3038
+DATA 4 0x020E05b8 0x3038
+DATA 4 0x020E05c0 0x3038
+
+DATA 4 0x020E05ac 0x0038
+DATA 4 0x020E05b4 0x0038
+DATA 4 0x020E0528 0x0038
+DATA 4 0x020E0520 0x0038
+
+DATA 4 0x020E0514 0x0038
+DATA 4 0x020E0510 0x0038
+DATA 4 0x020E05bc 0x0038
+DATA 4 0x020E05c4 0x0038
+
+DATA 4 0x020E056c 0x0038
+DATA 4 0x020E0578 0x0038
+DATA 4 0x020E0588 0x0038
+DATA 4 0x020E0594 0x0038
+
+DATA 4 0x020E057c 0x0038
+DATA 4 0x020E0590 0x0038
+DATA 4 0x020E0598 0x0038
+DATA 4 0x020E058c 0x
+
+DATA 4 0x020E059c 0x0038
+DATA 4 0x020E05a0 0x0038
+DATA 4 0x020E0784 0x0038
+DATA 4 0x020E0788 0x0038
+
+DATA 4 0x020E0794 0x0038
+DATA 4 0x020E079c 0x0038
+DATA 4 0x020E07a0 0x0038
+DATA 4 0x020E07a4 0x0038
+
+DATA 4 0x020E07a8 0x0038
+DATA 4 0x020E0748 0x0038
+DATA 4 0x020E074c 0x0038
+DATA 4 0x020E0750 0x0002
+
+DATA 4 0x020E0758 0x
+DATA 4 0x020E0774 0x0002
+DATA 4 0x020E078c 0x0038
+DATA 4 0x020E0798 0x0008
+
+DATA 4 0x021b001c 0x8000
+DATA 4 0x021b401c 0x8000
+
+DATA 4 0x021b085c 0x1b5f01ff
+DATA 4 0x021b485c 0x1b5f01ff
+
+DATA 4 0x021b0800 0xa139
+DATA 4 0x021b4800 0xa139
+
+DATA 4 0x021b0890 0x0040
+DATA 4 0x021b4890 0x0040
+
+DATA 4 0x021b48bc 0x0005
+
+DATA 4 0x021b08b8 0x0800
+DATA 4 0x021b48b8 0x0800
+
+DATA 4 0x021b081c 0x
+DATA 4 0x021b0820 0x
+DATA 4 0x021b0824 0x
+DATA 4 0x021b0828 0x
+DATA 4 0x021b481c 0x
+DATA 4 0x021b4820 0x
+DATA 4 0x021b4824 0x
+DATA 4 0x021b4828 0x
+
+DATA 4 0x021b082c 0xf333
+DATA 4 0x021b0830 0xf333
+DATA 4 0x021b0834 0xf333
+DATA 4 0x021b0838 0xf333
+DATA 4 0x021b482c 0xf333
+DATA 4 0x021b4830 0xf333
+DATA 4 0x021b4834 0xf333
+DATA 4 0x021b4838 0xf333
+
+DATA 4 0x021b0848 0x49383b39
+DATA 4 0x021b0850 0x30364738
+DATA 4 0x021b4848 0x3e3c3846
+DATA 4 0x021b4850 0x4c294b35
+
+DATA 4 0x021b083c 0x2000
+DATA 4 0x021b0840 0x0
+DATA 4 0x021b483c 0x2000
+DATA 4 0x021b4840 0x0
+
+DATA 4 0x021b0858 0xf00
+DATA 4 0x021b4858 0xf00
+
+DATA 4 0x021b08b8 0x800
+DATA 4 0x021b48b8 0x800
+
+DATA 4 0x021b000c 0x555a61a5
+DATA 4 0x021b0004 0x20036
+DATA 4 0x021b0010 0x160e83
+DATA 4 0x021b0014 0xdd
+DATA 4 0x021b0018 0x8174c
+DATA 4 0x021b002c 0xf9f26d2
+DATA 4 0x021b0030 0x20e
+DATA 4 0x021b0038 0x200aac
+DATA 4 0x021b0008 0x0
+
+DATA 4 0x021b0040 0x5f
+
+DATA 4 0x021b 0xc301
+
+DATA 4 0x021b400c 0x555a61a5
+DATA 4 0x021b4004 0x20036
+DATA 4 0x021b4010 0x160e83
+DATA 4 0x021b4014 0xdd
+DATA 4 0x021b4018 0x8174c
+DATA 4 0x021b402c 0xf9f26d2
+DATA 4 0x021b4030 0x20e
+DATA 4 0x021b4038 0x200aac
+DATA 4 0x021b4008 0x0
+
+DATA 4 0x021b4040 0x3f
+DATA 4 0x021b4000 0xc301
+
+DATA 4 0x021b001c 0x3f8030
+DATA 4 0x021b001c 0xff0a8030
+DATA 4 0x021b001c 0xc2018030
+DATA 4 0x021b001c 0x6028030
+DATA 4 0x021b001c 0x2038030
+
+DATA 4 0x021b401c 0x3f8030
+DATA 4 0x021b401c 0xff0a8030
+DATA 4 0x021b401c 0xc2018030
+DATA 4 0x021b401c 0x6028030
+DATA 4 0x021b401c 0x2038030
+
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b4800 0xa1390003
+
+DATA 4 0x021b0020 0x7800
+DATA 4 0x021b4020 0x7800
+
+DATA 4 0x021b0818 0x0
+DATA 4 0x021b4818 0x0
+
+DATA 4 0x0

[U-Boot] [PATCH v2 2/5] iMX6Q:arm2: Change the mmcroot and mmcpart env value

[Ye . Li]

1. Set the image load partition to the first FAT partition.
2. Set the kernel rootfs partition to the second partition.

Signed-off-by: Ye.Li 
---
Changes since v1:
- None

 include/configs/mx6qarm2.h |4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h
index f633525..97329a3 100644
--- a/include/configs/mx6qarm2.h
+++ b/include/configs/mx6qarm2.h
@@ -81,8 +81,8 @@
"boot_fdt=try\0" \
"ip_dyn=yes\0" \
"mmcdev=1\0" \
-   "mmcpart=2\0" \
-   "mmcroot=/dev/mmcblk0p3 rootwait rw\0" \
+   "mmcpart=1\0" \
+   "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=${mmcroot}\0" \
"loadbootscript=" \
-- 
1.7.4.1

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[U-Boot] [PATCH v2 4/5] iMX6: Checking PLL2 PFD0 and PFD2 for periph_clk before PFD reset

[Ye . Li]

Checking the pre_periph_clk_sel and pre_periph2_clk of CCM CBCMR
register, if the PLL2 PFD0 or PLL2 PFD2 is used for the clock source,
do not reset this PFD to avoid system hang. Customers may set this
in DDR script or use BT_FREQ to select low freq boot.

Signed-off-by: Ye.Li 
---
Changes since v1:
- Add this patch before support LPDDR2 ARM2 board, because LPDDR2 use 400Mhz
- DDR and set pre_periph_clk_sel to PLL2 PFD2. So we can't reset PFD2.

 arch/arm/cpu/armv7/mx6/soc.c |   24 
 1 files changed, 16 insertions(+), 8 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index ac84a1f..fd87162 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -339,10 +339,10 @@ const struct boot_mode soc_boot_modes[] = {
 void s_init(void)
 {
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
-   int is_6q = is_cpu_type(MXC_CPU_MX6Q);
+   struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
u32 mask480;
u32 mask528;
-
+   u32 reg, periph1, periph2;
 
if (is_cpu_type(MXC_CPU_MX6SX))
return;
@@ -357,15 +357,23 @@ void s_init(void)
ANATOP_PFD_CLKGATE_MASK(1) |
ANATOP_PFD_CLKGATE_MASK(2) |
ANATOP_PFD_CLKGATE_MASK(3);
-   mask528 = ANATOP_PFD_CLKGATE_MASK(0) |
-   ANATOP_PFD_CLKGATE_MASK(1) |
+   mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
ANATOP_PFD_CLKGATE_MASK(3);
 
-   /*
-* Don't reset PFD2 on DL/S
-*/
-   if (is_6q)
+   reg = readl(&ccm->cbcmr);
+   periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
+   >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
+   periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
+   >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
+
+   /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
+   if ((periph2 != 0x2) && (periph1 != 0x2))
+   mask528 |= ANATOP_PFD_CLKGATE_MASK(0);
+
+   if ((periph2 != 0x1) && (periph1 != 0x1) &&
+   (periph2 != 0x3) && (periph1 != 0x3))
mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
+
writel(mask480, &anatop->pfd_480_set);
writel(mask528, &anatop->pfd_528_set);
writel(mask480, &anatop->pfd_480_clr);
-- 
1.7.4.1

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Re: [U-Boot] [PATCH] MAINTAINERS: update the maintainer of Arndale board

[Masahiro YAMADA]

Hello Mikyu,


Could you pick up this patch, please?
I think there is a consensus that the maintainership of Arndale board
should be updated.

Please see
http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/187338


2014-08-04 10:13 GMT+09:00 Masahiro Yamada :
> Inderpal's email address is not working any more.
> Chander will be a new maintainer.
>
> Signed-off-by: Masahiro Yamada 
> Cc: Chander Kashyap 
> Cc: Minkyu Kang 
> ---
>
> A new maintainer was assigned to Arndale board.
> But nobody wouldn't send a patch.
>
> Please see
> http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/187338
>
>
>  board/samsung/arndale/MAINTAINERS | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/board/samsung/arndale/MAINTAINERS 
> b/board/samsung/arndale/MAINTAINERS
> index 0a01a07..7dc1785 100644
> --- a/board/samsung/arndale/MAINTAINERS
> +++ b/board/samsung/arndale/MAINTAINERS
> @@ -1,5 +1,5 @@
>  ARNDALE BOARD
> -M: Inderpal Singh 
> +M: Chander Kashyap 
>  S: Maintained
>  F: board/samsung/arndale/
>  F: include/configs/arndale.h
> --



-- 
Best Regards
Masahiro Yamada
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Re: [U-Boot] [PATCH v3 3/4] cleanup code which handles the Android sparse image format

[Tom Rini]

On Thu, Sep 04, 2014 at 07:28:04AM +0200, Wolfgang Denk wrote:
> Dear Steve Rae,
> 
> In message <1409763954-5494-4-git-send-email-s...@broadcom.com> you wrote:
> > - port dprintf() to debug()
> > - update formatting
> > 
> > Signed-off-by: Steve Rae 
> > ---
> > 
> > Changes in v3:
> > - use original license text
> > 
> > Changes in v2:
> > - use BSD-3-Clause
> > 
> >  common/aboot.c | 97 
> > +-
> >  1 file changed, 56 insertions(+), 41 deletions(-)
> > 
> > diff --git a/common/aboot.c b/common/aboot.c
> > index a302c92..3611feb 100644
> > --- a/common/aboot.c
> > +++ b/common/aboot.c
> > @@ -28,6 +28,9 @@
> >   * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
> >   * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> >   *
> > + * NOTE:
> > + *   Although it is very similar, this license text is not identical
> > + *   to the "BSD-3-Clause", therefore, DO NOT MODIFY THIS LICENSE TEXT!
> >   */
> 
> I understand your intention of starting with the pristine file, and
> then adaptng it to U-Boot, but I don't like adding a broken file in
> patch 1/4 only to fix it later in patch 3/4. I think it would be
> better to squash these patches.

But it would make tracking things a bit harder.  We could squash 2/4 and
3/4 into one easy enough tho.

> Second, as already mentioned, we need to assign a SPDX ID for this.
> 
> Did you check with SPDX if there a matching ID?

So, we've gone round-and-round on this, and Steve is doing what I asked
him to here.  In sum, this is _not_ BSD-3, it's a one-off from it with
some interesting wording changes that mean we can't just call it BSD-3.
Since there's nothing else going to use this (and frankly I'm mildly
puzzled by how hard it is to dig up an aboot.c with sparse image support
that doesn't have this change but also does come from a google domain) I
didn't want to add a new license file for this non-standard license.

-- 
Tom


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Re: [U-Boot] [PATCH v2] kconfig: show an error message when defconfig is not found

[Stephen Warren]

On 09/04/2014 07:16 AM, Masahiro Yamada wrote:

When a non-existing defconfig is specified,
display an easy-to-understand message
(fake the error message on Linux Kernel):

   $ make foo_defconfig
   ***
   *** Can't find default configuration "confis/foo_defconfig"!
   ***


Acked-by: Stephen Warren 
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Re: [U-Boot] Call for participation in the U-Boot Mini Summit 2014

[Marek Vasut]

On Wednesday, September 03, 2014 at 06:39:23 PM, Detlev Zundel wrote:
> Hi Marek,
> 
> [...]
> 
> > I got my talk, "Secure and flexible boot with U-Boot bootloader",
> > accepted for the main track it seems. It's mostly about "use fitImage
> > and use UBI on NAND" kind of talk, which covers introduction to
> > fitImage and storing system components on UBI/UBIFS to prevent
> > problems like silent data corruption on modern systems.
> 
> Excellent!
> 
> > That being said, I believe I won't be able to cover the fitImage
> > verified boot part properly, so I might as well cook a talk for the
> > u-boot summit about this advanced topic.
> 
> We had a talk about that exact topic last year on the main track by
> Simon and in the mini summit by Jagan Teki[1].  In what respect will
> your talk differ from that?

I believe there is never enough advertising when it comes to fitImage, since
we want to get rid of uImage. On the other hand, I see no point in artificially
filling the talk slots, so consider my offer only as a backup solution.

Best regards,
Marek Vasut
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Re: [U-Boot] [U-boot] [Patch 2/6] ARM: keystone2: clock: add K2E clock support

[Ivan Khoronzhuk]

On 09/04/2014 05:08 PM, Murali Karicheri wrote:

On 07/15/2014 05:59 PM, Ivan Khoronzhuk wrote:

From: Hao Zhang

This patch adds clock definitions and commands to support Keystone2
K2E SOC.

Signed-off-by: Hao Zhang
Signed-off-by: Ivan Khoronzhuk
---
  arch/arm/cpu/armv7/keystone/Makefile   |   1 +
  arch/arm/cpu/armv7/keystone/clock-k2e.c| 101 
+

  arch/arm/cpu/armv7/keystone/clock.c|   2 +
  arch/arm/cpu/armv7/keystone/cmd_clock.c|  31 ++--
  arch/arm/include/asm/arch-keystone/clock-k2e.h |  68 +
  arch/arm/include/asm/arch-keystone/clock.h |   4 +
  include/configs/ks2_evm.h  |   2 +-
  7 files changed, 203 insertions(+), 6 deletions(-)
  create mode 100644 arch/arm/cpu/armv7/keystone/clock-k2e.c
  create mode 100644 arch/arm/include/asm/arch-keystone/clock-k2e.h

diff --git a/arch/arm/cpu/armv7/keystone/Makefile 
b/arch/arm/cpu/armv7/keystone/Makefile

index 74c5160..f8519c0 100644
--- a/arch/arm/cpu/armv7/keystone/Makefile
+++ b/arch/arm/cpu/armv7/keystone/Makefile
@@ -9,6 +9,7 @@ obj-y+= init.o
  obj-y+= psc.o
  obj-y+= clock.o
  obj-$(CONFIG_SOC_K2HK) += clock-k2hk.o
+obj-$(CONFIG_SOC_K2E) += clock-k2e.o
  obj-y+= cmd_clock.o
  obj-y+= cmd_mon.o
  obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_nav.o
diff --git a/arch/arm/cpu/armv7/keystone/clock-k2e.c 
b/arch/arm/cpu/armv7/keystone/clock-k2e.c

new file mode 100644
index 000..42092e1
--- /dev/null
+++ b/arch/arm/cpu/armv7/keystone/clock-k2e.c
@@ -0,0 +1,101 @@
+/*
+ * Keystone2: get clk rate for K2E
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated,
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include
+#include
+#include
+
+const struct keystone_pll_regs keystone_pll_regs[] = {
+[CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
+[PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
+[DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
+};
+
+/**
+ * pll_freq_get - get pll frequency
+ * Fout = Fref * NF(mult) / NR(prediv) / OD
+ * @pll:pll identifier
+ */
+static unsigned long pll_freq_get(int pll)
+{
+unsigned long mult = 1, prediv = 1, output_div = 2;
+unsigned long ret;
+u32 tmp, reg;
+
+if (pll == CORE_PLL) {
+ret = external_clk[sys_clk];
+if (pllctl_reg_read(pll, ctl)&  PLLCTL_PLLEN) {
+/* PLL mode */
+tmp = __raw_readl(KS2_MAINPLLCTL0);
+prediv = (tmp&  PLL_DIV_MASK) + 1;
+mult = (((tmp&  PLLM_MULT_HI_SMASK)>>  6) |
+(pllctl_reg_read(pll, mult)&
+PLLM_MULT_LO_MASK)) + 1;
+output_div = ((pllctl_reg_read(pll, secctl)>>
+   PLL_CLKOD_SHIFT)&  PLL_CLKOD_MASK) + 1;
+
+ret = ret / prediv / output_div * mult;
+}
+} else {
+switch (pll) {
+case PASS_PLL:
+ret = external_clk[pa_clk];
+reg = KS2_PASSPLLCTL0;
+break;
+case DDR3_PLL:
+ret = external_clk[ddr3_clk];
+reg = KS2_DDR3APLLCTL0;
+break;
+default:
+return 0;
+}
+
+tmp = __raw_readl(reg);
+
Please remove this line as below is part of this and should be in a 
block IMO. With this change,


Acked-by: Murali Karicheri  


Murali,

This patch is already applied.
I will remove this line in separate patch.
Thanks.


+ if (!(tmp&  PLLCTL_BYPASS)) {

+/* Bypass disabled */
+prediv = (tmp&  PLL_DIV_MASK) + 1;
+mult = ((tmp>>  PLL_MULT_SHIFT)& PLL_MULT_MASK) + 1;
+output_div = ((tmp>>  PLL_CLKOD_SHIFT)&
+  PLL_CLKOD_MASK) + 1;
+ret = ((ret / prediv) * mult) / output_div;
+}
+}
+
+return ret;
+}
+
+unsigned long clk_get_rate(unsigned int clk)
+{
+switch (clk) {
+case core_pll_clk:  return pll_freq_get(CORE_PLL);
+case pass_pll_clk:  return pll_freq_get(PASS_PLL);
+case ddr3_pll_clk:  return pll_freq_get(DDR3_PLL);
+case sys_clk0_1_clk:
+case sys_clk0_clk:  return pll_freq_get(CORE_PLL) / 
pll0div_read(1);
+case sys_clk1_clk:  return pll_freq_get(CORE_PLL) / 
pll0div_read(2);
+case sys_clk2_clk:  return pll_freq_get(CORE_PLL) / 
pll0div_read(3);
+case sys_clk3_clk:  return pll_freq_get(CORE_PLL) / 
pll0div_read(4);

+case sys_clk0_2_clk:return clk_get_rate(sys_clk0_clk) / 2;
+case sys_clk0_3_clk:return clk_get_rate(sys_clk0_clk) / 3;
+case sys_clk0_4_clk:return clk_get_rate(sys_clk0_clk) / 4;
+case sys_clk0_6_clk:return clk_get_rate(sys_clk0_clk) / 6;
+case sys_clk0_8_clk:return clk_get_rate(sys_clk0_clk) / 8;
+case sys_clk0_12_clk:   return clk_get_rate(sys_clk0_clk) / 12;
+case sys_clk0_24_clk:   return clk_get_rate(sys_clk0_clk) / 24;
+case sys_clk1_3_clk:return clk_get_rate(sys_clk1_clk) / 3;
+case sys_clk1_4_clk:return clk

[U-Boot] [U-boot] [Patch] ARM: keystone: ddr3: workaround for ddr3a/3b memory issue

[Ivan Khoronzhuk]

From: Murali Karicheri 

This patch implements a workaround to fix DDR3 memory issue.
The code for workaround detects PGSR0 errors and then preps for
and executes a software-controlled hard reset.In board_early_init,
where logic has been added to identify whether or not the previous
reset was a PORz. PLL initialization is skipped in the case of a
software-controlled hard reset.

Signed-off-by: Murali Karicheri 
Signed-off-by: Keegan Garcia 
Signed-off-by: Ivan Khoronzhuk 
---

Based on
"[U-boot] [Patch 0/6] keystone2: add k2l SoC and k2l_evm board support" series
http://www.mail-archive.com/u-boot@lists.denx.de/msg146472.html

 arch/arm/cpu/armv7/keystone/ddr3.c| 73 +++
 arch/arm/include/asm/arch-keystone/ddr3.h |  1 +
 arch/arm/include/asm/arch-keystone/hardware.h |  2 +
 board/ti/ks2_evm/ddr3_k2hk.c  |  4 ++
 4 files changed, 80 insertions(+)

diff --git a/arch/arm/cpu/armv7/keystone/ddr3.c 
b/arch/arm/cpu/armv7/keystone/ddr3.c
index 2391e79..8cb9279 100644
--- a/arch/arm/cpu/armv7/keystone/ddr3.c
+++ b/arch/arm/cpu/armv7/keystone/ddr3.c
@@ -10,6 +10,7 @@
 #include 
 #include 
 #include 
+#include 
 
 void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
 {
@@ -86,3 +87,75 @@ void ddr3_reset_ddrphy(void)
tmp &= ~KS2_DDR3_PLLCTRL_PHY_RESET;
__raw_writel(tmp, KS2_DDR3APLLCTL1);
 }
+
+/**
+ * ddr3_reset_workaround - reset workaround in case if leveling error
+ * detected for PG 1.0 and 1.1 k2hk SoCs
+ */
+void ddr3_err_reset_workaround(void)
+{
+   unsigned int tmp;
+   unsigned int tmp_a;
+   unsigned int tmp_b;
+
+   /*
+* Check for PGSR0 error bits of DDR3 PHY.
+* Check for WLERR, QSGERR, WLAERR,
+* RDERR, WDERR, REERR, WEERR error to see if they are set or not
+*/
+   tmp_a = __raw_readl(KS2_DDR3A_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET);
+   tmp_b = __raw_readl(KS2_DDR3B_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET);
+
+   if (((tmp_a & 0x0FE0) != 0) || ((tmp_b & 0x0FE0) != 0)) {
+   printf("DDR Leveling Error Detected!\n");
+   printf("DDR3A PGSR0 = 0x%x\n", tmp_a);
+   printf("DDR3B PGSR0 = 0x%x\n", tmp_b);
+
+   /*
+* Write Keys to KICK registers to enable writes to registers
+* in boot config space
+*/
+   __raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
+   __raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
+
+   /*
+* Move DDR3A Module out of reset isolation by setting
+* MDCTL23[12] = 0
+*/
+   tmp_a = __raw_readl(KS2_PSC_BASE +
+   PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3A));
+
+   tmp_a = PSC_REG_MDCTL_SET_RESET_ISO(tmp_a, 0);
+   __raw_writel(tmp_a, KS2_PSC_BASE +
+PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3A));
+
+   /*
+* Move DDR3B Module out of reset isolation by setting
+* MDCTL24[12] = 0
+*/
+   tmp_b = __raw_readl(KS2_PSC_BASE +
+   PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3B));
+   tmp_b = PSC_REG_MDCTL_SET_RESET_ISO(tmp_b, 0);
+   __raw_writel(tmp_b, KS2_PSC_BASE +
+PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3B));
+
+   /*
+* Write 0x5A69 Key to RSTCTRL[15:0] to unlock writes
+* to RSTCTRL and RSTCFG
+*/
+   tmp = __raw_readl(KS2_RSTCTRL);
+   tmp &= KS2_RSTCTRL_MASK;
+   tmp |= KS2_RSTCTRL_KEY;
+   __raw_writel(tmp, KS2_RSTCTRL);
+
+   /*
+* Set PLL Controller to drive hard reset on SW trigger by
+* setting RSTCFG[13] = 0
+*/
+   tmp = __raw_readl(KS2_RSTCTRL_RSCFG);
+   tmp &= ~KS2_RSTYPE_PLL_SOFT;
+   __raw_writel(tmp, KS2_RSTCTRL_RSCFG);
+
+   reset_cpu(0);
+   }
+}
diff --git a/arch/arm/include/asm/arch-keystone/ddr3.h 
b/arch/arm/include/asm/arch-keystone/ddr3.h
index 4d229a2..6bf35d3 100644
--- a/arch/arm/include/asm/arch-keystone/ddr3.h
+++ b/arch/arm/include/asm/arch-keystone/ddr3.h
@@ -50,6 +50,7 @@ struct ddr3_emif_config {
 
 void ddr3_init(void);
 void ddr3_reset_ddrphy(void);
+void ddr3_err_reset_workaround(void);
 void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
 void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
 
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h 
b/arch/arm/include/asm/arch-keystone/hardware.h
index 2eec4e7..29f7bf1 100644
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -121,9 +121,11 @@ typedef volatile unsigned int   *dv_reg_p;
 #define KS2_CLOCK_BASE KS2_PLL_CNTRL_BASE
 #define KS2_RSTCTRL_RSTYPE

Re: [U-Boot] [PATCH v4] arm: tegra: initial support for apalis t30

[Masahiro YAMADA]

Hi Marcel,

2014-09-02 19:57 GMT+09:00 Marcel Ziswiler :

>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index dd987cc..e5d31f9 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -701,6 +701,9 @@ config TARGET_WHISTLER
>  config TARGET_COLIBRI_T20_IRIS
> bool "Support colibri_t20_iris"
>
> +config TARGET_APALIS_T30
> +   bool "Support Apalis T30"
> +
>  config TARGET_COLIBRI_T30
> bool "Support Colibri T30"


I am afraid this patch is no longer applicable to the mainline
since commit ddd960e6c4b8412fa5c5a35f36cc3ac9f3ffbc16
(tegra: kconfig: move board select menu and common settings).

I am sorry about this, but could you rebase your patch please?


Tom Warren,
Could you have u-boot-tegra/master to be fast-forwarded to u-boot/master
to avoid a lator conflict ?



-- 
Best Regards
Masahiro Yamada
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[U-Boot] [PATCH] buildman: fix typos of --dry-run help message

[Masahiro Yamada]

try run=> dry run
no nothing => do nothing/
"..."  => '...'

The last one is for consistency with the other option helps.

Signed-off-by: Masahiro Yamada 
---

 tools/buildman/buildman.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/buildman/buildman.py b/tools/buildman/buildman.py
index e18859b..f01e14c 100755
--- a/tools/buildman/buildman.py
+++ b/tools/buildman/buildman.py
@@ -97,7 +97,7 @@ parser.add_option('-k', '--keep-outputs', action='store_true',
 parser.add_option('--list-tool-chains', action='store_true', default=False,
help='List available tool chains')
 parser.add_option('-n', '--dry-run', action='store_true', dest='dry_run',
-   default=False, help="Do a try run (describe actions, but no nothing)")
+   default=False, help='Do a dry run (describe actions, but do nothing)')
 parser.add_option('-o', '--output-dir', type='string',
dest='output_dir', default='..',
help='Directory where all builds happen and buildman has its workspace 
(default is ../)')
-- 
1.9.1

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Re: [U-Boot] [PATCH] buildman: fix typos of --dry-run help message

[Simon Glass]

On 4 September 2014 10:19, Masahiro Yamada  wrote:
> try run=> dry run
> no nothing => do nothing/
> "..."  => '...'
>
> The last one is for consistency with the other option helps.
>
> Signed-off-by: Masahiro Yamada 

Acked-by: Simon Glass 
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[U-Boot] [PATCH 0/2] A little improvement of Kbuild script and Makefile cleanup

[Masahiro Yamada]

1/2 imports a build script update from Linux.

2/2 refactors examples/standalone/Makefile based on 1/2.



Masahiro Yamada (2):
  scripts/Makefile.clean: clean also $(extra-m) and $(extra-)
  kbuild: standalone: simplify clean-files

 examples/standalone/Makefile | 2 +-
 scripts/Makefile.clean   | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

-- 
1.9.1

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[U-Boot] [PATCH 1/2] scripts/Makefile.clean: clean also $(extra-m) and $(extra-)

[Masahiro Yamada]

This commit is a backport from Linux Kernel,
commit 9d5db8949f1ecf4019785b04d8986835d3c0e99e,
written by me.

Signed-off-by: Masahiro Yamada 
---

This patch was well-reviewed on Linux Kbuild ML and
is already in the Linux mainline.
It is surely safe.


 scripts/Makefile.clean | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/scripts/Makefile.clean b/scripts/Makefile.clean
index d6dcd47..88f14e2 100644
--- a/scripts/Makefile.clean
+++ b/scripts/Makefile.clean
@@ -45,8 +45,8 @@ subdir-ymn:= $(foreach f, $(subdir-ymn), \
 # build a list of files to remove, usually relative to the current
 # directory
 
-__clean-files  := $(extra-y) $(always)  \
-  $(targets) $(clean-files) \
+__clean-files  := $(extra-y) $(extra-m) $(extra-)   \
+  $(always) $(targets) $(clean-files)   \
   $(host-progs) \
   $(hostprogs-y) $(hostprogs-m) $(hostprogs-)
 
-- 
1.9.1

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[U-Boot] [PATCH 2/2] kbuild: standalone: simplify clean-files

[Masahiro Yamada]

Files added $(extra-) are removed by "make clean".
Besides, wildcard "*.srec *.bin" is simpler.

Signed-off-by: Masahiro Yamada 
---

 examples/standalone/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile
index 2dacba2..0863a8c 100644
--- a/examples/standalone/Makefile
+++ b/examples/standalone/Makefile
@@ -22,7 +22,7 @@ extra-$(CONFIG_PPC)+= sched
 ELF := $(strip $(extra-y))
 
 extra-y += $(addsuffix .srec,$(extra-y)) $(addsuffix .bin,$(extra-y))
-clean-files  := $(extra-) $(addsuffix .srec,$(extra-)) $(addsuffix 
.bin,$(extra-))
+clean-files  := *.srec *.bin
 
 COBJS  := $(ELF:=.o)
 
-- 
1.9.1

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[U-Boot] Kernel XIP

[Camilo Andres Roca Duarte]

Dear U-boot team
I'm currently working on an embedded system that uses U-boot as a second
step bootloader. I'm testing the booting time of the kernel with binary
formats. Before I was able to flash the first level bootloader, the u-boot
and the kernel (uImage) into the nand flash of the embedded system with the
following command on u-boot:
bootcmd=nand read.jffs2 0x2200 0x20 0xB0; bootm 0x2200

- I would like to know if the bootm command is actually loading the
complete kernel to RAM or if it is loading only the required pages from
flash.

- Also, please correct me if I'm wrong but from the description of the
bootm command, it seemed to me as if the bootm command should be enough to
actually start the kernel, nevertheless I encountered myself with needing
to previously read the kernel from the flash, to later be able to boot it,
why is that so?

- I have also tried an xipImage for the kernel, nevertheless once I use
this binary format, uboot promts an error: can't get kernel image!
I checked the tutorial available at your website
, and I
confirmed that my linux configuration creates an xipImage (not a uImage as
stated in the tutorial). Does u-boot supports kernel execution in place?
and if so, does it only loads the necesary pages or does it fully loads the
kernel from the nand flash.

Thanks for your attention
Kind regards
_
Camilo Andres Roca Duarte
Communication and Media Engineering Student
Hochschule Offenburg
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[U-Boot] [PATCH] powerpc/mpc85xx: Serdes protocol "00" is supported

[Ebony Zhu]

"0x00" is a valid serdes protocol for QorIQ parts, and can not be
used to test whether the serdes is enabled or disabled.

Signed-off-by: Ebony Zhu 
---
 arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c | 5 -
 1 file changed, 5 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c 
b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
index d1fc76a..8edf5bb 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
@@ -186,11 +186,6 @@ u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, 
u32 sd_prctl_shift)
 #endif
 
cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask;
-   /* Is serdes enabled at all? */
-   if (!cfg) {
-   printf("SERDES%d is not enabled\n", sd + 1);
-   return 0;
-   }
 
 /* Erratum A-007186
  * Freescale Scratch Pad Fuse Register n (SFP_FSPFR0)
-- 
1.8.3.1

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[U-Boot] [PATCH v2] buildman: fix typos of --dry-run help message

[Masahiro Yamada]

try run=> dry run
no nothing => do nothing
"..."  => '...'

The last one is for consistency with the other option helps.

Signed-off-by: Masahiro Yamada 
Acked-by: Simon Glass 
---

Changes in v2:
  - Fix a typo in my git-log
   do nothing/  => do nothing

 tools/buildman/buildman.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/buildman/buildman.py b/tools/buildman/buildman.py
index 1258b76..d08dcd7 100755
--- a/tools/buildman/buildman.py
+++ b/tools/buildman/buildman.py
@@ -99,7 +99,7 @@ parser.add_option('-l', '--list-error-boards', 
action='store_true',
 parser.add_option('--list-tool-chains', action='store_true', default=False,
help='List available tool chains')
 parser.add_option('-n', '--dry-run', action='store_true', dest='dry_run',
-   default=False, help="Do a try run (describe actions, but no nothing)")
+   default=False, help='Do a dry run (describe actions, but do nothing)')
 parser.add_option('-o', '--output-dir', type='string',
dest='output_dir', default='..',
help='Directory where all builds happen and buildman has its workspace 
(default is ../)')
-- 
1.9.1

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Re: [U-Boot] Kernel XIP

[Wolfgang Denk]

Dear Camilo Andres Roca Duarte,

In message  
you wrote:
>
> - I would like to know if the bootm command is actually loading the
> complete kernel to RAM or if it is loading only the required pages from
> flash.

"bootm" has no knowledge about things like what a kernel is or what
required pages might be,  From the image header it gets only
information about start address and size of a memory range, and this
is what it will process.  I guess this matches what you call "complete
kernel".

But please be careful: when talking about the "loading" that takes
place, then keep in mind that this is a copy to system memory, or a
decompress and store to system memory, but in both cases the origin
of the data is also somewhwere in the memory address range, i. e. in
RAM, NOR flash or similar.

Actually the 'm' in "bootm" means "boot an image that is located
somewhere in *M*emory".

> - Also, please correct me if I'm wrong but from the description of the
> bootm command, it seemed to me as if the bootm command should be enough to
> actually start the kernel, nevertheless I encountered myself with needing
> to previously read the kernel from the flash, to later be able to boot it,
> why is that so?

With "flash", you mean NAND flash.  NAND flash is not memory, but a
storage device.  So you need other means to read the data from the
storage device into memory.  Only then you can use "bootm".

> - I have also tried an xipImage for the kernel, nevertheless once I use
> this binary format, uboot promts an error: can't get kernel image!

Using XIP requires a really detailed understand of all the steps of
the boot process, both in U-Boot and in the kernel.

> I checked the tutorial available at your website
> , and I

Please have a look at the age of this page - the information there
cannot be used directly on recent code; you will need to adjust it
carefully.  [And if you do and get it working, it would be magnificent
if you could also update the wiki page so it is up to date again.]

> confirmed that my linux configuration creates an xipImage (not a uImage as
> stated in the tutorial). Does u-boot supports kernel execution in place?

In principle it does, but you really have to kow exactly what you are
doing.

> and if so, does it only loads the necesary pages or does it fully loads the
> kernel from the nand flash.

You asked the same before - see above.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
You can do this in a number of ways. IBM chose to do all of them.
Why do you find that funny?-- D. Taylor, Computer Science 350
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[U-Boot] [PATCH v2] patman: make run results better visible

[Vadim Bendebury]

For an occasional user of patman some failures are not obvious: for
instance when checkpatch reports warnings, the dry run still reports
that the email would be sent. If it is not dry run, the warnings are
shown on the screen, but it is not clear that the email was not sent.

Add some code to report failure to send email explicitly.

Tested by running the script on a patch with style violations,
observed error messages in the script output.

Signed-off-by: Vadim Bendebury 
---

Changes in v2:
  - modified the error message for accuracy

 tools/patman/patman.py | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/tools/patman/patman.py b/tools/patman/patman.py
index c60aa5a..86e8e63 100755
--- a/tools/patman/patman.py
+++ b/tools/patman/patman.py
@@ -154,13 +154,18 @@ else:
 
 # Email the patches out (giving the user time to check / cancel)
 cmd = ''
-if ok or options.ignore_errors:
+its_a_go = ok or options.ignore_errors
+if its_a_go:
 cmd = gitutil.EmailPatches(series, cover_fname, args,
 options.dry_run, not options.ignore_bad_tags, cc_file,
 in_reply_to=options.in_reply_to)
+else:
+print col.Color(col.RED, "Not sending emails due to errors/warnings")
 
 # For a dry run, just show our actions as a sanity check
 if options.dry_run:
 series.ShowActions(args, cmd, options.process_tags)
+if not its_a_go:
+print col.Color(col.RED, "Email would not be sent")
 
 os.remove(cc_file)
-- 
2.1.0.rc2.206.gedb03e5

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[U-Boot] Problem writing to Samsung E-Die NAND on OpenRD-like platform

[Wolfgang Wegner]

Hi list,

we have a custom legacy board based on OpenRD platform and using
OpenRD config with slight changes (few GPIOs remapped, slower
SDRAM timing and redundant environment).
Now we had to change to Samsung E-Die NAND for a new assembly, and I
can not write to the NAND any more. Switching to up-to-date U-Boot
(git pull from yesterday's master branch) did not help, even though
I set CONFIG_SYS_NAND_NO_SUBPAGE_WRITE which seems to be one of the
problems. The errors result in ECC errors during read, and I can see
that almost complete garbage is written in the flash. However, the
errors are absolutely reproducible over multiple write and read
attempts as well as old (some early 2010) and current U-Boot version.
(I changed nand->chip_delay to 50 in our old u-boot tree to make it
work at all.)

I am out of ideas, so I try to ask here if anybody has an idea what
might be the problem or where to start further investigation. All I
could find yet are hints to the to-be-increased chip_delay and
CONFIG_SYS_NAND_NO_SUBPAGE_WRITE which I both set at least for the
new U-Boot version.

Here's how I tested this:
tftp 0x80 192.168.2.88:uImage
nand erase clean 0x20 0x60
nand write.jffs2 0x80 0x20 ${filesize}
nand read.jffs2 0xb0 0x20 0x30

Data written to flash:
Marvell>> md.b 0x80 0x80
0080: 27 05 19 56 ec 84 36 50 54 07 3a d2 00 23 7d e8'..V..6PT.:..#}.
00800010: 00 00 80 00 00 00 80 00 83 23 fb 58 05 02 02 00.#.X
00800020: 4c 69 6e 75 78 2d 32 2e 36 2e 33 36 2d 73 76 6eLinux-2.6.36-svn
00800030: 33 34 38 30 32 00 00 00 00 00 00 00 00 00 00 0034802...
00800040: 00 00 a0 e1 00 00 a0 e1 00 00 a0 e1 00 00 a0 e1
00800050: 00 00 a0 e1 00 00 a0 e1 00 00 a0 e1 00 00 a0 e1
00800060: 02 00 00 ea 18 28 6f 01 00 00 00 00 e8 7d 23 00.(o..}#.
00800070: 01 70 a0 e1 02 80 a0 e1 00 20 0f e1 03 00 12 e3.p... ..
Data read back from flash:
Marvell>> md.b 0xb0 0x80
00b0: ff ff fd ff ff ff ff ff ff ff 3a d2 ff ff ff ff..:.
00b00010: 00 00 80 00 00 00 ff ff ff ff fb 58 ff ff ff ff...X
00b00020: 4c 69 6e 75 ff ff ff ff ff ff 33 36 ff ff 76 6eLinu..36..vn
00b00030: ff ff 38 30 ff ff ff ff ff ff ff ff 00 00 00 00..80
00b00040: ff ff ff ff ff ff ff ff ff ff a0 e1 ff ff ff ff
00b00050: 00 00 a0 e1 00 00 ff ff ff ff a0 e1 ff ff ff ff
00b00060: 02 00 00 ea ff ff ff ff ff ff 00 00 ff ff 23 00..#.
00b00070: ff ff a0 e1 ff ff ff ff ff ff ff ff 03 00 12 e3

I can not recognize an actual pattern here, although some portions
seem regularly aligned.
When writing the same image using openocd (also some prehistoric
version dating back 2010.06), there are also errors, but only
very few single bit errors:
Marvell>> cmp.b 0x80 0xb0 0x237e28
byte at 0x008a923b (0x16) != byte at 0x00ba923b (0x12)
Total of 692795 byte(s) were the same

Marvell>cmp.b 0x8b 0xbb 0x187e28  
byte at 0x0093983f (0x2a) != byte at 0x00c3983f (0x28)
Total of 563263 byte(s) were the same
[...]

Does all this sound familiar to anybody?
Any help is greatly appreciated!

Best regards,
Wolfgang

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Re: [U-Boot] [PATCH v9 0/14] Add some missing buildman features and deprecate MAKEALL

[Simon Glass]

Hi Tom,


On 31 August 2014 23:07, Simon Glass  wrote:

> Hi Tom,
>
> On 28 August 2014 05:48, Tom Rini  wrote:
> > On Tue, Aug 26, 2014 at 08:54:03PM -0600, Simon Glass wrote:
> >> Hi Tom,
> >>
> >> On 25 August 2014 14:21, Tom Rini  wrote:
> >> > On Mon, Aug 25, 2014 at 01:00:05PM -0600, Simon Glass wrote:
> >> >> Hi Tom,
> >> >>
> >> >> On 25 August 2014 12:54, Tom Rini  wrote:
> >> >> > On Mon, Aug 25, 2014 at 09:58:21AM -0600, Simon Glass wrote:
> >> >> >
> >> >> >> Buildman has been around for a little over a year and is used by
> a fair
> >> >> >> number of U-Boot developers. However quite a few people still use
> MAKEALL.
> >> >> >>
> >> >> >> Buildman was intended to replace MAKEALL, so perhaps now is a
> good time to
> >> >> >> start that process.
> >> >> >>
> >> >> >> The reasons to deprecate MAKEALL are:
> >> >> >> - We don't want to maintain two build systems
> >> >> >> - Buildman is typically faster
> >> >> >> - Buildman has a lot more features
> >> >> >>
> >> >> >> This series adds a few features to buildman to fill some gaps,
> adds some
> >> >> >> information into the README on how to migrate from MAKEALL, and
> adds a
> >> >> >> deprecation message to MAKEALL.
> >> >> >
> >> >> > I'm testing this out again in the Ubuntu 10.04 / LSF environment I
> have
> >> >> > access to but so far I'm still finding that test for --no-decorate
> isn't
> >> >> > working and I have to manually set it to False.
> >> >>
> >> >> Oh dear. I wrote a test for this in the second series. So if you
> apply
> >> >> that series, do the tests pass? It is in func_test.py and is called
> >> >> testGitSetup().
> >> >
> >> > With my local kludge removed yes, all tests pass.
> >>
> >> It's quite mysterious. I installed Ubuntu 10.04 and it runs python
> 2.6.5.
> >>
> >> The --no-decorate patch does work, although it does print an error. I
> >> could suppress that easily enough, just adding another arg
> >> 'capture_stderr=True' to the RunPipe() call in gitutil.py.Setup().
> >>
> >> I see a problem with timedelta not having total_seconds. After that
> >> the threading dies. So I'm quite impressed you can get buildman to run
> >> at all. Are you using one of the later 10.04 releases?
> >
> > *shakes fist at corporate IT*
> >
> > The box I use to launch jobs is Ubuntu 10.04.4.  The boxes the jobs run
> > on are actually Ubuntu 12.04.1 (I had assumed it was all the same for
> > some reason.
> >
> > They also have git 1.7.9.5.
>
> Well they obviously can't make it *too* easy. So where does this leave
> us in trying to figure this out?
>

It feels like we should probably get the current patches in and see where
this leaves us. I'll work on a pull request, unless you think we should
wait.

Regards,
Simon
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Re: [U-Boot] [PATCH v2 3/5] iMX6DL:arm2: Add support for i.MX6DL arm2 DDR3 board

[Otavio Salvador]

Hello Ye,

On Thu, Sep 4, 2014 at 11:17 AM, Ye.Li  wrote:
> This patch adds the i.MX6DL arm2 board support. The i.MX6DL ARM2
> shared the same board with i.MX6Q ARM2 board since the i.MX6DL is
> pin-pin compatible with i.MX6Q.
>
> The patch also support the DDR 32-BIT mode option. Please define
> CONFIG_DDR_32BIT in the board configure file to enable DDR 32-BIT
> mode.But due to the board design, it's 64bit DDR buswidth physically,
> so, if you CONFIG_DDR_32BIT, the DDR memory size will be half of it.
>
> Signed-off-by: Ye.Li 

Your patch short log could be improved for:

imx: mx6dlarm2: Add support for i.MX6DL arm2 DDR3 board

This could be reworked on the other patches as well.

My 2c.

-- 
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Re: [U-Boot] [PATCH v2] patman: make run results better visible

[Doug Anderson]

Vadim,

On Thu, Sep 4, 2014 at 10:45 AM, Vadim Bendebury  wrote:
> For an occasional user of patman some failures are not obvious: for
> instance when checkpatch reports warnings, the dry run still reports
> that the email would be sent. If it is not dry run, the warnings are
> shown on the screen, but it is not clear that the email was not sent.
>
> Add some code to report failure to send email explicitly.
>
> Tested by running the script on a patch with style violations,
> observed error messages in the script output.
>
> Signed-off-by: Vadim Bendebury 
> ---
>
> Changes in v2:
>   - modified the error message for accuracy
>
>  tools/patman/patman.py | 7 ++-
>  1 file changed, 6 insertions(+), 1 deletion(-)

Reviewed-by: Doug Anderson 
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Re: [U-Boot] SPL broken on i.mx31 platforms

[Magnus Lilja]

Hi

On 3 September 2014 03:13, Tom Rini  wrote:
> On Wed, Sep 03, 2014 at 02:53:17AM +0200, Benoît Thébaudeau wrote:
>> > IMHO, the 'b reset' and the 'nop nop nop' are two different issues, so
>> > Helmut should create a formal patch for the 'b reset' issue right now,
>> > which will fix mx31pdk (and maybe other boards) for the release. Then,
>> > once the 'nop nop nop' issue has been resolved for TT-01 (cache issue
>> > or something else), another formal patch should be created for this
>> > issue, unless it is purely out of tree.
>>
>> v2014.10 is getting closer with the release of -rc2. It would be much
>> better to get mx31pdk fixed for this release. Helmut, can you send a
>> patch for the 'b reset' issue? If not, do you agree that someone else
>> (maybe the board maintainer: Magnus?) sends it with a 'Reported-by:
>> Helmut Raiger '?
>
> Yes, please, I'd like to see this fixed for the release proper.

I'll try to test and submit a match in a couple of days.

Regards, Magnus
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Re: [U-Boot] SPL broken on i.mx31 platforms

[Benoît Thébaudeau]

Hi Magnus,

On Thu, Sep 4, 2014 at 9:12 PM, Magnus Lilja  wrote:
> On 3 September 2014 03:13, Tom Rini  wrote:
>> On Wed, Sep 03, 2014 at 02:53:17AM +0200, Benoît Thébaudeau wrote:
>>> > IMHO, the 'b reset' and the 'nop nop nop' are two different issues, so
>>> > Helmut should create a formal patch for the 'b reset' issue right now,
>>> > which will fix mx31pdk (and maybe other boards) for the release. Then,
>>> > once the 'nop nop nop' issue has been resolved for TT-01 (cache issue
>>> > or something else), another formal patch should be created for this
>>> > issue, unless it is purely out of tree.
>>>
>>> v2014.10 is getting closer with the release of -rc2. It would be much
>>> better to get mx31pdk fixed for this release. Helmut, can you send a
>>> patch for the 'b reset' issue? If not, do you agree that someone else
>>> (maybe the board maintainer: Magnus?) sends it with a 'Reported-by:
>>> Helmut Raiger '?
>>
>> Yes, please, I'd like to see this fixed for the release proper.
>
> I'll try to test and submit a match in a couple of days.

I have already submitted a patch for that yesterday. It's 'arm: Make
reset position-independent', and you were in Cc. So you just have to
test and to add your 'Tested-by'.

Thanks in advance.

Best regards,
Benoît
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Re: [U-Boot] SPL broken on i.mx31 platforms

[Magnus Lilja]

Hi


On 4 September 2014 21:50, Benoît Thébaudeau
 wrote:
> Hi Magnus,
>
 v2014.10 is getting closer with the release of -rc2. It would be much
 better to get mx31pdk fixed for this release. Helmut, can you send a
 patch for the 'b reset' issue? If not, do you agree that someone else
 (maybe the board maintainer: Magnus?) sends it with a 'Reported-by:
 Helmut Raiger '?
>>>
>>> Yes, please, I'd like to see this fixed for the release proper.
>>
>> I'll try to test and submit a match in a couple of days.
>
> I have already submitted a patch for that yesterday. It's 'arm: Make
> reset position-independent', and you were in Cc. So you just have to
> test and to add your 'Tested-by'.

Ah, missed that. Excellent, I'll test that within a day or two then!

Regards, Magnus
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Re: [U-Boot] [PATCH v3 0/4] introduce get_maintainer.pl

[Daniel Schwierzeck]

Hi Simon,

2014-09-04 1:34 GMT+02:00 Simon Glass :
> Hi Daniel,
>
> On 31 July 2014 18:24, Daniel Schwierzeck  
> wrote:
>>
>> This series imports get_maintainer.pl from kernel and reintroduce
>> the MAINTAINERS file in the according format. Currently one have to
>> manually grep all infos about board maintainers or custodians from
>> various sources like git log, wiki or boards.cfg. get_maintainer.pl
>> makes this task much easier. Also patman is already able to use it
>> for cc-cmd.
>>
>> The MAINTAINERS file contains all custodians and is hand-written based
>> on infos from wiki [1] and u-boot git forks [2]. Thus the source files
>> infos (F:) are not complete yet. Furthermore status (S:) and
>> maintainership (M:) for some custodian trees are probably wrong.
>> Any help in completing and fixing that is appreciated.
>>
>> The get_maintainers.pl script is modified to scan multiple
>> MAINTAINERS files in the board directory. This is required
>> with the switch to Kconfig which adds a MAINTAINERS file per board.
>>
>> Examples:
>>
>>  $ ./scripts/get_maintainer.pl --nogit-fallback -f board/sandbox/
>>Simon Glass  (maintainer:SANDBOX BOARD)
>>u-boot@lists.denx.de (open list)
>>
>>  $ ./scripts/get_maintainer.pl --nogit-fallback -f arch/sandbox/
>>Simon Glass  (maintainer:SANDBOX)
>>u-boot@lists.denx.de (open list)
>>
>>  $ ./scripts/get_maintainer.pl --nogit-fallback -f board/sandburst/metrobox/
>>Travis Sawyer  (orphan (since 
>> 2014-03):METROBOX BOARD)
>>u-boot@lists.denx.de (open list)
>>
>> This series is also available at 
>> git://git.denx.de/u-boot-mips.git/maintainers_v3.
>
> Patman now picks this up which is great. But it does sometimes produce
> a long list of maintainers. I wonder if we could have an option to
> turn it off (perhaps -m)?
>
> Regards,
> Simon

I think we should generally adapt the options for get_maintainers.pl
patman uses to not include all committers by default. Either we could
completely disable git (--nogit-fallback). Or we could increase the
minimum percentage of commits required (--git-min-percent 10).

-- 
- Daniel
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Re: [U-Boot] ARM: DRA72: DDR3: Add emif settings for 666MHz clock

[Tom Rini]

On Thu, Aug 28, 2014 at 12:01:04PM +0530, Lokesh Vutla wrote:

> From: R Sricharan 
> 
> On DRA72x, EMIF supports DDR3 upto 667MHz.
> Adding the required settings for DDR3 at 666MHz and enabling it.
> 
> Signed-off-by: R Sricharan 
> Signed-off-by: Lokesh Vutla 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] [U-Boot, U-boot] ARM: keystone: clock: use correct BWADJ field mask for PASSPLLCTL0

[Tom Rini]

On Mon, Aug 11, 2014 at 11:59:42AM +0300, Khoronzhuk, Ivan wrote:

> The mask for BWADJ field of PASSPLLCTL0 register has to be 0xff, but
> by mistake, here is used shift instead of mask, so correct it.
> 
> Signed-off-by: Ivan Khoronzhuk 

Applied to u-boot/master, thanks!

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Re: [U-Boot] omap3_beagle: Add boot script support to omap3 beagle board

[Tom Rini]

On Tue, Aug 26, 2014 at 10:48:13AM +0200, Guillaume GARDET wrote:

> This patch adds boot script support to omap3 beagle board.
> 
> Signed-off-by: Guillaume GARDET 
> Cc: Tom Rini 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, U-boot] keystone2: use readl/writel functions instead of redefinition

[Tom Rini]

On Thu, Aug 28, 2014 at 04:07:45PM +0300, Khoronzhuk, Ivan wrote:

> There is no reason to redefine pure readl/writel functions.
> So remove this redundancy.
> 
> Signed-off-by: Ivan Khoronzhuk 
> Acked-by: Vitaly Andrianov 

Applied to u-boot/master, thanks!

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Re: [U-Boot] arm: am335x: add Kconfig range attribute to prevent invalid CONS_INDEX

[Tom Rini]

On Mon, Sep 01, 2014 at 01:05:32AM +0900, Masahiro Yamada wrote:

> The help message in board/ti/am335x/Kconfig says AM335x has
> 6 UARTs, so the valid number for CONFIG_CONS_INDEX is from 1 to 6.
> 
> Signed-off-by: Masahiro Yamada 
> Cc: Tom Rini 

Applied to u-boot/master, thanks!

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Re: [U-Boot] [U-Boot, U-boot] mtd: nand: davinci_nand: correct keystone RBL layout definition

[Tom Rini]

On Tue, Sep 02, 2014 at 12:20:02AM +0300, Khoronzhuk, Ivan wrote:

> In case when 4K page keystone RBL layout is used the compilation
> error is appeared. That's because the #ifdef has to be placed under
> struct name. This patch correct it.
> 
> Signed-off-by: Ivan Khoronzhuk 

Applied to u-boot/master, thanks!

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Re: [U-Boot] mtd: nand: omap_gpmc: Enable multiple NAND flash devices

[Tom Rini]

On Tue, Sep 02, 2014 at 04:23:58PM +0200, Rostislav Lisovy wrote:

> Since the CS of a device connected to the GPMC was
> stored in the global variable, it was not possible to
> use multiple devices. In this patch the CS is stored per
> device in its 'struct omap_nand_info'. This makes it
> possible to use up to 'GPMC_MAX_CS' NAND Flash devices
> connected to U-boot.
> 
> Signed-off-by: Rostislav Lisovy 

Applied to u-boot/master, thanks!

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Re: [U-Boot] AM335x: igep0033: Convert to generic board and use ti_am335x_common.h.

[Tom Rini]

On Wed, Sep 03, 2014 at 05:59:57PM +0200, Enric Balletbò i Serra wrote:

> From: Enric Balletbo i Serra 
> 
> To reduce code duplication update am335x_igep0033.h to use ti_am335x_common.h
> and convert to generic board.
> 
> Signed-off-by: Enric Balletbo i Serra 

Applied to u-boot/master, thanks!

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Re: [U-Boot] mtd: nand: omap_gpmc: Fix 'bit-flip' errors

[Tom Rini]

On Tue, Sep 02, 2014 at 05:00:30PM +0200, Rostislav Lisovy wrote:

> OMAP GPMC driver used with some NAND Flash devices (e.g. Spansion
> S34ML08G1) causes that U-boot shows hundreds of 'nand: bit-flip
> corrected' error messages. Possible cause was discussed in the
> mailinglist thread:
> http://lists.denx.de/pipermail/u-boot/2014-April/177508.html
> 
> Quote (Author: Pekon Gupta ): "The issue is mainly
> due to a NAND protocol violation in the omap driver since the
> Random Data Output command (05h-E0h) expects to see only the
> column address that should be addressed within the already loaded
> read page into the read buffer. Only 2 address cycles with ALE
> active should be provided between the 05h and E0h commands. The
> Page read command expects the full address footprint (2bytes for
> column address + 3bytes for row address), but once the page is
> loaded into the read buffer, Random Data Output should be used
> with only 2bytes for column address."
> 
> This patch combines the solution proposed in the mailinglist and
> the patch provided by the Spansion company (GPLv2 code, source:
> http://www.spansion.com/Support/Software/u-boot-psp-04.04.00.01-NAND.zip)
> 
> Signed-off-by: Rostislav Lisovy 

Applied to u-boot/master, thanks!

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[U-Boot] Please pull u-boot-ti/master

[Tom Rini]

Hey,

The following changes since commit d6c1ffc7d23f4fe4ae8c91101861055b8e1501b6:

  Prepare v2014.10-rc2 (2014-09-02 16:58:29 -0400)

are available in the git repository at:

  git://git.denx.de/u-boot-ti.git master

for you to fetch changes up to 681f785f7cc616a70aaa0c93a25300b0820f6968:

  ARM: DRA72: DDR3: Add emif settings for 666MHz clock (2014-09-04 13:12:49 
-0400)


Enric Balletbo i Serra (1):
  AM335x: igep0033: Convert to generic board and use ti_am335x_common.h.

Guillaume GARDET (1):
  omap3_beagle: Add boot script support to omap3 beagle board

Khoronzhuk, Ivan (3):
  ARM: keystone: clock: use correct BWADJ field mask for PASSPLLCTL0
  keystone2: use readl/writel functions instead of redefinition
  mtd: nand: davinci_nand: correct keystone RBL layout definition

Masahiro Yamada (1):
  arm: am335x: add Kconfig range attribute to prevent invalid CONS_INDEX

R Sricharan (1):
  ARM: DRA72: DDR3: Add emif settings for 666MHz clock

Rostislav Lisovy (2):
  mtd: nand: omap_gpmc: Enable multiple NAND flash devices
  mtd: nand: omap_gpmc: Fix 'bit-flip' errors

 arch/arm/cpu/armv7/keystone/clock.c|2 +-
 arch/arm/cpu/armv7/keystone/psc.c  |   44 ++---
 arch/arm/cpu/armv7/omap5/hw_data.c |   39 -
 arch/arm/cpu/armv7/omap5/sdram.c   |   60 ++-
 arch/arm/include/asm/arch-keystone/emac_defs.h |7 +-
 board/ti/am335x/Kconfig|1 +
 drivers/mtd/nand/davinci_nand.c|2 +-
 drivers/mtd/nand/omap_gpmc.c   |   46 +++--
 drivers/net/keystone_net.c |   35 ++--
 include/configs/am335x_igep0033.h  |  221 +---
 include/configs/omap3_beagle.h |   13 +-
 11 files changed, 210 insertions(+), 260 deletions(-)

-- 
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Re: [U-Boot] [PATCH v3 0/4] introduce get_maintainer.pl

[Simon Glass]

Hi Daniel,


On 4 September 2014 14:45, Daniel Schwierzeck 
wrote:

> Hi Simon,
>
> 2014-09-04 1:34 GMT+02:00 Simon Glass :
> > Hi Daniel,
> >
> > On 31 July 2014 18:24, Daniel Schwierzeck 
> wrote:
> >>
> >> This series imports get_maintainer.pl from kernel and reintroduce
> >> the MAINTAINERS file in the according format. Currently one have to
> >> manually grep all infos about board maintainers or custodians from
> >> various sources like git log, wiki or boards.cfg. get_maintainer.pl
> >> makes this task much easier. Also patman is already able to use it
> >> for cc-cmd.
> >>
> >> The MAINTAINERS file contains all custodians and is hand-written based
> >> on infos from wiki [1] and u-boot git forks [2]. Thus the source files
> >> infos (F:) are not complete yet. Furthermore status (S:) and
> >> maintainership (M:) for some custodian trees are probably wrong.
> >> Any help in completing and fixing that is appreciated.
> >>
> >> The get_maintainers.pl script is modified to scan multiple
> >> MAINTAINERS files in the board directory. This is required
> >> with the switch to Kconfig which adds a MAINTAINERS file per board.
> >>
> >> Examples:
> >>
> >>  $ ./scripts/get_maintainer.pl --nogit-fallback -f board/sandbox/
> >>Simon Glass  (maintainer:SANDBOX BOARD)
> >>u-boot@lists.denx.de (open list)
> >>
> >>  $ ./scripts/get_maintainer.pl --nogit-fallback -f arch/sandbox/
> >>Simon Glass  (maintainer:SANDBOX)
> >>u-boot@lists.denx.de (open list)
> >>
> >>  $ ./scripts/get_maintainer.pl --nogit-fallback -f
> board/sandburst/metrobox/
> >>Travis Sawyer  (orphan (since
> 2014-03):METROBOX BOARD)
> >>u-boot@lists.denx.de (open list)
> >>
> >> This series is also available at git://
> git.denx.de/u-boot-mips.git/maintainers_v3.
> >
> > Patman now picks this up which is great. But it does sometimes produce
> > a long list of maintainers. I wonder if we could have an option to
> > turn it off (perhaps -m)?
> >
> > Regards,
> > Simon
>
> I think we should generally adapt the options for get_maintainers.pl
> patman uses to not include all committers by default. Either we could
> completely disable git (--nogit-fallback). Or we could increase the
> minimum percentage of commits required (--git-min-percent 10).
>

OK, so long as there is a way to also make get_maintainers.pl a nop, then
that is fine with me.

Regards,
Simon
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[U-Boot] [PATCH v5 0/14] Introduce driver model serial uclass

[Simon Glass]

This series adds support for a serial uclass, enabling serial drivers to be
converted to use driver model.

With v4, exynos boards all build and a second attempt has been made to add
Tegra support via the ns16550 driver, tested on beaver, Jetson-TK1 and
seaboard (i.e. 3 of the 4 SoCs in mainline).

To see the current state of driver model, look at u-boot-dm.git branch
'working'. This branch is at 'serial-working'.

Changes in v5:
- Add new patch to add a function to look up a chosen node
- Add struct udevice declaration
- Use /chosen/stdout-path instead of /aliases/console to specify the console

Changes in v4:
- Add a binding for sandbox serial
- Add a separate Tegra serial driver to deal with the clock issue
- Add new CONFIG_TEGRA_SERIAL option to enable dm driver
- Remove 'clock-frequency' property from serial nodes
- Remove clock frequency setup for ns16550 driver
- Remove pre-reloc fdt property
- Use hard-coded UART clock from Tegra configuration

Changes in v3:
- Add new change to enhance lists_bind_fdt()
- Add new patch for tegra serial port details
- Add new patch to collect common baud rate code in ns16550
- Add new patch to enable driver model for serial on tegra
- Add new patch to move baud rate calculation to ns16550.c
- Add new patch to support driver model in ns16550
- Add new patch to use V_NS16550_CLK only in SPL builds
- Automatically bind the console even if not marked for pre-relocation
- Avoid reordering functions
- Change pre-reloc fdt property to 'u-boot,dm-pre-reloc'
- Fix typo in commit message

Changes in v2:
- Rename struct device to struct udevice

Simon Glass (14):
  serial: Set up the 'priv' pointer when creating a serial device
  dm: fdt: Add a function to look up a chosen node
  dm: Adjust lists_bind_fdt() to return the bound device
  dm: Add a uclass for serial devices
  sandbox: Convert serial driver to use driver model
  sandbox: serial: Support a coloured console
  sandbox: dts: Add a serial console node
  dm: exynos: Mark exynos5 console as pre-reloc
  dm: exynos: Move serial to driver model
  dm: serial: Move baud rate calculation to ns16550.c
  dm: serial: Collect common baud rate code in ns16550
  dm: serial: Add driver model support for ns16550
  tegra: dts: Add serial port details
  dm: tegra: Enable driver model for serial

 arch/arm/dts/exynos5.dtsi  |   1 +
 arch/arm/dts/tegra114-dalmore.dts  |   4 +
 arch/arm/dts/tegra114.dtsi |  53 
 arch/arm/dts/tegra124-jetson-tk1.dts   |   4 +
 arch/arm/dts/tegra124-venice2.dts  |   4 +
 arch/arm/dts/tegra124.dtsi |  66 
 arch/arm/dts/tegra20-colibri_t20_iris.dts  |   4 +
 arch/arm/dts/tegra20-harmony.dts   |   4 +
 arch/arm/dts/tegra20-medcom-wide.dts   |   4 +
 arch/arm/dts/tegra20-paz00.dts |   4 +
 arch/arm/dts/tegra20-plutux.dts|   4 +
 arch/arm/dts/tegra20-seaboard.dts  |   4 +
 arch/arm/dts/tegra20-tec.dts   |   4 +
 arch/arm/dts/tegra20-trimslice.dts |   4 +
 arch/arm/dts/tegra20-ventana.dts   |   4 +
 arch/arm/dts/tegra20-whistler.dts  |   4 +
 arch/arm/dts/tegra20.dtsi  |  51 ++-
 arch/arm/dts/tegra30-beaver.dts|   4 +
 arch/arm/dts/tegra30-cardhu.dts|   4 +
 arch/arm/dts/tegra30-tamonten.dtsi |   4 +
 arch/arm/dts/tegra30.dtsi  |  66 
 arch/sandbox/dts/sandbox.dts   |  10 +
 doc/device-tree-bindings/serial/ns16550.txt|  10 +
 doc/device-tree-bindings/serial/sandbox-serial.txt |  13 +
 drivers/core/lists.c   |  10 +-
 drivers/core/root.c|   2 +-
 drivers/serial/Makefile|   7 +-
 drivers/serial/ns16550.c   | 203 ++--
 drivers/serial/sandbox.c   | 140 +++--
 drivers/serial/serial-uclass.c | 214 +
 drivers/serial/serial.c|   1 +
 drivers/serial/serial_ns16550.c|  14 +-
 drivers/serial/serial_s5p.c| 255 +--
 drivers/serial/serial_tegra.c  |  38 +++
 include/configs/exynos-common.h|   1 +
 include/configs/sandbox.h  |   3 +
 include/configs/tegra-common.h |   9 +-
 include/dm/lists.h |   6 +-
 include/dm/uclass-id.h |   1 +
 include/dt-bindings/clock/tegra114-car.h   | 342 +
 include/dt-bindings/clock/tegra124-car.h   | 342 +
 include/dt-bindings/clock/tegra20-car.h| 158 ++
 include/dt-bindings/clock/tegra30-car.h| 273 ++

[U-Boot] [PATCH v5 01/14] serial: Set up the 'priv' pointer when creating a serial device

[Simon Glass]

The stdio_dev structure has a private pointer for its creator, but it is
not set up by the serial system. Set it to point to the serial device so
that it can be found by code called by stdio.

Signed-off-by: Simon Glass 
---

Changes in v5: None
Changes in v4: None
Changes in v3:
- Fix typo in commit message

Changes in v2: None

 drivers/serial/serial.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index d2eb752..bbe60af 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -320,6 +320,7 @@ void serial_stdio_init(void)
dev.puts = serial_stub_puts;
dev.getc = serial_stub_getc;
dev.tstc = serial_stub_tstc;
+   dev.priv = s;
 
stdio_register(&dev);
 
-- 
2.1.0.rc2.206.gedb03e5

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[U-Boot] [PATCH v5 02/14] dm: fdt: Add a function to look up a chosen node

[Simon Glass]

Within /chosen we may have a node which points to another node, similar
to how /aliases works. Add a helper function to do this lookup.

Signed-off-by: Simon Glass 
---

Changes in v5:
- Add new patch to add a function to look up a chosen node

Changes in v4: None
Changes in v3: None
Changes in v2: None

 include/fdtdec.h | 12 
 lib/fdtdec.c | 15 +++
 2 files changed, 27 insertions(+)

diff --git a/include/fdtdec.h b/include/fdtdec.h
index 5f88938..2590d30 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -376,6 +376,18 @@ int fdtdec_get_alias_seq(const void *blob, const char 
*base, int node,
  */
 int fdtdec_get_alias_node(const void *blob, const char *name);
 
+/**
+ * Get the offset of the given chosen node
+ *
+ * This looks up a property in /chosen containing the path to another node,
+ * then finds the offset of that node.
+ *
+ * @param blob Device tree blob (if NULL, then error is returned)
+ * @param name Property name, e.g. "stdout-path"
+ * @return Node offset referred to by that chosen node, or -ve FDT_ERR_...
+ */
+int fdtdec_get_chosen_node(const void *blob, const char *name);
+
 /*
  * Get the name for a compatible ID
  *
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index c2f3645..06d4542 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -382,6 +382,21 @@ int fdtdec_get_alias_node(const void *blob, const char 
*name)
return fdt_path_offset(blob, prop);
 }
 
+int fdtdec_get_chosen_node(const void *blob, const char *name)
+{
+   const char *prop;
+   int chosen_node;
+   int len;
+
+   if (!blob)
+   return -FDT_ERR_NOTFOUND;
+   chosen_node = fdt_path_offset(blob, "/chosen");
+   prop = fdt_getprop(blob, chosen_node, name, &len);
+   if (!prop)
+   return -FDT_ERR_NOTFOUND;
+   return fdt_path_offset(blob, prop);
+}
+
 int fdtdec_check_fdt(void)
 {
/*
-- 
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[U-Boot] [PATCH v5 09/14] dm: exynos: Move serial to driver model

[Simon Glass]

Change the Exynos serial driver to work with driver model and switch over
all Exynos5 boards to use it.

Signed-off-by: Simon Glass 
---

Changes in v5: None
Changes in v4: None
Changes in v3:
- Avoid reordering functions

Changes in v2: None

 drivers/serial/serial_s5p.c | 255 
 include/configs/exynos-common.h |   1 +
 2 files changed, 73 insertions(+), 183 deletions(-)

diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c
index 98c62b4..8469afd 100644
--- a/drivers/serial/serial_s5p.c
+++ b/drivers/serial/serial_s5p.c
@@ -9,6 +9,8 @@
  */
 
 #include 
+#include 
+#include 
 #include 
 #include 
 #include 
@@ -18,26 +20,18 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define RX_FIFO_COUNT_MASK 0xff
-#define RX_FIFO_FULL_MASK  (1 << 8)
-#define TX_FIFO_FULL_MASK  (1 << 24)
+#define RX_FIFO_COUNT_SHIFT0
+#define RX_FIFO_COUNT_MASK (0xff << RX_FIFO_COUNT_SHIFT)
+#define RX_FIFO_FULL   (1 << 8)
+#define TX_FIFO_COUNT_SHIFT16
+#define TX_FIFO_COUNT_MASK (0xff << TX_FIFO_COUNT_SHIFT)
+#define TX_FIFO_FULL   (1 << 24)
 
 /* Information about a serial port */
-struct fdt_serial {
-   u32 base_addr;  /* address of registers in physical memory */
+struct s5p_serial_platdata {
+   struct s5p_uart *reg;  /* address of registers in physical memory */
u8 port_id; /* uart port number */
-   u8 enabled; /* 1 if enabled, 0 if disabled */
-} config __attribute__ ((section(".data")));
-
-static inline struct s5p_uart *s5p_get_base_uart(int dev_index)
-{
-#ifdef CONFIG_OF_CONTROL
-   return (struct s5p_uart *)(config.base_addr);
-#else
-   u32 offset = dev_index * sizeof(struct s5p_uart);
-   return (struct s5p_uart *)(samsung_get_base_uart() + offset);
-#endif
-}
+};
 
 /*
  * The coefficient, used to calculate the baudrate on S5P UARTs is
@@ -65,23 +59,13 @@ static const int udivslot[] = {
0xffdf,
 };
 
-static void serial_setbrg_dev(const int dev_index)
+int s5p_serial_setbrg(struct udevice *dev, int baudrate)
 {
-   struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
-   u32 uclk = get_uart_clk(dev_index);
-   u32 baudrate = gd->baudrate;
+   struct s5p_serial_platdata *plat = dev->platdata;
+   struct s5p_uart *const uart = plat->reg;
+   u32 uclk = get_uart_clk(plat->port_id);
u32 val;
 
-#if defined(CONFIG_SILENT_CONSOLE) && \
-   defined(CONFIG_OF_CONTROL) && \
-   !defined(CONFIG_SPL_BUILD)
-   if (fdtdec_get_config_int(gd->fdt_blob, "silent_console", 0))
-   gd->flags |= GD_FLG_SILENT;
-#endif
-
-   if (!config.enabled)
-   return;
-
val = uclk / baudrate;
 
writel(val / 16 - 1, &uart->ubrdiv);
@@ -90,15 +74,14 @@ static void serial_setbrg_dev(const int dev_index)
writew(udivslot[val % 16], &uart->rest.slot);
else
writeb(val % 16, &uart->rest.value);
+
+   return 0;
 }
 
-/*
- * Initialise the serial port with the given baudrate. The settings
- * are always 8 data bits, no parity, 1 stop bit, no start bits.
- */
-static int serial_init_dev(const int dev_index)
+static int s5p_serial_probe(struct udevice *dev)
 {
-   struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
+   struct s5p_serial_platdata *plat = dev->platdata;
+   struct s5p_uart *const uart = plat->reg;
 
/* enable FIFOs, auto clear Rx FIFO */
writel(0x3, &uart->ufcon);
@@ -108,14 +91,11 @@ static int serial_init_dev(const int dev_index)
/* No interrupts, no DMA, pure polling */
writel(0x245, &uart->ucon);
 
-   serial_setbrg_dev(dev_index);
-
return 0;
 }
 
-static int serial_err_check(const int dev_index, int op)
+static int serial_err_check(const struct s5p_uart *const uart, int op)
 {
-   struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
unsigned int mask;
 
/*
@@ -133,169 +113,78 @@ static int serial_err_check(const int dev_index, int op)
return readl(&uart->uerstat) & mask;
 }
 
-/*
- * Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
- * written into its argument c.
- */
-static int serial_getc_dev(const int dev_index)
+static int s5p_serial_getc(struct udevice *dev)
 {
-   struct s5p_uart *const uart = s5p_get_base_uart(dev_index);
-
-   if (!config.enabled)
-   return 0;
+   struct s5p_serial_platdata *plat = dev->platdata;
+   struct s5p_uart *const uart = plat->reg;
 
-   /* wait for character to arrive */
-   while (!(readl(&uart->ufstat) & (RX_FIFO_COUNT_MASK |
-RX_FIFO_FULL_MASK))) {
-   if (serial_err_check(dev_index, 0))
-   return 0;
-   }
+   if (!(readl(&uart->ufstat) & RX_FIFO_COUNT_MASK))
+   return -EAGAIN;
 
+   serial_err_c

[U-Boot] [PATCH v5 03/14] dm: Adjust lists_bind_fdt() to return the bound device

[Simon Glass]

Allow the caller to find out the device that was bound in response to this
call.

Signed-off-by: Simon Glass 
---

Changes in v5: None
Changes in v4: None
Changes in v3:
- Add new change to enhance lists_bind_fdt()

Changes in v2: None

 drivers/core/lists.c | 10 +++---
 drivers/core/root.c  |  2 +-
 include/dm/lists.h   |  6 +-
 3 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/drivers/core/lists.c b/drivers/core/lists.c
index 0f08bfd..699f94b 100644
--- a/drivers/core/lists.c
+++ b/drivers/core/lists.c
@@ -118,7 +118,8 @@ static int driver_check_compatible(const void *blob, int 
offset,
return -ENOENT;
 }
 
-int lists_bind_fdt(struct udevice *parent, const void *blob, int offset)
+int lists_bind_fdt(struct udevice *parent, const void *blob, int offset,
+  struct udevice **devp)
 {
struct driver *driver = ll_entry_start(struct driver, driver);
const int n_ents = ll_entry_count(struct driver, driver);
@@ -130,6 +131,8 @@ int lists_bind_fdt(struct udevice *parent, const void 
*blob, int offset)
int ret = 0;
 
dm_dbg("bind node %s\n", fdt_get_name(blob, offset, NULL));
+   if (devp)
+   *devp = NULL;
for (entry = driver; entry != driver + n_ents; entry++) {
ret = driver_check_compatible(blob, offset, entry->of_match);
name = fdt_get_name(blob, offset, NULL);
@@ -149,10 +152,11 @@ int lists_bind_fdt(struct udevice *parent, const void 
*blob, int offset)
ret = device_bind(parent, entry, name, NULL, offset, &dev);
if (ret) {
dm_warn("Error binding driver '%s'\n", entry->name);
-   if (!result || ret != -ENOENT)
-   result = ret;
+   return ret;
} else {
found = true;
+   if (devp)
+   *devp = dev;
}
break;
}
diff --git a/drivers/core/root.c b/drivers/core/root.c
index 393dd98..a328a48 100644
--- a/drivers/core/root.c
+++ b/drivers/core/root.c
@@ -91,7 +91,7 @@ int dm_scan_fdt_node(struct udevice *parent, const void 
*blob, int offset,
if (pre_reloc_only &&
!fdt_getprop(blob, offset, "u-boot,dm-pre-reloc", NULL))
continue;
-   err = lists_bind_fdt(parent, blob, offset);
+   err = lists_bind_fdt(parent, blob, offset, NULL);
if (err && !ret)
ret = err;
}
diff --git a/include/dm/lists.h b/include/dm/lists.h
index 87a3af5..2356895 100644
--- a/include/dm/lists.h
+++ b/include/dm/lists.h
@@ -53,7 +53,11 @@ int lists_bind_drivers(struct udevice *parent, bool 
pre_reloc_only);
  * @parent: parent driver (root)
  * @blob: device tree blob
  * @offset: offset of this device tree node
+ * @devp: if non-NULL, returns a pointer to the bound device
+ * @return 0 if device was bound, -EINVAL if the device tree is invalid,
+ * other -ve value on error
  */
-int lists_bind_fdt(struct udevice *parent, const void *blob, int offset);
+int lists_bind_fdt(struct udevice *parent, const void *blob, int offset,
+  struct udevice **devp);
 
 #endif
-- 
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[U-Boot] [PATCH v5 11/14] dm: serial: Collect common baud rate code in ns16550

[Simon Glass]

The same sequence is used in several places, so move it into a function.
Note that UART_LCR_BKSE is an alias for UART_LCR_DLAB.

Signed-off-by: Simon Glass 
---

Changes in v5: None
Changes in v4: None
Changes in v3:
- Add new patch to collect common baud rate code in ns16550

Changes in v2: None

 drivers/serial/ns16550.c | 33 +
 1 file changed, 13 insertions(+), 20 deletions(-)

diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 3f5f4ef..d54eba6 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -61,6 +61,14 @@ int ns16550_calc_divisor(NS16550_t port, int clock, int 
baudrate)
return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate);
 }
 
+static void NS16550_setbrg(NS16550_t com_port, int baud_divisor)
+{
+   serial_out(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr);
+   serial_out(baud_divisor & 0xff, &com_port->dll);
+   serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm);
+   serial_out(UART_LCRVAL, &com_port->lcr);
+}
+
 void NS16550_init(NS16550_t com_port, int baud_divisor)
 {
 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_OMAP34XX))
@@ -71,10 +79,7 @@ void NS16550_init(NS16550_t com_port, int baud_divisor)
 */
if ((serial_in(&com_port->lsr) & (UART_LSR_TEMT | UART_LSR_THRE))
 == UART_LSR_THRE) {
-   serial_out(UART_LCR_DLAB, &com_port->lcr);
-   serial_out(baud_divisor & 0xff, &com_port->dll);
-   serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm);
-   serial_out(UART_LCRVAL, &com_port->lcr);
+   NS16550_setbrg(com_port, baud_divisor);
serial_out(0, &com_port->mdr1);
}
 #endif
@@ -87,16 +92,10 @@ void NS16550_init(NS16550_t com_port, int baud_divisor)
defined(CONFIG_TI81XX) || defined(CONFIG_AM43XX)
serial_out(0x7, &com_port->mdr1);   /* mode select reset TL16C750*/
 #endif
-   serial_out(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr);
-   serial_out(0, &com_port->dll);
-   serial_out(0, &com_port->dlm);
-   serial_out(UART_LCRVAL, &com_port->lcr);
+   NS16550_setbrg(com_port, 0);
serial_out(UART_MCRVAL, &com_port->mcr);
serial_out(UART_FCRVAL, &com_port->fcr);
-   serial_out(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr);
-   serial_out(baud_divisor & 0xff, &com_port->dll);
-   serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm);
-   serial_out(UART_LCRVAL, &com_port->lcr);
+   NS16550_setbrg(com_port, baud_divisor);
 #if defined(CONFIG_OMAP) || \
defined(CONFIG_AM33XX) || defined(CONFIG_SOC_DA8XX) || \
defined(CONFIG_TI81XX) || defined(CONFIG_AM43XX)
@@ -113,16 +112,10 @@ void NS16550_init(NS16550_t com_port, int baud_divisor)
 void NS16550_reinit(NS16550_t com_port, int baud_divisor)
 {
serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
-   serial_out(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr);
-   serial_out(0, &com_port->dll);
-   serial_out(0, &com_port->dlm);
-   serial_out(UART_LCRVAL, &com_port->lcr);
+   NS16550_setbrg(com_port, 0);
serial_out(UART_MCRVAL, &com_port->mcr);
serial_out(UART_FCRVAL, &com_port->fcr);
-   serial_out(UART_LCR_BKSE, &com_port->lcr);
-   serial_out(baud_divisor & 0xff, &com_port->dll);
-   serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm);
-   serial_out(UART_LCRVAL, &com_port->lcr);
+   NS16550_setbrg(com_port, baud_divisor);
 }
 #endif /* CONFIG_NS16550_MIN_FUNCTIONS */
 
-- 
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[U-Boot] [PATCH v5 07/14] sandbox: dts: Add a serial console node

[Simon Glass]

If the sandbox device tree is provided to U-Boot (with the -d flag) then it
will use the device tree version in preference to the built-in device. The
only difference is the colour.

Signed-off-by: Simon Glass 
---

Changes in v5:
- Use /chosen/stdout-path instead of /aliases/console to specify the console

Changes in v4:
- Add a binding for sandbox serial
- Remove pre-reloc fdt property

Changes in v3:
- Change pre-reloc fdt property to 'u-boot,dm-pre-reloc'

Changes in v2: None

 arch/sandbox/dts/sandbox.dts   | 10 ++
 doc/device-tree-bindings/serial/sandbox-serial.txt | 13 +
 2 files changed, 23 insertions(+)
 create mode 100644 doc/device-tree-bindings/serial/sandbox-serial.txt

diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts
index efffacb..797478a 100644
--- a/arch/sandbox/dts/sandbox.dts
+++ b/arch/sandbox/dts/sandbox.dts
@@ -1,6 +1,16 @@
 /dts-v1/;
 
 / {
+   chosen {
+   stdout-path = "/serial";
+   };
+
+   /* Needs to be available prior to relocation */
+   uart0: serial {
+   compatible = "sandbox,serial";
+   sandbox,text-colour = "cyan";
+   };
+
triangle {
compatible = "demo-shape";
colour = "cyan";
diff --git a/doc/device-tree-bindings/serial/sandbox-serial.txt 
b/doc/device-tree-bindings/serial/sandbox-serial.txt
new file mode 100644
index 000..f429c90
--- /dev/null
+++ b/doc/device-tree-bindings/serial/sandbox-serial.txt
@@ -0,0 +1,13 @@
+Sandbox serial
+
+The sandbox serial device is an emulated device which displays its output
+on the host machine's console, and accepts input from its keyboard.
+
+Required properties:
+  compatible: "sandbox,serial"
+
+Optional properties:
+  sandbox,text-colour: If present, this is the colour of the console text.
+Supported values are:
+"black", "red", "green", "yellow", "blue", "megenta", "cyan",
+"white"
-- 
2.1.0.rc2.206.gedb03e5

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[U-Boot] [PATCH v5 08/14] dm: exynos: Mark exynos5 console as pre-reloc

[Simon Glass]

We will need the console before relocation, so mark it that way.

Signed-off-by: Simon Glass 
---

Changes in v5: None
Changes in v4: None
Changes in v3:
- Change pre-reloc fdt property to 'u-boot,dm-pre-reloc'

Changes in v2: None

 arch/arm/dts/exynos5.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/dts/exynos5.dtsi b/arch/arm/dts/exynos5.dtsi
index dc5405b..e539068 100644
--- a/arch/arm/dts/exynos5.dtsi
+++ b/arch/arm/dts/exynos5.dtsi
@@ -244,6 +244,7 @@
compatible = "samsung,exynos4210-uart";
reg = <0x12C3 0x100>;
interrupts = <0 54 0>;
+   u-boot,dm-pre-reloc;
id = <3>;
};
 
-- 
2.1.0.rc2.206.gedb03e5

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[U-Boot] [PATCH v5 12/14] dm: serial: Add driver model support for ns16550

[Simon Glass]

Add driver model support so that ns16550 can support operation both with
and without driver model.

The driver needs a clock frequency so cannot stand alone unfortunately. The
clock frequency must be provided by a separate driver.

Signed-off-by: Simon Glass 
---

Changes in v5:
- Add struct udevice declaration

Changes in v4:
- Remove clock frequency setup for ns16550 driver

Changes in v3:
- Add new patch to support driver model in ns16550

Changes in v2: None

 doc/device-tree-bindings/serial/ns16550.txt |  10 ++
 drivers/serial/Makefile |   2 +-
 drivers/serial/ns16550.c| 156 +++-
 include/ns16550.h   |  53 ++
 4 files changed, 218 insertions(+), 3 deletions(-)
 create mode 100644 doc/device-tree-bindings/serial/ns16550.txt

diff --git a/doc/device-tree-bindings/serial/ns16550.txt 
b/doc/device-tree-bindings/serial/ns16550.txt
new file mode 100644
index 000..ef0b9ae
--- /dev/null
+++ b/doc/device-tree-bindings/serial/ns16550.txt
@@ -0,0 +1,10 @@
+NS16550 UART
+
+This UART driver supports many chip variants and is used in mamy SoCs.
+
+Required properties:
+- compatible: "ns16550" or "nvidia,tegra20-uart"
+- reg: start address and size of registers
+- reg-shift: shift value indicating register size: 0=byte, 1=16bit,2=32bit etc.
+- clock-frequency: input clock frequency for the UART (used to calculate the
+baud rate divisor)
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 4720e1d..5ae6416 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -9,6 +9,7 @@ ifdef CONFIG_DM_SERIAL
 obj-y += serial-uclass.o
 else
 obj-y += serial.o
+obj-$(CONFIG_SYS_NS16550_SERIAL) += serial_ns16550.o
 endif
 
 obj-$(CONFIG_ALTERA_UART) += altera_uart.o
@@ -20,7 +21,6 @@ obj-$(CONFIG_MCFUART) += mcfuart.o
 obj-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o
 obj-$(CONFIG_SYS_NS16550) += ns16550.o
 obj-$(CONFIG_S5P) += serial_s5p.o
-obj-$(CONFIG_SYS_NS16550_SERIAL) += serial_ns16550.o
 obj-$(CONFIG_IMX_SERIAL) += serial_imx.o
 obj-$(CONFIG_KS8695_SERIAL) += serial_ks8695.o
 obj-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index d54eba6..63a9ef6 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -5,17 +5,25 @@
  */
 
 #include 
+#include 
+#include 
+#include 
 #include 
+#include 
 #include 
 #include 
 #include 
 
+DECLARE_GLOBAL_DATA_PTR;
+
 #define UART_LCRVAL UART_LCR_8N1   /* 8 data, 1 stop, no parity */
 #define UART_MCRVAL (UART_MCR_DTR | \
 UART_MCR_RTS)  /* RTS/DTR */
 #define UART_FCRVAL (UART_FCR_FIFO_EN |\
 UART_FCR_RXSR |\
 UART_FCR_TXSR) /* Clear & enable FIFOs */
+
+#ifndef CONFIG_DM_SERIAL
 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
 #define serial_out(x, y)   outb(x, (ulong)y)
 #define serial_in(y)   inb((ulong)y)
@@ -29,6 +37,7 @@
 #define serial_out(x, y)   writeb(x, y)
 #define serial_in(y)   readb(y)
 #endif
+#endif /* !CONFIG_DM_SERIAL */
 
 #if defined(CONFIG_SOC_KEYSTONE)
 #define UART_REG_VAL_PWREMU_MGMT_UART_DISABLE   0
@@ -45,6 +54,58 @@
 #define CONFIG_SYS_NS16550_IER  0x00
 #endif /* CONFIG_SYS_NS16550_IER */
 
+#ifdef CONFIG_DM_SERIAL
+static void ns16550_writeb(NS16550_t port, int offset, int value)
+{
+   struct ns16550_platdata *plat = port->plat;
+   unsigned char *addr;
+
+   offset *= 1 << plat->reg_shift;
+   addr = plat->base + offset;
+   /*
+* As far as we know it doesn't make sense to support selection of
+* these options at run-time, so use the existing CONFIG options.
+*/
+#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
+   outb(value, addr);
+#elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_SYS_BIG_ENDIAN)
+   out_le32(addr, value);
+#elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN)
+   out_be32(addr, value);
+#elif defined(CONFIG_SYS_BIG_ENDIAN)
+   writeb(value, addr + (1 << plat->reg_shift) - 1);
+#else
+   writeb(value, addr);
+#endif
+}
+
+static int ns16550_readb(NS16550_t port, int offset)
+{
+   struct ns16550_platdata *plat = port->plat;
+   unsigned char *addr;
+
+   offset *= 1 << plat->reg_shift;
+   addr = plat->base + offset;
+#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
+   return inb(addr);
+#elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_SYS_BIG_ENDIAN)
+   return in_le32(addr);
+#elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN)
+   return in_be32(addr);
+#elif defined(CONFIG_SYS_BIG_ENDIAN)
+   return readb(addr + (1 << plat->reg_shift) - 1);
+#else
+   return readb(addr);
+#endif
+}
+
+/* We can clean these up once everything is moved to driver model */
+#define serial_out(value, addr)\
+   ns16550_writeb(com_port, addr - (unsigned char *)com_port, value)
+#de

[U-Boot] [PATCH v5 13/14] tegra: dts: Add serial port details

[Simon Glass]

Some Tegra device tree files do not include information about the serial
ports. Add this and also add information about the input clock speed.

The console alias needs to be set up to indicate which port is used for
the console.

Also add a binding file since this is missing.

Series-changes; 5
- Add full serial port nodes from Linux tree (commit fc9d4dbe)
- Use /chosen/stdout-path instead of /aliases/console to specify the console

Signed-off-by: Simon Glass 
---

Changes in v5: None
Changes in v4:
- Remove 'clock-frequency' property from serial nodes

Changes in v3:
- Add new patch for tegra serial port details

Changes in v2: None

 arch/arm/dts/tegra114-dalmore.dts |   4 +
 arch/arm/dts/tegra114.dtsi|  53 +
 arch/arm/dts/tegra124-jetson-tk1.dts  |   4 +
 arch/arm/dts/tegra124-venice2.dts |   4 +
 arch/arm/dts/tegra124.dtsi|  66 ++
 arch/arm/dts/tegra20-colibri_t20_iris.dts |   4 +
 arch/arm/dts/tegra20-harmony.dts  |   4 +
 arch/arm/dts/tegra20-medcom-wide.dts  |   4 +
 arch/arm/dts/tegra20-paz00.dts|   4 +
 arch/arm/dts/tegra20-plutux.dts   |   4 +
 arch/arm/dts/tegra20-seaboard.dts |   4 +
 arch/arm/dts/tegra20-tec.dts  |   4 +
 arch/arm/dts/tegra20-trimslice.dts|   4 +
 arch/arm/dts/tegra20-ventana.dts  |   4 +
 arch/arm/dts/tegra20-whistler.dts |   4 +
 arch/arm/dts/tegra20.dtsi |  51 -
 arch/arm/dts/tegra30-beaver.dts   |   4 +
 arch/arm/dts/tegra30-cardhu.dts   |   4 +
 arch/arm/dts/tegra30-tamonten.dtsi|   4 +
 arch/arm/dts/tegra30.dtsi |  66 ++
 include/dt-bindings/clock/tegra114-car.h  | 342 ++
 include/dt-bindings/clock/tegra124-car.h  | 342 ++
 include/dt-bindings/clock/tegra20-car.h   | 158 ++
 include/dt-bindings/clock/tegra30-car.h   | 273 
 24 files changed, 1405 insertions(+), 10 deletions(-)
 create mode 100644 include/dt-bindings/clock/tegra114-car.h
 create mode 100644 include/dt-bindings/clock/tegra124-car.h
 create mode 100644 include/dt-bindings/clock/tegra20-car.h
 create mode 100644 include/dt-bindings/clock/tegra30-car.h

diff --git a/arch/arm/dts/tegra114-dalmore.dts 
b/arch/arm/dts/tegra114-dalmore.dts
index 435c01e..81ad212 100644
--- a/arch/arm/dts/tegra114-dalmore.dts
+++ b/arch/arm/dts/tegra114-dalmore.dts
@@ -6,6 +6,10 @@
model = "NVIDIA Dalmore";
compatible = "nvidia,dalmore", "nvidia,tegra114";
 
+   chosen {
+   stdout-path = &uartd;
+   };
+
aliases {
i2c0 = "/i2c@7000d000";
i2c1 = "/i2c@7000c000";
diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi
index 59434e0..88bdc49 100644
--- a/arch/arm/dts/tegra114.dtsi
+++ b/arch/arm/dts/tegra114.dtsi
@@ -1,3 +1,4 @@
+#include 
 #include 
 #include 
 
@@ -116,6 +117,58 @@
status = "disabled";
};
 
+   uarta: serial@70006000 {
+   compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
+   reg = <0x70006000 0x40>;
+   reg-shift = <2>;
+   interrupts = ;
+   clocks = <&tegra_car TEGRA114_CLK_UARTA>;
+   resets = <&tegra_car 6>;
+   reset-names = "serial";
+   dmas = <&apbdma 8>, <&apbdma 8>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   };
+
+   uartb: serial@70006040 {
+   compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
+   reg = <0x70006040 0x40>;
+   reg-shift = <2>;
+   interrupts = ;
+   clocks = <&tegra_car TEGRA114_CLK_UARTB>;
+   resets = <&tegra_car 7>;
+   reset-names = "serial";
+   dmas = <&apbdma 9>, <&apbdma 9>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   };
+
+   uartc: serial@70006200 {
+   compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
+   reg = <0x70006200 0x100>;
+   reg-shift = <2>;
+   interrupts = ;
+   clocks = <&tegra_car TEGRA114_CLK_UARTC>;
+   resets = <&tegra_car 55>;
+   reset-names = "serial";
+   dmas = <&apbdma 10>, <&apbdma 10>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+   };
+
+   uartd: serial@70006300 {
+   compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
+   reg = <0x70006300 0x100>;
+   reg-shift = <2>;
+   interrupts = ;
+   clocks = <&tegra_car TEGRA114_CLK_UARTD>;
+   resets = <&tegra_car 65>;
+   reset-names = "serial";
+   dmas = <&apbdma 19>, <&apbdma 19>;
+   dma-names = "rx", "tx";
+   status = "disabled";
+

[U-Boot] [PATCH v5 10/14] dm: serial: Move baud rate calculation to ns16550.c

[Simon Glass]

Move the function that calculates the baud rate divisor into ns16550.c so
it can be used by that file.

Signed-off-by: Simon Glass 
---

Changes in v5: None
Changes in v4: None
Changes in v3:
- Add new patch to move baud rate calculation to ns16550.c

Changes in v2: None

 drivers/serial/ns16550.c| 18 +-
 drivers/serial/serial_ns16550.c | 14 --
 include/ns16550.h   | 13 +
 3 files changed, 34 insertions(+), 11 deletions(-)

diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 079f67d..3f5f4ef 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -4,7 +4,7 @@
  * modified to use CONFIG_SYS_ISA_MEM and new defines
  */
 
-#include 
+#include 
 #include 
 #include 
 #include 
@@ -45,6 +45,22 @@
 #define CONFIG_SYS_NS16550_IER  0x00
 #endif /* CONFIG_SYS_NS16550_IER */
 
+int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate)
+{
+   const unsigned int mode_x_div = 16;
+
+#ifdef CONFIG_OMAP1510
+   /* If can't cleanly clock 115200 set div to 1 */
+   if ((clock == 1200) && (baudrate == 115200)) {
+   port->osc_12m_sel = OSC_12M_SEL;  /* enable 6.5 * divisor */
+   return 1;   /* return 1 for base divisor */
+   }
+   port->osc_12m_sel = 0;  /* clear if previsouly set */
+#endif
+
+   return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate);
+}
+
 void NS16550_init(NS16550_t com_port, int baud_divisor)
 {
 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_OMAP34XX))
diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c
index dafeed7..632da4c 100644
--- a/drivers/serial/serial_ns16550.c
+++ b/drivers/serial/serial_ns16550.c
@@ -81,7 +81,8 @@ static NS16550_t serial_ports[6] = {
static int  eserial##port##_init(void) \
{ \
int clock_divisor; \
-   clock_divisor = calc_divisor(serial_ports[port-1]); \
+   clock_divisor = ns16550_calc_divisor(serial_ports[port-1], \
+   CONFIG_SYS_NS16550_CLK, gd->baudrate); \
NS16550_init(serial_ports[port-1], clock_divisor); \
return 0 ; \
} \
@@ -118,14 +119,6 @@ static NS16550_t serial_ports[6] = {
.puts   = eserial##port##_puts, \
 }
 
-static int calc_divisor (NS16550_t port)
-{
-   const unsigned int mode_x_div = 16;
-
-   return DIV_ROUND_CLOSEST(CONFIG_SYS_NS16550_CLK,
-   mode_x_div * gd->baudrate);
-}
-
 void
 _serial_putc(const char c,const int port)
 {
@@ -167,7 +160,8 @@ _serial_setbrg (const int port)
 {
int clock_divisor;
 
-   clock_divisor = calc_divisor(PORT);
+   clock_divisor = ns16550_calc_divisor(PORT, CONFIG_SYS_NS16550_CLK,
+gd->baudrate);
NS16550_reinit(PORT, clock_divisor);
 }
 
diff --git a/include/ns16550.h b/include/ns16550.h
index d1f3a90..d93e28e 100644
--- a/include/ns16550.h
+++ b/include/ns16550.h
@@ -170,3 +170,16 @@ void NS16550_putc(NS16550_t com_port, char c);
 char NS16550_getc(NS16550_t com_port);
 int NS16550_tstc(NS16550_t com_port);
 void NS16550_reinit(NS16550_t com_port, int baud_divisor);
+
+/**
+ * ns16550_calc_divisor() - calculate the divisor given clock and baud rate
+ *
+ * Given the UART input clock and required baudrate, calculate the divisor
+ * that should be used.
+ *
+ * @port:  UART port
+ * @clock: UART input clock speed in Hz
+ * @baudrate:  Required baud rate
+ * @return baud rate divisor that should be used
+ */
+int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate);
-- 
2.1.0.rc2.206.gedb03e5

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[U-Boot] [PATCH v5 04/14] dm: Add a uclass for serial devices

[Simon Glass]

Serial devices support simple byte input/output and a few operations to find
out whether data is available. Add a basic uclass for serial devices to be
used by drivers that are converted to driver model.

Signed-off-by: Simon Glass 
---

Changes in v5:
- Use /chosen/stdout-path instead of /aliases/console to specify the console

Changes in v4: None
Changes in v3:
- Automatically bind the console even if not marked for pre-relocation

Changes in v2:
- Rename struct device to struct udevice

 drivers/serial/Makefile|   4 +
 drivers/serial/serial-uclass.c | 214 +
 include/dm/uclass-id.h |   1 +
 include/serial.h   |  92 ++
 4 files changed, 311 insertions(+)
 create mode 100644 drivers/serial/serial-uclass.c

diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 571c18f..4720e1d 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -5,7 +5,11 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
+ifdef CONFIG_DM_SERIAL
+obj-y += serial-uclass.o
+else
 obj-y += serial.o
+endif
 
 obj-$(CONFIG_ALTERA_UART) += altera_uart.o
 obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
new file mode 100644
index 000..cb491a8
--- /dev/null
+++ b/drivers/serial/serial-uclass.c
@@ -0,0 +1,214 @@
+/*
+ * Copyright (c) 2014 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* The currently-selected console serial device */
+struct udevice *cur_dev __attribute__ ((section(".data")));
+
+#ifndef CONFIG_SYS_MALLOC_F_LEN
+#error "Serial is required before relocation - define CONFIG_SYS_MALLOC_F_LEN 
to make this work"
+#endif
+
+static void serial_find_console_or_panic(void)
+{
+   int node;
+
+   /* Check for a chosen console */
+   node = fdtdec_get_chosen_node(gd->fdt_blob, "stdout-path");
+   if (!uclass_get_device_by_of_offset(UCLASS_SERIAL, node, &cur_dev))
+   return;
+   node = fdtdec_get_alias_node(gd->fdt_blob, "console");
+   if (!uclass_get_device_by_of_offset(UCLASS_SERIAL, node, &cur_dev))
+   return;
+
+   /*
+* If the console is not marked to be bound before relocation, bind
+* it anyway.
+*/
+   if (node > 0 &&
+   !lists_bind_fdt(gd->dm_root, gd->fdt_blob, node, &cur_dev)) {
+   if (!device_probe(cur_dev))
+   return;
+   cur_dev = NULL;
+   }
+
+   /*
+* Failing that, get the device with sequence number 0, or in extremis
+* just the first serial device we can find. But we insist on having
+* a console (even if it is silent).
+*/
+   if (uclass_get_device_by_seq(UCLASS_SERIAL, 0, &cur_dev) &&
+   (uclass_first_device(UCLASS_SERIAL, &cur_dev) || !cur_dev))
+   panic("No serial driver found");
+}
+
+/* Called prior to relocation */
+int serial_init(void)
+{
+   serial_find_console_or_panic();
+   gd->flags |= GD_FLG_SERIAL_READY;
+
+   return 0;
+}
+
+/* Called after relocation */
+void serial_initialize(void)
+{
+   serial_find_console_or_panic();
+}
+
+void serial_putc(char ch)
+{
+   struct dm_serial_ops *ops = serial_get_ops(cur_dev);
+   int err;
+
+   do {
+   err = ops->putc(cur_dev, ch);
+   } while (err == -EAGAIN);
+   if (ch == '\n')
+   serial_putc('\r');
+}
+
+void serial_setbrg(void)
+{
+   struct dm_serial_ops *ops = serial_get_ops(cur_dev);
+
+   if (ops->setbrg)
+   ops->setbrg(cur_dev, gd->baudrate);
+}
+
+void serial_puts(const char *str)
+{
+   while (*str)
+   serial_putc(*str++);
+}
+
+int serial_tstc(void)
+{
+   struct dm_serial_ops *ops = serial_get_ops(cur_dev);
+
+   if (ops->pending)
+   return ops->pending(cur_dev, true);
+
+   return 1;
+}
+
+int serial_getc(void)
+{
+   struct dm_serial_ops *ops = serial_get_ops(cur_dev);
+   int err;
+
+   do {
+   err = ops->getc(cur_dev);
+   } while (err == -EAGAIN);
+
+   return err >= 0 ? err : 0;
+}
+
+void serial_stdio_init(void)
+{
+}
+
+void serial_stub_putc(struct stdio_dev *sdev, const char ch)
+{
+   struct udevice *dev = sdev->priv;
+   struct dm_serial_ops *ops = serial_get_ops(dev);
+
+   ops->putc(dev, ch);
+}
+
+void serial_stub_puts(struct stdio_dev *sdev, const char *str)
+{
+   while (*str)
+   serial_stub_putc(sdev, *str++);
+}
+
+int serial_stub_getc(struct stdio_dev *sdev)
+{
+   struct udevice *dev = sdev->priv;
+   struct dm_serial_ops *ops = serial_get_ops(dev);
+
+   int err;
+
+   do {
+   err = ops->getc(dev);
+   } while (err == -EAGAIN);
+
+   return err >= 0 ? err : 0;
+}

[U-Boot] [PATCH v5 06/14] sandbox: serial: Support a coloured console

[Simon Glass]

The current sandbox serial driver is a pretty trivial example and does not
have the featues that might be needed for other board serial drivers. To
help provide a better example, add a text colour property to the device
tree for sandbox. This uses platform data, a device tree node, driver
private data and a remove() method.

Signed-off-by: Simon Glass 
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Rename struct device to struct udevice

 drivers/serial/sandbox.c | 83 
 1 file changed, 83 insertions(+)

diff --git a/drivers/serial/sandbox.c b/drivers/serial/sandbox.c
index ac54e01..cd2f91e 100644
--- a/drivers/serial/sandbox.c
+++ b/drivers/serial/sandbox.c
@@ -34,19 +34,67 @@ static char serial_buf[16];
 static unsigned int serial_buf_write;
 static unsigned int serial_buf_read;
 
+struct sandbox_serial_platdata {
+   int colour; /* Text colour to use for output, -1 for none */
+};
+
+struct sandbox_serial_priv {
+   bool start_of_line;
+};
+
+/**
+ * output_ansi_colour() - Output an ANSI colour code
+ *
+ * @colour: Colour to output (0-7)
+ */
+static void output_ansi_colour(int colour)
+{
+   char ansi_code[] = "\x1b[1;3Xm";
+
+   ansi_code[5] = '0' + colour;
+   os_write(1, ansi_code, sizeof(ansi_code) - 1);
+}
+
+static void output_ansi_reset(void)
+{
+   os_write(1, "\x1b[0m", 4);
+}
+
 static int sandbox_serial_probe(struct udevice *dev)
 {
struct sandbox_state *state = state_get_current();
+   struct sandbox_serial_priv *priv = dev_get_priv(dev);
 
if (state->term_raw != STATE_TERM_COOKED)
os_tty_raw(0, state->term_raw == STATE_TERM_RAW_WITH_SIGS);
+   priv->start_of_line = 0;
+
+   return 0;
+}
+
+static int sandbox_serial_remove(struct udevice *dev)
+{
+   struct sandbox_serial_platdata *plat = dev->platdata;
+
+   if (plat->colour != -1)
+   output_ansi_reset();
 
return 0;
 }
 
 static int sandbox_serial_putc(struct udevice *dev, const char ch)
 {
+   struct sandbox_serial_priv *priv = dev_get_priv(dev);
+   struct sandbox_serial_platdata *plat = dev->platdata;
+
+   if (priv->start_of_line && plat->colour != -1) {
+   priv->start_of_line = false;
+   output_ansi_colour(plat->colour);
+   }
+
os_write(1, &ch, 1);
+   if (ch == '\n')
+   priv->start_of_line = true;
 
return 0;
 }
@@ -91,6 +139,32 @@ static int sandbox_serial_getc(struct udevice *dev)
return result;
 }
 
+static const char * const ansi_colour[] = {
+   "black", "red", "green", "yellow", "blue", "megenta", "cyan",
+   "white",
+};
+
+static int sandbox_serial_ofdata_to_platdata(struct udevice *dev)
+{
+   struct sandbox_serial_platdata *plat = dev->platdata;
+   const char *colour;
+   int i;
+
+   plat->colour = -1;
+   colour = fdt_getprop(gd->fdt_blob, dev->of_offset,
+"sandbox,text-colour", NULL);
+   if (colour) {
+   for (i = 0; i < ARRAY_SIZE(ansi_colour); i++) {
+   if (!strcmp(colour, ansi_colour[i])) {
+   plat->colour = i;
+   break;
+   }
+   }
+   }
+
+   return 0;
+}
+
 static const struct dm_serial_ops sandbox_serial_ops = {
.putc = sandbox_serial_putc,
.pending = sandbox_serial_pending,
@@ -106,11 +180,20 @@ U_BOOT_DRIVER(serial_sandbox) = {
.name   = "serial_sandbox",
.id = UCLASS_SERIAL,
.of_match = sandbox_serial_ids,
+   .ofdata_to_platdata = sandbox_serial_ofdata_to_platdata,
+   .platdata_auto_alloc_size = sizeof(struct sandbox_serial_platdata),
+   .priv_auto_alloc_size = sizeof(struct sandbox_serial_priv),
.probe = sandbox_serial_probe,
+   .remove = sandbox_serial_remove,
.ops= &sandbox_serial_ops,
.flags = DM_FLAG_PRE_RELOC,
 };
 
+static const struct sandbox_serial_platdata platdata_non_fdt = {
+   .colour = -1,
+};
+
 U_BOOT_DEVICE(serial_sandbox_non_fdt) = {
.name = "serial_sandbox",
+   .platdata = &platdata_non_fdt,
 };
-- 
2.1.0.rc2.206.gedb03e5

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[U-Boot] [PATCH v5 14/14] dm: tegra: Enable driver model for serial

[Simon Glass]

Use driver model for serial ports.

Since Tegra now uses driver model for serial, adjust the definition of
V_NS16550_CLK so that it is clear that this is only used for SPL.

Signed-off-by: Simon Glass 
---

Changes in v5: None
Changes in v4:
- Add a separate Tegra serial driver to deal with the clock issue
- Add new CONFIG_TEGRA_SERIAL option to enable dm driver
- Use hard-coded UART clock from Tegra configuration

Changes in v3:
- Add new patch to enable driver model for serial on tegra
- Add new patch to use V_NS16550_CLK only in SPL builds

Changes in v2: None

 drivers/serial/Makefile|  1 +
 drivers/serial/serial_tegra.c  | 38 ++
 include/configs/tegra-common.h |  9 -
 3 files changed, 47 insertions(+), 1 deletion(-)
 create mode 100644 drivers/serial/serial_tegra.c

diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 5ae6416..853a8c6 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_BFIN_SERIAL) += serial_bfin.o
 obj-$(CONFIG_FSL_LPUART) += serial_lpuart.o
 obj-$(CONFIG_MXS_AUART) += mxs_auart.o
 obj-$(CONFIG_ARC_SERIAL) += serial_arc.o
+obj-$(CONFIG_TEGRA_SERIAL) += serial_tegra.o
 
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_USB_TTY) += usbtty.o
diff --git a/drivers/serial/serial_tegra.c b/drivers/serial/serial_tegra.c
new file mode 100644
index 000..7eb70e1
--- /dev/null
+++ b/drivers/serial/serial_tegra.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+static const struct udevice_id tegra_serial_ids[] = {
+   { .compatible = "nvidia,tegra20-uart" },
+   { }
+};
+
+static int tegra_serial_ofdata_to_platdata(struct udevice *dev)
+{
+   struct ns16550_platdata *plat = dev_get_platdata(dev);
+   int ret;
+
+   ret = ns16550_serial_ofdata_to_platdata(dev);
+   if (ret)
+   return ret;
+   plat->clock = V_NS16550_CLK;
+
+   return 0;
+}
+U_BOOT_DRIVER(serial_ns16550) = {
+   .name   = "serial_tegra20",
+   .id = UCLASS_SERIAL,
+   .of_match = tegra_serial_ids,
+   .ofdata_to_platdata = tegra_serial_ofdata_to_platdata,
+   .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
+   .priv_auto_alloc_size = sizeof(struct NS16550),
+   .probe = ns16550_serial_probe,
+   .ops= &ns16550_serial_ops,
+};
diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
index f1187f1..834b3d5 100644
--- a/include/configs/tegra-common.h
+++ b/include/configs/tegra-common.h
@@ -21,6 +21,9 @@
 #define CONFIG_DM
 #define CONFIG_CMD_DM
 #define CONFIG_DM_GPIO
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_DM_SERIAL
+#endif
 
 #define CONFIG_SYS_TIMER_RATE  100
 #define CONFIG_SYS_TIMER_COUNTER   NV_PA_TMRUS_BASE
@@ -46,10 +49,14 @@
 /*
  * NS16550 Configuration
  */
-#define CONFIG_SYS_NS16550
+#ifdef CONFIG_SPL_BUILD
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE(-4)
 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+#else
+#define CONFIG_TEGRA_SERIAL
+#endif
+#define CONFIG_SYS_NS16550
 
 /*
  * Common HW configuration.
-- 
2.1.0.rc2.206.gedb03e5

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[U-Boot] [PATCH v5 05/14] sandbox: Convert serial driver to use driver model

[Simon Glass]

Adjust the sandbox serial driver to use the new driver model uclass. The
driver works much as before, but within the new framework.

Signed-off-by: Simon Glass 
---

Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Rename struct device to struct udevice

 drivers/serial/sandbox.c  | 67 +--
 include/configs/sandbox.h |  3 +++
 2 files changed, 39 insertions(+), 31 deletions(-)

diff --git a/drivers/serial/sandbox.c b/drivers/serial/sandbox.c
index 51fd871..ac54e01 100644
--- a/drivers/serial/sandbox.c
+++ b/drivers/serial/sandbox.c
@@ -11,12 +11,16 @@
  */
 
 #include 
+#include 
+#include 
 #include 
 #include 
 #include 
 #include 
 #include 
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /*
  *
  *   serial_buf: A buffer that holds keyboard characters for the
@@ -30,27 +34,21 @@ static char serial_buf[16];
 static unsigned int serial_buf_write;
 static unsigned int serial_buf_read;
 
-static int sandbox_serial_init(void)
+static int sandbox_serial_probe(struct udevice *dev)
 {
struct sandbox_state *state = state_get_current();
 
if (state->term_raw != STATE_TERM_COOKED)
os_tty_raw(0, state->term_raw == STATE_TERM_RAW_WITH_SIGS);
-   return 0;
-}
 
-static void sandbox_serial_setbrg(void)
-{
+   return 0;
 }
 
-static void sandbox_serial_putc(const char ch)
+static int sandbox_serial_putc(struct udevice *dev, const char ch)
 {
os_write(1, &ch, 1);
-}
 
-static void sandbox_serial_puts(const char *str)
-{
-   os_write(1, str, strlen(str));
+   return 0;
 }
 
 static unsigned int increment_buffer_index(unsigned int index)
@@ -58,12 +56,15 @@ static unsigned int increment_buffer_index(unsigned int 
index)
return (index + 1) % ARRAY_SIZE(serial_buf);
 }
 
-static int sandbox_serial_tstc(void)
+static int sandbox_serial_pending(struct udevice *dev, bool input)
 {
const unsigned int next_index =
increment_buffer_index(serial_buf_write);
ssize_t count;
 
+   if (!input)
+   return 0;
+
os_usleep(100);
 #ifdef CONFIG_LCD
lcd_sync();
@@ -74,38 +75,42 @@ static int sandbox_serial_tstc(void)
count = os_read_no_block(0, &serial_buf[serial_buf_write], 1);
if (count == 1)
serial_buf_write = next_index;
+
return serial_buf_write != serial_buf_read;
 }
 
-static int sandbox_serial_getc(void)
+static int sandbox_serial_getc(struct udevice *dev)
 {
int result;
 
-   while (!sandbox_serial_tstc())
-   ;   /* buffer empty */
+   if (!sandbox_serial_pending(dev, true))
+   return -EAGAIN; /* buffer empty */
 
result = serial_buf[serial_buf_read];
serial_buf_read = increment_buffer_index(serial_buf_read);
return result;
 }
 
-static struct serial_device sandbox_serial_drv = {
-   .name   = "sandbox_serial",
-   .start  = sandbox_serial_init,
-   .stop   = NULL,
-   .setbrg = sandbox_serial_setbrg,
-   .putc   = sandbox_serial_putc,
-   .puts   = sandbox_serial_puts,
-   .getc   = sandbox_serial_getc,
-   .tstc   = sandbox_serial_tstc,
+static const struct dm_serial_ops sandbox_serial_ops = {
+   .putc = sandbox_serial_putc,
+   .pending = sandbox_serial_pending,
+   .getc = sandbox_serial_getc,
 };
 
-void sandbox_serial_initialize(void)
-{
-   serial_register(&sandbox_serial_drv);
-}
+static const struct udevice_id sandbox_serial_ids[] = {
+   { .compatible = "sandbox,serial" },
+   { }
+};
 
-__weak struct serial_device *default_serial_console(void)
-{
-   return &sandbox_serial_drv;
-}
+U_BOOT_DRIVER(serial_sandbox) = {
+   .name   = "serial_sandbox",
+   .id = UCLASS_SERIAL,
+   .of_match = sandbox_serial_ids,
+   .probe = sandbox_serial_probe,
+   .ops= &sandbox_serial_ops,
+   .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DEVICE(serial_sandbox_non_fdt) = {
+   .name = "serial_sandbox",
+};
diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h
index bf2d25c..f5fa4b3 100644
--- a/include/configs/sandbox.h
+++ b/include/configs/sandbox.h
@@ -31,6 +31,9 @@
 #define CONFIG_DM_DEMO_SHAPE
 #define CONFIG_DM_GPIO
 #define CONFIG_DM_TEST
+#define CONFIG_DM_SERIAL
+
+#define CONFIG_SYS_STDIO_DEREGISTER
 
 /* Number of bits in a C 'long' on this architecture */
 #define CONFIG_SANDBOX_BITS_PER_LONG   64
-- 
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Re: [U-Boot] [PATCH v2] patman: make run results better visible

[Simon Glass]

On 4 September 2014 12:57, Doug Anderson  wrote:

> Vadim,
>
> On Thu, Sep 4, 2014 at 10:45 AM, Vadim Bendebury 
> wrote:
> > For an occasional user of patman some failures are not obvious: for
> > instance when checkpatch reports warnings, the dry run still reports
> > that the email would be sent. If it is not dry run, the warnings are
> > shown on the screen, but it is not clear that the email was not sent.
> >
> > Add some code to report failure to send email explicitly.
> >
> > Tested by running the script on a patch with style violations,
> > observed error messages in the script output.
> >
> > Signed-off-by: Vadim Bendebury 
> > ---
> >
> > Changes in v2:
> >   - modified the error message for accuracy
> >
> >  tools/patman/patman.py | 7 ++-
> >  1 file changed, 6 insertions(+), 1 deletion(-)
>
> Reviewed-by: Doug Anderson 
>

Acked-by: Simon Glass 
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Re: [U-Boot] Force check of RSA-Signature

[Simon Glass]

Hi,

On 3 September 2014 09:12, Ulf Bartel  wrote:

> Hello.
>
> We are currently testing U-Boot on a PPC. Beside booting the system we
> like to use it do some system updates (e.g. Kernel, FDT and Initrd). I've
> compiled U-Boot with support for AES and RSA-Signatures. We are storing the
> RSA public keys using a Fit-Image for U-Boot configuration on Flash.
> Basically both AES and RSA support works as expected,
>
> but:
>
> 1) is there a possibility to always be sure that accessing an image from a
> Fit-container checks the signature?
> If the signature is wrong, we get an error as expected. But if we generate
> an image without any signature (which may be generated by anybody) the
> access is of course possible. Currently I used something like
>
> fdt get value algorithm /images/script@1/signature@1/ algo &&
> test "$algorithm" = "sha1,rsa2048" && echo success
>
> to check if the image has a signature before proceeding. But this feels
> wrong.
>

See the -r flag for mkimage. See also doc/uImage.FIT/beaglebone_vboot.txt
which uses it.

>
> 2) Is there a possibility to check the signature/CRC before copying the
> image to ram with imxtract?
>

I'm not sure of the specifics here - sometimes the image must be
decompressed, etc. so in principle this is tricky to implement (but not
impossible). Another option might be to zero it afterwards if the check
fails?

Regards,
Simon
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Re: [U-Boot] About verify uboot

[Simon Glass]

Hi,

On 21 July 2014 21:08, Duxiaoqiang  wrote:
>
> Hi
>
> I try to make use of uboot's secure verify feature, but failed. My procedure 
> is below:
>
> 1)   Enable control device tree
>
> Ø  Add CONFIG_OF_CONTROL / CONFIG_OF_SEPARATE to file vexpress_aemv8a.h
>
> 2)   Enable FIT and verify boot
>
> Ø  Add CONFIG_FIT/CONFIG_RSA/CONFIG_FIT_SIGNATURE to file vexpress_aemv8a.h
>
> 3)   Create RSA key pair use openssl named dev
>
> 4)   Create uboot.dts file as bellow
>
> /dts-v1/;
>
> / {
> model = "Keys";
> compatible = "denx, arm64 ";
>
> signature {
> key-dev {
> required = "conf";
> algo = "sha1,rsa2048";
> key-name-hint = "dev";
> };
> };
> };
>
>
> 5)   Compile uboot.dtb file
>
> dtc -p 0x1000 .uboot.dts -O dtb -o work/uboot.dtb
>
> 6)   Create kernel.its file as bellow
>
> /dts-v1/;
> / {
>
> description = "Simple image with single Linux kernel and FDT blob";
>
> #address-cells = <1>;
>
>images {
>
> kernel@1 {
>
> description = "Linux kernel";
>
> data = /incbin/("./arch/arm/boot/zImage");
>
> type = "kernel";
>
> arch = "arm";
>
> os = "linux";
>
> compression = "none";
>
> load = <0x40008000>;
>
> entry = <0x40008000>;
>
>  hash@1 {
>
> algo = "sha1";
>
> };
>
> };
>
>
> fdt@1 {
>
> description = "Flattened Device Tree blob";
>
> data = /incbin/("./arch/arm/boot/arm64.dtb");
>
> type = "flat_dt";
>
> arch = "arm";
>
> compression = "none";
>
> hash@1 {
>
> algo = "sha1";
>
> };
>
> };
>
> };
>
>
>
> configurations {
>
> default = "conf@1";
>
> conf@1 {
>
> description = "Boot Linux kernel with FDT blob";
>
> kernel = "kernel@1";
>
> fdt = "fdt@1";
>
> signature@1 {
>
> algo = "sha1,rsa2048";
>
> key-name-hint = "dev ";
>
> };
>
> };
>
> };
>
> };
>
> 7)   Sign the image
>
> Mkimage -D "-I dts -O dtb -p 2000" -f kernel.its - K uboot.dtb -k keys -r 
> rsa.img
>
> 8)   Make uboot FDT
>
> Make vexpress_aem64a_config
>
> Make DEV_TREE_BIN = work/uboot.dtb
>
>And the Error is happened when build uboot FDT, error information is 
> "Please define CONFIG_DEFAULT_DEVICE_TREE or build with DEVICE_TREE= 
> argument".
>
>  My question is :
>> Should I need to specify uboot.dts file when building FDT uboot

I only just saw this email. Yes, device tree is required.

Regards,
Simon
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Re: [U-Boot] Uboot - verified boot - CONFIG_OF_SEPARATE

[Simon Glass]

Hi,

On 11 March 2014 05:39, Thilo Cestonaro  wrote:
> Hey!
>
> When I build my Uboot with the CONFIG_OF_SEPARATE set to gain access to the
> compiled dtb, Uboot can't find my concatenated dtb during the boot.
> After injecting the pulbic keys for the verified boot, I cat the u-boot.dtb
> behind the u-boot.bin. After that I mkimage the u-boot.img as usuall.
>
> I found, that if I change the offset where the fdt_blob is searched for by
> +300, it finds the dtb correctly.
> Like this:
> ---
>  #elif defined CONFIG_OF_SEPARATE
> /* FDT is at end of image */
> -   gd->fdt_blob = (void *)(_end_ofs + _TEXT_BASE);
> +   gd->fdt_blob = (void *)(_end_ofs + _TEXT_BASE + 300);
>  #endif
> ---
>
> But I can't explain why this might be. The 300 isn't a random value! I
> calculated it via some debug output and it works reliably.
> But like it is with these workarounds, I don't like them!
> So I'm searching for an answer.
>
> Any ideas, why the offset is not _end_ofs + _TEXT_BASE, like it should be?

I just saw this now. You probably already know the outcome, but for
the record, commit 8974292 added a check for this problem, and it was
fixed for TI boards. Specifically for the Beaglebone, see
doc/uImage.FIT/beaglebone_vboot.txt for a walk-through.

Regards,
Simon
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Re: [U-Boot] [PATCH] dfu, usb: set usb descriptor to values defined in dfu spec 1.1

[Marek Vasut]

On Thursday, September 04, 2014 at 12:21:40 PM, Heiko Schocher wrote:

Hi Heiko,

I'll just rant a bit, but please wait until Lukasz does a proper runthrough.

> set bDeviceClass, bDeviceSubClass and bcdUSB to the values
> defined in dfu spec 1.1 chapter 4.2.1 found here:
> 
> http://www.usb.org/developers/devclass_docs/DFU_1.1.pdf

This URL gives me a website with:
"
Resource not found.
Please check the URL and try again.
"

> Signed-off-by: Heiko Schocher 
> Cc: Lukasz Majewski 
> Cc: Marek Vasut 
> Cc: Roger Meier 
> 
> ---
> 
> before this patch, "dfu-util -l" showed:
> 
> Bus 002 Device 114: ID 0908:02c5 Siemens AG
> Device Descriptor:
>   bLength18
>   bDescriptorType 1
>   bcdUSB   2.00
>   bDeviceClass2 Communications
>   bDeviceSubClass 2 Abstract (modem)
>   bDeviceProtocol 0 None
>   bMaxPacketSize064
>   idVendor   0x0908 Siemens AG
>   idProduct  0x02c5
>   bcdDevice0.00
>   iManufacturer   1 Siemens AG
> 
> with this patch:
> 
> Bus 002 Device 089: ID 0908:02c5 Siemens AG
> Device Descriptor:
>   bLength18
>   bDescriptorType 1
>   bcdUSB   1.10
>   bDeviceClass0 (Defined at Interface level)
>   bDeviceSubClass 0
>   bDeviceProtocol 0
>   bMaxPacketSize064
>   idVendor   0x0908 Siemens AG
>   idProduct  0x02c5
>   bcdDevice0.00
>   iManufacturer   1 Siemens AG
>   iProduct2 USB download gadget
> 
> which fits for "bcdUSB", "bDeviceClass" and "bDeviceSubClass" with
> the DFU spezifikation.

This patch doesn't seem fully right, let me explain below please.

> ---
>  drivers/usb/gadget/f_dfu.c | 5 +++--
>  drivers/usb/gadget/g_dnl.c | 6 +++---
>  2 files changed, 6 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/usb/gadget/f_dfu.c b/drivers/usb/gadget/f_dfu.c
> index 9128add..9429e50 100644
> --- a/drivers/usb/gadget/f_dfu.c
> +++ b/drivers/usb/gadget/f_dfu.c
> @@ -83,8 +83,9 @@ static struct usb_descriptor_header *dfu_runtime_descs[]
> = { static const struct usb_qualifier_descriptor dev_qualifier = {
>   .bLength =  sizeof dev_qualifier,
>   .bDescriptorType =  USB_DT_DEVICE_QUALIFIER,
> - .bcdUSB =   __constant_cpu_to_le16(0x0200),
> - .bDeviceClass = USB_CLASS_VENDOR_SPEC,
> + .bcdUSB =   __constant_cpu_to_le16(0x0110),

See [1] and look for first and second instance of 'bcdUsb' there please. Quote 
of the second one:

'
The bcdUSB field reports the highest version of USB the device supports. The 
value is in binary coded decimal with a format of 0xJJMN where JJ is the major 
version number, M is the minor version number and N is the sub minor version 
number. e.g. USB 2.0 is reported as 0x0200, USB 1.1 as 0x0110 and USB 1.0 as 
0x0100.
'

So this should be configured dynamically based on what the highest mode the 
controller supports is, no?

> + .bDeviceClass = USB_CLASS_PER_INTERFACE,

This might be OK.

> + .bDeviceSubClass =  0x00,

But this is not, the device definitelly isn't CDC-serial.

[...]

[1] http://www.beyondlogic.org/usbnutshell/usb5.shtml

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Re: [U-Boot] [PATCH v2] kconfig: zynq: Add ZYBO board

[Masahiro Yamada]

On Mon,  1 Sep 2014 12:58:54 +0200
Michal Simek  wrote:

> From: Peter Crosthwaite 
> 
> Add a defconfig and Kconfigury for the Digilent ZYBO board.
> 
> Signed-off-by: Peter Crosthwaite 
> Signed-off-by: Michal Simek 
> Acked-by: Jagannadha Sutradharudu Teki 
> ---

Looks good to me.

Reviewed-by: Masahiro Yamada 

Thanks!

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Re: [U-Boot] [PATCH v3 5/6] arm: debug: add Kconfig entries for lowlevel debug

[Masahiro Yamada]

Hi Simon,


On Wed, 3 Sep 2014 18:01:44 -0600
Simon Glass  wrote:

> Hi Masahiro,
> 
> On 31 August 2014 20:06, Masahiro Yamada  wrote:
> > We have not had a good method to debug the early boot stage such as
> > lowlevel_init function.  I guess developers generally use dedicated
> > debuggers for that, but it is difficult in some cases.
> > (For example, my debugger cannot connect to the ARM processor when
> > it is in the secure state.  It sometimes happens when I need to
> > debug the early boot stage on ARM SoCs with secure extension.)
> >
> > The low level debug feature in Linux would be also helpful for U-boot
> > when we are stucking in nasty problems where the console is not
> > available yet.
> >
> > You have to enable CONFIG_DEBUG_LL to use this feature.
> > For now, only 8250-compatible UART devices are supported.
> > You can add a header file under arch/arm/include/debug/ directory
> > to support your UART device if necessary.
> >
> > Signed-off-by: Masahiro Yamada 
> 
> Is it possible to use the existing drivers for this? It seems
> unfortunate to duplicate the ns16550 driver (if that is what has
> happened).

I am afraid it is difficult since the serial drivers are too
complicated and written in C.
Indeed, it is unfortunate, though.

This low level debug framework only uses r0, r1, r2, r3
registers and does not need stack.

I think it has an advantage over the serial drivers
for debugging the lowlevel_init where no stack is ready.



Best Regards
Masahiro Yamada

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Re: [U-Boot] [PATCH] nand/denali: Adding Denali NAND driver support

[Masahiro Yamada]

Hi Chin,

Are you planning to send v10
with the fixes suggested by Scott?


Best Regards
Masahiro Yamada



On Tue, 2 Sep 2014 21:15:52 -0500
Scott Wood  wrote:

> On Sat, 2014-08-30 at 07:45 -0400, Tom Rini wrote:
> > On Thu, Aug 28, 2014 at 11:13:40AM +0900, Masahiro Yamada wrote:
> > > Hi Scott,
> > > 
> > > 
> > > On Tue, 19 Aug 2014 04:47:40 -0500
> > > Chin Liang See  wrote:
> > > 
> > > > To add the Denali NAND driver support into U-Boot.
> > > > This driver is leveraged from Linux.
> > > > 
> > > > Signed-off-by: Chin Liang See 
> > > > Cc: Scott Wood 
> > > > Cc: Masahiro Yamada 
> > > > ---
> > > > Changes for v9
> > > > - Updated the commit messageb
> > > > - Removed macro kern_xx
> > > > - Removed debug macro
> > > > - Changed CONFIG_NAND_DENALI_64BIT to CONFIG_SYS_NAND_DENALI_64BIT
> > > 
> > > 
> > > Any comments?
> > > 
> > > If nothing, please apply this patch.
> > 
> > I don't see anything obviously wrong here, but since Scott has reviewed
> > previous versions I want to give him a little more time to ack.  I'm OK
> > pulling this into master with Scott's ack or lets say Wednesday next
> > week and we'll ask Chin Liang to address any late feedback.  Thanks all!
> 
> I still don't see a reference to the SHA of the corresponding Linux
> driver.
> 
> #define MODE5_WORKAROUND 0 still exists even though it's never used.
> 
> I still see (void *) casts in memcpy -- v8 comments said "removed" but
> not all instances were removed.
> 
> It still introduces CONFIG_SYS_NAND_DENALI_64BIT without documenting it.
> 
> -scott
> 



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Re: [U-Boot] [PATCH] dfu, usb: set usb descriptor to values defined in dfu spec 1.1

[Heiko Schocher]

Hello Marek,

Am 05.09.2014 00:42, schrieb Marek Vasut:

On Thursday, September 04, 2014 at 12:21:40 PM, Heiko Schocher wrote:

Hi Heiko,

I'll just rant a bit, but please wait until Lukasz does a proper runthrough.


set bDeviceClass, bDeviceSubClass and bcdUSB to the values
defined in dfu spec 1.1 chapter 4.2.1 found here:

http://www.usb.org/developers/devclass_docs/DFU_1.1.pdf


This URL gives me a website with:
"
Resource not found.
Please check the URL and try again.
"


:-( Maybe it is deleted currently there?
Hmm.. there is a search field if you open the above URL ... and if you type
DFU and press search, you get:

DFU
File Format: PDF/Adobe Acrobat
Aug 5, 2004 ... USB Device Firmware Upgrade Specification, Revision 1.1. 2. 
Intellectual Property Disclaimer. THIS SPECIFICATION IS PROVIDED “AS IS” ...
www.usb.org/developers/devclass_docs/DFU_1.1.pdf

This is exactly the above link ...

This link is also referenced from openmoko:

http://wiki.openmoko.org/wiki/USB_DFU_-_The_USB_Device_Firmware_Upgrade_standard


Signed-off-by: Heiko Schocher
Cc: Lukasz Majewski
Cc: Marek Vasut
Cc: Roger Meier

---

before this patch, "dfu-util -l" showed:

Bus 002 Device 114: ID 0908:02c5 Siemens AG
Device Descriptor:
   bLength18
   bDescriptorType 1
   bcdUSB   2.00
   bDeviceClass2 Communications
   bDeviceSubClass 2 Abstract (modem)
   bDeviceProtocol 0 None
   bMaxPacketSize064
   idVendor   0x0908 Siemens AG
   idProduct  0x02c5
   bcdDevice0.00
   iManufacturer   1 Siemens AG

with this patch:

Bus 002 Device 089: ID 0908:02c5 Siemens AG
Device Descriptor:
   bLength18
   bDescriptorType 1
   bcdUSB   1.10
   bDeviceClass0 (Defined at Interface level)
   bDeviceSubClass 0
   bDeviceProtocol 0
   bMaxPacketSize064
   idVendor   0x0908 Siemens AG
   idProduct  0x02c5
   bcdDevice0.00
   iManufacturer   1 Siemens AG
   iProduct2 USB download gadget

which fits for "bcdUSB", "bDeviceClass" and "bDeviceSubClass" with
the DFU spezifikation.


This patch doesn't seem fully right, let me explain below please.


---
  drivers/usb/gadget/f_dfu.c | 5 +++--
  drivers/usb/gadget/g_dnl.c | 6 +++---
  2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/usb/gadget/f_dfu.c b/drivers/usb/gadget/f_dfu.c
index 9128add..9429e50 100644
--- a/drivers/usb/gadget/f_dfu.c
+++ b/drivers/usb/gadget/f_dfu.c
@@ -83,8 +83,9 @@ static struct usb_descriptor_header *dfu_runtime_descs[]
= { static const struct usb_qualifier_descriptor dev_qualifier = {
.bLength =  sizeof dev_qualifier,
.bDescriptorType =  USB_DT_DEVICE_QUALIFIER,
-   .bcdUSB =   __constant_cpu_to_le16(0x0200),
-   .bDeviceClass = USB_CLASS_VENDOR_SPEC,
+   .bcdUSB =   __constant_cpu_to_le16(0x0110),


See [1] and look for first and second instance of 'bcdUsb' there please. Quote
of the second one:

'
The bcdUSB field reports the highest version of USB the device supports. The
value is in binary coded decimal with a format of 0xJJMN where JJ is the major
version number, M is the minor version number and N is the sub minor version
number. e.g. USB 2.0 is reported as 0x0200, USB 1.1 as 0x0110 and USB 1.0 as
0x0100.
'

So this should be configured dynamically based on what the highest mode the
controller supports is, no?


Good question ... the DFU 1.1 spezification says in chapter
4.2.1 DFU Mode Device Descriptor:

bcdUSB = 0100  USB specification release number in binary coded decimal.
   (which seems wrong, as the spez is version 1.1, see [2])
bDeviceClass = 0
bDeviceSubClass = 0

... ?

I discussed this change with Lukasz, see:

[2] http://lists.denx.de/pipermail/u-boot/2014-August/186918.html




+   .bDeviceClass = USB_CLASS_PER_INTERFACE,


This might be OK.


+   .bDeviceSubClass =  0x00,


But this is not, the device definitelly isn't CDC-serial.

[...]

[1] http://www.beyondlogic.org/usbnutshell/usb5.shtml


bye,
Heiko
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Re: [U-Boot] Force check of RSA-Signature

[Wolfgang Denk]

Dear Simon & Ulf,

In message  
you wrote:
> 
> > 2) Is there a possibility to check the signature/CRC before copying the
> > image to ram with imxtract?
> 
> I'm not sure of the specifics here - sometimes the image must be
> decompressed, etc. so in principle this is tricky to implement (but not
> impossible). Another option might be to zero it afterwards if the check
> fails?

Maybe I misunderstand the question, but: in any case we have to read
the image from a storage device into memory to be able to look at the
data, which is obviously needed for computing a checksum or signature.

Best regards,

Wolfgang Denk

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Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
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taken away. - Terry Pratchett, _Sourcery_
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[U-Boot] [PATCH v3 3/3] spi, sf: use offset and size in sf cmd from mtdpartition

[Heiko Schocher]

with this patch, it is possible to get the offset and size information
from the mtdpartiton setting in "mtdparts", similiar to the
"nand" commandos.

=> sf
sf - SPI flash sub-system

Usage:
sf probe [[bus:]cs] [hz] [mode] - init flash device on given SPI bus
  and chip select
sf read addr offset|partition len   - read `len' bytes starting at
  `offset' to memory at `addr'
sf write addr offset|partition len  - write `len' bytes from memory
  at `addr' to flash at `offset'
sf erase offset|partition [+]len- erase `len' bytes from `offset'
  `+len' round up `len' to block size
sf update addr offset|partition len - erase and write `len' bytes from 
memory
  at `addr' to flash at `offset'
=>
for example "env" is defined in mtdparts:

=> sf read 1300 env
device 0 offset 0xd, size 0x1
SF: 65536 bytes @ 0xd Read: OK
=>

Signed-off-by: Heiko Schocher 
Cc: Jagannadha Sutradharudu Teki 

---
- changes for v2:
  none
- changes for v3:
  rebase with d6c1ffc7d23f4fe4ae8c91101861055b8e1501b6
---
 common/cmd_sf.c | 50 +-
 1 file changed, 25 insertions(+), 25 deletions(-)

diff --git a/common/cmd_sf.c b/common/cmd_sf.c
index 7653d7e..fc306ee 100644
--- a/common/cmd_sf.c
+++ b/common/cmd_sf.c
@@ -10,6 +10,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 #include 
 
@@ -244,23 +246,21 @@ static int spi_flash_update(struct spi_flash *flash, u32 
offset,
 static int do_spi_flash_read_write(int argc, char * const argv[])
 {
unsigned long addr;
-   unsigned long offset;
-   unsigned long len;
void *buf;
char *endp;
int ret = 1;
+   int dev = 0;
+   loff_t offset, len, maxsize;
 
-   if (argc < 4)
+   if (argc < 3)
return -1;
 
addr = simple_strtoul(argv[1], &endp, 16);
if (*argv[1] == 0 || *endp != 0)
return -1;
-   offset = simple_strtoul(argv[2], &endp, 16);
-   if (*argv[2] == 0 || *endp != 0)
-   return -1;
-   len = simple_strtoul(argv[3], &endp, 16);
-   if (*argv[3] == 0 || *endp != 0)
+
+   if (arg_off_size(argc - 2, &argv[2], &dev, &offset, &len, &maxsize,
+   MTD_DEV_TYPE_NOR, flash->size))
return -1;
 
/* Consistency checking */
@@ -299,31 +299,31 @@ static int do_spi_flash_read_write(int argc, char * const 
argv[])
 
 static int do_spi_flash_erase(int argc, char * const argv[])
 {
-   unsigned long offset;
-   unsigned long len;
-   char *endp;
int ret;
+   int dev = 0;
+   loff_t offset, len, maxsize;
+   ulong size;
 
if (argc < 3)
return -1;
 
-   offset = simple_strtoul(argv[1], &endp, 16);
-   if (*argv[1] == 0 || *endp != 0)
+   if (arg_off(argv[1], &dev, &offset, &len, &maxsize,
+   MTD_DEV_TYPE_NOR, flash->size))
return -1;
 
-   ret = sf_parse_len_arg(argv[2], &len);
+   ret = sf_parse_len_arg(argv[2], &size);
if (ret != 1)
return -1;
 
/* Consistency checking */
-   if (offset + len > flash->size) {
+   if (offset + size > flash->size) {
printf("ERROR: attempting %s past flash size (%#x)\n",
   argv[0], flash->size);
return 1;
}
 
-   ret = spi_flash_erase(flash, offset, len);
-   printf("SF: %zu bytes @ %#x Erased: %s\n", (size_t)len, (u32)offset,
+   ret = spi_flash_erase(flash, offset, size);
+   printf("SF: %zu bytes @ %#x Erased: %s\n", (size_t)size, (u32)offset,
   ret ? "ERROR" : "OK");
 
return ret == 0 ? 0 : 1;
@@ -545,13 +545,13 @@ U_BOOT_CMD(
"SPI flash sub-system",
"probe [[bus:]cs] [hz] [mode]   - init flash device on given SPI bus\n"
" and chip select\n"
-   "sf read addr offset len- read `len' bytes starting at\n"
-   " `offset' to memory at `addr'\n"
-   "sf write addr offset len   - write `len' bytes from memory\n"
-   " at `addr' to flash at `offset'\n"
-   "sf erase offset [+]len - erase `len' bytes from `offset'\n"
-   " `+len' round up `len' to block size\n"
-   "sf update addr offset len  - erase and write `len' bytes from 
memory\n"
-   " at `addr' to flash at `offset'"
+   "sf read addr offset|partition len  - read `len' bytes starting 
at\n"
+   " `offset' to memory at 
`addr'\n"
+   "sf write addr offset|partition len - write `len' bytes from 
memory\n"
+   " at `a

[U-Boot] [PATCH v3 0/3] spi, sf: add mtdparts feature to spi and sf commands

[Heiko Schocher]

This patchserie add the popssibility to define mtd partitions on
spi nor flash, and use this settings with the sf commands.

steps:

- add MTD layer driver for spi, original patch from:
http://git.denx.de/?p=u-boot/u-boot-mips.git;a=commitdiff;h=bb246819cdc90493dd7089eaa51b9e639765cced

  and addapted it to current mainline.

- move common functions to get offset and size from
  cmdline nand command to extract offset and size from
  a mtd partition to common place "drivers/mtd/mtd_uboot.c"
  maybe another place is better?

- add to the sf command the possibility to use offset and size from
  the settings in mtdparts

With this patchset, the sf command looks now:

=> sf
sf - SPI flash sub-system

Usage:
sf probe [[bus:]cs] [hz] [mode] - init flash device on given SPI bus
  and chip select
sf read addr offset|partition len   - read `len' bytes starting at
  `offset' to memory at `addr'
sf write addr offset|partition len  - write `len' bytes from memory
  at `addr' to flash at `offset'
sf erase offset|partition [+]len- erase `len' bytes from `offset'
  `+len' round up `len' to block size
sf update addr offset|partition len - erase and write `len' bytes from 
memory
  at `addr' to flash at `offset'
=>
for example "env" is defined in mtdparts:

=> sf read 1300 env
device 0 offset 0xd, size 0x1
SF: 65536 bytes @ 0xd Read: OK
=>

There are the followings checkpatch warnings:

CHECK: Alignment should match open parenthesis
#153: FILE: common/cmd_nand.c:217:
+   if (arg_off(argv[2], &idx, &addr, &maxsize, &maxsize,
+   MTD_DEV_TYPE_NAND, nand_info[idx].size)) {

CHECK: Alignment should match open parenthesis
#179: FILE: common/cmd_nand.c:557:
+   if (arg_off(argv[3], &dev, &off, &size, &maxsize,
+   MTD_DEV_TYPE_NAND, nand_info[dev].size))

CHECK: Alignment should match open parenthesis
#193: FILE: common/cmd_nand.c:576:
+   if (arg_off_size(argc - 3, argv + 3, &dev, &off, &size,
+   &maxsize, MTD_DEV_TYPE_NAND,

total: 0 errors, 0 warnings, 3 checks, 361 lines checked

NOTE: Ignored message types: COMPLEX_MACRO CONSIDER_KSTRTO MINMAX 
MULTISTATEMENT_MACRO_USE_DO_WHILE NETWORKING_BLOCK_COMMENT_STYLE USLEEP_RANGE

20140714_ml_mtdparts/0002-mtd-nand-move-common-functions-from-cmd_nand.c-to-co.patch
 has style problems, please review.

I see not, why this warning pops up ...

- changes for v2:
  - mtd-spi-add-MTD-layer-driver.patch
- add comment from Daniel Schwierzeck:
  fix compile error from original patch with
  "static inline" rather than "static __maybe_unused"
- changes for v3:
  - rebase with d6c1ffc7d23f4fe4ae8c91101861055b8e1501b6
  - add comments from scott wood:
- align MTD_DEV_TYPE_NAND correct
- remove unnecessary inline
- rework "jffs2 header" problem later

Cc: Scott Wood 
Cc: Tom Rini 
Cc: Daniel Schwierzeck 
Cc: Jagannadha Sutradharudu Teki 

Daniel Schwierzeck (1):
  mtd, spi: add MTD layer driver

Heiko Schocher (2):
  mtd, nand: move common functions from cmd_nand.c to common place
  spi, sf: use offset and size in sf cmd from mtdpartition

 README|   3 +
 common/cmd_nand.c | 140 --
 common/cmd_onenand.c  |  19 ++
 common/cmd_sf.c   |  59 +-
 drivers/mtd/Makefile  |   4 +-
 drivers/mtd/mtd_uboot.c   | 114 ++
 drivers/mtd/spi/Makefile  |   1 +
 drivers/mtd/spi/sf_internal.h |  13 
 drivers/mtd/spi/sf_mtd.c  | 104 +++
 drivers/mtd/spi/sf_probe.c|   5 ++
 include/linux/mtd/mtd.h   |   7 +++
 11 files changed, 310 insertions(+), 159 deletions(-)
 create mode 100644 drivers/mtd/mtd_uboot.c
 create mode 100644 drivers/mtd/spi/sf_mtd.c

-- 
1.8.3.1

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[U-Boot] [PATCH v3 1/3] mtd, spi: add MTD layer driver

[Heiko Schocher]

From: Daniel Schwierzeck 

add MTD layer driver for spi, original patch from:
http://git.denx.de/?p=u-boot/u-boot-mips.git;a=commitdiff;h=bb246819cdc90493dd7089eaa51b9e639765cced

changes from Heiko Schocher against this patch:
- remove compile error if not defining CONFIG_SPI_FLASH_MTD:

  LD  drivers/mtd/spi/built-in.o
drivers/mtd/spi/sf_probe.o: In function `spi_flash_mtd_unregister':
/home/hs/abb/imx6/u-boot/drivers/mtd/spi/sf_internal.h:168: multiple definition 
of `spi_flash_mtd_unregister'
drivers/mtd/spi/sf_params.o:/home/hs/abb/imx6/u-boot/drivers/mtd/spi/sf_internal.h:168:
 first defined here
drivers/mtd/spi/sf_ops.o: In function `spi_flash_mtd_unregister':
/home/hs/abb/imx6/u-boot/drivers/mtd/spi/sf_internal.h:168: multiple definition 
of `spi_flash_mtd_unregister'
drivers/mtd/spi/sf_params.o:/home/hs/abb/imx6/u-boot/drivers/mtd/spi/sf_internal.h:168:
 first defined here
make[1]: *** [drivers/mtd/spi/built-in.o] Fehler 1
make: *** [drivers/mtd/spi] Fehler 2

- add a README entry.
- add correct writebufsize, to fit with Linux v3.14
  MTD, UBI/UBIFS sync.

Signed-off-by: Daniel Schwierzeck 
Signed-off-by: Heiko Schocher 
Cc: Jagannadha Sutradharudu Teki 

---
MAKEALL for ar, mips, powerc compiles clean

- changes for v2:
  - add comment from Daniel Schwierzeck:
fix compile error from original patch with
"static inline" rather than "static __maybe_unused"
- changes for v3:
  rebase with d6c1ffc7d23f4fe4ae8c91101861055b8e1501b6
---
 README|   3 ++
 common/cmd_sf.c   |   9 ++--
 drivers/mtd/spi/Makefile  |   1 +
 drivers/mtd/spi/sf_internal.h |  13 ++
 drivers/mtd/spi/sf_mtd.c  | 104 ++
 drivers/mtd/spi/sf_probe.c|   5 ++
 6 files changed, 131 insertions(+), 4 deletions(-)
 create mode 100644 drivers/mtd/spi/sf_mtd.c

diff --git a/README b/README
index 0a0f528..e7be54e 100644
--- a/README
+++ b/README
@@ -2965,6 +2965,9 @@ CBFS (Coreboot Filesystem) support
operation will not execute. The only way to exit this
hardware-protected mode is to drive W#/VPP HIGH.
 
+   CONFIG_SPI_FLASH_MTD
+   add  MTD translation layer driver.
+
 - SystemACE Support:
CONFIG_SYSTEMACE
 
diff --git a/common/cmd_sf.c b/common/cmd_sf.c
index b4ceb71..7653d7e 100644
--- a/common/cmd_sf.c
+++ b/common/cmd_sf.c
@@ -121,16 +121,17 @@ static int do_spi_flash_probe(int argc, char * const 
argv[])
return -1;
}
 
+   if (flash)
+   spi_flash_free(flash);
+
new = spi_flash_probe(bus, cs, speed, mode);
+   flash = new;
+
if (!new) {
printf("Failed to initialize SPI flash at %u:%u\n", bus, cs);
return 1;
}
 
-   if (flash)
-   spi_flash_free(flash);
-   flash = new;
-
return 0;
 }
 
diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index 9e18fb4..b15d273 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -12,6 +12,7 @@ endif
 
 obj-$(CONFIG_CMD_SF) += sf.o
 obj-$(CONFIG_SPI_FLASH) += sf_params.o sf_probe.o sf_ops.o
+obj-$(CONFIG_SPI_FLASH_MTD) += sf_mtd.o
 obj-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.o
 obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o
 obj-$(CONFIG_SPI_M95XXX) += eeprom_m95xxx.o
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 19d4914..a9f97d1 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -160,4 +160,17 @@ int spi_flash_read_common(struct spi_flash *flash, const 
u8 *cmd,
 int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
size_t len, void *data);
 
+#ifdef CONFIG_SPI_FLASH_MTD
+int spi_flash_mtd_register(struct spi_flash *flash);
+void spi_flash_mtd_unregister(void);
+#else
+static inline int spi_flash_mtd_register(struct spi_flash *flash)
+{
+   return 0;
+}
+static inline void spi_flash_mtd_unregister(void)
+{
+}
+#endif
+
 #endif /* _SF_INTERNAL_H_ */
diff --git a/drivers/mtd/spi/sf_mtd.c b/drivers/mtd/spi/sf_mtd.c
new file mode 100644
index 000..0b9cb62
--- /dev/null
+++ b/drivers/mtd/spi/sf_mtd.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (C) 2012-2014 Daniel Schwierzeck, daniel.schwierz...@gmail.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static struct mtd_info sf_mtd_info;
+static char sf_mtd_name[8];
+
+static int spi_flash_mtd_erase(struct mtd_info *mtd, struct erase_info *instr)
+{
+   struct spi_flash *flash = mtd->priv;
+   int err;
+
+   instr->state = MTD_ERASING;
+
+   err = spi_flash_erase(flash, instr->addr, instr->len);
+   if (err) {
+   instr->state = MTD_ERASE_FAILED;
+   instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
+   return -EIO;
+   }
+
+   instr->state = MTD_ERASE_DONE;
+   mtd_erase_callback(instr);
+
+   return 0;
+}
+
+sta

[U-Boot] [PATCH v3 2/3] mtd, nand: move common functions from cmd_nand.c to common place

[Heiko Schocher]

move common functions from cmd_nand.c (for calculating offset
and size from cmdline paramter) to common place, so they could
used from other commands which use mtd partitions.

For onenand the arg_off_size() is left in common/cmd_onenand.c.
It should use now the common arg_off() function, but as I could
not test onenand I let it there ...

Signed-off-by: Heiko Schocher 
Cc: Scott Wood 
Cc: Tom Rini 

---
- changes for v2:
  none
- changes for v3:
  - add comments from scott wood:
- align MTD_DEV_TYPE_NAND correct
- remove unnecessary inline
- rework "jffs2 header" problem later
  - rebase with d6c1ffc7d23f4fe4ae8c91101861055b8e1501b6
---
 common/cmd_nand.c   | 140 +---
 common/cmd_onenand.c|  19 +++
 drivers/mtd/Makefile|   4 +-
 drivers/mtd/mtd_uboot.c | 114 +++
 include/linux/mtd/mtd.h |   7 +++
 5 files changed, 154 insertions(+), 130 deletions(-)
 create mode 100644 drivers/mtd/mtd_uboot.c

diff --git a/common/cmd_nand.c b/common/cmd_nand.c
index f9ced9d..099ba00 100644
--- a/common/cmd_nand.c
+++ b/common/cmd_nand.c
@@ -133,115 +133,6 @@ static int set_dev(int dev)
return 0;
 }
 
-static inline int str2off(const char *p, loff_t *num)
-{
-   char *endptr;
-
-   *num = simple_strtoull(p, &endptr, 16);
-   return *p != '\0' && *endptr == '\0';
-}
-
-static inline int str2long(const char *p, ulong *num)
-{
-   char *endptr;
-
-   *num = simple_strtoul(p, &endptr, 16);
-   return *p != '\0' && *endptr == '\0';
-}
-
-static int get_part(const char *partname, int *idx, loff_t *off, loff_t *size,
-   loff_t *maxsize)
-{
-#ifdef CONFIG_CMD_MTDPARTS
-   struct mtd_device *dev;
-   struct part_info *part;
-   u8 pnum;
-   int ret;
-
-   ret = mtdparts_init();
-   if (ret)
-   return ret;
-
-   ret = find_dev_and_part(partname, &dev, &pnum, &part);
-   if (ret)
-   return ret;
-
-   if (dev->id->type != MTD_DEV_TYPE_NAND) {
-   puts("not a NAND device\n");
-   return -1;
-   }
-
-   *off = part->offset;
-   *size = part->size;
-   *maxsize = part->size;
-   *idx = dev->id->num;
-
-   ret = set_dev(*idx);
-   if (ret)
-   return ret;
-
-   return 0;
-#else
-   puts("offset is not a number\n");
-   return -1;
-#endif
-}
-
-static int arg_off(const char *arg, int *idx, loff_t *off, loff_t *size,
-   loff_t *maxsize)
-{
-   if (!str2off(arg, off))
-   return get_part(arg, idx, off, size, maxsize);
-
-   if (*off >= nand_info[*idx].size) {
-   puts("Offset exceeds device limit\n");
-   return -1;
-   }
-
-   *maxsize = nand_info[*idx].size - *off;
-   *size = *maxsize;
-   return 0;
-}
-
-static int arg_off_size(int argc, char *const argv[], int *idx,
-   loff_t *off, loff_t *size, loff_t *maxsize)
-{
-   int ret;
-
-   if (argc == 0) {
-   *off = 0;
-   *size = nand_info[*idx].size;
-   *maxsize = *size;
-   goto print;
-   }
-
-   ret = arg_off(argv[0], idx, off, size, maxsize);
-   if (ret)
-   return ret;
-
-   if (argc == 1)
-   goto print;
-
-   if (!str2off(argv[1], size)) {
-   printf("'%s' is not a number\n", argv[1]);
-   return -1;
-   }
-
-   if (*size > *maxsize) {
-   puts("Size exceeds partition or device limit\n");
-   return -1;
-   }
-
-print:
-   printf("device %d ", *idx);
-   if (*size == nand_info[*idx].size)
-   puts("whole chip\n");
-   else
-   printf("offset 0x%llx, size 0x%llx\n",
-  (unsigned long long)*off, (unsigned long long)*size);
-   return 0;
-}
-
 #ifdef CONFIG_CMD_NAND_LOCK_UNLOCK
 static void print_status(ulong start, ulong end, ulong erasesize, int status)
 {
@@ -322,7 +213,12 @@ int do_nand_env_oob(cmd_tbl_t *cmdtp, int argc, char 
*const argv[])
goto usage;
 
/* We don't care about size, or maxsize. */
-   if (arg_off(argv[2], &idx, &addr, &maxsize, &maxsize)) {
+   if (arg_off(argv[2], &idx, &addr, &maxsize, &maxsize,
+   MTD_DEV_TYPE_NAND, nand_info[idx].size)) {
+   puts("Offset or partition name expected\n");
+   return 1;
+   }
+   if (set_dev(idx)) {
puts("Offset or partition name expected\n");
return 1;
}
@@ -592,7 +488,10 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
printf("\nNAND %s: ", cmd);
/* skip first two or three arguments, look for offset and size 
*/
if (arg_off

[U-Boot] [PATCH v4 1/6] nand: denali: add Denali NAND driver for SPL

[Masahiro Yamada]

The SPL-mode driver for Denali(Cadence) NAND Flash Memory Controller IP.

This driver requires two CONFIG macros:
 - CONFIG_SPL_NAND_DENALI
 Define to enable this driver.
 - CONFIG_SYS_NAND_BAD_BLOCK_POS
 Specify bad block mark position in the oob space. Typically 0.

Signed-off-by: Masahiro Yamada 
Cc: Chin Liang See 
Cc: Scott Wood 
---

Changes in v4:
  - Add a workaround to not depend on the Denali driver
posted by Chin Liang See.
This driver has been taking too long:
http://patchwork.ozlabs.org/patch/381305/

Changes in v3: None
Changes in v2:
  - Avoid unaligned access
  - Replace a magic number 0x2000 with PIPELINE_ACCESS

 drivers/mtd/nand/Makefile |   1 +
 drivers/mtd/nand/denali_spl.c | 245 ++
 2 files changed, 246 insertions(+)
 create mode 100644 drivers/mtd/nand/denali_spl.c

diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index bf1312a..f90f9a0 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -12,6 +12,7 @@ NORMAL_DRIVERS=y
 endif
 
 obj-$(CONFIG_SPL_NAND_AM33XX_BCH) += am335x_spl_bch.o
+obj-$(CONFIG_SPL_NAND_DENALI) += denali_spl.o
 obj-$(CONFIG_SPL_NAND_DOCG4) += docg4_spl.o
 obj-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o
 obj-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o
diff --git a/drivers/mtd/nand/denali_spl.c b/drivers/mtd/nand/denali_spl.c
new file mode 100644
index 000..ab23743
--- /dev/null
+++ b/drivers/mtd/nand/denali_spl.c
@@ -0,0 +1,245 @@
+/*
+ * Copyright (C) 2014   Panasonic Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#if 0
+#include "denali.h"
+#else
+/* workaround until denali.h is merged */
+#define TRANSFER_SPARE_REG 0x10
+#define ECC_ENABLE 0xe0
+#define PAGES_PER_BLOCK0x150
+#define DEVICE_MAIN_AREA_SIZE  0x170
+#define DEVICE_SPARE_AREA_SIZE 0x180
+
+#define INTR_STATUS(__bank)(0x410 + ((__bank) * 0x50))
+#define INTR_STATUS__ECC_UNCOR_ERR 0x0001
+#define INTR_STATUS__LOAD_COMP 0x0040
+
+#define INDEX_CTRL_REG0x0
+#define INDEX_DATA_REG0x10
+#define MODE_010x0400
+#define MODE_100x0800
+#endif
+
+#define SPARE_ACCESS   0x41
+#define MAIN_ACCESS0x42
+#define PIPELINE_ACCESS0x2000
+
+#define BANK(x) ((x) << 24)
+
+static void __iomem *denali_flash_mem =
+   (void __iomem *)CONFIG_SYS_NAND_DATA_BASE;
+static void __iomem *denali_flash_reg =
+   (void __iomem *)CONFIG_SYS_NAND_REGS_BASE;
+
+static const int flash_bank;
+static uint8_t page_buffer[NAND_MAX_PAGESIZE];
+static int page_size, oob_size, pages_per_block;
+
+static void index_addr(uint32_t address, uint32_t data)
+{
+   writel(address, denali_flash_mem + INDEX_CTRL_REG);
+   writel(data, denali_flash_mem + INDEX_DATA_REG);
+}
+
+static int wait_for_irq(uint32_t irq_mask)
+{
+   unsigned long timeout = 100;
+   uint32_t intr_status;
+
+   do {
+   intr_status = readl(denali_flash_reg + INTR_STATUS(flash_bank));
+
+   if (intr_status & INTR_STATUS__ECC_UNCOR_ERR) {
+   debug("Uncorrected ECC detected\n");
+   return -EIO;
+   }
+
+   if (intr_status & irq_mask)
+   break;
+
+   udelay(1);
+   timeout--;
+   } while (timeout);
+
+   if (!timeout) {
+   debug("Timeout with interrupt status %08x\n", intr_status);
+   return -EIO;
+   }
+
+   return 0;
+}
+
+static void read_data_from_flash_mem(uint8_t *buf, int len)
+{
+   int i;
+   uint32_t *buf32;
+
+   /* transfer the data from the flash */
+   buf32 = (uint32_t *)buf;
+
+   /*
+* Let's take care of unaligned access although it rarely happens.
+* Avoid put_unaligned() for the normal use cases since it leads to
+* a bit performance regression.
+*/
+   if ((unsigned long)buf32 % 4) {
+   for (i = 0; i < len / 4; i++)
+   put_unaligned(readl(denali_flash_mem + INDEX_DATA_REG),
+ buf32++);
+   } else {
+   for (i = 0; i < len / 4; i++)
+   *buf32++ = readl(denali_flash_mem + INDEX_DATA_REG);
+   }
+
+   if (len % 4) {
+   u32 tmp;
+
+   tmp = cpu_to_le32(readl(denali_flash_mem + INDEX_DATA_REG));
+   buf = (uint8_t *)buf32;
+   for (i = 0; i < len % 4; i++) {
+   *buf++ = tmp;
+   tmp >>= 8;
+   }
+   }
+}
+
+int denali_send_pipeline_cmd(int page, int ecc_en, int access_type)
+{
+   uint32_t addr, cmd;
+   static uint32_t page_count = 1;
+
+   writel(ecc_en, denal

[U-Boot] [PATCH v4 2/6] serial: add UniPhier serial driver

[Masahiro Yamada]

The driver for on-chip UART used on Panasonic UniPhier platform.

Signed-off-by: Masahiro Yamada 
---

Changes in v4: None
Changes in v3: None
Changes in v2:
  - Use "const unsigned int mode_x_div = 16"
  instead of "#define MODE_X_DIV   16"
  - Use DIV_ROUND_CLOSEST() macro to compute the divisor

 drivers/serial/Makefile  |   1 +
 drivers/serial/serial.c  |   2 +
 drivers/serial/serial_uniphier.c | 204 +++
 3 files changed, 207 insertions(+)
 create mode 100644 drivers/serial/serial_uniphier.c

diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 571c18f..385b2f9 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -34,6 +34,7 @@ obj-$(CONFIG_BFIN_SERIAL) += serial_bfin.o
 obj-$(CONFIG_FSL_LPUART) += serial_lpuart.o
 obj-$(CONFIG_MXS_AUART) += mxs_auart.o
 obj-$(CONFIG_ARC_SERIAL) += serial_arc.o
+obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o
 
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_USB_TTY) += usbtty.o
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index d2eb752..d32673e 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -157,6 +157,7 @@ serial_initfunc(sh_serial_initialize);
 serial_initfunc(arm_dcc_initialize);
 serial_initfunc(mxs_auart_initialize);
 serial_initfunc(arc_serial_initialize);
+serial_initfunc(uniphier_serial_initialize);
 
 /**
  * serial_register() - Register serial driver with serial driver core
@@ -250,6 +251,7 @@ void serial_initialize(void)
arm_dcc_initialize();
mxs_auart_initialize();
arc_serial_initialize();
+   uniphier_serial_initialize();
 
serial_assign(default_serial_console()->name);
 }
diff --git a/drivers/serial/serial_uniphier.c b/drivers/serial/serial_uniphier.c
new file mode 100644
index 000..f8c9d92
--- /dev/null
+++ b/drivers/serial/serial_uniphier.c
@@ -0,0 +1,204 @@
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada 
+ *
+ * Based on serial_ns16550.c
+ * (C) Copyright 2000
+ * Rob Taylor, Flying Pig Systems. r...@flyingpig.com.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+
+#define UART_REG(x)\
+   u8 x;   \
+   u8 postpad_##x[3];
+
+/*
+ * Note: Register map is slightly different from that of 16550.
+ */
+struct uniphier_serial {
+   UART_REG(rbr);  /* 0x00 */
+   UART_REG(ier);  /* 0x04 */
+   UART_REG(iir);  /* 0x08 */
+   UART_REG(fcr);  /* 0x0c */
+   u8 mcr; /* 0x10 */
+   u8 lcr;
+   u16 __postpad;
+   UART_REG(lsr);  /* 0x14 */
+   UART_REG(msr);  /* 0x18 */
+   u32 __none1;
+   u32 __none2;
+   u16 dlr;
+   u16 __postpad2;
+};
+
+#define thr rbr
+
+/*
+ * These are the definitions for the Line Control Register
+ */
+#define UART_LCR_WLS_8 0x03/* 8 bit character length */
+
+/*
+ * These are the definitions for the Line Status Register
+ */
+#define UART_LSR_DR0x01/* Data ready */
+#define UART_LSR_THRE  0x20/* Xmit holding register empty */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void uniphier_serial_init(struct uniphier_serial *port)
+{
+   const unsigned int mode_x_div = 16;
+   unsigned int divisor;
+
+   writeb(UART_LCR_WLS_8, &port->lcr);
+
+   divisor = DIV_ROUND_CLOSEST(CONFIG_SYS_UNIPHIER_UART_CLK,
+   mode_x_div * gd->baudrate);
+
+   writew(divisor, &port->dlr);
+}
+
+static void uniphier_serial_setbrg(struct uniphier_serial *port)
+{
+   uniphier_serial_init(port);
+}
+
+static int uniphier_serial_tstc(struct uniphier_serial *port)
+{
+   return (readb(&port->lsr) & UART_LSR_DR) != 0;
+}
+
+static int uniphier_serial_getc(struct uniphier_serial *port)
+{
+   while (!uniphier_serial_tstc(port))
+   ;
+
+   return readb(&port->rbr);
+}
+
+static void uniphier_serial_putc(struct uniphier_serial *port, const char c)
+{
+   if (c == '\n')
+   uniphier_serial_putc(port, '\r');
+
+   while (!(readb(&port->lsr) & UART_LSR_THRE))
+   ;
+
+   writeb(c, &port->thr);
+}
+
+static struct uniphier_serial *serial_ports[4] = {
+#ifdef CONFIG_SYS_UNIPHIER_SERIAL_BASE0
+   (struct uniphier_serial *)CONFIG_SYS_UNIPHIER_SERIAL_BASE0,
+#else
+   NULL,
+#endif
+#ifdef CONFIG_SYS_UNIPHIER_SERIAL_BASE1
+   (struct uniphier_serial *)CONFIG_SYS_UNIPHIER_SERIAL_BASE1,
+#else
+   NULL,
+#endif
+#ifdef CONFIG_SYS_UNIPHIER_SERIAL_BASE2
+   (struct uniphier_serial *)CONFIG_SYS_UNIPHIER_SERIAL_BASE2,
+#else
+   NULL,
+#endif
+#ifdef CONFIG_SYS_UNIPHIER_SERIAL_BASE3
+   (struct uniphier_serial *)CONFIG_SYS_UNIPHIER_SERIAL_BASE3,
+#else
+   NULL,
+#endif
+};
+
+/* Multi serial device functions */
+#define DECLARE_ESERIAL_FUNCTIONS(port) \
+   static int  es

[U-Boot] [PATCH v4 4/6] arm: uniphier: add Kconfig and defconfig

[Masahiro Yamada]

Add entries for Panasonic UniPhier family:
PH1-LD4, PH1-Pro4, PH1-sLD8

Signed-off-by: Masahiro Yamada 
---

Changes in v4: None
Changes in v3:
  - Rebase on the current u-boot/master

Changes in v2:
  - Rebase on the current u-boot/master

 arch/arm/Kconfig|  5 +
 arch/arm/cpu/armv7/uniphier/Kconfig | 32 
 configs/ph1_ld4_defconfig   |  4 
 configs/ph1_pro4_defconfig  |  4 
 configs/ph1_sld8_defconfig  |  4 
 5 files changed, 49 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/uniphier/Kconfig
 create mode 100644 configs/ph1_ld4_defconfig
 create mode 100644 configs/ph1_pro4_defconfig
 create mode 100644 configs/ph1_sld8_defconfig

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 22f0f09..9a35639 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -509,6 +509,9 @@ config TARGET_COLIBRI_PXA270
 config TARGET_JORNADA
bool "Support jornada"
 
+config ARCH_UNIPHIER
+   bool "Panasonic UniPhier platform"
+
 endchoice
 
 source "arch/arm/cpu/arm926ejs/davinci/Kconfig"
@@ -535,6 +538,8 @@ source "arch/arm/cpu/armv7/rmobile/Kconfig"
 
 source "arch/arm/cpu/armv7/tegra-common/Kconfig"
 
+source "arch/arm/cpu/armv7/uniphier/Kconfig"
+
 source "arch/arm/cpu/arm926ejs/versatile/Kconfig"
 
 source "arch/arm/cpu/armv7/zynq/Kconfig"
diff --git a/arch/arm/cpu/armv7/uniphier/Kconfig 
b/arch/arm/cpu/armv7/uniphier/Kconfig
new file mode 100644
index 000..34f5496
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/Kconfig
@@ -0,0 +1,32 @@
+menu "Panasonic UniPhier platform"
+   depends on ARCH_UNIPHIER
+
+config SYS_CPU
+   string
+   default "armv7"
+
+config SYS_SOC
+   string
+   default "uniphier"
+
+config SYS_CONFIG_NAME
+   string
+   default "ph1_pro4" if MACH_PH1_PRO4
+   default "ph1_ld4" if MACH_PH1_LD4
+   default "ph1_sld8" if MACH_PH1_SLD8
+
+choice
+   prompt "UniPhier SoC select"
+
+config MACH_PH1_PRO4
+   bool "PH1-Pro4"
+
+config MACH_PH1_LD4
+   bool "PH1-LD4"
+
+config MACH_PH1_SLD8
+   bool "PH1-sLD8"
+
+endchoice
+
+endmenu
diff --git a/configs/ph1_ld4_defconfig b/configs/ph1_ld4_defconfig
new file mode 100644
index 000..d6fcb25
--- /dev/null
+++ b/configs/ph1_ld4_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SPL=y
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_UNIPHIER=y
++S:CONFIG_MACH_PH1_LD4=y
diff --git a/configs/ph1_pro4_defconfig b/configs/ph1_pro4_defconfig
new file mode 100644
index 000..557b3aa
--- /dev/null
+++ b/configs/ph1_pro4_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SPL=y
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_UNIPHIER=y
++S:CONFIG_MACH_PH1_PRO4=y
diff --git a/configs/ph1_sld8_defconfig b/configs/ph1_sld8_defconfig
new file mode 100644
index 000..8028d12
--- /dev/null
+++ b/configs/ph1_sld8_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SPL=y
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_UNIPHIER=y
++S:CONFIG_MACH_PH1_SLD8=y
-- 
1.9.1

___
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[U-Boot] [PATCH v4 5/6] MAINTAINERS: add me as a maintainer of UniPhier platform

[Masahiro Yamada]

Signed-off-by: Masahiro Yamada 
---

Changes in v4: None
Changes in v3: None
Changes in v2:
  - Newly added

 MAINTAINERS | 8 
 1 file changed, 8 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index af194ca..cb5b3f0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -149,6 +149,14 @@ F: arch/arm/include/asm/arch-davinci/
 F: arch/arm/include/asm/arch-omap*/
 F: arch/arm/include/asm/ti-common/
 
+ARM UNIPHIER
+M: Masahiro Yamada 
+S: Maintained
+F: arch/arm/cpu/armv7/uniphier/
+F: arch/arm/include/asm/arch-uniphier/
+F: configs/ph1_*_defconfig
+F: drivers/serial/serial_uniphier.c
+
 ARM ZYNQ
 M: Michal Simek 
 S: Maintained
-- 
1.9.1

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[U-Boot] [PATCH v4 6/6] git-mailrc: add me as a maintainer of UniPhier platform

[Masahiro Yamada]

Signed-off-by: Masahiro Yamada 
---

Changes in v4: None
Changes in v3: None
Changes in v2:
  - Rebase

 doc/git-mailrc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/doc/git-mailrc b/doc/git-mailrc
index 0fba100..35f2eb2 100644
--- a/doc/git-mailrc
+++ b/doc/git-mailrc
@@ -63,6 +63,7 @@ alias sunxi  uboot, ijc, jwrdegoede
 alias tegra  uboot, sjg, Tom Warren , Stephen 
Warren 
 alias tegra2 tegra
 alias ti uboot, trini
+alias uniphier   uboot, masahiro
 alias zynq   uboot, monstr
 
 alias avr32  uboot, abiessmann
-- 
1.9.1

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Re: [U-Boot] [PATCH v8 00/12] Add support to Odroid U3/X2

[Minkyu Kang]

On 01/09/14 20:50, Przemyslaw Marczak wrote:
> This patch set introduces changes to common Samsung code
> as a preparation of new board support:
> - boot device check - code cleanup
> - automatic init order of mmc drivers
> - automatic setting of dfu entities which depends on boot device
> - pre reset function call for board own implementation
> - setting board info environment for multi board support
> 
> New board config:
> - odroid_config - Odroid U3/X2 support
> 
> V8 changes:
> - patchset adjust to Kconfig
> 
> Przemyslaw Marczak (12):
>   samsung: misc: fix soc revision setting in the set_board_info()
>   exynos: pinmux: fix the gpio names for exynos4x12 mmc
>   arch:exynos: boot mode: add get_boot_mode(), code cleanup
>   board:samsung: check the boot device and init the right mmc driver.
>   samsung: misc: add function for setting $dfu_alt_info
>   samsung:board: misc_init_r: call set_dfu_alt_info()
>   arm:reset: call the reset_misc() before the cpu reset
>   samsung: board: enable support of multiple board types
>   samsung: misc: use board specific functions to set env board info
>   odroid: add board file for Odroid X2/U3 based on Samsung Exynos4412
>   odroid: add odroid U3/X2 device tree description
>   odroid: kconfig: add odroid_defconfig
> 
>  arch/arm/cpu/armv7/exynos/Kconfig|   4 +
>  arch/arm/cpu/armv7/exynos/pinmux.c   |   4 +-
>  arch/arm/cpu/armv7/exynos/power.c|   7 +
>  arch/arm/cpu/armv7/exynos/spl_boot.c |   7 +-
>  arch/arm/dts/Makefile|   3 +-
>  arch/arm/dts/exynos4412-odroid.dts   |  70 +
>  arch/arm/include/asm/arch-exynos/power.h |  21 ++
>  arch/arm/include/asm/arch-exynos/spl.h   |  17 +-
>  arch/arm/lib/reset.c |   6 +
>  board/samsung/common/board.c |  55 +++-
>  board/samsung/common/misc.c  |  57 +++-
>  board/samsung/odroid/Kconfig |  15 +
>  board/samsung/odroid/MAINTAINERS |   6 +
>  board/samsung/odroid/Makefile|   8 +
>  board/samsung/odroid/odroid.c| 470 
> +++
>  board/samsung/odroid/setup.h | 255 +
>  configs/odroid_defconfig |   3 +
>  doc/README.odroid| 143 ++
>  include/common.h |   1 +
>  include/configs/odroid.h | 216 ++
>  include/samsung/misc.h   |  10 +
>  21 files changed, 1337 insertions(+), 41 deletions(-)
>  create mode 100644 arch/arm/dts/exynos4412-odroid.dts
>  create mode 100644 board/samsung/odroid/Kconfig
>  create mode 100644 board/samsung/odroid/MAINTAINERS
>  create mode 100644 board/samsung/odroid/Makefile
>  create mode 100644 board/samsung/odroid/odroid.c
>  create mode 100644 board/samsung/odroid/setup.h
>  create mode 100644 configs/odroid_defconfig
>  create mode 100644 doc/README.odroid
>  create mode 100644 include/configs/odroid.h
> 

applied to u-boot-samsung

Thanks,
Minkyu Kang.
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[U-Boot] [PATCH v6 0/17] arm: ls102xa: Add Freescale LS102xA SoC and LS1021AQDS/TWR board support

[Alison Wang]

This series contain the support for Freescale LS102xA SoC and LS1021AQDS/TWR 
board.

The QorIQ LS1 family is built on Layerscape architecture, the industry's first
software-aware, core-agnostic networking architecture to offer unprecedented
efficiency and scale.

Freescale LS102xA is a set of SoCs combines two ARM Cortex-A7 cores that have
been optimized for high reliability and pack the highest level of integration
available for sub-3 W embedded communications processors with Layerscape
architecture and with a comprehensive enablement model focused on ease of
programmability.

For the detail information about LS1021AQDS/TWR board, please refer to README 
in the patch.

Changes in v6:
- Fix checkpatch warnings.
- Use #define instead of magic numbers.
- Remove redundant codes.
- Give more detail commits.
- Move OCRAM_BASE_ADDR and OCRAM_SIZE to soc config.
- Change NS16550 fdt node's name according the update in kernel.
- Split ESDHC patch into two parts.

Changes in v5:
- Remove private MDIO read/write functions. Handling the board
  muxing between the RGMII/SGMII phys in eth.c.
- Add detailed commit messages for I2C patch.
- Adjust the video patches' order.
- Remove LETECH patch, as it is used internally, maybe send out later.

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[U-Boot] [PATCH v6 05/17] ls102xa: etsec: Add etsec support for LS102xA

[Alison Wang]

This patch is to add etsec support for LS102xA. First, Little-endian
descriptor mode should be enabled. So RxBDs and TxBDs are interpreted
with little-endian byte ordering. Second, TSEC_SIZE and TSEC_MDIO_OFFSET
are different from PowerPC, redefine them for LS1021xA.

Signed-off-by: Alison Wang 
---
Change log:
 v6: Fix checkpatch error.
 Make the commit more clear.
 v5: No change.
 v4: No change.
 v3: No change.
 v2: Add private mdio read and write support.

 drivers/net/tsec.c | 7 +++
 include/tsec.h | 7 ++-
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index e9138f0..79d6561 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -20,6 +20,7 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -270,6 +271,9 @@ void redundant_init(struct eth_device *dev)
out_be32(®s->tstat, TSTAT_CLEAR_THALT);
out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
+#ifdef CONFIG_LS102XA
+   setbits_be32(®s->dmactrl, DMACTRL_LE);
+#endif
 
do {
uint16_t status;
@@ -366,6 +370,9 @@ static void startup_tsec(struct eth_device *dev)
out_be32(®s->tstat, TSTAT_CLEAR_THALT);
out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
+#ifdef CONFIG_LS102XA
+   setbits_be32(®s->dmactrl, DMACTRL_LE);
+#endif
 }
 
 /* This returns the status bits of the device. The return value
diff --git a/include/tsec.h b/include/tsec.h
index 2054715..1119d2c 100644
--- a/include/tsec.h
+++ b/include/tsec.h
@@ -20,10 +20,14 @@
 #include 
 #include 
 #include 
-#include 
 
+#ifdef CONFIG_LS102XA
+#define TSEC_SIZE  0x4
+#define TSEC_MDIO_OFFSET   0x4
+#else
 #define TSEC_SIZE  0x01000
 #define TSEC_MDIO_OFFSET   0x01000
+#endif
 
 #define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + 0x520)
 
@@ -128,6 +132,7 @@
 #define DMACTRL_INIT_SETTINGS  0x00c3
 #define DMACTRL_GRS0x0010
 #define DMACTRL_GTS0x0008
+#define DMACTRL_LE 0x8000
 
 #define TSTAT_CLEAR_THALT  0x8000
 #define RSTAT_CLEAR_RHALT  0x0080
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v6 03/17] net: Merge asm/fsl_enet.h into fsl_mdio.h

[Alison Wang]

From: Claudiu Manoil 

fsl_enet.h defines the mapping of the usual MII management
registers, which are included in the MDIO register block
common to Freescale ethernet controllers. So it shouldn't
depend on the CPU architecture but it should be actually
part of the arch independent fsl_mdio.h.

To remove the arch dependency, merge the content of
asm/fsl_enet.h into fsl_mdio.h.
Some files (like fm_eth.h) were simply including fsl_enet.h
only for phy.h. These were updated to include phy.h instead.

Signed-off-by: Claudiu Manoil 
---
Change log:
 v6: Fix checkpatch error.
 v5: No change.
 v4: No change.
 v3: No change.
 v2: No change.

 arch/powerpc/include/asm/fsl_enet.h   | 24 
 board/freescale/mpc8360emds/mpc8360emds.c |  2 +-
 board/freescale/mpc837xemds/mpc837xemds.c |  1 -
 drivers/net/fm/dtsec.c|  1 -
 drivers/net/fm/fm.h   |  2 +-
 drivers/net/fm/init.c |  1 +
 drivers/net/fm/memac.c|  1 -
 drivers/net/fm/tgec.c |  1 -
 drivers/net/fsl_mdio.c|  1 -
 drivers/qe/uec.h  |  1 -
 include/fm_eth.h  |  2 +-
 include/fsl_mdio.h| 13 -
 include/tsec.h|  2 +-
 13 files changed, 17 insertions(+), 35 deletions(-)
 delete mode 100644 arch/powerpc/include/asm/fsl_enet.h

diff --git a/arch/powerpc/include/asm/fsl_enet.h 
b/arch/powerpc/include/asm/fsl_enet.h
deleted file mode 100644
index 96146b6..000
--- a/arch/powerpc/include/asm/fsl_enet.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright 2010 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-
-#ifndef __ASM_PPC_FSL_ENET_H
-#define __ASM_PPC_FSL_ENET_H
-
-#include 
-
-struct tsec_mii_mng {
-   u32 miimcfg;/* MII management configuration reg */
-   u32 miimcom;/* MII management command reg */
-   u32 miimadd;/* MII management address reg */
-   u32 miimcon;/* MII management control reg */
-   u32 miimstat;   /* MII management status reg  */
-   u32 miimind;/* MII management indication reg */
-   u32 ifstat; /* Interface Status Register */
-} __attribute__ ((packed));
-
-int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc);
-
-#endif /* __ASM_PPC_FSL_ENET_H */
diff --git a/board/freescale/mpc8360emds/mpc8360emds.c 
b/board/freescale/mpc8360emds/mpc8360emds.c
index ac96163..5ff9dff 100644
--- a/board/freescale/mpc8360emds/mpc8360emds.c
+++ b/board/freescale/mpc8360emds/mpc8360emds.c
@@ -11,13 +11,13 @@
 #include 
 #include 
 #include 
+#include 
 #if defined(CONFIG_PCI)
 #include 
 #endif
 #include 
 #include 
 #include 
-#include 
 #include 
 #if defined(CONFIG_OF_LIBFDT)
 #include 
diff --git a/board/freescale/mpc837xemds/mpc837xemds.c 
b/board/freescale/mpc837xemds/mpc837xemds.c
index 0a3c972..c749e55 100644
--- a/board/freescale/mpc837xemds/mpc837xemds.c
+++ b/board/freescale/mpc837xemds/mpc837xemds.c
@@ -10,7 +10,6 @@
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
diff --git a/drivers/net/fm/dtsec.c b/drivers/net/fm/dtsec.c
index 78bbd43..8d3dc0e 100644
--- a/drivers/net/fm/dtsec.c
+++ b/drivers/net/fm/dtsec.c
@@ -7,7 +7,6 @@
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
diff --git a/drivers/net/fm/fm.h b/drivers/net/fm/fm.h
index 316e06e..a9691c6 100644
--- a/drivers/net/fm/fm.h
+++ b/drivers/net/fm/fm.h
@@ -8,8 +8,8 @@
 #define __FM_H__
 
 #include 
+#include 
 #include 
-#include 
 #include 
 
 /* Port ID */
diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c
index ff04695..6cf21c6 100644
--- a/drivers/net/fm/init.c
+++ b/drivers/net/fm/init.c
@@ -6,6 +6,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "fm.h"
 
diff --git a/drivers/net/fm/memac.c b/drivers/net/fm/memac.c
index 592a67f..9499290 100644
--- a/drivers/net/fm/memac.c
+++ b/drivers/net/fm/memac.c
@@ -12,7 +12,6 @@
 #include 
 #include 
 #include 
-#include 
 #include 
 
 #include "fm.h"
diff --git a/drivers/net/fm/tgec.c b/drivers/net/fm/tgec.c
index f450f80..5017123 100644
--- a/drivers/net/fm/tgec.c
+++ b/drivers/net/fm/tgec.c
@@ -12,7 +12,6 @@
 #include 
 #include 
 #include 
-#include 
 #include 
 
 #include "fm.h"
diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c
index 1d88e65..8d09f5d 100644
--- a/drivers/net/fsl_mdio.c
+++ b/drivers/net/fsl_mdio.c
@@ -11,7 +11,6 @@
 #include 
 #include 
 #include 
-#include 
 
 void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr,
int dev_addr, int regnum, int value)
diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h
index 48a1634..6b559f7 100644
--- a/drivers/qe/uec.h
+++ b/drivers/qe/uec.h
@@ -13,7 +13,6 @@
 #include "qe.h"
 #include "uccf.h"
 #include 
-#include 
 
 #define MAX_TX_THREADS   

[U-Boot] [PATCH v6 04/17] net: mdio: Use mb() to be compatible for both ARM and PowerPC

[Alison Wang]

Use mb() instead of sync assembly instruction to be
compatible for both ARM and PowerPC.

Signed-off-by: Alison Wang 
---
Change log:
 v6: Fix checkpatch error.
 v5: No change.
 v4: No change.
 v3: Use mb() to be compatible for both ARM and PowerPC.
 Split from the 0004-arm-ls102xa-Add-etsec-support-for-LS102xA patch.
 v2: Add private mdio read and write support.

 drivers/net/fsl_mdio.c | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c
index 8d09f5d..d6b181b 100644
--- a/drivers/net/fsl_mdio.c
+++ b/drivers/net/fsl_mdio.c
@@ -19,7 +19,8 @@ void tsec_local_mdio_write(struct tsec_mii_mng __iomem 
*phyregs, int port_addr,
 
out_be32(&phyregs->miimadd, (port_addr << 8) | (regnum & 0x1f));
out_be32(&phyregs->miimcon, value);
-   asm("sync");
+   /* Memory barrier */
+   mb();
 
while ((in_be32(&phyregs->miimind) & MIIMIND_BUSY) && timeout--)
;
@@ -37,11 +38,13 @@ int tsec_local_mdio_read(struct tsec_mii_mng __iomem 
*phyregs, int port_addr,
 
/* Clear the command register, and wait */
out_be32(&phyregs->miimcom, 0);
-   asm("sync");
+   /* Memory barrier */
+   mb();
 
/* Initiate a read command, and wait */
out_be32(&phyregs->miimcom, MIIMCOM_READ_CYCLE);
-   asm("sync");
+   /* Memory barrier */
+   mb();
 
/* Wait for the the indication that the read is done */
while ((in_be32(&phyregs->miimind) & (MIIMIND_NOTVALID | MIIMIND_BUSY))
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v6 01/17] arm: ls102xa: Add Freescale LS102xA SoC support

[Alison Wang]

From: Wang Huan 

The QorIQ LS1 family is built on Layerscape architecture,
the industry's first software-aware, core-agnostic networking
architecture to offer unprecedented efficiency and scale.

Freescale LS102xA is a set of SoCs combines two ARM
Cortex-A7 cores that have been optimized for high
reliability and pack the highest level of integration
available for sub-3 W embedded communications processors
with Layerscape architecture and with a comprehensive
enablement model focused on ease of programmability.

Signed-off-by: Alison Wang 
Signed-off-by: Jason Jin 
Signed-off-by: Jingchang Lu 
Signed-off-by: Prabhakar Kushwaha 
---
Change log:
 v6: Fix checkpatch errors.
 Add macros to avoid using magic numbers.
 Move OCRAM_BASE_ADDR and OCRAM_SIZE to soc config.
 Change NS16550 fdt node's name according the update in kernel. 
 v5: No change.
 v4: No change.
 v3: Fix checkpatch errors.
 v2: Add serdes support.
 Update DDR frequency and data rate information.
 Fix overflow condition error for the timer.

 arch/arm/cpu/armv7/ls102xa/Makefile   |  12 +
 arch/arm/cpu/armv7/ls102xa/clock.c| 130 ++
 arch/arm/cpu/armv7/ls102xa/cpu.c  | 103 +
 arch/arm/cpu/armv7/ls102xa/fdt.c  | 136 ++
 arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c   | 120 ++
 arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.h   |  12 +
 arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c   |  41 ++
 arch/arm/cpu/armv7/ls102xa/timer.c| 127 ++
 arch/arm/include/asm/arch-ls102xa/clock.h |  23 +
 arch/arm/include/asm/arch-ls102xa/config.h|  74 
 arch/arm/include/asm/arch-ls102xa/fsl_serdes.h|  33 ++
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 493 ++
 arch/arm/include/asm/arch-ls102xa/imx-regs.h  |  53 +++
 arch/arm/include/asm/config.h |   4 +
 arch/arm/include/asm/io.h |   8 +-
 drivers/watchdog/Makefile |   2 +-
 16 files changed, 1369 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/ls102xa/Makefile
 create mode 100644 arch/arm/cpu/armv7/ls102xa/clock.c
 create mode 100644 arch/arm/cpu/armv7/ls102xa/cpu.c
 create mode 100644 arch/arm/cpu/armv7/ls102xa/fdt.c
 create mode 100644 arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c
 create mode 100644 arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.h
 create mode 100644 arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c
 create mode 100644 arch/arm/cpu/armv7/ls102xa/timer.c
 create mode 100644 arch/arm/include/asm/arch-ls102xa/clock.h
 create mode 100644 arch/arm/include/asm/arch-ls102xa/config.h
 create mode 100644 arch/arm/include/asm/arch-ls102xa/fsl_serdes.h
 create mode 100644 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
 create mode 100644 arch/arm/include/asm/arch-ls102xa/imx-regs.h

diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile 
b/arch/arm/cpu/armv7/ls102xa/Makefile
new file mode 100644
index 000..d82ce8d
--- /dev/null
+++ b/arch/arm/cpu/armv7/ls102xa/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:  GPL-2.0+
+#
+
+obj-y  += cpu.o
+obj-y  += clock.o
+obj-y  += timer.o
+
+obj-$(CONFIG_OF_LIBFDT) += fdt.o
+obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o
diff --git a/arch/arm/cpu/armv7/ls102xa/clock.c 
b/arch/arm/cpu/armv7/ls102xa/clock.c
new file mode 100644
index 000..8f80c61
--- /dev/null
+++ b/arch/arm/cpu/armv7/ls102xa/clock.c
@@ -0,0 +1,130 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
+#define CONFIG_SYS_FSL_NUM_CC_PLLS  2
+#endif
+
+void get_sys_info(struct sys_info *sys_info)
+{
+   struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+#ifdef CONFIG_FSL_IFC
+   struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
+   u32 ccr;
+#endif
+   struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_LS1_CLK_ADDR);
+   unsigned int cpu;
+   const u8 core_cplx_pll[6] = {
+   [0] = 0,/* CC1 PPL / 1 */
+   [1] = 0,/* CC1 PPL / 2 */
+   [4] = 1,/* CC2 PPL / 1 */
+   [5] = 1,/* CC2 PPL / 2 */
+   };
+
+   const u8 core_cplx_pll_div[6] = {
+   [0] = 1,/* CC1 PPL / 1 */
+   [1] = 2,/* CC1 PPL / 2 */
+   [4] = 1,/* CC2 PPL / 1 */
+   [5] = 2,/* CC2 PPL / 2 */
+   };
+
+   uint i;
+   uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
+   uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
+   unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
+
+   sys_info->freq_systembus = sysclk;
+#ifdef CONFIG_DDR_CLK_FREQ
+   sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
+#else
+   sys_info->freq_ddrbus 

[U-Boot] [PATCH v6 06/17] esdhc: Add CONFIG_SYS_FSL_ESDHC_LE and CONFIG_SYS_FSL_ESDHC_BE macros

[Alison Wang]

From: Wang Huan 

For LS102xA, the processor is in little-endian mode, while esdhc IP is
in big-endian mode. CONFIG_SYS_FSL_ESDHC_LE and CONFIG_SYS_FSL_ESDHC_BE
are added. So accessing ESDHC registers can be determined by ESDHC IP's
endian mode.

Signed-off-by: Alison Wang 
---
Change log:
 v6: New patch. Split from the v5's 06 patch.

 doc/README.fsl-esdhc |  5 +
 include/fsl_esdhc.h  | 14 +-
 2 files changed, 18 insertions(+), 1 deletion(-)
 create mode 100644 doc/README.fsl-esdhc

diff --git a/doc/README.fsl-esdhc b/doc/README.fsl-esdhc
new file mode 100644
index 000..b70f271
--- /dev/null
+++ b/doc/README.fsl-esdhc
@@ -0,0 +1,5 @@
+CONFIG_SYS_FSL_ESDHC_LE means ESDHC IP is in little-endian mode.
+CONFIG_SYS_FSL_ESDHC_BE means ESDHC IP is in big-endian mode.
+
+Accessing ESDHC registers can be determined by ESDHC IP's endian
+mode or processor's endian mode.
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index 9814964..c1b6648 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -162,7 +162,19 @@ struct fsl_esdhc_cfg {
 };
 
 /* Select the correct accessors depending on endianess */
-#if __BYTE_ORDER == __LITTLE_ENDIAN
+#if defined CONFIG_SYS_FSL_ESDHC_LE
+#define esdhc_read32   in_le32
+#define esdhc_write32  out_le32
+#define esdhc_clrsetbits32 clrsetbits_le32
+#define esdhc_clrbits32clrbits_le32
+#define esdhc_setbits32setbits_le32
+#elif defined(CONFIG_SYS_FSL_ESDHC_BE)
+#define esdhc_read32in_be32
+#define esdhc_write32   out_be32
+#define esdhc_clrsetbits32  clrsetbits_be32
+#define esdhc_clrbits32 clrbits_be32
+#define esdhc_setbits32 setbits_be32
+#elif __BYTE_ORDER == __LITTLE_ENDIAN
 #define esdhc_read32   in_le32
 #define esdhc_write32  out_le32
 #define esdhc_clrsetbits32 clrsetbits_le32
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v6 10/17] driver/ddr/fsl: Add support of overriding chip select write leveling

[Alison Wang]

From: York Sun 

JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This
is not an issue unless some DQ pins are not connected. If a platform uses
regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on
those floating pins for the second rank. The workaround is to use a known
good chip select for this purpose.

Signed-off-by: York Sun 
---
Change log:
 v6: No change.
 v5: No change.
 v4: No change.
 v3: No change.
 v2: No change.

 drivers/ddr/fsl/ctrl_regs.c   | 3 +++
 drivers/ddr/fsl/interactive.c | 2 ++
 include/fsl_ddr_sdram.h   | 2 ++
 3 files changed, 7 insertions(+)

diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 5e0ee77..d9cac22 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -2276,6 +2276,9 @@ compute_fsl_memctl_config_regs(const memctl_options_t 
*popts,
if (ip_rev > 0x40400)
unq_mrs_en = 1;
 
+   if (ip_rev > 0x40700)
+   ddr->debug[18] = popts->cswl_override;
+
set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
set_ddr_sdram_mode(ddr, popts, common_dimm,
cas_latency, additive_latency, unq_mrs_en);
diff --git a/drivers/ddr/fsl/interactive.c b/drivers/ddr/fsl/interactive.c
index 7fb4187..6aa16b2 100644
--- a/drivers/ddr/fsl/interactive.c
+++ b/drivers/ddr/fsl/interactive.c
@@ -511,6 +511,7 @@ static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo,
CTRL_OPTIONS(wrlvl_override),
CTRL_OPTIONS(wrlvl_sample),
CTRL_OPTIONS(wrlvl_start),
+   CTRL_OPTIONS(cswl_override),
CTRL_OPTIONS(rcw_override),
CTRL_OPTIONS(rcw_1),
CTRL_OPTIONS(rcw_2),
@@ -801,6 +802,7 @@ static void print_memctl_options(const memctl_options_t 
*popts)
CTRL_OPTIONS(wrlvl_override),
CTRL_OPTIONS(wrlvl_sample),
CTRL_OPTIONS(wrlvl_start),
+   CTRL_OPTIONS_HEX(cswl_override),
CTRL_OPTIONS(rcw_override),
CTRL_OPTIONS(rcw_1),
CTRL_OPTIONS(rcw_2),
diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h
index e8a2db9..987119b 100644
--- a/include/fsl_ddr_sdram.h
+++ b/include/fsl_ddr_sdram.h
@@ -281,6 +281,7 @@ typedef struct memctl_options_partial_s {
 #define DDR_DATA_BUS_WIDTH_64 0
 #define DDR_DATA_BUS_WIDTH_32 1
 #define DDR_DATA_BUS_WIDTH_16 2
+#define DDR_CSWL_CS0   0x0401
 /*
  * Generalized parameters for memory controller configuration,
  * might be a little specific to the FSL memory controller
@@ -340,6 +341,7 @@ typedef struct memctl_options_s {
unsigned int cpo_override;
unsigned int write_data_delay;  /* DQS adjust */
 
+   unsigned int cswl_override;
unsigned int wrlvl_override;
unsigned int wrlvl_sample;  /* Write leveling */
unsigned int wrlvl_start;
-- 
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[U-Boot] [PATCH v6 02/17] ls102xa: i2c: Add i2c support for LS102xA

[Alison Wang]

From: Wang Huan 

The existing i.MX's I2C driver mxc_i2c.c is compatible
with the controller of LS102xA. As I2C's registers
are 8-bit on LS102xA, I2C_QUIRK_REG is enabled to
use 8-bit driver.

This patch is to add I2C 1,2,3 support for LS102xA.

Signed-off-by: Alison Wang 
---
Change log:
 v6: Fix checkpatch error.
 v5: Add detailed commit messages.
 v4: Add commit messages.
 v3: Add I2C 3 support.
 v2: No change.

 drivers/i2c/mxc_i2c.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index c14797c..021b2fe 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -423,7 +423,7 @@ static void * const i2c_bases[] = {
(void *)IMX_I2C2_BASE
 #elif defined(CONFIG_MX31) || defined(CONFIG_MX35) || \
defined(CONFIG_MX51) || defined(CONFIG_MX53) || \
-   defined(CONFIG_MX6)
+   defined(CONFIG_MX6) || defined(CONFIG_LS102XA)
(void *)I2C1_BASE_ADDR,
(void *)I2C2_BASE_ADDR,
(void *)I2C3_BASE_ADDR
@@ -545,7 +545,7 @@ U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
 CONFIG_SYS_MXC_I2C2_SLAVE, 1)
 #if defined(CONFIG_MX31) || defined(CONFIG_MX35) ||\
defined(CONFIG_MX51) || defined(CONFIG_MX53) ||\
-   defined(CONFIG_MX6)
+   defined(CONFIG_MX6) || defined(CONFIG_LS102XA)
 U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
 mxc_i2c_read, mxc_i2c_write,
 mxc_i2c_set_bus_speed,
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH v6 09/17] driver/ddr/freescale: Fix DDR3 driver for ARM

[Alison Wang]

From: York Sun 

Reading DDR register should use ddr_in32() for proper endianess.
This patch fixes incorrect waiting time for ARM platforms.

Signed-off-by: York Sun 
---
Change log:
 v6: No change.
 v5: No change.
 v4: No change.
 v3: No change.
 v2: No change.

 drivers/ddr/fsl/arm_ddr_gen3.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c
index d4ed9ae..59f2fd6 100644
--- a/drivers/ddr/fsl/arm_ddr_gen3.c
+++ b/drivers/ddr/fsl/arm_ddr_gen3.c
@@ -194,7 +194,7 @@ step2:
 * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
 * Let's wait for 800ms
 */
-   bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
+   bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
>> SDRAM_CFG_DBW_SHIFT);
timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
(get_ddr_freq(0) >> 20)) << 1;
-- 
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[U-Boot] [PATCH v6 08/17] driver/ddr/freescale: Add support of accumulate ECC

[Alison Wang]

From: York Sun 

If less than 8 ECC pins are used for DDR data bus width smaller than 64
bits, the 8-bit ECC code will be transmitted/received across several beats,
and it will be used to check 64-bits of data once 8-bits of ECC are
accumulated.

Signed-off-by: York Sun 
---
Change log:
 v6: No change.
 v5: No change.
 v4: No change.
 v3: No change.
 v2: No change.

 drivers/ddr/fsl/ctrl_regs.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 04e4178..5e0ee77 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -693,6 +693,7 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
unsigned int x32_en = 0;/* x32 enable */
unsigned int pchb8 = 0; /* precharge bit 8 enable */
unsigned int hse;   /* Global half strength override */
+   unsigned int acc_ecc_en = 0;/* Accumulated ECC enable */
unsigned int mem_halt = 0;  /* memory controller halt */
unsigned int bi = 0;/* Bypass initialization */
 
@@ -736,6 +737,9 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
ba_intlv_ctl = popts->ba_intlv_ctl;
hse = popts->half_strength_driver_enable;
 
+   /* set when ddr bus width < 64 */
+   acc_ecc_en = (dbw != 0 && ecc_en == 1) ? 1 : 0;
+
ddr->ddr_sdram_cfg = (0
| ((mem_en & 0x1) << 31)
| ((sren & 0x1) << 30)
@@ -752,6 +756,7 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
| ((x32_en & 0x1) << 5)
| ((pchb8 & 0x1) << 4)
| ((hse & 0x1) << 3)
+   | ((acc_ecc_en & 0x1) << 2)
| ((mem_halt & 0x1) << 1)
| ((bi & 0x1) << 0)
);
-- 
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[U-Boot] [PATCH v6 13/17] net: tsec: Remove tx snooping support from LS1

[Alison Wang]

From: Claudiu Manoil 

Remove the DMCTRL Tx snooping bits (TDSEN and TBDSEN) as a
workaround for LS1.  It has been observed that currently
the Tx stops functioning after a fair amount of Tx traffic
with these settings on.  These bits are sticky and once set
they cannot be reset from Linux, for instance.

Signed-off-by: Claudiu Manoil 
---
Change log:
 v6: Fix checkpatch error.
 v5: No change.
 v4: No change.
 v3: New file.

 include/tsec.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/include/tsec.h b/include/tsec.h
index 1119d2c..58cdc19 100644
--- a/include/tsec.h
+++ b/include/tsec.h
@@ -129,7 +129,11 @@
 
 #define MINFLR_INIT_SETTINGS   0x0040
 
+#ifdef CONFIG_LS102XA
+#define DMACTRL_INIT_SETTINGS  0x0003
+#else
 #define DMACTRL_INIT_SETTINGS  0x00c3
+#endif
 #define DMACTRL_GRS0x0010
 #define DMACTRL_GTS0x0008
 #define DMACTRL_LE 0x8000
-- 
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[U-Boot] [PATCH v6 14/17] serial: lpuart: add 32-bit registers lpuart support

[Alison Wang]

From: Jingchang Lu 

On vybrid, lpuart's registers are 8-bit. On LS102xA, lpuart's registers
are 32-bit. This patch adds the support for 32-bit registers on
LS102xA.

Signed-off-by: Jingchang Lu 
Signed-off-by: Yuan Yao 
---
Change log:
 v6: Fix the influence to other board.
 v5: No change.
 v4: Add commit messages.
 v3: New file.

 drivers/serial/serial_lpuart.c | 118 +
 1 file changed, 118 insertions(+)

diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
index da5f9a2..b0c6f6f 100644
--- a/drivers/serial/serial_lpuart.c
+++ b/drivers/serial/serial_lpuart.c
@@ -17,10 +17,34 @@
 #define UC2_TE  (1 << 3)
 #define UC2_RE  (1 << 2)
 
+#define STAT_LBKDIF(1 << 31)
+#define STAT_RXEDGIF   (1 << 30)
+#define STAT_TDRE  (1 << 23)
+#define STAT_RDRF  (1 << 21)
+#define STAT_IDLE  (1 << 20)
+#define STAT_OR(1 << 19)
+#define STAT_NF(1 << 18)
+#define STAT_FE(1 << 17)
+#define STAT_PF(1 << 16)
+#define STAT_MA1F  (1 << 15)
+#define STAT_MA2F  (1 << 14)
+#define STAT_FLAGS (STAT_LBKDIF | STAT_RXEDGIF | STAT_IDLE | STAT_OR | \
+   STAT_NF | STAT_FE | STAT_PF | STAT_MA1F | STAT_MA2F)
+
+#define CTRL_TE(1 << 19)
+#define CTRL_RE(1 << 18)
+
+#define FIFO_TXFE  0x80
+#define FIFO_RXFE  0x40
+
+#define WATER_TXWATER_OFF  1
+#define WATER_RXWATER_OFF  16
+
 DECLARE_GLOBAL_DATA_PTR;
 
 struct lpuart_fsl *base = (struct lpuart_fsl *)LPUART_BASE;
 
+#ifndef CONFIG_LPUART_32B_REG
 static void lpuart_serial_setbrg(void)
 {
u32 clk = mxc_get_clock(MXC_UART_CLK);
@@ -107,13 +131,107 @@ static struct serial_device lpuart_serial_drv = {
.getc = lpuart_serial_getc,
.tstc = lpuart_serial_tstc,
 };
+#else
+static void lpuart32_serial_setbrg(void)
+{
+   u32 clk = CONFIG_SYS_CLK_FREQ;
+   u32 sbr;
+
+   if (!gd->baudrate)
+   gd->baudrate = CONFIG_BAUDRATE;
+
+   sbr = (clk / (16 * gd->baudrate));
+   /* place adjustment later - n/32 BRFA */
+
+   out_be32(&base->baud, sbr);
+}
+
+static int lpuart32_serial_getc(void)
+{
+   u32 stat;
+
+   while (((stat = in_be32(&base->stat)) & STAT_RDRF) == 0) {
+   out_be32(&base->stat, STAT_FLAGS);
+   WATCHDOG_RESET();
+   }
+
+   return in_be32(&base->data) & 0x3ff;
+}
+
+static void lpuart32_serial_putc(const char c)
+{
+   if (c == '\n')
+   serial_putc('\r');
+
+   while (!(in_be32(&base->stat) & STAT_TDRE))
+   WATCHDOG_RESET();
+
+   out_be32(&base->data, c);
+}
+
+/*
+ * Test whether a character is in the RX buffer
+ */
+static int lpuart32_serial_tstc(void)
+{
+   if ((in_be32(&base->water) >> 24) == 0)
+   return 0;
+
+   return 1;
+}
+
+/*
+ * Initialise the serial port with the given baudrate. The settings
+ * are always 8 data bits, no parity, 1 stop bit, no start bits.
+ */
+static int lpuart32_serial_init(void)
+{
+   u8 ctrl;
+
+   ctrl = in_be32(&base->ctrl);
+   ctrl &= ~CTRL_RE;
+   ctrl &= ~CTRL_TE;
+   out_be32(&base->ctrl, ctrl);
+
+   out_be32(&base->modir, 0);
+   out_be32(&base->fifo, ~(FIFO_TXFE | FIFO_RXFE));
+
+   out_be32(&base->match, 0);
+   /* provide data bits, parity, stop bit, etc */
+
+   serial_setbrg();
+
+   out_be32(&base->ctrl, CTRL_RE | CTRL_TE);
+
+   return 0;
+}
+
+static struct serial_device lpuart32_serial_drv = {
+   .name = "lpuart32_serial",
+   .start = lpuart32_serial_init,
+   .stop = NULL,
+   .setbrg = lpuart32_serial_setbrg,
+   .putc = lpuart32_serial_putc,
+   .puts = default_serial_puts,
+   .getc = lpuart32_serial_getc,
+   .tstc = lpuart32_serial_tstc,
+};
+#endif
 
 void lpuart_serial_initialize(void)
 {
+#ifdef CONFIG_LPUART_32B_REG
+   serial_register(&lpuart32_serial_drv);
+#else
serial_register(&lpuart_serial_drv);
+#endif
 }
 
 __weak struct serial_device *default_serial_console(void)
 {
+#ifdef CONFIG_LPUART_32B_REG
+   return &lpuart32_serial_drv;
+#else
return &lpuart_serial_drv;
+#endif
 }
-- 
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[U-Boot] [PATCH v6 07/17] ls102xa: esdhc: Add esdhc support for LS102xA

[Alison Wang]

From: Wang Huan 

For LS1, esdhc is big-endian IP. Accessing the registers
should be in big-endian mode. So we use esdhc_read32()
to read Host controller capabilities register for LS1.

For LS1, when using CMD12, cmdtype need to be set to
ABORT, otherwise, next read command will hang.

Signed-off-by: Alison Wang 
---
Change log:
 v6: Make the commit more clear.
 Split from the v5' 06 patch.
 v5: No change.
 v4: No change.
 v3: Add commit messages.
 v2: No change.

 drivers/mmc/fsl_esdhc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 5541613..97d0389 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -96,7 +96,7 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct 
mmc_data *data)
else if (cmd->resp_type & MMC_RSP_PRESENT)
xfertyp |= XFERTYP_RSPTYP_48;
 
-#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240)
+#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || 
defined(CONFIG_LS102XA)
if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
xfertyp |= XFERTYP_CMDTYP_ABORT;
 #endif
@@ -561,7 +561,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg 
*cfg)
memset(&cfg->cfg, 0, sizeof(cfg->cfg));
 
voltage_caps = 0;
-   caps = regs->hostcapblt;
+   caps = esdhc_read32(®s->hostcapblt);
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
-- 
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[U-Boot] [PATCH v6 11/17] arm: ls102xa: Add basic support for LS1021AQDS board

[Alison Wang]

From: Wang Huan 

LS102xA is an ARMv7 implementation. This patch is to add
basic support for LS1021AQDS board.
 One DDR controller
 DUART1 is used as the console

For the detail board information, please refer to README.

Signed-off-by: Alison Wang 
Signed-off-by: Jason Jin 
Signed-off-by: York Sun 
Signed-off-by: Yuan Yao 
Signed-off-by: Prabhakar Kushwaha 
---
Change log:
 v6: Fix checkpatch error.
 Use #define instead of magic numbers.
 Remove redundant codes.
 Add support for some command.
 Give more detail commits.
 v5: Change eth.c and handle the board muxing between the
 RGMII/SGMII phys.
 v4: Add more commit messages.
 v3: Fix checkpatch error.
 Update to Kconfig. 
 v2: Remove ethaddr/ipaddr setting.
 Add board maintainer.
 Add serdes and multiple ethernet controllers support.

 arch/arm/Kconfig  |   4 +
 board/freescale/ls1021aqds/Kconfig|  23 ++
 board/freescale/ls1021aqds/MAINTAINERS|   6 +
 board/freescale/ls1021aqds/Makefile   |   9 +
 board/freescale/ls1021aqds/README | 112 
 board/freescale/ls1021aqds/ddr.c  | 159 +++
 board/freescale/ls1021aqds/ddr.h  |  49 
 board/freescale/ls1021aqds/eth.c  | 186 
 board/freescale/ls1021aqds/ls1021aqds.c   | 255 +
 board/freescale/ls1021aqds/ls1021aqds_qixis.h |  35 +++
 configs/ls1021aqds_nor_defconfig  |   2 +
 include/configs/ls1021aqds.h  | 389 ++
 12 files changed, 1229 insertions(+)
 create mode 100644 board/freescale/ls1021aqds/Kconfig
 create mode 100644 board/freescale/ls1021aqds/MAINTAINERS
 create mode 100644 board/freescale/ls1021aqds/Makefile
 create mode 100644 board/freescale/ls1021aqds/README
 create mode 100644 board/freescale/ls1021aqds/ddr.c
 create mode 100644 board/freescale/ls1021aqds/ddr.h
 create mode 100644 board/freescale/ls1021aqds/eth.c
 create mode 100644 board/freescale/ls1021aqds/ls1021aqds.c
 create mode 100644 board/freescale/ls1021aqds/ls1021aqds_qixis.h
 create mode 100644 configs/ls1021aqds_nor_defconfig
 create mode 100644 include/configs/ls1021aqds.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 22f0f09..d7ed3e2 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -470,6 +470,9 @@ config TARGET_LS2085A_EMU
 config TARGET_LS2085A_SIMU
bool "Support ls2085a_simu"
 
+config TARGET_LS1021AQDS
+   bool "Support ls1021aqds_nor"
+
 config TARGET_BALLOON3
bool "Support balloon3"
 
@@ -594,6 +597,7 @@ source "board/eukrea/cpu9260/Kconfig"
 source "board/eukrea/cpuat91/Kconfig"
 source "board/faraday/a320evb/Kconfig"
 source "board/freescale/ls2085a/Kconfig"
+source "board/freescale/ls1021aqds/Kconfig"
 source "board/freescale/mx23evk/Kconfig"
 source "board/freescale/mx25pdk/Kconfig"
 source "board/freescale/mx28evk/Kconfig"
diff --git a/board/freescale/ls1021aqds/Kconfig 
b/board/freescale/ls1021aqds/Kconfig
new file mode 100644
index 000..c28bd2b
--- /dev/null
+++ b/board/freescale/ls1021aqds/Kconfig
@@ -0,0 +1,23 @@
+if TARGET_LS1021AQDS
+
+config SYS_CPU
+   string
+   default "armv7"
+
+config SYS_BOARD
+   string
+   default "ls1021aqds"
+
+config SYS_VENDOR
+   string
+   default "freescale"
+
+config SYS_SOC
+   string
+   default "ls102xa"
+
+config SYS_CONFIG_NAME
+   string
+   default "ls1021aqds"
+
+endif
diff --git a/board/freescale/ls1021aqds/MAINTAINERS 
b/board/freescale/ls1021aqds/MAINTAINERS
new file mode 100644
index 000..021d82b
--- /dev/null
+++ b/board/freescale/ls1021aqds/MAINTAINERS
@@ -0,0 +1,6 @@
+LS1021AQDS BOARD
+M: Alison Wang 
+S: Maintained
+F: board/freescale/ls1021aqds/
+F: include/configs/ls1021aqds.h
+F: configs/ls1021aqds_nor_defconfig
diff --git a/board/freescale/ls1021aqds/Makefile 
b/board/freescale/ls1021aqds/Makefile
new file mode 100644
index 000..3b6903c
--- /dev/null
+++ b/board/freescale/ls1021aqds/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:  GPL-2.0+
+#
+
+obj-y += ls1021aqds.o
+obj-y += ddr.o
+obj-y += eth.o
diff --git a/board/freescale/ls1021aqds/README 
b/board/freescale/ls1021aqds/README
new file mode 100644
index 000..c561776
--- /dev/null
+++ b/board/freescale/ls1021aqds/README
@@ -0,0 +1,112 @@
+Overview
+
+The LS1021AQDS is a Freescale reference board that hosts the LS1021A SoC.
+
+LS1021A SoC Overview
+--
+The QorIQ LS1 family, which includes the LS1021A communications processor,
+is built on Layerscape architecture, the industry's first software-aware,
+core-agnostic networking architecture to offer unprecedented efficiency
+and scale.
+
+A member of the value-performance tier, the QorIQ LS1021A processor provides
+extensive integration and power efficiency for fanless, small form factor
+enterprise networking applications. Incorporating d

[U-Boot] [PATCH v6 12/17] arm: ls102xa: Add basic support for LS1021ATWR board

[Alison Wang]

From: Wang Huan 

LS102xA is an ARMv7 implementation. This patch is to add
basic support for LS1021ATWR board.
 One DDR controller
 DUART1 is used as the console

For the detail board information, please refer to README.

Signed-off-by: Chen Lu 
Signed-off-by: Yuan Yao 
Signed-off-by: Alison Wang 
---
Change log:
 v6: Fix checkpatch error.
 Use #define instead of magic numbers.
 Remove redundant codes.
 Add support for some commands.
 v5: No change.
 v4: Add more commit messages.
 v3: Fix checkpatch error.
 Update to Kconfig. 
 v2: New file.

 arch/arm/Kconfig|   4 +
 board/freescale/ls1021atwr/Kconfig  |  23 ++
 board/freescale/ls1021atwr/MAINTAINERS  |   6 +
 board/freescale/ls1021atwr/Makefile |   7 +
 board/freescale/ls1021atwr/README   | 109 
 board/freescale/ls1021atwr/ls1021atwr.c | 482 
 configs/ls1021atwr_nor_defconfig|   2 +
 include/configs/ls1021atwr.h| 273 ++
 8 files changed, 906 insertions(+)
 create mode 100644 board/freescale/ls1021atwr/Kconfig
 create mode 100644 board/freescale/ls1021atwr/MAINTAINERS
 create mode 100644 board/freescale/ls1021atwr/Makefile
 create mode 100644 board/freescale/ls1021atwr/README
 create mode 100644 board/freescale/ls1021atwr/ls1021atwr.c
 create mode 100644 configs/ls1021atwr_nor_defconfig
 create mode 100644 include/configs/ls1021atwr.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index d7ed3e2..11143a8 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -473,6 +473,9 @@ config TARGET_LS2085A_SIMU
 config TARGET_LS1021AQDS
bool "Support ls1021aqds_nor"
 
+config TARGET_LS1021ATWR
+   bool "Support ls1021atwr_nor"
+
 config TARGET_BALLOON3
bool "Support balloon3"
 
@@ -598,6 +601,7 @@ source "board/eukrea/cpuat91/Kconfig"
 source "board/faraday/a320evb/Kconfig"
 source "board/freescale/ls2085a/Kconfig"
 source "board/freescale/ls1021aqds/Kconfig"
+source "board/freescale/ls1021atwr/Kconfig"
 source "board/freescale/mx23evk/Kconfig"
 source "board/freescale/mx25pdk/Kconfig"
 source "board/freescale/mx28evk/Kconfig"
diff --git a/board/freescale/ls1021atwr/Kconfig 
b/board/freescale/ls1021atwr/Kconfig
new file mode 100644
index 000..057808d
--- /dev/null
+++ b/board/freescale/ls1021atwr/Kconfig
@@ -0,0 +1,23 @@
+if TARGET_LS1021ATWR
+
+config SYS_CPU
+   string
+   default "armv7"
+
+config SYS_BOARD
+   string
+   default "ls1021atwr"
+
+config SYS_VENDOR
+   string
+   default "freescale"
+
+config SYS_SOC
+   string
+   default "ls102xa"
+
+config SYS_CONFIG_NAME
+   string
+   default "ls1021atwr"
+
+endif
diff --git a/board/freescale/ls1021atwr/MAINTAINERS 
b/board/freescale/ls1021atwr/MAINTAINERS
new file mode 100644
index 000..4e5bc15
--- /dev/null
+++ b/board/freescale/ls1021atwr/MAINTAINERS
@@ -0,0 +1,6 @@
+LS1021ATWR BOARD
+M: Alison Wang 
+S: Maintained
+F: board/freescale/ls1021atwr/
+F: include/configs/ls1021atwr.h
+F: configs/ls1021atwr_nor_defconfig
diff --git a/board/freescale/ls1021atwr/Makefile 
b/board/freescale/ls1021atwr/Makefile
new file mode 100644
index 000..b5df668
--- /dev/null
+++ b/board/freescale/ls1021atwr/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:  GPL-2.0+
+#
+
+obj-y += ls1021atwr.o
diff --git a/board/freescale/ls1021atwr/README 
b/board/freescale/ls1021atwr/README
new file mode 100644
index 000..d2821cb
--- /dev/null
+++ b/board/freescale/ls1021atwr/README
@@ -0,0 +1,109 @@
+Overview
+
+The LS1021ATWR is a Freescale reference board that hosts the LS1021A SoC.
+
+LS1021A SoC Overview
+--
+The QorIQ LS1 family, which includes the LS1021A communications processor,
+is built on Layerscape architecture, the industry's first software-aware,
+core-agnostic networking architecture to offer unprecedented efficiency
+and scale.
+
+A member of the value-performance tier, the QorIQ LS1021A processor provides
+extensive integration and power efficiency for fanless, small form factor
+enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
+running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
+performance of over 6,000, as well as virtualization support, advanced
+security features and the broadest array of high-speed interconnects and
+optimized peripheral features ever offered in a sub-3 W processor.
+
+The QorIQ LS1021A processor features an integrated LCD controller,
+CAN controller for implementing industrial protocols, DDR3L/4 running
+up to 1600 MHz, integrated security engine and QUICC Engine, and ECC
+protection on both L1 and L2 caches. The LS1021A processor is pin- and
+software-compatible with the QorIQ LS1020A and LS1022A processors.
+
+The LS1021A SoC includes the following function and features:
+
+ - ARM Cortex-A7 MPCore compliant with ARMv7-A architecture
+ - Dual h

[U-Boot] [PATCH v6 16/17] video: dcu: Add Sii9022A HDMI Transmitter support

[Alison Wang]

From: Wang Huan 

On LS1021ATWR, Silicon's Sii9022A HDMI Transmitter
is used. This patch adds the common setting for this
chip.

Signed-off-by: Alison Wang 
---
Change log:
 v6: No change.
 v5: Change the patch order.
 v4: Add commit messages.
 v3: New file.

 board/freescale/common/Makefile   |   2 +
 board/freescale/common/dcu_sii9022a.c | 153 ++
 board/freescale/common/dcu_sii9022a.h |  13 +++
 3 files changed, 168 insertions(+)
 create mode 100644 board/freescale/common/dcu_sii9022a.c
 create mode 100644 board/freescale/common/dcu_sii9022a.h

diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 50d7731..32b5a3b 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -36,6 +36,8 @@ endif
 
 obj-$(CONFIG_FSL_DIU_CH7301)   += diu_ch7301.o
 
+obj-$(CONFIG_FSL_DCU_SII9022A)+= dcu_sii9022a.o
+
 obj-$(CONFIG_MPC8541CDS)   += cds_pci_ft.o
 obj-$(CONFIG_MPC8548CDS)   += cds_pci_ft.o
 obj-$(CONFIG_MPC8555CDS)   += cds_pci_ft.o
diff --git a/board/freescale/common/dcu_sii9022a.c 
b/board/freescale/common/dcu_sii9022a.c
new file mode 100644
index 000..2da627e
--- /dev/null
+++ b/board/freescale/common/dcu_sii9022a.c
@@ -0,0 +1,153 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define PIXEL_CLK_LSB_REG  0x00
+#define PIXEL_CLK_MSB_REG  0x01
+#define VERT_FREQ_LSB_REG  0x02
+#define VERT_FREQ_MSB_REG  0x03
+#define TOTAL_PIXELS_LSB_REG   0x04
+#define TOTAL_PIXELS_MSB_REG   0x05
+#define TOTAL_LINES_LSB_REG0x06
+#define TOTAL_LINES_MSB_REG0x07
+#define TPI_INBUS_FMT_REG  0x08
+#define TPI_INPUT_FMT_REG  0x09
+#define TPI_OUTPUT_FMT_REG 0x0A
+#define TPI_SYS_CTRL_REG   0x1A
+#define TPI_PWR_STAT_REG   0x1E
+#define TPI_AUDIO_HANDING_REG  0x25
+#define TPI_AUDIO_INTF_REG 0x26
+#define TPI_AUDIO_FREQ_REG 0x27
+#define TPI_SET_PAGE_REG   0xBC
+#define TPI_SET_OFFSET_REG 0xBD
+#define TPI_RW_ACCESS_REG  0xBE
+#define TPI_TRANS_MODE_REG 0xC7
+
+#define TPI_INBUS_CLOCK_RATIO_1(1 << 6)
+#define TPI_INBUS_FULL_PIXEL_WIDE  (1 << 5)
+#define TPI_INBUS_RISING_EDGE  (1 << 4)
+#define TPI_INPUT_CLR_DEPTH_8BIT   (0 << 6)
+#define TPI_INPUT_VRANGE_EXPAN_AUTO(0 << 2)
+#define TPI_INPUT_CLR_RGB  (0 << 0)
+#define TPI_OUTPUT_CLR_DEPTH_8BIT  (0 << 6)
+#define TPI_OUTPUT_VRANGE_COMPRE_AUTO  (0 << 2)
+#define TPI_OUTPUT_CLR_HDMI_RGB(0 << 0)
+#define TPI_SYS_TMDS_OUTPUT(0 << 4)
+#define TPI_SYS_AV_NORAML  (0 << 3)
+#define TPI_SYS_AV_MUTE(1 << 3)
+#define TPI_SYS_DVI_MODE   (0 << 0)
+#define TPI_SYS_HDMI_MODE  (1 << 0)
+#define TPI_PWR_STAT_MASK  (3 << 0)
+#define TPI_PWR_STAT_D0(0 << 0)
+#define TPI_AUDIO_PASS_BASIC   (0 << 0)
+#define TPI_AUDIO_INTF_I2S (2 << 6)
+#define TPI_AUDIO_INTF_NORMAL  (0 << 4)
+#define TPI_AUDIO_TYPE_PCM (1 << 0)
+#define TPI_AUDIO_SAMP_SIZE_16BIT  (1 << 6)
+#define TPI_AUDIO_SAMP_FREQ_44K(2 << 3)
+#define TPI_SET_PAGE_SII9022A  0x01
+#define TPI_SET_OFFSET_SII9022A0x82
+#define TPI_RW_EN_SRC_TERMIN   (1 << 0)
+#define TPI_TRANS_MODE_ENABLE  (0 << 7)
+
+/* Programming of Silicon SIi9022a HDMI Transmitter */
+int dcu_set_dvi_encoder(struct fb_videomode *videomode)
+{
+   u8 temp;
+   u16 temp1, temp2;
+   u32 temp3;
+
+   i2c_set_bus_num(CONFIG_SYS_I2C_DVI_BUS_NUM);
+
+   /* Enable TPI transmitter mode */
+   temp = TPI_TRANS_MODE_ENABLE;
+   i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_TRANS_MODE_REG, 1, &temp, 1);
+
+   /* Enter into D0 state, full operation */
+   i2c_read(CONFIG_SYS_I2C_DVI_ADDR, TPI_PWR_STAT_REG, 1, &temp, 1);
+   temp &= ~TPI_PWR_STAT_MASK;
+   temp |= TPI_PWR_STAT_D0;
+   i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_PWR_STAT_REG, 1, &temp, 1);
+
+   /* Enable source termination */
+   temp = TPI_SET_PAGE_SII9022A;
+   i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_SET_PAGE_REG, 1, &temp, 1);
+   temp = TPI_SET_OFFSET_SII9022A;
+   i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_SET_OFFSET_REG, 1, &temp, 1);
+
+   i2c_read(CONFIG_SYS_I2C_DVI_ADDR, TPI_RW_ACCESS_REG, 1, &temp, 1);
+   temp |= TPI_RW_EN_SRC_TERMIN;
+   i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_RW_ACCESS_REG, 1, &temp, 1);
+
+   /* Set TPI system control */
+   temp = TPI_SYS_TMDS_OUTPUT | TPI_SYS_AV_NORAML | TPI_SYS_DVI_MODE;
+   i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_SYS_CTRL_REG, 1, &temp, 1);
+
+   /* Set pixel clock */
+   temp