Re: [U-Boot] [PATCH 1/3] mtd: onenand: Fix unaligned access
On Tuesday, December 31, 2013 at 11:43:48 AM, Lukasz Majewski wrote:
> Hi Marek,
>
> > On Saturday, December 28, 2013 at 05:06:28 PM, Lukasz Majewski wrote:
> > > Hi Marek,
> > >
> > > > On Thursday, December 26, 2013 at 01:01:24 AM, Marek Vasut wrote:
> > > > > Fix unaligned access in OneNAND core. The problem is that the
> > > > > ffchars[] array is an array of "unsigned char", but in
> > > > > onenand_write_ops_nolock() can be passed to the memcpy_16()
> > > > > function. The memcpy_16() function will treat the buffer as an
> > > > > array of "unsigned short", thus triggering unaligned access if
> > > > > the compiler decided ffchars[] to be not aligned.
> > > > >
> > > > > I managed to trigger the problem with regular ELDK 5.4 GCC
> > > > > compiler.
> > > > >
> > > > > Signed-off-by: Marek Vasut
> > > > > Cc: Albert Aribaud
> > > > > Cc: Scott Wood
> > > > > Cc: Tom Rini
> > > > > ---
> > > > >
> > > > > drivers/mtd/onenand/onenand_base.c | 8 +++-
> > > > > 1 file changed, 7 insertions(+), 1 deletion(-)
> > > > >
> > > > > diff --git a/drivers/mtd/onenand/onenand_base.c
> > > > > b/drivers/mtd/onenand/onenand_base.c index 979e4af..e33e8d3
> > > > > 100644 --- a/drivers/mtd/onenand/onenand_base.c
> > > > > +++ b/drivers/mtd/onenand/onenand_base.c
> > > > > @@ -91,7 +91,13 @@ static struct nand_ecclayout onenand_oob_32
> > > > > = {
> > > > >
> > > > > .oobfree= { {2, 3}, {14, 2}, {18, 3}, {30, 2} }
> > > > >
> > > > > };
> > > > >
> > > > > -static const unsigned char ffchars[] = {
> > > > > +/*
> > > > > + * Warning! This array is used with the memcpy_16() function,
> > > > > thus
> > > > > + * it must be aligned to 2 bytes. GCC can make this array
> > > > > unaligned
> > > > > + * as the array is made of unsigned char, which memcpy16()
> > > > > doesn't
> > > > > + * like and will cause unaligned access.
> > > > > + */
> > > > > +static const unsigned char __aligned(2) ffchars[] = {
> > > > >
> > > > > 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> > > > > 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> > > > >
> > > > > 0xff, /*
> > > > >
> > > > > 16 */ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
> > > >
> > > > Lukasz, can you please review this one?
> > >
> > > No problem, I will review the patch when I come back to the office
> > > (and be able to test it on the proper HW).
> >
> > Thanks, I'd love to get this fix into 2014.01 . Maybe the real fix
> > here would be to fix the memcpy_16() instead tho.
>
> I've tested it with eldk-5.4 toolchain on GONI device. It seems that no
> regression is caused by this patch.
>
> As a side note - this problem didn't show up for GONI board. Apparently
> I was lucky.
>
> I will scrutinize this code in respect of code alignment.
>
> Applied to u-boot-onenand.
Thank you very much!
Have a happy new year, guys !
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH V2 7/7] CONFIG: SMDK5420: Enable FIMD and DP
On 12/11/13 21:27, Ajay Kumar wrote: > Enable FIMD and DP drivers on SMDK5420 so that we get to > see the LCD console on eDP panel. > > Signed-off-by: Ajay Kumar > --- > include/configs/smdk5420.h | 8 > 1 file changed, 8 insertions(+) > > diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h > index 46aeec0..d3fa49b 100644 > --- a/include/configs/smdk5420.h > +++ b/include/configs/smdk5420.h > @@ -57,4 +57,12 @@ > #define CONFIG_POWER_I2C > #define CONFIG_POWER_S2MPS11 > > +/* Display */ > +#define CONFIG_LCD > +#ifdef CONFIG_LCD > +#define CONFIG_EXYNOS_FB > +#define CONFIG_EXYNOS_DP > +#define LCD_BPP LCD_COLOR16 please use space. > +#endif > + > #endif /* __CONFIG_5420_H */ > Thanks, Minkyu Kang. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V3 3/7] arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420
On 12/11/13 21:27, Ajay Kumar wrote:
> Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by
I think, they are not callback functions.
> exynos video driver.
> Also, configure ACLK_400_DISP1 as the parent for MUX_ACLK_400_DISP1_SUB_SEL.
>
> Signed-off-by: Ajay Kumar
> ---
> arch/arm/cpu/armv7/exynos/clock.c | 74
> +--
> arch/arm/cpu/armv7/exynos/exynos5_setup.h | 2 +-
> arch/arm/include/asm/arch-exynos/clk.h| 1 +
> 3 files changed, 73 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/exynos/clock.c
> b/arch/arm/cpu/armv7/exynos/clock.c
> index b52e61a..60ca7ea 100644
> --- a/arch/arm/cpu/armv7/exynos/clock.c
> +++ b/arch/arm/cpu/armv7/exynos/clock.c
> @@ -82,7 +82,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r,
> unsigned int k)
>* VPLL_CON: MIDV [24:16]
>* BPLL_CON: MIDV [25:16]: Exynos5
>*/
> - if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
> + if (pllreg == APLL || pllreg == MPLL ||
> + pllreg == BPLL || pllreg == SPLL)
> mask = 0x3ff;
> else
> mask = 0x1ff;
> @@ -391,6 +392,9 @@ static unsigned long exynos5420_get_pll_clk(int pllreg)
> r = readl(&clk->rpll_con0);
> k = readl(&clk->rpll_con1);
> break;
> + case SPLL:
> + r = readl(&clk->spll_con0);
> + break;
> default:
> printf("Unsupported PLL (%d)\n", pllreg);
> return 0;
> @@ -1038,6 +1042,40 @@ static unsigned long exynos5_get_lcd_clk(void)
> return pclk;
> }
>
> +static unsigned long exynos5420_get_lcd_clk(void)
> +{
> + struct exynos5420_clock *clk =
> + (struct exynos5420_clock *)samsung_get_base_clock();
> + unsigned long pclk, sclk;
> + unsigned int sel;
> + unsigned int ratio;
> +
> + /*
> + * CLK_SRC_DISP10
> + * FIMD1_SEL [4]
> + * 0: SCLK_RPLL
> + * 1: SCLK_SPLL
> + */
> + sel = readl(&clk->src_disp10);
> + sel &= (1 << 4);
> +
> + if (sel)
> + sclk = get_pll_clk(SPLL);
> + else
> + sclk = get_pll_clk(RPLL);
> +
> + /*
> + * CLK_DIV_DISP10
> + * FIMD1_RATIO [3:0]
> + */
> + ratio = readl(&clk->div_disp10);
> + ratio = ratio & 0xf;
> +
> + pclk = sclk / (ratio + 1);
> +
> + return pclk;
> +}
> +
> void exynos4_set_lcd_clk(void)
> {
> struct exynos4_clock *clk =
> @@ -1162,6 +1200,33 @@ void exynos5_set_lcd_clk(void)
> writel(cfg, &clk->div_disp1_0);
> }
>
> +void exynos5420_set_lcd_clk(void)
> +{
> + struct exynos5420_clock *clk =
> + (struct exynos5420_clock *)samsung_get_base_clock();
> + unsigned int cfg;
> +
> + /*
> + * CLK_SRC_DISP10
> + * FIMD1_SEL [4]
> + * 0: SCLK_RPLL
> + * 1: SCLK_SPLL
> + */
> + cfg = readl(&clk->src_disp10);
> + cfg &= ~(0x1 << 4);
> + cfg |= (0 << 4);
> + writel(cfg, &clk->src_disp10);
> +
> + /*
> + * CLK_DIV_DISP10
> + * FIMD1_RATIO [3:0]
> + */
> + cfg = readl(&clk->div_disp10);
> + cfg &= ~(0xf << 0);
> + cfg |= (0 << 0);
> + writel(cfg, &clk->div_disp10);
> +}
> +
> void exynos4_set_mipi_clk(void)
> {
> struct exynos4_clock *clk =
> @@ -1657,14 +1722,17 @@ unsigned long get_lcd_clk(void)
> {
> if (cpu_is_exynos4())
> return exynos4_get_lcd_clk();
> - else
> - return exynos5_get_lcd_clk();
> + else if (proid_is_exynos5420())
please don't mix cpu_is... and proid_is..
please refer other functions.
> + return exynos5420_get_lcd_clk();
> + return exynos5_get_lcd_clk();
> }
>
> void set_lcd_clk(void)
> {
> if (cpu_is_exynos4())
> exynos4_set_lcd_clk();
> + else if (proid_is_exynos5420())
> + exynos5420_set_lcd_clk();
ditto.
> else
> exynos5_set_lcd_clk();
> }
> diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h
> b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
> index 8e05a00..70b1c04 100644
> --- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h
> +++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
> @@ -780,7 +780,7 @@
> #define CLK_SRC_TOP2_VAL 0x11101000
> #define CLK_SRC_TOP3_VAL 0x
> #define CLK_SRC_TOP4_VAL 0x0111
> -#define CLK_SRC_TOP5_VAL 0x1100
> +#define CLK_SRC_TOP5_VAL 0x1101
> #define CLK_SRC_TOP6_VAL 0x0111
> #define CLK_SRC_TOP7_VAL 0x00022200
>
> diff --git a/arch/arm/include/asm/arch-exynos/clk.h
> b/arch/arm/include/asm/arch-exynos/clk.h
> index cdeef32..98faae7 100644
> --- a/arch/arm/include/asm/arch-exynos/clk.h
> +++ b/arch/arm/include/asm/arch-exynos/clk.h
> @@ -15,6 +15,7 @@
> #define VPLL 4
> #define BPLL 5
> #define RPLL 6
> +#define SPLL 7
>
> enum pll_src_bit {
> EXYNOS_SRC_MPLL = 6,
>
Thanks,
Minkyu Kang.
___
[U-Boot] Fwd: Re: [PATCH V2 1/7] exynos_fb: Remove usage of static defines
On 12/11/13 21:27, Ajay Kumar wrote:
> Previously, we used to statically assign values for vl_col, vl_row and
> vl_bpix using #defines like LCD_XRES, LCD_YRES and LCD_COLOR16.
>
> Introducing the function exynos_lcd_early_init() would take care of this
> assignment on the fly by parsing FIMD DT properties, thereby allowing us
> to remove LCD_XRES and LCD_YRES from the main config file.
>
> Signed-off-by: Ajay Kumar
> ---
> arch/arm/include/asm/arch-exynos/system.h | 1 +
> board/samsung/common/board.c | 15 +++
> drivers/video/exynos_fb.c | 20 ++--
> include/configs/exynos5250-dt.h | 2 --
> 4 files changed, 22 insertions(+), 16 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-exynos/system.h
> b/arch/arm/include/asm/arch-exynos/system.h
> index 7e2057c..4968d3d 100644
> --- a/arch/arm/include/asm/arch-exynos/system.h
> +++ b/arch/arm/include/asm/arch-exynos/system.h
> @@ -39,5 +39,6 @@ struct exynos5_sysreg {
>
> void set_usbhost_mode(unsigned int mode);
> void set_system_display_ctrl(void);
> +int exynos_lcd_early_init(const void *blob);
>
> #endif /* _EXYNOS4_SYSTEM_H */
> diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
> index cc83724..2536457 100644
> --- a/board/samsung/common/board.c
> +++ b/board/samsung/common/board.c
> @@ -20,6 +20,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -135,6 +136,20 @@ int board_early_init_f(void)
> #ifdef CONFIG_SYS_I2C_INIT_BOARD
> board_i2c_init(gd->fdt_blob);
> #endif
> +
> +#if defined(CONFIG_OF_CONTROL) && defined(CONFIG_EXYNOS_FB)
> +/*
> + * board_init_f(arch/arm/lib/board.c) calls lcd_setmem() which needs
> + * panel_info.vl_col, panel_info.vl_row and panel_info.vl_bpix, to reserve
> + * FB memory at a very early stage. So, we need to fill panel_info.vl_col,
> + * panel_info.vl_row and panel_info.vl_bpix before lcd_setmem() is called.
> + */
please fix indentation.
> + err = exynos_lcd_early_init(gd->fdt_blob);
> + if (err) {
> + debug("LCD early init failed\n");
> + return err;
> + }
> +#endif
> return err;
> }
> #endif
> diff --git a/drivers/video/exynos_fb.c b/drivers/video/exynos_fb.c
> index 7d4c6e0..69899a1 100644
> --- a/drivers/video/exynos_fb.c
> +++ b/drivers/video/exynos_fb.c
> @@ -27,17 +27,12 @@ DECLARE_GLOBAL_DATA_PTR;
>
> static unsigned int panel_width, panel_height;
>
> -/*
> - * board_init_f(arch/arm/lib/board.c) calls lcd_setmem() which needs
> - * panel_info.vl_col, panel_info.vl_row and panel_info.vl_bpix to reserve
> - * FB memory at a very early stage, i.e even before exynos_fimd_parse_dt()
> - * is called. So, we are forced to statically assign it.
> - */
> #ifdef CONFIG_OF_CONTROL
> vidinfo_t panel_info = {
> - .vl_col = LCD_XRES,
> - .vl_row = LCD_YRES,
> - .vl_bpix = LCD_COLOR16,
> + /* Insert a value here so that we don't end up in the BSS
> + * Reference: drivers/video/tegra.c
> + */
wrong comment style.
> + .vl_col = -1,
> };
> #endif
>
> @@ -159,7 +154,7 @@ static void lcd_panel_on(vidinfo_t *vid)
> }
>
> #ifdef CONFIG_OF_CONTROL
> -int exynos_fimd_parse_dt(const void *blob)
> +int exynos_lcd_early_init(const void *blob)
> {
> unsigned int node;
> node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS_FIMD);
> @@ -303,10 +298,7 @@ void lcd_ctrl_init(void *lcdbase)
> set_system_display_ctrl();
> set_lcd_clk();
>
> -#ifdef CONFIG_OF_CONTROL
> - if (exynos_fimd_parse_dt(gd->fdt_blob))
> - debug("Can't get proper panel info\n");
> -#else
> +#ifndef CONFIG_OF_CONTROL
> /* initialize parameters which is specific to panel. */
> init_panel_info(&panel_info);
> #endif
> diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h
> index 689919d..508962c 100644
> --- a/include/configs/exynos5250-dt.h
> +++ b/include/configs/exynos5250-dt.h
> @@ -50,8 +50,6 @@
> #ifdef CONFIG_LCD
> #define CONFIG_EXYNOS_FB
> #define CONFIG_EXYNOS_DP
> -#define LCD_XRES 2560
> -#define LCD_YRES 1600
> #define LCD_BPP LCD_COLOR16
> #endif
> #endif /* __CONFIG_5250_H */
>
Thanks,
Minkyu Kang.
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[U-Boot] [PATCH v2] spi/cadence: Adding Cadence SPI driver support for SOCFPGA
To add the Cadence SPI driver support for Altera SOCFPGA. It
required information such as clocks and timing from platform's
configuration header file within include/configs folder
Signed-off-by: Chin Liang See
Cc: Jagan Teki
Cc: Gerhard Sittig
---
Changes for v2
- Combine driver into single C file instead of 2
- Added documentation on the macro used
- Using structure for registers instead of macro
---
doc/README.socfpga | 47 ++
drivers/spi/Makefile |1 +
drivers/spi/cadence_qspi.c | 1018
drivers/spi/cadence_qspi.h | 170
4 files changed, 1236 insertions(+)
create mode 100644 drivers/spi/cadence_qspi.c
create mode 100644 drivers/spi/cadence_qspi.h
diff --git a/doc/README.socfpga b/doc/README.socfpga
index cfcbbfe..242af97 100644
--- a/doc/README.socfpga
+++ b/doc/README.socfpga
@@ -51,3 +51,50 @@ the card
#define CONFIG_SOCFPGA_DWMMC_BUS_HZ5000
-> The clock rate to controller. Do note the controller have a wrapper which
divide the clock from PLL by 4.
+
+
+cadence_qspi
+
+Here are macro and detailed configuration required to enable Cadence QSPI
+controller support within SOCFPGA
+
+#define CONFIG_SPI_FLASH
+-> To enable the SPI flash framework support
+
+#define CONFIG_CMD_SF
+-> To enable the console support for SPI flash
+
+#define CONFIG_SF_DEFAULT_SPEED(5000)
+-> To set the target SPI clock frequency in Hz
+
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
+-> To set the SPI mode (CPOL & CPHA). Normally use mode 3 for serial NOR flash
+
+#define CONFIG_SPI_FLASH_QUAD (1)
+-> To enable the Quad IO mode for performance boost
+
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_SPANSION
+-> To enable the SPI flash support for vendor Micron and Spansion
+
+#define CONFIG_CQSPI_BASE (SOCFPGA_QSPIREGS_ADDRESS)
+#define CONFIG_CQSPI_AHB_BASE (SOCFPGA_QSPIDATA_ADDRESS)
+-> To specify the base address for controller CSR base and AHB data base addr
+
+#define CONFIG_CQSPI_REF_CLK (4)
+-> The clock frequency supplied from PLL to the QSPI controller
+
+#define CONFIG_CQSPI_PAGE_SIZE (256)
+-> To define the page size of serial flash in bytes
+
+#define CONFIG_CQSPI_BLOCK_SIZE(16)
+-> To define the block size of serial flash in pages
+
+#define CONFIG_CQSPI_DECODER (0)
+-> To enable the 4-to-16 decoder which enable up to 16 serial flash devices
+
+#define CONFIG_CQSPI_TSHSL_NS (200)
+#define CONFIG_CQSPI_TSD2D_NS (255)
+#define CONFIG_CQSPI_TCHSH_NS (20)
+#define CONFIG_CQSPI_TSLCH_NS (20)
+-> Configure the controller based on serial flash device timing characteristic
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index ed4ecd7..b8d56ea 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
obj-$(CONFIG_BFIN_SPI) += bfin_spi.o
obj-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o
+obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o
obj-$(CONFIG_CF_SPI) += cf_spi.o
obj-$(CONFIG_CF_QSPI) += cf_qspi.o
obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
new file mode 100644
index 000..4712b45
--- /dev/null
+++ b/drivers/spi/cadence_qspi.c
@@ -0,0 +1,1018 @@
+/*
+ * (C) Copyright 2014 Altera Corporation
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "cadence_qspi.h"
+
+static int qspi_is_init;
+static unsigned int qspi_calibrated_hz;
+static unsigned int qspi_calibrated_cs;
+
+static const struct cadence_qspi *cadence_qspi_base = (void *)QSPI_BASE;
+
+#define to_cadence_qspi_slave(s) \
+ container_of(s, struct cadence_qspi_slave, slave)
+
+#define CQSPI_CAL_DELAY(tdelay_ns, tref_ns, tsclk_ns) \
+ tdelay_ns) - (tsclk_ns)) / (tref_ns)))
+
+#define CQSPI_GET_WR_SRAM_LEVEL() \
+ ((readl(&cadence_qspi_base->sramfill) >>\
+ CQSPI_REG_SRAMLEVEL_WR_LSB) & CQSPI_REG_SRAMLEVEL_WR_MASK)
+
+static unsigned int cadence_qspi_apb_cmd2addr(const unsigned char *addr_buf,
+ unsigned int addr_width)
+{
+ unsigned int addr;
+
+ addr = (addr_buf[0] << 16) | (addr_buf[1] << 8) | addr_buf[2];
+
+ if (addr_width == 4)
+ addr = (addr << 8) | addr_buf[3];
+
+ return addr;
+}
+
+static void cadence_qspi_apb_read_fifo_data(void *dest,
+ const void *src_ahb_addr, unsigned int bytes)
+{
+ unsigned int temp;
+ int remaining = bytes;
+ unsigned int *dest_ptr = (unsigned int *)dest;
+ unsigned int *src_ptr = (unsigned int *)src_ahb_addr;
+
+ while (remaining > 0) {
+ if (remaining >= CQSPI_FIFO_WIDTH) {
+
Re: [U-Boot] [PATCH V3 3/7] arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420
Hi Minkyu,
On Thu, Jan 2, 2014 at 6:09 AM, Minkyu Kang wrote:
> On 12/11/13 21:27, Ajay Kumar wrote:
> > Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by
>
> I think, they are not callback functions.
Ok. I will change the comment.
> > exynos video driver.
> > Also, configure ACLK_400_DISP1 as the parent for
> MUX_ACLK_400_DISP1_SUB_SEL.
> >
> > Signed-off-by: Ajay Kumar
> > ---
> > arch/arm/cpu/armv7/exynos/clock.c | 74
> +--
> > arch/arm/cpu/armv7/exynos/exynos5_setup.h | 2 +-
> > arch/arm/include/asm/arch-exynos/clk.h| 1 +
> > 3 files changed, 73 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/arm/cpu/armv7/exynos/clock.c
> b/arch/arm/cpu/armv7/exynos/clock.c
> > index b52e61a..60ca7ea 100644
> > --- a/arch/arm/cpu/armv7/exynos/clock.c
> > +++ b/arch/arm/cpu/armv7/exynos/clock.c
> > @@ -82,7 +82,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int
> r, unsigned int k)
> >* VPLL_CON: MIDV [24:16]
> >* BPLL_CON: MIDV [25:16]: Exynos5
> >*/
> > - if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
> > + if (pllreg == APLL || pllreg == MPLL ||
> > + pllreg == BPLL || pllreg == SPLL)
> > mask = 0x3ff;
> > else
> > mask = 0x1ff;
> > @@ -391,6 +392,9 @@ static unsigned long exynos5420_get_pll_clk(int
> pllreg)
> > r = readl(&clk->rpll_con0);
> > k = readl(&clk->rpll_con1);
> > break;
> > + case SPLL:
> > + r = readl(&clk->spll_con0);
> > + break;
> > default:
> > printf("Unsupported PLL (%d)\n", pllreg);
> > return 0;
> > @@ -1038,6 +1042,40 @@ static unsigned long exynos5_get_lcd_clk(void)
> > return pclk;
> > }
> >
> > +static unsigned long exynos5420_get_lcd_clk(void)
> > +{
> > + struct exynos5420_clock *clk =
> > + (struct exynos5420_clock *)samsung_get_base_clock();
> > + unsigned long pclk, sclk;
> > + unsigned int sel;
> > + unsigned int ratio;
> > +
> > + /*
> > + * CLK_SRC_DISP10
> > + * FIMD1_SEL [4]
> > + * 0: SCLK_RPLL
> > + * 1: SCLK_SPLL
> > + */
> > + sel = readl(&clk->src_disp10);
> > + sel &= (1 << 4);
> > +
> > + if (sel)
> > + sclk = get_pll_clk(SPLL);
> > + else
> > + sclk = get_pll_clk(RPLL);
> > +
> > + /*
> > + * CLK_DIV_DISP10
> > + * FIMD1_RATIO [3:0]
> > + */
> > + ratio = readl(&clk->div_disp10);
> > + ratio = ratio & 0xf;
> > +
> > + pclk = sclk / (ratio + 1);
> > +
> > + return pclk;
> > +}
> > +
> > void exynos4_set_lcd_clk(void)
> > {
> > struct exynos4_clock *clk =
> > @@ -1162,6 +1200,33 @@ void exynos5_set_lcd_clk(void)
> > writel(cfg, &clk->div_disp1_0);
> > }
> >
> > +void exynos5420_set_lcd_clk(void)
> > +{
> > + struct exynos5420_clock *clk =
> > + (struct exynos5420_clock *)samsung_get_base_clock();
> > + unsigned int cfg;
> > +
> > + /*
> > + * CLK_SRC_DISP10
> > + * FIMD1_SEL [4]
> > + * 0: SCLK_RPLL
> > + * 1: SCLK_SPLL
> > + */
> > + cfg = readl(&clk->src_disp10);
> > + cfg &= ~(0x1 << 4);
> > + cfg |= (0 << 4);
> > + writel(cfg, &clk->src_disp10);
> > +
> > + /*
> > + * CLK_DIV_DISP10
> > + * FIMD1_RATIO [3:0]
> > + */
> > + cfg = readl(&clk->div_disp10);
> > + cfg &= ~(0xf << 0);
> > + cfg |= (0 << 0);
> > + writel(cfg, &clk->div_disp10);
> > +}
> > +
> > void exynos4_set_mipi_clk(void)
> > {
> > struct exynos4_clock *clk =
> > @@ -1657,14 +1722,17 @@ unsigned long get_lcd_clk(void)
> > {
> > if (cpu_is_exynos4())
> > return exynos4_get_lcd_clk();
> > - else
> > - return exynos5_get_lcd_clk();
> > + else if (proid_is_exynos5420())
>
> please don't mix cpu_is... and proid_is..
> please refer other functions.
>
> Ok. I will change it.
> > + return exynos5420_get_lcd_clk();
> > + return exynos5_get_lcd_clk();
> > }
> >
> > void set_lcd_clk(void)
> > {
> > if (cpu_is_exynos4())
> > exynos4_set_lcd_clk();
> > + else if (proid_is_exynos5420())
> > + exynos5420_set_lcd_clk();
>
> ditto.
>
> Ok.
> > else
> > exynos5_set_lcd_clk();
> > }
> > diff --git a/arch/arm/cpu/armv7/exynos/exynos5_setup.h
> b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
> > index 8e05a00..70b1c04 100644
> > --- a/arch/arm/cpu/armv7/exynos/exynos5_setup.h
> > +++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h
> > @@ -780,7 +780,7 @@
> > #define CLK_SRC_TOP2_VAL 0x11101000
> > #define CLK_SRC_TOP3_VAL 0x
> > #define CLK_SRC_TOP4_VAL 0x0111
> > -#define CLK_SRC_TOP5_VAL 0x1100
> > +#define CLK_SRC_TOP5_VAL 0x1101
> > #define CLK_SRC_TOP6_VAL 0x0111
> > #define CLK_SRC_TOP7_VAL 0x00
Re: [U-Boot] [PATCH V2 7/7] CONFIG: SMDK5420: Enable FIMD and DP
Hi Minkyu, On Thu, Jan 2, 2014 at 6:09 AM, Minkyu Kang wrote: > On 12/11/13 21:27, Ajay Kumar wrote: > > Enable FIMD and DP drivers on SMDK5420 so that we get to > > see the LCD console on eDP panel. > > > > Signed-off-by: Ajay Kumar > > --- > > include/configs/smdk5420.h | 8 > > 1 file changed, 8 insertions(+) > > > > diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h > > index 46aeec0..d3fa49b 100644 > > --- a/include/configs/smdk5420.h > > +++ b/include/configs/smdk5420.h > > @@ -57,4 +57,12 @@ > > #define CONFIG_POWER_I2C > > #define CONFIG_POWER_S2MPS11 > > > > +/* Display */ > > +#define CONFIG_LCD > > +#ifdef CONFIG_LCD > > +#define CONFIG_EXYNOS_FB > > +#define CONFIG_EXYNOS_DP > > +#define LCD_BPP LCD_COLOR16 > > please use space. > > Ok. Will fix this in the next patchset. > > +#endif > > + > > #endif /* __CONFIG_5420_H */ > > > > Thanks, > Minkyu Kang. > > > ___ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot > Thanks and Regards, Ajay ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2 5/7] smdk5420: Implement callbacks needed by exynos_fb driver
Hi Simon,
Had posted a patch for same long back and some how it did not get reviewed
later, this needs to reworked again.
Following is the link for same.
https://patches.linaro.org/15850/
Regards,
Rajeshwari
On Fri, Dec 20, 2013 at 10:06 PM, Simon Glass wrote:
> Hi Ajay,
>
> On 20 December 2013 02:43, Ajay kumar wrote:
> > Hi Simon,
> >
> >
> > On Fri, Dec 20, 2013 at 2:10 AM, Simon Glass wrote:
> >>
> >> Hi Ajay,
> >>
> >> On 12 November 2013 05:27, Ajay Kumar wrote:
> >> > Add callbacks to set up DP-HPD, backlight and LCD power
> >> > on SMDK5420.
> >> >
> >> > Signed-off-by: Ajay Kumar
> >> > ---
> >> > board/samsung/smdk5420/smdk5420.c | 102
> >> > +++---
> >> > 1 file changed, 17 insertions(+), 85 deletions(-)
> >> >
> >> > diff --git a/board/samsung/smdk5420/smdk5420.c
> >> > b/board/samsung/smdk5420/smdk5420.c
> >> > index d85b953..75b22cc 100644
> >> > --- a/board/samsung/smdk5420/smdk5420.c
> >> > +++ b/board/samsung/smdk5420/smdk5420.c
> >> > @@ -43,98 +43,30 @@ int exynos_init(void)
> >> > }
> >> >
> >> > #ifdef CONFIG_LCD
> >> > -void cfg_lcd_gpio(void)
> >> > +void exynos_cfg_lcd_gpio(void)
> >> > {
> >> > - struct exynos5_gpio_part1 *gpio1 =
> >> > - (struct exynos5_gpio_part1
> >> > *)samsung_get_base_gpio_part1();
> >> > -
> >> > - /* For Backlight */
> >> > - s5p_gpio_cfg_pin(&gpio1->b2, 0, GPIO_OUTPUT);
> >> > - s5p_gpio_set_value(&gpio1->b2, 0, 1);
> >> > -
> >> > - /* LCD power on */
> >> > - s5p_gpio_cfg_pin(&gpio1->x1, 5, GPIO_OUTPUT);
> >> > - s5p_gpio_set_value(&gpio1->x1, 5, 1);
> >> > + struct exynos5420_gpio_part2 *gpio2 =
> >> > + (struct exynos5420_gpio_part2
> >> > *)samsung_get_base_gpio_part2();
> >> >
> >> > /* Set Hotplug detect for DP */
> >> > - s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
> >> > + s5p_gpio_cfg_pin(&gpio2->x0, 7, GPIO_FUNC(0x3));
> >> > }
> >> >
> >> > -vidinfo_t panel_info = {
> >> > - .vl_freq= 60,
> >> > - .vl_col = 2560,
> >> > - .vl_row = 1600,
> >> > - .vl_width = 2560,
> >> > - .vl_height = 1600,
> >> > - .vl_clkp= CONFIG_SYS_LOW,
> >> > - .vl_hsp = CONFIG_SYS_LOW,
> >> > - .vl_vsp = CONFIG_SYS_LOW,
> >> > - .vl_dp = CONFIG_SYS_LOW,
> >> > - .vl_bpix= 4,/* LCD_BPP = 2^4, for output conosle
> on
> >> > LCD */
> >> > -
> >> > - /* wDP panel timing infomation */
> >> > - .vl_hspw= 32,
> >> > - .vl_hbpd= 80,
> >> > - .vl_hfpd= 48,
> >> > -
> >> > - .vl_vspw= 6,
> >> > - .vl_vbpd= 37,
> >> > - .vl_vfpd= 3,
> >> > - .vl_cmd_allow_len = 0xf,
> >> > -
> >> > - .win_id = 3,
> >> > - .cfg_gpio = cfg_lcd_gpio,
> >> > - .backlight_on = NULL,
> >> > - .lcd_power_on = NULL,
> >> > - .reset_lcd = NULL,
> >> > - .dual_lcd_enabled = 0,
> >> > -
> >> > - .init_delay = 0,
> >> > - .power_on_delay = 0,
> >> > - .reset_delay= 0,
> >> > - .interface_mode = FIMD_RGB_INTERFACE,
> >> > - .dp_enabled = 1,
> >> > -};
> >> > -
> >> > -static struct edp_device_info edp_info = {
> >> > - .disp_info = {
> >> > - .h_res = 2560,
> >> > - .h_sync_width = 32,
> >> > - .h_back_porch = 80,
> >> > - .h_front_porch = 48,
> >> > - .v_res = 1600,
> >> > - .v_sync_width = 6,
> >> > - .v_back_porch = 37,
> >> > - .v_front_porch = 3,
> >> > - .v_sync_rate = 60,
> >> > - },
> >> > - .lt_info = {
> >> > - .lt_status = DP_LT_NONE,
> >> > - },
> >> > - .video_info = {
> >> > - .master_mode = 0,
> >> > - .bist_mode = DP_DISABLE,
> >> > - .bist_pattern = NO_PATTERN,
> >> > - .h_sync_polarity = 0,
> >> > - .v_sync_polarity = 0,
> >> > - .interlaced = 0,
> >> > - .color_space = COLOR_RGB,
> >> > - .dynamic_range = VESA,
> >> > - .ycbcr_coeff = COLOR_YCBCR601,
> >> > - .color_depth = COLOR_8,
> >> > - },
> >> > -};
> >> > -
> >> > -static struct exynos_dp_platform_data dp_platform_data = {
> >> > - .phy_enable = set_dp_phy_ctrl,
> >> > - .edp_dev_info = &edp_info,
> >> > -};
> >> > -
> >> > -void init_panel_info(vidinfo_t *vid)
> >> > +void exynos_backlight_on(unsigned int onoff)
> >> > {
> >> > - vid->rgb_mode = MODE_RGB_P,
> >> > + struct exynos5420_gpio_part1 *gpio1 =
> >> > + (struct exynos5420_gpio_part1
> >> > *)samsung_get_base_gpio_part1();
> >> > +
> >> > + struct exynos5420_gpio_part2 *gpio2 =
> >> > + (struct exynos5420_gpio_part2
> >>
Re: [U-Boot] [PATCH v2 12/13] trats2: add LCD download menu support
On 19/12/13 03:31, Przemyslaw Marczak wrote: > Signed-off-by: Przemyslaw Marczak > > --- > changes v2: > - add definitions for check keys > - cleanup config definitions > --- > include/configs/trats2.h | 27 +++ > 1 file changed, 27 insertions(+) > > diff --git a/include/configs/trats2.h b/include/configs/trats2.h > index 80d3ed0..b0dcfa4 100644 > --- a/include/configs/trats2.h > +++ b/include/configs/trats2.h > @@ -19,6 +19,8 @@ > #define CONFIG_S5P /* which is in a S5P Family */ > #define CONFIG_EXYNOS4 /* which is in a EXYNOS4XXX */ > #define CONFIG_TIZEN /* TIZEN lib */ > +#define CONFIG_TRATS2 > +#define CONFIG_BOARD_NAME"TRATS2" > > #include /* get chip and board defs */ > > @@ -319,6 +321,31 @@ > /* Common misc for Samsung */ > #define CONFIG_MISC_INIT_R > > +/* Download menu - Samsung common */ > +#define CONFIG_LCD_MENU > +#define CONFIG_LCD_MENU_BOARD > + > +/* Download menu - definitions for check keys */ > +#ifndef __ASSEMBLY__ > +#ifdef __COMMON_H_ why this ifdef(__COMMON_H_) is needed? > +#include > +#include > + > +#define KEY_PWR_PMIC_NAME"MAX77686_PMIC" > +#define KEY_PWR_STATUS_REG MAX77686_REG_PMIC_STATUS1 > +#define KEY_PWR_STATUS_MASK (1 << 0) > +#define KEY_PWR_INTERRUPT_REGMAX77686_REG_PMIC_INT1 > +#define KEY_PWR_INTERRUPT_MASK (1 << 1) > + > +#define KEY_VOL_UP_GPIO exynos4x12_gpio_get(2, x2, 2) > +#define KEY_VOL_DOWN_GPIOexynos4x12_gpio_get(2, x3, 3) > +#endif /* __COMMON_H_ */ > +#endif /* __ASSEMBLY__ */ > + > +/* LCD console */ > +#define LCD_BPP LCD_COLOR16 > +#define CONFIG_SYS_WHITE_ON_BLACK > + > /* LCD */ > #define CONFIG_EXYNOS_FB > #define CONFIG_LCD > Thanks, Minkyu Kang. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 02/13] trats: add optional cflags to board object file.
On 19/12/13 03:31, Przemyslaw Marczak wrote: > This change avoids unexpected unaligned access. > > more info: README.arm-unaligned-accesses > > Signed-off-by: Przemyslaw Marczak > cc: Lukasz Majewski > > --- > Changes v2: > - new patch > --- > board/samsung/trats/Makefile |2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/board/samsung/trats/Makefile b/board/samsung/trats/Makefile > index 5dc8a1f..c1bcd63 100644 > --- a/board/samsung/trats/Makefile > +++ b/board/samsung/trats/Makefile > @@ -6,3 +6,5 @@ > # > > obj-y+= trats.o > + > +$(obj)trats.o: CFLAGS += $(PLATFORM_NO_UNALIGNED) > \ No newline at end of file > What is the example of unexpected unaligned access on trats? Thanks, Minkyu Kang. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 01/13] s5p: gpio: change gpio coding method for s5p gpio.
Hi, On 19/12/13 03:31, Przemyslaw Marczak wrote: > Old s5p gpio coding method was not clean and was not working properly > for all parts and banks. New method is clean and easy to extend. > > Gpio coding mask: > 0x00ff - pin number > 0x0000 - bank offset > 0xff00 - part number > > Signed-off-by: Przemyslaw Marczak > --- > arch/arm/include/asm/arch-exynos/gpio.h | 169 > +++--- > arch/arm/include/asm/arch-s5pc1xx/gpio.h | 47 +++-- > drivers/gpio/s5p_gpio.c | 15 +-- > include/configs/s5p_goni.h |4 +- > include/configs/s5pc210_universal.h | 12 +-- > include/configs/trats.h |8 +- > include/configs/trats2.h | 12 +-- > 7 files changed, 125 insertions(+), 142 deletions(-) > patch failed. $ patch --dry-run -p1 < U-Boot-v2-01-13-s5p-gpio-change-gpio-coding-method-for-s5p-gpio..patch patching file arch/arm/include/asm/arch-exynos/gpio.h Hunk #1 FAILED at 196. 1 out of 1 hunk FAILED -- saving rejects to file arch/arm/include/asm/arch-exynos/gpio.h.rej patching file arch/arm/include/asm/arch-s5pc1xx/gpio.h patching file drivers/gpio/s5p_gpio.c patching file include/configs/s5p_goni.h patching file include/configs/s5pc210_universal.h patching file include/configs/trats.h Hunk #1 FAILED at 283. 1 out of 1 hunk FAILED -- saving rejects to file include/configs/trats.h.rej patching file include/configs/trats2.h Hunk #1 FAILED at 293. 1 out of 1 hunk FAILED -- saving rejects to file include/configs/trats2.h.rej please check it. Thanks, Minkyu Kang. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 06/13] common: makefile: Add optional cflags to object: common/lcd.o
On 19/12/13 03:31, Przemyslaw Marczak wrote: > This change adds CFLAGS: -mno-unaligned-access > which depends on option: PLATFORM_NO_UNALIGNED > > This option avoids unaligned data access exception on armv7, caused > by access to logo data which is mostly unaligned initialized array. OK. I understood about option. At here, please write on why you added this option. > > more info: README.arm-unaligned-accesses > > Signed-off-by: Przemyslaw Marczak > > --- > Changes v2: > - new patch > --- > common/Makefile |1 + > 1 file changed, 1 insertion(+) > > diff --git a/common/Makefile b/common/Makefile > index 74404be..619d72c 100644 > --- a/common/Makefile > +++ b/common/Makefile > @@ -240,3 +240,4 @@ $(obj)env_embedded.o: $(src)env_embedded.c > # SEE README.arm-unaligned-accesses > $(obj)hush.o: CFLAGS += $(PLATFORM_NO_UNALIGNED) > $(obj)fdt_support.o: CFLAGS += $(PLATFORM_NO_UNALIGNED) > +$(obj)lcd.o: CFLAGS += $(PLATFORM_NO_UNALIGNED) > Thanks, Minkyu Kang. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 04/13] samsung: common: Add misc file and common function misc_init_r().
On 19/12/13 03:31, Przemyslaw Marczak wrote:
> Config: CONFIG_MISC_INIT_R enables implementation of misc_init_r()
> in common file::
> - board/samsung/common/misc.c
I can't understand this commit message.
What means?
>
> Signed-off-by: Przemyslaw Marczak
>
> ---
> Changes v2:
> - change CONFIG_SAMSUNG to CONFIG_MISC_INIT_R
> ---
> board/samsung/common/Makefile |1 +
> board/samsung/common/misc.c | 14 ++
> 2 files changed, 15 insertions(+)
> create mode 100644 board/samsung/common/misc.c
>
> diff --git a/board/samsung/common/Makefile b/board/samsung/common/Makefile
> index 501d974..c30bb3d 100644
> --- a/board/samsung/common/Makefile
> +++ b/board/samsung/common/Makefile
> @@ -8,3 +8,4 @@
> obj-$(CONFIG_SOFT_I2C_MULTI_BUS) += multi_i2c.o
> obj-$(CONFIG_THOR_FUNCTION) += thor.o
> obj-$(CONFIG_CMD_USB_MASS_STORAGE) += ums.o
> +obj-$(CONFIG_MISC_INIT_R) += misc.o
> diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c
> new file mode 100644
> index 000..3764d12
> --- /dev/null
> +++ b/board/samsung/common/misc.c
> @@ -0,0 +1,14 @@
> +/*
> + * Copyright (C) 2013 Samsung Electronics
> + * Przemyslaw Marczak
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include
> +
> +/* Common for Samsung boards */
> +int misc_init_r(void)
> +{
> + return 0;
> +}
>
___
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Re: [U-Boot] [PATCH 1/4] power: Add support for TPS65090 PMU chip.
Hello, On 02/04/13 09:04, Simon Glass wrote: > From: Tom Wai-Hong Tam > > This adds driver support for the TPS65090 PMU. Support includes > hooking into the pmic infrastructure so that the pmic commands > can be used on the console. The TPS65090 supports the following > functionality: > > - fet enable/disable/querying > - getting and setting of charge state > > Even though it is connected to the pmic infrastructure it does > not hook into the pmic charging charging infrastructure. > > Signed-off-by: Tom Wai-Hong Tam > Signed-off-by: Simon Glass > Signed-off-by: Hatim Ali > Signed-off-by: Katie Roberts-Hoffman > Signed-off-by: Rong Chang > Signed-off-by: Sean Paul > Signed-off-by: Vincent Palatin > Signed-off-by: Aaron Durbin > --- > doc/device-tree-bindings/power/tps65090.txt | 21 ++ > drivers/power/pmic/Makefile | 1 + > drivers/power/pmic/pmic_tps65090.c | 296 > > include/fdtdec.h| 1 + > include/power/tps65090_pmic.h | 83 > lib/fdtdec.c| 1 + > 6 files changed, 403 insertions(+) > create mode 100644 doc/device-tree-bindings/power/tps65090.txt > create mode 100644 drivers/power/pmic/pmic_tps65090.c > create mode 100644 include/power/tps65090_pmic.h > Is this patch still available? also, http://patchwork.ozlabs.org/patch/232842/ and http://patchwork.ozlabs.org/patch/232849/ I didn't notice that patch was delegated to me, because this patch is for power. I'm sorry for long pending. Thanks, Minkyu Kang. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2 5/7] smdk5420: Implement callbacks needed by exynos_fb driver
On 02/01/14 15:32, Rajeshwari Birje wrote: > Hi Simon, > > Had posted a patch for same long back and some how it did not get reviewed > later, this needs to reworked again. > Following is the link for same. > https://patches.linaro.org/15850/ This patchset was marked to "Changes Requested". please check. it's 3/3 v5 http://patchwork.ozlabs.org/patch/233418/ and it's 4/4 v3 http://patchwork.ozlabs.org/patch/218903/ Thanks, Minkyu Kang. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 01/13] s5p: gpio: change gpio coding method for s5p gpio.
Hello Minkyu, On 01/02/2014 07:35 AM, Minkyu Kang wrote: Hi, On 19/12/13 03:31, Przemyslaw Marczak wrote: Old s5p gpio coding method was not clean and was not working properly for all parts and banks. New method is clean and easy to extend. Gpio coding mask: 0x00ff - pin number 0x0000 - bank offset 0xff00 - part number Signed-off-by: Przemyslaw Marczak --- arch/arm/include/asm/arch-exynos/gpio.h | 169 +++--- arch/arm/include/asm/arch-s5pc1xx/gpio.h | 47 +++-- drivers/gpio/s5p_gpio.c | 15 +-- include/configs/s5p_goni.h |4 +- include/configs/s5pc210_universal.h | 12 +-- include/configs/trats.h |8 +- include/configs/trats2.h | 12 +-- 7 files changed, 125 insertions(+), 142 deletions(-) patch failed. $ patch --dry-run -p1 < U-Boot-v2-01-13-s5p-gpio-change-gpio-coding-method-for-s5p-gpio..patch patching file arch/arm/include/asm/arch-exynos/gpio.h Hunk #1 FAILED at 196. 1 out of 1 hunk FAILED -- saving rejects to file arch/arm/include/asm/arch-exynos/gpio.h.rej patching file arch/arm/include/asm/arch-s5pc1xx/gpio.h patching file drivers/gpio/s5p_gpio.c patching file include/configs/s5p_goni.h patching file include/configs/s5pc210_universal.h patching file include/configs/trats.h Hunk #1 FAILED at 283. 1 out of 1 hunk FAILED -- saving rejects to file include/configs/trats.h.rej patching file include/configs/trats2.h Hunk #1 FAILED at 293. 1 out of 1 hunk FAILED -- saving rejects to file include/configs/trats2.h.rej please check it. Thanks, Minkyu Kang. Thank you for reply. Probably there were some changes in tree since I had sent this patch set. I will check this. Regards -- Przemyslaw Marczak Samsung R&D Institute Poland Samsung Electronics p.marc...@samsung.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
