Re: [U-Boot] [PATCH] ARM: EXYNOS: fixed compiler warning message

[Minkyu Kang]

On 11 July 2012 13:17, Rajeshwari Birje  wrote:
> Hi Jaehoon Chung,
>
> Acked-by: Rajeshwari Shinde 
>
> Thanks and Regards,
> Rajeshwari Shinde.
>
> On Tue, Jul 10, 2012 at 12:50 PM, Jaehoon Chung  
> wrote:
>> Removed [-Wuninitialized] warning message.
>> The fout_sel is assigned to "-1" by default.
>> And start, gpio_func is initialized to 0.
>>
>> Signed-off-by: Jaehoon Chung 
>> Signed-off-by: Kyungmin Park 
>> ---
>>  arch/arm/cpu/armv7/exynos/clock.c  |3 +++
>>  arch/arm/cpu/armv7/exynos/pinmux.c |2 +-
>>  2 files changed, 4 insertions(+), 1 deletions(-)

applied to u-boot-samsung.

Thanks.
Minkyu Kang.
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Re: [U-Boot] [PATCH u-boot-arm/next v2 1/1] OMAP3: igep00x0: add SPL support for IGEP-based boards

[Javier Martinez Canillas]

On Thu, Jul 19, 2012 at 8:56 AM, Enric Balletbò i Serra
 wrote:
> 2012/7/19 Javier Martinez Canillas :
>> On Wed, Jul 18, 2012 at 5:49 PM, Thomas Petazzoni
>>  wrote:
>>> Le Tue, 17 Jul 2012 02:15:17 +0200,
>>> Javier Martinez Canillas  a écrit :
>>>
 +void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 
 *rfr_ctrl,
 + u32 *mr)
 +{
 + *mr = MICRON_V_MR_165;
 +#ifdef CONFIG_BOOT_NAND
 + *mcfg = MICRON_V_MCFG_165(512 << 20);
 + *ctrla = MICRON_V_ACTIMA_165;
 + *ctrlb = MICRON_V_ACTIMB_165;
 + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
>>>
>>> I thought the NAND version of the IGEPv2 was capable of using the 200
>>> Mhz timings. At least, from the limited testing I had done, it seemed
>>> to work.
>>>
>>> Best regards,
>>>
>>> Thomas
>>> --
>>
>> Hi Thomas,
>>
>> Yes, you are right. I just tested the following patch on my NAND
>> version IGEPv2 and it seems to work just fine.
>>
>> Do you know if the OneNAND version also supports 200 MHz timings? If I
>> remember correctly the OMAP3730 version did but the OMAP3530 didn't.
>>
>> I guess Enric knows the answer :-)
>>
>
> Both memories can work at 200MHz, I guess the limitation is on the
> processor that is populated on the board. If the IGEP board comes with
> OMAP3530 should work at 166MHz, if comes with DM3730 can work at
> 200MHz.
>
> Cheers,
>Enric

Hi Enric,

That's what I remembered but I wasn't sure about it, thanks for the
clarification.

What do you think about this patch then?

diff --git a/board/isee/igep0020/igep0020.c b/board/isee/igep0020/igep0020.c
index 40436d6..a4d099a 100644
--- a/board/isee/igep0020/igep0020.c
+++ b/board/isee/igep0020/igep0020.c
@@ -77,15 +77,23 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla,
u32 *ctrlb, u32 *rfr_ctrl,
 {
*mr = MICRON_V_MR_165;
 #ifdef CONFIG_BOOT_NAND
-   *mcfg = MICRON_V_MCFG_165(512 << 20);
-   *ctrla = MICRON_V_ACTIMA_165;
-   *ctrlb = MICRON_V_ACTIMB_165;
-   *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+   *mcfg = MICRON_V_MCFG_200(512 << 20);
+   *ctrla = MICRON_V_ACTIMA_200;
+   *ctrlb = MICRON_V_ACTIMB_200;
+   *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
 #else
-   *mcfg = NUMONYX_V_MCFG_165(512 << 20);
-   *ctrla = NUMONYX_V_ACTIMA_165;
-   *ctrlb = NUMONYX_V_ACTIMB_165;
-   *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+   if (get_cpu_family() == CPU_OMAP34XX) {
+   *mcfg = NUMONYX_V_MCFG_165(512 << 20);
+   *ctrla = NUMONYX_V_ACTIMA_165;
+   *ctrlb = NUMONYX_V_ACTIMB_165;
+   *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+
+   } else {
+   *mcfg = NUMONYX_V_MCFG_200(512 << 20);
+   *ctrla = NUMONYX_V_ACTIMA_200;
+   *ctrlb = NUMONYX_V_ACTIMB_200;
+   *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+   }
 #endif
 }
 #endif
diff --git a/board/isee/igep0030/igep0030.c b/board/isee/igep0030/igep0030.c
index 41a7548..4f8b645 100644
--- a/board/isee/igep0030/igep0030.c
+++ b/board/isee/igep0030/igep0030.c
@@ -64,15 +64,23 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla,
u32 *ctrlb, u32 *rfr_ctrl,
 {
*mr = MICRON_V_MR_165;
 #ifdef CONFIG_BOOT_NAND
-   *mcfg = MICRON_V_MCFG_165(512 << 20);
-   *ctrla = MICRON_V_ACTIMA_165;
-   *ctrlb = MICRON_V_ACTIMB_165;
-   *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+   *mcfg = MICRON_V_MCFG_200(512 << 20);
+   *ctrla = MICRON_V_ACTIMA_200;
+   *ctrlb = MICRON_V_ACTIMB_200;
+   *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
 #else
-   *mcfg = NUMONYX_V_MCFG_165(512 << 20);
-   *ctrla = NUMONYX_V_ACTIMA_165;
-   *ctrlb = NUMONYX_V_ACTIMB_165;
-   *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+   if (get_cpu_family() == CPU_OMAP34XX) {
+   *mcfg = NUMONYX_V_MCFG_165(512 << 20);
+   *ctrla = NUMONYX_V_ACTIMA_165;
+   *ctrlb = NUMONYX_V_ACTIMB_165;
+   *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+
+   } else {
+   *mcfg = NUMONYX_V_MCFG_200(512 << 20);
+   *ctrla = NUMONYX_V_ACTIMA_200;
+   *ctrlb = NUMONYX_V_ACTIMB_200;
+   *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+   }
 #endif
 }
 #endif
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[U-Boot] Please pull u-boot-imx for v2012.07

[Stefano Babic]

Hi Albert,

please pull from u-boot-imx, thanks.

The following changes since commit 444def73695103c4aca06a70e9f4de9a5e6df28a:

  ARM: OMAP4: PANDA: Add rest of the USB module pads to essentials
(2012-07-19 00:03:34 +0200)

are available in the git repository at:

  git://www.denx.de/git/u-boot-imx.git master

for you to fetch changes up to 7c5f5118c70fd463df2fc131bd48e9769097e92f:

  mx6: Make pad name macro consistent with the datasheet (2012-07-19
09:11:04 +0200)


Anatolij Gustschin (1):
  mx28: Fix elftosb source link in README.mx28_common

Ashok (1):
  mx6: Make pad name macro consistent with the datasheet

Fabio Estevam (1):
  doc: README.mx28_common: Add missing entry into Contents

 arch/arm/include/asm/arch-mx6/mx6x_pins.h |4 ++--
 doc/README.mx28_common|9 +
 2 files changed, 7 insertions(+), 6 deletions(-)


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Re: [U-Boot] [PATCH 1/7 V5] EXYNOS: CLK: Add i2c clock

[Rajeshwari Birje]

Hi Simon Glass,

The warning messages are fixed in following patch:
"[PATCH] ARM: EXYNOS: fixed compiler warning message"
They are applied to u-boot today by Minkyu Kang.

Thanks and Regards,
Rajeshwari Shinde.

On Thu, Jul 19, 2012 at 11:31 AM, Rajeshwari Birje
 wrote:
> Hi Simon Glass,
>
> Thank you for comments.
>
> On Wed, Jul 18, 2012 at 10:46 PM, Simon Glass  wrote:
>> Hi,
>>
>> On Thu, Jul 5, 2012 at 12:59 PM, Rajeshwari Shinde
>>  wrote:
>>> This adds i2c clock information for EXYNOS5.
>>>
>>> Signed-off-by: Alim Akhtar 
>>> Signed-off-by: Doug Anderson 
>>> Signed-off-by: Rajeshwari Shinde 
>>> Acked-by: Simon Glass 
>>
>> Sorry for late comments. Please see below for some nits.
>>
>> Also I get these warnings with the samsung/master branch at present:
>>
>> clock.c: In function 'get_pll_clk':
>> clock.c:178:6: warning: 'fout_sel' may be used uninitialized in this
>> function [-Wmaybe-uninitialized]
>> clock.c:101:35: note: 'fout_sel' was declared here
>> pinmux.c: In function 'exynos_pinmux_config':
>> pinmux.c:100:20: warning: 'gpio_func' may be used uninitialized in
>> this function [-Wmaybe-uninitialized]
>> pinmux.c:69:16: note: 'gpio_func' was declared here
>> pinmux.c:99:3: warning: 'start' may be used uninitialized in this
>> function [-Wmaybe-uninitialized]
>> pinmux.c:69:9: note: 'start' was declared here
>> clock.c: In function 'get_pll_clk':
>> clock.c:178:6: warning: 'fout_sel' may be used uninitialized in this
>> function [-Wmaybe-uninitialized]
>> clock.c:101:35: note: 'fout_sel' was declared here
>> pinmux.c: In function 'exynos_pinmux_config':
>> pinmux.c:100:20: warning: 'gpio_func' may be used uninitialized in
>> this function [-Wmaybe-uninitialized]
>> pinmux.c:69:16: note: 'gpio_func' was declared here
>> pinmux.c:99:3: warning: 'start' may be used uninitialized in this
>> function [-Wmaybe-uninitialized]
>> pinmux.c:69:9: note: 'start' was declared here
>>
>>
> -- Sorry for inconvenience.. will correct them
>>> ---
>>> changes in V2:
>>> - Incorporated comments from Simon Glass which are removed extra
>>>   braces around (readl(&clk->div_top1)) >> 24 and gave a tab space 
>>> for
>>>   return statement.
>>> Changes in V3:
>>> - None
>>> Changes in V4:
>>> - None
>>> Changes in V5:
>>> - None.
>>>  arch/arm/cpu/armv7/exynos/clock.c  |   33 
>>> 
>>>  arch/arm/include/asm/arch-exynos/clk.h |1 +
>>>  2 files changed, 34 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/arch/arm/cpu/armv7/exynos/clock.c 
>>> b/arch/arm/cpu/armv7/exynos/clock.c
>>> index fc0ed5e..83ee25e 100644
>>> --- a/arch/arm/cpu/armv7/exynos/clock.c
>>> +++ b/arch/arm/cpu/armv7/exynos/clock.c
>>> @@ -602,6 +602,29 @@ void exynos4_set_mipi_clk(void)
>>> writel(cfg, &clk->div_lcd0);
>>>  }
>>>
>>> +/*
>>> + * I2C
>>> + *
>>> + * exynos5: obtaining the I2C clock
>>> + */
>>> +static unsigned long exynos5_get_i2c_clk(void)
>>> +{
>>> +   struct exynos5_clock *clk =
>>> +   (struct exynos5_clock *)samsung_get_base_clock();
>>> +   unsigned long aclk_66, aclk_66_pre, sclk;
>>> +   unsigned int ratio;
>>> +
>>> +   sclk = get_pll_clk(MPLL);
>>> +
>>> +   ratio = (readl(&clk->div_top1)) >> 24;
>>> +   ratio &= (0x7);
>>
>> Don't really need the ()
> -- ok.
>>
>>> +   aclk_66_pre = sclk/(ratio+1);
>>
>> spaces around operators, and below
> -- will correct this.
>>
>>> +   ratio = readl(&clk->div_top0);
>>> +   ratio &= (0x7);
>>> +   aclk_66 = aclk_66_pre/(ratio+1);
>>> +   return aclk_66;
>>> +}
>>> +
>>>  unsigned long get_pll_clk(int pllreg)
>>>  {
>>> if (cpu_is_exynos5())
>>> @@ -618,6 +641,16 @@ unsigned long get_arm_clk(void)
>>> return exynos4_get_arm_clk();
>>>  }
>>>
>>> +unsigned long get_i2c_clk(void)
>>> +{
>>> +   if (cpu_is_exynos5()) {
>>> +   return exynos5_get_i2c_clk();
>>> +   } else {
>>> +   debug("I2C clock is not set for this CPU\n");
>>> +   return 0;
>>> +   }
>>> +}
>>> +
>>>  unsigned long get_pwm_clk(void)
>>>  {
>>> if (cpu_is_exynos5())
>>> diff --git a/arch/arm/include/asm/arch-exynos/clk.h 
>>> b/arch/arm/include/asm/arch-exynos/clk.h
>>> index e99339a..5529025 100644
>>> --- a/arch/arm/include/asm/arch-exynos/clk.h
>>> +++ b/arch/arm/include/asm/arch-exynos/clk.h
>>> @@ -31,6 +31,7 @@
>>>
>>>  unsigned long get_pll_clk(int pllreg);
>>>  unsigned long get_arm_clk(void);
>>> +unsigned long get_i2c_clk(void);
>>>  unsigned long get_pwm_clk(void);
>>>  unsigned long get_uart_clk(int dev_index);
>>>  void set_mmc_clk(int dev_index, unsigned int div);
>>> --
>>> 1.7.4.4
>>>
>>
>> Regards,
>> Simon
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Re: [U-Boot] [PATCH v3 08/18] tegra: Add SOC support for display/lcd

[Thierry Reding]

On Thu, Jul 12, 2012 at 08:25:08AM -0700, Simon Glass wrote:
> From: Wei Ni 
> 
> Add support for the LCD peripheral at the Tegra2 SOC level. A separate
> LCD driver will use this functionality to configure the display.
> 
> Mayuresh Kulkarni:
> - changes to remove bitfields and clean up for submission
> 
> Simon Glass:
> - simplify code, move clock control into here, clean-up
> 
> Signed-off-by: Mayuresh Kulkarni 
> Signed-off-by: Simon Glass 
> ---
> Changes in v3:
> - Add probe function to read in fdt parameters in display driver
> - Separate display driver and LCD driver more in fdt
> 
>  arch/arm/cpu/armv7/tegra2/Makefile |2 +-
>  arch/arm/cpu/armv7/tegra2/display.c|  389 
>  arch/arm/include/asm/arch-tegra2/dc.h  |  544 
> 
>  arch/arm/include/asm/arch-tegra2/display.h |  152 
>  include/fdtdec.h   |1 +
>  lib/fdtdec.c   |1 +
>  6 files changed, 1088 insertions(+), 1 deletions(-)
>  create mode 100644 arch/arm/cpu/armv7/tegra2/display.c
>  create mode 100644 arch/arm/include/asm/arch-tegra2/dc.h
>  create mode 100644 arch/arm/include/asm/arch-tegra2/display.h
> 
[...]
> diff --git a/arch/arm/cpu/armv7/tegra2/display.c 
> b/arch/arm/cpu/armv7/tegra2/display.c
[...]
> +int setup_window(struct disp_ctl_win *win, struct fdt_disp_config *config)
> +{
> + win->x = 0;
> + win->y = 0;
> + win->w = config->width;
> + win->h = config->height;
> + win->out_x = 0;
> + win->out_y = 0;
> + win->out_w = config->width;
> + win->out_h = config->height;
> + win->phys_addr = config->frame_buffer;
> + win->stride = config->width * (1 << config->log2_bpp) / 8;
> + debug("%s: depth = %d\n", __func__, config->log2_bpp);
> + switch (config->log2_bpp) {
> + case 5:
> + case 24:

What's the 24 doing here?

[...]
> +static int tegra_display_decode_config(const void *blob,
> +struct fdt_disp_config *config)
> +{
> + int front, back, ref;
> + int node, rgb;
> + int bpp, bit;
> +
> + node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA20_DC);
> + if (node < 0) {
> + debug("%s: Cannot find display controller node in fdt\n",
> +   __func__);
> + return node;
> + }
> + config->disp = (struct disp_ctlr *)fdtdec_get_addr(blob, node, "reg");
> + if (!config->disp) {
> + debug("%s: No display controller address\n", __func__);
> + return -1;
> + }
> +
> + rgb = fdt_subnode_offset(blob, node, "rgb");
> +
> + config->frame_buffer = fdtdec_get_addr(blob, rgb,
> +"nvidia,frame-buffer");
> + config->width = fdtdec_get_int(blob, rgb, "xres", -1);
> + config->height = fdtdec_get_int(blob, rgb, "yres", -1);
> + bpp = fdtdec_get_int(blob, rgb, "nvidia,bits-per-pixel", -1);
> + bit = ffs(bpp) - 1;
> + if (bpp == (1 << bit))
> + config->log2_bpp = bit;
> + else
> + config->log2_bpp = bpp;
> + config->bpp = bpp;
> + config->pixel_clock = fdtdec_get_int(blob, rgb, "clock", 0);
> + if (!config->pixel_clock || bpp == -1 ||
> + config->width == -1 || config->height == -1) {
> + debug("%s: Pixel parameters missing\n", __func__);
> + return -FDT_ERR_NOTFOUND;
> + }
> +
> + /* Use a ref-to-sync of 1 always, and take this from the front porch */
> + back = fdtdec_get_int(blob, rgb, "left-margin", -1);
> + front = fdtdec_get_int(blob, rgb, "right-margin", -1);
> + ref = fdtdec_get_int(blob, rgb, "hsync-len", -1);
> + if ((back | front | ref) == -1) {
> + debug("%s: Horizontal parameters missing\n", __func__);
> + return -FDT_ERR_NOTFOUND;
> + }
> + config->horiz_timing[FDT_LCD_TIMING_REF_TO_SYNC] = 11;

The comment above says this should be 1.

> + config->horiz_timing[FDT_LCD_TIMING_SYNC_WIDTH] = ref;
> + config->horiz_timing[FDT_LCD_TIMING_BACK_PORCH] = back;
> + config->horiz_timing[FDT_LCD_TIMING_FRONT_PORCH] = front -
> + config->horiz_timing[FDT_LCD_TIMING_REF_TO_SYNC];
> + debug_timing("horiz", config->horiz_timing);
> +
> + back = fdtdec_get_int(blob, rgb, "upper-margin", -1);
> + front = fdtdec_get_int(blob, rgb, "lower-margin", -1);
> + ref = fdtdec_get_int(blob, rgb, "vsync-len", -1);
> + if ((back | front | ref) == -1) {
> + debug("%s: Vertical parameters missing\n", __func__);
> + return -FDT_ERR_NOTFOUND;
> + }
> + config->vert_timing[FDT_LCD_TIMING_REF_TO_SYNC] = 1;
> + config->vert_timing[FDT_LCD_TIMING_SYNC_WIDTH] = ref;
> + config->vert_timing[FDT_LCD_TIMING_BACK_PORCH] = back;
> + config->vert_timing[FDT_LCD_TIMING_FRONT_PORCH] = front -
> + config->vert_timing[FDT_LCD_TIMING_REF_TO_SYNC];
> + debu

Re: [U-Boot] [PATCH v3 09/18] tegra: Add LCD driver

[Thierry Reding]

On Thu, Jul 12, 2012 at 08:25:09AM -0700, Simon Glass wrote:
> This driver supports driving a single LCD and providing a U-Boot console
> on it.
> 
> Signed-off-by: Simon Glass 
> ---
> Changes in v2:
> - Update LCD driver to deal with new fdt bindings
> 
> Changes in v3:
> - Adjust LCD driver to use new SOC display driver structures
> - Move some fdt decode code from LCD driver to SOC display driver
> - Rename fdt config structures
> - Use new pwm binding from pre-linux-next
> 
>  drivers/video/Makefile |1 +
>  drivers/video/tegra.c  |  357 
> 
>  2 files changed, 358 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/video/tegra.c
> 
[...]
> diff --git a/drivers/video/tegra.c b/drivers/video/tegra.c
[...]
> +static int fdt_decode_lcd(const void *blob, struct fdt_panel_config *config)
> +{
> + int err;
> + int display_node;
> +
> + disp_config = tegra_display_get_config();
> + if (!disp_config) {
> + debug("%s: Display controller is not configured\n", __func__);
> + return -1;
> + }
> + display_node = disp_config->panel_node;
> + if (display_node < 0) {
> + debug("%s: No panel configuration available\n", __func__);
> + return -1;
> + }
> +
> + config->pwm_channel = pwm_request(blob, display_node, "nvidia,pwm");
> + if (config->pwm_channel < 0) {
> + debug("%s: Unable to request PWM channel\n", __func__);
> + return -1;
> + }
> +
> + config->cache_type = fdtdec_get_int(blob, display_node,
> + "nvidia,cache-type",
> + FDT_LCD_CACHE_WRITE_BACK_FLUSH);
> +
> + err = fdtdec_decode_gpio(blob, display_node,
> +   "nvidia,backlight-enable-gpios",
> +   &config->backlight_en);
> + err |= fdtdec_decode_gpio(blob, display_node,
> + "nvidia,lvds-shutdown-gpios", &config->lvds_shutdown);
> + fdtdec_decode_gpio(blob, display_node, "nvidia,backlight-vdd-gpios",
> +&config->backlight_vdd);
> + err |= fdtdec_decode_gpio(blob, display_node, "nvidia,panel-vdd-gpios",
> +   &config->panel_vdd);
> + if (err)
> + return -FDT_ERR_NOTFOUND;

This effectively makes those GPIOs mandatory. The Medcom, however,
doesn't have any of these, so I had to comment this return out to test
the series. I know that this might be an unusual setup, but it's
something that needs to be supported anyway.

Thierry


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Re: [U-Boot] [PATCH u-boot-arm/next v2 1/1] OMAP3: igep00x0: add SPL support for IGEP-based boards

[Enric Balletbò i Serra]

2012/7/19 Javier Martinez Canillas :
> On Thu, Jul 19, 2012 at 8:56 AM, Enric Balletbò i Serra
>  wrote:
>> 2012/7/19 Javier Martinez Canillas :
>>> On Wed, Jul 18, 2012 at 5:49 PM, Thomas Petazzoni
>>>  wrote:
 Le Tue, 17 Jul 2012 02:15:17 +0200,
 Javier Martinez Canillas  a écrit :

> +void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 
> *rfr_ctrl,
> + u32 *mr)
> +{
> + *mr = MICRON_V_MR_165;
> +#ifdef CONFIG_BOOT_NAND
> + *mcfg = MICRON_V_MCFG_165(512 << 20);
> + *ctrla = MICRON_V_ACTIMA_165;
> + *ctrlb = MICRON_V_ACTIMB_165;
> + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;

 I thought the NAND version of the IGEPv2 was capable of using the 200
 Mhz timings. At least, from the limited testing I had done, it seemed
 to work.

 Best regards,

 Thomas
 --
>>>
>>> Hi Thomas,
>>>
>>> Yes, you are right. I just tested the following patch on my NAND
>>> version IGEPv2 and it seems to work just fine.
>>>
>>> Do you know if the OneNAND version also supports 200 MHz timings? If I
>>> remember correctly the OMAP3730 version did but the OMAP3530 didn't.
>>>
>>> I guess Enric knows the answer :-)
>>>
>>
>> Both memories can work at 200MHz, I guess the limitation is on the
>> processor that is populated on the board. If the IGEP board comes with
>> OMAP3530 should work at 166MHz, if comes with DM3730 can work at
>> 200MHz.
>>
>> Cheers,
>>Enric
>
> Hi Enric,
>
> That's what I remembered but I wasn't sure about it, thanks for the
> clarification.
>
> What do you think about this patch then?
>
> diff --git a/board/isee/igep0020/igep0020.c b/board/isee/igep0020/igep0020.c
> index 40436d6..a4d099a 100644
> --- a/board/isee/igep0020/igep0020.c
> +++ b/board/isee/igep0020/igep0020.c
> @@ -77,15 +77,23 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla,
> u32 *ctrlb, u32 *rfr_ctrl,
>  {
> *mr = MICRON_V_MR_165;
>  #ifdef CONFIG_BOOT_NAND
> -   *mcfg = MICRON_V_MCFG_165(512 << 20);
> -   *ctrla = MICRON_V_ACTIMA_165;
> -   *ctrlb = MICRON_V_ACTIMB_165;
> -   *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
> +   *mcfg = MICRON_V_MCFG_200(512 << 20);
> +   *ctrla = MICRON_V_ACTIMA_200;
> +   *ctrlb = MICRON_V_ACTIMB_200;
> +   *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
>  #else
> -   *mcfg = NUMONYX_V_MCFG_165(512 << 20);
> -   *ctrla = NUMONYX_V_ACTIMA_165;
> -   *ctrlb = NUMONYX_V_ACTIMB_165;
> -   *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
> +   if (get_cpu_family() == CPU_OMAP34XX) {
> +   *mcfg = NUMONYX_V_MCFG_165(512 << 20);
> +   *ctrla = NUMONYX_V_ACTIMA_165;
> +   *ctrlb = NUMONYX_V_ACTIMB_165;
> +   *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
> +
> +   } else {
> +   *mcfg = NUMONYX_V_MCFG_200(512 << 20);
> +   *ctrla = NUMONYX_V_ACTIMA_200;
> +   *ctrlb = NUMONYX_V_ACTIMB_200;
> +   *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
> +   }
>  #endif
>  }
>  #endif
> diff --git a/board/isee/igep0030/igep0030.c b/board/isee/igep0030/igep0030.c
> index 41a7548..4f8b645 100644
> --- a/board/isee/igep0030/igep0030.c
> +++ b/board/isee/igep0030/igep0030.c
> @@ -64,15 +64,23 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla,
> u32 *ctrlb, u32 *rfr_ctrl,
>  {
> *mr = MICRON_V_MR_165;
>  #ifdef CONFIG_BOOT_NAND
> -   *mcfg = MICRON_V_MCFG_165(512 << 20);
> -   *ctrla = MICRON_V_ACTIMA_165;
> -   *ctrlb = MICRON_V_ACTIMB_165;
> -   *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
> +   *mcfg = MICRON_V_MCFG_200(512 << 20);
> +   *ctrla = MICRON_V_ACTIMA_200;
> +   *ctrlb = MICRON_V_ACTIMB_200;
> +   *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
>  #else
> -   *mcfg = NUMONYX_V_MCFG_165(512 << 20);
> -   *ctrla = NUMONYX_V_ACTIMA_165;
> -   *ctrlb = NUMONYX_V_ACTIMB_165;
> -   *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
> +   if (get_cpu_family() == CPU_OMAP34XX) {
> +   *mcfg = NUMONYX_V_MCFG_165(512 << 20);
> +   *ctrla = NUMONYX_V_ACTIMA_165;
> +   *ctrlb = NUMONYX_V_ACTIMB_165;
> +   *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
> +
> +   } else {
> +   *mcfg = NUMONYX_V_MCFG_200(512 << 20);
> +   *ctrla = NUMONYX_V_ACTIMA_200;
> +   *ctrlb = NUMONYX_V_ACTIMB_200;
> +   *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
> +   }
>  #endif
>  }
>  #endif

Thanks Thomas for making this observation.

Javier, the patch looks good for me. If we have the Numonyx OneNAND we
should check if the processor is OMAP3530 or DM3730 and apply the
correct timings. If we have the Micron NAND memory this check is not
necessary because all boards with this memory uses DM3730.

Cheers,
   Enric
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Re: [U-Boot] [PATCH v3 0/18] tegra: Add display driver and LCD support for Seaboard

[Thierry Reding]

On Thu, Jul 12, 2012 at 08:25:00AM -0700, Simon Glass wrote:
> This series adds support for the Tegra2x's display peripheral. This
> supports the LCD display on Seaboard and we use this to enable console
> output in U-Boot on the LCD.
> 
> Configuration is via the device tree. Proposed bindings are included
> in this series, taken from pwm bindings that should be in linux-next,
> a Tegra video binding that might be accepted in devicetree-discuss
> and a proposed video mode binding posted to dri-devel.
> 
> While I agree EDID is convenient for machines I would prefer to provide
> a user-friendly way of selecting LCD settings as well, with EDID more
> as a fallback and auto-detection when available.
> 
> To improve performance two optimisations are offered:
> 
> 1. The LCD frame buffer is cached, with the cache being flushed after
> each newline sent to putc(), and in a few other situations. This
> dramatically increases performance (around 10x). This requires a few
> additions to the ARM cache support.
> 
> 2. The console supports scrolling in steps of more than 1 line. This
> speeds up scrolling output considerably, particularly commands like
> 'printenv' which display a lot of output, and particular when the
> dcache is off. This requires a new CONFIG and a change to the
> console_scrollup() function.
> 
> Changes in v2:
> - Add new patch to use const in pinmux_config_pingroup/table()
> - Add nvidia prefix to device tree properties
> - Align tegra display using new CONFIG_LCD_ALIGNMENT feature
> - Put the LCD cache flush logic into lcd_putc() instead of lcd_puts()
> - Update LCD driver to deal with new fdt bindings
> - Update seaboard LCD definitions for new fdt binding
> - Use a more generic config CONFIG_LCD_ALIGNMENT for lcd alignment
> - Use const where possible in funcmux
> 
> Changes in v3:
> - Add new commit for pwm binding and node
> - Add new panel binding to fit with tegra display controller binding
> - Add probe function to read in fdt parameters in display driver
> - Add separate call to pwm_init() in board_init()
> - Adjust LCD driver to use new SOC display driver structures
> - Bring in proposed tegra display controller binding
> - Decode fdt node within the pwm driver
> - Fix tiny bug in mult-line lcd scrolling
> - Handle a cached frame buffer out of normal U-Boot memory
> - Introduce concept of a pwm channel, rather than separate peripherals
> - Move some fdt decode code from LCD driver to SOC display driver
> - Put the LCD cache flush logic back into lcd_puts()
> - Remove LPW1 pin which is not needed by display
> - Remove spurious newline from fdtdec_get_addr() debug output
> - Rename fdt config structures
> - Rename pwfm driver to pwm
> - Separate display driver and LCD driver more in fdt
> - Tidy up fdtdec_decode_gpios() debug output
> - Use displaymode binding for fdt
> - Use new proposed upstream pwm binding
> - Use new pwm binding from pre-linux-next
> - Use new upstream proposed LCD definitions
> 
> Mayuresh Kulkarni (1):
>   tegra: Enable display/lcd support on Seaboard
> 
> Simon Glass (16):
>   fdt: Tidy debugging, add to fdtdec_get_int/addr()
>   fdt: Add header guard to fdtdec.h
>   tegra: Use const for pinmux_config_pingroup/table()
>   tegra: Add display support to funcmux
>   tegra: fdt: Add pwm binding and node
>   tegra: fdt: Add LCD definitions for Tegra
>   tegra: Add support for PWM
>   tegra: Add LCD driver
>   tegra: Add LCD support to Nvidia boards
>   arm: Add control over cachability of memory regions
>   lcd: Add CONFIG_LCD_ALIGNMENT to select frame buffer alignment
>   lcd: Add support for flushing LCD fb from dcache after update
>   tegra: Align LCD frame buffer to section boundary
>   tegra: Support control of cache settings for LCD
>   tegra: fdt: Add LCD definitions for Seaboard
>   lcd: Add CONSOLE_SCROLL_LINES option to speed console
> 
> Wei Ni (1):
>   tegra: Add SOC support for display/lcd

I was able to make this work on the Medcom with the one workaround to
make backlight and panel GPIOs optional and adding the corresponding DTS
and configuration entries for Medcom, so:

Tested-by: Thierry Reding 

The display corruption does no longer seem to happen. While I haven't
thoroughly reviewed, I think this is in pretty good shape. Thanks Simon.

Thierry


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Re: [U-Boot] [PATCH v3 08/18] tegra: Add SOC support for display/lcd

[Adam Jiang]

On Thu, Jul 12, 2012 at 11:25:08PM +0800, Simon Glass wrote:
> From: Wei Ni 
> 
> Add support for the LCD peripheral at the Tegra2 SOC level. A separate
> LCD driver will use this functionality to configure the display.
> 
> Mayuresh Kulkarni:
> - changes to remove bitfields and clean up for submission
> 
> Simon Glass:
> - simplify code, move clock control into here, clean-up
> 
> Signed-off-by: Mayuresh Kulkarni 
> Signed-off-by: Simon Glass 
> ---
> Changes in v3:
> - Add probe function to read in fdt parameters in display driver
> - Separate display driver and LCD driver more in fdt
> 
>  arch/arm/cpu/armv7/tegra2/Makefile |2 +-
>  arch/arm/cpu/armv7/tegra2/display.c|  389 
>  arch/arm/include/asm/arch-tegra2/dc.h  |  544 
> 
>  arch/arm/include/asm/arch-tegra2/display.h |  152 
>  include/fdtdec.h   |1 +
>  lib/fdtdec.c   |1 +
>  6 files changed, 1088 insertions(+), 1 deletions(-)
>  create mode 100644 arch/arm/cpu/armv7/tegra2/display.c
>  create mode 100644 arch/arm/include/asm/arch-tegra2/dc.h
>  create mode 100644 arch/arm/include/asm/arch-tegra2/display.h
> 
> diff --git a/arch/arm/cpu/armv7/tegra2/Makefile 
> b/arch/arm/cpu/armv7/tegra2/Makefile
> index 5d271c4..79e1319 100644
> --- a/arch/arm/cpu/armv7/tegra2/Makefile
> +++ b/arch/arm/cpu/armv7/tegra2/Makefile
> @@ -40,7 +40,7 @@ COBJS-$(CONFIG_TEGRA_PMU) += pmu.o
>  COBJS-$(CONFIG_USB_EHCI_TEGRA) += usb.o
>  COBJS-$(CONFIG_TEGRA2_LP0) += crypto.o warmboot.o warmboot_avp.o
>  COBJS-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o
> -COBJS-$(CONFIG_VIDEO_TEGRA) += pwm.o
> +COBJS-$(CONFIG_VIDEO_TEGRA) += display.o pwm.o
> 
>  COBJS  := $(COBJS-y)
>  SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
> diff --git a/arch/arm/cpu/armv7/tegra2/display.c 
> b/arch/arm/cpu/armv7/tegra2/display.c
> new file mode 100644
> index 000..267e89e
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/tegra2/display.c
> @@ -0,0 +1,389 @@
> +/*
> + *  (C) Copyright 2010
> + *  NVIDIA Corporation 
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +static struct fdt_disp_config config;
> +
> +static void update_window(struct dc_ctlr *dc, struct disp_ctl_win *win)
> +{
> +   unsigned h_dda, v_dda;
> +   unsigned long val;
> +
> +   val = readl(&dc->cmd.disp_win_header);
> +   val |= WINDOW_A_SELECT;
> +   writel(val, &dc->cmd.disp_win_header);
> +
> +   writel(win->fmt, &dc->win.color_depth);
> +
> +   val = readl(&dc->win.byte_swap);
> +   val |= BYTE_SWAP_NOSWAP << BYTE_SWAP_SHIFT;
> +   writel(val, &dc->win.byte_swap);
> +
> +   val = win->out_x << H_POSITION_SHIFT;
> +   val |= win->out_y << V_POSITION_SHIFT;
> +   writel(val, &dc->win.pos);
> +
> +   val = win->out_w << H_SIZE_SHIFT;
> +   val |= win->out_h << V_SIZE_SHIFT;
> +   writel(val, &dc->win.size);
> +
> +   val = (win->w * win->bpp / 8) << H_PRESCALED_SIZE_SHIFT;
> +   val |= win->h << V_PRESCALED_SIZE_SHIFT;
> +   writel(val, &dc->win.prescaled_size);
> +
> +   writel(0, &dc->win.h_initial_dda);
> +   writel(0, &dc->win.v_initial_dda);
> +
> +   h_dda = (win->w * 0x1000) / max(win->out_w - 1, 1);
> +   v_dda = (win->h * 0x1000) / max(win->out_h - 1, 1);
> +
> +   val = h_dda << H_DDA_INC_SHIFT;
> +   val |= v_dda << V_DDA_INC_SHIFT;
> +   writel(val, &dc->win.dda_increment);
> +
> +   writel(win->stride, &dc->win.line_stride);
> +   writel(0, &dc->win.buf_stride);
> +
> +   val = WIN_ENABLE;
> +   if (win->bpp < 24)
> +   val |= COLOR_EXPAND;
> +   writel(val, &dc->win.win_opt);
> +
> +   writel((unsigned long)win->phys_addr, &dc->winbuf.start_addr);
> +   writel(win->x, &dc->winbuf.addr_h_offset);
> +   writel(win->y, &dc->winbuf.addr_v_offset);
> +
> +   writel(0xff00, &dc->win.blend_nokey);
> +   writel(0xff00, &dc->win.blend_1win);
> +
> +   val = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
> +   val |= GENERAL_UPDATE | WIN_A_UPDATE;
> 

Re: [U-Boot] [PATCH u-boot-arm/next v2 1/1] OMAP3: igep00x0: add SPL support for IGEP-based boards

[Javier Martinez Canillas]

On Thu, Jul 19, 2012 at 9:44 AM, Enric Balletbò i Serra
 wrote:
> 2012/7/19 Javier Martinez Canillas :
>> On Thu, Jul 19, 2012 at 8:56 AM, Enric Balletbò i Serra
>>  wrote:
>>> 2012/7/19 Javier Martinez Canillas :
 On Wed, Jul 18, 2012 at 5:49 PM, Thomas Petazzoni
  wrote:
> Le Tue, 17 Jul 2012 02:15:17 +0200,
> Javier Martinez Canillas  a écrit :
>
>> +void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 
>> *rfr_ctrl,
>> + u32 *mr)
>> +{
>> + *mr = MICRON_V_MR_165;
>> +#ifdef CONFIG_BOOT_NAND
>> + *mcfg = MICRON_V_MCFG_165(512 << 20);
>> + *ctrla = MICRON_V_ACTIMA_165;
>> + *ctrlb = MICRON_V_ACTIMB_165;
>> + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
>
> I thought the NAND version of the IGEPv2 was capable of using the 200
> Mhz timings. At least, from the limited testing I had done, it seemed
> to work.
>
> Best regards,
>
> Thomas
> --

 Hi Thomas,

 Yes, you are right. I just tested the following patch on my NAND
 version IGEPv2 and it seems to work just fine.

 Do you know if the OneNAND version also supports 200 MHz timings? If I
 remember correctly the OMAP3730 version did but the OMAP3530 didn't.

 I guess Enric knows the answer :-)

>>>
>>> Both memories can work at 200MHz, I guess the limitation is on the
>>> processor that is populated on the board. If the IGEP board comes with
>>> OMAP3530 should work at 166MHz, if comes with DM3730 can work at
>>> 200MHz.
>>>
>>> Cheers,
>>>Enric
>>
>> Hi Enric,
>>
>> That's what I remembered but I wasn't sure about it, thanks for the
>> clarification.
>>
>> What do you think about this patch then?
>>
>> diff --git a/board/isee/igep0020/igep0020.c b/board/isee/igep0020/igep0020.c
>> index 40436d6..a4d099a 100644
>> --- a/board/isee/igep0020/igep0020.c
>> +++ b/board/isee/igep0020/igep0020.c
>> @@ -77,15 +77,23 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla,
>> u32 *ctrlb, u32 *rfr_ctrl,
>>  {
>> *mr = MICRON_V_MR_165;
>>  #ifdef CONFIG_BOOT_NAND
>> -   *mcfg = MICRON_V_MCFG_165(512 << 20);
>> -   *ctrla = MICRON_V_ACTIMA_165;
>> -   *ctrlb = MICRON_V_ACTIMB_165;
>> -   *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
>> +   *mcfg = MICRON_V_MCFG_200(512 << 20);
>> +   *ctrla = MICRON_V_ACTIMA_200;
>> +   *ctrlb = MICRON_V_ACTIMB_200;
>> +   *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
>>  #else
>> -   *mcfg = NUMONYX_V_MCFG_165(512 << 20);
>> -   *ctrla = NUMONYX_V_ACTIMA_165;
>> -   *ctrlb = NUMONYX_V_ACTIMB_165;
>> -   *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
>> +   if (get_cpu_family() == CPU_OMAP34XX) {
>> +   *mcfg = NUMONYX_V_MCFG_165(512 << 20);
>> +   *ctrla = NUMONYX_V_ACTIMA_165;
>> +   *ctrlb = NUMONYX_V_ACTIMB_165;
>> +   *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
>> +
>> +   } else {
>> +   *mcfg = NUMONYX_V_MCFG_200(512 << 20);
>> +   *ctrla = NUMONYX_V_ACTIMA_200;
>> +   *ctrlb = NUMONYX_V_ACTIMB_200;
>> +   *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
>> +   }
>>  #endif
>>  }
>>  #endif
>> diff --git a/board/isee/igep0030/igep0030.c b/board/isee/igep0030/igep0030.c
>> index 41a7548..4f8b645 100644
>> --- a/board/isee/igep0030/igep0030.c
>> +++ b/board/isee/igep0030/igep0030.c
>> @@ -64,15 +64,23 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla,
>> u32 *ctrlb, u32 *rfr_ctrl,
>>  {
>> *mr = MICRON_V_MR_165;
>>  #ifdef CONFIG_BOOT_NAND
>> -   *mcfg = MICRON_V_MCFG_165(512 << 20);
>> -   *ctrla = MICRON_V_ACTIMA_165;
>> -   *ctrlb = MICRON_V_ACTIMB_165;
>> -   *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
>> +   *mcfg = MICRON_V_MCFG_200(512 << 20);
>> +   *ctrla = MICRON_V_ACTIMA_200;
>> +   *ctrlb = MICRON_V_ACTIMB_200;
>> +   *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
>>  #else
>> -   *mcfg = NUMONYX_V_MCFG_165(512 << 20);
>> -   *ctrla = NUMONYX_V_ACTIMA_165;
>> -   *ctrlb = NUMONYX_V_ACTIMB_165;
>> -   *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
>> +   if (get_cpu_family() == CPU_OMAP34XX) {
>> +   *mcfg = NUMONYX_V_MCFG_165(512 << 20);
>> +   *ctrla = NUMONYX_V_ACTIMA_165;
>> +   *ctrlb = NUMONYX_V_ACTIMB_165;
>> +   *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
>> +
>> +   } else {
>> +   *mcfg = NUMONYX_V_MCFG_200(512 << 20);
>> +   *ctrla = NUMONYX_V_ACTIMA_200;
>> +   *ctrlb = NUMONYX_V_ACTIMB_200;
>> +   *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
>> +   }
>>  #endif
>>  }
>>  #endif
>
> Thanks Thomas for making this observation.
>
> Javier, the patch looks good for me. If we have the Numonyx OneNAND we
> should check if the processor is OMAP3530 or DM3730 and apply the
> correct timings. If we have the Micron NAND memory this check is 

Re: [U-Boot] [PATCH v3 08/18] tegra: Add SOC support for display/lcd

[Adam Jiang]

On Thu, Jul 19, 2012 at 03:37:07PM +0800, Thierry Reding wrote:
> * PGP Signed by an unknown key
> 
> On Thu, Jul 12, 2012 at 08:25:08AM -0700, Simon Glass wrote:
> > From: Wei Ni 
> > 
> > Add support for the LCD peripheral at the Tegra2 SOC level. A separate
> > LCD driver will use this functionality to configure the display.
> > 
> > Mayuresh Kulkarni:
> > - changes to remove bitfields and clean up for submission
> > 
> > Simon Glass:
> > - simplify code, move clock control into here, clean-up
> > 
> > Signed-off-by: Mayuresh Kulkarni 
> > Signed-off-by: Simon Glass 
> > ---
> > Changes in v3:
> > - Add probe function to read in fdt parameters in display driver
> > - Separate display driver and LCD driver more in fdt
> > 
> >  arch/arm/cpu/armv7/tegra2/Makefile |2 +-
> >  arch/arm/cpu/armv7/tegra2/display.c|  389 
> >  arch/arm/include/asm/arch-tegra2/dc.h  |  544 
> > 
> >  arch/arm/include/asm/arch-tegra2/display.h |  152 
> >  include/fdtdec.h   |1 +
> >  lib/fdtdec.c   |1 +
> >  6 files changed, 1088 insertions(+), 1 deletions(-)
> >  create mode 100644 arch/arm/cpu/armv7/tegra2/display.c
> >  create mode 100644 arch/arm/include/asm/arch-tegra2/dc.h
> >  create mode 100644 arch/arm/include/asm/arch-tegra2/display.h
> > 
> [...]
> > diff --git a/arch/arm/cpu/armv7/tegra2/display.c 
> > b/arch/arm/cpu/armv7/tegra2/display.c
> [...]
> > +int setup_window(struct disp_ctl_win *win, struct fdt_disp_config *config)
> > +{
> > +   win->x = 0;
> > +   win->y = 0;
> > +   win->w = config->width;
> > +   win->h = config->height;
> > +   win->out_x = 0;
> > +   win->out_y = 0;
> > +   win->out_w = config->width;
> > +   win->out_h = config->height;
> > +   win->phys_addr = config->frame_buffer;
> > +   win->stride = config->width * (1 << config->log2_bpp) / 8;
> > +   debug("%s: depth = %d\n", __func__, config->log2_bpp);
> > +   switch (config->log2_bpp) {
> > +   case 5:
> > +   case 24:
> 
> What's the 24 doing here?

This has been explained in the definition of the log2_bpp. When bpp is
24, the integer holds 24 itself because there is no 2^N expression for
it.

/Adam

> 
> [...]
> > +static int tegra_display_decode_config(const void *blob,
> > +  struct fdt_disp_config *config)
> > +{
> > +   int front, back, ref;
> > +   int node, rgb;
> > +   int bpp, bit;
> > +
> > +   node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA20_DC);
> > +   if (node < 0) {
> > +   debug("%s: Cannot find display controller node in fdt\n",
> > + __func__);
> > +   return node;
> > +   }
> > +   config->disp = (struct disp_ctlr *)fdtdec_get_addr(blob, node, "reg");
> > +   if (!config->disp) {
> > +   debug("%s: No display controller address\n", __func__);
> > +   return -1;
> > +   }
> > +
> > +   rgb = fdt_subnode_offset(blob, node, "rgb");
> > +
> > +   config->frame_buffer = fdtdec_get_addr(blob, rgb,
> > +  "nvidia,frame-buffer");
> > +   config->width = fdtdec_get_int(blob, rgb, "xres", -1);
> > +   config->height = fdtdec_get_int(blob, rgb, "yres", -1);
> > +   bpp = fdtdec_get_int(blob, rgb, "nvidia,bits-per-pixel", -1);
> > +   bit = ffs(bpp) - 1;
> > +   if (bpp == (1 << bit))
> > +   config->log2_bpp = bit;
> > +   else
> > +   config->log2_bpp = bpp;
> > +   config->bpp = bpp;
> > +   config->pixel_clock = fdtdec_get_int(blob, rgb, "clock", 0);
> > +   if (!config->pixel_clock || bpp == -1 ||
> > +   config->width == -1 || config->height == -1) {
> > +   debug("%s: Pixel parameters missing\n", __func__);
> > +   return -FDT_ERR_NOTFOUND;
> > +   }
> > +
> > +   /* Use a ref-to-sync of 1 always, and take this from the front porch */
> > +   back = fdtdec_get_int(blob, rgb, "left-margin", -1);
> > +   front = fdtdec_get_int(blob, rgb, "right-margin", -1);
> > +   ref = fdtdec_get_int(blob, rgb, "hsync-len", -1);
> > +   if ((back | front | ref) == -1) {
> > +   debug("%s: Horizontal parameters missing\n", __func__);
> > +   return -FDT_ERR_NOTFOUND;
> > +   }
> > +   config->horiz_timing[FDT_LCD_TIMING_REF_TO_SYNC] = 11;
> 
> The comment above says this should be 1.
> 
> > +   config->horiz_timing[FDT_LCD_TIMING_SYNC_WIDTH] = ref;
> > +   config->horiz_timing[FDT_LCD_TIMING_BACK_PORCH] = back;
> > +   config->horiz_timing[FDT_LCD_TIMING_FRONT_PORCH] = front -
> > +   config->horiz_timing[FDT_LCD_TIMING_REF_TO_SYNC];
> > +   debug_timing("horiz", config->horiz_timing);
> > +
> > +   back = fdtdec_get_int(blob, rgb, "upper-margin", -1);
> > +   front = fdtdec_get_int(blob, rgb, "lower-margin", -1);
> > +   ref = fdtdec_get_int(blob, rgb, "vsync-len", -1);
> > +   if ((back | front | ref) == -1) {
> > +   debug("%s: Vertical parameters missing\n", __func__);
> > +   return -

Re: [U-Boot] [PATCH v3 08/18] tegra: Add SOC support for display/lcd

[Thierry Reding]

On Thu, Jul 19, 2012 at 05:24:35PM +0900, Adam Jiang wrote:
> On Thu, Jul 19, 2012 at 03:37:07PM +0800, Thierry Reding wrote:
> > * PGP Signed by an unknown key
> > 
> > On Thu, Jul 12, 2012 at 08:25:08AM -0700, Simon Glass wrote:
> > > From: Wei Ni 
> > > 
> > > Add support for the LCD peripheral at the Tegra2 SOC level. A separate
> > > LCD driver will use this functionality to configure the display.
> > > 
> > > Mayuresh Kulkarni:
> > > - changes to remove bitfields and clean up for submission
> > > 
> > > Simon Glass:
> > > - simplify code, move clock control into here, clean-up
> > > 
> > > Signed-off-by: Mayuresh Kulkarni 
> > > Signed-off-by: Simon Glass 
> > > ---
> > > Changes in v3:
> > > - Add probe function to read in fdt parameters in display driver
> > > - Separate display driver and LCD driver more in fdt
> > > 
> > >  arch/arm/cpu/armv7/tegra2/Makefile |2 +-
> > >  arch/arm/cpu/armv7/tegra2/display.c|  389 
> > >  arch/arm/include/asm/arch-tegra2/dc.h  |  544 
> > > 
> > >  arch/arm/include/asm/arch-tegra2/display.h |  152 
> > >  include/fdtdec.h   |1 +
> > >  lib/fdtdec.c   |1 +
> > >  6 files changed, 1088 insertions(+), 1 deletions(-)
> > >  create mode 100644 arch/arm/cpu/armv7/tegra2/display.c
> > >  create mode 100644 arch/arm/include/asm/arch-tegra2/dc.h
> > >  create mode 100644 arch/arm/include/asm/arch-tegra2/display.h
> > > 
> > [...]
> > > diff --git a/arch/arm/cpu/armv7/tegra2/display.c 
> > > b/arch/arm/cpu/armv7/tegra2/display.c
> > [...]
> > > +int setup_window(struct disp_ctl_win *win, struct fdt_disp_config 
> > > *config)
> > > +{
> > > + win->x = 0;
> > > + win->y = 0;
> > > + win->w = config->width;
> > > + win->h = config->height;
> > > + win->out_x = 0;
> > > + win->out_y = 0;
> > > + win->out_w = config->width;
> > > + win->out_h = config->height;
> > > + win->phys_addr = config->frame_buffer;
> > > + win->stride = config->width * (1 << config->log2_bpp) / 8;
> > > + debug("%s: depth = %d\n", __func__, config->log2_bpp);
> > > + switch (config->log2_bpp) {
> > > + case 5:
> > > + case 24:
> > 
> > What's the 24 doing here?
> 
> This has been explained in the definition of the log2_bpp. When bpp is
> 24, the integer holds 24 itself because there is no 2^N expression for
> it.

Right, I missed that. Thanks.

Thierry


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[U-Boot] [PATCH u-boot-arm/next v2 2/2] OMAP3: igep00x0: add SPL support for IGEP-based boards

[Javier Martinez Canillas]

This patch adds SPL support for IGEP-based boards.

Tested on an IGEPv2 Rev.C board with Micron NAND Flash memory.

Signed-off-by: Javier Martinez Canillas 
---

Changes since v1:

- Set NAND memory 200 Mhz timings when possible as suggested by Thomas Petazzoni

 board/isee/igep0020/config.mk  |   33 
 board/isee/igep0020/igep0020.c |   42 +-
 board/isee/igep0030/config.mk  |   33 
 board/isee/igep0030/igep0030.c |   42 +-
 include/configs/igep00x0.h |   65 
 5 files changed, 147 insertions(+), 68 deletions(-)
 delete mode 100644 board/isee/igep0020/config.mk
 delete mode 100644 board/isee/igep0030/config.mk

diff --git a/board/isee/igep0020/config.mk b/board/isee/igep0020/config.mk
deleted file mode 100644
index 7964621..000
--- a/board/isee/igep0020/config.mk
+++ /dev/null
@@ -1,33 +0,0 @@
-#
-# (C) Copyright 2009
-# ISEE 2007 SL, 
-#
-# IGEP0020 uses OMAP3 (ARM-CortexA8) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-# Physical Address:
-# 8000' (bank0)
-# A000/ (bank1)
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-
-# For use with external or internal boots.
-CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/board/isee/igep0020/igep0020.c b/board/isee/igep0020/igep0020.c
index 971e31b..a4d099a 100644
--- a/board/isee/igep0020/igep0020.c
+++ b/board/isee/igep0020/igep0020.c
@@ -58,6 +58,46 @@ int board_init(void)
return 0;
 }
 
+#ifdef CONFIG_SPL_BUILD
+/*
+ * Routine: omap_rev_string
+ * Description: For SPL builds output board rev
+ */
+void omap_rev_string(void)
+{
+}
+
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on both banks.
+ */
+void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
+   u32 *mr)
+{
+   *mr = MICRON_V_MR_165;
+#ifdef CONFIG_BOOT_NAND
+   *mcfg = MICRON_V_MCFG_200(512 << 20);
+   *ctrla = MICRON_V_ACTIMA_200;
+   *ctrlb = MICRON_V_ACTIMB_200;
+   *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+#else
+   if (get_cpu_family() == CPU_OMAP34XX) {
+   *mcfg = NUMONYX_V_MCFG_165(512 << 20);
+   *ctrla = NUMONYX_V_ACTIMA_165;
+   *ctrlb = NUMONYX_V_ACTIMB_165;
+   *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+
+   } else {
+   *mcfg = NUMONYX_V_MCFG_200(512 << 20);
+   *ctrla = NUMONYX_V_ACTIMA_200;
+   *ctrlb = NUMONYX_V_ACTIMB_200;
+   *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+   }
+#endif
+}
+#endif
+
 /*
  * Routine: setup_net_chip
  * Description: Setting up the configuration GPMC registers specific to the
@@ -91,7 +131,7 @@ static void setup_net_chip(void)
 }
 #endif
 
-#ifdef CONFIG_GENERIC_MMC
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
 int board_mmc_init(bd_t *bis)
 {
omap_mmc_init(0, 0, 0);
diff --git a/board/isee/igep0030/config.mk b/board/isee/igep0030/config.mk
deleted file mode 100644
index 059a878..000
--- a/board/isee/igep0030/config.mk
+++ /dev/null
@@ -1,33 +0,0 @@
-#
-# (C) Copyright 2009
-# ISEE 2007 SL, 
-#
-# IGEP0030 uses OMAP3 (ARM-CortexA8) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, B

Re: [U-Boot] [PATCH] nds32: split common cache access from cpu into lib

[Marek Vasut]

Dear Mike Frysinger,

> On Sunday 15 July 2012 04:12:45 Marek Vasut wrote:
> > Dear Macpaul Lin,
> > 
> > > +void flush_cache(unsigned long addr, unsigned long size)
> > > +{
> > > + flush_dcache_range(addr, addr + size);
> > > + invalidate_icache_range(addr, addr + size);
> > 
> > You probably want to flush dcache in here and that's it.
> 
> i don't think so ... i think that's what flush_dcache_range() is for.  and
> our common/cmd_*.c files assume that flush_cache() will invalidate icache
> (see the bootm/load funcs that write executable content into memory and
> then flush the regions).

Than it's borked on arm926ejs too ... ?

Best regards,
Marek Vasut
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[U-Boot] [PATCH] net: link_local: fix build

[Benoît Thébaudeau]

Fix comment within comment build error.

Signed-off-by: Benoît Thébaudeau 
Cc: Joe Hershberger 
---
 .../net/link_local.c   |6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git u-boot-66714b1.orig/net/link_local.c u-boot-66714b1/net/link_local.c
index 8e7665f..d52f13a 100644
--- u-boot-66714b1.orig/net/link_local.c
+++ u-boot-66714b1/net/link_local.c
@@ -225,8 +225,8 @@ void link_local_receive_arp(struct arp_hdr *arp, int len)
timeout_ms = diff | 1; /* never 0 */
}
}
-/*
- * XXX Don't bother with ethernet link just yet
+#if 0
+ /* XXX Don't bother with ethernet link just yet */
if ((fds[0].revents & POLLIN) == 0) {
if (fds[0].revents & POLLERR) {
/*
@@ -240,7 +240,7 @@ void link_local_receive_arp(struct arp_hdr *arp, int len)
}
continue;
}
-*/
+#endif
 
debug_cond(DEBUG_INT_STATE, "%s recv arp type=%d, op=%d,\n",
eth_get_name(), ntohs(arp->ar_pro),
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[U-Boot] [PATCH] net: bootp: fix build

[Benoît Thébaudeau]

Fix NetSetState function name used with CONFIG_BOOTP_MAY_FAIL.

Signed-off-by: Benoît Thébaudeau 
Cc: Joe Hershberger 
---
 .../net/bootp.c|2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git u-boot-66714b1.orig/net/bootp.c u-boot-66714b1/net/bootp.c
index 87e30ab..c9b8349 100644
--- u-boot-66714b1.orig/net/bootp.c
+++ u-boot-66714b1/net/bootp.c
@@ -330,7 +330,7 @@ BootpTimeout(void)
if (BootpTry >= TIMEOUT_COUNT) {
 #ifdef CONFIG_BOOTP_MAY_FAIL
puts("\nRetry count exceeded\n");
-   NetSetState(NETLOOP_FAIL);
+   net_set_state(NETLOOP_FAIL);
 #else
puts("\nRetry count exceeded; starting again\n");
NetStartAgain();
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Re: [U-Boot] [PATCH v2 0/4] Board support and feature for LaCie devices

[Simon Guinot]

On Wed, Jun 06, 2012 at 01:16:49AM +0200, Simon Guinot wrote:
> Changes for v2:
>  - Move board support and feature into a separate patch set.
>  - Move mach-types update into a separate patch.
> 
> Simon Guinot (4):
>   lacie_kw: add support for EFI partitions
>   ARM: add netspace_mini_v2 to mach-types.h
>   ARM: add support for Network Space v2 Lite and Mini
>   ARM: add support for d2 Network v2
> 
>  arch/arm/include/asm/mach-types.h |   13 +++
>  board/LaCie/common/common.c   |   36 ++-
>  board/LaCie/common/common.h   |1 +
>  board/LaCie/netspace_v2/kwbimage-ns2l.cfg |  162 
> +
>  board/LaCie/netspace_v2/netspace_v2.c |4 +
>  boards.cfg|3 +
>  include/configs/lacie_kw.h|   42 ++--
>  7 files changed, 252 insertions(+), 9 deletions(-)
>  create mode 100644 board/LaCie/netspace_v2/kwbimage-ns2l.cfg

Hi Prafulla,

Please, consider picking this patches.

Regards,

Simon

> 
> -- 
> 1.7.9.5
> 
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[U-Boot] [PATCH] ARM1136: Fix cache range checks

[Benoît Thébaudeau]

bad_cache_range actually returned true if the range was OK, but it was used
according to its name, which resulted in all valid dcache range invalidate/flush
operations being dropped. Hence, most DMA transfers resulted in garbage data.

This patch renames this function according to what it does, and it fixes the
interpretation of its return value by other functions. The chosen naming is the
same as for ARM926EJ-S in order to be consistent.

Signed-off-by: Benoît Thébaudeau 
Cc: Albert Aribaud 
---
 .../arch/arm/cpu/arm1136/cpu.c |6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git u-boot-66714b1.orig/arch/arm/cpu/arm1136/cpu.c 
u-boot-66714b1/arch/arm/cpu/arm1136/cpu.c
index f72bab6..b98e3d9 100644
--- u-boot-66714b1.orig/arch/arm/cpu/arm1136/cpu.c
+++ u-boot-66714b1/arch/arm/cpu/arm1136/cpu.c
@@ -95,7 +95,7 @@ void flush_dcache_all(void)
asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
 }
 
-static inline int bad_cache_range(unsigned long start, unsigned long stop)
+static int check_cache_range(unsigned long start, unsigned long stop)
 {
int ok = 1;
 
@@ -114,7 +114,7 @@ static inline int bad_cache_range(unsigned long start, 
unsigned long stop)
 
 void invalidate_dcache_range(unsigned long start, unsigned long stop)
 {
-   if (bad_cache_range(start, stop))
+   if (!check_cache_range(start, stop))
return;
 
while (start < stop) {
@@ -125,7 +125,7 @@ void invalidate_dcache_range(unsigned long start, unsigned 
long stop)
 
 void flush_dcache_range(unsigned long start, unsigned long stop)
 {
-   if (bad_cache_range(start, stop))
+   if (!check_cache_range(start, stop))
return;
 
while (start < stop) {
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Re: [U-Boot] [PATCH v7 01/15] tegra20: rename tegra2 -> tegra20

[Simon Glass]

Hi Allen,

On Tue, Jul 17, 2012 at 12:02 AM, Allen Martin  wrote:
> This is make naming consistent with the kernel and devicetree and in
> preparation of pulling out the common tegra20 code.
>
> Signed-off-by: Allen Martin 
> Acked-by: Stephen Warren 
> Tested-by: Thierry Reding 

...

> diff --git a/include/configs/tec.h b/include/configs/tec.h
> index 3d0a788..39400d9 100644
> --- a/include/configs/tec.h
> +++ b/include/configs/tec.h
> @@ -26,21 +26,21 @@
>  #ifndef __CONFIG_H
>  #define __CONFIG_H
>
> -#include "tegra2-common.h"
> +#include "tegra20-common.h"
>
>  /* Enable fdt support for TEC. Flash the image in u-boot-dtb.bin */
> -#define CONFIG_DEFAULT_DEVICE_TREE tegra2-tec
> +#define CONFIG_DEFAULT_DEVICE_TREE tegra20-tec
>  #define CONFIG_OF_CONTROL
>  #define CONFIG_OF_SEPARATE
>
>  /* High-level configuration options */
> -#define V_PROMPT   "Tegra2 (TEC) # "
> -#define CONFIG_TEGRA2_BOARD_STRING "Avionic Design Tamonten Evaluation 
> Carrier"
> +#define V_PROMPT   "Tegra20 (TEC) # "
> +#define CONFIG_TEGRA20_BOARD_STRING"Avionic Design Tamonten Evaluation 
> Carrier"

Just a nit here - this is over 80cols.

Regards,
Simon
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[U-Boot] [PATCH 0/8 V6] EXYNOS5: Enable I2C support

[Rajeshwari Shinde]

This patch set enables I2C support for EXYNOS5.
This patchset modifies the s3c24x0 I2C driver to use same for EXYNOS5.
Multichannel support has been added to the s3c24x0 I2C driver.
s3c24x0_i2c struct has been moved to a common place as it can used
by different SOC's.

Changes in V2:
- Incorporated review comments from Simon Glass.
- Aligned the pinmux functionality as per latest comments
Changes in V3:
- Incorporated review comments from Joonyoung Shim for
  I2C driver.
Changes in V4:
- Resolved build error for S3C2410.
Changes in V5:
- Pinmux setting moved to board file.
- Multi Bus I2C offset calculation done based on
  EXYNOS_I2C_SPACE.
- Peripheral id calculation removed from i2c driver.
Changes in V6:
- Incorporated review comments from Simon Glass.

Rajeshwari Shinde (8):
  EXYNOS: CLK: Add i2c clock
  EXYNOS: Add I2C base address.
  EXYNOS5: Define EXYNOS5_I2C_SPACING
  EXYNOS: PINMUX: Add pinmux support for I2C
  I2C: Move struct s3c24x0_i2c to a common place.
  I2C: Modify the I2C driver for EXYNOS5
  I2C: Add support for Multi channel
  CONFIG: SMDK5250: I2C: Enable I2C

 arch/arm/cpu/armv7/exynos/clock.c   |   33 
 arch/arm/cpu/armv7/exynos/pinmux.c  |   52 +++
 arch/arm/include/asm/arch-exynos/clk.h  |1 +
 arch/arm/include/asm/arch-exynos/cpu.h  |5 +
 arch/arm/include/asm/arch-exynos/periph.h   |8 +
 arch/arm/include/asm/arch-s3c24x0/s3c24x0.h |   10 --
 board/samsung/smdk5250/smdk5250.c   |   23 +++-
 drivers/i2c/s3c24x0_i2c.c   |  220 ++-
 drivers/i2c/s3c24x0_i2c.h   |   33 
 include/configs/smdk5250.h  |8 +
 10 files changed, 307 insertions(+), 86 deletions(-)
 create mode 100644 drivers/i2c/s3c24x0_i2c.h

-- 
1.7.4.4

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[U-Boot] [PATCH 2/8 V6] EXYNOS: Add I2C base address.

[Rajeshwari Shinde]

This patch adds the base address for I2C.

Signed-off-by: Alim Akhtar 
Signed-off-by: Rajeshwari Shinde 
Acked-by: Simon Glass 
---
Changes in V2:
- None
Changes in V3:
- None
Changes in V4:
- None
Changes in V5:
- None
Changes in V6:
- None
 arch/arm/include/asm/arch-exynos/cpu.h |3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/arch-exynos/cpu.h 
b/arch/arm/include/asm/arch-exynos/cpu.h
index 0c341d4..ab46b70 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -49,6 +49,7 @@
 #define EXYNOS4_USB_HOST_EHCI_BASE 0x1258
 #define EXYNOS4_USBPHY_BASE0x125B
 #define EXYNOS4_UART_BASE  0x1380
+#define EXYNOS4_I2C_BASE   0x1386
 #define EXYNOS4_ADC_BASE   0x1391
 #define EXYNOS4_PWMTIMER_BASE  0x139D
 #define EXYNOS4_MODEM_BASE 0x13A0
@@ -76,6 +77,7 @@
 #define EXYNOS5_MMC_BASE   0x1220
 #define EXYNOS5_SROMC_BASE 0x1225
 #define EXYNOS5_UART_BASE  0x12C0
+#define EXYNOS5_I2C_BASE   0x12C6
 #define EXYNOS5_PWMTIMER_BASE  0x12DD
 #define EXYNOS5_GPIO_PART2_BASE0x1340
 #define EXYNOS5_FIMD_BASE  0x1440
@@ -148,6 +150,7 @@ SAMSUNG_BASE(adc, ADC_BASE)
 SAMSUNG_BASE(clock, CLOCK_BASE)
 SAMSUNG_BASE(sysreg, SYSREG_BASE)
 SAMSUNG_BASE(fimd, FIMD_BASE)
+SAMSUNG_BASE(i2c, I2C_BASE)
 SAMSUNG_BASE(mipi_dsim, MIPI_DSIM_BASE)
 SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE)
 SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE)
-- 
1.7.4.4

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[U-Boot] [PATCH 1/8 V6] EXYNOS: CLK: Add i2c clock

[Rajeshwari Shinde]

This adds i2c clock information for EXYNOS5.

Signed-off-by: Alim Akhtar 
Signed-off-by: Doug Anderson 
Signed-off-by: Rajeshwari Shinde 
Acked-by: Simon Glass 
---
changes in V2:
- Incorporated comments from Simon Glass which are removed extra
  braces around (readl(&clk->div_top1)) >> 24 and gave a tab space for
  return statement.
Changes in V3:
- None
Changes in V4:
- None
Changes in V5:
- None.
Changes in V6:
- Incorporated review comments from Simon Glass.
 arch/arm/cpu/armv7/exynos/clock.c  |   33 
 arch/arm/include/asm/arch-exynos/clk.h |1 +
 2 files changed, 34 insertions(+), 0 deletions(-)

diff --git a/arch/arm/cpu/armv7/exynos/clock.c 
b/arch/arm/cpu/armv7/exynos/clock.c
index 672598f..de3db8e 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -605,6 +605,29 @@ void exynos4_set_mipi_clk(void)
writel(cfg, &clk->div_lcd0);
 }
 
+/*
+ * I2C
+ *
+ * exynos5: obtaining the I2C clock
+ */
+static unsigned long exynos5_get_i2c_clk(void)
+{
+   struct exynos5_clock *clk =
+   (struct exynos5_clock *)samsung_get_base_clock();
+   unsigned long aclk_66, aclk_66_pre, sclk;
+   unsigned int ratio;
+
+   sclk = get_pll_clk(MPLL);
+
+   ratio = (readl(&clk->div_top1)) >> 24;
+   ratio &= 0x7;
+   aclk_66_pre = sclk / (ratio + 1);
+   ratio = readl(&clk->div_top0);
+   ratio &= 0x7;
+   aclk_66 = aclk_66_pre / (ratio + 1);
+   return aclk_66;
+}
+
 unsigned long get_pll_clk(int pllreg)
 {
if (cpu_is_exynos5())
@@ -621,6 +644,16 @@ unsigned long get_arm_clk(void)
return exynos4_get_arm_clk();
 }
 
+unsigned long get_i2c_clk(void)
+{
+   if (cpu_is_exynos5()) {
+   return exynos5_get_i2c_clk();
+   } else {
+   debug("I2C clock is not set for this CPU\n");
+   return 0;
+   }
+}
+
 unsigned long get_pwm_clk(void)
 {
if (cpu_is_exynos5())
diff --git a/arch/arm/include/asm/arch-exynos/clk.h 
b/arch/arm/include/asm/arch-exynos/clk.h
index e99339a..5529025 100644
--- a/arch/arm/include/asm/arch-exynos/clk.h
+++ b/arch/arm/include/asm/arch-exynos/clk.h
@@ -31,6 +31,7 @@
 
 unsigned long get_pll_clk(int pllreg);
 unsigned long get_arm_clk(void);
+unsigned long get_i2c_clk(void);
 unsigned long get_pwm_clk(void);
 unsigned long get_uart_clk(int dev_index);
 void set_mmc_clk(int dev_index, unsigned int div);
-- 
1.7.4.4

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[U-Boot] [PATCH 3/8 V6] EXYNOS5: define EXYNOS5_I2C_SPACING

[Rajeshwari Shinde]

This patch defined EXYNOS5_I2C_SPACING used to calculate I2C channel
base address.

Signed-off-by: Rajeshwari Shinde 
---
Changes in V6:
- New patch.
 arch/arm/include/asm/arch-exynos/cpu.h |2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/arch-exynos/cpu.h 
b/arch/arm/include/asm/arch-exynos/cpu.h
index ab46b70..0e6ea87 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -58,6 +58,8 @@
 #define EXYNOS4_GPIO_PART4_BASEDEVICE_NOT_AVAILABLE
 
 /* EXYNOS5 */
+#define EXYNOS5_I2C_SPACING0x1
+
 #define EXYNOS5_GPIO_PART4_BASE0x0386
 #define EXYNOS5_PRO_ID 0x1000
 #define EXYNOS5_CLOCK_BASE 0x1001
-- 
1.7.4.4

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[U-Boot] [PATCH 4/8 V6] EXYNOS: PINMUX: Add pinmux support for I2C

[Rajeshwari Shinde]

This patch adds pinmux code for I2C.

Signed-off-by: Rajeshwari Shinde 
Acked-by: Simon Glass 
---
Changes in V2:
- Aligned the pinmux functionality as per the latest comments.
Changes in V3:
- None
Changes in V4:
- None
Changes in V5:
- None
Changes in V6:
- None
 arch/arm/cpu/armv7/exynos/pinmux.c|   52 +
 arch/arm/include/asm/arch-exynos/periph.h |8 
 2 files changed, 60 insertions(+), 0 deletions(-)

diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c 
b/arch/arm/cpu/armv7/exynos/pinmux.c
index 0e91a6c..7776add 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -188,6 +188,48 @@ static void exynos5_sromc_config(int flags)
}
 }
 
+static void exynos5_i2c_config(int peripheral, int flags)
+{
+
+   struct exynos5_gpio_part1 *gpio1 =
+   (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
+
+   switch (peripheral) {
+   case PERIPH_ID_I2C0:
+   s5p_gpio_cfg_pin(&gpio1->b3, 0, GPIO_FUNC(0x2));
+   s5p_gpio_cfg_pin(&gpio1->b3, 1, GPIO_FUNC(0x2));
+   break;
+   case PERIPH_ID_I2C1:
+   s5p_gpio_cfg_pin(&gpio1->b3, 2, GPIO_FUNC(0x2));
+   s5p_gpio_cfg_pin(&gpio1->b3, 3, GPIO_FUNC(0x2));
+   break;
+   case PERIPH_ID_I2C2:
+   s5p_gpio_cfg_pin(&gpio1->a0, 6, GPIO_FUNC(0x3));
+   s5p_gpio_cfg_pin(&gpio1->a0, 7, GPIO_FUNC(0x3));
+   break;
+   case PERIPH_ID_I2C3:
+   s5p_gpio_cfg_pin(&gpio1->a1, 2, GPIO_FUNC(0x3));
+   s5p_gpio_cfg_pin(&gpio1->a1, 3, GPIO_FUNC(0x3));
+   break;
+   case PERIPH_ID_I2C4:
+   s5p_gpio_cfg_pin(&gpio1->a2, 0, GPIO_FUNC(0x3));
+   s5p_gpio_cfg_pin(&gpio1->a2, 1, GPIO_FUNC(0x3));
+   break;
+   case PERIPH_ID_I2C5:
+   s5p_gpio_cfg_pin(&gpio1->a2, 2, GPIO_FUNC(0x3));
+   s5p_gpio_cfg_pin(&gpio1->a2, 3, GPIO_FUNC(0x3));
+   break;
+   case PERIPH_ID_I2C6:
+   s5p_gpio_cfg_pin(&gpio1->b1, 3, GPIO_FUNC(0x4));
+   s5p_gpio_cfg_pin(&gpio1->b1, 4, GPIO_FUNC(0x4));
+   break;
+   case PERIPH_ID_I2C7:
+   s5p_gpio_cfg_pin(&gpio1->b2, 2, GPIO_FUNC(0x3));
+   s5p_gpio_cfg_pin(&gpio1->b2, 3, GPIO_FUNC(0x3));
+   break;
+   }
+}
+
 static int exynos5_pinmux_config(int peripheral, int flags)
 {
switch (peripheral) {
@@ -205,6 +247,16 @@ static int exynos5_pinmux_config(int peripheral, int flags)
case PERIPH_ID_SROMC:
exynos5_sromc_config(flags);
break;
+   case PERIPH_ID_I2C0:
+   case PERIPH_ID_I2C1:
+   case PERIPH_ID_I2C2:
+   case PERIPH_ID_I2C3:
+   case PERIPH_ID_I2C4:
+   case PERIPH_ID_I2C5:
+   case PERIPH_ID_I2C6:
+   case PERIPH_ID_I2C7:
+   exynos5_i2c_config(peripheral, flags);
+   break;
default:
debug("%s: invalid peripheral %d", __func__, peripheral);
return -1;
diff --git a/arch/arm/include/asm/arch-exynos/periph.h 
b/arch/arm/include/asm/arch-exynos/periph.h
index 5db25aa..b861d7d 100644
--- a/arch/arm/include/asm/arch-exynos/periph.h
+++ b/arch/arm/include/asm/arch-exynos/periph.h
@@ -30,6 +30,14 @@
  *
  */
 enum periph_id {
+   PERIPH_ID_I2C0,
+   PERIPH_ID_I2C1,
+   PERIPH_ID_I2C2,
+   PERIPH_ID_I2C3,
+   PERIPH_ID_I2C4,
+   PERIPH_ID_I2C5,
+   PERIPH_ID_I2C6,
+   PERIPH_ID_I2C7,
PERIPH_ID_SDMMC0,
PERIPH_ID_SDMMC1,
PERIPH_ID_SDMMC2,
-- 
1.7.4.4

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Re: [U-Boot] [PATCH v7 09/15] ARM: add tegra20 support to arm720t

[Simon Glass]

Hi Allen,

On Tue, Jul 17, 2012 at 12:02 AM, Allen Martin  wrote:
> Add support for tegra20 arm7 boot processor.  This processor is used
> to power on the Cortex A9 and transfer control to it.  In tegra this
> processor is an ARM7TDMI not an ARM720T, but since we don't use cache
> it was easier to just reuse the ARM720T code as the processors are
> otherwise identical except for cache and MMU.
>
> Signed-off-by: Allen Martin 
> Acked-by: Stephen Warren 
> Tested-by: Thierry Reding 
> ---
>  arch/arm/cpu/arm720t/cpu.c   |2 +
>  arch/arm/cpu/arm720t/interrupts.c|5 +
>  arch/arm/cpu/arm720t/start.S |6 +-
>  arch/arm/cpu/arm720t/tegra20/Makefile|   48 +
>  arch/arm/cpu/arm720t/tegra20/board.h |   25 +++
>  arch/arm/cpu/arm720t/tegra20/config.mk   |   26 +++
>  arch/arm/cpu/arm720t/tegra20/cpu.c   |  258 
> ++
>  arch/arm/cpu/arm720t/tegra20/cpu.h   |  100 ++
>  arch/arm/cpu/arm720t/tegra20/spl.c   |  132 +
>  arch/arm/include/asm/arch-tegra20/hardware.h |   29 +++
>  10 files changed, 630 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/cpu/arm720t/tegra20/Makefile
>  create mode 100644 arch/arm/cpu/arm720t/tegra20/board.h
>  create mode 100644 arch/arm/cpu/arm720t/tegra20/config.mk
>  create mode 100644 arch/arm/cpu/arm720t/tegra20/cpu.c
>  create mode 100644 arch/arm/cpu/arm720t/tegra20/cpu.h
>  create mode 100644 arch/arm/cpu/arm720t/tegra20/spl.c
>  create mode 100644 arch/arm/include/asm/arch-tegra20/hardware.h
>
> diff --git a/arch/arm/cpu/arm720t/cpu.c b/arch/arm/cpu/arm720t/cpu.c
> index 974f288..b6eee7e 100644
> --- a/arch/arm/cpu/arm720t/cpu.c
> +++ b/arch/arm/cpu/arm720t/cpu.c
> @@ -51,6 +51,8 @@ int cleanup_before_linux (void)
> /* Nothing more needed */
>  #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
> /* No cleanup before linux for IntegratorAP/CM720T as yet */
> +#elif defined (CONFIG_TEGRA)

Another little nit, shouldn't have space before (

Regards,
Simon
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[U-Boot] [PATCH 5/8 V6] I2C: Move struct s3c24x0_i2c to a common place.

[Rajeshwari Shinde]

struct s3c24x0_i2c is being moved to common local header file so that
the same can be used by s3c series and exynos series SoCs.

Signed-off-by: Alim Akhtar 
Signed-off-by: Doug Anderson 
Signed-off-by: Rajeshwari Shinde 
Acked-by: Simon Glass 
---
Changes in V2:
- None
Changes in V3:
- None
Changes in V4:
- None
Changes in V5:
- None
Changes in V6:
- None
 arch/arm/include/asm/arch-s3c24x0/s3c24x0.h |   10 
 drivers/i2c/s3c24x0_i2c.h   |   33 +++
 2 files changed, 33 insertions(+), 10 deletions(-)
 create mode 100644 drivers/i2c/s3c24x0_i2c.h

diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h 
b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
index ca978c9..0f75c31 100644
--- a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
+++ b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
@@ -343,16 +343,6 @@ struct s3c24x0_watchdog {
u32 wtcnt;
 };
 
-
-/* IIC (see manual chapter 20) */
-struct s3c24x0_i2c {
-   u32 iiccon;
-   u32 iicstat;
-   u32 iicadd;
-   u32 iicds;
-};
-
-
 /* IIS (see manual chapter 21) */
 struct s3c24x0_i2s {
 #ifdef __BIG_ENDIAN
diff --git a/drivers/i2c/s3c24x0_i2c.h b/drivers/i2c/s3c24x0_i2c.h
new file mode 100644
index 000..2dd4b06
--- /dev/null
+++ b/drivers/i2c/s3c24x0_i2c.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _S3C24X0_I2C_H
+#define _S3C24X0_I2C_H
+
+struct s3c24x0_i2c {
+   u32 iiccon;
+   u32 iicstat;
+   u32 iicadd;
+   u32 iicds;
+   u32 iiclc;
+};
+#endif /* _S3C24X0_I2C_H */
-- 
1.7.4.4

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[U-Boot] [PATCH 7/8 V6] I2C: Add support for Multi channel

[Rajeshwari Shinde]

This adds multiple i2c channel support for I2C.

Signed-off-by: Alim Akhtar 
Signed-off-by: Rajeshwari Shinde 
Acked-by: Simon Glass 
---
Changes in V2:
- None
Changes in V3:
- None
Changes in V4:
- None
Changes in V5:
- Pinmux setting of all bus done during board init.
Changes in V6:
- None
 drivers/i2c/s3c24x0_i2c.c |   27 +++
 1 files changed, 27 insertions(+), 0 deletions(-)

diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c
index 421c7dd..39a0365 100644
--- a/drivers/i2c/s3c24x0_i2c.c
+++ b/drivers/i2c/s3c24x0_i2c.c
@@ -158,6 +158,33 @@ static void i2c_ch_init(struct s3c24x0_i2c *i2c, int 
speed, int slaveadd)
writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat);
 }
 
+/*
+ * MULTI BUS I2C support
+ */
+
+#ifdef CONFIG_I2C_MULTI_BUS
+int i2c_set_bus_num(unsigned int bus)
+{
+   struct s3c24x0_i2c *i2c;
+
+   if ((bus < 0) || (bus >= CONFIG_MAX_I2C_NUM)) {
+   debug("Bad bus: %d\n", bus);
+   return -1;
+   }
+
+   g_current_bus = bus;
+   i2c = get_base_i2c();
+   i2c_ch_init(i2c, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+   return 0;
+}
+
+unsigned int i2c_get_bus_num(void)
+{
+   return g_current_bus;
+}
+#endif
+
 void i2c_init(int speed, int slaveadd)
 {
struct s3c24x0_i2c *i2c = get_base_i2c();
-- 
1.7.4.4

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[U-Boot] [PATCH 6/8 V6] I2C: Modify the I2C driver for EXYNOS5

[Rajeshwari Shinde]

This patch modifies the S3C I2C driver to suppport EXYNOS5.
The cahnges made to driver are as follows:
- I2C base address is passed as a parameter to many
functions to avoid multiple #ifdef
- Channel initialisation is moved to a commom funation
as it is required by i2c_init.
- Hardcoding for I2CCON_ACKGEN removed.
- Replaced printf with debug.
- Checkpatch issues resolved.
- Pinmux setting will be done in board/samsung/smdk5250/smdk5250.c
to avoid repeated setting of gpio lines, as it have multi bus support.

Signed-off-by: Alim Akhtar 
Signed-off-by: Doug Anderson 
Signed-off-by: Rajeshwari Shinde 
Acked-by: Simon Glass 
---
Changes in V2:
- Removed #define for I2C cahnnels from hearder file except for I2C0.
- Incorporated review comments from Simon Glass.
Changes in V3:
- Incorporated review comments from Joonyoung Shim.
- Reduced the number of #ifdef by modifying get_i2c_base function.
- Removed duplicate code.
Changes in V4:
- Resolved build error for s3c2410.
Changes in V5:
- Pinmux setting will be done in board/samsung/smdk5250/smdk5250.c
  to avoid repeated setting of gpio lines, as it have multi bus support.
- I2C bus offset calulation done based on EXYNOS_I2C_SPACING
- Peripharal related code removed.
Changes in V6:
- g_current_bus made common to all platforms.
 drivers/i2c/s3c24x0_i2c.c |  193 +++-
 1 files changed, 118 insertions(+), 75 deletions(-)

diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c
index ba6f39b..421c7dd 100644
--- a/drivers/i2c/s3c24x0_i2c.c
+++ b/drivers/i2c/s3c24x0_i2c.c
@@ -27,10 +27,15 @@
  */
 
 #include 
+#ifdef CONFIG_EXYNOS5
+#include 
+#include 
+#else
 #include 
-
+#endif
 #include 
 #include 
+#include "s3c24x0_i2c.h"
 
 #ifdef CONFIG_HARD_I2C
 
@@ -45,6 +50,7 @@
 
 #define I2CSTAT_BSY0x20/* Busy bit */
 #define I2CSTAT_NACK   0x01/* Nack bit */
+#define I2CCON_ACKGEN  0x80/* Acknowledge generation */
 #define I2CCON_IRPND   0x10/* Interrupt pending bit */
 #define I2C_MODE_MT0xC0/* Master Transmit Mode */
 #define I2C_MODE_MR0x80/* Master Receive Mode */
@@ -53,6 +59,10 @@
 
 #define I2C_TIMEOUT 1  /* 1 second */
 
+
+static unsigned int g_current_bus; /* Stores Current I2C Bus */
+
+#ifndef CONFIG_EXYNOS5
 static int GetI2CSDA(void)
 {
struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
@@ -77,16 +87,17 @@ static void SetI2CSCL(int x)
struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
 
 #ifdef CONFIG_S3C2410
-   writel((readl(&gpio->gpedat) & ~0x4000) | (x & 1) << 14, &gpio->gpedat);
+   writel((readl(&gpio->gpedat) & ~0x4000) |
+   (x & 1) << 14, &gpio->gpedat);
 #endif
 #ifdef CONFIG_S3C2400
writel((readl(&gpio->pgdat) & ~0x0040) | (x & 1) << 6, &gpio->pgdat);
 #endif
 }
+#endif
 
-static int WaitForXfer(void)
+static int WaitForXfer(struct s3c24x0_i2c *i2c)
 {
-   struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c();
int i;
 
i = I2C_TIMEOUT * 1;
@@ -98,35 +109,77 @@ static int WaitForXfer(void)
return (readl(&i2c->iiccon) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT;
 }
 
-static int IsACK(void)
+static int IsACK(struct s3c24x0_i2c *i2c)
 {
-   struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c();
-
return !(readl(&i2c->iicstat) & I2CSTAT_NACK);
 }
 
-static void ReadWriteByte(void)
+static void ReadWriteByte(struct s3c24x0_i2c *i2c)
 {
-   struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c();
-
writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon);
 }
 
+static struct s3c24x0_i2c *get_base_i2c(void)
+{
+#ifdef CONFIG_EXYNOS5
+   struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c()
+   + (EXYNOS5_I2C_SPACING
+   * g_current_bus));
+   return i2c;
+#else
+   return s3c24x0_get_base_i2c();
+#endif
+}
+
+static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
+{
+   ulong freq, pres = 16, div;
+#ifdef CONFIG_EXYNOS5
+   freq = get_i2c_clk();
+#else
+   freq = get_PCLK();
+#endif
+   /* calculate prescaler and divisor values */
+   if ((freq / pres / (16 + 1)) > speed)
+   /* set prescaler to 512 */
+   pres = 512;
+
+   div = 0;
+   while ((freq / pres / (div + 1)) > speed)
+   div++;
+
+   /* set prescaler, divisor according to freq, also set ACKGEN, IRQ */
+   writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon);
+
+   /* init to SLAVE REVEIVE and set slaveaddr */
+   writel(0, &i2c->iicstat);
+   writel(slaveadd, &i2c->iicadd);
+   /* program Master Transmit (and implicit STOP) */
+   writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iics

[U-Boot] [PATCH 8/8 V6] CONFIG: SMDK5250: I2C: Enable I2C

[Rajeshwari Shinde]

This enables I2C support on smdk5250.
Pinmux setting moved to board file to avoid repeated setting of
gpio lines.

Signed-off-by: Alim Akhtar 
Signed-off-by: Doug Anderson 
Signed-off-by: Rajeshwari Shinde 
Acked-by: Simon Glass 
---
Changes in V2:
- None
Changes in V3:
- None
Changes in V4:
- None
Changes in V5:
- Pinmux setting of gpio lines moved to board_early_init_f.
Chnages in V6:
- EXYNOS_I2C_SPACING moved to cpu.h
- board_i2c_init compiled only when CONFIG_DRIVER_S3C24X0_I2C is 
defined.
 board/samsung/smdk5250/smdk5250.c |   28 +++-
 include/configs/smdk5250.h|8 
 2 files changed, 35 insertions(+), 1 deletions(-)

diff --git a/board/samsung/smdk5250/smdk5250.c 
b/board/samsung/smdk5250/smdk5250.c
index b593325..12e6e66 100644
--- a/board/samsung/smdk5250/smdk5250.c
+++ b/board/samsung/smdk5250/smdk5250.c
@@ -172,9 +172,35 @@ static int board_uart_init(void)
return 0;
 }
 
+#ifdef CONFIG_DRIVER_S3C24X0_I2C
+static int board_i2c_init(void)
+{
+   int i, err;
+
+   for (i = 0; i < CONFIG_MAX_I2C_NUM; i++) {
+   err = exynos_pinmux_config((PERIPH_ID_I2C0 + i),
+   PINMUX_FLAG_NONE);
+   if (err) {
+   debug("I2C%d not configured\n", (PERIPH_ID_I2C0 + i));
+   return err;
+   }
+   }
+   return 0;
+}
+#endif
+
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {
-   return board_uart_init();
+   int err;
+   err = board_uart_init();
+   if (err) {
+   debug("UART init failed\n");
+   return err;
+   }
+#ifdef CONFIG_DRIVER_S3C24X0_I2C
+   err = board_i2c_init();
+#endif
+   return err;
 }
 #endif
diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h
index c0eaaf8..65dfe9f 100644
--- a/include/configs/smdk5250.h
+++ b/include/configs/smdk5250.h
@@ -198,6 +198,14 @@
 
 #define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_LOAD_ADDR - 0x100)
 
+/* I2C */
+#define CONFIG_HARD_I2C
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C_SPEED   10  /* 100 Kbps */
+#define CONFIG_DRIVER_S3C24X0_I2C
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_MAX_I2C_NUM 8
+
 /* Ethernet Controllor Driver */
 #ifdef CONFIG_CMD_NET
 #define CONFIG_SMC911X
-- 
1.7.4.4

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Re: [U-Boot] i.MX dcache issues

[Benoît Thébaudeau]

Hi all,

On Tue, Jul 17, 2012 at 12:30:22AM +0200, Marek Vasut wrote:
> Dear Dirk Behme,
> 
> > On 15.07.2012 00:08, Benoît Thébaudeau wrote:
> > > On Sat, Jul 14, 2012 at 11:28:03PM +0200, Benoît Thébaudeau
> > > wrote:
> > >> Shouldn't the MMC/eSDHC drivers flush/invalidate the dcache
> > >> ranges
> > >> that they use
> > >> for DMA operations? Not doing so would explain why
> > >> stack-allocated
> > >> buffers are
> > >> more affected than buffers in unused RAM areas.
> > > 
> > > That will help:
> > > http://git.denx.de/?p=u-boot/u-boot-mmc.git;a=commitdiff;h=e576bd90f94080
> > > 6b989ffd666552081f17f032c8
> > 
> > Are you sure that this patch does really help?
> > 
> > If I remember correctly (will re-check) we have this patch locally
> > applied. But even with this patch, we have issues so that we
> > enabled
> > CONFIG_SYS_DCACHE_OFF, i.e. disabled the dcache.
> 
> Try using the bounce buffer as I do on mx28.
> 
> > The issues we observed *without* CONFIG_SYS_DCACHE_OFF: The SD card
> > was detected as 1-bit only (mmcinfo), while with dcache off it was
> > used as 4-bit. Debugging this showed that wrong configuration data
> > was
> > read [1]. Having a fat partition on the card, mmc part/fatls etc
> > failed, too, with cache enabled.
> 
> Ad caches -- FEC should be fixed on these platforms, USB might work,
> MMC should
> work if you use the bounce buffer. FAT should be fixed, so should be
> ext2

I have switched to the git head, and applied all the latest EHCI/MSC patches
from u-boot-usb-next. Since then, all my MMC/EHCI/FEC i.MX DMA issues are
resolved, except on i.MX35 because of a huge bug in the handling of cache range
checks on ARM1136. I have just posted a patch that fixes this issue.

Best regards,
Benoît
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Re: [U-Boot] i.MX dcache issues

[Marek Vasut]

Dear Benoît Thébaudeau,

> Hi all,
> 
> On Tue, Jul 17, 2012 at 12:30:22AM +0200, Marek Vasut wrote:
> > Dear Dirk Behme,
> > 
> > > On 15.07.2012 00:08, Benoît Thébaudeau wrote:
> > > > On Sat, Jul 14, 2012 at 11:28:03PM +0200, Benoît Thébaudeau
> > > > 
> > > > wrote:
> > > >> Shouldn't the MMC/eSDHC drivers flush/invalidate the dcache
> > > >> ranges
> > > >> that they use
> > > >> for DMA operations? Not doing so would explain why
> > > >> stack-allocated
> > > >> buffers are
> > > >> more affected than buffers in unused RAM areas.
> > > > 
> > > > That will help:
> > > > http://git.denx.de/?p=u-boot/u-boot-mmc.git;a=commitdiff;h=e576bd90f9
> > > > 4080 6b989ffd666552081f17f032c8
> > > 
> > > Are you sure that this patch does really help?
> > > 
> > > If I remember correctly (will re-check) we have this patch locally
> > > applied. But even with this patch, we have issues so that we
> > > enabled
> > > CONFIG_SYS_DCACHE_OFF, i.e. disabled the dcache.
> > 
> > Try using the bounce buffer as I do on mx28.
> > 
> > > The issues we observed *without* CONFIG_SYS_DCACHE_OFF: The SD card
> > > was detected as 1-bit only (mmcinfo), while with dcache off it was
> > > used as 4-bit. Debugging this showed that wrong configuration data
> > > was
> > > read [1]. Having a fat partition on the card, mmc part/fatls etc
> > > failed, too, with cache enabled.
> > 
> > Ad caches -- FEC should be fixed on these platforms, USB might work,
> > MMC should
> > work if you use the bounce buffer. FAT should be fixed, so should be
> > ext2
> 
> I have switched to the git head, and applied all the latest EHCI/MSC
> patches from u-boot-usb-next. Since then, all my MMC/EHCI/FEC i.MX DMA
> issues are resolved, except on i.MX35 because of a huge bug in the
> handling of cache range checks on ARM1136. I have just posted a patch that
> fixes this issue.

AARGH! Thank you very much!

> Best regards,
> Benoît

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] ARM1136: Fix cache range checks

[Stefano Babic]

On 19/07/2012 13:35, Benoît Thébaudeau wrote:
> bad_cache_range actually returned true if the range was OK, but it was used
> according to its name, which resulted in all valid dcache range 
> invalidate/flush
> operations being dropped. Hence, most DMA transfers resulted in garbage data.
> 
> This patch renames this function according to what it does, and it fixes the
> interpretation of its return value by other functions. The chosen naming is 
> the
> same as for ARM926EJ-S in order to be consistent.
> 
> Signed-off-by: Benoît Thébaudeau 
> Cc: Albert Aribaud 
> ---

Hi Benoît,

thanks for fix this !

>  .../arch/arm/cpu/arm1136/cpu.c |6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git u-boot-66714b1.orig/arch/arm/cpu/arm1136/cpu.c 
> u-boot-66714b1/arch/arm/cpu/arm1136/cpu.c
> index f72bab6..b98e3d9 100644
> --- u-boot-66714b1.orig/arch/arm/cpu/arm1136/cpu.c
> +++ u-boot-66714b1/arch/arm/cpu/arm1136/cpu.c
> @@ -95,7 +95,7 @@ void flush_dcache_all(void)
>   asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
>  }
>  
> -static inline int bad_cache_range(unsigned long start, unsigned long stop)
> +static int check_cache_range(unsigned long start, unsigned long stop)
>  {
>   int ok = 1;
>  
> @@ -114,7 +114,7 @@ static inline int bad_cache_range(unsigned long start, 
> unsigned long stop)
>  
>  void invalidate_dcache_range(unsigned long start, unsigned long stop)
>  {
> - if (bad_cache_range(start, stop))
> + if (!check_cache_range(start, stop))
>   return;
>  
>   while (start < stop) {
> @@ -125,7 +125,7 @@ void invalidate_dcache_range(unsigned long start, 
> unsigned long stop)
>  
>  void flush_dcache_range(unsigned long start, unsigned long stop)
>  {
> - if (bad_cache_range(start, stop))
> + if (!check_cache_range(start, stop))
>   return;
>  
>   while (start < stop) {

Acked-by: Stefano Babic 

Albert, this is surely a fix - can you apply it for the release ?

Thanks,
Stefano

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Re: [U-Boot] [PATCH 0/17] tegra: Add display driver and LCD support for Seaboard

[Christian Kroehnert]

Am 18.07.2012 08:51, schrieb Simon Glass:

+Tom, Stephen

On Tue, Jul 17, 2012 at 5:11 PM, Thierry Reding
 wrote:

On Sat, Jul 14, 2012 at 10:03:31AM +0200, Simon Glass wrote:

Hi Christian,

On Thu, Apr 19, 2012 at 2:41 PM, Christian Kroehnert
 wrote:

On 15.01.2012 01:47, Simon Glass wrote:


This series adds support for the Tegra2x's display peripheral. This
supports the LCD display on Seaboard and we use this to enable console
output in U-Boot on the LCD.

Configuration is via the device tree. Proposed bindings are included
in this series.

To improve performance two optimisations are offered:

1. The LCD frame buffer is cached, with the cache being flushed after
each call puts(). This dramatically increases performance (around 10x).
This requires a few additions to the ARM cache support.

2. The console supports scrolling in steps of more than 1 line. This
speeds up scrolling output considerably, particularly commands like
'printenv' which display a lot of output. This requires a new CONFIG
and a change to the console_scrollup() function.


Mayuresh Kulkarni (1):
tegra: Enable display/lcd support on Seaboard

Simon Glass (15):
fdt: Add function to look up a phandle's register address
fdt: Add header guard to fdtdec.h
fdt: Correct GPIO name access in fdtdec
tegra: Add display support to funcmux
tegra: fdt: Add LCD definitions for Tegra
tegra: Add support for PWFM
tegra: Add LCD driver
tegra: Add LCD support to Nvidia boards
arm: Add control over cachability of memory regions
lcd: Add CONFIG_ALIGN_LCD_TO_SECTION to align lcd for MMU
lcd: Add support for flushing LCD fb from dcache after update
tegra: Align LCD frame buffer to section boundary
tegra: Support control of cache settings for LCD
tegra: fdt: Add LCD definitions for Seaboard
lcd: Add CONSOLE_SCROLL_LINES option to speed console

Wei Ni (1):
tegra: Add SOC support for display/lcd

   README  |   16 +
   arch/arm/cpu/armv7/cache_v7.c   |   11 +
   arch/arm/cpu/armv7/tegra2/Makefile  |1 +
   arch/arm/cpu/armv7/tegra2/display.c |  271 +++
   arch/arm/cpu/armv7/tegra2/funcmux.c |   39 ++
   arch/arm/cpu/armv7/tegra2/pwfm.c|   40 ++
   arch/arm/dts/tegra20.dtsi   |   25 +
   arch/arm/include/asm/arch-tegra2/dc.h   |  544
+++
   arch/arm/include/asm/arch-tegra2/display.h  |  133 ++
   arch/arm/include/asm/arch-tegra2/pwfm.h |   54 +++
   arch/arm/include/asm/system.h   |   30 ++
   arch/arm/lib/cache-cp15.c   |   62 +++-
   board/nvidia/common/board.c |   21 +-
   board/nvidia/dts/tegra2-seaboard.dts|   21 +
   common/cmd_echo.c   |3 +-
   common/lcd.c|   85 +++-
   doc/device-tree-bindings/video/nvidia-video.txt |   92 
   drivers/video/Makefile  |1 +
   drivers/video/tegra.c   |  388 
   include/configs/seaboard.h  |   12 +-
   include/configs/tegra2-common.h |1 +
   include/fdtdec.h|   17 +
   include/lcd.h   |   11 +
   lib/fdtdec.c|   15 +-
   24 files changed, 1862 insertions(+), 31 deletions(-)
   create mode 100644 arch/arm/cpu/armv7/tegra2/display.c
   create mode 100644 arch/arm/cpu/armv7/tegra2/pwfm.c
   create mode 100644 arch/arm/include/asm/arch-tegra2/dc.h
   create mode 100644 arch/arm/include/asm/arch-tegra2/display.h
   create mode 100644 arch/arm/include/asm/arch-tegra2/pwfm.h
   create mode 100644 doc/device-tree-bindings/video/nvidia-video.txt
   create mode 100644 drivers/video/tegra.c



Hi Simon,

I have added your patch sources manually into the "Prepare v2012.04-rc1
release", because I got errors at apply. Also I added a device tree source
file for Harmony.

I tested the device tree source file for Harmony and your patch sources on
our Harmony hardware and generated a new patch file:

http://poeggi.dotsec.net/nvidia/uboot-lvds-init-patch/0001-Add-display-driver-and-LCD-support-for-Harmony-board.patch

I hope it's all okay, this my first patch release.

In the display.c source file I implemented a bug fix, because I get garbled
images on the LCD without this fix.


I see this code:

   u32 m_value;

   m_value = readl(0x54202e04);
   m_value &= ~0x2;
   writel(m_value, 0x54202e04);

What register are you actually writing here? I can't find it in my
manual, but maybe I just haven't seen that address.


At the time I did look for that register as well but couldn't find
anything. But I believe that we saw the garbled display issue that
has been mentioned in another thread. If I remember correctly this
particular register wr

[U-Boot] [PATCH 1/2] net: fec_mxc: Fix setting of RCR for xMII

[Benoît Thébaudeau]

At least on i.MX25, the RMII mode did not work, which is fixed by this patch.

The MII_MODE bit of the FEC RCR register means xMII, i.e. 'not 7-wire', so set
it accordingly.

According to the xMII and 7-wire (aka GPSI) standards, full duplex should be
available on xMII, but not on 7-wire, so set FCE accordingly. The FEC may
support full duplex for 7-wire too, but the reference manual does not say that,
so avoid an invalid assumption. Actually, the choice between half and full
duplex also depends on the endpoint/switch/repeater configuration, so a config
option could be added for that, but there has been no need for it so far.

Signed-off-by: Benoît Thébaudeau 
Cc: Joe Hershberger 
Cc: Stefano Babic 
---
 .../drivers/net/fec_mxc.c  |8 +++-
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git u-boot-66714b1.orig/drivers/net/fec_mxc.c 
u-boot-66714b1/drivers/net/fec_mxc.c
index eee41d7..c64a223 100644
--- u-boot-66714b1.orig/drivers/net/fec_mxc.c
+++ u-boot-66714b1/drivers/net/fec_mxc.c
@@ -424,14 +424,12 @@ static void fec_reg_setup(struct fec_priv *fec)
 
/* Start with frame length = 1518, common for all modes. */
rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
-   if (fec->xcv_type == SEVENWIRE)
-   rcntrl |= FEC_RCNTRL_FCE;
-   else if (fec->xcv_type == RGMII)
+   if (fec->xcv_type != SEVENWIRE) /* xMII modes */
+   rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
+   if (fec->xcv_type == RGMII)
rcntrl |= FEC_RCNTRL_RGMII;
else if (fec->xcv_type == RMII)
rcntrl |= FEC_RCNTRL_RMII;
-   else/* MII mode */
-   rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
 
writel(rcntrl, &fec->eth->r_cntrl);
 }
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[U-Boot] [PATCH 2/2] net: fec_mxc: Fix MDC for xMII

[Benoît Thébaudeau]

The MDC signal is available on all xMII (i.e. 'not 7-wire') interfaces, so
mii_speed has to be set for all these interfaces, and not only for MII.

Signed-off-by: Benoît Thébaudeau 
Cc: Joe Hershberger 
Cc: Stefano Babic 
---
 .../drivers/net/fec_mxc.c  |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git u-boot-66714b1.orig/drivers/net/fec_mxc.c 
u-boot-66714b1/drivers/net/fec_mxc.c
index c64a223..e25cde0 100644
--- u-boot-66714b1.orig/drivers/net/fec_mxc.c
+++ u-boot-66714b1/drivers/net/fec_mxc.c
@@ -597,7 +597,7 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
 
fec_reg_setup(fec);
 
-   if (fec->xcv_type == MII10 || fec->xcv_type == MII100)
+   if (fec->xcv_type != SEVENWIRE)
fec_mii_setspeed(fec);
 
/*
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[U-Boot] I apply to maintain S3C6400 board for u-boot

[Zhong Hongbo]

Hi Denx,

I get some information from MAINTAINERS file. I know The board of
S3C6400 is a orphaned board. Also I have not the board, But I have a
S3C6410 board in my hand. In my development u-boot for my board, I know
the S3C6410 replace the s3c6400, and they use the same arm1176
architecture. So I think that I can help do a little thing for S3C6400's
u-boot.

In the recently, I send the patch serial of S3C6400. This patch
is very important for S3C64XX. It clear the old method to operate the
I/O port, and adopt the new SPL boot to reduce the code number. I expect
get the advice for this patch. But I wait for a long time, I do not know
who can help me to review this patch? who can merge this patch?

If anyone believe me, I will continue to maintain the board, Maybe I
have some limitation, Such as I have a poor english.  But I believe I
can keep the board can work normal in u-boot mainline, and I will reply
the email about S3C64xx CPU in time.

What do you think it?

Thanks
hongbo
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Re: [U-Boot] I apply to maintain S3C6400 board for u-boot

[Zhong Hongbo]

On 07/19/2012 08:21 PM, Zhong Hongbo wrote:
> Hi Denx,
> 
> I get some information from MAINTAINERS file. I know The board of
> S3C6400 is a orphaned board. Also I have not the board, But I have a
> S3C6410 board in my hand. In my development u-boot for my board, I know
> the S3C6410 replace the s3c6400, and they use the same arm1176
> architecture. So I think that I can help do a little thing for S3C6400's
> u-boot.
> 
> In the recently, I send the patch serial of S3C6400. This patch
> is very important for S3C64XX. It clear the old method to operate the
> I/O port, and adopt the new SPL boot to reduce the code number. I expect
> get the advice for this patch. But I wait for a long time, I do not know
> who can help me to review this patch? who can merge this patch?
Sorry, I check the patchwork. I found this patch are delegated to Minkyu
Kang. But I can not receive the notify email.

Thanks,
hongbo
> 
> If anyone believe me, I will continue to maintain the board, Maybe I
> have some limitation, Such as I have a poor english.  But I believe I
> can keep the board can work normal in u-boot mainline, and I will reply
> the email about S3C64xx CPU in time.
> 
> What do you think it?
> 
> Thanks
> hongbo
> 


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Re: [U-Boot] i.MX dcache issues

[Stefano Babic]

On 19/07/2012 13:43, Benoît Thébaudeau wrote:
> Hi all,
> 

Hi,

> I have switched to the git head, and applied all the latest EHCI/MSC patches
> from u-boot-usb-next.

Marek, should we maybe try to merge these patches still in the incoming
release ? It makes no sense if the release is broken and we have already
a solution to fix it.

> Since then, all my MMC/EHCI/FEC i.MX DMA issues are
> resolved, except on i.MX35 because of a huge bug in the handling of cache 
> range
> checks on ARM1136. I have just posted a patch that fixes this issue.

Thanks for fixing !

Best regards,
Stefano Babic


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Re: [U-Boot] i.MX dcache issues

[Marek Vasut]

Dear Stefano Babic,

> On 19/07/2012 13:43, Benoît Thébaudeau wrote:
> > Hi all,
> 
> Hi,
> 
> > I have switched to the git head, and applied all the latest EHCI/MSC
> > patches from u-boot-usb-next.
> 
> Marek, should we maybe try to merge these patches still in the incoming
> release ? It makes no sense if the release is broken and we have already
> a solution to fix it.

But Wolfgang will make three small ones of me if they break anything ;-) like 
with the last release, I'm really a bit cautious here. But ok then, I'll grow 
some balls and submit a pull request ;-)

> > Since then, all my MMC/EHCI/FEC i.MX DMA issues are
> > resolved, except on i.MX35 because of a huge bug in the handling of cache
> > range checks on ARM1136. I have just posted a patch that fixes this
> > issue.
> 
> Thanks for fixing !
> 
> Best regards,
> Stefano Babic

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] video: cfb_console: flush dcache for frame buffer in DRAM

[Mike Frysinger]

On Tuesday 05 June 2012 03:28:40 Anatolij Gustschin wrote:
> On Sat, 28 Apr 2012 17:04:07 +0200 Anatolij Gustschin wrote:
> > Data cache flushing is required for frame buffer in RAM to fix the
> > distorted console text output. Currently this text distortion is
> > observed with cfb on beageboard and N900 when running with data
> > cache enabled.
> 
> Applied to u-boot-video/master after rebasing and fixing commit log.

this patch is still wrong for the reasons i cited earlier.  your cache 
functions are broken, not the driver.
-mike


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Re: [U-Boot] [PATCH] Added watchdog support for davinchi_dm365evm

[Mike Frysinger]

On Saturday 02 June 2012 11:32:14 Stijn Souffriau wrote:
> On 05/20/2012 08:59 PM, Mike Frysinger wrote:
> > On Sunday 20 May 2012 12:50:40 Stijn Souffriau wrote:
> >> --- a/board/davinci/dm365evm/dm365evm.c
> >> +++ b/board/davinci/dm365evm/dm365evm.c
> >> 
> >> +#ifdef CONFIG_HW_WATCHDOG
> >> +static struct davinci_timer * const wdttimer =
> >> +(struct davinci_timer *)CONFIG_SYS_WDTTIMERBASE;
> >> +
> >> +/* WDTCR bit definitions */
> >> +#define WDEN(1<<  14)
> >> +#define WDFLAG  (1<<  15)
> >> +#define WDKEY_SEQ0  (0xa5c6<<  16)
> >> +#define WDKEY_SEQ1  (0xda7e<<  16)
> > 
> > if this is an on-chip hardware block, this stuff should be in an
> > SoC-specific header
> 
> Yes but as far as I know It only works for the davinci dm356evm.

if it's part of the SoC, then i don't see how it could only work for one 
board.  SoC bits belong in the SoC tree (arch/arm//...) while board bits 
belong in the board tree (board/...).
-mike


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Re: [U-Boot] [PATCH] nds32: split common cache access from cpu into lib

[Mike Frysinger]

On Thursday 19 July 2012 05:02:21 Marek Vasut wrote:
> Dear Mike Frysinger,
> > On Sunday 15 July 2012 04:12:45 Marek Vasut wrote:
> > > Dear Macpaul Lin,
> > > > +void flush_cache(unsigned long addr, unsigned long size)
> > > > +{
> > > > +   flush_dcache_range(addr, addr + size);
> > > > +   invalidate_icache_range(addr, addr + size);
> > > 
> > > You probably want to flush dcache in here and that's it.
> > 
> > i don't think so ... i think that's what flush_dcache_range() is for. 
> > and our common/cmd_*.c files assume that flush_cache() will invalidate
> > icache (see the bootm/load funcs that write executable content into
> > memory and then flush the regions).
> 
> Than it's borked on arm926ejs too ... ?

if it doesn't flush icache in the flush_cache() function, then i would say so

sounds like we should rip all this cache stuff out of common.h and into like 
cache.h so we can document the API expectations.  i think Wolfgang was against 
this before, but maybe that was just creating a header for one specific cache 
macro and not all cache stuff ?
-mike


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Re: [U-Boot] [PATCH v3 02/18] fdt: Add header guard to fdtdec.h

[Mike Frysinger]

On Thursday 12 July 2012 11:25:02 Simon Glass wrote:
> This makes it easier to include this header from other headers.

Acked-by: Mike Frysinger 

> --- a/include/fdtdec.h
> +++ b/include/fdtdec.h
>
>  const u8 *fdtdec_locate_byte_array(const void *blob, int node,
>const char *prop_name, int count);
> +#endif

personally, i like seeing a blank line before the final #endif
-mike


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Re: [U-Boot] [PATCH v3 03/18] tegra: Use const for pinmux_config_pingroup/table()

[Mike Frysinger]

Acked-by: Mike Frysinger 
-mike


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Re: [U-Boot] [PATCH v3 04/18] tegra: Add display support to funcmux

[Mike Frysinger]

Acked-by: Mike Frysinger 
-mike


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Re: [U-Boot] [PATCH v3 07/18] tegra: Add support for PWM

[Mike Frysinger]

On Thursday 12 July 2012 11:25:07 Simon Glass wrote:
> --- a/arch/arm/cpu/armv7/tegra2/Makefile
> +++ b/arch/arm/cpu/armv7/tegra2/Makefile
>
> +COBJS-$(CONFIG_VIDEO_TEGRA) += pwm.o

should this get its own knob ?  PWM isn't video specific ...
-mike


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Re: [U-Boot] [PATCH v3 12/18] lcd: Add CONFIG_LCD_ALIGNMENT to select frame buffer alignment

[Mike Frysinger]

On Thursday 12 July 2012 11:25:12 Simon Glass wrote:
> --- a/common/lcd.c
> +++ b/common/lcd.c
>
> +#ifdef CONFIG_ARM
> +#include 
> +#endif

this header isn't ARM specific.  also, i think most arches just include this in 
their "main" points rather than any non-arch places including it explicitly.
-mike


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Re: [U-Boot] [PATCH v3 13/18] lcd: Add support for flushing LCD fb from dcache after update

[Mike Frysinger]

On Thursday 12 July 2012 11:25:13 Simon Glass wrote:
> --- a/common/lcd.c
> +++ b/common/lcd.c
> 
> +/* Flush LCD activity to the caches */
> +void lcd_sync(void)
> +{
> + /*
> +  * flush_dcache_range() is declared in common.h but it seems that some
> +  * architectures do not actually implement it. Is there a way to find
> +  * out whether it exists? For now, ARM is safe.
> +  */
> +#ifdef CONFIG_ARM
> + int line_length;
> +
> + if (lcd_flush_dcache)
> + flush_dcache_range((u32)lcd_base,
> + (u32)(lcd_base + lcd_get_size(&line_length)));
> +#endif
> +}

we should just let those people build fail imo so they'll be forced to add 
this
-mike


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Re: [U-Boot] [PATCH v3 14/18] tegra: Align LCD frame buffer to section boundary

[Mike Frysinger]

Acked-by: Mike Frysinger 
-mike


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Re: [U-Boot] [PATCH] nds32: split common cache access from cpu into lib

[Marek Vasut]

Dear Mike Frysinger,

> On Thursday 19 July 2012 05:02:21 Marek Vasut wrote:
> > Dear Mike Frysinger,
> > 
> > > On Sunday 15 July 2012 04:12:45 Marek Vasut wrote:
> > > > Dear Macpaul Lin,
> > > > 
> > > > > +void flush_cache(unsigned long addr, unsigned long size)
> > > > > +{
> > > > > + flush_dcache_range(addr, addr + size);
> > > > > + invalidate_icache_range(addr, addr + size);
> > > > 
> > > > You probably want to flush dcache in here and that's it.
> > > 
> > > i don't think so ... i think that's what flush_dcache_range() is for.
> > > and our common/cmd_*.c files assume that flush_cache() will invalidate
> > > icache (see the bootm/load funcs that write executable content into
> > > memory and then flush the regions).
> > 
> > Than it's borked on arm926ejs too ... ?
> 
> if it doesn't flush icache in the flush_cache() function, then i would say
> so
> 
> sounds like we should rip all this cache stuff out of common.h and into
> like cache.h so we can document the API expectations.  i think Wolfgang
> was against this before, but maybe that was just creating a header for one
> specific cache macro and not all cache stuff ?

Certainly this sounds good. We'd also be able to add some nice instrumentation 
while at that, to detect problematic cases with DEBUG enabled or so. The cache 
stuff is starting to get really crazy.

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v3 17/18] lcd: Add CONSOLE_SCROLL_LINES option to speed console

[Mike Frysinger]

On Thursday 12 July 2012 11:25:17 Simon Glass wrote:
> --- a/README
> +++ b/README
> 
> + CONSOLE_SCROLL_LINES
> +
> + When the console need to be scrolled, this is the number of
> + lines to scroll by. It defaults to 1. Increasing this makes
> + the console jump but can help speed up operation when scrolling
> + is slow.

board knobs should be CONFIG_xxx

> --- a/common/lcd.c
> +++ b/common/lcd.c
> 
>  static void console_scrollup (void)
>  {
> + int rows = 1;
> +
> +#ifdef CONSOLE_SCROLL_LINES
> + rows = CONSOLE_SCROLL_LINES;
> +#endif

seems like this should be at the top of the file:
#ifndef CONSOLE_SCROLL_LINES
# define CONSOLE_SCROLL_LINES 1
#endif
-mike


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Re: [U-Boot] [PATCH v3 11/18] arm: Add control over cachability of memory regions

[Mike Frysinger]

On Thursday 12 July 2012 14:12:41 Albert ARIBAUD wrote:
> On Thu, 12 Jul 2012 08:25:11 -0700, Simon Glass wrote:
> > --- a/arch/arm/include/asm/system.h
> > +++ b/arch/arm/include/asm/system.h
> > 
> > +/* options available for data cache on each page */
> > +enum dcache_option {
> > +   DCACHE_OFF,
> > +   DCACHE_WRITETHROUGH,
> > +   DCACHE_WRITEBACK,
> > +};
> >
> > --- a/arch/arm/lib/cache-cp15.c
> > +++ b/arch/arm/lib/cache-cp15.c
> > 
> > -static inline void dram_bank_mmu_setup(int bank)
> > +void set_section_dcache(int section, enum dcache_option option)
> >  {
> > +   u32 value = section << MMU_SECTION_SHIFT | (3 << 10);
> > u32 *page_table = (u32 *)gd->tlb_addr;
> > +
> > +   switch (option) {
> > +   case DCACHE_WRITETHROUGH:
> > +   value |= 0x1a;
> > +   break;
> > +
> > +   case DCACHE_WRITEBACK:
> > +   value |= 0x1e;
> > +   break;
> > +
> > +   case DCACHE_OFF:
> > +   value |= 0x12;
> > +   break;
> > +   }
> 
> what's the benefit of introducing an arbitrary enum rather than
> defining DCACHE_WRITETHROUGH, DCACHE_WRITEBACK and DCACHE_OFF equal
> respecitvely to 0x1a, 0x1e and 0x12? All it does is force this
> switch case instead of a simple 'value |= option;' statement.

if these magic bitmasks are going to be the same for all arm cores (the enum 
is in common arm header), then you can get the advantages of both:
enum dcache_option {
DCACHE_OFF = 0x12,
DCACHE_WRITETHROUGH = 0x1a,
DCACHE_WRITEBACK = 0x1e,
};

then just do:
value |= option;
-mike


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Re: [U-Boot] [PATCH v3 08/18] tegra: Add SOC support for display/lcd

[Mike Frysinger]

On Thursday 19 July 2012 04:03:04 Adam Jiang wrote:
> On Thu, Jul 12, 2012 at 11:25:08PM +0800, Simon Glass wrote:
> > +   /* Use a ref-to-sync of 1 always, and take this from the front
> > porch */
> 
> ref-to-sync is supposed to be 1 here.
> 
> > +   back = fdtdec_get_int(blob, rgb, "left-margin", -1);
> > +   front = fdtdec_get_int(blob, rgb, "right-margin", -1);
> > +   ref = fdtdec_get_int(blob, rgb, "hsync-len", -1);
> > +   if ((back | front | ref) == -1) {
> > +   debug("%s: Horizontal parameters missing\n", __func__);
> > +   return -FDT_ERR_NOTFOUND;
> > +   }
> > +   config->horiz_timing[FDT_LCD_TIMING_REF_TO_SYNC] = 11;
> 
> It is assigned to 11.

when replying, please delete anything you aren't quoting.  in this case, there 
was over 1000 lines of content that was just noise.  it makes it hard to see 
what your responses are if you don't clip.
-mike


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Re: [U-Boot] [PATCH v4 1/1] zfs: Add ZFS filesystem support

[Mike Frysinger]

On Thursday 19 July 2012 00:51:23 Jorgen Lundman wrote:
> Mike Frysinger wrote:
> > i just picked out the first "version 3" i saw in your patch.  going back
> > to it and searching again shows more than just one file.
> 
> You are correct, 3 files to be precise:
> 
> zfs_fletcher.c zfs_lzjb.c zfs_sha256.c
> 
> but the other two are functionally not changed.
> 
> Syntactically, they have gone through a "unsigned char *" to "grub_uint8_t
> *" to "uint8_t *".

that's fine

> Not entirely sure how I would "re-write" my "uint8_t *" change to be more
> clearly from "unsigned char *", as opposed to "grub_uint_8 *", to show it
> is based on the version 2 of the license.

post a new patchset with the correct version, and detail these things 
justifying the content/license shifts
-mike


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Re: [U-Boot] [PATCH] arm: armv7: add compile option -mno-unaligned-access if available

[Mike Frysinger]

On Thursday 19 July 2012 02:28:05 Albert ARIBAUD wrote:
> On Thu, 19 Jul 2012 00:29:23 -0400, Mike Frysinger wrote:
> > On Monday 02 July 2012 12:14:40 Måns Rullgård wrote:
> > > It's slightly more complicated than that.  Data can be misaligned for a
> > > variety of reasons:
> > > 
> > > 1. Errors in software.
> > > 2. Specified by a file format or communication protocol.
> > > 3. Deliberately misaligned by the compiler.
> > > 
> > > Misaligned data of type 1 should of course be fixed properly, not
> > > worked around in any way.
> > 
> > it's also a reliability aspect.  people don't write bug free software,
> > not bug free protocols, nor bug free compilers.  when misalignment does
> > happen in the field, it's a hell of a lot better if the software
> > continued to execute correctly rather than randomly triggered an
> > exception.
> 
> Nitpick: this is robustness, not reliability.

useless pedantry: by increasing robustness, the system is more reliable

> That being said, yes, this robustness is desirable when you do not control
> all of the SW running on the product; Linux, for instance, will have to
> execute processes which were built with any old (or new) compiler
> settings, thus the Linux folks have to make sure the kernel won't fail
> running those.
> 
> But the only uncontrolled SW U-Boot runs is its payload -- typically the
> kernel image -- which are usually very cautious in what they assume they
> can do, thus are unlikely to perform unaligned accesses.

it isn't just that.  there is no way you can guarantee both the linux kernel 
and u-boot code bases themselves are perfect.  in fact, it's even worse when 
these are the ones that get tripped up because it means your system 
resets/hardlocks/kills a kitten.  when doing driver development under the 
linux kernel, we would come across parts of core stacks that lacked alignment 
checking and would panic the system.  sometimes it would always panic, other 
times it depended on factors that made life worse: the compiler version (newer 
ones always like to pack/optimize better), the actual data stream, or the 
execution paths.

> > simply search the kernel for get_unaligned then.  there are plenty of
> > examples in there.  granted, many apply to stacks that don't show up in
> > u-boot (yet?) such as bluetooth, wireless, and irda, but i'm pretty sure
> > TCP/IPv4 has a few edge cases too.
> 
> I'll have a look, if only to lament that protocol are not what they used to
> be in the old days. :)
> 
> Anyway: as I said: performing *controlled* unaligned accesses for external
> reasons other than bugs is fine with me. Having our own get_unaligned() in
> such places would be fine with me.

i have no problem adding put/get_unaligned() to all the right places.  that 
makes perfect sense.  but, as an orthogonal issue wrt ARMv7, i don't see any 
problem enabling hardware functionality: it increases robustness (:P), shrinks 
the code base (all the get/put unaligned macros expand into a single memory 
access as they no longer have to do alignment fixups in software), and speeds 
up the runtime (a single unaligned memory access is always faster than address 
masking/multiple loads/bit shifting/etc... -- obviously this ignores 
multimedia type code that does alignment adjustment at the start, then lets of 
memory accesses, then another adjustment at the end, but that's not what we're 
talking about here).

if you want to tell people that if they found an unaligned access in code they 
must fix that, then great.  make them fix it.  then once that bug has been 
fixed, 
let's merge the purely optimization patch that allows the hardware to do 
unaligned accesses.
-mike


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Re: [U-Boot] [PATCH v4 1/2] tools, config.mk: add binutils-version

[Tom Rini]

-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1

On 07/18/2012 08:11 PM, Mike Frysinger wrote:
> On Wednesday 18 July 2012 19:45:52 Allen Martin wrote:
>> +MAJOR=$($gas --version | head -1 | awk '{print $NF}' | cut -d . 
>> -f 1) +MINOR=$($gas --version | head -1 | awk '{print $NF}' |
>> cut -d . -f 2) + +printf "%02d%02d\\n" $MAJOR $MINOR
> 
> can be replaced with a single awk script:
> 
> $gas --version | awk '{ gsub(/[.]/, " ", $NF) $0 = $NF printf 
> "%02d%02d\n", $1, $2 exit }'

That looks much longer and we call this once so a few execs is noise.

- -- 
Tom

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Re: [U-Boot] [PATCH v4 2/2] arm: work around assembler bug

[Tom Rini]

On 07/18/2012 11:06 PM, Albert ARIBAUD wrote:
> Hi Allen,
> 
> On Wed, 18 Jul 2012 16:45:53 -0700, Allen Martin  wrote:
>> Disable sibling call optimization based on binutils version.  This is
>> to work around a bug in the assember in binutils versions < 2.22.
>> Branches to weak symbols can be incorrectly optimized in thumb mode to
>> a short branch (b.n instruction) that won't reach when the symbol gets
>> preempted.
>>
>> http://sourceware.org/bugzilla/show_bug.cgi?id=12532
>>
>> Signed-off-by: Allen Martin 
>> ---
>> changes for v4:
>>  -removed warning print
>> changes for v3:
>>  -split shell line to improve readability
>> changes for v2:
>>  -changed GAS_BUG_12532 from yes/no to y/n to be consistent
>>  -added additional warning about code size increase
>> ---
>>  arch/arm/config.mk |   18 ++
>>  1 file changed, 18 insertions(+)
>>
>> diff --git a/arch/arm/config.mk b/arch/arm/config.mk
>> index 3f4453a..24b9d7c 100644
>> --- a/arch/arm/config.mk
>> +++ b/arch/arm/config.mk
>> @@ -87,3 +87,21 @@ endif
>>  ifndef CONFIG_NAND_SPL
>>  LDFLAGS_u-boot += -pie
>>  endif
>> +
>> +#
>> +# FIXME: binutils versions < 2.22 have a bug in the assembler where
>> +# branches to weak symbols can be incorrectly optimized in thumb mode
>> +# to a short branch (b.n instruction) that won't reach when the symbol
>> +# gets preempted
>> +#
>> +# http://sourceware.org/bugzilla/show_bug.cgi?id=12532
>> +#
>> +ifeq ($(CONFIG_SYS_THUMB_BUILD),y)
>> +ifeq ($(GAS_BUG_12532),)
>> +export GAS_BUG_12532:=$(shell if [ $(call binutils-version) -lt 0222 ] ; \
>> +then echo y; else echo n; fi)
>> +endif
>> +ifeq ($(GAS_BUG_12532),y)
>> +PLATFORM_RELFLAGS += -fno-optimize-sibling-calls
>> +endif
>> +endif
> 
> Can previous reviewers ack or test this? I would like to have it in the ARM
> master branch in time for 12.07.

Acked-by: Tom Rini 

-- 
Tom
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[U-Boot] [PATCH v2] kirkwood: add support for Iomega iConnect board

[Luka Perkov]

Add support for new board iConnect from Iomega.

More information about the device can be found here:

http://go.iomega.com/en/products/network-storage-desktop/wireless-data-station/network-hard-drive-iconnect/?partner=4735

Signed-off-by: Luka Perkov 
Tested-by: Wojciech Dubowik 
Tested-by: Tim Fletcher 
---

Changes from v1:

 * remove #ifdef CONFIG_CMD_IDE part from include/configs/iconnect.h
   (board does not have IDE ports)
 * add compression defines in include/configs/iconnect.h

 MAINTAINERS|1 +
 board/iomega/iconnect/Makefile |   43 ++
 board/iomega/iconnect/iconnect.c   |  107 +++
 board/iomega/iconnect/iconnect.h   |   39 +
 board/iomega/iconnect/kwbimage.cfg |  165 
 boards.cfg |1 +
 include/configs/iconnect.h |  129 
 7 files changed, 485 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index fd0c65c..9e9d8d7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -787,6 +787,7 @@ Linus Walleij 
 Luka Perkov 
 
ib62x0  ARM926EJS
+   iconnectARM926EJS
 
 Dave Peverley 
 
diff --git a/board/iomega/iconnect/Makefile b/board/iomega/iconnect/Makefile
new file mode 100644
index 000..f77fcfb
--- /dev/null
+++ b/board/iomega/iconnect/Makefile
@@ -0,0 +1,43 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor 
+# Written-by: Prafulla Wadaskar 
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see .
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).o
+
+COBJS  := iconnect.o
+
+SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
+SOBJS  := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):$(obj).depend $(OBJS) $(SOBJS)
+   $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/iomega/iconnect/iconnect.c b/board/iomega/iconnect/iconnect.c
new file mode 100644
index 000..6ee3b84
--- /dev/null
+++ b/board/iomega/iconnect/iconnect.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright (C) 2009-2012
+ * Wojciech Dubowik 
+ * Luka Perkov 
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "iconnect.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+   /*
+* default gpio configuration
+* There are maximum 64 gpios controlled through 2 sets of registers
+* the below configuration configures mainly initial LED status
+*/
+   kw_config_gpio(ICONNECT_OE_VAL_LOW,
+   ICONNECT_OE_VAL_HIGH,
+   ICONNECT_OE_LOW, ICONNECT_OE_HIGH);
+
+   /* Multi-Purpose Pins Functionality configuration */
+   u32 kwmpp_config[] = {
+   MPP0_NF_IO2,
+   MPP1_NF_IO3,
+   MPP2_NF_IO4,
+   MPP3_NF_IO5,
+   MPP4_NF_IO6,
+   MPP5_NF_IO7,
+   MPP6_SYSRST_OUTn,
+   MPP7_GPO,
+   MPP8_TW_SDA,
+   MPP9_TW_SCK,
+   MPP10_UART0_TXD,
+   MPP11_UART0_RXD,
+   MPP12_GPO,
+   MPP13_SD_CMD,
+   MPP14_SD_D0,
+   MPP15_SD_D1,
+   MPP16_SD_D2,
+   MPP17_SD_D3,
+   MPP18_NF_IO0,
+   MPP19_NF_IO1,
+   MPP20_GE1_0,
+   MPP21_GE

[U-Boot] cross compile suceeds but not usable

[kqt4at5v]

I downloaded the latest u-boot snapshot on 20120717, installed Sourcery 
CodeBench, set the CROSS_COMPILE variable, and compiled. There 
were no errors. When I try to load with kwboot it fails. If I build the 
same u-boot source on the target, Guruplug, with Debian Wheezy installed I 
get a usable u-boot.kwb.



[rray@grumpy2 u-boot_new_for_guruplug]$ arm-none-linux-gnueabi-gcc -v
Using built-in specs.
COLLECT_GCC=arm-none-linux-gnueabi-gcc
COLLECT_LTO_WRAPPER=/backup_2/work/arm/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_GNU_Linux/bin/../libexec/gcc/arm-none-linux-gnueabi/4.6.3/lto-wrapper
Target: arm-none-linux-gnueabi
Configured with: /scratch/nsidwell/arm/linux/src/gcc-4.6-2012.03/configure 
--build=i686-pc-linux-gnu --host=i686-pc-linux-gnu 
--target=arm-none-linux-gnueabi --enable-threads --disable-libmudflap 
--disable-libssp --disable-libstdcxx-pch --enable-extra-sgxxlite-multilibs 
--with-arch=armv5te --with-gnu-as --with-gnu-ld 
--with-specs='%{save-temps: -fverbose-asm} 
%{funwind-tables|fno-unwind-tables|mabi=*|ffreestanding|nostdlib:;:-funwind-tables} 
-D__CS_SOURCERYGXX_MAJ__=2012 -D__CS_SOURCERYGXX_MIN__=3 
-D__CS_SOURCERYGXX_REV__=57 %{O2:%{!fno-remove-local-statics: 
-fremove-local-statics}} 
%{O*:%{O|O0|O1|O2|Os:;:%{!fno-remove-local-statics: 
-fremove-local-statics}}}' --enable-languages=c,c++ --enable-shared 
--enable-lto --enable-symvers=gnu --enable-__cxa_atexit 
--with-pkgversion='Sourcery CodeBench Lite 2012.03-57' 
--with-bugurl=https://support.codesourcery.com/GNUToolchain/ --disable-nls 
--prefix=/opt/codesourcery 
--with-sysroot=/opt/codesourcery/arm-none-linux-gnueabi/libc 
--with-build-sysroot=/scratch/nsidwell/arm/linux/install/arm-none-linux-gnueabi/libc 
--with-gmp=/scratch/nsidwell/arm/linux/obj/host-libs-2012.03-57-arm-none-linux-gnueabi-i686-pc-linux-gnu/usr 
--with-mpfr=/scratch/nsidwell/arm/linux/obj/host-libs-2012.03-57-arm-none-linux-gnueabi-i686-pc-linux-gnu/usr 
--with-mpc=/scratch/nsidwell/arm/linux/obj/host-libs-2012.03-57-arm-none-linux-gnueabi-i686-pc-linux-gnu/usr 
--with-ppl=/scratch/nsidwell/arm/linux/obj/host-libs-2012.03-57-arm-none-linux-gnueabi-i686-pc-linux-gnu/usr 
--with-host-libstdcxx='-static-libgcc -Wl,-Bstatic,-lstdc++,-Bdynamic -lm' 
--with-cloog=/scratch/nsidwell/arm/linux/obj/host-libs-2012.03-57-arm-none-linux-gnueabi-i686-pc-linux-gnu/usr 
--with-libelf=/scratch/nsidwell/arm/linux/obj/host-libs-2012.03-57-arm-none-linux-gnueabi-i686-pc-linux-gnu/usr 
--disable-libgomp --enable-poison-system-directories 
--with-build-time-tools=/scratch/nsidwell/arm/linux/install/arm-none-linux-gnueabi/bin 
--with-build-time-tools=/scratch/nsidwell/arm/linux/install/arm-none-linux-gnueabi/bin

Thread model: posix
gcc version 4.6.3 (Sourcery CodeBench Lite 2012.03-57)


[rray@grumpy2 u-boot_new_for_guruplug]$ CROSS_COMPILE=arm-none-linux-gnueabi-
[rray@grumpy2 u-boot_new_for_guruplug]$ export CROSS_COMPILE
[rray@grumpy2 u-boot_new_for_guruplug]$ make mrproper
[rray@grumpy2 u-boot_new_for_guruplug]$ make guruplug_config
Configuring for guruplug board...
[rray@grumpy2 u-boot_new_for_guruplug]$ make u-boot.kwb
Generating include/autoconf.mk
Generating include/autoconf.mk.dep
arm-none-linux-gnueabi-gcc -DDO_DEPS_ONLY \
-g  -Os   -fno-common -ffixed-r8 -msoft-float  -D__KERNEL__ 
-DCONFIG_SYS_TEXT_BASE=0x0060 
-I/backup_2/u-boot_new_for_guruplug/include -fno-builtin -ffreestanding 
-nostdinc -isystem 
/backup_2/work/arm/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_GNU_Linux/bin/../lib/gcc/arm-none-linux-gnueabi/4.6.3/include 
-pipe  -DCONFIG_ARM -D__ARM__ -marm -mno-thumb-interwork -mabi=aapcs-linux 
-march=armv5te -Wall -Wstrict-prototypes -fno-stack-protector 
-Wno-format-nonliteral -Wno-format-security -fstack-usage   \

-o lib/asm-offsets.s lib/asm-offsets.c -c -S
Generating include/generated/generic-asm-offsets.h
tools/scripts/make-asm-offsets lib/asm-offsets.s 
include/generated/generic-asm-offsets.h

if [ -f arch/arm/cpu/arm926ejs/kirkwood/asm-offsets.c ];then \
arm-none-linux-gnueabi-gcc -DDO_DEPS_ONLY \
-g  -Os   -fno-common -ffixed-r8 -msoft-float  -D__KERNEL__ 
-DCONFIG_SYS_TEXT_BASE=0x0060 
-I/backup_2/u-boot_new_for_guruplug/include -fno-builtin -ffreestanding 
-nostdinc -isystem 
/backup_2/work/arm/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_GNU_Linux/bin/../lib/gcc/arm-none-linux-gnueabi/4.6.3/include 
-pipe  -DCONFIG_ARM -D__ARM__ -marm -mno-thumb-interwork -mabi=aapcs-linux 
-march=armv5te -Wall -Wstrict-prototypes -fno-stack-protector 
-Wno-format-nonliteral -Wno-format-security -fstack-usage   \
  -o arch/arm/cpu/arm926ejs/kirkwood/asm-offsets.s 
arch/arm/cpu/arm926ejs/kirkwood/asm-offsets.c -c -S; \

  else \
touch arch/arm/cpu/arm926ejs/kirkwood/asm-offsets.s; \
  fi
Generating include/generated/asm-offsets.h
tools/scripts/make-asm-offsets 
arch/arm/cpu/arm926ejs/kirkwood/asm-offsets.s 
include/generated/asm-offsets.h
for dir in tools examples/standalone examples/api arch/arm/cpu/arm926ejs 
; do \

  make -C

Re: [U-Boot] [PATCH v4 1/2] tools, config.mk: add binutils-version

[Mike Frysinger]

On Thursday 19 July 2012 11:08:10 Tom Rini wrote:
> On 07/18/2012 08:11 PM, Mike Frysinger wrote:
> > On Wednesday 18 July 2012 19:45:52 Allen Martin wrote:
> >> +MAJOR=$($gas --version | head -1 | awk '{print $NF}' | cut -d . -f 1)
> >> +MINOR=$($gas --version | head -1 | awk '{print $NF}' | cut -d . -f 2)
> >> +
> >> +printf "%02d%02d\\n" $MAJOR $MINOR
> > 
> > can be replaced with a single awk script:
> > 
> > $gas --version | awk '{ gsub(/[.]/, " ", $NF) $0 = $NF printf
> > "%02d%02d\n", $1, $2 exit }'
> 
> That looks much longer and we call this once so a few execs is noise.

here's a shorter version:
$gas --version | awk '{ gsub(/[.]/, " ", $NF); $0 = $NF; printf "%02d%02d\n", 
$1, $2; exit }'
-mike


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Re: [U-Boot] [PATCH u-boot-arm/next v2 2/2] OMAP3: igep00x0: add SPL support for IGEP-based boards

[Enric Balletbò i Serra]

2012/7/19 Javier Martinez Canillas :
> This patch adds SPL support for IGEP-based boards.
>
> Tested on an IGEPv2 Rev.C board with Micron NAND Flash memory.
>
> Signed-off-by: Javier Martinez Canillas 
> ---
>
> Changes since v1:
>
> - Set NAND memory 200 Mhz timings when possible as suggested by Thomas 
> Petazzoni
>
>  board/isee/igep0020/config.mk  |   33 
>  board/isee/igep0020/igep0020.c |   42 +-
>  board/isee/igep0030/config.mk  |   33 
>  board/isee/igep0030/igep0030.c |   42 +-
>  include/configs/igep00x0.h |   65 
> 
>  5 files changed, 147 insertions(+), 68 deletions(-)
>  delete mode 100644 board/isee/igep0020/config.mk
>  delete mode 100644 board/isee/igep0030/config.mk
>
> diff --git a/board/isee/igep0020/config.mk b/board/isee/igep0020/config.mk
> deleted file mode 100644
> index 7964621..000
> --- a/board/isee/igep0020/config.mk
> +++ /dev/null
> @@ -1,33 +0,0 @@
> -#
> -# (C) Copyright 2009
> -# ISEE 2007 SL, 
> -#
> -# IGEP0020 uses OMAP3 (ARM-CortexA8) cpu
> -# see http://www.ti.com/ for more information on Texas Instruments
> -#
> -# See file CREDITS for list of people who contributed to this
> -# project.
> -#
> -# This program is free software; you can redistribute it and/or
> -# modify it under the terms of the GNU General Public License as
> -# published by the Free Software Foundation; either version 2 of
> -# the License, or (at your option) any later version.
> -#
> -# This program is distributed in the hope that it will be useful,
> -# but WITHOUT ANY WARRANTY; without even the implied warranty of
> -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> -# GNU General Public License for more details.
> -#
> -# You should have received a copy of the GNU General Public License
> -# along with this program; if not, write to the Free Software
> -# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> -# MA 02111-1307 USA
> -#
> -# Physical Address:
> -# 8000' (bank0)
> -# A000/ (bank1)
> -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
> -# (mem base + reserved)
> -
> -# For use with external or internal boots.
> -CONFIG_SYS_TEXT_BASE = 0x80008000
> diff --git a/board/isee/igep0020/igep0020.c b/board/isee/igep0020/igep0020.c
> index 971e31b..a4d099a 100644
> --- a/board/isee/igep0020/igep0020.c
> +++ b/board/isee/igep0020/igep0020.c
> @@ -58,6 +58,46 @@ int board_init(void)
> return 0;
>  }
>
> +#ifdef CONFIG_SPL_BUILD
> +/*
> + * Routine: omap_rev_string
> + * Description: For SPL builds output board rev
> + */
> +void omap_rev_string(void)
> +{
> +}
> +
> +/*
> + * Routine: get_board_mem_timings
> + * Description: If we use SPL then there is no x-loader nor config header
> + * so we have to setup the DDR timings ourself on both banks.
> + */
> +void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
> +   u32 *mr)
> +{
> +   *mr = MICRON_V_MR_165;
> +#ifdef CONFIG_BOOT_NAND
> +   *mcfg = MICRON_V_MCFG_200(512 << 20);
> +   *ctrla = MICRON_V_ACTIMA_200;
> +   *ctrlb = MICRON_V_ACTIMB_200;
> +   *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
> +#else
> +   if (get_cpu_family() == CPU_OMAP34XX) {
> +   *mcfg = NUMONYX_V_MCFG_165(512 << 20);
> +   *ctrla = NUMONYX_V_ACTIMA_165;
> +   *ctrlb = NUMONYX_V_ACTIMB_165;
> +   *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
> +
> +   } else {
> +   *mcfg = NUMONYX_V_MCFG_200(512 << 20);
> +   *ctrla = NUMONYX_V_ACTIMA_200;
> +   *ctrlb = NUMONYX_V_ACTIMB_200;
> +   *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
> +   }
> +#endif
> +}
> +#endif
> +
>  /*
>   * Routine: setup_net_chip
>   * Description: Setting up the configuration GPMC registers specific to the
> @@ -91,7 +131,7 @@ static void setup_net_chip(void)
>  }
>  #endif
>
> -#ifdef CONFIG_GENERIC_MMC
> +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
>  int board_mmc_init(bd_t *bis)
>  {
> omap_mmc_init(0, 0, 0);
> diff --git a/board/isee/igep0030/config.mk b/board/isee/igep0030/config.mk
> deleted file mode 100644
> index 059a878..000
> --- a/board/isee/igep0030/config.mk
> +++ /dev/null
> @@ -1,33 +0,0 @@
> -#
> -# (C) Copyright 2009
> -# ISEE 2007 SL, 
> -#
> -# IGEP0030 uses OMAP3 (ARM-CortexA8) cpu
> -# see http://www.ti.com/ for more information on Texas Instruments
> -#
> -# See file CREDITS for list of people who contributed to this
> -# project.
> -#
> -# This program is free software; you can redistribute it and/or
> -# modify it under the terms of the GNU General Public License as
> -# published by the Free Software Foundation; either version 2 of
> -# the License, or (at your option) any later version.
> -#
> -# This program is distributed in the hope that it will be useful,
> -# but WITHOUT ANY WARRANTY; without even the i

Re: [U-Boot] [PATCH v7 00/15] split tegra20 arm7 code into separate SPL

[Tom Warren]

Allen,

> -Original Message-
> From: Allen Martin [mailto:amar...@nvidia.com]
> Sent: Wednesday, July 18, 2012 5:02 PM
> To: Tom Warren
> Cc: swar...@wwwdotorg.org; s...@chromium.org; thierry.reding@avionic-
> design.de; u-boot@lists.denx.de
> Subject: Re: [PATCH v7 00/15] split tegra20 arm7 code into separate SPL
> 
> On Tue, Jul 17, 2012 at 12:32:53PM -0700, Tom Warren wrote:
> > Allen,
> >
> > > -Original Message-
> > > From: Allen Martin [mailto:amar...@nvidia.com]
> > > Sent: Monday, July 16, 2012 4:02 PM
> > > To: Tom Warren; swar...@wwwdotorg.org; s...@chromium.org;
> > > thierry.red...@avionic-design.de
> > > Cc: u-boot@lists.denx.de; Allen Martin
> > > Subject: [PATCH v7 00/15] split tegra20 arm7 code into separate SPL
> > >
> > > This patch series fixes a long standing problem with the tegra20
> > > u-boot build.  Tegra20 contains an ARM7TDMI boot processor and a
> > > Cortex A9 main processor.  Prior to this patch series this was
> > > accomplished by #ifdefing out any armv7 code from the early boot
> > > sequence and creating a single binary that runs on both both the
> > > ARM7TDMI and A9.  This was very fragile as changes to compiler
> > > options or any additions or rearranging of the early boot code could
> > > add additional armv7 specific code causing it to fail on the ARM7TDMI.
> > >
> > > This patch series pulls all the armv4t code out into a separate SPL
> > > that does nothing more than initialize the A9 and transfer control
> > > to it.  The resultint SPL and armv7 u-boot are concatenated together
> > > into a single image.
> > >
> > > This patch series is also available from:
> > > git://github.com/arm000/u-boot.git
> > > branch: tegra-spl-v7
> > >
> >
> > Applied to u-boot-tegra/next AOK, tested on my Seaboard AOK, so:
> > Tested-by: Tom Warren 
> >
> > Note that I was confused by the final binary name (u-boot-dtb-tegra.bin),
> since I'm used to flashing u-boot-dtb.bin.
> >
> > We need to come to a consensus about the final binary name for Tegra U-
> Boot (I'd thought we had, and that it would be u-boot-dtb.bin, since that's
> what most devs are used to looking for in Tegra builds).
> >
> 
> Yeah, I'd like some stability there too.  The -dtb rule is not tegra
> specific, which is why I didn't want to modify or remove it.  I think we're
> the only one that uses it though, so maybe it's not so bad.
> 
> > Also, one nit: I see the 2 sign-on strings (U-Boot SPL 2012.04.xxx, and
> then U-Boot 2012.04.xxx), separated by 2 lines. I think it'd look better if
> you had them one right after the other, i.e. eliminate the extra linefeeds.
> >
> 
> The extra lines come from display_banner() which is ARM generic from the
> main u-boot.  I assume they are there to separate the banner from any junk
> that was on your screen before you rebooted, so it would make sense to move
> them to the SPL banner instead if you have SPL enabled.
> I'll make a separate patch for that in a week after I get back from
> vacation.
> 
> -Allen

Cool, thanks. Until then:

Tegra2 SPL patches have been applied to u-boot-tegra/next & pushed to Denx. I'm 
going to hold off putting it into tegra/master and generating a pull request 
for awhile to allow all Tegra devs to test it, comment, etc., since it's a 
major change to the Tegra build.

If possible, please post any new Tegra changes against tegra/next (i.e. using 
Allen's SPL file locations).

Thanks,

Tom
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Re: [U-Boot] [PATCH v4 1/2] tools, config.mk: add binutils-version

[Tom Rini]

-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1

On 07/19/2012 08:21 AM, Mike Frysinger wrote:
> On Thursday 19 July 2012 11:08:10 Tom Rini wrote:
>> On 07/18/2012 08:11 PM, Mike Frysinger wrote:
>>> On Wednesday 18 July 2012 19:45:52 Allen Martin wrote:
 +MAJOR=$($gas --version | head -1 | awk '{print $NF}' | cut
 -d . -f 1) +MINOR=$($gas --version | head -1 | awk '{print
 $NF}' | cut -d . -f 2) + +printf "%02d%02d\\n" $MAJOR $MINOR
>>> 
>>> can be replaced with a single awk script:
>>> 
>>> $gas --version | awk '{ gsub(/[.]/, " ", $NF) $0 = $NF printf 
>>> "%02d%02d\n", $1, $2 exit }'
>> 
>> That looks much longer and we call this once so a few execs is
>> noise.
> 
> here's a shorter version: $gas --version | awk '{ gsub(/[.]/, " ",
> $NF); $0 = $NF; printf "%02d%02d\n", $1, $2; exit }'

And still over 80 chars before we assign it to a variable.  I could
get it to 77 chars with all whitespace removed.

- -- 
Tom


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Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/

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Re: [U-Boot] [PATCH] video: cfb_console: flush dcache for frame buffer in DRAM

[Marek Vasut]

Dear Mike Frysinger,

> On Tuesday 05 June 2012 03:28:40 Anatolij Gustschin wrote:
> > On Sat, 28 Apr 2012 17:04:07 +0200 Anatolij Gustschin wrote:
> > > Data cache flushing is required for frame buffer in RAM to fix the
> > > distorted console text output. Currently this text distortion is
> > > observed with cfb on beageboard and N900 when running with data
> > > cache enabled.
> > 
> > Applied to u-boot-video/master after rebasing and fixing commit log.
> 
> this patch is still wrong for the reasons i cited earlier.  your cache
> functions are broken, not the driver.

The cache stuff is completely borked on ARM, I have no idea why people enable 
it.

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH u-boot-arm/next v2 2/2] OMAP3: igep00x0: add SPL support for IGEP-based boards

[Javier Martinez Canillas]

On Thu, Jul 19, 2012 at 5:26 PM, Enric Balletbò i Serra
 wrote:
> 2012/7/19 Javier Martinez Canillas :
>> This patch adds SPL support for IGEP-based boards.
>>
>> Tested on an IGEPv2 Rev.C board with Micron NAND Flash memory.
>>
>> Signed-off-by: Javier Martinez Canillas 
>> ---
>>
>> Changes since v1:
>>
>> - Set NAND memory 200 Mhz timings when possible as suggested by Thomas 
>> Petazzoni
>>
>>  board/isee/igep0020/config.mk  |   33 
>>  board/isee/igep0020/igep0020.c |   42 +-
>>  board/isee/igep0030/config.mk  |   33 
>>  board/isee/igep0030/igep0030.c |   42 +-
>>  include/configs/igep00x0.h |   65 
>> 
>>  5 files changed, 147 insertions(+), 68 deletions(-)
>>  delete mode 100644 board/isee/igep0020/config.mk
>>  delete mode 100644 board/isee/igep0030/config.mk
>>
>> diff --git a/board/isee/igep0020/config.mk b/board/isee/igep0020/config.mk
>> deleted file mode 100644
>> index 7964621..000
>> --- a/board/isee/igep0020/config.mk
>> +++ /dev/null
>> @@ -1,33 +0,0 @@
>> -#
>> -# (C) Copyright 2009
>> -# ISEE 2007 SL, 
>> -#
>> -# IGEP0020 uses OMAP3 (ARM-CortexA8) cpu
>> -# see http://www.ti.com/ for more information on Texas Instruments
>> -#
>> -# See file CREDITS for list of people who contributed to this
>> -# project.
>> -#
>> -# This program is free software; you can redistribute it and/or
>> -# modify it under the terms of the GNU General Public License as
>> -# published by the Free Software Foundation; either version 2 of
>> -# the License, or (at your option) any later version.
>> -#
>> -# This program is distributed in the hope that it will be useful,
>> -# but WITHOUT ANY WARRANTY; without even the implied warranty of
>> -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> -# GNU General Public License for more details.
>> -#
>> -# You should have received a copy of the GNU General Public License
>> -# along with this program; if not, write to the Free Software
>> -# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>> -# MA 02111-1307 USA
>> -#
>> -# Physical Address:
>> -# 8000' (bank0)
>> -# A000/ (bank1)
>> -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
>> -# (mem base + reserved)
>> -
>> -# For use with external or internal boots.
>> -CONFIG_SYS_TEXT_BASE = 0x80008000
>> diff --git a/board/isee/igep0020/igep0020.c b/board/isee/igep0020/igep0020.c
>> index 971e31b..a4d099a 100644
>> --- a/board/isee/igep0020/igep0020.c
>> +++ b/board/isee/igep0020/igep0020.c
>> @@ -58,6 +58,46 @@ int board_init(void)
>> return 0;
>>  }
>>
>> +#ifdef CONFIG_SPL_BUILD
>> +/*
>> + * Routine: omap_rev_string
>> + * Description: For SPL builds output board rev
>> + */
>> +void omap_rev_string(void)
>> +{
>> +}
>> +
>> +/*
>> + * Routine: get_board_mem_timings
>> + * Description: If we use SPL then there is no x-loader nor config header
>> + * so we have to setup the DDR timings ourself on both banks.
>> + */
>> +void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
>> +   u32 *mr)
>> +{
>> +   *mr = MICRON_V_MR_165;
>> +#ifdef CONFIG_BOOT_NAND
>> +   *mcfg = MICRON_V_MCFG_200(512 << 20);
>> +   *ctrla = MICRON_V_ACTIMA_200;
>> +   *ctrlb = MICRON_V_ACTIMB_200;
>> +   *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
>> +#else
>> +   if (get_cpu_family() == CPU_OMAP34XX) {
>> +   *mcfg = NUMONYX_V_MCFG_165(512 << 20);
>> +   *ctrla = NUMONYX_V_ACTIMA_165;
>> +   *ctrlb = NUMONYX_V_ACTIMB_165;
>> +   *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
>> +
>> +   } else {
>> +   *mcfg = NUMONYX_V_MCFG_200(512 << 20);
>> +   *ctrla = NUMONYX_V_ACTIMA_200;
>> +   *ctrlb = NUMONYX_V_ACTIMB_200;
>> +   *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
>> +   }
>> +#endif
>> +}
>> +#endif
>> +
>>  /*
>>   * Routine: setup_net_chip
>>   * Description: Setting up the configuration GPMC registers specific to the
>> @@ -91,7 +131,7 @@ static void setup_net_chip(void)
>>  }
>>  #endif
>>
>> -#ifdef CONFIG_GENERIC_MMC
>> +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
>>  int board_mmc_init(bd_t *bis)
>>  {
>> omap_mmc_init(0, 0, 0);
>> diff --git a/board/isee/igep0030/config.mk b/board/isee/igep0030/config.mk
>> deleted file mode 100644
>> index 059a878..000
>> --- a/board/isee/igep0030/config.mk
>> +++ /dev/null
>> @@ -1,33 +0,0 @@
>> -#
>> -# (C) Copyright 2009
>> -# ISEE 2007 SL, 
>> -#
>> -# IGEP0030 uses OMAP3 (ARM-CortexA8) cpu
>> -# see http://www.ti.com/ for more information on Texas Instruments
>> -#
>> -# See file CREDITS for list of people who contributed to this
>> -# project.
>> -#
>> -# This program is free software; you can redistribute it and/or
>> -# modify it under the terms of the GNU General Public License as
>> -# published by the Free Software Founda

Re: [U-Boot] [PATCH 3/3] Makefile: cosmetic: optimize usage of LIBS-y

[Daniel Schwierzeck]

Hi Mike,

2012/7/19 Mike Frysinger :
> On Thursday 28 June 2012 12:45:21 Daniel Schwierzeck wrote:
>> --- a/Makefile
>> +++ b/Makefile
>>
>> +HAVE_VENDOR_COMMON_LIB := $(shell [ -f board/$(VENDOR)/common/Makefile ] \
>> + && echo y || echo n)
>
> HAVE_VENDOR_COMMON_LIB = $(if $(wildcard board/$(VENDOR)/common/Makefile),y,n)
> -mike

yes, that's better.
I'll also cook a patch for spl/Makefile that already has this piece of code.

Thanks,
Daniel
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[U-Boot] [PATCH u-boot-arm/next v3 2/2] OMAP3: igep00x0: add SPL support for IGEP-based boards

[Javier Martinez Canillas]

This patch adds SPL support for IGEP-based boards.

Tested on an IGEPv2 Rev.C board with Micron NAND Flash memory.

Signed-off-by: Javier Martinez Canillas 
---

Changes since v1:
 - Set NAND memory 200 Mhz timings when possible as suggested by Thomas 
Petazzoni

Changes since v2:
 - Add Numonyx 200MHz timings as suggested by Enric Balletbo i Serra

 arch/arm/include/asm/arch-omap3/mem.h |   29 +++
 board/isee/igep0020/config.mk |   33 -
 board/isee/igep0020/igep0020.c|   42 +-
 board/isee/igep0030/config.mk |   33 -
 board/isee/igep0030/igep0030.c|   42 +-
 include/configs/igep00x0.h|   65 +
 6 files changed, 176 insertions(+), 68 deletions(-)
 delete mode 100644 board/isee/igep0020/config.mk
 delete mode 100644 board/isee/igep0030/config.mk

diff --git a/arch/arm/include/asm/arch-omap3/mem.h 
b/arch/arm/include/asm/arch-omap3/mem.h
index 9f6992a..12dcf4e 100644
--- a/arch/arm/include/asm/arch-omap3/mem.h
+++ b/arch/arm/include/asm/arch-omap3/mem.h
@@ -294,6 +294,35 @@ enum {
 #define NUMONYX_RASWIDTH_165   15
 #define NUMONYX_V_MCFG_165(size)   MCFG((size), NUMONYX_RASWIDTH_165)
 
+/* NUMONYX part of IGEP v2 (200MHz optimized) 5 ns */
+#define NUMONYX_TDAL_200   6   /* Twr/Tck + Trp/tck*/
+   /* 15/5 + 15/5 = 3 + 3 -> 6 */
+#define NUMONYX_TDPL_200   3   /* 15/5 = 3 -> 3 (Twr)  */
+#define NUMONYX_TRRD_200   2   /* 10/5 = 2 */
+#define NUMONYX_TRCD_200   4   /* 16.2/5 = 3.24 -> 4   */
+#define NUMONYX_TRP_2003   /* 15/5 = 3 
*/
+#define NUMONYX_TRAS_200   8   /* 40/5 = 8 */
+#define NUMONYX_TRC_20011  /* 55/5 = 11
*/
+#define NUMONYX_TRFC_20028  /* 140/5 = 28   */
+
+#define NUMONYX_V_ACTIMA_200   \
+   ACTIM_CTRLA(NUMONYX_TRFC_200, NUMONYX_TRC_200,  \
+   NUMONYX_TRAS_200, NUMONYX_TRP_200,  \
+   NUMONYX_TRCD_200, NUMONYX_TRRD_200, \
+   NUMONYX_TDPL_200, NUMONYX_TDAL_200)
+
+#define NUMONYX_TWTR_200   2
+#define NUMONYX_TCKE_200   2
+#define NUMONYX_TXP_2003
+#define NUMONYX_XSR_20040
+
+#define NUMONYX_V_ACTIMB_200   \
+   ACTIM_CTRLB(NUMONYX_TWTR_200, NUMONYX_TCKE_200, \
+   NUMONYX_TXP_200, NUMONYX_XSR_200)
+
+#define NUMONYX_RASWIDTH_200   15
+#define NUMONYX_V_MCFG_200(size)   MCFG((size), NUMONYX_RASWIDTH_200)
+
 /*
  * GPMC settings -
  * Definitions is as per the following format
diff --git a/board/isee/igep0020/config.mk b/board/isee/igep0020/config.mk
deleted file mode 100644
index 7964621..000
--- a/board/isee/igep0020/config.mk
+++ /dev/null
@@ -1,33 +0,0 @@
-#
-# (C) Copyright 2009
-# ISEE 2007 SL, 
-#
-# IGEP0020 uses OMAP3 (ARM-CortexA8) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-# Physical Address:
-# 8000' (bank0)
-# A000/ (bank1)
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-
-# For use with external or internal boots.
-CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/board/isee/igep0020/igep0020.c b/board/isee/igep0020/igep0020.c
index 971e31b..a4d099a 100644
--- a/board/isee/igep0020/igep0020.c
+++ b/board/isee/igep0020/igep0020.c
@@ -58,6 +58,46 @@ int board_init(void)
return 0;
 }
 
+#ifdef CONFIG_SPL_BUILD
+/*
+ * Routine: omap_rev_string
+ * Description: For SPL builds output board rev
+ */
+void omap_rev_string(void)
+{
+}
+
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on both banks.
+ */
+void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
+   u32 *mr)
+{
+   *mr = MICRON_V_MR_165;
+#ifdef CONFIG_BOOT_NAND
+   *mcfg = MICRON_

Re: [U-Boot] [PATCH v4 1/2] tools, config.mk: add binutils-version

[Mike Frysinger]

On Thursday 19 July 2012 11:38:39 Tom Rini wrote:
> On 07/19/2012 08:21 AM, Mike Frysinger wrote:
> > On Thursday 19 July 2012 11:08:10 Tom Rini wrote:
> >> On 07/18/2012 08:11 PM, Mike Frysinger wrote:
> >>> On Wednesday 18 July 2012 19:45:52 Allen Martin wrote:
>  +MAJOR=$($gas --version | head -1 | awk '{print $NF}' | cut -d . -f 1)
>  +MINOR=$($gas --version | head -1 | awk '{print $NF}' | cut -d . -f 2)
>  +
>  +printf "%02d%02d\\n" $MAJOR $MINOR
> >>> 
> >>> can be replaced with a single awk script:
> >>> 
> >>> $gas --version | awk '{ gsub(/[.]/, " ", $NF) $0 = $NF printf
> >>> "%02d%02d\n", $1, $2 exit }'
> >> 
> >> That looks much longer and we call this once so a few execs is
> >> noise.
> > 
> > here's a shorter version: $gas --version | awk '{ gsub(/[.]/, " ",
> > $NF); $0 = $NF; printf "%02d%02d\n", $1, $2; exit }'
> 
> And still over 80 chars before we assign it to a variable.  I could
> get it to 77 chars with all whitespace removed.

which is why i unrolled it to make it readable.  i don't know what metrics 
you're using here, but i don't think the awk version is "longer" by really any 
of them.
-mike


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Re: [U-Boot] [PATCH] video: cfb_console: flush dcache for frame buffer in DRAM

[Mike Frysinger]

On Thursday 19 July 2012 11:49:20 Marek Vasut wrote:
> Dear Mike Frysinger,
> > On Tuesday 05 June 2012 03:28:40 Anatolij Gustschin wrote:
> > > On Sat, 28 Apr 2012 17:04:07 +0200 Anatolij Gustschin wrote:
> > > > Data cache flushing is required for frame buffer in RAM to fix the
> > > > distorted console text output. Currently this text distortion is
> > > > observed with cfb on beageboard and N900 when running with data
> > > > cache enabled.
> > > 
> > > Applied to u-boot-video/master after rebasing and fixing commit log.
> > 
> > this patch is still wrong for the reasons i cited earlier.  your cache
> > functions are broken, not the driver.
> 
> The cache stuff is completely borked on ARM, I have no idea why people
> enable it.

in this case, it's making it worse for other arches, and setting bad 
precedents in the process

i think Simon's solution is a good middle ground:
lcd: Add support for flushing LCD fb from dcache after update
-mike


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Re: [U-Boot] [PATCH v3 13/18] lcd: Add support for flushing LCD fb from dcache after update

[Mike Frysinger]

On Thursday 12 July 2012 11:25:13 Simon Glass wrote:
> +void lcd_sync(void)
> +{
> + /*
> +  * flush_dcache_range() is declared in common.h but it seems that some
> +  * architectures do not actually implement it. Is there a way to find
> +  * out whether it exists? For now, ARM is safe.
> +  */
> +#ifdef CONFIG_ARM
> + int line_length;
> +
> + if (lcd_flush_dcache)
> + flush_dcache_range((u32)lcd_base,
> + (u32)(lcd_base + lcd_get_size(&line_length)));
> +#endif
> +}

hmm, i think this should be more fine grained

>   /* Clear the last one */
>   memset (CONSOLE_ROW_LAST, COLOR_MASK(lcd_color_bg), CONSOLE_ROW_SIZE);
> + lcd_sync();
>  }

this requires only updating one row and not the entire display right ?  so we 
should only flush that one line.  seems like other parts suffer similar over-
flushing behavior.

> +/**
> + * Set whether we need to flush the dcache when changing the LCD image.
> + * This defaults to off.

i wonder if this default is correct.  perhaps it should default to 1 since 
setting up custom memory maps to disable cache is fairly specially.
-mike


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[U-Boot] Pull request: u-boot-net.git next

[Joe Hershberger]

The following changes since commit 0878222fed3fafbfd0b1f2e5a6b2da90a81e910d:
  Wolfgang Denk (1):
Merge branch 'next' of git://git.denx.de/u-boot-net into next

are available in the git repository at:

  git://git.denx.de/u-boot-net.git next

Tetsuyuki Kobayashi (1):
  net: nfs: make NFS_TIMEOUT configurable

benoit.thebaudeau@advans (2):
  net: fec_mxc: Fix setting of RCR for xMII
  net: fec_mxc: Fix MDC for xMII

 README|7 +++
 drivers/net/fec_mxc.c |   10 --
 net/nfs.c |6 +-
 3 files changed, 16 insertions(+), 7 deletions(-)
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Re: [U-Boot] [PATCH v4 1/2] tools, config.mk: add binutils-version

[Tom Rini]

-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1

On 07/19/2012 09:43 AM, Mike Frysinger wrote:
> On Thursday 19 July 2012 11:38:39 Tom Rini wrote:
>> On 07/19/2012 08:21 AM, Mike Frysinger wrote:
>>> On Thursday 19 July 2012 11:08:10 Tom Rini wrote:
 On 07/18/2012 08:11 PM, Mike Frysinger wrote:
> On Wednesday 18 July 2012 19:45:52 Allen Martin wrote:
>> +MAJOR=$($gas --version | head -1 | awk '{print $NF}' |
>> cut -d . -f 1) +MINOR=$($gas --version | head -1 | awk
>> '{print $NF}' | cut -d . -f 2) + +printf "%02d%02d\\n"
>> $MAJOR $MINOR
> 
> can be replaced with a single awk script:
> 
> $gas --version | awk '{ gsub(/[.]/, " ", $NF) $0 = $NF
> printf "%02d%02d\n", $1, $2 exit }'
 
 That looks much longer and we call this once so a few execs
 is noise.
>>> 
>>> here's a shorter version: $gas --version | awk '{ gsub(/[.]/, "
>>> ", $NF); $0 = $NF; printf "%02d%02d\n", $1, $2; exit }'
>> 
>> And still over 80 chars before we assign it to a variable.  I
>> could get it to 77 chars with all whitespace removed.
> 
> which is why i unrolled it to make it readable.  i don't know what
> metrics you're using here, but i don't think the awk version is
> "longer" by really any of them.

The metric of 'wc -c' and "what fits in a single line, unwrapped on an
80x24 terminal."  awk is great and awesome, don't get me wrong, but
it's not doing the job as compactly as the original.

- -- 
Tom
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[U-Boot] Pull request: u-boot-net.git master

[Joe Hershberger]

The following changes since commit 66714b1a6df0a5a9f1656a6d4e6eea3c7ecdf7ae:
  Wolfgang Denk (1):
Merge branch 'next' of git://git.denx.de/u-boot-video

are available in the git repository at:

  git://git.denx.de/u-boot-net.git master

benoit.thebaudeau@advans (2):
  net: bootp: fix build
  net: link_local: fix build

 net/bootp.c  |2 +-
 net/link_local.c |6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)
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Re: [U-Boot] [PATCH] i.MX28: bug fixes in PMU configuration code

[Marek Vasut]

Dear Stathis Voukelatos,

> Fixed some typos in the i.MX28 PMU code that sets up the VDDD
> and VDDIO power rails. In addition the VDDD and VDDIO brownout
> offset values should be divided by a step size before being
> programmed to the corresponding registers.
> 
> Signed-off-by: Stathis Voukelatos 
> Cc: Stefano Babic 
> Cc: Marek Vasut 

Stefano, I think this should be applied.

THanks!

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 3/3] ARM: mx28: Remove CONFIG_ARCH_CPU_INIT

[Marek Vasut]

Dear Albert ARIBAUD,

> Hi Fabio,
> 
> On Thu, 1 Mar 2012 19:31:54 +0100, Marek Vasut  wrote:
> > > No need to define CONFIG_ARCH_CPU_INIT.
> > > 
> > > All mx28 based boards should use arch_cpu_init().
> > 
> > Acked-by: Marek Vasut 
> > 
> > > Signed-off-by: Fabio Estevam 
> > > ---
> 
> Applied to ub-boot-arm/master, thanks.

Did you also apply 1/3 ? If not, everything will be broken now (at least mx28 
doesn't boot without 1/3 applied as well).

> Amicalement,

Best regards,
Marek Vasut
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[U-Boot] (no subject)

[Gigin Jose]

http://blog.eduangelis.com.br/wp-content/plugins/zefeeldfego/work.php?shinning213.jpeg___
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Re: [U-Boot] [PATCH] net: link_local: fix build

[Joe Hershberger]

Hi Benoît,

On Thu, Jul 19, 2012 at 6:19 AM, Benoît Thébaudeau
 wrote:
> Fix comment within comment build error.
>
> Signed-off-by: Benoît Thébaudeau 
> Cc: Joe Hershberger 
> ---

Applied, thanks.

-Joe
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Re: [U-Boot] [PATCH] net: bootp: fix build

[Joe Hershberger]

Hi Benoît,

On Thu, Jul 19, 2012 at 6:23 AM, Benoît Thébaudeau
 wrote:
> Fix NetSetState function name used with CONFIG_BOOTP_MAY_FAIL.
>
> Signed-off-by: Benoît Thébaudeau 
> Cc: Joe Hershberger 
> ---

Applied, thanks.

-Joe
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Re: [U-Boot] [PATCH 2/2] net: fec_mxc: Fix MDC for xMII

[Joe Hershberger]

Hi Benoît,

On Thu, Jul 19, 2012 at 7:12 AM, Benoît Thébaudeau
 wrote:
> The MDC signal is available on all xMII (i.e. 'not 7-wire') interfaces, so
> mii_speed has to be set for all these interfaces, and not only for MII.
>
> Signed-off-by: Benoît Thébaudeau 
> Cc: Joe Hershberger 
> Cc: Stefano Babic 
> ---

Applied to next, thanks.

-Joe
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[U-Boot] [PATCH V3 02/25] mxc_i2c: remove ifdef of CONFIG_HARD_I2C

[Troy Kisky]

This is always selected when CONFIG_I2C_MXC is
selected, so it adds no value.

Signed-off-by: Troy Kisky 
Acked-by: Marek Vasut 

---
v2: add ack
---
 drivers/i2c/mxc_i2c.c |6 +-
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index c0c45fd..0b46c9c 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -31,12 +31,9 @@
  */
 
 #include 
-#include 
-
-#if defined(CONFIG_HARD_I2C)
-
 #include 
 #include 
+#include 
 #include 
 
 struct mxc_i2c_regs {
@@ -446,4 +443,3 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buf, 
int len)
 
return ret;
 }
-#endif /* CONFIG_HARD_I2C */
-- 
1.7.9.5

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[U-Boot] [PATCH V3 03/25] mxc_i2c: create tx_byte function

[Troy Kisky]

Use tx_byte function instead of having 3 copies
of the code.

Signed-off-by: Troy Kisky 
Acked-by: Marek Vasut 

---
v2: add ack
change ret to integer from unsigned
---
 drivers/i2c/mxc_i2c.c |   82 +++--
 1 file changed, 24 insertions(+), 58 deletions(-)

diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 0b46c9c..d147dd5 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -33,6 +33,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -207,17 +208,21 @@ int i2c_imx_trx_complete(void)
udelay(1);
}
 
-   return 1;
+   return -ETIMEDOUT;
 }
 
-/*
- * Check if the transaction was ACKed
- */
-int i2c_imx_acked(void)
+static int tx_byte(struct mxc_i2c_regs *i2c_regs, u8 byte)
 {
-   struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
+   int ret;
 
-   return readb(&i2c_regs->i2sr) & I2SR_RX_NO_AK;
+   writeb(byte, &i2c_regs->i2dr);
+   ret = i2c_imx_trx_complete();
+   if (ret < 0)
+   return ret;
+   ret = readb(&i2c_regs->i2sr);
+   if (ret & I2SR_RX_NO_AK)
+   return -ENODEV;
+   return 0;
 }
 
 /*
@@ -271,30 +276,6 @@ void i2c_imx_stop(void)
 }
 
 /*
- * Set chip address and access mode
- *
- * read = 1: READ access
- * read = 0: WRITE access
- */
-int i2c_imx_set_chip_addr(uchar chip, int read)
-{
-   struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
-   int ret;
-
-   writeb((chip << 1) | read, &i2c_regs->i2dr);
-
-   ret = i2c_imx_trx_complete();
-   if (ret)
-   return ret;
-
-   ret = i2c_imx_acked();
-   if (ret)
-   return ret;
-
-   return ret;
-}
-
-/*
  * Write register address
  */
 int i2c_imx_set_reg_addr(uint addr, int alen)
@@ -303,14 +284,8 @@ int i2c_imx_set_reg_addr(uint addr, int alen)
int ret = 0;
 
while (alen--) {
-   writeb((addr >> (alen * 8)) & 0xff, &i2c_regs->i2dr);
-
-   ret = i2c_imx_trx_complete();
-   if (ret)
-   break;
-
-   ret = i2c_imx_acked();
-   if (ret)
+   ret = tx_byte(i2c_regs, (addr >> (alen * 8)) & 0xff);
+   if (ret < 0)
break;
}
 
@@ -322,18 +297,15 @@ int i2c_imx_set_reg_addr(uint addr, int alen)
  */
 int i2c_probe(uchar chip)
 {
+   struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
int ret;
 
ret = i2c_imx_start();
if (ret)
return ret;
 
-   ret = i2c_imx_set_chip_addr(chip, 0);
-   if (ret)
-   return ret;
-
+   ret = tx_byte(i2c_regs, chip << 1);
i2c_imx_stop();
-
return ret;
 }
 
@@ -352,8 +324,8 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, 
int len)
return ret;
 
/* write slave address */
-   ret = i2c_imx_set_chip_addr(chip, 0);
-   if (ret)
+   ret = tx_byte(i2c_regs, chip << 1);
+   if (ret < 0)
return ret;
 
ret = i2c_imx_set_reg_addr(addr, alen);
@@ -364,8 +336,8 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, 
int len)
temp |= I2CR_RSTA;
writeb(temp, &i2c_regs->i2cr);
 
-   ret = i2c_imx_set_chip_addr(chip, 1);
-   if (ret)
+   ret = tx_byte(i2c_regs, (chip << 1) | 1);
+   if (ret < 0)
return ret;
 
/* setup bus to read data */
@@ -419,8 +391,8 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buf, 
int len)
return ret;
 
/* write slave address */
-   ret = i2c_imx_set_chip_addr(chip, 0);
-   if (ret)
+   ret = tx_byte(i2c_regs, chip << 1);
+   if (ret < 0)
return ret;
 
ret = i2c_imx_set_reg_addr(addr, alen);
@@ -428,14 +400,8 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buf, 
int len)
return ret;
 
for (i = 0; i < len; i++) {
-   writeb(buf[i], &i2c_regs->i2dr);
-
-   ret = i2c_imx_trx_complete();
-   if (ret)
-   return ret;
-
-   ret = i2c_imx_acked();
-   if (ret)
+   ret = tx_byte(i2c_regs, buf[i]);
+   if (ret < 0)
return ret;
}
 
-- 
1.7.9.5

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[U-Boot] [PATCH V3 06/25] mxc_i2c: call i2c_imx_stop on error in i2c_read/i2c_write

[Troy Kisky]

Signed-off-by: Troy Kisky 
---
 drivers/i2c/mxc_i2c.c |   10 +++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 4ce695a..55a688a 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -337,8 +337,10 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, 
int len)
writeb(temp, &i2c_regs->i2cr);
 
ret = tx_byte(i2c_regs, (chip << 1) | 1);
-   if (ret < 0)
+   if (ret < 0) {
+   i2c_imx_stop();
return ret;
+   }
 
/* setup bus to read data */
temp = readb(&i2c_regs->i2cr);
@@ -352,8 +354,10 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, 
int len)
/* read data */
for (i = 0; i < len; i++) {
ret = i2c_imx_trx_complete();
-   if (ret)
+   if (ret) {
+   i2c_imx_stop();
return ret;
+   }
 
/*
 * It must generate STOP before read I2DR to prevent
@@ -395,7 +399,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buf, 
int len)
for (i = 0; i < len; i++) {
ret = tx_byte(i2c_regs, buf[i]);
if (ret < 0)
-   return ret;
+   break;
}
 
i2c_imx_stop();
-- 
1.7.9.5

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[U-Boot] [PATCH V3 01/25] mxc_i2c: fix i2c_imx_stop

[Troy Kisky]

Instead of clearing 2 bits, all the other
bits were set because '|=' was used instead
of '&='.

Signed-off-by: Troy Kisky 
Acked-by: Marek Vasut 
Acked-by: Stefano Babic 

---
V2: add acks



V3: rename toggle to idle_bus in patches 17,18,24
and a rebase


Heiko, can you take 1-19 if no comments
Stefano, can you take 20-23


24 and 25 will wait until both sets are in same tree


---
 drivers/i2c/mxc_i2c.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index fc68062..c0c45fd 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -264,7 +264,7 @@ void i2c_imx_stop(void)
 
/* Stop I2C transaction */
temp = readb(&i2c_regs->i2cr);
-   temp |= ~(I2CR_MSTA | I2CR_MTX);
+   temp &= ~(I2CR_MSTA | I2CR_MTX);
writeb(temp, &i2c_regs->i2cr);
 
i2c_imx_bus_busy(0);
-- 
1.7.9.5

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[U-Boot] [PATCH V3 09/25] mxc_i2c: remove redundant read

[Troy Kisky]

wait_for_sr_state returns i2sr on success
so no need to read again.

Signed-off-by: Troy Kisky 
Acked-by: Marek Vasut 

---
v2: add ack
---
 drivers/i2c/mxc_i2c.c |1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 01a6408..83c2fab 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -195,7 +195,6 @@ static int tx_byte(struct mxc_i2c_regs *i2c_regs, u8 byte)
ret = wait_for_sr_state(i2c_regs, ST_IIF);
if (ret < 0)
return ret;
-   ret = readb(&i2c_regs->i2sr);
if (ret & I2SR_RX_NO_AK)
return -ENODEV;
return 0;
-- 
1.7.9.5

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[U-Boot] [PATCH V3 04/25] mxc_i2c: clear i2sr before waiting for bit

[Troy Kisky]

Let's clear the sr register before waiting for
bit to be set, instead of clearing it after
hardware sets it. No real operational difference here,
but allows combining of i2c_imx_trx_complete and
i2c_imx_bus_busy in later patches.

Signed-off-by: Troy Kisky 
Acked-by: Marek Vasut 

---
v2: add ack
add clear of i2sr in i2c_read
---
 drivers/i2c/mxc_i2c.c |9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index d147dd5..57027ad 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -200,10 +200,8 @@ int i2c_imx_trx_complete(void)
int timeout = I2C_MAX_TIMEOUT;
 
while (timeout--) {
-   if (readb(&i2c_regs->i2sr) & I2SR_IIF) {
-   writeb(0, &i2c_regs->i2sr);
+   if (readb(&i2c_regs->i2sr) & I2SR_IIF)
return 0;
-   }
 
udelay(1);
}
@@ -215,6 +213,7 @@ static int tx_byte(struct mxc_i2c_regs *i2c_regs, u8 byte)
 {
int ret;
 
+   writeb(0, &i2c_regs->i2sr);
writeb(byte, &i2c_regs->i2dr);
ret = i2c_imx_trx_complete();
if (ret < 0)
@@ -346,7 +345,8 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, 
int len)
if (len == 1)
temp |= I2CR_TX_NO_AK;
writeb(temp, &i2c_regs->i2cr);
-   readb(&i2c_regs->i2dr);
+   writeb(0, &i2c_regs->i2sr);
+   readb(&i2c_regs->i2dr); /* dummy read to clear ICF */
 
/* read data */
for (i = 0; i < len; i++) {
@@ -369,6 +369,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, 
int len)
writeb(temp, &i2c_regs->i2cr);
}
 
+   writeb(0, &i2c_regs->i2sr);
buf[i] = readb(&i2c_regs->i2dr);
}
 
-- 
1.7.9.5

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[U-Boot] [PATCH V3 13/25] mxc_i2c: change slave addr if conflicts with destination.

[Troy Kisky]

The i2c controller cannot be both master and slave in the
same transaction.

Signed-off-by: Troy Kisky 

---
v2: no change
---
 drivers/i2c/mxc_i2c.c |2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 1a5e379..ba2aad3 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -223,6 +223,8 @@ static int i2c_init_transfer(struct mxc_i2c_regs *i2c_regs,
/* Wait for controller to be stable */
udelay(50);
}
+   if (readb(&i2c_regs->iadr) == (chip << 1))
+   writeb((chip << 1) ^ 2, &i2c_regs->iadr);
writeb(0, &i2c_regs->i2sr);
ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE);
if (ret < 0)
-- 
1.7.9.5

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[U-Boot] [PATCH V3 10/25] mxc_i2c: place imx_start code inline

[Troy Kisky]

imx_start is only referenced once so
move to that location.

Signed-off-by: Troy Kisky 
Acked-by: Marek Vasut 

---
v2: add ack
---
 drivers/i2c/mxc_i2c.c |   53 +++--
 1 file changed, 20 insertions(+), 33 deletions(-)

diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 83c2fab..9efa9bd 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -201,37 +201,6 @@ static int tx_byte(struct mxc_i2c_regs *i2c_regs, u8 byte)
 }
 
 /*
- * Start the controller
- */
-int i2c_imx_start(void)
-{
-   struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
-   unsigned int temp = 0;
-   int result;
-
-   /* Enable I2C controller */
-   writeb(0, &i2c_regs->i2sr);
-   writeb(I2CR_IEN, &i2c_regs->i2cr);
-
-   /* Wait controller to be stable */
-   udelay(50);
-
-   /* Start I2C transaction */
-   temp = readb(&i2c_regs->i2cr);
-   temp |= I2CR_MSTA;
-   writeb(temp, &i2c_regs->i2cr);
-
-   result = wait_for_sr_state(i2c_regs, ST_BUS_BUSY);
-   if (result < 0)
-   return result;
-
-   temp |= I2CR_MTX | I2CR_TX_NO_AK;
-   writeb(temp, &i2c_regs->i2cr);
-
-   return 0;
-}
-
-/*
  * Stop the controller
  */
 void i2c_imx_stop(void)
@@ -259,10 +228,28 @@ void i2c_imx_stop(void)
 static int i2c_init_transfer(struct mxc_i2c_regs *i2c_regs,
uchar chip, uint addr, int alen)
 {
-   int ret = i2c_imx_start();
-   if (ret)
+   unsigned int temp;
+   int ret;
+
+   /* Enable I2C controller */
+   writeb(0, &i2c_regs->i2sr);
+   writeb(I2CR_IEN, &i2c_regs->i2cr);
+
+   /* Wait for controller to be stable */
+   udelay(50);
+
+   /* Start I2C transaction */
+   temp = readb(&i2c_regs->i2cr);
+   temp |= I2CR_MSTA;
+   writeb(temp, &i2c_regs->i2cr);
+
+   ret = wait_for_sr_state(i2c_regs, ST_BUS_BUSY);
+   if (ret < 0)
goto exit;
 
+   temp |= I2CR_MTX | I2CR_TX_NO_AK;
+   writeb(temp, &i2c_regs->i2cr);
+
/* write slave address */
ret = tx_byte(i2c_regs, chip << 1);
if (ret < 0)
-- 
1.7.9.5

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Re: [U-Boot] [PATCH 1/8 V6] EXYNOS: CLK: Add i2c clock

[Simon Glass]

On Thu, Jul 19, 2012 at 12:39 PM, Rajeshwari Shinde
 wrote:
> This adds i2c clock information for EXYNOS5.
>
> Signed-off-by: Alim Akhtar 
> Signed-off-by: Doug Anderson 
> Signed-off-by: Rajeshwari Shinde 
> Acked-by: Simon Glass 

Acked-by: Simon Glass 

> ---
> changes in V2:
> - Incorporated comments from Simon Glass which are removed extra
>   braces around (readl(&clk->div_top1)) >> 24 and gave a tab space for
>   return statement.
> Changes in V3:
> - None
> Changes in V4:
> - None
> Changes in V5:
> - None.
> Changes in V6:
> - Incorporated review comments from Simon Glass.
>  arch/arm/cpu/armv7/exynos/clock.c  |   33 
> 
>  arch/arm/include/asm/arch-exynos/clk.h |1 +
>  2 files changed, 34 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/exynos/clock.c 
> b/arch/arm/cpu/armv7/exynos/clock.c
> index 672598f..de3db8e 100644
> --- a/arch/arm/cpu/armv7/exynos/clock.c
> +++ b/arch/arm/cpu/armv7/exynos/clock.c
> @@ -605,6 +605,29 @@ void exynos4_set_mipi_clk(void)
> writel(cfg, &clk->div_lcd0);
>  }
>
> +/*
> + * I2C
> + *
> + * exynos5: obtaining the I2C clock
> + */
> +static unsigned long exynos5_get_i2c_clk(void)
> +{
> +   struct exynos5_clock *clk =
> +   (struct exynos5_clock *)samsung_get_base_clock();
> +   unsigned long aclk_66, aclk_66_pre, sclk;
> +   unsigned int ratio;
> +
> +   sclk = get_pll_clk(MPLL);
> +
> +   ratio = (readl(&clk->div_top1)) >> 24;
> +   ratio &= 0x7;
> +   aclk_66_pre = sclk / (ratio + 1);
> +   ratio = readl(&clk->div_top0);
> +   ratio &= 0x7;
> +   aclk_66 = aclk_66_pre / (ratio + 1);
> +   return aclk_66;
> +}
> +
>  unsigned long get_pll_clk(int pllreg)
>  {
> if (cpu_is_exynos5())
> @@ -621,6 +644,16 @@ unsigned long get_arm_clk(void)
> return exynos4_get_arm_clk();
>  }
>
> +unsigned long get_i2c_clk(void)
> +{
> +   if (cpu_is_exynos5()) {
> +   return exynos5_get_i2c_clk();
> +   } else {
> +   debug("I2C clock is not set for this CPU\n");
> +   return 0;
> +   }
> +}
> +
>  unsigned long get_pwm_clk(void)
>  {
> if (cpu_is_exynos5())
> diff --git a/arch/arm/include/asm/arch-exynos/clk.h 
> b/arch/arm/include/asm/arch-exynos/clk.h
> index e99339a..5529025 100644
> --- a/arch/arm/include/asm/arch-exynos/clk.h
> +++ b/arch/arm/include/asm/arch-exynos/clk.h
> @@ -31,6 +31,7 @@
>
>  unsigned long get_pll_clk(int pllreg);
>  unsigned long get_arm_clk(void);
> +unsigned long get_i2c_clk(void);
>  unsigned long get_pwm_clk(void);
>  unsigned long get_uart_clk(int dev_index);
>  void set_mmc_clk(int dev_index, unsigned int div);
> --
> 1.7.4.4
>
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[U-Boot] [PATCH V3 05/25] mxc_i2c: create i2c_init_transfer

[Troy Kisky]

Initial code of i2c_read and i2c_write
is identical, move to subroutine.

Signed-off-by: Troy Kisky 
Acked-by: Marek Vasut 
Acked-by: Stefano Babic 

---
v2: add ack
---
 drivers/i2c/mxc_i2c.c |   44 ++--
 1 file changed, 18 insertions(+), 26 deletions(-)

diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 57027ad..4ce695a 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -275,19 +275,29 @@ void i2c_imx_stop(void)
 }
 
 /*
- * Write register address
+ * Send start signal, chip address and
+ * write register address
  */
-int i2c_imx_set_reg_addr(uint addr, int alen)
+static int i2c_init_transfer(struct mxc_i2c_regs *i2c_regs,
+   uchar chip, uint addr, int alen)
 {
-   struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
-   int ret = 0;
+   int ret = i2c_imx_start();
+   if (ret)
+   goto exit;
+
+   /* write slave address */
+   ret = tx_byte(i2c_regs, chip << 1);
+   if (ret < 0)
+   goto exit;
 
while (alen--) {
ret = tx_byte(i2c_regs, (addr >> (alen * 8)) & 0xff);
if (ret < 0)
-   break;
+   goto exit;
}
-
+   return 0;
+exit:
+   i2c_imx_stop();
return ret;
 }
 
@@ -318,19 +328,10 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, 
int len)
unsigned int temp;
int i;
 
-   ret = i2c_imx_start();
-   if (ret)
-   return ret;
-
-   /* write slave address */
-   ret = tx_byte(i2c_regs, chip << 1);
+   ret = i2c_init_transfer(i2c_regs, chip, addr, alen);
if (ret < 0)
return ret;
 
-   ret = i2c_imx_set_reg_addr(addr, alen);
-   if (ret)
-   return ret;
-
temp = readb(&i2c_regs->i2cr);
temp |= I2CR_RSTA;
writeb(temp, &i2c_regs->i2cr);
@@ -387,19 +388,10 @@ int i2c_write(uchar chip, uint addr, int alen, uchar 
*buf, int len)
int ret;
int i;
 
-   ret = i2c_imx_start();
-   if (ret)
-   return ret;
-
-   /* write slave address */
-   ret = tx_byte(i2c_regs, chip << 1);
+   ret = i2c_init_transfer(i2c_regs, chip, addr, alen);
if (ret < 0)
return ret;
 
-   ret = i2c_imx_set_reg_addr(addr, alen);
-   if (ret)
-   return ret;
-
for (i = 0; i < len; i++) {
ret = tx_byte(i2c_regs, buf[i]);
if (ret < 0)
-- 
1.7.9.5

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[U-Boot] [PATCH V3 08/25] mxc_i2c: combine i2c_imx_bus_busy and i2c_imx_trx_complete into wait_for_sr_state

[Troy Kisky]

Not using udelay gives a more accurate timeout. The current implementation of 
udelay
in imx-common does not seem to wait at all for a udelay(1).

Signed-off-by: Troy Kisky 
Acked-by: Marek Vasut 


V2: Added WATCHDOG_RESET as suggested by Marek Vasut
add error message when stop fails

mxc_i2c: code i2c_probe as a 0 length i2c_write

Signed-off-by: Troy Kisky 
Acked-by: Marek Vasut 
Acked-by: Stefano Babic 

---
v2: add acks
---
 drivers/i2c/mxc_i2c.c |   80 ++---
 1 file changed, 29 insertions(+), 51 deletions(-)

diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 626e13e..01a6408 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -36,6 +36,7 @@
 #include 
 #include 
 #include 
+#include 
 
 struct mxc_i2c_regs {
uint32_tiadr;
@@ -63,8 +64,6 @@ struct mxc_i2c_regs {
 #error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver"
 #endif
 
-#define I2C_MAX_TIMEOUT1
-
 static u16 i2c_clk_div[50][2] = {
{ 22,   0x20 }, { 24,   0x21 }, { 26,   0x22 }, { 28,   0x23 },
{ 30,   0x00 }, { 32,   0x24 }, { 36,   0x25 }, { 40,   0x26 },
@@ -164,48 +163,26 @@ unsigned int i2c_get_bus_speed(void)
return mxc_get_clock(MXC_IPG_PERCLK) / i2c_clk_div[clk_div][0];
 }
 
-/*
- * Wait for bus to be busy (or free if for_busy = 0)
- *
- * for_busy = 1: Wait for IBB to be asserted
- * for_busy = 0: Wait for IBB to be de-asserted
- */
-int i2c_imx_bus_busy(int for_busy)
-{
-   struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
-   unsigned int temp;
-
-   int timeout = I2C_MAX_TIMEOUT;
-
-   while (timeout--) {
-   temp = readb(&i2c_regs->i2sr);
-
-   if (for_busy && (temp & I2SR_IBB))
-   return 0;
-   if (!for_busy && !(temp & I2SR_IBB))
-   return 0;
-
-   udelay(1);
-   }
-
-   return 1;
-}
+#define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
+#define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8))
+#define ST_IIF (I2SR_IIF | (I2SR_IIF << 8))
 
-/*
- * Wait for transaction to complete
- */
-int i2c_imx_trx_complete(void)
+static int wait_for_sr_state(struct mxc_i2c_regs *i2c_regs, unsigned state)
 {
-   struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
-   int timeout = I2C_MAX_TIMEOUT;
-
-   while (timeout--) {
-   if (readb(&i2c_regs->i2sr) & I2SR_IIF)
-   return 0;
-
-   udelay(1);
+   unsigned sr;
+   ulong elapsed;
+   ulong start_time = get_timer(0);
+   for (;;) {
+   sr = readb(&i2c_regs->i2sr);
+   if ((sr & (state >> 8)) == (unsigned char)state)
+   return sr;
+   WATCHDOG_RESET();
+   elapsed = get_timer(start_time);
+   if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */
+   break;
}
-
+   printf("%s: failed sr=%x cr=%x state=%x\n", __func__,
+   sr, readb(&i2c_regs->i2cr), state);
return -ETIMEDOUT;
 }
 
@@ -215,7 +192,7 @@ static int tx_byte(struct mxc_i2c_regs *i2c_regs, u8 byte)
 
writeb(0, &i2c_regs->i2sr);
writeb(byte, &i2c_regs->i2dr);
-   ret = i2c_imx_trx_complete();
+   ret = wait_for_sr_state(i2c_regs, ST_IIF);
if (ret < 0)
return ret;
ret = readb(&i2c_regs->i2sr);
@@ -245,8 +222,8 @@ int i2c_imx_start(void)
temp |= I2CR_MSTA;
writeb(temp, &i2c_regs->i2cr);
 
-   result = i2c_imx_bus_busy(1);
-   if (result)
+   result = wait_for_sr_state(i2c_regs, ST_BUS_BUSY);
+   if (result < 0)
return result;
 
temp |= I2CR_MTX | I2CR_TX_NO_AK;
@@ -260,6 +237,7 @@ int i2c_imx_start(void)
  */
 void i2c_imx_stop(void)
 {
+   int ret;
struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
unsigned int temp = 0;
 
@@ -268,8 +246,9 @@ void i2c_imx_stop(void)
temp &= ~(I2CR_MSTA | I2CR_MTX);
writeb(temp, &i2c_regs->i2cr);
 
-   i2c_imx_bus_busy(0);
-
+   ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE);
+   if (ret < 0)
+   printf("%s:trigger stop failed\n", __func__);
/* Disable I2C controller */
writeb(0, &i2c_regs->i2cr);
 }
@@ -336,8 +315,8 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, 
int len)
 
/* read data */
for (i = 0; i < len; i++) {
-   ret = i2c_imx_trx_complete();
-   if (ret) {
+   ret = wait_for_sr_state(i2c_regs, ST_IIF);
+   if (ret < 0) {
i2c_imx_stop();
return ret;
}
@@ -350,20 +329,19 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buf, 
int len)
temp = readb(&i2c_regs->i2cr);
temp &= ~(I2CR_MSTA | I2CR_MTX);
writeb(temp,

[U-Boot] [PATCH V3 18/25] mxc_i2c: add bus recovery support

[Troy Kisky]

Add support for calling a function that will toggle the
SCL line to return the bus to idle condition.

The actual toggling function is added in a later patch.

Signed-off-by: Troy Kisky 

---
v2: commit log change, global data in sram section.
make toggle_i2c return int

v3: rename toggle to idle_bus
---
 drivers/i2c/mxc_i2c.c |   26 ++
 1 file changed, 26 insertions(+)

diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index ead6e20..c00ead1 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -251,6 +251,8 @@ static int i2c_init_transfer_(struct mxc_i2c_regs *i2c_regs,
return 0;
 }
 
+static int i2c_idle_bus(void *base);
+
 static int i2c_init_transfer(struct mxc_i2c_regs *i2c_regs,
uchar chip, uint addr, int alen)
 {
@@ -269,6 +271,8 @@ static int i2c_init_transfer(struct mxc_i2c_regs *i2c_regs,
if (ret != -ERESTART)
writeb(0, &i2c_regs->i2cr); /* Disable controller */
udelay(100);
+   if (i2c_idle_bus(i2c_regs) < 0)
+   break;
}
printf("%s: give up i2c_regs=%p\n", __func__, i2c_regs);
return ret;
@@ -390,6 +394,28 @@ void *get_base(void)
 #endif
 }
 
+static struct i2c_parms *i2c_get_parms(void *base)
+{
+   int i = 0;
+   struct i2c_parms *p = srdata.i2c_data;
+   while (i < ARRAY_SIZE(srdata.i2c_data)) {
+   if (p->base == base)
+   return p;
+   p++;
+   i++;
+   }
+   printf("Invalid I2C base: %p\n", base);
+   return NULL;
+}
+
+static int i2c_idle_bus(void *base)
+{
+   struct i2c_parms *p = i2c_get_parms(base);
+   if (p && p->idle_bus_fn)
+   return p->idle_bus_fn(p->idle_bus_data);
+   return 0;
+}
+
 int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
 {
return bus_i2c_read(get_base(), chip, addr, alen, buf, len);
-- 
1.7.9.5

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[U-Boot] [PATCH V3 07/25] mxc_i2c.c: code i2c_probe as a 0 length i2c_write

[Troy Kisky]

Signed-off-by: Troy Kisky 
Acked-by: Marek Vasut 
Acked-by: Stefano Babic 

---
v2: add acks
change comment
---
---
 drivers/i2c/mxc_i2c.c |   25 -
 1 file changed, 8 insertions(+), 17 deletions(-)

diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 55a688a..626e13e 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -302,23 +302,6 @@ exit:
 }
 
 /*
- * Try if a chip add given address responds (probe the chip)
- */
-int i2c_probe(uchar chip)
-{
-   struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
-   int ret;
-
-   ret = i2c_imx_start();
-   if (ret)
-   return ret;
-
-   ret = tx_byte(i2c_regs, chip << 1);
-   i2c_imx_stop();
-   return ret;
-}
-
-/*
  * Read data from I2C device
  */
 int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
@@ -406,3 +389,11 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buf, 
int len)
 
return ret;
 }
+
+/*
+ * Test if a chip at a given address responds (probe the chip)
+ */
+int i2c_probe(uchar chip)
+{
+   return i2c_write(chip, 0, 0, NULL, 0);
+}
-- 
1.7.9.5

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[U-Boot] [PATCH V3 23/25] i.mx53: add definition for I2C3_BASE_ADDR

[Troy Kisky]

Signed-off-by: Troy Kisky 

---
v2: no change
---
 arch/arm/include/asm/arch-mx5/imx-regs.h |1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h 
b/arch/arm/include/asm/arch-mx5/imx-regs.h
index 88fb7cb..10f0ced 100644
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -98,6 +98,7 @@
 #define GPIO5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000DC000)
 #define GPIO6_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E)
 #define GPIO7_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E4000)
+#define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x000EC000)
 #define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F)
 #endif
 /*
-- 
1.7.9.5

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[U-Boot] [PATCH V3 15/25] mxc_i2c: add retries

[Troy Kisky]

Retry unexpected hardware errors. This
will not retry a received NAK.

Signed-off-by: Troy Kisky 

---
v2: if i2c_init_transfer_ returns no error, then return 0
---
 drivers/i2c/mxc_i2c.c |   36 +++-
 1 file changed, 27 insertions(+), 9 deletions(-)

diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 093a73f..cbb0fff 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -218,7 +218,7 @@ void i2c_imx_stop(void)
  * Send start signal, chip address and
  * write register address
  */
-static int i2c_init_transfer(struct mxc_i2c_regs *i2c_regs,
+static int i2c_init_transfer_(struct mxc_i2c_regs *i2c_regs,
uchar chip, uint addr, int alen)
 {
unsigned int temp;
@@ -235,7 +235,7 @@ static int i2c_init_transfer(struct mxc_i2c_regs *i2c_regs,
writeb(0, &i2c_regs->i2sr);
ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE);
if (ret < 0)
-   goto exit;
+   return ret;
 
/* Start I2C transaction */
temp = readb(&i2c_regs->i2cr);
@@ -244,7 +244,7 @@ static int i2c_init_transfer(struct mxc_i2c_regs *i2c_regs,
 
ret = wait_for_sr_state(i2c_regs, ST_BUS_BUSY);
if (ret < 0)
-   goto exit;
+   return ret;
 
temp |= I2CR_MTX | I2CR_TX_NO_AK;
writeb(temp, &i2c_regs->i2cr);
@@ -252,18 +252,36 @@ static int i2c_init_transfer(struct mxc_i2c_regs 
*i2c_regs,
/* write slave address */
ret = tx_byte(i2c_regs, chip << 1);
if (ret < 0)
-   goto exit;
+   return ret;
 
while (alen--) {
ret = tx_byte(i2c_regs, (addr >> (alen * 8)) & 0xff);
if (ret < 0)
-   goto exit;
+   return ret;
}
return 0;
-exit:
-   i2c_imx_stop();
-   /* Disable I2C controller */
-   writeb(0, &i2c_regs->i2cr);
+}
+
+static int i2c_init_transfer(struct mxc_i2c_regs *i2c_regs,
+   uchar chip, uint addr, int alen)
+{
+   int retry;
+   int ret;
+   for (retry = 0; retry < 3; retry++) {
+   ret = i2c_init_transfer_(i2c_regs, chip, addr, alen);
+   if (ret >= 0)
+   return 0;
+   i2c_imx_stop();
+   if (ret == -ENODEV)
+   return ret;
+
+   printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip,
+   retry);
+   if (ret != -ERESTART)
+   writeb(0, &i2c_regs->i2cr); /* Disable controller */
+   udelay(100);
+   }
+   printf("%s: give up i2c_regs=%p\n", __func__, i2c_regs);
return ret;
 }
 
-- 
1.7.9.5

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Re: [U-Boot] [PATCH 3/8 V6] EXYNOS5: define EXYNOS5_I2C_SPACING

[Simon Glass]

On Thu, Jul 19, 2012 at 12:39 PM, Rajeshwari Shinde
 wrote:
> This patch defined EXYNOS5_I2C_SPACING used to calculate I2C channel
> base address.
>
> Signed-off-by: Rajeshwari Shinde 

Acked-by: Simon Glass 

> ---
> Changes in V6:
> - New patch.
>  arch/arm/include/asm/arch-exynos/cpu.h |2 ++
>  1 files changed, 2 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-exynos/cpu.h 
> b/arch/arm/include/asm/arch-exynos/cpu.h
> index ab46b70..0e6ea87 100644
> --- a/arch/arm/include/asm/arch-exynos/cpu.h
> +++ b/arch/arm/include/asm/arch-exynos/cpu.h
> @@ -58,6 +58,8 @@
>  #define EXYNOS4_GPIO_PART4_BASEDEVICE_NOT_AVAILABLE
>
>  /* EXYNOS5 */
> +#define EXYNOS5_I2C_SPACING0x1
> +
>  #define EXYNOS5_GPIO_PART4_BASE0x0386
>  #define EXYNOS5_PRO_ID 0x1000
>  #define EXYNOS5_CLOCK_BASE 0x1001
> --
> 1.7.4.4
>
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Re: [U-Boot] [PATCH 6/8 V6] I2C: Modify the I2C driver for EXYNOS5

[Simon Glass]

On Thu, Jul 19, 2012 at 12:39 PM, Rajeshwari Shinde
 wrote:
> This patch modifies the S3C I2C driver to suppport EXYNOS5.
> The cahnges made to driver are as follows:
> - I2C base address is passed as a parameter to many
> functions to avoid multiple #ifdef
> - Channel initialisation is moved to a commom funation
> as it is required by i2c_init.
> - Hardcoding for I2CCON_ACKGEN removed.
> - Replaced printf with debug.
> - Checkpatch issues resolved.
> - Pinmux setting will be done in board/samsung/smdk5250/smdk5250.c
> to avoid repeated setting of gpio lines, as it have multi bus support.
>
> Signed-off-by: Alim Akhtar 
> Signed-off-by: Doug Anderson 
> Signed-off-by: Rajeshwari Shinde 
> Acked-by: Simon Glass 

I think this is reasonable thank you.

Acked-by: Simon Glass 

> ---
> Changes in V2:
> - Removed #define for I2C cahnnels from hearder file except for I2C0.
> - Incorporated review comments from Simon Glass.
> Changes in V3:
> - Incorporated review comments from Joonyoung Shim.
> - Reduced the number of #ifdef by modifying get_i2c_base function.
> - Removed duplicate code.
> Changes in V4:
> - Resolved build error for s3c2410.
> Changes in V5:
> - Pinmux setting will be done in board/samsung/smdk5250/smdk5250.c
>   to avoid repeated setting of gpio lines, as it have multi bus 
> support.
> - I2C bus offset calulation done based on EXYNOS_I2C_SPACING
> - Peripharal related code removed.
> Changes in V6:
> - g_current_bus made common to all platforms.
>  drivers/i2c/s3c24x0_i2c.c |  193 +++-
>  1 files changed, 118 insertions(+), 75 deletions(-)
>
> diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c
> index ba6f39b..421c7dd 100644
> --- a/drivers/i2c/s3c24x0_i2c.c
> +++ b/drivers/i2c/s3c24x0_i2c.c
> @@ -27,10 +27,15 @@
>   */
>
>  #include 
> +#ifdef CONFIG_EXYNOS5
> +#include 
> +#include 
> +#else
>  #include 
> -
> +#endif
>  #include 
>  #include 
> +#include "s3c24x0_i2c.h"
>
>  #ifdef CONFIG_HARD_I2C
>
> @@ -45,6 +50,7 @@
>
>  #define I2CSTAT_BSY0x20/* Busy bit */
>  #define I2CSTAT_NACK   0x01/* Nack bit */
> +#define I2CCON_ACKGEN  0x80/* Acknowledge generation */
>  #define I2CCON_IRPND   0x10/* Interrupt pending bit */
>  #define I2C_MODE_MT0xC0/* Master Transmit Mode */
>  #define I2C_MODE_MR0x80/* Master Receive Mode */
> @@ -53,6 +59,10 @@
>
>  #define I2C_TIMEOUT 1  /* 1 second */
>
> +
> +static unsigned int g_current_bus; /* Stores Current I2C Bus */
> +
> +#ifndef CONFIG_EXYNOS5
>  static int GetI2CSDA(void)
>  {
> struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
> @@ -77,16 +87,17 @@ static void SetI2CSCL(int x)
> struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
>
>  #ifdef CONFIG_S3C2410
> -   writel((readl(&gpio->gpedat) & ~0x4000) | (x & 1) << 14, 
> &gpio->gpedat);
> +   writel((readl(&gpio->gpedat) & ~0x4000) |
> +   (x & 1) << 14, &gpio->gpedat);
>  #endif
>  #ifdef CONFIG_S3C2400
> writel((readl(&gpio->pgdat) & ~0x0040) | (x & 1) << 6, &gpio->pgdat);
>  #endif
>  }
> +#endif
>
> -static int WaitForXfer(void)
> +static int WaitForXfer(struct s3c24x0_i2c *i2c)
>  {
> -   struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c();
> int i;
>
> i = I2C_TIMEOUT * 1;
> @@ -98,35 +109,77 @@ static int WaitForXfer(void)
> return (readl(&i2c->iiccon) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT;
>  }
>
> -static int IsACK(void)
> +static int IsACK(struct s3c24x0_i2c *i2c)
>  {
> -   struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c();
> -
> return !(readl(&i2c->iicstat) & I2CSTAT_NACK);
>  }
>
> -static void ReadWriteByte(void)
> +static void ReadWriteByte(struct s3c24x0_i2c *i2c)
>  {
> -   struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c();
> -
> writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon);
>  }
>
> +static struct s3c24x0_i2c *get_base_i2c(void)
> +{
> +#ifdef CONFIG_EXYNOS5
> +   struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c 
> *)(samsung_get_base_i2c()
> +   + (EXYNOS5_I2C_SPACING
> +   * g_current_bus));
> +   return i2c;
> +#else
> +   return s3c24x0_get_base_i2c();
> +#endif
> +}
> +
> +static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd)
> +{
> +   ulong freq, pres = 16, div;
> +#ifdef CONFIG_EXYNOS5
> +   freq = get_i2c_clk();
> +#else
> +   freq = get_PCLK();
> +#endif
> +   /* calculate prescaler and divisor values */
> +   if ((freq / pres / (16 + 1)) > speed)
> +   /* set prescaler to 512 */
> +   pres = 512;
> +
> +   div = 0;
> +   while ((freq / pres / (div + 1)) > speed)
> +   div++;
> +

Re: [U-Boot] [PATCH 8/8 V6] CONFIG: SMDK5250: I2C: Enable I2C

[Simon Glass]

On Thu, Jul 19, 2012 at 12:40 PM, Rajeshwari Shinde
 wrote:
> This enables I2C support on smdk5250.
> Pinmux setting moved to board file to avoid repeated setting of
> gpio lines.
>
> Signed-off-by: Alim Akhtar 
> Signed-off-by: Doug Anderson 
> Signed-off-by: Rajeshwari Shinde 
> Acked-by: Simon Glass 

Acked-by: Simon Glass 

> ---
> Changes in V2:
> - None
> Changes in V3:
> - None
> Changes in V4:
> - None
> Changes in V5:
> - Pinmux setting of gpio lines moved to board_early_init_f.
> Chnages in V6:
> - EXYNOS_I2C_SPACING moved to cpu.h
> - board_i2c_init compiled only when CONFIG_DRIVER_S3C24X0_I2C is 
> defined.
>  board/samsung/smdk5250/smdk5250.c |   28 +++-
>  include/configs/smdk5250.h|8 
>  2 files changed, 35 insertions(+), 1 deletions(-)
>
> diff --git a/board/samsung/smdk5250/smdk5250.c 
> b/board/samsung/smdk5250/smdk5250.c
> index b593325..12e6e66 100644
> --- a/board/samsung/smdk5250/smdk5250.c
> +++ b/board/samsung/smdk5250/smdk5250.c
> @@ -172,9 +172,35 @@ static int board_uart_init(void)
> return 0;
>  }
>
> +#ifdef CONFIG_DRIVER_S3C24X0_I2C
> +static int board_i2c_init(void)
> +{
> +   int i, err;
> +
> +   for (i = 0; i < CONFIG_MAX_I2C_NUM; i++) {
> +   err = exynos_pinmux_config((PERIPH_ID_I2C0 + i),
> +   PINMUX_FLAG_NONE);
> +   if (err) {
> +   debug("I2C%d not configured\n", (PERIPH_ID_I2C0 + i));
> +   return err;
> +   }
> +   }
> +   return 0;
> +}
> +#endif
> +
>  #ifdef CONFIG_BOARD_EARLY_INIT_F
>  int board_early_init_f(void)
>  {
> -   return board_uart_init();
> +   int err;
> +   err = board_uart_init();
> +   if (err) {
> +   debug("UART init failed\n");
> +   return err;
> +   }
> +#ifdef CONFIG_DRIVER_S3C24X0_I2C
> +   err = board_i2c_init();
> +#endif
> +   return err;
>  }
>  #endif
> diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h
> index c0eaaf8..65dfe9f 100644
> --- a/include/configs/smdk5250.h
> +++ b/include/configs/smdk5250.h
> @@ -198,6 +198,14 @@
>
>  #define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_LOAD_ADDR - 0x100)
>
> +/* I2C */
> +#define CONFIG_HARD_I2C
> +#define CONFIG_CMD_I2C
> +#define CONFIG_SYS_I2C_SPEED   10  /* 100 Kbps */
> +#define CONFIG_DRIVER_S3C24X0_I2C
> +#define CONFIG_I2C_MULTI_BUS
> +#define CONFIG_MAX_I2C_NUM 8
> +
>  /* Ethernet Controllor Driver */
>  #ifdef CONFIG_CMD_NET
>  #define CONFIG_SMC911X
> --
> 1.7.4.4
>
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[U-Boot] [PATCH V3 24/25] imx-common: add i2c.c for bus recovery support

[Troy Kisky]

Signed-off-by: Troy Kisky 

---
v2: do nothing if bus is already idle
print failure message if appropriate
change enable_i2c_clock to enable_i2c_clk
clear non-idle bus before calling bus_i2c_init.
wait .2 seconds for bus to clear before returning error
fix compiler warnings

v3: rename toggle to idle_bus
---
 arch/arm/cpu/armv7/imx-common/Makefile|4 +-
 arch/arm/cpu/armv7/imx-common/i2c.c   |   99 +
 arch/arm/cpu/armv7/mx5/clock.c|   20 ++
 arch/arm/cpu/armv7/mx6/clock.c|   20 ++
 arch/arm/include/asm/arch-mx5/clock.h |1 +
 arch/arm/include/asm/arch-mx6/clock.h |1 +
 arch/arm/include/asm/imx-common/mxc_i2c.h |   42 
 7 files changed, 186 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/cpu/armv7/imx-common/i2c.c
 create mode 100644 arch/arm/include/asm/imx-common/mxc_i2c.h

diff --git a/arch/arm/cpu/armv7/imx-common/Makefile 
b/arch/arm/cpu/armv7/imx-common/Makefile
index 53296fa..bf36be5 100644
--- a/arch/arm/cpu/armv7/imx-common/Makefile
+++ b/arch/arm/cpu/armv7/imx-common/Makefile
@@ -27,7 +27,9 @@ include $(TOPDIR)/config.mk
 
 LIB = $(obj)libimx-common.o
 
-COBJS  = iomux-v3.o timer.o cpu.o speed.o
+COBJS-y= iomux-v3.o timer.o cpu.o speed.o
+COBJS-$(CONFIG_I2C_MXC) += i2c.o
+COBJS  := $(sort $(COBJS-y))
 
 SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS   := $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/arch/arm/cpu/armv7/imx-common/i2c.c 
b/arch/arm/cpu/armv7/imx-common/i2c.c
new file mode 100644
index 000..da2b26f
--- /dev/null
+++ b/arch/arm/cpu/armv7/imx-common/i2c.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright (C) 2012 Boundary Devices Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static int force_idle_bus(void *priv)
+{
+   int i;
+   int sda, scl;
+   ulong elapsed, start_time;
+   struct i2c_pads_info *p = (struct i2c_pads_info *)priv;
+   int ret = 0;
+
+   gpio_direction_input(p->sda.gp);
+   gpio_direction_input(p->scl.gp);
+
+   imx_iomux_v3_setup_pad(p->sda.gpio_mode);
+   imx_iomux_v3_setup_pad(p->scl.gpio_mode);
+
+   sda = gpio_get_value(p->sda.gp);
+   scl = gpio_get_value(p->scl.gp);
+   if ((sda & scl) == 1)
+   goto exit;  /* Bus is idle already */
+
+   printf("%s: sda=%d scl=%d sda.gp=0x%x scl.gp=0x%x\n", __func__,
+   sda, scl, p->sda.gp, p->scl.gp);
+   /* Send high and low on the SCL line */
+   for (i = 0; i < 9; i++) {
+   gpio_direction_output(p->scl.gp, 0);
+   udelay(50);
+   gpio_direction_input(p->scl.gp);
+   udelay(50);
+   }
+   start_time = get_timer(0);
+   for (;;) {
+   sda = gpio_get_value(p->sda.gp);
+   scl = gpio_get_value(p->scl.gp);
+   if ((sda & scl) == 1)
+   break;
+   WATCHDOG_RESET();
+   elapsed = get_timer(start_time);
+   if (elapsed > (CONFIG_SYS_HZ / 5)) {/* .2 seconds */
+   ret = -EBUSY;
+   printf("%s: failed to clear bus, sda=%d scl=%d\n",
+   __func__, sda, scl);
+   break;
+   }
+   }
+exit:
+   imx_iomux_v3_setup_pad(p->sda.i2c_mode);
+   imx_iomux_v3_setup_pad(p->scl.i2c_mode);
+   return ret;
+}
+
+static void * const i2c_bases[] = {
+   (void *)I2C1_BASE_ADDR,
+   (void *)I2C2_BASE_ADDR,
+#ifdef I2C3_BASE_ADDR
+   (void *)I2C3_BASE_ADDR,
+#endif
+};
+
+/* i2c_index can be from 0 - 2 */
+void setup_i2c(unsigned i2c_index, int speed, int slave_addr,
+   struct i2c_pads_info *p)
+{
+   if (i2c_index >= ARRAY_SIZE(i2c_bases))
+   return;
+   /* Enable i2c clock */
+   enable_i2c_clk(1, i2c_index);
+   /* Make sure bus is idle */
+   force_idle_bus(p);
+   bus_i2c_init(i2c_bases[i2c_index], speed, slave_addr,
+   force_idle_bus, p);
+}
diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
index 6

[U-Boot] [PATCH V3 20/25] iomux-v3: remove include of mx6x_pins.h

[Troy Kisky]

This include is not needed.

Signed-off-by: Troy Kisky 

---
v2: no change
---
 arch/arm/cpu/armv7/mx6/iomux-v3.c |1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/mx6/iomux-v3.c 
b/arch/arm/cpu/armv7/mx6/iomux-v3.c
index 8785532..a0c4b15 100644
--- a/arch/arm/cpu/armv7/mx6/iomux-v3.c
+++ b/arch/arm/cpu/armv7/mx6/iomux-v3.c
@@ -23,7 +23,6 @@
 #include 
 #include 
 #include 
-#include 
 #include 
 
 static void *base = (void *)IOMUXC_BASE_ADDR;
-- 
1.7.9.5

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[U-Boot] [PATCH V3 11/25] mxc_i2c: place i2c_reset code inline

[Troy Kisky]

imx_reset is only referenced once so
move to that location.

Signed-off-by: Troy Kisky 
Acked-by: Marek Vasut 

---
v2: add ack
---
 drivers/i2c/mxc_i2c.c |   15 +++
 1 file changed, 3 insertions(+), 12 deletions(-)

diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 9efa9bd..717bc7a 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -114,17 +114,6 @@ static uint8_t i2c_imx_get_clk(unsigned int rate)
 }
 
 /*
- * Reset I2C Controller
- */
-void i2c_reset(void)
-{
-   struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
-
-   writeb(0, &i2c_regs->i2cr); /* Reset module */
-   writeb(0, &i2c_regs->i2sr);
-}
-
-/*
  * Init I2C Bus
  */
 void i2c_init(int speed, int unused)
@@ -136,7 +125,9 @@ void i2c_init(int speed, int unused)
/* Store divider value */
writeb(idx, &i2c_regs->ifdr);
 
-   i2c_reset();
+   /* Reset module */
+   writeb(0, &i2c_regs->i2cr);
+   writeb(0, &i2c_regs->i2sr);
 }
 
 /*
-- 
1.7.9.5

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