[U-Boot] [PATCH] EXYNOS5: GPIO: fix wrong gpio bank offset
res1[] size is wrong.
It didn't consider the s5p_gpio_bank size.
Signed-off-by: Jaehoon Chung
Signed-off-by: Kyungmin Park
---
arch/arm/include/asm/arch-exynos/gpio.h |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h
b/arch/arm/include/asm/arch-exynos/gpio.h
index 7a9bb90..9f22b5c 100644
--- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -100,7 +100,7 @@ struct exynos5_gpio_part1 {
struct s5p_gpio_bank y4;
struct s5p_gpio_bank y5;
struct s5p_gpio_bank y6;
- struct s5p_gpio_bank res1[0x980];
+ struct s5p_gpio_bank res1[76];
struct s5p_gpio_bank x0;
struct s5p_gpio_bank x1;
struct s5p_gpio_bank x2;
@@ -124,7 +124,7 @@ struct exynos5_gpio_part3 {
struct s5p_gpio_bank v1;
struct s5p_gpio_bank v2;
struct s5p_gpio_bank v3;
- struct s5p_gpio_bank res1[0x20];
+ struct s5p_gpio_bank res1[2];
struct s5p_gpio_bank v4;
};
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Re: [U-Boot] [PATCH] EXYNOS: PINMUX: modify the gpio function value for mmc
Hi Rajeshwari,
I just considered the EVT1 board.
I will resend the patch for this.
Best Regards,
Jaehoon Chung
On 06/20/2012 02:55 PM, Rajeshwari Birje wrote:
> Hi Jaehoon Chung,
>
> Had few comments...
>
> Is this changes for EVT1 board?
> As per the EVT1 Manual I have it is:
> MMC0: Correct as per your changes.
> MMC1: Bank C2 - 4 bit: func - 0x2
> MMC2: Bank C3 - 4 bit: func - 0x2, You have made it 8 bit. (EVT0 the
> manual I have it says func 0x2)
> MMC3 not there.
>
> On Wed, Jun 20, 2012 at 10:31 AM, Jaehoon Chung
> wrote:
>> In Exynos5, if used 8-bit busmode, set the gpio configuration to
>> GPIO_FUNC(0x2).
>>
>> Signed-off-by: Jaehoon Chung
>> Signed-off-by: Kyungmin Park
>> ---
>> arch/arm/cpu/armv7/exynos/pinmux.c | 20 +++-
>> 1 files changed, 11 insertions(+), 9 deletions(-)
>>
>> diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c
>> b/arch/arm/cpu/armv7/exynos/pinmux.c
>> index d2b7d2c..356cf8d 100644
>> --- a/arch/arm/cpu/armv7/exynos/pinmux.c
>> +++ b/arch/arm/cpu/armv7/exynos/pinmux.c
>> @@ -66,12 +66,14 @@ static int exynos5_mmc_config(int peripheral, int flags)
>>struct exynos5_gpio_part1 *gpio1 =
>>(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
>>struct s5p_gpio_bank *bank, *bank_ext;
>> - int i;
>> + int i, gpio_func, gpio_start;
>>
>>switch (peripheral) {
>>case PERIPH_ID_SDMMC0:
>>bank = &gpio1->c0;
>>bank_ext = &gpio1->c1;
>> + gpio_func = GPIO_FUNC(0x2);
>> + gpio_start = 0;
>>break;
>>case PERIPH_ID_SDMMC1:
>>bank = &gpio1->c1;
>> @@ -80,6 +82,8 @@ static int exynos5_mmc_config(int peripheral, int flags)
>>case PERIPH_ID_SDMMC2:
>>bank = &gpio1->c2;
>>bank_ext = &gpio1->c3;
>> + gpio_func = GPIO_FUNC(0x3);
>> + gpio_start = 3;
>>break;
>>case PERIPH_ID_SDMMC3:
>>bank = &gpio1->c3;
>> @@ -92,18 +96,16 @@ static int exynos5_mmc_config(int peripheral, int flags)
>>return -1;
>>}
>>if (flags & PINMUX_FLAG_8BIT_MODE) {
>> - for (i = 3; i <= 6; i++) {
>> - s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3));
>> + for (i = gpio_start; i <= gpio_start + 3; i++) {
>> + s5p_gpio_cfg_pin(bank_ext, i, gpio_func);
>>s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
>>s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
>>}
>>}
>> - for (i = 0; i < 2; i++) {
>> - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
>> - s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
>> - s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
>> - }
>> - for (i = 3; i <= 6; i++) {
>> +
>> + for (i = 0; i <= 6; i++) {
>> + if (i == 2)
>> + continue;
>>s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
>>s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
> --- Do we have to pull up for CMD, and CLK gpio ?
> -- CD line not set?
>>s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
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Re: [U-Boot] [PATCH] fix IDE_BUS(dev) macro
Sorry Luka (and all), been tied up pretty heavily recently, had to adjust to find some free time again. I will test your patch today and post results tonight. 2012/6/7 Luka Perkov > > Hi Albert, > > On Tue, May 15, 2012 at 09:42:59PM +0200, Albert ARIBAUD wrote: > > >On Sun, Apr 29, 2012 at 10:19:41PM +0200, Luka Perkov wrote: > > >>On Thu, Apr 19, 2012 at 08:38:19AM +0200, Albert ARIBAUD wrote: > > >>>Not my main area of expertise here, but I am not sure how this plays > > >>>on Marvell non-kirkwood platforms (e.g., orion5x). > > >>> > > >>>ISTR it is not the first time we deal with the whole IDE number of > > >>>bus / number of ports [ / useable ports ] issue, and we may be > > >>>running in circles here, fixing one platform and breaking another. > > >>> > > >>>I'll try this on EDMiniV2 in the coming days, and let people know > > >>>the results in this thread. > > >> > > >>I was just wondering did you have the time to test this patch on your > > >>board? > > > > > >Albert, did you maybe have time to test this patch. I have included it > > >bellow so you dont have to search for it... > > > > > >Signed-off-by: Simon Baatz > > >Tested-by: Luka Perkov > > >--- > > > > > >Simon discovered this while adding support for new board IB NAS6210. > > > > > >More info can be found here: > > > > > >http://lists.denx.de/pipermail/u-boot/2012-April/122525.html > > > > > > include/ide.h | 2 +- > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > >diff --git a/include/ide.h b/include/ide.h > > >index 8ecc9dd..385e909 100644 > > >--- a/include/ide.h > > >+++ b/include/ide.h > > >@@ -24,7 +24,7 @@ > > > #ifndef _IDE_H > > > #define _IDE_H > > > > > >-#define IDE_BUS(dev) (dev>> 1) > > >+#define IDE_BUS(dev) (dev / (CONFIG_SYS_IDE_MAXDEVICE / > > >CONFIG_SYS_IDE_MAXBUS)) > > > > > > #define ATA_CURR_BASE(dev) > > > (CONFIG_SYS_ATA_BASE_ADDR+ide_bus_offset[IDE_BUS(dev)]) > > > > Sorry, been busier than usual. I'll try and test this tomorrow > > night; if not, that'll be next week I'm afraid. > > It's me beeing boring again, sorry... Can we get your feedback on this one? > > Regards, > Luka > Amicalement, Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 6/8 V4] I2C: Modify the I2C driver for EXYNOS5
Dear Rajeshwari Birje, On 19 June 2012 19:57, Rajeshwari Birje wrote: > Hi Joonyoung Shim, > > On Tue, Jun 19, 2012 at 1:20 PM, Joonyoung Shim wrote: >> Hi, >> >> I add some comments at the below. >> > -- ok >> And current SMDK5250 uses Exynos5250 EVT0 base codes, >> but i know the kernel supports only Exynos5250 EVT1. >> >> So, let's remove Exynos5250 EVT0 codes and add EVT1 codes at the u-boot also. >> Could you follow up it? >> > -- Yes currently we are working on that So.. do you need to support EVT0? or not? We want to support EVT1 codes only. (without EVT0) Thanks. Minkyu Kang. -- from. prom. www.promsoft.net ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 6/8 V4] I2C: Modify the I2C driver for EXYNOS5
Hi Minkyu Kang, This being I2C driver code should not have any dependency on EVT0 or EVT1. Regards, Rajeshwari Shinde. On Wed, Jun 20, 2012 at 2:01 PM, Minkyu Kang wrote: > Dear Rajeshwari Birje, > > On 19 June 2012 19:57, Rajeshwari Birje wrote: >> Hi Joonyoung Shim, >> >> On Tue, Jun 19, 2012 at 1:20 PM, Joonyoung Shim wrote: >>> Hi, >>> >>> I add some comments at the below. >>> >> -- ok >>> And current SMDK5250 uses Exynos5250 EVT0 base codes, >>> but i know the kernel supports only Exynos5250 EVT1. >>> >>> So, let's remove Exynos5250 EVT0 codes and add EVT1 codes at the u-boot >>> also. >>> Could you follow up it? >>> >> -- Yes currently we are working on that > > So.. do you need to support EVT0? or not? > We want to support EVT1 codes only. (without EVT0) > > Thanks. > Minkyu Kang. > -- > from. prom. > www.promsoft.net ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 2/2] hush.c: Move default CONFIG_SYS_PROMPT_HUSH_PS2 to hush.c
On 20/06/2012 00:54, Tom Rini wrote: > Exactly one board has defined CONFIG_SYS_PROMPT_HUSH_PS2 to a value > different than "> " which is vision2. I have Cc'd the maintainer here > as I strongly suspect this is a bug rather than intentional behavior. > > Cc: Stefano Babic > Signed-off-by: Tom Rini > > --- > Changes in v4: > - Rebase to current master > --- Acked-by: Stefano Babic Best regards, Stefano -- = DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 1/1] tegra: usb: Fix device enumeration problem of USB1
A known hardware issue of USB1 port where bit 1 (connect status
change) of PORTSC register will be set after issuing Port Reset
(like "usb reset" in u-boot command line).
This will be treated as an error and stops later device enumeration.
Therefore we clear that bit after Port Reset in order to proceed
later device enumeration.
Signed-off-by: Jim Lin
---
To reproduce this issue, you can modify board .dts file to set
as the following to build u-boot binary.
"
usb0 = "/usb@c500";
usb1 = "/usb@c5008000";
"
Install device on USB1 port (address at 0xc500).
And run "usb reset" in u-boot console to enumerate device.
Before adding this patch, we could see problem every time.
After adding, tried 10 times of "usb reset", "usb tree", "usb stop"
, without seeing issue.
Changes in v3:
- Move patch for USB1 controller into ehci_powerup_fixup of ehci-tegra.c
- Update copyright year to 2012
Changes in v2:
- Change config name
- Add a callback function at the end of ehci_submit_root() function
drivers/usb/host/ehci-tegra.c | 19 ++-
1 files changed, 18 insertions(+), 1 deletions(-)
diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
index a7e105b..8e516e5 100644
--- a/drivers/usb/host/ehci-tegra.c
+++ b/drivers/usb/host/ehci-tegra.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2009 NVIDIA Corporation
+ * Copyright (c) 2009-2012 NVIDIA Corporation
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -29,6 +29,23 @@
#include
#include
+/*
+ * A known hardware issue where Connect Status Change bit of PORTSC register
+ * of USB1 controller will be set after Port Reset.
+ * We have to clear it in order for later device enumeration to proceed.
+ */
+void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
+{
+ uint32_t my_reg;
+
+ mdelay(50);
+ if (((u32) status_reg & 0xC000) != TEGRA_USB1_BASE)
+ return;
+ my_reg = ehci_readl(status_reg);
+ /* For EHCI_PS_CSC to be cleared in ehci_hcd.c */
+ if (my_reg & EHCI_PS_CSC)
+ *reg |= EHCI_PS_CSC;
+}
/*
* Create the appropriate control structures to manage
--
1.7.3
nvpublic
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Re: [U-Boot] [PATCH v2 3/7] da850/omap-l138: Add support to read u-boot image from MMC/SD
Hi Prabhakar,
On Tue, Jun 19, 2012 at 7:06 AM, Lad, Prabhakar wrote:
> Hi Christian,
>
> On Tue, Jun 19, 2012 at 01:09:08, Christian Riesch wrote:
>> Hi,
>> Sorry for the delay, had a lot of other work to do :-/
>>
>> On Thursday, June 7, 2012, Prabhakar Lad wrote:
>>
>>
>> From: Lad, Prabhakar >
>>
>> DA850/OMAP-L138 does not support strict MMC/SD boot mode. SPL will
>> be in SPI flash and U-Boot image will be in MMC/SD card. SPL will
>> do the low level initialization and then loads the u-boot image
>> from MMC/SD card.
>>
>> Define the CONFIG_SPL_MMC_LOAD macro in the DA850/OMAP-L138
>> configuration file to enable this feature.
>>
>> Signed-off-by: Lad, Prabhakar >
>> Signed-off-by: Rajashekhara, Sudhakar > >
>> Signed-off-by: Hadli, Manjunath
>> >
>> ---
>> arch/arm/cpu/arm926ejs/davinci/spl.c | 12 ++-
>> drivers/mmc/Makefile | 4 ++
>> drivers/mmc/spl_mmc_load.c | 62
>> ++
>> include/configs/da850evm.h | 8
>> include/mmc.h | 2 +
>> 5 files changed, 87 insertions(+), 1 deletions(-)
>> create mode 100644 drivers/mmc/spl_mmc_load.c
>>
>> diff --git a/arch/arm/cpu/arm926ejs/davinci/spl.c
>> b/arch/arm/cpu/arm926ejs/davinci/spl.c
>> index 74632e5..be397ce 100644
>> --- a/arch/arm/cpu/arm926ejs/davinci/spl.c
>> +++ b/arch/arm/cpu/arm926ejs/davinci/spl.c
>> @@ -28,6 +28,11 @@
>> #include
>> #include
>> #include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>>
>> #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
>>
>> @@ -91,6 +96,11 @@ void board_init_r(gd_t *id, ulong dummy)
>> gd->have_console = 1;
>>
>> puts("SPI boot...\n");
>> +#ifdef CONFIG_SPL_MMC_LOAD
>> + spl_mmc_load();
>> +#else
>> spi_boot();
>> -#endif
>>
>>
>> Hmm, now the code prints "SPI boot" and then it boots from MMC, right?
>> Please output correct messages.
>>
> The board is booted up in SPI boot mode only, ie the SPL is loaded from
> SPI flash itself and finally when low level initialization is completed
> The SPL loads the U-boot image in MMC/SD card when CONFIG_SPL_MMC_LOAD
> Config is defined. If CONFIG_SPL_MMC_LOAD is not defined by default the
> SPL loads the U-boot image from SPI flash itself.
Yes, but your code prints "SPI boot" for both cases, doesn't it?
>>
>> +#endif /* CONFIG_SPL_MMC_LOAD */
>> +
>> +#endif /* CONFIG_SPL_SPI_LOAD */
>>
>>
>> So, CONFIG_SPL_SPI_LOAD must be defined to boot from MMC?? Ths does not make
>> sense to me.
>
> No not to boot from MMC, its indicating to SPL which is flashed in
> SPI flash to load the U-boot image(u-boot.bin) from MMC.
Yes, but your code requires both CONFIG_SPL_MMC_LOAD and
CONFIG_SPL_SPI_LOAD to be defined to load u-boot from MMC, right? This
is confusing.
Of course SPL itself is loaded from SPI flash in both cases, but this
does not matter here, since the SPL has already loaded to the internal
SRAM of the SoC by the ROM bootloader of the chip. The SPL could have
been loaded from some other kind of memory (or UART) as well and would
not know the difference.
Regards, Christian
>
> Thx,
> --Prabhakar Lad
>
>>
>> Regards, Christian
>>
>
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Re: [U-Boot] [PATCH 6/8 V4] I2C: Modify the I2C driver for EXYNOS5
2012/6/20 Rajeshwari Birje : > Hi Minkyu Kang, > > This being I2C driver code should not have any dependency on EVT0 or EVT1. I mean *all* arch and driver codes for Exynos5250 should support EVT1 only. Thanks. > > Regards, > Rajeshwari Shinde. > > On Wed, Jun 20, 2012 at 2:01 PM, Minkyu Kang wrote: >> Dear Rajeshwari Birje, >> >> On 19 June 2012 19:57, Rajeshwari Birje wrote: >>> Hi Joonyoung Shim, >>> >>> On Tue, Jun 19, 2012 at 1:20 PM, Joonyoung Shim wrote: Hi, I add some comments at the below. >>> -- ok And current SMDK5250 uses Exynos5250 EVT0 base codes, but i know the kernel supports only Exynos5250 EVT1. So, let's remove Exynos5250 EVT0 codes and add EVT1 codes at the u-boot also. Could you follow up it? >>> -- Yes currently we are working on that >> >> So.. do you need to support EVT0? or not? >> We want to support EVT1 codes only. (without EVT0) >> >> Thanks. >> Minkyu Kang. >> -- >> from. prom. >> www.promsoft.net -- - Joonyoung Shim ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 3/7] da850/omap-l138: Add support to read u-boot image from MMC/SD
Hi Christian,
On Wed, Jun 20, 2012 at 14:50:41, Christian Riesch wrote:
> Hi Prabhakar,
>
> On Tue, Jun 19, 2012 at 7:06 AM, Lad, Prabhakar wrote:
> > Hi Christian,
> >
> > On Tue, Jun 19, 2012 at 01:09:08, Christian Riesch wrote:
> >> Hi,
> >> Sorry for the delay, had a lot of other work to do :-/
> >>
> >> On Thursday, June 7, 2012, Prabhakar Lad wrote:
> >>
> >>
> >> From: Lad, Prabhakar >
> >>
> >> DA850/OMAP-L138 does not support strict MMC/SD boot mode. SPL will
> >> be in SPI flash and U-Boot image will be in MMC/SD card. SPL will
> >> do the low level initialization and then loads the u-boot image
> >> from MMC/SD card.
> >>
> >> Define the CONFIG_SPL_MMC_LOAD macro in the DA850/OMAP-L138
> >> configuration file to enable this feature.
> >>
> >> Signed-off-by: Lad, Prabhakar >
> >> Signed-off-by: Rajashekhara, Sudhakar >> >
> >> Signed-off-by: Hadli, Manjunath >> >
> >> ---
> >> arch/arm/cpu/arm926ejs/davinci/spl.c | 12 ++-
> >> drivers/mmc/Makefile | 4 ++
> >> drivers/mmc/spl_mmc_load.c | 62
> >> ++
> >> include/configs/da850evm.h | 8
> >> include/mmc.h | 2 +
> >> 5 files changed, 87 insertions(+), 1 deletions(-)
> >> create mode 100644 drivers/mmc/spl_mmc_load.c
> >>
> >> diff --git a/arch/arm/cpu/arm926ejs/davinci/spl.c
> >> b/arch/arm/cpu/arm926ejs/davinci/spl.c
> >> index 74632e5..be397ce 100644
> >> --- a/arch/arm/cpu/arm926ejs/davinci/spl.c
> >> +++ b/arch/arm/cpu/arm926ejs/davinci/spl.c
> >> @@ -28,6 +28,11 @@
> >> #include
> >> #include
> >> #include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >> +#include
> >>
> >> #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
> >>
> >> @@ -91,6 +96,11 @@ void board_init_r(gd_t *id, ulong dummy)
> >> gd->have_console = 1;
> >>
> >> puts("SPI boot...\n");
> >> +#ifdef CONFIG_SPL_MMC_LOAD
> >> + spl_mmc_load();
> >> +#else
> >> spi_boot();
> >> -#endif
> >>
> >>
> >> Hmm, now the code prints "SPI boot" and then it boots from MMC, right?
> >> Please output correct messages.
> >>
Ok
> > The board is booted up in SPI boot mode only, ie the SPL is loaded from
> > SPI flash itself and finally when low level initialization is completed
> > The SPL loads the U-boot image in MMC/SD card when CONFIG_SPL_MMC_LOAD
> > Config is defined. If CONFIG_SPL_MMC_LOAD is not defined by default the
> > SPL loads the U-boot image from SPI flash itself.
>
> Yes, but your code prints "SPI boot" for both cases, doesn't it?
>
> >>
> >> +#endif /* CONFIG_SPL_MMC_LOAD */
> >> +
> >> +#endif /* CONFIG_SPL_SPI_LOAD */
> >>
> >>
> >> So, CONFIG_SPL_SPI_LOAD must be defined to boot from MMC?? Ths does not
> >> make sense to me.
> >
> > No not to boot from MMC, its indicating to SPL which is flashed in
> > SPI flash to load the U-boot image(u-boot.bin) from MMC.
>
> Yes, but your code requires both CONFIG_SPL_MMC_LOAD and
> CONFIG_SPL_SPI_LOAD to be defined to load u-boot from MMC, right? This
> is confusing.
>
> Of course SPL itself is loaded from SPI flash in both cases, but this
> does not matter here, since the SPL has already loaded to the internal
> SRAM of the SoC by the ROM bootloader of the chip. The SPL could have
> been loaded from some other kind of memory (or UART) as well and would
> not know the difference.
Ok I'll use CONFIG_SPL_MMC_LOAD while loading from MMC. I'll incorporate
These changes for v3.
Thx,
--Prabhakar Lad
>
> Regards, Christian
>
> >
> > Thx,
> > --Prabhakar Lad
> >
> >>
> >> Regards, Christian
> >>
> >
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[U-Boot] [PATCH 0/9]EXYNOS5: Support for Exynos5250 Rev 1.0
This patch set adds support for Exynos5250 Rev 1.0. Exynos5250 Rev 1.0 supports DDR3 Memory configuration and support for LPDDR2 is removed. Exynos5250 Rev 1.0 supports DWMMC driver but the support for same is not yet gone into Mainline. After DWMMC driver is added to Mainline support for generic S5P MMC driver will be removed. Due to Support of generic S5P MMC driver currently still being there in the Mainline you can see the following error on boot. mmc_reset: timeout error mmc_change_clock: timeout error mmc_send_cmd: waiting for status update MMC init failed Rajeshwari Shinde (9): ARCH: SPL: Add parametric board initializer SMDK5250: SPL: Define parametric board initializer SMDK5250: Add smdk5250-uboot-spl.lds EXYNOS5: CLOCK: define additional clock registers for Exynos5250 Rev 1.0 EXYNOS5: CLOCK: Add clock support for Exynos5250 Rev 1.0 Exynos5: DDR3: Adding the DDR3 memory setup for Exynos5250 Rev 1.0 EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0 EXYNOS5 : Modify pinnumx settings as per Exynos5250 Rev 1.0 SMDK5250: Enable UART and MMC for Exynos5250 Rev 1.0 arch/arm/cpu/armv7/exynos/clock.c | 12 +- arch/arm/cpu/armv7/exynos/pinmux.c| 18 +- arch/arm/include/asm/arch-exynos/clock.h | 37 +- arch/arm/include/asm/arch-exynos/dmc.h| 65 +++ arch/arm/include/asm/arch-exynos/spl.h| 95 +++ board/samsung/smdk5250/Makefile |3 +- board/samsung/smdk5250/clock_init.c | 714 +++ board/samsung/smdk5250/clock_init.h | 149 + board/samsung/smdk5250/dmc_common.c | 199 +++ board/samsung/smdk5250/dmc_init.c | 462 --- board/samsung/smdk5250/dmc_init_ddr3.c| 228 board/samsung/smdk5250/setup.h| 765 +++-- board/samsung/smdk5250/smdk5250-uboot-spl.lds | 66 +++ board/samsung/smdk5250/smdk5250.c |6 +- board/samsung/smdk5250/smdk5250_spl.c | 68 +++ include/configs/smdk5250.h|7 +- 16 files changed, 1968 insertions(+), 926 deletions(-) create mode 100644 arch/arm/include/asm/arch-exynos/spl.h create mode 100644 board/samsung/smdk5250/clock_init.h create mode 100644 board/samsung/smdk5250/dmc_common.c delete mode 100644 board/samsung/smdk5250/dmc_init.c create mode 100644 board/samsung/smdk5250/dmc_init_ddr3.c create mode 100644 board/samsung/smdk5250/smdk5250-uboot-spl.lds create mode 100644 board/samsung/smdk5250/smdk5250_spl.c -- 1.7.4.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/9] ARCH: SPL: Add parametric board initializer
Add a structure for table-driven configuration mechanism such that no
recompilation
is needed to update the configuration parameters, rather than hard-coding
board initialization parameters.
Signed-off-by: Che-Liang Chiou
Signed-off-by: Abhilash Kesavan
Signed-off-by: Tom Wai-Hong Tam
Signed-off-by: Simon Glass
Signed-off-by: Rajeshwari Shinde
---
arch/arm/include/asm/arch-exynos/spl.h | 95
1 files changed, 95 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/include/asm/arch-exynos/spl.h
diff --git a/arch/arm/include/asm/arch-exynos/spl.h
b/arch/arm/include/asm/arch-exynos/spl.h
new file mode 100644
index 000..1d79239
--- /dev/null
+++ b/arch/arm/include/asm/arch-exynos/spl.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_EXYNOS_SPL_H__
+#define __ASM_ARCH_EXYNOS_SPL_H__
+
+#include
+
+enum boot_mode {
+ /*
+* Assign the OM pin values for respective boot modes.
+* Exynos4 does not support spi boot and the mmc boot OM
+* pin values are the same across Exynos4 and Exynos5.
+*/
+ BOOT_MODE_MMC = 4,
+ BOOT_MODE_SERIAL = 20,
+ /* Boot based on Operating Mode pin settings */
+ BOOT_MODE_OM = 32,
+ BOOT_MODE_USB, /* Boot using USB download */
+};
+
+/* Parameters of early board initialization in SPL */
+struct spl_machine_param {
+ /* Add fields as and when required */
+ u32 signature;
+ u32 version;/* Version number */
+ u32 size; /* Size of block */
+ /**
+* Parameters we expect, in order, terminated with \0. Each parameter
+* is a single character representing one 32-bit word in this
+* structure.
+*
+* Valid characters in this string are:
+*
+* Code Name
+* vmem_iv_size
+* mmem_type
+* uuboot_size
+* bboot_source
+* ffrequency_mhz (memory frequency in MHz)
+* aARM clock frequency in MHz
+* sserial base address
+* ii2c base address for early access (meant for PMIC)
+* rboard rev GPIO numbers used to read board revision
+* (lower halfword=bit 0, upper=bit 1)
+* MMemory Manufacturer name
+* \0 termination
+*/
+ charparams[12]; /* Length must be word-aligned */
+ u32 mem_iv_size;/* Memory channel interleaving size */
+ enum ddr_mode mem_type; /* Type of on-board memory */
+ /*
+* U-boot size - The iROM mmc copy function used by the SPL takes a
+* block count paramter to describe the u-boot size unlike the spi
+* boot copy function which just uses the u-boot size directly. Align
+* the u-boot size to block size (512 bytes) when populating the SPL
+* table only for mmc boot.
+*/
+ u32 uboot_size;
+ enum boot_mode boot_source;/* Boot device */
+ enum mem_manuf mem_manuf; /* Memory Manufacturer */
+ unsignedfrequency_mhz; /* Frequency of memory in MHz */
+ unsignedarm_freq_mhz; /* ARM Frequency in MHz */
+ u32 serial_base;/* Serial base address */
+ u32 i2c_base; /* i2c base address */
+} __attribute__((__packed__));
+
+/**
+ * Validate signature and return a pointer to the parameter table. If the
+ * signature is invalid, call panic() and never return.
+ *
+ * @return pointer to the parameter table if signature matched or never return.
+ */
+struct spl_machine_param *spl_get_machine_params(void);
+
+#endif /* __ASM_ARCH_EXYNOS_SPL_H__ */
--
1.7.4.4
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[U-Boot] [PATCH 2/9] SMDK5250: SPL: Define parametric board initializer
Define table-driven configuration mechanism for SMDK5250
rather than hard-coding board initialization parameters.
Signed-off-by: Che-Liang Chiou
Signed-off-by: Abhilash Kesavan
Signed-off-by: Tom Wai-Hong Tam
Signed-off-by: Simon Glass
Signed-off-by: Rajeshwari Shinde
---
board/samsung/smdk5250/Makefile |1 +
board/samsung/smdk5250/smdk5250_spl.c | 68 +
2 files changed, 69 insertions(+), 0 deletions(-)
create mode 100644 board/samsung/smdk5250/smdk5250_spl.c
diff --git a/board/samsung/smdk5250/Makefile b/board/samsung/smdk5250/Makefile
index 226db1f..3675fad 100644
--- a/board/samsung/smdk5250/Makefile
+++ b/board/samsung/smdk5250/Makefile
@@ -29,6 +29,7 @@ SOBJS := lowlevel_init.o
COBJS := clock_init.o
COBJS += dmc_init.o
COBJS += tzpc_init.o
+COBJS += smdk5250_spl.o
ifndef CONFIG_SPL_BUILD
COBJS += smdk5250.o
diff --git a/board/samsung/smdk5250/smdk5250_spl.c
b/board/samsung/smdk5250/smdk5250_spl.c
new file mode 100644
index 000..1d453ca
--- /dev/null
+++ b/board/samsung/smdk5250/smdk5250_spl.c
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+#include
+#include
+#include
+
+#define SIGNATURE 0xdeadbeef
+
+/* Parameters of early board initialization in SPL */
+static struct spl_machine_param machine_param
+ __attribute__((section(".machine_param"))) = {
+ .signature = SIGNATURE,
+ .version= 1,
+ .params = "vmubfasirM",
+ .size = sizeof(machine_param),
+
+ .mem_iv_size= 0x1f,
+ .mem_type = DDR_MODE_DDR3,
+
+ /*
+* Set uboot_size to 0x10 bytes.
+*
+* This is an overly conservative value chosen to accommodate all
+* possible U-Boot image. You are advised to set this value to a
+* smaller realistic size via scripts that modifies the .machine_param
+* section of output U-Boot image.
+*/
+ .uboot_size = 0x10,
+
+ .boot_source= BOOT_MODE_OM,
+ .frequency_mhz = 800,
+ .arm_freq_mhz = 1700,
+ .serial_base= 0x12c3,
+ .i2c_base = 0x12c6,
+ .mem_manuf = MEM_MANUF_SAMSUNG,
+};
+
+struct spl_machine_param *spl_get_machine_params(void)
+{
+ if (machine_param.signature != SIGNATURE) {
+ /* Will hang if SIGNATURE dont match */
+ while (1)
+ ;
+ }
+
+ return &machine_param;
+}
--
1.7.4.4
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[U-Boot] [PATCH 4/9] EXYNOS5: CLOCK: define additional clock registers for Exynos5250 Rev 1.0
Define additional registers for clock control in Exynos5250 Rev 1.0
Signed-off-by: Hatim Ali
Signed-off-by: Rajeshwari Shinde
---
arch/arm/include/asm/arch-exynos/clock.h | 36 +
1 files changed, 26 insertions(+), 10 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/clock.h
b/arch/arm/include/asm/arch-exynos/clock.h
index 50da958..7cc3d5e 100644
--- a/arch/arm/include/asm/arch-exynos/clock.h
+++ b/arch/arm/include/asm/arch-exynos/clock.h
@@ -272,7 +272,7 @@ struct exynos5_clock {
unsigned intclkout_cmu_cpu;
unsigned intclkout_cmu_cpu_div_stat;
unsigned char res8[0x5f8];
- unsigned intarmclk_stopctrl;
+ unsigned intarmclk_stopctrl;/* base + 0x1000 */
unsigned intatclk_stopctrl;
unsigned char res9[0x8];
unsigned intparityfail_status;
@@ -323,10 +323,12 @@ struct exynos5_clock {
unsigned char res19[0xf8];
unsigned intdiv_core0;
unsigned intdiv_core1;
- unsigned char res20[0xf8];
+ unsigned intdiv_sysrgt;
+ unsigned char res20[0xf4];
unsigned intdiv_stat_core0;
unsigned intdiv_stat_core1;
- unsigned char res21[0x2f8];
+ unsigned intdiv_stat_sysrgt;
+ unsigned char res21[0x2f4];
unsigned intgate_ip_core;
unsigned char res22[0xfc];
unsigned intclkout_cmu_core;
@@ -352,7 +354,11 @@ struct exynos5_clock {
unsigned intdiv_stat_acp;
unsigned char res30[0x1fc];
unsigned intgate_ip_acp;
- unsigned char res31[0x1fc];
+ unsigned char res31a[0xfc];
+ unsigned intdiv_syslft;
+ unsigned char res31b[0xc];
+ unsigned intdiv_stat_syslft;
+ unsigned char res31c[0xec];
unsigned intclkout_cmu_acp;
unsigned intclkout_cmu_acp_div_stat;
unsigned char res32[0x38f8];
@@ -379,7 +385,9 @@ struct exynos5_clock {
unsigned intepll_lock;
unsigned char res40[0xc];
unsigned intvpll_lock;
- unsigned char res41[0xdc];
+ unsigned char res41a[0xc];
+ unsigned intgpll_lock;
+ unsigned char res41b[0xcc];
unsigned intcpll_con0;
unsigned intcpll_con1;
unsigned char res42[0x8];
@@ -390,7 +398,10 @@ struct exynos5_clock {
unsigned intvpll_con0;
unsigned intvpll_con1;
unsigned intvpll_con2;
- unsigned char res44[0xc4];
+ unsigned char res44a[0x4];
+ unsigned intgpll_con0;
+ unsigned intgpll_con1;
+ unsigned char res44b[0xb8];
unsigned intsrc_top0;
unsigned intsrc_top1;
unsigned intsrc_top2;
@@ -521,7 +532,9 @@ struct exynos5_clock {
unsigned intclkout_cmu_top_div_stat;
unsigned char res84[0x37f8];
unsigned intsrc_lex;
- unsigned char res85[0x2fc];
+ unsigned char res85[0x1fc];
+ unsigned intmux_stat_lex;
+ unsigned char res85b[0xfc];
unsigned intdiv_lex;
unsigned char res86[0xfc];
unsigned intdiv_stat_lex;
@@ -549,7 +562,8 @@ struct exynos5_clock {
unsigned intclkout_cmu_r1x;
unsigned intclkout_cmu_r1x_div_stat;
unsigned char res98[0x3608];
- unsigned intbpll_lock;
+
+ unsigned intbpll_lock; /* base + 0x2000c */
unsigned char res99[0xfc];
unsigned intbpll_con0;
unsigned intbpll_con1;
@@ -574,8 +588,10 @@ struct exynos5_clock {
unsigned intclkout_cmu_cdrex_div_stat;
unsigned char res108[0x8];
unsigned intlpddr3phy_ctrl;
- unsigned char res109[0xf5f8];
+ unsigned char res109a[0xc];
+ unsigned intlpddr3phy_con3;
+ unsigned intpll_div2_sel;
+ unsigned char res109b[0xf5e4];
};
#endif
-
#endif
--
1.7.4.4
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[U-Boot] [PATCH 3/9] SMDK5250: Add smdk5250-uboot-spl.lds
Default spl/u-boot-spl.lds created by spl/Makefile resolves
the spl text load addr to 0x0. As 0x0 belongs to iROM addr so
Global variables can not be used.
Adding specific smdk5250-uboot-spl.lds makes possible to use Global Variables
in spl.
Signed-off-by: Alim Akhtar
Signed-off-by: Rajeshwari Shinde
---
board/samsung/smdk5250/smdk5250-uboot-spl.lds | 66 +
include/configs/smdk5250.h|5 ++
2 files changed, 71 insertions(+), 0 deletions(-)
create mode 100644 board/samsung/smdk5250/smdk5250-uboot-spl.lds
diff --git a/board/samsung/smdk5250/smdk5250-uboot-spl.lds
b/board/samsung/smdk5250/smdk5250-uboot-spl.lds
new file mode 100644
index 000..d78dd77
--- /dev/null
+++ b/board/samsung/smdk5250/smdk5250-uboot-spl.lds
@@ -0,0 +1,66 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering,
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Based on arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE, \
+ LENGTH = CONFIG_SPL_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+
+SECTIONS
+{
+ .text :
+ {
+ __start = .;
+ arch/arm/cpu/armv7/start.o (.text)
+ *(.text*)
+ } >.sram
+ . = ALIGN(4);
+
+ .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+ . = ALIGN(4);
+
+ .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+ . = ALIGN(4);
+
+ /* Align .machine_param on 256 byte boundary for easier searching */
+ .machine_param ALIGN(0x100) : { *(.machine_param) } >.sram
+ . = ALIGN(4);
+
+ __image_copy_end = .;
+ _end = .;
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } >.sram
+}
diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h
index 9659f9e..405abd5 100644
--- a/include/configs/smdk5250.h
+++ b/include/configs/smdk5250.h
@@ -105,6 +105,11 @@
#define CONFIG_SPL
#define COPY_BL2_FNPTR_ADDR0x02020030
+/* specific .lds file */
+#define CONFIG_SPL_LDSCRIPT"board/samsung/smdk5250/smdk5250-uboot-spl.lds"
+#define CONFIG_SPL_TEXT_BASE 0x02023400
+#define CONFIG_SPL_MAX_SIZE(14 * 1024)
+
#define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000"
/* Miscellaneous configurable options */
--
1.7.4.4
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[U-Boot] [PATCH 5/9] EXYNOS5: CLOCK: Add clock support for Exynos5250 Rev 1.0
Add new clock values for Exynos5250 Rev 1.0
Signed-off-by: Hatim Ali
Signed-off-by: Rajeshwari Shinde
---
board/samsung/smdk5250/clock_init.c | 714 --
board/samsung/smdk5250/clock_init.h | 149
board/samsung/smdk5250/setup.h | 718 +++
3 files changed, 1136 insertions(+), 445 deletions(-)
create mode 100644 board/samsung/smdk5250/clock_init.h
diff --git a/board/samsung/smdk5250/clock_init.c
b/board/samsung/smdk5250/clock_init.c
index 305842d..2eba397 100644
--- a/board/samsung/smdk5250/clock_init.c
+++ b/board/samsung/smdk5250/clock_init.c
@@ -22,181 +22,643 @@
* MA 02111-1307 USA
*/
+#include
#include
-#include
#include
+#include
#include
-#include
-#include
+#include
+
+#include "clock_init.h"
#include "setup.h"
-void system_clock_init()
+DECLARE_GLOBAL_DATA_PTR;
+
+struct arm_clk_ratios arm_clk_ratios[] = {
+ {
+ .arm_freq_mhz = 600,
+
+ .apll_mdiv = 0xc8,
+ .apll_pdiv = 0x4,
+ .apll_sdiv = 0x1,
+
+ .arm2_ratio = 0x0,
+ .apll_ratio = 0x1,
+ .pclk_dbg_ratio = 0x1,
+ .atb_ratio = 0x2,
+ .periph_ratio = 0x7,
+ .acp_ratio = 0x7,
+ .cpud_ratio = 0x1,
+ .arm_ratio = 0x0,
+ }, {
+ .arm_freq_mhz = 800,
+
+ .apll_mdiv = 0x64,
+ .apll_pdiv = 0x3,
+ .apll_sdiv = 0x0,
+
+ .arm2_ratio = 0x0,
+ .apll_ratio = 0x1,
+ .pclk_dbg_ratio = 0x1,
+ .atb_ratio = 0x3,
+ .periph_ratio = 0x7,
+ .acp_ratio = 0x7,
+ .cpud_ratio = 0x2,
+ .arm_ratio = 0x0,
+ }, {
+ .arm_freq_mhz = 1000,
+
+ .apll_mdiv = 0x7d,
+ .apll_pdiv = 0x3,
+ .apll_sdiv = 0x0,
+
+ .arm2_ratio = 0x0,
+ .apll_ratio = 0x1,
+ .pclk_dbg_ratio = 0x1,
+ .atb_ratio = 0x4,
+ .periph_ratio = 0x7,
+ .acp_ratio = 0x7,
+ .cpud_ratio = 0x2,
+ .arm_ratio = 0x0,
+ }, {
+ .arm_freq_mhz = 1200,
+
+ .apll_mdiv = 0x96,
+ .apll_pdiv = 0x3,
+ .apll_sdiv = 0x0,
+
+ .arm2_ratio = 0x0,
+ .apll_ratio = 0x3,
+ .pclk_dbg_ratio = 0x1,
+ .atb_ratio = 0x5,
+ .periph_ratio = 0x7,
+ .acp_ratio = 0x7,
+ .cpud_ratio = 0x3,
+ .arm_ratio = 0x0,
+ }, {
+ .arm_freq_mhz = 1400,
+
+ .apll_mdiv = 0xaf,
+ .apll_pdiv = 0x3,
+ .apll_sdiv = 0x0,
+
+ .arm2_ratio = 0x0,
+ .apll_ratio = 0x3,
+ .pclk_dbg_ratio = 0x1,
+ .atb_ratio = 0x6,
+ .periph_ratio = 0x7,
+ .acp_ratio = 0x7,
+ .cpud_ratio = 0x3,
+ .arm_ratio = 0x0,
+ }, {
+ .arm_freq_mhz = 1700,
+
+ .apll_mdiv = 0x1a9,
+ .apll_pdiv = 0x6,
+ .apll_sdiv = 0x0,
+
+ .arm2_ratio = 0x0,
+ .apll_ratio = 0x3,
+ .pclk_dbg_ratio = 0x1,
+ .atb_ratio = 0x6,
+ .periph_ratio = 0x7,
+ .acp_ratio = 0x7,
+ .cpud_ratio = 0x3,
+ .arm_ratio = 0x0,
+ }
+};
+struct mem_timings mem_timings[] = {
+ {
+ .mem_manuf = MEM_MANUF_ELPIDA,
+ .mem_type = DDR_MODE_DDR3,
+ .frequency_mhz = 800,
+ .mpll_mdiv = 0xc8,
+ .mpll_pdiv = 0x3,
+ .mpll_sdiv = 0x0,
+ .cpll_mdiv = 0xde,
+ .cpll_pdiv = 0x4,
+ .cpll_sdiv = 0x2,
+ .gpll_mdiv = 0x215,
+ .gpll_pdiv = 0xc,
+ .gpll_sdiv = 0x1,
+ .epll_mdiv = 0x60,
+ .epll_pdiv = 0x3,
+ .epll_sdiv = 0x3,
+ .vpll_mdiv = 0x96,
+ .vpll_pdiv = 0x3,
+ .vpll_sdiv = 0x2,
+
+ .bpll_mdiv = 0x64,
+ .bpll_pdiv = 0x3,
+ .bpll_sdiv = 0x0,
+ .pclk_cdrex_ratio = 0x5,
+ .direct_cmd_msr = {
+ 0x00020018, 0x0003, 0x00010042, 0x0d70
+ },
+ .timing_ref = 0x00bb,
+ .timing_row = 0x8c36650e,
+ .timing_data = 0x3630580b,
+ .timing_power = 0x41000a44,
+ .phy0_dqs = 0x08080808,
+ .phy1_dqs = 0x08080808,
+ .phy0_dq = 0x08080808,
+ .phy1_dq = 0x08080808,
+ .phy0_tFS = 0x4,
+ .phy1_tFS = 0x4,
+ .phy0_pulld_dqs = 0xf,
+
[U-Boot] [PATCH 7/9] EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0
MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz.
Adjust the divisor value to get 800MHz as needed by devices
like UART etc
Signed-off-by: Hatim Ali
Signed-off-by: Rajeshwari Shinde
---
arch/arm/cpu/armv7/exynos/clock.c| 12 +++-
arch/arm/include/asm/arch-exynos/clock.h |3 +++
2 files changed, 14 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index 330bd75..dbd5f11 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -98,7 +98,7 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
struct exynos5_clock *clk =
(struct exynos5_clock *)samsung_get_base_clock();
unsigned long r, m, p, s, k = 0, mask, fout;
- unsigned int freq;
+ unsigned int freq, pll_div2_sel, mpll_fout_sel;
switch (pllreg) {
case APLL:
@@ -155,6 +155,16 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
fout = m * (freq / (p * (1 << (s - 1;
}
+ /* According to the user manual, in EVT1 MPLL always gives
+* 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/
+ if (pllreg == MPLL) {
+ pll_div2_sel = readl(&clk->pll_div2_sel);
+ mpll_fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT)
+ & MPLL_FOUT_SEL_MASK;
+ if (mpll_fout_sel == 0)
+ fout /= 2;
+ }
+
return fout;
}
diff --git a/arch/arm/include/asm/arch-exynos/clock.h
b/arch/arm/include/asm/arch-exynos/clock.h
index 7cc3d5e..a34a3f0 100644
--- a/arch/arm/include/asm/arch-exynos/clock.h
+++ b/arch/arm/include/asm/arch-exynos/clock.h
@@ -594,4 +594,7 @@ struct exynos5_clock {
unsigned char res109b[0xf5e4];
};
#endif
+
+#define MPLL_FOUT_SEL_SHIFT4
+#define MPLL_FOUT_SEL_MASK 0x1
#endif
--
1.7.4.4
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[U-Boot] [PATCH 8/9] EXYNOS5 : Modify pinnumx settings as per Exynos5250 Rev 1.0
This patch modifies the pinmux settings of MMC and UART as per
Exynos5250 Rev 1.0
Signed-off-by: Rajeshwari Shinde
---
arch/arm/cpu/armv7/exynos/pinmux.c | 18 +-
1 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c
b/arch/arm/cpu/armv7/exynos/pinmux.c
index d2b7d2c..7611c7a 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -40,8 +40,8 @@ static void exynos5_uart_config(int peripheral)
count = 4;
break;
case PERIPH_ID_UART1:
- bank = &gpio1->a0;
- start = 4;
+ bank = &gpio1->d0;
+ start = 0;
count = 4;
break;
case PERIPH_ID_UART2:
@@ -66,25 +66,25 @@ static int exynos5_mmc_config(int peripheral, int flags)
struct exynos5_gpio_part1 *gpio1 =
(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
struct s5p_gpio_bank *bank, *bank_ext;
- int i;
+ int i, start;
switch (peripheral) {
case PERIPH_ID_SDMMC0:
bank = &gpio1->c0;
bank_ext = &gpio1->c1;
+ start = 0;
break;
case PERIPH_ID_SDMMC1:
- bank = &gpio1->c1;
+ bank = &gpio1->c2;
bank_ext = NULL;
break;
case PERIPH_ID_SDMMC2:
- bank = &gpio1->c2;
- bank_ext = &gpio1->c3;
- break;
- case PERIPH_ID_SDMMC3:
bank = &gpio1->c3;
bank_ext = NULL;
break;
+ case PERIPH_ID_SDMMC3:
+ debug("SDMMC3 not supported yet");
+ return -1;
}
if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
debug("SDMMC device %d does not support 8bit mode",
@@ -92,7 +92,7 @@ static int exynos5_mmc_config(int peripheral, int flags)
return -1;
}
if (flags & PINMUX_FLAG_8BIT_MODE) {
- for (i = 3; i <= 6; i++) {
+ for (i = start; i <= (start + 3); i++) {
s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3));
s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
--
1.7.4.4
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[U-Boot] [PATCH 6/9] Exynos5: DDR3: Adding the DDR3 memory setup for Exynos5250 Rev 1.0
The patch adds the memory initialization sequence of DDR3.
Signed-off-by: Hatim Ali
Signed-off-by: Rajeshwari Shinde
---
arch/arm/include/asm/arch-exynos/dmc.h | 65 +
board/samsung/smdk5250/Makefile|2 +-
board/samsung/smdk5250/dmc_common.c| 199 ++
board/samsung/smdk5250/dmc_init.c | 462
board/samsung/smdk5250/dmc_init_ddr3.c | 228
board/samsung/smdk5250/setup.h | 59 -
6 files changed, 551 insertions(+), 464 deletions(-)
create mode 100644 board/samsung/smdk5250/dmc_common.c
delete mode 100644 board/samsung/smdk5250/dmc_init.c
create mode 100644 board/samsung/smdk5250/dmc_init_ddr3.c
diff --git a/arch/arm/include/asm/arch-exynos/dmc.h
b/arch/arm/include/asm/arch-exynos/dmc.h
index bd52d16..f65c676 100644
--- a/arch/arm/include/asm/arch-exynos/dmc.h
+++ b/arch/arm/include/asm/arch-exynos/dmc.h
@@ -251,5 +251,70 @@ struct exynos5_phy_control {
unsigned int phy_con41;
unsigned int phy_con42;
};
+
+enum ddr_mode {
+ DDR_MODE_DDR2,
+ DDR_MODE_DDR3,
+ DDR_MODE_LPDDR2,
+ DDR_MODE_LPDDR3,
+
+ DDR_MODE_COUNT,
+};
+
+enum mem_manuf {
+ MEM_MANUF_AUTODETECT,
+ MEM_MANUF_ELPIDA,
+ MEM_MANUF_SAMSUNG,
+
+ MEM_MANUF_COUNT,
+};
+
+/* CONCONTROL register fields */
+#define CONCONTROL_DFI_INIT_START_SHIFT28
+#define CONCONTROL_RD_FETCH_SHIFT 12
+#define CONCONTROL_RD_FETCH_MASK (0x7 << CONCONTROL_RD_FETCH_SHIFT)
+#define CONCONTROL_AREF_EN_SHIFT 5
+
+/* PRECHCONFIG register field */
+#define PRECHCONFIG_TP_CNT_SHIFT 24
+
+/* PWRDNCONFIG register field */
+#define PWRDNCONFIG_DPWRDN_CYC_SHIFT 0
+#define PWRDNCONFIG_DSREF_CYC_SHIFT16
+
+/* PHY_CON0 register fields */
+#define PHY_CON0_T_WRRDCMD_SHIFT 17
+#define PHY_CON0_T_WRRDCMD_MASK(0x7 <<
PHY_CON0_T_WRRDCMD_SHIFT)
+#define PHY_CON0_CTRL_DDR_MODE_SHIFT 11
+
+/* PHY_CON1 register fields */
+#define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT0
+
+/* PHY_CON12 register fields */
+#define PHY_CON12_CTRL_START_POINT_SHIFT 24
+#define PHY_CON12_CTRL_INC_SHIFT 16
+#define PHY_CON12_CTRL_FORCE_SHIFT 8
+#define PHY_CON12_CTRL_START_SHIFT 6
+#define PHY_CON12_CTRL_START_MASK (1 << PHY_CON12_CTRL_START_SHIFT)
+#define PHY_CON12_CTRL_DLL_ON_SHIFT5
+#define PHY_CON12_CTRL_DLL_ON_MASK (1 << PHY_CON12_CTRL_DLL_ON_SHIFT)
+#define PHY_CON12_CTRL_REF_SHIFT 1
+
+/* PHY_CON16 register fields */
+#define PHY_CON16_ZQ_MODE_DDS_SHIFT24
+#define PHY_CON16_ZQ_MODE_DDS_MASK (0x7 << PHY_CON16_ZQ_MODE_DDS_SHIFT)
+
+#define PHY_CON16_ZQ_MODE_TERM_SHIFT 21
+#define PHY_CON16_ZQ_MODE_TERM_MASK(0x7 << PHY_CON16_ZQ_MODE_TERM_SHIFT)
+
+#define PHY_CON16_ZQ_MODE_NOTERM_MASK (1 << 19)
+
+/* PHY_CON42 register fields */
+#define PHY_CON42_CTRL_BSTLEN_SHIFT8
+#define PHY_CON42_CTRL_BSTLEN_MASK (0xff << PHY_CON42_CTRL_BSTLEN_SHIFT)
+
+#define PHY_CON42_CTRL_RDLAT_SHIFT 0
+#define PHY_CON42_CTRL_RDLAT_MASK (0x1f << PHY_CON42_CTRL_RDLAT_SHIFT)
+
#endif
#endif
diff --git a/board/samsung/smdk5250/Makefile b/board/samsung/smdk5250/Makefile
index 3675fad..1474fa8 100644
--- a/board/samsung/smdk5250/Makefile
+++ b/board/samsung/smdk5250/Makefile
@@ -27,7 +27,7 @@ LIB = $(obj)lib$(BOARD).o
SOBJS := lowlevel_init.o
COBJS := clock_init.o
-COBJS += dmc_init.o
+COBJS += dmc_common.o dmc_init_ddr3.o
COBJS += tzpc_init.o
COBJS += smdk5250_spl.o
diff --git a/board/samsung/smdk5250/dmc_common.c
b/board/samsung/smdk5250/dmc_common.c
new file mode 100644
index 000..109602a
--- /dev/null
+++ b/board/samsung/smdk5250/dmc_common.c
@@ -0,0 +1,199 @@
+/*
+ * Mem setup common file for different types of DDR present on SMDK5250 boards.
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+#include
+
+#include "clock_init.h"
+#include "setup.h"
+
+#define ZQ_INIT_TIMEOUT1
+
+int dmc_config_zq(struct mem_timings *mem,
+ struct exynos5_phy_control *phy0_ctrl,
+ struct exynos5_phy_control *phy1_ctrl)
+{
+ unsigned long val = 0;
+ int i;
+
+
[U-Boot] [PATCH 9/9] SMDK5250: Enable UART and MMC for Exynos5250 Rev 1.0
This patch sets UART3 and MMC channle 0 for Exynos5250 Rev 1.0
Signed-off-by: Rajeshwari Shinde
---
board/samsung/smdk5250/smdk5250.c |6 +++---
include/configs/smdk5250.h|2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/board/samsung/smdk5250/smdk5250.c
b/board/samsung/smdk5250/smdk5250.c
index 3b078da..b593325 100644
--- a/board/samsung/smdk5250/smdk5250.c
+++ b/board/samsung/smdk5250/smdk5250.c
@@ -130,13 +130,13 @@ int board_mmc_init(bd_t *bis)
{
int err;
- err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
+ err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
if (err) {
- debug("SDMMC2 not configured\n");
+ debug("SDMMC0 not configured\n");
return err;
}
- err = s5p_mmc_init(2, 4);
+ err = s5p_mmc_init(0, 8);
return err;
}
#endif
diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h
index 405abd5..d4d370f 100644
--- a/include/configs/smdk5250.h
+++ b/include/configs/smdk5250.h
@@ -69,7 +69,7 @@
/* select serial console configuration */
#define CONFIG_SERIAL_MULTI
-#define CONFIG_SERIAL1 /* use SERIAL 1 */
+#define CONFIG_SERIAL3 /* use SERIAL 3 */
#define CONFIG_BAUDRATE115200
#define EXYNOS5_DEFAULT_UART_OFFSET0x01
--
1.7.4.4
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[U-Boot] [PATCH 0/9 V2]EXYNOS5: Support for Exynos5250 Rev 1.0
This patch set adds support for Exynos5250 Rev 1.0. Exynos5250 Rev 1.0 supports DDR3 Memory configuration and support for LPDDR2 is removed. Exynos5250 Rev 1.0 supports DWMMC driver but the support for same is not yet gone into Mainline. After DWMMC driver is added to Mainline support for generic S5P MMC driver will be removed. Due to Support of generic S5P MMC driver currently still being there in the Mainline you can see the following error on boot. mmc_reset: timeout error mmc_change_clock: timeout error mmc_send_cmd: waiting for status update MMC init failed Changes in V2: - Included Paramateric structure with in #ifndef __ASSEMBLY__. Rajeshwari Shinde (9): ARCH: SPL: Add parametric board initializer SMDK5250: SPL: Define parametric board initializer SMDK5250: Add smdk5250-uboot-spl.lds EXYNOS5: CLOCK: define additional clock registers for Exynos5250 Rev 1.0 EXYNOS5: CLOCK: Add clock support for Exynos5250 Rev 1.0 Exynos5: DDR3: Adding the DDR3 memory setup for Exynos5250 Rev 1.0 EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0 EXYNOS5 : Modify pinnumx settings as per Exynos5250 Rev 1.0 SMDK5250: Enable UART and MMC for Exynos5250 Rev 1.0 arch/arm/cpu/armv7/exynos/clock.c | 12 +- arch/arm/cpu/armv7/exynos/pinmux.c| 18 +- arch/arm/include/asm/arch-exynos/clock.h | 37 +- arch/arm/include/asm/arch-exynos/dmc.h| 65 +++ arch/arm/include/asm/arch-exynos/spl.h| 95 +++ board/samsung/smdk5250/Makefile |3 +- board/samsung/smdk5250/clock_init.c | 714 +++ board/samsung/smdk5250/clock_init.h | 149 + board/samsung/smdk5250/dmc_common.c | 199 +++ board/samsung/smdk5250/dmc_init.c | 462 --- board/samsung/smdk5250/dmc_init_ddr3.c| 228 board/samsung/smdk5250/setup.h| 765 +++-- board/samsung/smdk5250/smdk5250-uboot-spl.lds | 66 +++ board/samsung/smdk5250/smdk5250.c |6 +- board/samsung/smdk5250/smdk5250_spl.c | 68 +++ include/configs/smdk5250.h|7 +- 16 files changed, 1968 insertions(+), 926 deletions(-) create mode 100644 arch/arm/include/asm/arch-exynos/spl.h create mode 100644 board/samsung/smdk5250/clock_init.h create mode 100644 board/samsung/smdk5250/dmc_common.c delete mode 100644 board/samsung/smdk5250/dmc_init.c create mode 100644 board/samsung/smdk5250/dmc_init_ddr3.c create mode 100644 board/samsung/smdk5250/smdk5250-uboot-spl.lds create mode 100644 board/samsung/smdk5250/smdk5250_spl.c -- 1.7.4.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/9 V2] ARCH: SPL: Add parametric board initializer
Add a structure for table-driven configuration mechanism such that no
recompilation
is needed to update the configuration parameters, rather than hard-coding
board initialization parameters.
Signed-off-by: Che-Liang Chiou
Signed-off-by: Abhilash Kesavan
Signed-off-by: Tom Wai-Hong Tam
Signed-off-by: Simon Glass
Signed-off-by: Rajeshwari Shinde
---
Changes in V2:
- Included Paramateric structure with in #ifndef __ASSEMBLY__.
arch/arm/include/asm/arch-exynos/spl.h | 97
1 files changed, 97 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/include/asm/arch-exynos/spl.h
diff --git a/arch/arm/include/asm/arch-exynos/spl.h
b/arch/arm/include/asm/arch-exynos/spl.h
new file mode 100644
index 000..306b41d
--- /dev/null
+++ b/arch/arm/include/asm/arch-exynos/spl.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_EXYNOS_SPL_H__
+#define __ASM_ARCH_EXYNOS_SPL_H__
+
+#include
+
+enum boot_mode {
+ /*
+* Assign the OM pin values for respective boot modes.
+* Exynos4 does not support spi boot and the mmc boot OM
+* pin values are the same across Exynos4 and Exynos5.
+*/
+ BOOT_MODE_MMC = 4,
+ BOOT_MODE_SERIAL = 20,
+ /* Boot based on Operating Mode pin settings */
+ BOOT_MODE_OM = 32,
+ BOOT_MODE_USB, /* Boot using USB download */
+};
+
+#ifndef __ASSEMBLY__
+/* Parameters of early board initialization in SPL */
+struct spl_machine_param {
+ /* Add fields as and when required */
+ u32 signature;
+ u32 version;/* Version number */
+ u32 size; /* Size of block */
+ /**
+* Parameters we expect, in order, terminated with \0. Each parameter
+* is a single character representing one 32-bit word in this
+* structure.
+*
+* Valid characters in this string are:
+*
+* Code Name
+* vmem_iv_size
+* mmem_type
+* uuboot_size
+* bboot_source
+* ffrequency_mhz (memory frequency in MHz)
+* aARM clock frequency in MHz
+* sserial base address
+* ii2c base address for early access (meant for PMIC)
+* rboard rev GPIO numbers used to read board revision
+* (lower halfword=bit 0, upper=bit 1)
+* MMemory Manufacturer name
+* \0 termination
+*/
+ charparams[12]; /* Length must be word-aligned */
+ u32 mem_iv_size;/* Memory channel interleaving size */
+ enum ddr_mode mem_type; /* Type of on-board memory */
+ /*
+* U-boot size - The iROM mmc copy function used by the SPL takes a
+* block count paramter to describe the u-boot size unlike the spi
+* boot copy function which just uses the u-boot size directly. Align
+* the u-boot size to block size (512 bytes) when populating the SPL
+* table only for mmc boot.
+*/
+ u32 uboot_size;
+ enum boot_mode boot_source;/* Boot device */
+ enum mem_manuf mem_manuf; /* Memory Manufacturer */
+ unsignedfrequency_mhz; /* Frequency of memory in MHz */
+ unsignedarm_freq_mhz; /* ARM Frequency in MHz */
+ u32 serial_base;/* Serial base address */
+ u32 i2c_base; /* i2c base address */
+} __attribute__((__packed__));
+#endif
+
+/**
+ * Validate signature and return a pointer to the parameter table. If the
+ * signature is invalid, call panic() and never return.
+ *
+ * @return pointer to the parameter table if signature matched or never return.
+ */
+struct spl_machine_param *spl_get_machine_params(void);
+
+#endif /* __ASM_ARCH_EXYNOS_SPL_H__ */
--
1.7.4.4
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[U-Boot] [PATCH 2/9 V2] SMDK5250: SPL: Define parametric board initializer
Define table-driven configuration mechanism for SMDK5250
rather than hard-coding board initialization parameters.
Signed-off-by: Che-Liang Chiou
Signed-off-by: Abhilash Kesavan
Signed-off-by: Tom Wai-Hong Tam
Signed-off-by: Simon Glass
Signed-off-by: Rajeshwari Shinde
---
Chnages in V2:
- None
board/samsung/smdk5250/Makefile |1 +
board/samsung/smdk5250/smdk5250_spl.c | 68 +
2 files changed, 69 insertions(+), 0 deletions(-)
create mode 100644 board/samsung/smdk5250/smdk5250_spl.c
diff --git a/board/samsung/smdk5250/Makefile b/board/samsung/smdk5250/Makefile
index 226db1f..3675fad 100644
--- a/board/samsung/smdk5250/Makefile
+++ b/board/samsung/smdk5250/Makefile
@@ -29,6 +29,7 @@ SOBJS := lowlevel_init.o
COBJS := clock_init.o
COBJS += dmc_init.o
COBJS += tzpc_init.o
+COBJS += smdk5250_spl.o
ifndef CONFIG_SPL_BUILD
COBJS += smdk5250.o
diff --git a/board/samsung/smdk5250/smdk5250_spl.c
b/board/samsung/smdk5250/smdk5250_spl.c
new file mode 100644
index 000..1d453ca
--- /dev/null
+++ b/board/samsung/smdk5250/smdk5250_spl.c
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+#include
+#include
+#include
+
+#define SIGNATURE 0xdeadbeef
+
+/* Parameters of early board initialization in SPL */
+static struct spl_machine_param machine_param
+ __attribute__((section(".machine_param"))) = {
+ .signature = SIGNATURE,
+ .version= 1,
+ .params = "vmubfasirM",
+ .size = sizeof(machine_param),
+
+ .mem_iv_size= 0x1f,
+ .mem_type = DDR_MODE_DDR3,
+
+ /*
+* Set uboot_size to 0x10 bytes.
+*
+* This is an overly conservative value chosen to accommodate all
+* possible U-Boot image. You are advised to set this value to a
+* smaller realistic size via scripts that modifies the .machine_param
+* section of output U-Boot image.
+*/
+ .uboot_size = 0x10,
+
+ .boot_source= BOOT_MODE_OM,
+ .frequency_mhz = 800,
+ .arm_freq_mhz = 1700,
+ .serial_base= 0x12c3,
+ .i2c_base = 0x12c6,
+ .mem_manuf = MEM_MANUF_SAMSUNG,
+};
+
+struct spl_machine_param *spl_get_machine_params(void)
+{
+ if (machine_param.signature != SIGNATURE) {
+ /* Will hang if SIGNATURE dont match */
+ while (1)
+ ;
+ }
+
+ return &machine_param;
+}
--
1.7.4.4
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[U-Boot] [PATCH 3/9 V2] SMDK5250: Add smdk5250-uboot-spl.lds
Default spl/u-boot-spl.lds created by spl/Makefile resolves
the spl text load addr to 0x0. As 0x0 belongs to iROM addr so
Global variables can not be used.
Adding specific smdk5250-uboot-spl.lds makes possible to use Global Variables
in spl.
Signed-off-by: Alim Akhtar
Signed-off-by: Rajeshwari Shinde
---
Chnages in V2:
- None
board/samsung/smdk5250/smdk5250-uboot-spl.lds | 66 +
include/configs/smdk5250.h|5 ++
2 files changed, 71 insertions(+), 0 deletions(-)
create mode 100644 board/samsung/smdk5250/smdk5250-uboot-spl.lds
diff --git a/board/samsung/smdk5250/smdk5250-uboot-spl.lds
b/board/samsung/smdk5250/smdk5250-uboot-spl.lds
new file mode 100644
index 000..d78dd77
--- /dev/null
+++ b/board/samsung/smdk5250/smdk5250-uboot-spl.lds
@@ -0,0 +1,66 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering,
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Based on arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE, \
+ LENGTH = CONFIG_SPL_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+
+SECTIONS
+{
+ .text :
+ {
+ __start = .;
+ arch/arm/cpu/armv7/start.o (.text)
+ *(.text*)
+ } >.sram
+ . = ALIGN(4);
+
+ .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+ . = ALIGN(4);
+
+ .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+ . = ALIGN(4);
+
+ /* Align .machine_param on 256 byte boundary for easier searching */
+ .machine_param ALIGN(0x100) : { *(.machine_param) } >.sram
+ . = ALIGN(4);
+
+ __image_copy_end = .;
+ _end = .;
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start = .;
+ *(.bss*)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } >.sram
+}
diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h
index 9659f9e..405abd5 100644
--- a/include/configs/smdk5250.h
+++ b/include/configs/smdk5250.h
@@ -105,6 +105,11 @@
#define CONFIG_SPL
#define COPY_BL2_FNPTR_ADDR0x02020030
+/* specific .lds file */
+#define CONFIG_SPL_LDSCRIPT"board/samsung/smdk5250/smdk5250-uboot-spl.lds"
+#define CONFIG_SPL_TEXT_BASE 0x02023400
+#define CONFIG_SPL_MAX_SIZE(14 * 1024)
+
#define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000"
/* Miscellaneous configurable options */
--
1.7.4.4
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[U-Boot] [PATCH 4/9 V2] EXYNOS5: CLOCK: define additional clock registers for Exynos5250 Rev 1.0
Define additional registers for clock control in Exynos5250 Rev 1.0
Signed-off-by: Hatim Ali
Signed-off-by: Rajeshwari Shinde
---
Chnages in V2:
- None
arch/arm/include/asm/arch-exynos/clock.h | 36 +
1 files changed, 26 insertions(+), 10 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/clock.h
b/arch/arm/include/asm/arch-exynos/clock.h
index 50da958..7cc3d5e 100644
--- a/arch/arm/include/asm/arch-exynos/clock.h
+++ b/arch/arm/include/asm/arch-exynos/clock.h
@@ -272,7 +272,7 @@ struct exynos5_clock {
unsigned intclkout_cmu_cpu;
unsigned intclkout_cmu_cpu_div_stat;
unsigned char res8[0x5f8];
- unsigned intarmclk_stopctrl;
+ unsigned intarmclk_stopctrl;/* base + 0x1000 */
unsigned intatclk_stopctrl;
unsigned char res9[0x8];
unsigned intparityfail_status;
@@ -323,10 +323,12 @@ struct exynos5_clock {
unsigned char res19[0xf8];
unsigned intdiv_core0;
unsigned intdiv_core1;
- unsigned char res20[0xf8];
+ unsigned intdiv_sysrgt;
+ unsigned char res20[0xf4];
unsigned intdiv_stat_core0;
unsigned intdiv_stat_core1;
- unsigned char res21[0x2f8];
+ unsigned intdiv_stat_sysrgt;
+ unsigned char res21[0x2f4];
unsigned intgate_ip_core;
unsigned char res22[0xfc];
unsigned intclkout_cmu_core;
@@ -352,7 +354,11 @@ struct exynos5_clock {
unsigned intdiv_stat_acp;
unsigned char res30[0x1fc];
unsigned intgate_ip_acp;
- unsigned char res31[0x1fc];
+ unsigned char res31a[0xfc];
+ unsigned intdiv_syslft;
+ unsigned char res31b[0xc];
+ unsigned intdiv_stat_syslft;
+ unsigned char res31c[0xec];
unsigned intclkout_cmu_acp;
unsigned intclkout_cmu_acp_div_stat;
unsigned char res32[0x38f8];
@@ -379,7 +385,9 @@ struct exynos5_clock {
unsigned intepll_lock;
unsigned char res40[0xc];
unsigned intvpll_lock;
- unsigned char res41[0xdc];
+ unsigned char res41a[0xc];
+ unsigned intgpll_lock;
+ unsigned char res41b[0xcc];
unsigned intcpll_con0;
unsigned intcpll_con1;
unsigned char res42[0x8];
@@ -390,7 +398,10 @@ struct exynos5_clock {
unsigned intvpll_con0;
unsigned intvpll_con1;
unsigned intvpll_con2;
- unsigned char res44[0xc4];
+ unsigned char res44a[0x4];
+ unsigned intgpll_con0;
+ unsigned intgpll_con1;
+ unsigned char res44b[0xb8];
unsigned intsrc_top0;
unsigned intsrc_top1;
unsigned intsrc_top2;
@@ -521,7 +532,9 @@ struct exynos5_clock {
unsigned intclkout_cmu_top_div_stat;
unsigned char res84[0x37f8];
unsigned intsrc_lex;
- unsigned char res85[0x2fc];
+ unsigned char res85[0x1fc];
+ unsigned intmux_stat_lex;
+ unsigned char res85b[0xfc];
unsigned intdiv_lex;
unsigned char res86[0xfc];
unsigned intdiv_stat_lex;
@@ -549,7 +562,8 @@ struct exynos5_clock {
unsigned intclkout_cmu_r1x;
unsigned intclkout_cmu_r1x_div_stat;
unsigned char res98[0x3608];
- unsigned intbpll_lock;
+
+ unsigned intbpll_lock; /* base + 0x2000c */
unsigned char res99[0xfc];
unsigned intbpll_con0;
unsigned intbpll_con1;
@@ -574,8 +588,10 @@ struct exynos5_clock {
unsigned intclkout_cmu_cdrex_div_stat;
unsigned char res108[0x8];
unsigned intlpddr3phy_ctrl;
- unsigned char res109[0xf5f8];
+ unsigned char res109a[0xc];
+ unsigned intlpddr3phy_con3;
+ unsigned intpll_div2_sel;
+ unsigned char res109b[0xf5e4];
};
#endif
-
#endif
--
1.7.4.4
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[U-Boot] [PATCH 5/9 V2] EXYNOS5: CLOCK: Add clock support for Exynos5250 Rev 1.0
Add new clock values for Exynos5250 Rev 1.0
Signed-off-by: Hatim Ali
Signed-off-by: Rajeshwari Shinde
---
Chnages in V2:
- None
board/samsung/smdk5250/clock_init.c | 714 --
board/samsung/smdk5250/clock_init.h | 149
board/samsung/smdk5250/setup.h | 718 +++
3 files changed, 1136 insertions(+), 445 deletions(-)
create mode 100644 board/samsung/smdk5250/clock_init.h
diff --git a/board/samsung/smdk5250/clock_init.c
b/board/samsung/smdk5250/clock_init.c
index 305842d..2eba397 100644
--- a/board/samsung/smdk5250/clock_init.c
+++ b/board/samsung/smdk5250/clock_init.c
@@ -22,181 +22,643 @@
* MA 02111-1307 USA
*/
+#include
#include
-#include
#include
+#include
#include
-#include
-#include
+#include
+
+#include "clock_init.h"
#include "setup.h"
-void system_clock_init()
+DECLARE_GLOBAL_DATA_PTR;
+
+struct arm_clk_ratios arm_clk_ratios[] = {
+ {
+ .arm_freq_mhz = 600,
+
+ .apll_mdiv = 0xc8,
+ .apll_pdiv = 0x4,
+ .apll_sdiv = 0x1,
+
+ .arm2_ratio = 0x0,
+ .apll_ratio = 0x1,
+ .pclk_dbg_ratio = 0x1,
+ .atb_ratio = 0x2,
+ .periph_ratio = 0x7,
+ .acp_ratio = 0x7,
+ .cpud_ratio = 0x1,
+ .arm_ratio = 0x0,
+ }, {
+ .arm_freq_mhz = 800,
+
+ .apll_mdiv = 0x64,
+ .apll_pdiv = 0x3,
+ .apll_sdiv = 0x0,
+
+ .arm2_ratio = 0x0,
+ .apll_ratio = 0x1,
+ .pclk_dbg_ratio = 0x1,
+ .atb_ratio = 0x3,
+ .periph_ratio = 0x7,
+ .acp_ratio = 0x7,
+ .cpud_ratio = 0x2,
+ .arm_ratio = 0x0,
+ }, {
+ .arm_freq_mhz = 1000,
+
+ .apll_mdiv = 0x7d,
+ .apll_pdiv = 0x3,
+ .apll_sdiv = 0x0,
+
+ .arm2_ratio = 0x0,
+ .apll_ratio = 0x1,
+ .pclk_dbg_ratio = 0x1,
+ .atb_ratio = 0x4,
+ .periph_ratio = 0x7,
+ .acp_ratio = 0x7,
+ .cpud_ratio = 0x2,
+ .arm_ratio = 0x0,
+ }, {
+ .arm_freq_mhz = 1200,
+
+ .apll_mdiv = 0x96,
+ .apll_pdiv = 0x3,
+ .apll_sdiv = 0x0,
+
+ .arm2_ratio = 0x0,
+ .apll_ratio = 0x3,
+ .pclk_dbg_ratio = 0x1,
+ .atb_ratio = 0x5,
+ .periph_ratio = 0x7,
+ .acp_ratio = 0x7,
+ .cpud_ratio = 0x3,
+ .arm_ratio = 0x0,
+ }, {
+ .arm_freq_mhz = 1400,
+
+ .apll_mdiv = 0xaf,
+ .apll_pdiv = 0x3,
+ .apll_sdiv = 0x0,
+
+ .arm2_ratio = 0x0,
+ .apll_ratio = 0x3,
+ .pclk_dbg_ratio = 0x1,
+ .atb_ratio = 0x6,
+ .periph_ratio = 0x7,
+ .acp_ratio = 0x7,
+ .cpud_ratio = 0x3,
+ .arm_ratio = 0x0,
+ }, {
+ .arm_freq_mhz = 1700,
+
+ .apll_mdiv = 0x1a9,
+ .apll_pdiv = 0x6,
+ .apll_sdiv = 0x0,
+
+ .arm2_ratio = 0x0,
+ .apll_ratio = 0x3,
+ .pclk_dbg_ratio = 0x1,
+ .atb_ratio = 0x6,
+ .periph_ratio = 0x7,
+ .acp_ratio = 0x7,
+ .cpud_ratio = 0x3,
+ .arm_ratio = 0x0,
+ }
+};
+struct mem_timings mem_timings[] = {
+ {
+ .mem_manuf = MEM_MANUF_ELPIDA,
+ .mem_type = DDR_MODE_DDR3,
+ .frequency_mhz = 800,
+ .mpll_mdiv = 0xc8,
+ .mpll_pdiv = 0x3,
+ .mpll_sdiv = 0x0,
+ .cpll_mdiv = 0xde,
+ .cpll_pdiv = 0x4,
+ .cpll_sdiv = 0x2,
+ .gpll_mdiv = 0x215,
+ .gpll_pdiv = 0xc,
+ .gpll_sdiv = 0x1,
+ .epll_mdiv = 0x60,
+ .epll_pdiv = 0x3,
+ .epll_sdiv = 0x3,
+ .vpll_mdiv = 0x96,
+ .vpll_pdiv = 0x3,
+ .vpll_sdiv = 0x2,
+
+ .bpll_mdiv = 0x64,
+ .bpll_pdiv = 0x3,
+ .bpll_sdiv = 0x0,
+ .pclk_cdrex_ratio = 0x5,
+ .direct_cmd_msr = {
+ 0x00020018, 0x0003, 0x00010042, 0x0d70
+ },
+ .timing_ref = 0x00bb,
+ .timing_row = 0x8c36650e,
+ .timing_data = 0x3630580b,
+ .timing_power = 0x41000a44,
+ .phy0_dqs = 0x08080808,
+ .phy1_dqs = 0x08080808,
+ .phy0_dq = 0x08080808,
+ .phy1_dq = 0x08080808,
+ .phy0_tFS = 0x4,
+ .phy1_tFS = 0x4,
+ .phy0_
[U-Boot] [PATCH 6/9 V2] Exynos5: DDR3: Adding the DDR3 memory setup for Exynos5250 Rev 1.0
The patch adds the memory initialization sequence of DDR3.
Signed-off-by: Hatim Ali
Signed-off-by: Rajeshwari Shinde
---
Chnages in V2:
- None
arch/arm/include/asm/arch-exynos/dmc.h | 65 +
board/samsung/smdk5250/Makefile|2 +-
board/samsung/smdk5250/dmc_common.c| 199 ++
board/samsung/smdk5250/dmc_init.c | 462
board/samsung/smdk5250/dmc_init_ddr3.c | 228
board/samsung/smdk5250/setup.h | 59 -
6 files changed, 551 insertions(+), 464 deletions(-)
create mode 100644 board/samsung/smdk5250/dmc_common.c
delete mode 100644 board/samsung/smdk5250/dmc_init.c
create mode 100644 board/samsung/smdk5250/dmc_init_ddr3.c
diff --git a/arch/arm/include/asm/arch-exynos/dmc.h
b/arch/arm/include/asm/arch-exynos/dmc.h
index bd52d16..f65c676 100644
--- a/arch/arm/include/asm/arch-exynos/dmc.h
+++ b/arch/arm/include/asm/arch-exynos/dmc.h
@@ -251,5 +251,70 @@ struct exynos5_phy_control {
unsigned int phy_con41;
unsigned int phy_con42;
};
+
+enum ddr_mode {
+ DDR_MODE_DDR2,
+ DDR_MODE_DDR3,
+ DDR_MODE_LPDDR2,
+ DDR_MODE_LPDDR3,
+
+ DDR_MODE_COUNT,
+};
+
+enum mem_manuf {
+ MEM_MANUF_AUTODETECT,
+ MEM_MANUF_ELPIDA,
+ MEM_MANUF_SAMSUNG,
+
+ MEM_MANUF_COUNT,
+};
+
+/* CONCONTROL register fields */
+#define CONCONTROL_DFI_INIT_START_SHIFT28
+#define CONCONTROL_RD_FETCH_SHIFT 12
+#define CONCONTROL_RD_FETCH_MASK (0x7 << CONCONTROL_RD_FETCH_SHIFT)
+#define CONCONTROL_AREF_EN_SHIFT 5
+
+/* PRECHCONFIG register field */
+#define PRECHCONFIG_TP_CNT_SHIFT 24
+
+/* PWRDNCONFIG register field */
+#define PWRDNCONFIG_DPWRDN_CYC_SHIFT 0
+#define PWRDNCONFIG_DSREF_CYC_SHIFT16
+
+/* PHY_CON0 register fields */
+#define PHY_CON0_T_WRRDCMD_SHIFT 17
+#define PHY_CON0_T_WRRDCMD_MASK(0x7 <<
PHY_CON0_T_WRRDCMD_SHIFT)
+#define PHY_CON0_CTRL_DDR_MODE_SHIFT 11
+
+/* PHY_CON1 register fields */
+#define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT0
+
+/* PHY_CON12 register fields */
+#define PHY_CON12_CTRL_START_POINT_SHIFT 24
+#define PHY_CON12_CTRL_INC_SHIFT 16
+#define PHY_CON12_CTRL_FORCE_SHIFT 8
+#define PHY_CON12_CTRL_START_SHIFT 6
+#define PHY_CON12_CTRL_START_MASK (1 << PHY_CON12_CTRL_START_SHIFT)
+#define PHY_CON12_CTRL_DLL_ON_SHIFT5
+#define PHY_CON12_CTRL_DLL_ON_MASK (1 << PHY_CON12_CTRL_DLL_ON_SHIFT)
+#define PHY_CON12_CTRL_REF_SHIFT 1
+
+/* PHY_CON16 register fields */
+#define PHY_CON16_ZQ_MODE_DDS_SHIFT24
+#define PHY_CON16_ZQ_MODE_DDS_MASK (0x7 << PHY_CON16_ZQ_MODE_DDS_SHIFT)
+
+#define PHY_CON16_ZQ_MODE_TERM_SHIFT 21
+#define PHY_CON16_ZQ_MODE_TERM_MASK(0x7 << PHY_CON16_ZQ_MODE_TERM_SHIFT)
+
+#define PHY_CON16_ZQ_MODE_NOTERM_MASK (1 << 19)
+
+/* PHY_CON42 register fields */
+#define PHY_CON42_CTRL_BSTLEN_SHIFT8
+#define PHY_CON42_CTRL_BSTLEN_MASK (0xff << PHY_CON42_CTRL_BSTLEN_SHIFT)
+
+#define PHY_CON42_CTRL_RDLAT_SHIFT 0
+#define PHY_CON42_CTRL_RDLAT_MASK (0x1f << PHY_CON42_CTRL_RDLAT_SHIFT)
+
#endif
#endif
diff --git a/board/samsung/smdk5250/Makefile b/board/samsung/smdk5250/Makefile
index 3675fad..1474fa8 100644
--- a/board/samsung/smdk5250/Makefile
+++ b/board/samsung/smdk5250/Makefile
@@ -27,7 +27,7 @@ LIB = $(obj)lib$(BOARD).o
SOBJS := lowlevel_init.o
COBJS := clock_init.o
-COBJS += dmc_init.o
+COBJS += dmc_common.o dmc_init_ddr3.o
COBJS += tzpc_init.o
COBJS += smdk5250_spl.o
diff --git a/board/samsung/smdk5250/dmc_common.c
b/board/samsung/smdk5250/dmc_common.c
new file mode 100644
index 000..109602a
--- /dev/null
+++ b/board/samsung/smdk5250/dmc_common.c
@@ -0,0 +1,199 @@
+/*
+ * Mem setup common file for different types of DDR present on SMDK5250 boards.
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+#include
+
+#include "clock_init.h"
+#include "setup.h"
+
+#define ZQ_INIT_TIMEOUT1
+
+int dmc_config_zq(struct mem_timings *mem,
+ struct exynos5_phy_control *phy0_ctrl,
+ struct exynos5_phy_control *phy1_ctrl)
+{
+ unsigned lo
[U-Boot] [PATCH 7/9 V2] EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0
MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz.
Adjust the divisor value to get 800MHz as needed by devices
like UART etc
Signed-off-by: Hatim Ali
Signed-off-by: Rajeshwari Shinde
---
Chnages in V2:
- None
arch/arm/cpu/armv7/exynos/clock.c| 12 +++-
arch/arm/include/asm/arch-exynos/clock.h |3 +++
2 files changed, 14 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index 330bd75..dbd5f11 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -98,7 +98,7 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
struct exynos5_clock *clk =
(struct exynos5_clock *)samsung_get_base_clock();
unsigned long r, m, p, s, k = 0, mask, fout;
- unsigned int freq;
+ unsigned int freq, pll_div2_sel, mpll_fout_sel;
switch (pllreg) {
case APLL:
@@ -155,6 +155,16 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
fout = m * (freq / (p * (1 << (s - 1;
}
+ /* According to the user manual, in EVT1 MPLL always gives
+* 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/
+ if (pllreg == MPLL) {
+ pll_div2_sel = readl(&clk->pll_div2_sel);
+ mpll_fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT)
+ & MPLL_FOUT_SEL_MASK;
+ if (mpll_fout_sel == 0)
+ fout /= 2;
+ }
+
return fout;
}
diff --git a/arch/arm/include/asm/arch-exynos/clock.h
b/arch/arm/include/asm/arch-exynos/clock.h
index 7cc3d5e..a34a3f0 100644
--- a/arch/arm/include/asm/arch-exynos/clock.h
+++ b/arch/arm/include/asm/arch-exynos/clock.h
@@ -594,4 +594,7 @@ struct exynos5_clock {
unsigned char res109b[0xf5e4];
};
#endif
+
+#define MPLL_FOUT_SEL_SHIFT4
+#define MPLL_FOUT_SEL_MASK 0x1
#endif
--
1.7.4.4
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[U-Boot] [PATCH 8/9 V2] EXYNOS5 : Modify pinnumx settings as per Exynos5250 Rev 1.0
This patch modifies the pinmux settings of MMC and UART as per
Exynos5250 Rev 1.0
Signed-off-by: Rajeshwari Shinde
---
Chnages in V2:
- None
arch/arm/cpu/armv7/exynos/pinmux.c | 18 +-
1 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c
b/arch/arm/cpu/armv7/exynos/pinmux.c
index d2b7d2c..7611c7a 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -40,8 +40,8 @@ static void exynos5_uart_config(int peripheral)
count = 4;
break;
case PERIPH_ID_UART1:
- bank = &gpio1->a0;
- start = 4;
+ bank = &gpio1->d0;
+ start = 0;
count = 4;
break;
case PERIPH_ID_UART2:
@@ -66,25 +66,25 @@ static int exynos5_mmc_config(int peripheral, int flags)
struct exynos5_gpio_part1 *gpio1 =
(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
struct s5p_gpio_bank *bank, *bank_ext;
- int i;
+ int i, start;
switch (peripheral) {
case PERIPH_ID_SDMMC0:
bank = &gpio1->c0;
bank_ext = &gpio1->c1;
+ start = 0;
break;
case PERIPH_ID_SDMMC1:
- bank = &gpio1->c1;
+ bank = &gpio1->c2;
bank_ext = NULL;
break;
case PERIPH_ID_SDMMC2:
- bank = &gpio1->c2;
- bank_ext = &gpio1->c3;
- break;
- case PERIPH_ID_SDMMC3:
bank = &gpio1->c3;
bank_ext = NULL;
break;
+ case PERIPH_ID_SDMMC3:
+ debug("SDMMC3 not supported yet");
+ return -1;
}
if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
debug("SDMMC device %d does not support 8bit mode",
@@ -92,7 +92,7 @@ static int exynos5_mmc_config(int peripheral, int flags)
return -1;
}
if (flags & PINMUX_FLAG_8BIT_MODE) {
- for (i = 3; i <= 6; i++) {
+ for (i = start; i <= (start + 3); i++) {
s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3));
s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
--
1.7.4.4
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[U-Boot] [PATCH 9/9 V2] SMDK5250: Enable UART and MMC for Exynos5250 Rev 1.0
This patch sets UART3 and MMC channle 0 for Exynos5250 Rev 1.0
Signed-off-by: Rajeshwari Shinde
---
Chnages in V2:
- None
board/samsung/smdk5250/smdk5250.c |6 +++---
include/configs/smdk5250.h|2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/board/samsung/smdk5250/smdk5250.c
b/board/samsung/smdk5250/smdk5250.c
index 3b078da..b593325 100644
--- a/board/samsung/smdk5250/smdk5250.c
+++ b/board/samsung/smdk5250/smdk5250.c
@@ -130,13 +130,13 @@ int board_mmc_init(bd_t *bis)
{
int err;
- err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
+ err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
if (err) {
- debug("SDMMC2 not configured\n");
+ debug("SDMMC0 not configured\n");
return err;
}
- err = s5p_mmc_init(2, 4);
+ err = s5p_mmc_init(0, 8);
return err;
}
#endif
diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h
index 405abd5..d4d370f 100644
--- a/include/configs/smdk5250.h
+++ b/include/configs/smdk5250.h
@@ -69,7 +69,7 @@
/* select serial console configuration */
#define CONFIG_SERIAL_MULTI
-#define CONFIG_SERIAL1 /* use SERIAL 1 */
+#define CONFIG_SERIAL3 /* use SERIAL 3 */
#define CONFIG_BAUDRATE115200
#define EXYNOS5_DEFAULT_UART_OFFSET0x01
--
1.7.4.4
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Re: [U-Boot] [PATCH 8/9 V2] EXYNOS5 : Modify pinnumx settings as per Exynos5250 Rev 1.0
Hi Rajeshwari,
On 06/20/2012 08:11 PM, Rajeshwari Shinde wrote:
> This patch modifies the pinmux settings of MMC and UART as per
> Exynos5250 Rev 1.0
>
> Signed-off-by: Rajeshwari Shinde
> ---
> Chnages in V2:
> - None
> arch/arm/cpu/armv7/exynos/pinmux.c | 18 +-
> 1 files changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c
> b/arch/arm/cpu/armv7/exynos/pinmux.c
> index d2b7d2c..7611c7a 100644
> --- a/arch/arm/cpu/armv7/exynos/pinmux.c
> +++ b/arch/arm/cpu/armv7/exynos/pinmux.c
> @@ -40,8 +40,8 @@ static void exynos5_uart_config(int peripheral)
> count = 4;
> break;
> case PERIPH_ID_UART1:
> - bank = &gpio1->a0;
> - start = 4;
> + bank = &gpio1->d0;
> + start = 0;
> count = 4;
> break;
> case PERIPH_ID_UART2:
> @@ -66,25 +66,25 @@ static int exynos5_mmc_config(int peripheral, int flags)
> struct exynos5_gpio_part1 *gpio1 =
> (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
> struct s5p_gpio_bank *bank, *bank_ext;
> - int i;
> + int i, start;
>
> switch (peripheral) {
> case PERIPH_ID_SDMMC0:
> bank = &gpio1->c0;
> bank_ext = &gpio1->c1;
> + start = 0;
> break;
> case PERIPH_ID_SDMMC1:
> - bank = &gpio1->c1;
> + bank = &gpio1->c2;
> bank_ext = NULL;
> break;
> case PERIPH_ID_SDMMC2:
> - bank = &gpio1->c2;
> - bank_ext = &gpio1->c3;
> - break;
> - case PERIPH_ID_SDMMC3:
> bank = &gpio1->c3;
> bank_ext = NULL;
> break;
if SDMMC2 is supported 8BIT_MODE. Need gpio1->c4,
> + case PERIPH_ID_SDMMC3:
> + debug("SDMMC3 not supported yet");
> + return -1;
> }
> if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
> debug("SDMMC device %d does not support 8bit mode",
> @@ -92,7 +92,7 @@ static int exynos5_mmc_config(int peripheral, int flags)
> return -1;
> }
> if (flags & PINMUX_FLAG_8BIT_MODE) {
> - for (i = 3; i <= 6; i++) {
> + for (i = start; i <= (start + 3); i++) {
> s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3));
At EVT1, i known GPIO_FUNC(0x3) is wrong.
> s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
> s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
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Re: [U-Boot] [PATCH 8/9 V2] EXYNOS5 : Modify pinnumx settings as per Exynos5250 Rev 1.0
Hi Jaehoon Chung
On Wed, Jun 20, 2012 at 5:28 PM, Jaehoon Chung wrote:
> Hi Rajeshwari,
>
> On 06/20/2012 08:11 PM, Rajeshwari Shinde wrote:
>
>> This patch modifies the pinmux settings of MMC and UART as per
>> Exynos5250 Rev 1.0
>>
>> Signed-off-by: Rajeshwari Shinde
>> ---
>> Chnages in V2:
>> - None
>> arch/arm/cpu/armv7/exynos/pinmux.c | 18 +-
>> 1 files changed, 9 insertions(+), 9 deletions(-)
>>
>> diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c
>> b/arch/arm/cpu/armv7/exynos/pinmux.c
>> index d2b7d2c..7611c7a 100644
>> --- a/arch/arm/cpu/armv7/exynos/pinmux.c
>> +++ b/arch/arm/cpu/armv7/exynos/pinmux.c
>> @@ -40,8 +40,8 @@ static void exynos5_uart_config(int peripheral)
>> count = 4;
>> break;
>> case PERIPH_ID_UART1:
>> - bank = &gpio1->a0;
>> - start = 4;
>> + bank = &gpio1->d0;
>> + start = 0;
>> count = 4;
>> break;
>> case PERIPH_ID_UART2:
>> @@ -66,25 +66,25 @@ static int exynos5_mmc_config(int peripheral, int flags)
>> struct exynos5_gpio_part1 *gpio1 =
>> (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
>> struct s5p_gpio_bank *bank, *bank_ext;
>> - int i;
>> + int i, start;
>>
>> switch (peripheral) {
>> case PERIPH_ID_SDMMC0:
>> bank = &gpio1->c0;
>> bank_ext = &gpio1->c1;
>> + start = 0;
>> break;
>> case PERIPH_ID_SDMMC1:
>> - bank = &gpio1->c1;
>> + bank = &gpio1->c2;
>> bank_ext = NULL;
>> break;
>> case PERIPH_ID_SDMMC2:
>> - bank = &gpio1->c2;
>> - bank_ext = &gpio1->c3;
>> - break;
>> - case PERIPH_ID_SDMMC3:
>> bank = &gpio1->c3;
>> bank_ext = NULL;
>> break;
>
> if SDMMC2 is supported 8BIT_MODE. Need gpio1->c4,
-- ohh ok the manual which I have does not have gpio1->c4. I possible
can you send me the user manual which you are referring to.
>
>> + case PERIPH_ID_SDMMC3:
>> + debug("SDMMC3 not supported yet");
>> + return -1;
>
>> }
>> if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) {
>> debug("SDMMC device %d does not support 8bit mode",
>> @@ -92,7 +92,7 @@ static int exynos5_mmc_config(int peripheral, int flags)
>> return -1;
>> }
>> if (flags & PINMUX_FLAG_8BIT_MODE) {
>> - for (i = 3; i <= 6; i++) {
>> + for (i = start; i <= (start + 3); i++) {
>> s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3));
>
> At EVT1, i known GPIO_FUNC(0x3) is wrong.
-- Ohh ok
>
>> s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
>> s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
>
>
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Regards,
Rajeshwari Shinde.
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Re: [U-Boot] [PATCH v2 1/2] CONFIG_SYS_BAUDRATE_TABLE: Add , place there
On 06/19/2012 01:50 PM, Wolfgang Denk wrote:
> Dear Tom Rini,
>
> In message <1335480396-29478-1-git-send-email-tr...@ti.com> you wrote:
>> We provide a default table of { 9600, 19200, 38400, 57600, 115200 }
>> in which mkconfig places after in
>> the generated config file. This is used when a board has not set its
>> own table. A number of boards set values below 9600 but it is my belief
>> that this was done for completeness rather than as a requirement so they
>> have opted to the new default table.
>>
>> Signed-off-by: Tom Rini
>
> Sorry, this doesn't apply any more, Can you please rebase?
As you can see from Stefano's ack, it's made, but stuck in the
moderation queue for size. Should I post it to the wiki?
--
Tom
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[U-Boot] [PATCH v3 0/6] USB and cache related fixes
Hey all, In commit b8adb12 the cache flushing behavior was changed for the EHCI stack. This change showed a few different problems on TI platforms (where our cacheline size is 64 not 32). First, the dcache_off call that ehci-omap had been doing was now not happening soon enough to paper over the cache issues. This call is removed in patch 1. The second patch deal with the same problem in EHCI and MUSB. The USB spec says that 32 bytes is the minimum alignment but we need larger alignment when the cache is larger. Note that we can't use MAX() here as gcc doesn't allow that expansion inside of align(..). Patches 3 to 6 disable dcache support at build time on all platforms that enable CONFIG_USB_EHCI_OMAP because performing a run-time 'dcache off' operation leaves USB unusable due to the unaligned flushes that are still attempted. Run-time testing on an omap3_beagle shows a very slight (less than half a second, checked with grabserial) increase in load time for a 3.5-rc3 kernel image from SD card. Note that otherwise a tftp load takes minutes to complete rather than seconds due to all of the console spam. Tested on omap3_beagle (which was previously broken) and a MAKEALL -a arm looks good too. Changes in v3: - Drop the cache_v7.c change and instead make all CONFIG_USB_EHCI_OMAP boards disable DCACHE at build time. Changes in v2: - Condense last two patches into one that puts the test into -- Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 1/6] ehci-omap: Do not call dcache_off from omap_ehci_hcd_init
This has never been completely sufficient and now happens too late to paper over the cache coherency problems with the current USB stack. Cc: Marek Vasut Signed-off-by: Tom Rini --- drivers/usb/host/ehci-omap.c |1 - 1 file changed, 1 deletion(-) diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c index 1ed7710..292673b 100644 --- a/drivers/usb/host/ehci-omap.c +++ b/drivers/usb/host/ehci-omap.c @@ -246,7 +246,6 @@ int omap_ehci_hcd_init(struct omap_usbhs_board_data *usbhs_pdata) if (is_ehci_phy_mode(usbhs_pdata->port_mode[i])) omap_ehci_soft_phy_reset(i); - dcache_disable(); hccr = (struct ehci_hccr *)(OMAP_EHCI_BASE); hcor = (struct ehci_hcor *)(OMAP_EHCI_BASE + 0x10); -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 2/6] ehci-hcd.c, musb_core, usb.h: Add USB_DMA_MINALIGN define for cache alignment
The USB spec says that 32 bytes is the minimum required alignment.
However on some platforms we have a larger minimum requirement for cache
coherency. In those cases, use that value rather than the USB spec
minimum. We add a cpp check to to define USB_DMA_MINALIGN and
make use of it in ehci-hcd.c and musb_core.h. We cannot use MAX() here
as we are not allowed to have tests inside of align(...).
Cc: Marek Vasut
Signed-off-by: Tom Rini
--
Changes in v2:
- Move test to , expand comment.
---
drivers/usb/host/ehci-hcd.c | 13 +++--
drivers/usb/musb/musb_core.h |2 +-
include/usb.h| 10 ++
3 files changed, 18 insertions(+), 7 deletions(-)
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 04300be..5a86117 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -29,12 +29,13 @@
#include "ehci.h"
-int rootdev;
-struct ehci_hccr *hccr;/* R/O registers, not need for volatile */
-volatile struct ehci_hcor *hcor;
+int rootdev __attribute__((aligned(USB_DMA_MINALIGN)));
+/* R/O registers, not need for volatile */
+struct ehci_hccr *hccr __attribute__((aligned(USB_DMA_MINALIGN)));
+volatile struct ehci_hcor *hcor __attribute__((aligned(USB_DMA_MINALIGN)));
static uint16_t portreset;
-static struct QH qh_list __attribute__((aligned(32)));
+static struct QH qh_list __attribute__((aligned(USB_DMA_MINALIGN)));
static struct descriptor {
struct usb_hub_descriptor hub;
@@ -207,8 +208,8 @@ static int
ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
int length, struct devrequest *req)
{
- static struct QH qh __attribute__((aligned(32)));
- static struct qTD qtd[3] __attribute__((aligned (32)));
+ static struct QH qh __attribute__((aligned(USB_DMA_MINALIGN)));
+ static struct qTD qtd[3] __attribute__((aligned(USB_DMA_MINALIGN)));
int qtd_counter = 0;
volatile struct qTD *vtd;
diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h
index a8adcce..e914369 100644
--- a/drivers/usb/musb/musb_core.h
+++ b/drivers/usb/musb/musb_core.h
@@ -145,7 +145,7 @@ struct musb_regs {
struct musb_epN_regs epN;
} ep[16];
-} __attribute__((packed, aligned(32)));
+} __attribute__((packed, aligned(USB_DMA_MINALIGN)));
#endif
/*
diff --git a/include/usb.h b/include/usb.h
index 6da91e7..ba3d169 100644
--- a/include/usb.h
+++ b/include/usb.h
@@ -29,6 +29,16 @@
#include
#include
+/*
+ * The EHCI spec says that we must align to at least 32 bytes. However,
+ * some platforms require larger alignment.
+ */
+#if ARCH_DMA_MINALIGN > 32
+#define USB_DMA_MINALIGN ARCH_DMA_MINALIGN
+#else
+#define USB_DMA_MINALIGN 32
+#endif
+
/* Everything is aribtrary */
#define USB_ALTSETTINGALLOC4
#define USB_MAXALTSETTING 128 /* Hard limit */
--
1.7.9.5
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[U-Boot] [PATCH v3 5/6] omap4_panda: Disable DCACHE since USB EHCI is enabled
USB EHCI and DCACHE are not compatible, so disable DCACHE support at build-time as run-time disable is insufficient for USB use. Cc: Sricharan R Signed-off-by: Tom Rini --- include/configs/omap4_panda.h |1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h index b4756be..468cf7a 100644 --- a/include/configs/omap4_panda.h +++ b/include/configs/omap4_panda.h @@ -38,6 +38,7 @@ #define CONFIG_USB_HOST #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_OMAP +#define CONFIG_SYS_DCACHE_OFF /* USB_EHCI is unusable with DCACHE support */ #define CONFIG_USB_STORAGE #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 3/6] mcx: Disable DCACHE since USB EHCI is enabled
USB EHCI and DCACHE are not compatible, so disable DCACHE support at build-time as run-time disable is insufficient for USB use. Cc: Ilya Yanok Signed-off-by: Tom Rini --- include/configs/mcx.h |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/mcx.h b/include/configs/mcx.h index f6a83a8..0b29b08 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -110,9 +110,9 @@ #define CONFIG_OMAP3_GPIO_5 #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_OMAP +#define CONFIG_SYS_DCACHE_OFF /* USB_EHCI is unusable with DCACHE support */ #define CONFIG_USB_ULPI #define CONFIG_USB_ULPI_VIEWPORT_OMAP -/*#define CONFIG_EHCI_DCACHE*/ /* leave it disabled for now */ #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 154 #define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 152 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 6/6] tam3517-common: Disable DCACHE since USB EHCI is enabled
USB EHCI and DCACHE are not compatible, so disable DCACHE support at build-time as run-time disable is insufficient for USB use. Cc: Stefano Babic Signed-off-by: Tom Rini --- include/configs/tam3517-common.h |1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index 3fc2c44..b9c96b9 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -100,6 +100,7 @@ #define CONFIG_OMAP3_GPIO_5 #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_OMAP +#define CONFIG_SYS_DCACHE_OFF /* USB_EHCI is unusable with DCACHE support */ #define CONFIG_USB_ULPI #define CONFIG_USB_ULPI_VIEWPORT_OMAP #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25 -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 4/6] omap3_beagle: Disable DCACHE since USB EHCI is enabled
USB EHCI and DCACHE are not compatible, so disable DCACHE support at build-time as run-time disable is insufficient for USB use. Signed-off-by: Tom Rini --- include/configs/omap3_beagle.h |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index b891ee4..79560d7 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -131,7 +131,7 @@ #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_OMAP -/*#define CONFIG_EHCI_DCACHE*/ /* leave it disabled for now */ +#define CONFIG_SYS_DCACHE_OFF /* USB_EHCI is unusable with DCACHE support */ #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 147 #define CONFIG_USB_ULPI -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 1/1] tegra: usb: Fix device enumeration problem of USB1
On 06/20/2012 03:15 AM, Jim Lin wrote:
> A known hardware issue of USB1 port where bit 1 (connect status
> change) of PORTSC register will be set after issuing Port Reset
> (like "usb reset" in u-boot command line).
> This will be treated as an error and stops later device enumeration.
>
> Therefore we clear that bit after Port Reset in order to proceed
> later device enumeration.
>
> Signed-off-by: Jim Lin
Acked-by: Stephen Warren
But a couple of nits below,
> diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
> +/*
> + * A known hardware issue where Connect Status Change bit of PORTSC register
> + * of USB1 controller will be set after Port Reset.
> + * We have to clear it in order for later device enumeration to proceed.
> + */
It might be worth adding a note in that comment saying that this
overrides a weak symbol in ehci-hcd.c so that people know where it's called.
> +void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
> +{
> + uint32_t my_reg;
I would rename this variable just "reg"; the variable doesn't belong to
a person, and names with "my" in just make me cringe.
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Re: [U-Boot] [PATCH 2/4] cache_v7: Check for dcache enablement in dcache flush functions
Hi Sricharan, On 06/15/2012 07:48 AM, R, Sricharan wrote: Hi, On Fri, Jun 15, 2012 at 12:31 AM, Tom Rini wrote: If we are built with D-CACHE enabled but have run 'dcache off' and then attempt to flush unaligned regions we spam the console with problems that aren't true (as the cache was off). Today we do cache maintenance operations after the dcache is turned off. One example is before jumping to kernel, we try to invalidate the caches, in cache turned off state. So with this patch those maintenance calls will do nothing, which is not correct. Ah yes, But, shouldn't we be doing these same operations as part of turning the cache off? The problem is that while turning of dcaches, we flush it, and turn cache and MMU off. But these operations are not happening automatically in a single call. So there is a chance of valid entries present in cache even after it is OFF. I think this is what we need to fix. Otherwise, Tom's change looks good to me. How about an invalidate in dcache_disable() or something like that? br, Aneesh ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 1/2] CONFIG_SYS_BAUDRATE_TABLE: Add , place there
Dear Tom Rini,
In message <1340146475-15969-1-git-send-email-tr...@ti.com> you wrote:
> We provide a default table of { 9600, 19200, 38400, 57600, 115200 }
> in which mkconfig places after in
> the generated config file. This is used when a board has not set its
> own table.
>
> Signed-off-by: Tom Rini
>
> ---
> Changes in v4:
> - Rebase to current master
> - Catch a few more boards after auditing all users after rebase
>
> Changes in v3:
> - Only modify boards that had the default values, ignoring ones that set
> slower rates too (per Wolfgang Denk)
>
> Changes in v2:
> - Create, use rather than mkconfig directly for
> this table (per Mike Frysinger).
> ---
> arch/blackfin/include/asm/config.h |3 ---
> board/fads/fads.h |2 --
> include/config_fallbacks.h | 16
> include/configs/A3000.h|1 -
> include/configs/AMX860.h |2 --
> include/configs/Adder.h|2 --
> include/configs/BMW.h |1 -
> include/configs/CPC45.h|1 -
> include/configs/CPU86.h|2 --
> include/configs/CPU87.h|2 --
> include/configs/CU824.h|1 -
> include/configs/EB+MCF-EV123.h |1 -
> include/configs/ELPT860.h |1 -
> include/configs/EP88x.h|2 --
> include/configs/ESTEEM192E.h |4
> include/configs/ETX094.h |2 --
> include/configs/FADS823.h |2 --
> include/configs/FADS850SAR.h |2 --
> include/configs/FLAGADM.h |2 --
> include/configs/FPS850L.h |2 --
> include/configs/FPS860L.h |2 --
> include/configs/GEN860T.h | 10 --
> include/configs/HIDDEN_DRAGON.h|1 -
> include/configs/IAD210.h |2 --
> include/configs/ICU862.h |2 --
> include/configs/IDS8247.h |2 --
> include/configs/IP860.h|2 --
> include/configs/IPHASE4539.h |2 --
> include/configs/ISPAN.h|2 --
> include/configs/IVML24.h |2 --
> include/configs/IVMS8.h|2 --
> include/configs/LANTEC.h |2 --
> include/configs/M5208EVBE.h|1 -
> include/configs/M52277EVB.h|1 -
> include/configs/M5235EVB.h |1 -
> include/configs/M5249EVB.h |1 -
> include/configs/M5253DEMO.h|1 -
> include/configs/M5253EVBE.h|1 -
> include/configs/M5271EVB.h |1 -
> include/configs/M5272C3.h |1 -
> include/configs/M5275EVB.h |1 -
> include/configs/M5282EVB.h |1 -
> include/configs/M53017EVB.h|1 -
> include/configs/M5329EVB.h |1 -
> include/configs/M5373EVB.h |1 -
> include/configs/M54451EVB.h|1 -
> include/configs/M54455EVB.h|1 -
> include/configs/M5475EVB.h |1 -
> include/configs/M5485EVB.h |1 -
> include/configs/MBX.h |2 --
> include/configs/MBX860T.h |2 --
> include/configs/MHPC.h |2 --
> include/configs/MOUSSE.h |2 --
> include/configs/MUSENKI.h |1 -
> include/configs/MVBLUE.h |1 -
> include/configs/MVS1.h |2 --
> include/configs/NETPHONE.h |2 --
> include/configs/NETTA.h|2 --
> include/configs/NETTA2.h |2 --
> include/configs/NETVIA.h |2 --
> include/configs/NSCU.h |2 --
> include/configs/NX823.h|2 --
> include/configs/PCIPPC2.h |1 -
> include/configs/PCIPPC6.h |1 -
> include/configs/PM826.h|2 --
> include/configs/PM828.h|2 --
> include/configs/PMC405DE.h |4
> include/configs/PN62.h |1 -
> include/configs/QS823.h|2 --
> include/configs/QS850.h|2 --
> include/configs/QS860T.h |2 --
> include/configs/R360MPI.h |2 --
> include/configs/RBC823.h |2 --
> include/configs/RPXClassic.h |2 --
> include/configs/RPXlite.h |2 --
> include/configs/RPXlite_DW.h |1 -
> include/configs/RPXsuper.h |3 ---
> include/configs/RRvision.h |2 --
> include/configs/SCM.h |2 --
> include/configs/SM850.h|2 --
> include/configs/SPD823TS.h |2 --
> include/configs/SX1.h |2 --
> include/configs/SXNI855T.h |2 --
> i
Re: [U-Boot] [PATCH v4 2/2] hush.c: Move default CONFIG_SYS_PROMPT_HUSH_PS2 to hush.c
Dear Tom Rini, In message <1340146475-15969-2-git-send-email-tr...@ti.com> you wrote: > Exactly one board has defined CONFIG_SYS_PROMPT_HUSH_PS2 to a value > different than "> " which is vision2. I have Cc'd the maintainer here > as I strongly suspect this is a bug rather than intentional behavior. > > Cc: Stefano Babic > Signed-off-by: Tom Rini > > --- > Changes in v4: > - Rebase to current master > --- > board/fads/fads.h |1 - > common/hush.c |3 +++ > include/configs/AP1000.h |1 - > include/configs/ASH405.h |3 --- > include/configs/Adder.h|1 - > include/configs/CATcenter.h|3 --- > include/configs/CMS700.h |3 --- > include/configs/CPC45.h|3 --- > include/configs/CPCI2DP.h |3 --- > include/configs/CPCI405.h |3 --- > include/configs/CPCI4052.h |3 --- > include/configs/CPCI405AB.h|3 --- > include/configs/CPCI405DT.h|3 --- > include/configs/CPCI750.h |1 - > include/configs/CRAYL1.h |1 - > include/configs/CU824.h|3 --- > include/configs/DB64360.h |1 - > include/configs/DB64460.h |1 - > include/configs/DP405.h|3 --- > include/configs/EB+MCF-EV123.h |1 - > include/configs/EP88x.h|1 - > include/configs/EVB64260.h |1 - > include/configs/FPS850L.h |3 --- > include/configs/FPS860L.h |3 --- > include/configs/G2000.h|3 --- > include/configs/GEN860T.h |1 - > include/configs/HH405.h|3 --- > include/configs/HUB405.h |3 --- > include/configs/HWW1U1A.h |1 - > include/configs/ISPAN.h|1 - > include/configs/IceCube.h |1 - > include/configs/JSE.h |3 --- > include/configs/KAREF.h|1 - > include/configs/M5271EVB.h |1 - > include/configs/MBX.h |3 --- > include/configs/MERGERBOX.h|1 - > include/configs/METROBOX.h |1 - > include/configs/MIP405.h |1 - > include/configs/MPC8260ADS.h |1 - > include/configs/MPC8308RDB.h |1 - > include/configs/MPC8313ERDB.h |1 - > include/configs/MPC8315ERDB.h |3 --- > include/configs/MPC8323ERDB.h |3 --- > include/configs/MPC832XEMDS.h |3 --- > include/configs/MPC8349EMDS.h |3 --- > include/configs/MPC8349ITX.h |1 - > include/configs/MPC8360EMDS.h |3 --- > include/configs/MPC8360ERDK.h |3 --- > include/configs/MPC837XEMDS.h |3 --- > include/configs/MPC837XERDB.h |3 --- > include/configs/MPC8536DS.h|3 --- > include/configs/MPC8540ADS.h |1 - > include/configs/MPC8541CDS.h |1 - > include/configs/MPC8544DS.h|3 --- > include/configs/MPC8548CDS.h |3 --- > include/configs/MPC8555CDS.h |1 - > include/configs/MPC8560ADS.h |1 - > include/configs/MPC8568MDS.h |1 - > include/configs/MPC8569MDS.h |1 - > include/configs/MPC8572DS.h|3 --- > include/configs/MPC8610HPCD.h |3 --- > include/configs/MPC8641HPCN.h |3 --- > include/configs/MVBC_P.h |1 - > include/configs/MVBLM7.h |1 - > include/configs/MVS1.h |3 --- > include/configs/MVSMR.h|1 - > include/configs/NETPHONE.h |1 - > include/configs/NETTA.h|1 - > include/configs/NETTA2.h |1 - > include/configs/NSCU.h |3 --- > include/configs/P1010RDB.h |3 --- > include/configs/P1022DS.h |1 - > include/configs/P1023RDS.h |3 --- > include/configs/P1_P2_RDB.h|3 --- > include/configs/P2020COME.h|3 --- > include/configs/P2020DS.h |3 --- > include/configs/P2041RDB.h |1 - > include/configs/P3G4.h |1 - > include/configs/PCI405.h |3 --- > include/configs/PCIPPC2.h |3 --- > include/configs/PCIPPC6.h |3 --- > include/configs/PIP405.h |1 - > include/configs/PK1C20.h |1 - > include/configs/PLU405.h |3 --- > include/configs/PMC405.h |3 --- > include/configs/PPChameleonEVB.h |3 --- > include/configs/QS823.h|1 - > include/configs/QS850.h|1 - > in
Re: [U-Boot] [PATCH v3 2/6] ehci-hcd.c, musb_core, usb.h: Add USB_DMA_MINALIGN define for cache alignment
Dear Tom Rini,
> The USB spec says that 32 bytes is the minimum required alignment.
> However on some platforms we have a larger minimum requirement for cache
> coherency. In those cases, use that value rather than the USB spec
> minimum. We add a cpp check to to define USB_DMA_MINALIGN and
> make use of it in ehci-hcd.c and musb_core.h. We cannot use MAX() here
> as we are not allowed to have tests inside of align(...).
>
> Cc: Marek Vasut
> Signed-off-by: Tom Rini
>
> --
> Changes in v2:
> - Move test to , expand comment.
> ---
> drivers/usb/host/ehci-hcd.c | 13 +++--
> drivers/usb/musb/musb_core.h |2 +-
> include/usb.h| 10 ++
> 3 files changed, 18 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
> index 04300be..5a86117 100644
> --- a/drivers/usb/host/ehci-hcd.c
> +++ b/drivers/usb/host/ehci-hcd.c
> @@ -29,12 +29,13 @@
>
> #include "ehci.h"
>
> -int rootdev;
> -struct ehci_hccr *hccr; /* R/O registers, not need for volatile */
> -volatile struct ehci_hcor *hcor;
> +int rootdev __attribute__((aligned(USB_DMA_MINALIGN)));
> +/* R/O registers, not need for volatile */
> +struct ehci_hccr *hccr __attribute__((aligned(USB_DMA_MINALIGN)));
> +volatile struct ehci_hcor *hcor
> __attribute__((aligned(USB_DMA_MINALIGN)));
^ these need to be aligned too?
>
> static uint16_t portreset;
> -static struct QH qh_list __attribute__((aligned(32)));
> +static struct QH qh_list __attribute__((aligned(USB_DMA_MINALIGN)));
>
> static struct descriptor {
> struct usb_hub_descriptor hub;
> @@ -207,8 +208,8 @@ static int
> ehci_submit_async(struct usb_device *dev, unsigned long pipe, void
> *buffer, int length, struct devrequest *req)
> {
> - static struct QH qh __attribute__((aligned(32)));
> - static struct qTD qtd[3] __attribute__((aligned (32)));
> + static struct QH qh __attribute__((aligned(USB_DMA_MINALIGN)));
> + static struct qTD qtd[3] __attribute__((aligned(USB_DMA_MINALIGN)));
> int qtd_counter = 0;
>
> volatile struct qTD *vtd;
> diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h
> index a8adcce..e914369 100644
> --- a/drivers/usb/musb/musb_core.h
> +++ b/drivers/usb/musb/musb_core.h
> @@ -145,7 +145,7 @@ struct musb_regs {
> struct musb_epN_regs epN;
> } ep[16];
>
> -} __attribute__((packed, aligned(32)));
> +} __attribute__((packed, aligned(USB_DMA_MINALIGN)));
> #endif
>
> /*
> diff --git a/include/usb.h b/include/usb.h
> index 6da91e7..ba3d169 100644
> --- a/include/usb.h
> +++ b/include/usb.h
> @@ -29,6 +29,16 @@
> #include
> #include
>
> +/*
> + * The EHCI spec says that we must align to at least 32 bytes. However,
> + * some platforms require larger alignment.
> + */
> +#if ARCH_DMA_MINALIGN > 32
> +#define USB_DMA_MINALIGN ARCH_DMA_MINALIGN
> +#else
> +#define USB_DMA_MINALIGN 32
> +#endif
> +
> /* Everything is aribtrary */
> #define USB_ALTSETTINGALLOC 4
> #define USB_MAXALTSETTING128 /* Hard limit */
Best regards,
Marek Vasut
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 2/6] ehci-hcd.c, musb_core, usb.h: Add USB_DMA_MINALIGN define for cache alignment
On Wed, Jun 20, 2012 at 09:00:45PM +0200, Marek Vasut wrote: > Dear Tom Rini, > > > The USB spec says that 32 bytes is the minimum required alignment. > > However on some platforms we have a larger minimum requirement for cache > > coherency. In those cases, use that value rather than the USB spec > > minimum. We add a cpp check to to define USB_DMA_MINALIGN and > > make use of it in ehci-hcd.c and musb_core.h. We cannot use MAX() here > > as we are not allowed to have tests inside of align(...). > > > > Cc: Marek Vasut > > Signed-off-by: Tom Rini > > > > -- > > Changes in v2: > > - Move test to , expand comment. > > --- > > drivers/usb/host/ehci-hcd.c | 13 +++-- > > drivers/usb/musb/musb_core.h |2 +- > > include/usb.h| 10 ++ > > 3 files changed, 18 insertions(+), 7 deletions(-) > > > > diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c > > index 04300be..5a86117 100644 > > --- a/drivers/usb/host/ehci-hcd.c > > +++ b/drivers/usb/host/ehci-hcd.c > > @@ -29,12 +29,13 @@ > > > > #include "ehci.h" > > > > -int rootdev; > > -struct ehci_hccr *hccr;/* R/O registers, not need for volatile */ > > -volatile struct ehci_hcor *hcor; > > +int rootdev __attribute__((aligned(USB_DMA_MINALIGN))); > > +/* R/O registers, not need for volatile */ > > +struct ehci_hccr *hccr __attribute__((aligned(USB_DMA_MINALIGN))); > > +volatile struct ehci_hcor *hcor > > __attribute__((aligned(USB_DMA_MINALIGN))); > > ^ these need to be aligned too? Yes, these were the first and easy to spot ones in the cache flush messages, I would swear. -- Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 2/6] ehci-hcd.c, musb_core, usb.h: Add USB_DMA_MINALIGN define for cache alignment
Dear Tom Rini, > On Wed, Jun 20, 2012 at 09:00:45PM +0200, Marek Vasut wrote: > > Dear Tom Rini, > > > > > The USB spec says that 32 bytes is the minimum required alignment. > > > However on some platforms we have a larger minimum requirement for > > > cache coherency. In those cases, use that value rather than the USB > > > spec minimum. We add a cpp check to to define > > > USB_DMA_MINALIGN and make use of it in ehci-hcd.c and musb_core.h. We > > > cannot use MAX() here as we are not allowed to have tests inside of > > > align(...). > > > > > > Cc: Marek Vasut > > > Signed-off-by: Tom Rini > > > > > > -- > > > Changes in v2: > > > - Move test to , expand comment. > > > --- > > > > > > drivers/usb/host/ehci-hcd.c | 13 +++-- > > > drivers/usb/musb/musb_core.h |2 +- > > > include/usb.h| 10 ++ > > > 3 files changed, 18 insertions(+), 7 deletions(-) > > > > > > diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c > > > index 04300be..5a86117 100644 > > > --- a/drivers/usb/host/ehci-hcd.c > > > +++ b/drivers/usb/host/ehci-hcd.c > > > @@ -29,12 +29,13 @@ > > > > > > #include "ehci.h" > > > > > > -int rootdev; > > > -struct ehci_hccr *hccr; /* R/O registers, not need for volatile */ > > > -volatile struct ehci_hcor *hcor; > > > +int rootdev __attribute__((aligned(USB_DMA_MINALIGN))); > > > +/* R/O registers, not need for volatile */ > > > +struct ehci_hccr *hccr __attribute__((aligned(USB_DMA_MINALIGN))); > > > +volatile struct ehci_hcor *hcor > > > __attribute__((aligned(USB_DMA_MINALIGN))); > > > > ^ these need to be aligned too? > > Yes, these were the first and easy to spot ones in the cache flush > messages, I would swear. hcor and hccr are register locations though ... so it's pretty weird. Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 2/6] ehci-hcd.c, musb_core, usb.h: Add USB_DMA_MINALIGN define for cache alignment
On Wed, Jun 20, 2012 at 11:15:26PM +0200, Marek Vasut wrote: > Dear Tom Rini, > > > On Wed, Jun 20, 2012 at 09:00:45PM +0200, Marek Vasut wrote: > > > Dear Tom Rini, > > > > > > > The USB spec says that 32 bytes is the minimum required alignment. > > > > However on some platforms we have a larger minimum requirement for > > > > cache coherency. In those cases, use that value rather than the USB > > > > spec minimum. We add a cpp check to to define > > > > USB_DMA_MINALIGN and make use of it in ehci-hcd.c and musb_core.h. We > > > > cannot use MAX() here as we are not allowed to have tests inside of > > > > align(...). > > > > > > > > Cc: Marek Vasut > > > > Signed-off-by: Tom Rini > > > > > > > > -- > > > > Changes in v2: > > > > - Move test to , expand comment. > > > > --- > > > > > > > > drivers/usb/host/ehci-hcd.c | 13 +++-- > > > > drivers/usb/musb/musb_core.h |2 +- > > > > include/usb.h| 10 ++ > > > > 3 files changed, 18 insertions(+), 7 deletions(-) > > > > > > > > diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c > > > > index 04300be..5a86117 100644 > > > > --- a/drivers/usb/host/ehci-hcd.c > > > > +++ b/drivers/usb/host/ehci-hcd.c > > > > @@ -29,12 +29,13 @@ > > > > > > > > #include "ehci.h" > > > > > > > > -int rootdev; > > > > -struct ehci_hccr *hccr;/* R/O registers, not need for volatile > > > > */ > > > > -volatile struct ehci_hcor *hcor; > > > > +int rootdev __attribute__((aligned(USB_DMA_MINALIGN))); > > > > +/* R/O registers, not need for volatile */ > > > > +struct ehci_hccr *hccr __attribute__((aligned(USB_DMA_MINALIGN))); > > > > +volatile struct ehci_hcor *hcor > > > > __attribute__((aligned(USB_DMA_MINALIGN))); > > > > > > ^ these need to be aligned too? > > > > Yes, these were the first and easy to spot ones in the cache flush > > messages, I would swear. > > hcor and hccr are register locations though ... so it's pretty weird. OK, now that I look harder at the messages, doing that is only masking a problem. At issue (from u-boot.map): .bss 0x801586c0 0x1c0 drivers/usb/host/libusb_host.o 0x80158860hcor And a message of: ERROR: v7_dcache_inval_range - stop address is not aligned - 0x9ffbc860 Using 'bdinfo' to see reloc offset gives us hcor, but _end_ not start means it's something within the anonymous part of the bss and padding hcor out just masks the real problem. I'll resubmit a v4 shortly. Thanks! -- Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 0/6] USB and cache related fixes
Hey all, In commit b8adb12 the cache flushing behavior was changed for the EHCI stack. This change showed a few different problems on TI platforms (where our cacheline size is 64 not 32). First, the dcache_off call that ehci-omap had been doing was now not happening soon enough to paper over the cache issues. This call is removed in patch 1. The second patch deal with the same problem in EHCI and MUSB. The USB spec says that 32 bytes is the minimum alignment but we need larger alignment when the cache is larger. Note that we can't use MAX() here as gcc doesn't allow that expansion inside of align(..). Patches 3 to 6 disable dcache support at build time on all platforms that enable CONFIG_USB_EHCI_OMAP because performing a run-time 'dcache off' operation leaves USB unusable due to the unaligned flushes that are still attempted. Run-time testing on an omap3_beagle shows a very slight (less than half a second, checked with grabserial) increase in load time for a 3.5-rc3 kernel image from SD card. Note that otherwise a tftp load takes minutes to complete rather than seconds due to all of the console spam. Tested on omap3_beagle (which was previously broken) and a MAKEALL -a arm looks good too. Changes in v4: - Drop alignment on rootdev/hccr/hcor as a double-check showed that was masking an alignment problem elsewhere (Marek Vasut) Changes in v3: - Drop the cache_v7.c change and instead make all CONFIG_USB_EHCI_OMAP boards disable DCACHE at build time. Changes in v2: - Condense last two patches into one that puts the test into -- Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 2/6] ehci-hcd.c, musb_core, usb.h: Add USB_DMA_MINALIGN define for cache alignment
The USB spec says that 32 bytes is the minimum required alignment.
However on some platforms we have a larger minimum requirement for cache
coherency. In those cases, use that value rather than the USB spec
minimum. We add a cpp check to to define USB_DMA_MINALIGN and
make use of it in ehci-hcd.c and musb_core.h. We cannot use MAX() here
as we are not allowed to have tests inside of align(...).
Cc: Marek Vasut
Signed-off-by: Tom Rini
--
Changes in v4:
- Re-checking shows we do not need to add alignment to rootdev/hcor/hccr
Changes in v2:
- Move test to , expand comment.
---
drivers/usb/host/ehci-hcd.c |6 +++---
drivers/usb/musb/musb_core.h |2 +-
include/usb.h| 10 ++
3 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 04300be..d34c675 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -34,7 +34,7 @@ struct ehci_hccr *hccr; /* R/O registers, not need for
volatile */
volatile struct ehci_hcor *hcor;
static uint16_t portreset;
-static struct QH qh_list __attribute__((aligned(32)));
+static struct QH qh_list __attribute__((aligned(USB_DMA_MINALIGN)));
static struct descriptor {
struct usb_hub_descriptor hub;
@@ -207,8 +207,8 @@ static int
ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
int length, struct devrequest *req)
{
- static struct QH qh __attribute__((aligned(32)));
- static struct qTD qtd[3] __attribute__((aligned (32)));
+ static struct QH qh __attribute__((aligned(USB_DMA_MINALIGN)));
+ static struct qTD qtd[3] __attribute__((aligned(USB_DMA_MINALIGN)));
int qtd_counter = 0;
volatile struct qTD *vtd;
diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h
index a8adcce..e914369 100644
--- a/drivers/usb/musb/musb_core.h
+++ b/drivers/usb/musb/musb_core.h
@@ -145,7 +145,7 @@ struct musb_regs {
struct musb_epN_regs epN;
} ep[16];
-} __attribute__((packed, aligned(32)));
+} __attribute__((packed, aligned(USB_DMA_MINALIGN)));
#endif
/*
diff --git a/include/usb.h b/include/usb.h
index 6da91e7..ba3d169 100644
--- a/include/usb.h
+++ b/include/usb.h
@@ -29,6 +29,16 @@
#include
#include
+/*
+ * The EHCI spec says that we must align to at least 32 bytes. However,
+ * some platforms require larger alignment.
+ */
+#if ARCH_DMA_MINALIGN > 32
+#define USB_DMA_MINALIGN ARCH_DMA_MINALIGN
+#else
+#define USB_DMA_MINALIGN 32
+#endif
+
/* Everything is aribtrary */
#define USB_ALTSETTINGALLOC4
#define USB_MAXALTSETTING 128 /* Hard limit */
--
1.7.9.5
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[U-Boot] [PATCH v4 3/6] mcx: Disable DCACHE since USB EHCI is enabled
USB EHCI and DCACHE are not compatible, so disable DCACHE support at build-time as run-time disable is insufficient for USB use. Cc: Ilya Yanok Signed-off-by: Tom Rini --- include/configs/mcx.h |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/mcx.h b/include/configs/mcx.h index f6a83a8..0b29b08 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -110,9 +110,9 @@ #define CONFIG_OMAP3_GPIO_5 #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_OMAP +#define CONFIG_SYS_DCACHE_OFF /* USB_EHCI is unusable with DCACHE support */ #define CONFIG_USB_ULPI #define CONFIG_USB_ULPI_VIEWPORT_OMAP -/*#define CONFIG_EHCI_DCACHE*/ /* leave it disabled for now */ #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 154 #define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 152 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 1/6] ehci-omap: Do not call dcache_off from omap_ehci_hcd_init
This has never been completely sufficient and now happens too late to paper over the cache coherency problems with the current USB stack. Cc: Marek Vasut Signed-off-by: Tom Rini --- drivers/usb/host/ehci-omap.c |1 - 1 file changed, 1 deletion(-) diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c index 1ed7710..292673b 100644 --- a/drivers/usb/host/ehci-omap.c +++ b/drivers/usb/host/ehci-omap.c @@ -246,7 +246,6 @@ int omap_ehci_hcd_init(struct omap_usbhs_board_data *usbhs_pdata) if (is_ehci_phy_mode(usbhs_pdata->port_mode[i])) omap_ehci_soft_phy_reset(i); - dcache_disable(); hccr = (struct ehci_hccr *)(OMAP_EHCI_BASE); hcor = (struct ehci_hcor *)(OMAP_EHCI_BASE + 0x10); -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 4/6] omap3_beagle: Disable DCACHE since USB EHCI is enabled
USB EHCI and DCACHE are not compatible, so disable DCACHE support at build-time as run-time disable is insufficient for USB use. Signed-off-by: Tom Rini --- include/configs/omap3_beagle.h |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index b891ee4..79560d7 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -131,7 +131,7 @@ #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_OMAP -/*#define CONFIG_EHCI_DCACHE*/ /* leave it disabled for now */ +#define CONFIG_SYS_DCACHE_OFF /* USB_EHCI is unusable with DCACHE support */ #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 147 #define CONFIG_USB_ULPI -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 5/6] omap4_panda: Disable DCACHE since USB EHCI is enabled
USB EHCI and DCACHE are not compatible, so disable DCACHE support at build-time as run-time disable is insufficient for USB use. Cc: Sricharan R Signed-off-by: Tom Rini --- include/configs/omap4_panda.h |1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h index b4756be..468cf7a 100644 --- a/include/configs/omap4_panda.h +++ b/include/configs/omap4_panda.h @@ -38,6 +38,7 @@ #define CONFIG_USB_HOST #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_OMAP +#define CONFIG_SYS_DCACHE_OFF /* USB_EHCI is unusable with DCACHE support */ #define CONFIG_USB_STORAGE #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 6/6] tam3517-common: Disable DCACHE since USB EHCI is enabled
USB EHCI and DCACHE are not compatible, so disable DCACHE support at build-time as run-time disable is insufficient for USB use. Cc: Stefano Babic Signed-off-by: Tom Rini --- include/configs/tam3517-common.h |1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index 3fc2c44..b9c96b9 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -100,6 +100,7 @@ #define CONFIG_OMAP3_GPIO_5 #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_OMAP +#define CONFIG_SYS_DCACHE_OFF /* USB_EHCI is unusable with DCACHE support */ #define CONFIG_USB_ULPI #define CONFIG_USB_ULPI_VIEWPORT_OMAP #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25 -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 0/9]EXYNOS5: Support for Exynos5250 Rev 1.0
Hi Rajeshwari, On 06/20/2012 07:40 PM, Rajeshwari Shinde wrote: > This patch set adds support for Exynos5250 Rev 1.0. > Exynos5250 Rev 1.0 supports DDR3 Memory configuration and > support for LPDDR2 is removed. > Exynos5250 Rev 1.0 supports DWMMC driver but the support for same is > not yet gone into Mainline. After DWMMC driver is added to Mainline > support for generic S5P MMC driver will be removed. > > Due to Support of generic S5P MMC driver currently still being there in the > Mainline you can see the following error on boot. > > mmc_reset: timeout error > mmc_change_clock: timeout error > mmc_send_cmd: waiting for status update > MMC init failed Is this error produced at exynos5, otherwise all samsung-soc? I didn't understand why explain mmc issue in these patch series.. Best Regards, Jaehoon Chung > > Rajeshwari Shinde (9): > ARCH: SPL: Add parametric board initializer > SMDK5250: SPL: Define parametric board initializer > SMDK5250: Add smdk5250-uboot-spl.lds > EXYNOS5: CLOCK: define additional clock registers for Exynos5250 Rev > 1.0 > EXYNOS5: CLOCK: Add clock support for Exynos5250 Rev 1.0 > Exynos5: DDR3: Adding the DDR3 memory setup for Exynos5250 Rev 1.0 > EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0 > EXYNOS5 : Modify pinnumx settings as per Exynos5250 Rev 1.0 > SMDK5250: Enable UART and MMC for Exynos5250 Rev 1.0 > > arch/arm/cpu/armv7/exynos/clock.c | 12 +- > arch/arm/cpu/armv7/exynos/pinmux.c| 18 +- > arch/arm/include/asm/arch-exynos/clock.h | 37 +- > arch/arm/include/asm/arch-exynos/dmc.h| 65 +++ > arch/arm/include/asm/arch-exynos/spl.h| 95 +++ > board/samsung/smdk5250/Makefile |3 +- > board/samsung/smdk5250/clock_init.c | 714 +++ > board/samsung/smdk5250/clock_init.h | 149 + > board/samsung/smdk5250/dmc_common.c | 199 +++ > board/samsung/smdk5250/dmc_init.c | 462 --- > board/samsung/smdk5250/dmc_init_ddr3.c| 228 > board/samsung/smdk5250/setup.h| 765 > +++-- > board/samsung/smdk5250/smdk5250-uboot-spl.lds | 66 +++ > board/samsung/smdk5250/smdk5250.c |6 +- > board/samsung/smdk5250/smdk5250_spl.c | 68 +++ > include/configs/smdk5250.h|7 +- > 16 files changed, 1968 insertions(+), 926 deletions(-) > create mode 100644 arch/arm/include/asm/arch-exynos/spl.h > create mode 100644 board/samsung/smdk5250/clock_init.h > create mode 100644 board/samsung/smdk5250/dmc_common.c > delete mode 100644 board/samsung/smdk5250/dmc_init.c > create mode 100644 board/samsung/smdk5250/dmc_init_ddr3.c > create mode 100644 board/samsung/smdk5250/smdk5250-uboot-spl.lds > create mode 100644 board/samsung/smdk5250/smdk5250_spl.c > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 2/6] ehci-hcd.c, musb_core, usb.h: Add USB_DMA_MINALIGN define for cache alignment
Dear Tom Rini, > On Wed, Jun 20, 2012 at 11:15:26PM +0200, Marek Vasut wrote: > > Dear Tom Rini, > > > > > On Wed, Jun 20, 2012 at 09:00:45PM +0200, Marek Vasut wrote: > > > > Dear Tom Rini, > > > > > > > > > The USB spec says that 32 bytes is the minimum required alignment. > > > > > However on some platforms we have a larger minimum requirement for > > > > > cache coherency. In those cases, use that value rather than the > > > > > USB spec minimum. We add a cpp check to to define > > > > > USB_DMA_MINALIGN and make use of it in ehci-hcd.c and musb_core.h. > > > > > We cannot use MAX() here as we are not allowed to have tests > > > > > inside of align(...). > > > > > > > > > > Cc: Marek Vasut > > > > > Signed-off-by: Tom Rini > > > > > > > > > > -- > > > > > Changes in v2: > > > > > - Move test to , expand comment. > > > > > --- > > > > > > > > > > drivers/usb/host/ehci-hcd.c | 13 +++-- > > > > > drivers/usb/musb/musb_core.h |2 +- > > > > > include/usb.h| 10 ++ > > > > > 3 files changed, 18 insertions(+), 7 deletions(-) > > > > > > > > > > diff --git a/drivers/usb/host/ehci-hcd.c > > > > > b/drivers/usb/host/ehci-hcd.c index 04300be..5a86117 100644 > > > > > --- a/drivers/usb/host/ehci-hcd.c > > > > > +++ b/drivers/usb/host/ehci-hcd.c > > > > > @@ -29,12 +29,13 @@ > > > > > > > > > > #include "ehci.h" > > > > > > > > > > -int rootdev; > > > > > -struct ehci_hccr *hccr; /* R/O registers, not need for volatile */ > > > > > -volatile struct ehci_hcor *hcor; > > > > > +int rootdev __attribute__((aligned(USB_DMA_MINALIGN))); > > > > > +/* R/O registers, not need for volatile */ > > > > > +struct ehci_hccr *hccr __attribute__((aligned(USB_DMA_MINALIGN))); > > > > > +volatile struct ehci_hcor *hcor > > > > > __attribute__((aligned(USB_DMA_MINALIGN))); > > > > > > > > ^ these need to be aligned too? > > > > > > Yes, these were the first and easy to spot ones in the cache flush > > > messages, I would swear. > > > > hcor and hccr are register locations though ... so it's pretty weird. > > OK, now that I look harder at the messages, doing that is only masking a > problem. At issue (from u-boot.map): > .bss 0x801586c0 0x1c0 drivers/usb/host/libusb_host.o > 0x80158860hcor > And a message of: > ERROR: v7_dcache_inval_range - stop address is not aligned - 0x9ffbc860 > Using 'bdinfo' to see reloc offset gives us hcor, but _end_ not start > means it's something within the anonymous part of the bss and padding > hcor out just masks the real problem. I'll resubmit a v4 shortly. > Thanks! You're welcome, Add my Acked-by: Marek Vasut and push through omap since it's part of a bigger patchset. Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] omap: am335x_evm: enable i2c1 channel
On Mon, Jun 04, 2012 at 08:34:39AM -0700, Steve Sakoman wrote: > This patch sets up pinmux, enables fclk, and > defines CONFIG_I2C_MULTI_BUS You add, but don't use the pinmux for i2c1: mux.c:283: warning: 'i2c1_pin_mux' defined but not used v2 please? :) -- Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/4] OMAP3: twister: add video support
On Thu, Jun 14, 2012 at 10:29:47AM +0200, Stefano Babic wrote:
> Signed-off-by: Stefano Babic
[snip]
> +static GraphicDevice panel;
> +static const struct panel_config lcd_cfg = {
> + .timing_h = 0x01101d1b, /* Horizontal timing */
> + .timing_v = 0x01400b02, /* Vertical timing */
> + .pol_freq = 0x00023000, /* Pol Freq */
> + .divisor= 0x0001000d, /* 33Mhz Pixel Clock */
> + .lcd_size = ((YRES - 1) << 16 | (XRES - 1)),
> + .panel_type = 0x01, /* TFT */
> + .data_lines = 0x03, /* 24 Bit RGB */
> + .load_mode = 0x02 /* Frame Mode */
> +};
You need #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
type testing here[1] that the mt_ventoux board patch has. Shall I or
will you v2? And I'll sanity test this on omap3_beagle tomorrow, but I
suspect it's fine :)
[1]: twister.c:50: warning: 'panel' defined but not used
--
Tom
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[U-Boot] (no subject)
http://amaiko.net/files/live/google.html?sdm=ef.sxfs&ony=yug.jyg&ydl=tsuw ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] ARMv7: Add register definition of global timer
ARMv7 has global timer. This provides the register definition of this timer.
Signed-off-by: Nobuhiro Iwamatsu
---
arch/arm/include/asm/arch-armv7/globaltimer.h | 36 +
1 file changed, 36 insertions(+)
create mode 100644 arch/arm/include/asm/arch-armv7/globaltimer.h
diff --git a/arch/arm/include/asm/arch-armv7/globaltimer.h
b/arch/arm/include/asm/arch-armv7/globaltimer.h
new file mode 100644
index 000..0ac70fd
--- /dev/null
+++ b/arch/arm/include/asm/arch-armv7/globaltimer.h
@@ -0,0 +1,36 @@
+/*
+ * (C) Copyright 2012 Nobuhiro Iwamatsu
+ * (C) Copyright 2012 Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _GLOBALTIMER_H_
+#define _GLOBALTIMER_H_
+
+struct globaltimer {
+ u32 cnt_l; /* 0x00 */
+ u32 cnt_h;
+ u32 ctl;
+ u32 stat;
+ u32 cmp_l; /* 0x10 */
+ u32 cmp_h;
+ u32 inc;
+};
+
+#endif /* _GLOBALTIMER_H_ */
--
1.7.10
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[U-Boot] [PATCH 1/2] arm: rmobile: Add basic support for Renesas R-Mobile
This patch adds minimum support for R-Mobile. Only minimal support with timer.
This CPU can uses the peripheral of Renesas SuperH.
Signed-off-by: Nobuhiro Iwamatsu
---
arch/arm/cpu/armv7/rmobile/Makefile | 48 +
arch/arm/cpu/armv7/rmobile/cpu_info.c | 74
arch/arm/cpu/armv7/rmobile/timer.c | 97 +++
arch/arm/include/asm/arch-rmobile/rmobile.h |8 +++
4 files changed, 227 insertions(+)
create mode 100644 arch/arm/cpu/armv7/rmobile/Makefile
create mode 100644 arch/arm/cpu/armv7/rmobile/cpu_info.c
create mode 100644 arch/arm/cpu/armv7/rmobile/timer.c
create mode 100644 arch/arm/include/asm/arch-rmobile/rmobile.h
diff --git a/arch/arm/cpu/armv7/rmobile/Makefile
b/arch/arm/cpu/armv7/rmobile/Makefile
new file mode 100644
index 000..e7eb90f
--- /dev/null
+++ b/arch/arm/cpu/armv7/rmobile/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(SOC).o
+
+COBJS += cpu_info.o
+COBJS += timer.o
+
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(LIB)
+
+$(LIB):$(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
+
diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info.c
b/arch/arm/cpu/armv7/rmobile/cpu_info.c
new file mode 100644
index 000..7d25a28
--- /dev/null
+++ b/arch/arm/cpu/armv7/rmobile/cpu_info.c
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright 2012 Nobuhiro Iwamatsu
+ * (C) Copyright 2012 Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include
+#include
+#include
+
+#ifdef CONFIG_ARCH_CPU_INIT
+int arch_cpu_init(void)
+{
+ icache_enable();
+ return 0;
+}
+#endif
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+ dcache_enable();
+}
+#endif
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+static u32 get_cpu_type(void)
+{
+ u32 id;
+ u32 type;
+
+ id = readl(CCCR);
+ type = (id >> 8) & 0xFF;
+
+ return type;
+}
+
+static u32 get_cpu_rev(void)
+{
+ u32 id;
+ u32 rev;
+
+ id = readl(CCCR);
+ rev = (id >> 4) & 0xF;
+
+ return rev;
+}
+
+int print_cpuinfo(void)
+{
+ switch (get_cpu_type()) {
+ default:
+ printf("CPU: Renesas Electronics CPU rev %d", get_cpu_rev());
+ break;
+ }
+ return 0;
+}
+#endif
diff --git a/arch/arm/cpu/armv7/rmobile/timer.c
b/arch/arm/cpu/armv7/rmobile/timer.c
new file mode 100644
index 000..1818739
--- /dev/null
+++ b/arch/arm/cpu/armv7/rmobile/timer.c
@@ -0,0 +1,97 @@
+/*
+ * (C) Copyright 2012 Nobuhiro Iwamatsu
+ * (C) Copyright 2012 Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distribut
[U-Boot] [PATCH v4 1/1] tegra: usb: Fix device enumeration problem of USB1
A known hardware issue of USB1 port where bit 1 (connect status
change) of PORTSC register will be set after issuing Port Reset
(like "usb reset" in u-boot command line).
This will be treated as an error and stops later device enumeration.
Therefore we clear that bit after Port Reset in order to proceed
later device enumeration.
Signed-off-by: Jim Lin
---
To reproduce this issue, you can modify board .dts file to set
as the following to build u-boot binary.
"
usb0 = "/usb@c500";
usb1 = "/usb@c5008000";
"
Install device on USB1 port (address at 0xc500).
And run "usb reset" in u-boot console to enumerate device.
Before adding this patch, we could see problem every time.
After adding, tried 10 times of "usb reset", "usb tree", "usb stop"
, without seeing issue.
Changes in v4:
- Add comment to describe replacing weak function ehci_powerup_fixup of
ehci-hcd.c
- Remove using variable my_reg
Changes in v3:
- Move patch for USB1 controller into ehci_powerup_fixup of ehci-tegra.c
- Update copyright year to 2012
Changes in v2:
- Change config name
- Add a callback function at the end of ehci_submit_root() function
drivers/usb/host/ehci-tegra.c | 18 +-
1 files changed, 17 insertions(+), 1 deletions(-)
diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
index a7e105b..6646d3a 100644
--- a/drivers/usb/host/ehci-tegra.c
+++ b/drivers/usb/host/ehci-tegra.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2009 NVIDIA Corporation
+ * Copyright (c) 2009-2012 NVIDIA Corporation
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -29,6 +29,22 @@
#include
#include
+/*
+ * A known hardware issue where Connect Status Change bit of PORTSC register
+ * of USB1 controller will be set after Port Reset.
+ * We have to clear it in order for later device enumeration to proceed.
+ * This ehci_powerup_fixup overrides the weak function ehci_powerup_fixup
+ * in "ehci-hcd.c".
+ */
+void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
+{
+ mdelay(50);
+ if (((u32) status_reg & 0xC000) != TEGRA_USB1_BASE)
+ return;
+ /* For EHCI_PS_CSC to be cleared in ehci_hcd.c */
+ if (ehci_readl(status_reg) & EHCI_PS_CSC)
+ *reg |= EHCI_PS_CSC;
+}
/*
* Create the appropriate control structures to manage
--
1.7.3
nvpublic
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Re: [U-Boot] [PATCH 4/9] EXYNOS5: CLOCK: define additional clock registers for Exynos5250 Rev 1.0
Hi, Rajeshwari.
2012/6/20 Rajeshwari Shinde :
> Define additional registers for clock control in Exynos5250 Rev 1.0
>
Many registers for clock is missed for EVT1 and exist for EVT0 still
in this patch.
Please make using all registers of clock for EVT1 only.
Thanks.
> Signed-off-by: Hatim Ali
> Signed-off-by: Rajeshwari Shinde
> ---
> arch/arm/include/asm/arch-exynos/clock.h | 36 +
> 1 files changed, 26 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-exynos/clock.h
> b/arch/arm/include/asm/arch-exynos/clock.h
> index 50da958..7cc3d5e 100644
> --- a/arch/arm/include/asm/arch-exynos/clock.h
> +++ b/arch/arm/include/asm/arch-exynos/clock.h
> @@ -272,7 +272,7 @@ struct exynos5_clock {
> unsigned int clkout_cmu_cpu;
> unsigned int clkout_cmu_cpu_div_stat;
> unsigned char res8[0x5f8];
> - unsigned int armclk_stopctrl;
> + unsigned int armclk_stopctrl; /* base + 0x1000 */
> unsigned int atclk_stopctrl;
> unsigned char res9[0x8];
> unsigned int parityfail_status;
> @@ -323,10 +323,12 @@ struct exynos5_clock {
> unsigned char res19[0xf8];
> unsigned int div_core0;
> unsigned int div_core1;
> - unsigned char res20[0xf8];
> + unsigned int div_sysrgt;
> + unsigned char res20[0xf4];
> unsigned int div_stat_core0;
> unsigned int div_stat_core1;
> - unsigned char res21[0x2f8];
> + unsigned int div_stat_sysrgt;
> + unsigned char res21[0x2f4];
> unsigned int gate_ip_core;
> unsigned char res22[0xfc];
> unsigned int clkout_cmu_core;
> @@ -352,7 +354,11 @@ struct exynos5_clock {
> unsigned int div_stat_acp;
> unsigned char res30[0x1fc];
> unsigned int gate_ip_acp;
> - unsigned char res31[0x1fc];
> + unsigned char res31a[0xfc];
> + unsigned int div_syslft;
> + unsigned char res31b[0xc];
> + unsigned int div_stat_syslft;
> + unsigned char res31c[0xec];
> unsigned int clkout_cmu_acp;
> unsigned int clkout_cmu_acp_div_stat;
> unsigned char res32[0x38f8];
> @@ -379,7 +385,9 @@ struct exynos5_clock {
> unsigned int epll_lock;
> unsigned char res40[0xc];
> unsigned int vpll_lock;
> - unsigned char res41[0xdc];
> + unsigned char res41a[0xc];
> + unsigned int gpll_lock;
> + unsigned char res41b[0xcc];
> unsigned int cpll_con0;
> unsigned int cpll_con1;
> unsigned char res42[0x8];
> @@ -390,7 +398,10 @@ struct exynos5_clock {
> unsigned int vpll_con0;
> unsigned int vpll_con1;
> unsigned int vpll_con2;
> - unsigned char res44[0xc4];
> + unsigned char res44a[0x4];
> + unsigned int gpll_con0;
> + unsigned int gpll_con1;
> + unsigned char res44b[0xb8];
> unsigned int src_top0;
> unsigned int src_top1;
> unsigned int src_top2;
> @@ -521,7 +532,9 @@ struct exynos5_clock {
> unsigned int clkout_cmu_top_div_stat;
> unsigned char res84[0x37f8];
> unsigned int src_lex;
> - unsigned char res85[0x2fc];
> + unsigned char res85[0x1fc];
> + unsigned int mux_stat_lex;
> + unsigned char res85b[0xfc];
> unsigned int div_lex;
> unsigned char res86[0xfc];
> unsigned int div_stat_lex;
> @@ -549,7 +562,8 @@ struct exynos5_clock {
> unsigned int clkout_cmu_r1x;
> unsigned int clkout_cmu_r1x_div_stat;
> unsigned char res98[0x3608];
> - unsigned int bpll_lock;
> +
> + unsigned int bpll_lock; /* base + 0x2000c */
> unsigned char res99[0xfc];
> unsigned int bpll_con0;
> unsigned int bpll_con1;
> @@ -574,8 +588,10 @@ struct exynos5_clock {
> unsigned int clkout_cmu_cdrex_div_stat;
> unsigned char res108[0x8];
> unsigned int lpddr3phy_ctrl;
> - unsigned char res109[0xf5f8];
> + unsigned char res109a[0xc];
> + unsigned int lpddr3phy_con3;
> + unsigned int pll_div2_sel;
> + unsigned char res109b[0xf5e4];
> };
> #endif
> -
> #endif
> --
> 1.7.4.4
>
--
- Joonyoung Shim
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Re: [U-Boot] [PATCH 7/9] EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0
Hi,
2012/6/20 Rajeshwari Shinde :
> MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz.
> Adjust the divisor value to get 800MHz as needed by devices
> like UART etc
>
> Signed-off-by: Hatim Ali
> Signed-off-by: Rajeshwari Shinde
> ---
> arch/arm/cpu/armv7/exynos/clock.c | 12 +++-
> arch/arm/include/asm/arch-exynos/clock.h | 3 +++
> 2 files changed, 14 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/exynos/clock.c
> b/arch/arm/cpu/armv7/exynos/clock.c
> index 330bd75..dbd5f11 100644
> --- a/arch/arm/cpu/armv7/exynos/clock.c
> +++ b/arch/arm/cpu/armv7/exynos/clock.c
> @@ -98,7 +98,7 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
> struct exynos5_clock *clk =
> (struct exynos5_clock *)samsung_get_base_clock();
> unsigned long r, m, p, s, k = 0, mask, fout;
> - unsigned int freq;
> + unsigned int freq, pll_div2_sel, mpll_fout_sel;
>
> switch (pllreg) {
> case APLL:
> @@ -155,6 +155,16 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
> fout = m * (freq / (p * (1 << (s - 1;
> }
>
> + /* According to the user manual, in EVT1 MPLL always gives
> + * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/
> + if (pllreg == MPLL) {
> + pll_div2_sel = readl(&clk->pll_div2_sel);
> + mpll_fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT)
> + & MPLL_FOUT_SEL_MASK;
> + if (mpll_fout_sel == 0)
> + fout /= 2;
> + }
> +
I think BPLL also needs this.
--
- Joonyoung Shim
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Re: [U-Boot] [PATCH 4/9] EXYNOS5: CLOCK: define additional clock registers for Exynos5250 Rev 1.0
Hi Joonyoung Shim,
Thank you for comments.
On Thu, Jun 21, 2012 at 10:25 AM, Joonyoung Shim wrote:
> Hi, Rajeshwari.
>
> 2012/6/20 Rajeshwari Shinde :
>> Define additional registers for clock control in Exynos5250 Rev 1.0
>>
>
> Many registers for clock is missed for EVT1 and exist for EVT0 still
> in this patch.
> Please make using all registers of clock for EVT1 only.
-- Will check the same and resend the patch.
>
> Thanks.
>
>> Signed-off-by: Hatim Ali
>> Signed-off-by: Rajeshwari Shinde
>> ---
>> arch/arm/include/asm/arch-exynos/clock.h | 36
>> +
>> 1 files changed, 26 insertions(+), 10 deletions(-)
>>
>> diff --git a/arch/arm/include/asm/arch-exynos/clock.h
>> b/arch/arm/include/asm/arch-exynos/clock.h
>> index 50da958..7cc3d5e 100644
>> --- a/arch/arm/include/asm/arch-exynos/clock.h
>> +++ b/arch/arm/include/asm/arch-exynos/clock.h
>> @@ -272,7 +272,7 @@ struct exynos5_clock {
>> unsigned int clkout_cmu_cpu;
>> unsigned int clkout_cmu_cpu_div_stat;
>> unsigned char res8[0x5f8];
>> - unsigned int armclk_stopctrl;
>> + unsigned int armclk_stopctrl; /* base + 0x1000 */
>> unsigned int atclk_stopctrl;
>> unsigned char res9[0x8];
>> unsigned int parityfail_status;
>> @@ -323,10 +323,12 @@ struct exynos5_clock {
>> unsigned char res19[0xf8];
>> unsigned int div_core0;
>> unsigned int div_core1;
>> - unsigned char res20[0xf8];
>> + unsigned int div_sysrgt;
>> + unsigned char res20[0xf4];
>> unsigned int div_stat_core0;
>> unsigned int div_stat_core1;
>> - unsigned char res21[0x2f8];
>> + unsigned int div_stat_sysrgt;
>> + unsigned char res21[0x2f4];
>> unsigned int gate_ip_core;
>> unsigned char res22[0xfc];
>> unsigned int clkout_cmu_core;
>> @@ -352,7 +354,11 @@ struct exynos5_clock {
>> unsigned int div_stat_acp;
>> unsigned char res30[0x1fc];
>> unsigned int gate_ip_acp;
>> - unsigned char res31[0x1fc];
>> + unsigned char res31a[0xfc];
>> + unsigned int div_syslft;
>> + unsigned char res31b[0xc];
>> + unsigned int div_stat_syslft;
>> + unsigned char res31c[0xec];
>> unsigned int clkout_cmu_acp;
>> unsigned int clkout_cmu_acp_div_stat;
>> unsigned char res32[0x38f8];
>> @@ -379,7 +385,9 @@ struct exynos5_clock {
>> unsigned int epll_lock;
>> unsigned char res40[0xc];
>> unsigned int vpll_lock;
>> - unsigned char res41[0xdc];
>> + unsigned char res41a[0xc];
>> + unsigned int gpll_lock;
>> + unsigned char res41b[0xcc];
>> unsigned int cpll_con0;
>> unsigned int cpll_con1;
>> unsigned char res42[0x8];
>> @@ -390,7 +398,10 @@ struct exynos5_clock {
>> unsigned int vpll_con0;
>> unsigned int vpll_con1;
>> unsigned int vpll_con2;
>> - unsigned char res44[0xc4];
>> + unsigned char res44a[0x4];
>> + unsigned int gpll_con0;
>> + unsigned int gpll_con1;
>> + unsigned char res44b[0xb8];
>> unsigned int src_top0;
>> unsigned int src_top1;
>> unsigned int src_top2;
>> @@ -521,7 +532,9 @@ struct exynos5_clock {
>> unsigned int clkout_cmu_top_div_stat;
>> unsigned char res84[0x37f8];
>> unsigned int src_lex;
>> - unsigned char res85[0x2fc];
>> + unsigned char res85[0x1fc];
>> + unsigned int mux_stat_lex;
>> + unsigned char res85b[0xfc];
>> unsigned int div_lex;
>> unsigned char res86[0xfc];
>> unsigned int div_stat_lex;
>> @@ -549,7 +562,8 @@ struct exynos5_clock {
>> unsigned int clkout_cmu_r1x;
>> unsigned int clkout_cmu_r1x_div_stat;
>> unsigned char res98[0x3608];
>> - unsigned int bpll_lock;
>> +
>> + unsigned int bpll_lock; /* base + 0x2000c */
>> unsigned char res99[0xfc];
>> unsigned int bpll_con0;
>> unsigned int bpll_con1;
>> @@ -574,8 +588,10 @@ struct exynos5_clock {
>> unsigned int clkout_cmu_cdrex_div_stat;
>> unsigned char res108[0x8];
>> unsigned int lpddr3phy_ctrl;
>> - unsigned char res109[0xf5f8];
>> + unsigned char res109a[0xc];
>> + unsigned int lpddr3phy_con3;
>> + unsigned int pll_div2_sel;
>> + unsigned char res109b[0xf5e4];
>> };
>> #endif
>> -
>> #endif
>> --
>> 1.7.4.4
>>
>
>
>
> --
> - Joonyoung Shim
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Regards,
Rajeshwari Shinde.
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Re: [U-Boot] [PATCH v4 1/1] tegra: usb: Fix device enumeration problem of USB1
On 06/20/2012 09:24 PM, Jim Lin wrote: > A known hardware issue of USB1 port where bit 1 (connect status > change) of PORTSC register will be set after issuing Port Reset > (like "usb reset" in u-boot command line). > This will be treated as an error and stops later device enumeration. > > Therefore we clear that bit after Port Reset in order to proceed > later device enumeration. > > Signed-off-by: Jim Lin Acked-by: Stephen Warren ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] sh: Add support pin function control using GPIO
Renesas SH and R-Mobile set up device using PFC.
This provide the framework. Most codes were brought from linux kernel.
Signed-off-by: Nobuhiro Iwamatsu
---
drivers/gpio/Makefile |1 +
drivers/gpio/sh_pfc.c | 629 +
include/sh_pfc.h | 192 +++
3 files changed, 822 insertions(+)
create mode 100644 drivers/gpio/sh_pfc.c
create mode 100644 include/sh_pfc.h
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index fb3b09a..9192582 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -39,6 +39,7 @@ COBJS-$(CONFIG_TEGRA2_GPIO) += tegra2_gpio.o
COBJS-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o
COBJS-$(CONFIG_ALTERA_PIO) += altera_pio.o
COBJS-$(CONFIG_MPC83XX_GPIO) += mpc83xx_gpio.o
+COBJS-$(CONFIG_SH_GPIO_PFC)+= sh_pfc.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/gpio/sh_pfc.c b/drivers/gpio/sh_pfc.c
new file mode 100644
index 000..7a5af20
--- /dev/null
+++ b/drivers/gpio/sh_pfc.c
@@ -0,0 +1,629 @@
+/*
+ * Pinmuxed GPIO support for SuperH.
+ * Copy from linux kernel driver/sh/pfc.c
+ *
+ * Copyright (C) 2008 Magnus Damm
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include
+#include
+#include
+#include
+
+static struct pinmux_info *gpioc;
+
+#define pfc_phys_to_virt(p, a) ((void *)a)
+
+static int enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
+{
+ if (enum_id < r->begin)
+ return 0;
+
+ if (enum_id > r->end)
+ return 0;
+
+ return 1;
+}
+
+static unsigned long gpio_read_raw_reg(void *mapped_reg,
+ unsigned long reg_width)
+{
+ switch (reg_width) {
+
+ case 8:
+ return readb(mapped_reg);
+ case 16:
+ return readw(mapped_reg);
+ case 32:
+ return readl(mapped_reg);
+ }
+
+ BUG();
+ return 0;
+}
+
+static void gpio_write_raw_reg(void *mapped_reg,
+ unsigned long reg_width,
+ unsigned long data)
+{
+ switch (reg_width) {
+ case 8:
+ writeb(data, mapped_reg);
+ return;
+ case 16:
+ writew(data, mapped_reg);
+ return;
+ case 32:
+ writel(data, mapped_reg);
+ return;
+ }
+
+ BUG();
+}
+
+static int gpio_read_bit(struct pinmux_data_reg *dr,
+unsigned long in_pos)
+{
+ unsigned long pos;
+
+ pos = dr->reg_width - (in_pos + 1);
+
+ debug("read_bit: addr = %lx, pos = %ld, "
+"r_width = %ld\n", dr->reg, pos, dr->reg_width);
+
+ return (gpio_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1;
+}
+
+static void gpio_write_bit(struct pinmux_data_reg *dr,
+ unsigned long in_pos, unsigned long value)
+{
+ unsigned long pos;
+
+ pos = dr->reg_width - (in_pos + 1);
+
+ debug("write_bit addr = %lx, value = %d, pos = %ld, "
+"r_width = %ld\n",
+dr->reg, !!value, pos, dr->reg_width);
+
+ if (value)
+ __set_bit(pos, &dr->reg_shadow);
+ else
+ __clear_bit(pos, &dr->reg_shadow);
+
+ gpio_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow);
+}
+
+static void config_reg_helper(struct pinmux_info *gpioc,
+ struct pinmux_cfg_reg *crp,
+ unsigned long in_pos,
+#if 0
+ void __iomem **mapped_regp,
+#else
+ void **mapped_regp,
+#endif
+ unsigned long *maskp,
+ unsigned long *posp)
+{
+ int k;
+
+ *mapped_regp = pfc_phys_to_virt(gpioc, crp->reg);
+
+ if (crp->field_width) {
+ *maskp = (1 << crp->field_width) - 1;
+ *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
+ } else {
+ *maskp = (1 << crp->var_field_width[in_pos]) - 1;
+ *posp = crp->reg_width;
+ for (k = 0; k <= in_pos; k++)
+ *posp -= crp->var_field_width[k];
+ }
+}
+
+static int read_config_reg(struct pinmux_info *gpioc,
+ struct pinmux_cfg_reg *crp,
+ unsigned long field)
+{
+ void *mapped_reg;
+
+ unsigned long mask, pos;
+
+ config_reg_helper(gpioc, crp, field, &mapped_reg, &mask, &pos);
+
+ debug("read_reg: addr = %lx, field = %ld, "
+"r_width = %ld, f_width = %ld\n",
+crp->reg, field, crp->reg_width, crp->field_width);
+
+ return (gpio_read_raw_reg(mapped_reg, crp->reg_width) >> pos) & mask;
+}
+
+static void write_config_reg(struct pinmux_info *g
[U-Boot] [PATCH] sh: Add support pin function control using GPIO
Renesas SH and R-Mobile set up device using PFC.
This provide the framework. Most codes were brought from linux kernel.
Signed-off-by: Nobuhiro Iwamatsu
---
drivers/gpio/Makefile |1 +
drivers/gpio/sh_pfc.c | 629 +
include/sh_pfc.h | 192 +++
3 files changed, 822 insertions(+)
create mode 100644 drivers/gpio/sh_pfc.c
create mode 100644 include/sh_pfc.h
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index fb3b09a..9192582 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -39,6 +39,7 @@ COBJS-$(CONFIG_TEGRA2_GPIO) += tegra2_gpio.o
COBJS-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o
COBJS-$(CONFIG_ALTERA_PIO) += altera_pio.o
COBJS-$(CONFIG_MPC83XX_GPIO) += mpc83xx_gpio.o
+COBJS-$(CONFIG_SH_GPIO_PFC)+= sh_pfc.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/gpio/sh_pfc.c b/drivers/gpio/sh_pfc.c
new file mode 100644
index 000..7a5af20
--- /dev/null
+++ b/drivers/gpio/sh_pfc.c
@@ -0,0 +1,629 @@
+/*
+ * Pinmuxed GPIO support for SuperH.
+ * Copy from linux kernel driver/sh/pfc.c
+ *
+ * Copyright (C) 2008 Magnus Damm
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include
+#include
+#include
+#include
+
+static struct pinmux_info *gpioc;
+
+#define pfc_phys_to_virt(p, a) ((void *)a)
+
+static int enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
+{
+ if (enum_id < r->begin)
+ return 0;
+
+ if (enum_id > r->end)
+ return 0;
+
+ return 1;
+}
+
+static unsigned long gpio_read_raw_reg(void *mapped_reg,
+ unsigned long reg_width)
+{
+ switch (reg_width) {
+
+ case 8:
+ return readb(mapped_reg);
+ case 16:
+ return readw(mapped_reg);
+ case 32:
+ return readl(mapped_reg);
+ }
+
+ BUG();
+ return 0;
+}
+
+static void gpio_write_raw_reg(void *mapped_reg,
+ unsigned long reg_width,
+ unsigned long data)
+{
+ switch (reg_width) {
+ case 8:
+ writeb(data, mapped_reg);
+ return;
+ case 16:
+ writew(data, mapped_reg);
+ return;
+ case 32:
+ writel(data, mapped_reg);
+ return;
+ }
+
+ BUG();
+}
+
+static int gpio_read_bit(struct pinmux_data_reg *dr,
+unsigned long in_pos)
+{
+ unsigned long pos;
+
+ pos = dr->reg_width - (in_pos + 1);
+
+ debug("read_bit: addr = %lx, pos = %ld, "
+"r_width = %ld\n", dr->reg, pos, dr->reg_width);
+
+ return (gpio_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1;
+}
+
+static void gpio_write_bit(struct pinmux_data_reg *dr,
+ unsigned long in_pos, unsigned long value)
+{
+ unsigned long pos;
+
+ pos = dr->reg_width - (in_pos + 1);
+
+ debug("write_bit addr = %lx, value = %d, pos = %ld, "
+"r_width = %ld\n",
+dr->reg, !!value, pos, dr->reg_width);
+
+ if (value)
+ __set_bit(pos, &dr->reg_shadow);
+ else
+ __clear_bit(pos, &dr->reg_shadow);
+
+ gpio_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow);
+}
+
+static void config_reg_helper(struct pinmux_info *gpioc,
+ struct pinmux_cfg_reg *crp,
+ unsigned long in_pos,
+#if 0
+ void __iomem **mapped_regp,
+#else
+ void **mapped_regp,
+#endif
+ unsigned long *maskp,
+ unsigned long *posp)
+{
+ int k;
+
+ *mapped_regp = pfc_phys_to_virt(gpioc, crp->reg);
+
+ if (crp->field_width) {
+ *maskp = (1 << crp->field_width) - 1;
+ *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
+ } else {
+ *maskp = (1 << crp->var_field_width[in_pos]) - 1;
+ *posp = crp->reg_width;
+ for (k = 0; k <= in_pos; k++)
+ *posp -= crp->var_field_width[k];
+ }
+}
+
+static int read_config_reg(struct pinmux_info *gpioc,
+ struct pinmux_cfg_reg *crp,
+ unsigned long field)
+{
+ void *mapped_reg;
+
+ unsigned long mask, pos;
+
+ config_reg_helper(gpioc, crp, field, &mapped_reg, &mask, &pos);
+
+ debug("read_reg: addr = %lx, field = %ld, "
+"r_width = %ld, f_width = %ld\n",
+crp->reg, field, crp->reg_width, crp->field_width);
+
+ return (gpio_read_raw_reg(mapped_reg, crp->reg_width) >> pos) & mask;
+}
+
+static void write_config_reg(struct pinmux_info *g
[U-Boot] [PATCH] arm: rmobile: Add supoprt for KMC KZM-A9-GT board
The KZM-A9-GT board has Renesas R-Mobile SH73A0, 512MB DDR2-SDRAM,
USB, Ethernet, and more.
This patch supports the following functions:
- 512MB DDR2-SDRAM
- 16MB NOR Flash memory
- Serial console (SCIF)
- Ethernet (SMSC)
- I2C
Signed-off-by: Nobuhiro Iwamatsu
---
arch/arm/include/asm/mach-types.h |2 +
board/kmc/kzm/Makefile| 51 ++
board/kmc/kzm/kzm.c | 142 +
board/kmc/kzm/lowlevel_init.S | 308 +
boards.cfg|1 +
include/configs/kzm_a9_gt.h | 164
6 files changed, 668 insertions(+)
create mode 100644 board/kmc/kzm/Makefile
create mode 100644 board/kmc/kzm/kzm.c
create mode 100644 board/kmc/kzm/lowlevel_init.S
create mode 100644 include/configs/kzm_a9_gt.h
diff --git a/arch/arm/include/asm/mach-types.h
b/arch/arm/include/asm/mach-types.h
index 2d5c3bc..98c992c 100644
--- a/arch/arm/include/asm/mach-types.h
+++ b/arch/arm/include/asm/mach-types.h
@@ -1106,6 +1106,8 @@ extern unsigned int __machine_arch_type;
#define MACH_TYPE_ATDGP318 3494
#define MACH_TYPE_OMAP5_SEVM 3777
+#define MACH_TYPE_KZM9G4140
+
#ifdef CONFIG_ARCH_EBSA110
# ifdef machine_arch_type
# undef machine_arch_type
diff --git a/board/kmc/kzm/Makefile b/board/kmc/kzm/Makefile
new file mode 100644
index 000..8601230
--- /dev/null
+++ b/board/kmc/kzm/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2012 Nobuhiro Iwamatsu
+# (C) Copyright 2012 Renesas Solutions Corp.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).o
+
+COBJS := kzm.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):$(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj) .depend
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/kmc/kzm/kzm.c b/board/kmc/kzm/kzm.c
new file mode 100644
index 000..ae0868e
--- /dev/null
+++ b/board/kmc/kzm/kzm.c
@@ -0,0 +1,142 @@
+/*
+ * (C) Copyright 2012 Nobuhiro Iwamatsu
+ * (C) Copyright 2012 Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CS0BCR_D (0x06C00400)
+#define CS4BCR_D (0x06C00400)
+#define CS0WCR_D (0x55062C42)
+#define CS4WCR_D (0x19051443)
+#define CMNCR_BROMMD0 (1 << 21)
+#define CMNCR_BROMMD1 (1 << 22)
+#define CMNCR_BROMMD (CMNCR_BROMMD0|CMNCR_BROMMD1)
+#define VCLKCR1_D (0x27)
+
+#define SMSTPCR1_CMT0 (1 << 24)
+#define SMSTPCR1_I2C0 (1 << 16)
+#define SMSTPCR3_USB (1 << 22)
+
+#define PORT32CR (0xE6051020)
+#define PORT33CR (0xE6051021)
+#define PORT34CR (0xE6051022)
+#define PORT35CR (0xE6051023)
+
+int board_early_init_f(void)
+{
+ writel(CS0BCR_D, CS0BCR);
+ writel(CS4BCR_D, CS4BCR);
+ writel(CS0WCR_D, CS0WCR);
+ writel(CS4WCR_D, CS4WCR);
+
+ clrsetbits_le32(CMNCR, ~CMNCR_BROMMD, CMNCR_BROMMD);
+
+ clrbi
[U-Boot] net: sh_eth: fix build error when CONFIG_CPU_SH7757 is set
This patch fixes the following build error when CONFIG_CPU_SH7757 is set:
In file included from sh_eth.c:32:
sh_eth.h:466: error: expected identifier before ‘}’ token
sh_eth.c: In function ‘sh_eth_config’:
sh_eth.c:380: error: ‘ECSIPR_BRCRXIP’ undeclared (first use in this function)
sh_eth.c:380: error: (Each undeclared identifier is reported only once
sh_eth.c:380: error: for each function it appears in.)
sh_eth.c:380: error: ‘ECSIPR_PSRTOIP’ undeclared (first use in this function)
sh_eth.c:380: error: ‘ECSIPR_LCHNGIP’ undeclared (first use in this function)
sh_eth.c:380: error: ‘ECSIPR_MPDIP’ undeclared (first use in this function)
sh_eth.c:380: error: ‘ECSIPR_ICDIP’ undeclared (first use in this function)
make[1]: *** [sh_eth.o] Error 1
Signed-off-by: Yoshihiro Shimoda
---
drivers/net/sh_eth.h |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index a1ba68b..f2bd734 100644
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -452,9 +452,11 @@ enum ECSR_STATUS_BIT {
/* ECSIPR */
enum ECSIPR_STATUS_MASK_BIT {
-#if defined(CONFIG_CPU_SH7724)
+#if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757)
+ ECSIPR_BRCRXIP = 0x20,
ECSIPR_PSRTOIP = 0x10,
ECSIPR_LCHNGIP = 0x04,
+ ECSIPR_MPDIP = 0x02,
ECSIPR_ICDIP = 0x01,
#elif defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
ECSIPR_PSRTOIP = 0x10,
--
1.7.1
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Re: [U-Boot] net: sh_eth: fix build error when CONFIG_CPU_SH7757 is set
Hi, 2012/06/21 15:51, Nobuhiro Iwamatsu wrote: > Hi, > > This patch already send to this ML > http://lists.denx.de/pipermail/u-boot/2012-June/125789.html Thank you for the information. I will test the patch. Best regards, Yoshihiro Shimoda ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] net: sh_eth: fix build error when CONFIG_CPU_SH7757 is set
Hi,
This patch already send to this ML
http://lists.denx.de/pipermail/u-boot/2012-June/125789.html
Best regards,
Nobuhiro
2012/6/21 Shimoda, Yoshihiro :
> This patch fixes the following build error when CONFIG_CPU_SH7757 is set:
>
> In file included from sh_eth.c:32:
> sh_eth.h:466: error: expected identifier before ‘}’ token
> sh_eth.c: In function ‘sh_eth_config’:
> sh_eth.c:380: error: ‘ECSIPR_BRCRXIP’ undeclared (first use in this function)
> sh_eth.c:380: error: (Each undeclared identifier is reported only once
> sh_eth.c:380: error: for each function it appears in.)
> sh_eth.c:380: error: ‘ECSIPR_PSRTOIP’ undeclared (first use in this function)
> sh_eth.c:380: error: ‘ECSIPR_LCHNGIP’ undeclared (first use in this function)
> sh_eth.c:380: error: ‘ECSIPR_MPDIP’ undeclared (first use in this function)
> sh_eth.c:380: error: ‘ECSIPR_ICDIP’ undeclared (first use in this function)
> make[1]: *** [sh_eth.o] Error 1
>
> Signed-off-by: Yoshihiro Shimoda
> ---
> drivers/net/sh_eth.h | 4 +++-
> 1 files changed, 3 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
> index a1ba68b..f2bd734 100644
> --- a/drivers/net/sh_eth.h
> +++ b/drivers/net/sh_eth.h
> @@ -452,9 +452,11 @@ enum ECSR_STATUS_BIT {
>
> /* ECSIPR */
> enum ECSIPR_STATUS_MASK_BIT {
> -#if defined(CONFIG_CPU_SH7724)
> +#if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757)
> + ECSIPR_BRCRXIP = 0x20,
> ECSIPR_PSRTOIP = 0x10,
> ECSIPR_LCHNGIP = 0x04,
> + ECSIPR_MPDIP = 0x02,
> ECSIPR_ICDIP = 0x01,
> #elif defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
> ECSIPR_PSRTOIP = 0x10,
> --
> 1.7.1
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--
Nobuhiro Iwamatsu
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