Re: [U-Boot] [PATCH] S3C64XX: timer: replace bss variable by gd
Dear seedshope, On 6 January 2011 00:57, seedshope wrote: > On 01/05/2011 03:04 PM, Minkyu Kang wrote: >> >> Dear seedshope, >> >> On 4 January 2011 23:56, seedshope wrote: >>> >>> On 01/04/2011 10:46 PM, seedshope wrote: On 01/04/2011 04:14 PM, Minkyu Kang wrote: > > Use the global data instead of bss variable, replace as follow. > timer_load_val -> timer_rate_hz > timestamp -> timer_reset_value > lastdec -> lastinc I have already test the patch on s3c6410 . It is work perfect. >>> >>> Before I am not use the patch, When I use the command "nand read", >>> The some information will generate. as following: >>> raise: Signal # 8 caught >>> >>> I also trace the timer.c, But I can't resolve it. As if after the first >>> initial timer, >>> I guess the bss will be clear. >>> >>> Now It is ok after patch this patch. >>> >>> Thanks, >>> seedshope >> >> Thanks for testing. >> >> Did you test with latest version? > > Yes, >> >> Currently, SMDK6400 can't build because didn't rework for relocation. >> If you are OK, could you please fix it? > > Ok, recently, I do the patch for SMD6400 and SMDK6410, > I will send request review in the weekend。 > Thanks! :) Minkyu Kang -- from. prom. www.promsoft.net ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] S3C64XX: timer: replace bss variable by gd
Dear concerned, >> Use the global data instead of bss variable, replace as follow. >> timer_load_val -> timer_rate_hz >> timestamp -> timer_reset_value I am not too happy about this "misuse" of gd->variables making them "misnomers" and the code harder to read. timer_rate_hz is supposed to hold the rate at which the high speed timer increments. timer_reset_value supposedly holds the high speed timer's value when timer_reset() is called. There was a discussion started about this a while ago, but came to no conclusion... Best Regards, Reinhard ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] ftpmu010: fix relocation and enhance features
1. ftpmu010.h: fix and add definitions
Enhanced for more features and asm related support
according to datasheet.
Note:
- FTPMU010_PDLLCR0_HCLKOUTDIS is "incorrect" in datasheet.
- FTPMU010_PDLLCR0_DLLFRANG is only 1 bit at bit #19. (not 20-19)
- FTPMU010_PDLLCR0_HCLKOUTDIS is 4 bits at bit #20. (not 24-21)
2. ftpmu010.c: enhance features and fix relocation
- The following functions is added for pmu features.
ftpmu010_mfpsr_select_dev()
ftpmu010_sdramhtc_set()
- This patch also fix the declare statement for relocation.
Signed-off-by: Macpaul Lin
---
Note:
This patch was based on previous patch:
[Patch v2 1/2] ftpmu010: support faraday ftpmu010 driver
drivers/power/ftpmu010.c | 39 +--
drivers/power/ftpmu010.h | 38 +++---
2 files changed, 72 insertions(+), 5 deletions(-)
diff --git a/drivers/power/ftpmu010.c b/drivers/power/ftpmu010.c
index 7924ac1..b072519 100644
--- a/drivers/power/ftpmu010.c
+++ b/drivers/power/ftpmu010.c
@@ -25,10 +25,10 @@
#include
#include "ftpmu010.h"
-static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
-
+/* OSCC: OSC Control Register */
void ftpmu010_32768osc_enable(void)
{
+ static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
unsigned int oscc;
/* enable the 32768Hz oscillator */
@@ -46,8 +46,31 @@ void ftpmu010_32768osc_enable(void)
writel(oscc, &pmu->OSCC);
}
+/* MFPSR: Multi-Function Port Setting Register */
+void ftpmu010_mfpsr_select_dev(unsigned int dev)
+{
+ static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
+ unsigned int mfpsr;
+
+ mfpsr = readl(&pmu->MFPSR);
+ mfpsr |= dev;
+ writel(mfpsr, &pmu->MFPSR);
+}
+
+void ftpmu010_mfpsr_diselect_dev(unsigned int dev)
+{
+ static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
+ unsigned int mfpsr;
+
+ mfpsr = readl(&pmu->MFPSR);
+ mfpsr &= ~dev;
+ writel(mfpsr, &pmu->MFPSR);
+}
+
+/* PDLLCR0: PLL/DLL Control Register 0 */
void ftpmu010_dlldis_disable(void)
{
+ static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
unsigned int pdllcr0;
pdllcr0 = readl(&pmu->PDLLCR0);
@@ -57,9 +80,21 @@ void ftpmu010_dlldis_disable(void)
void ftpmu010_sdram_clk_disable(unsigned int cr0)
{
+ static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
unsigned int pdllcr0;
pdllcr0 = readl(&pmu->PDLLCR0);
pdllcr0 |= FTPMU010_PDLLCR0_HCLKOUTDIS(cr0);
writel(pdllcr0, &pmu->PDLLCR0);
}
+
+/* SDRAMHTC: SDRAM Signal Hold Time Control */
+void ftpmu010_sdramhtc_set(unsigned int val)
+{
+ static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE;
+ unsigned int sdramhtc;
+
+ sdramhtc = readl(&pmu->SDRAMHTC);
+ sdramhtc |= val;
+ writel(sdramhtc, &pmu->SDRAMHTC);
+}
diff --git a/drivers/power/ftpmu010.h b/drivers/power/ftpmu010.h
index 8ef7a37..58c862b 100644
--- a/drivers/power/ftpmu010.h
+++ b/drivers/power/ftpmu010.h
@@ -126,21 +126,53 @@ struct ftpmu010 {
/*
* Multi-Function Port Setting Register
*/
+#define FTPMU010_MFPSR_DEBUGSEL(1 << 17)
+#define FTPMU010_MFPSR_DMA0PINSEL (1 << 16)
+#define FTPMU010_MFPSR_DMA1PINSEL (1 << 15)
#define FTPMU010_MFPSR_MODEMPINSEL (1 << 14)
#define FTPMU010_MFPSR_AC97CLKOUTSEL (1 << 13)
+#define FTPMU010_MFPSR_PWM1PINSEL (1 << 11)
+#define FTPMU010_MFPSR_PWM0PINSEL (1 << 10)
+#define FTPMU010_MFPSR_IRDACLKSEL (1 << 9)
+#define FTPMU010_MFPSR_UARTCLKSEL (1 << 8)
+#define FTPMU010_MFPSR_SSPCLKSEL (1 << 6)
+#define FTPMU010_MFPSR_I2SCLKSEL (1 << 5)
+#define FTPMU010_MFPSR_AC97CLKSEL (1 << 4)
#define FTPMU010_MFPSR_AC97PINSEL (1 << 3)
+#define FTPMU010_MFPSR_TRIAHBDIS (1 << 1)
+#define FTPMU010_MFPSR_TRIAHBDBG (1 << 0)
/*
* PLL/DLL Control Register 0
+ * Note:
+ * 1. FTPMU010_PDLLCR0_HCLKOUTDIS:
+ * Datasheet indicated it starts at bit #21 which was wrong.
+ * 2. FTPMU010_PDLLCR0_DLLFRAG:
+ * Datasheet indicated it has 2 bit which was wrong.
*/
-#define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0) (((cr0) >> 20) & 0xf)
-#define FTPMU010_PDLLCR0_DLLFRAG (1 << 19)
+#define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0) (((cr0) & 0xf) << 20)
+#define FTPMU010_PDLLCR0_DLLFRAG(cr0) (1 << 19)
#define FTPMU010_PDLLCR0_DLLSTSEL (1 << 18)
#define FTPMU010_PDLLCR0_DLLSTABLE (1 << 17)
#define FTPMU010_PDLLCR0_DLLDIS(1 << 16)
-#define FTPMU010_PDLLCR0_PLL1NS(cr0) (((cr0) >> 3) & 0x1ff)
+#define FTPMU010_PDLLCR0_PLL1FRANG(cr0)(((cr0) & 0x3) << 12)
+#define FTPMU010_PDLLCR0_PLL1NS(cr0) (((cr0) & 0x1ff) << 3)
#define FTPMU010_PDLLCR0_PLL1STSEL (1 << 2)
#define FTPMU010_PDLLCR0_PLL1STABLE
[U-Boot] -a -e values for initrd on s3c2440
Hi , What is the value of -a , -e argument for creating the initrd image on s3c2440. The base address of my RAM is 0x3000 and the kernel (zImage) is loaded to to 0x30008000. The total RAM size is 64 MB. I am uisng uboot version 1.1.6 and linux kernel 2.6.30.4. thanks & regardsGIGIN ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-BOOT] [PATCH 2/6] mv: seperate kirkwood and mmp from common setting
> -Original Message- > From: Lei Wen [mailto:adrian.w...@gmail.com] > Sent: Thursday, January 06, 2011 8:59 AM > To: Prafulla Wadaskar > Cc: Lei Wen; u-boot@lists.denx.de; Yu Tang; Ashish Karkare; Prabhanjan > Sarnaik > Subject: Re: [U-BOOT] [PATCH 2/6] mv: seperate kirkwood and mmp from > common setting ...snip... > >> put into the common code... > >> #ifndef CONFIG_ARMADA100 /* will be removed latter */-#define > >> CONFIG_CMD_EXT2 > >> #define CONFIG_CMD_JFFS2 > >> #define CONFIG_CMD_FAT > >> #define CONFIG_CMD_UBI > >> #define CONFIG_CMD_UBIFS > >> #define CONFIG_RBTREE > >> #define CONFIG_MTD_DEVICE /* needed for mtdparts > commands > >> */ > >> #define CONFIG_MTD_PARTITIONS > >> #define CONFIG_CMD_MTDPARTS > >> #define CONFIG_LZO > >> #endif > > > > Well, we can.. > > only replace #ifndef CONFIG_ARMADA100 with #ifdef CONFIG_SYS_MVFS and > define this macro in arch-kirkwood/config.h, this way in future after > enabling ide, nand, spi driver support just defining the same macro in > armada100/config.h will enable the file system support for armada100 > platforms. > > I think not all platform under marvell would need to enable all those > configure... > What if it only want to enable one setting from this big group, like > it only want the CONFIG_CMD_FAT, > then you need to it set the CONFIG_SYS_MVFS with other unnessary > setting enabled... Please follow the strategy used to include in board config file, further followed by #undef for not needed definitions. Regards.. Prafulla .. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 11/11] powerpc/8xxx: Replace is_fsl_pci_cfg with is_serdes_configured
On Dec 17, 2010, at 5:33 PM, Kumar Gala wrote: > Now that we have serdes support for all 85xx/86xx/Pxxx chips we can > replace the is_fsl_pci_cfg() code with the is_serdes_configured(). > > Signed-off-by: Kumar Gala > --- > arch/powerpc/cpu/mpc8xxx/Makefile |1 - > arch/powerpc/cpu/mpc8xxx/pci_cfg.c| 204 - > arch/powerpc/include/asm/fsl_pci.h|2 - > board/freescale/mpc8544ds/mpc8544ds.c |7 +- > board/freescale/mpc8548cds/mpc8548cds.c |3 +- > board/freescale/mpc8568mds/mpc8568mds.c |3 +- > board/freescale/mpc8569mds/mpc8569mds.c |3 +- > board/freescale/mpc8572ds/mpc8572ds.c |7 +- > board/freescale/mpc8610hpcd/mpc8610hpcd.c | 11 +- > board/freescale/mpc8641hpcn/mpc8641hpcn.c |5 +- > board/freescale/p1_p2_rdb/pci.c | 10 +- > board/freescale/p2020ds/p2020ds.c |7 +- > board/sbc8548/sbc8548.c |3 +- > board/sbc8641d/sbc8641d.c |5 +- > board/tqc/tqm85xx/tqm85xx.c |5 +- > board/xes/common/fsl_8xxx_pci.c | 11 +- > 16 files changed, 39 insertions(+), 248 deletions(-) > delete mode 100644 arch/powerpc/cpu/mpc8xxx/pci_cfg.c applied - k ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] powerpc/85xx: Fix bug in dcache_disable
On Jan 5, 2011, at 10:39 AM, Kumar Gala wrote: > We set the L1 dache register with a bogus register value. Need to be > using 'r3' instead of 'r0'. > > Reported-by: John Traill > Signed-off-by: Kumar Gala > --- > arch/powerpc/cpu/mpc85xx/start.S |4 ++-- > 1 files changed, 2 insertions(+), 2 deletions(-) applied to 85xx - k ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] powerpc/85xx: Rework corenet_ds pci_init_board to use common FSL PCIe code
Remove duplicated code in corenet_ds boards and utilize the common
fsl_pcie_init_board().
Signed-off-by: Kumar Gala
---
board/freescale/corenet_ds/pci.c | 118 +-
1 files changed, 2 insertions(+), 116 deletions(-)
diff --git a/board/freescale/corenet_ds/pci.c b/board/freescale/corenet_ds/pci.c
index 775b623..18a75de 100644
--- a/board/freescale/corenet_ds/pci.c
+++ b/board/freescale/corenet_ds/pci.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2007-2010 Freescale Semiconductor, Inc.
+ * Copyright 2007-2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -28,123 +28,9 @@
#include
#include
-#ifdef CONFIG_PCIE1
-static struct pci_controller pcie1_hose;
-#endif
-
-#ifdef CONFIG_PCIE2
-static struct pci_controller pcie2_hose;
-#endif
-
-#ifdef CONFIG_PCIE3
-static struct pci_controller pcie3_hose;
-#endif
-
-#ifdef CONFIG_PCIE4
-static struct pci_controller pcie4_hose;
-#endif
-
void pci_init_board(void)
{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- struct fsl_pci_info pci_info[4];
- u32 devdisr;
- int first_free_busno = 0;
- int num = 0;
-
- int pcie_ep, pcie_configured;
-
- devdisr = in_be32(&gur->devdisr);
-
- debug (" pci_init_board: devdisr=%x\n", devdisr);
-
-#ifdef CONFIG_PCIE1
- pcie_configured = is_serdes_configured(PCIE1);
-
- if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE1)) {
- set_next_law(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M,
- LAW_TRGT_IF_PCIE_1);
- set_next_law(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K,
- LAW_TRGT_IF_PCIE_1);
- SET_STD_PCIE_INFO(pci_info[num], 1);
- pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
- printf("PCIE1: connected to Slot 1 as %s (base addr %lx)\n",
- pcie_ep ? "End Point" : "Root Complex",
- pci_info[num].regs);
- first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie1_hose, first_free_busno);
- } else {
- printf("PCIE1: disabled\n");
- }
-#else
- setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE1); /* disable */
-#endif
-
-#ifdef CONFIG_PCIE2
- pcie_configured = is_serdes_configured(PCIE2);
-
- if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE2)) {
- set_next_law(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M,
- LAW_TRGT_IF_PCIE_2);
- set_next_law(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K,
- LAW_TRGT_IF_PCIE_2);
- SET_STD_PCIE_INFO(pci_info[num], 2);
- pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
- printf("PCIE2: connected to Slot 3 as %s (base addr %lx)\n",
- pcie_ep ? "End Point" : "Root Complex",
- pci_info[num].regs);
- first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie2_hose, first_free_busno);
- } else {
- printf("PCIE2: disabled\n");
- }
-#else
- setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE2); /* disable */
-#endif
-
-#ifdef CONFIG_PCIE3
- pcie_configured = is_serdes_configured(PCIE3);
-
- if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE3)) {
- set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M,
- LAW_TRGT_IF_PCIE_3);
- set_next_law(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K,
- LAW_TRGT_IF_PCIE_3);
- SET_STD_PCIE_INFO(pci_info[num], 3);
- pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
- printf("PCIE3: connected to Slot 2 as %s (base addr %lx)\n",
- pcie_ep ? "End Point" : "Root Complex",
- pci_info[num].regs);
- first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie3_hose, first_free_busno);
- } else {
- printf("PCIE3: disabled\n");
- }
-#else
- setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE3); /* disable */
-#endif
-
-#ifdef CONFIG_PCIE4
- pcie_configured = is_serdes_configured(PCIE4);
-
- if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE4)) {
- set_next_law(CONFIG_SYS_PCIE4_MEM_PHYS, LAW_SIZE_512M,
- LAW_TRGT_IF_PCIE_4);
- set_next_law(CONFIG_SYS_PCIE4_IO_PHYS, LAW_SIZE_64K,
- LAW_TRGT_IF_PCIE_4);
- SET_STD_PCIE_INFO(pci_info[num], 4);
- pcie_ep = fsl_setup_hose(&pcie4_hose, pci_info[num].regs);
- printf("PCIE
[U-Boot] [PATCH 2/7] powerpc/85xx: Convert MPC8548CDS to use common SRIO init code
Signed-off-by: Kumar Gala
---
board/freescale/mpc8548cds/law.c |5 +
board/freescale/mpc8548cds/tlb.c |9 -
include/configs/MPC8548CDS.h | 15 ---
3 files changed, 13 insertions(+), 16 deletions(-)
diff --git a/board/freescale/mpc8548cds/law.c b/board/freescale/mpc8548cds/law.c
index e59fee8..5b6943d 100644
--- a/board/freescale/mpc8548cds/law.c
+++ b/board/freescale/mpc8548cds/law.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2008,2010 Freescale Semiconductor, Inc.
+ * Copyright 2008,2010-2011 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, w...@denx.de.
@@ -57,9 +57,6 @@ struct law_entry law_table[] = {
#endif
/* LBC window - maps 256M 0xf000 -> 0x */
SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-#ifdef CONFIG_SYS_RIO_MEM_PHYS
- SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
-#endif
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c
index 2267ad7..b2c1b31 100644
--- a/board/freescale/mpc8548cds/tlb.c
+++ b/board/freescale/mpc8548cds/tlb.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008, 2011 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, w...@denx.de.
@@ -58,21 +58,20 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_1G, 1),
-#ifdef CONFIG_SYS_RIO_MEM_PHYS
/*
* TLB 2: 256MNon-cacheable, guarded
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT, CONFIG_SYS_RIO_MEM_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
/*
* TLB 3: 256MNon-cacheable, guarded
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT + 0x1000,
CONFIG_SYS_RIO_MEM_PHYS + 0x1000,
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT + 0x1000,
CONFIG_SYS_SRIO1_MEM_PHYS + 0x1000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_256M, 1),
-#endif
+
/*
* TLB 5: 64M Non-cacheable, guarded
* 0xe000_ 1M CCSRBAR
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 4c5b998..da1f728 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2004, 2007, 2010 Freescale Semiconductor.
+ * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -40,10 +40,12 @@
#define CONFIG_SYS_TEXT_BASE 0xfff8
#endif
+#define CONFIG_SYS_HAS_SRIO
+#define CONFIG_SRIO1 /* SRIO port 1 */
+
#define CONFIG_PCI /* enable any pci type devices */
#define CONFIG_PCI1/* PCI controller 1 */
#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
-#undef CONFIG_RIO
#undef CONFIG_PCI2
#define CONFIG_FSL_PCI_INIT1 /* Use common FSL init code */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
@@ -364,14 +366,13 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_PCIE1_IO_SIZE 0x0010 /* 1M */
#endif
-#ifdef CONFIG_RIO
/*
* RapidIO MMU
*/
-#define CONFIG_SYS_RIO_MEM_VIRT0xC000
-#define CONFIG_SYS_RIO_MEM_BUS 0xC000
-#define CONFIG_SYS_RIO_MEM_SIZE0x2000 /* 512M */
-#endif
+#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC000
+#define CONFIG_SYS_SRIO1_MEM_BUS 0xC000
+#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS
+#define CONFIG_SYS_SRIO1_MEM_SIZE 0x2000 /* 512M */
#ifdef CONFIG_LEGACY
#define BRIDGE_ID 17
--
1.7.2.3
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[U-Boot] [PATCH 3/7] powerpc/85xx: Convert MPC8568MDS to use common SRIO init code
Signed-off-by: Kumar Gala
---
board/freescale/mpc8568mds/law.c |3 +--
include/configs/MPC8568MDS.h | 12
2 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/board/freescale/mpc8568mds/law.c b/board/freescale/mpc8568mds/law.c
index e24b72b..c5cf7ba 100644
--- a/board/freescale/mpc8568mds/law.c
+++ b/board/freescale/mpc8568mds/law.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2008, 2010 Freescale Semiconductor, Inc.
+ * Copyright 2008, 2010-2011 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, w...@denx.de.
@@ -50,7 +50,6 @@
*/
struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_SRIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
/* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */
SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
};
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index a491650..0c858c9 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2004-2007, 2010 Freescale Semiconductor.
+ * Copyright 2004-2007, 2010-2011 Freescale Semiconductor.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -35,6 +35,9 @@
#defineCONFIG_SYS_TEXT_BASE0xfff8
+#define CONFIG_SYS_HAS_SRIO
+#define CONFIG_SRIO1 /* SRIO port 1 */
+
#define CONFIG_PCI 1 /* Enable PCI/PCIE */
#define CONFIG_PCI11 /* PCI controller */
#define CONFIG_PCIE1 1 /* PCIE controller */
@@ -303,9 +306,10 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_PCIE1_IO_PHYS 0xe280
#define CONFIG_SYS_PCIE1_IO_SIZE 0x0080 /* 8M */
-#define CONFIG_SYS_SRIO_MEM_VIRT 0xc000
-#define CONFIG_SYS_SRIO_MEM_BUS0xc000
-#define CONFIG_SYS_SRIO_MEM_PHYS 0xc000
+#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC000
+#define CONFIG_SYS_SRIO1_MEM_BUS 0xC000
+#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS
+#define CONFIG_SYS_SRIO1_MEM_SIZE 0x2000 /* 512M */
#ifdef CONFIG_QE
/*
--
1.7.2.3
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[U-Boot] [PATCH 1/7] powerpc/8xxx: Refactor SRIO initialization into common code
Moved the SRIO init out of corenet_ds and into common code for
8xxx/QorIQ processors that have SRIO. We mimic what we do with PCIe
controllers for SRIO.
We utilize the fact that SRIO is over serdes to determine if its
configured or not and thus can setup the LAWs needed for it dynamically.
We additionally update the device tree (to remove the SRIO nodes) if the
board doesn't have SRIO enabled.
Introduced the following standard defines for board config.h:
CONFIG_SYS_HAS_SRIO - Chip has SRIO or not
CONFIG_SRIO1 - Board has SRIO 1 port available
CONFIG_SRIO2 - Board has SRIO 2 port available
(where 'n' is the port #)
CONFIG_SYS_SRIOn_MEM_VIRT - virtual address in u-boot
CONFIG_SYS_SRIOn_MEM_PHYS - physical address (for law setup)
CONFIG_SYS_SRIOn_MEM_SIZE - size of window (for law setup)
[ These mimic what we have for PCI and PCIe controllers ]
Signed-off-by: Kumar Gala
---
arch/powerpc/cpu/mpc85xx/cpu_init.c |8 +++
arch/powerpc/cpu/mpc85xx/fdt.c |7 +++
arch/powerpc/cpu/mpc8xxx/Makefile |1 +
arch/powerpc/cpu/mpc8xxx/fdt.c | 21
arch/powerpc/cpu/mpc8xxx/srio.c | 86 +++
arch/powerpc/include/asm/fsl_law.h |1 +
board/freescale/corenet_ds/corenet_ds.c | 44
include/configs/corenet_ds.h| 17 +++---
8 files changed, 133 insertions(+), 52 deletions(-)
create mode 100644 arch/powerpc/cpu/mpc8xxx/srio.c
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 4a6cc65..b2be1fc 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -40,6 +40,10 @@
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_SYS_HAS_SRIO
+extern void srio_init(void);
+#endif
+
#ifdef CONFIG_QE
extern qe_iop_conf_t qe_iop_conf_tab[];
extern void qe_config_iopin(u8 port, u8 pin, int dir,
@@ -384,6 +388,10 @@ int cpu_init_r(void)
/* needs to be in ram since code uses global static vars */
fsl_serdes_init();
+#ifdef CONFIG_SYS_HAS_SRIO
+ srio_init();
+#endif
+
#if defined(CONFIG_MP)
setup_mp();
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 53e0596..5cfe497 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -38,6 +38,9 @@ DECLARE_GLOBAL_DATA_PTR;
extern void ft_qe_setup(void *blob);
extern void ft_fixup_num_cores(void *blob);
+#ifdef CONFIG_SYS_HAS_SRIO
+extern void ft_srio_setup(void *blob);
+#endif
#ifdef CONFIG_MP
#include "mp.h"
@@ -478,4 +481,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
fdt_fixup_qportals(blob);
#endif
+
+#ifdef CONFIG_SYS_HAS_SRIO
+ ft_srio_setup(blob);
+#endif
}
diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile
b/arch/powerpc/cpu/mpc8xxx/Makefile
index 95c73be..99332e6 100644
--- a/arch/powerpc/cpu/mpc8xxx/Makefile
+++ b/arch/powerpc/cpu/mpc8xxx/Makefile
@@ -16,6 +16,7 @@ endif
COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
COBJS-$(CONFIG_FSL_LBC) += fsl_lbc.o
+COBJS-$(CONFIG_SYS_HAS_SRIO) += srio.o
SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index 54e60bb..e9dbdc2 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -28,6 +28,7 @@
#include
#include
#include
+#include
#if defined(CONFIG_MP) && (defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx))
static int ft_del_cpuhandle(void *blob, int cpuhandle)
@@ -239,3 +240,23 @@ int fdt_fixup_phy_connection(void *blob, int offset, enum
fsl_phy_enet_if phyc)
return fdt_setprop_string(blob, offset, "phy-connection-type",
fsl_phy_enet_if_str[phyc]);
}
+
+#ifdef CONFIG_SYS_HAS_SRIO
+void ft_srio_setup(void *blob)
+{
+#ifdef CONFIG_SRIO1
+ if (!is_serdes_configured(SRIO1)) {
+ fdt_del_node_and_alias(blob, "rio0");
+ }
+#else
+ fdt_del_node_and_alias(blob, "rio0");
+#endif
+#ifdef CONFIG_SRIO2
+ if (!is_serdes_configured(SRIO2)) {
+ fdt_del_node_and_alias(blob, "rio1");
+ }
+#else
+ fdt_del_node_and_alias(blob, "rio1");
+#endif
+}
+#endif
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
new file mode 100644
index 000..e46d328
--- /dev/null
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Pub
[U-Boot] [PATCH 4/7] powerpc/85xx: Convert MPC8569MDS to use common SRIO init code
Signed-off-by: Kumar Gala
---
board/freescale/mpc8569mds/law.c |3 +--
include/configs/MPC8569MDS.h | 12
2 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/board/freescale/mpc8569mds/law.c b/board/freescale/mpc8569mds/law.c
index bcd0311..4f4a93b 100644
--- a/board/freescale/mpc8569mds/law.c
+++ b/board/freescale/mpc8569mds/law.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, w...@denx.de.
@@ -52,7 +52,6 @@ struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_1G, LAW_TRGT_IF_DDR),
#endif
SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_SRIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index 814c175..2c2d775 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -35,6 +35,9 @@
#define CONFIG_FSL_ELBC1 /* Has Enhance localbus
controller */
+#define CONFIG_SYS_HAS_SRIO
+#define CONFIG_SRIO1 /* SRIO port 1 */
+
#define CONFIG_PCI 1 /* Disable PCI/PCIE */
#define CONFIG_PCIE1 1 /* PCIE controller */
#define CONFIG_FSL_PCI_INIT1 /* use common fsl pci init code */
@@ -355,9 +358,10 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_PCIE1_IO_PHYS 0xe280
#define CONFIG_SYS_PCIE1_IO_SIZE 0x0080 /* 8M */
-#define CONFIG_SYS_SRIO_MEM_VIRT 0xc000
-#define CONFIG_SYS_SRIO_MEM_BUS0xc000
-#define CONFIG_SYS_SRIO_MEM_PHYS 0xc000
+#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC000
+#define CONFIG_SYS_SRIO1_MEM_BUS 0xC000
+#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS
+#define CONFIG_SYS_SRIO1_MEM_SIZE 0x2000 /* 512M */
#ifdef CONFIG_QE
/*
--
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[U-Boot] [PATCH 5/7] powerpc/86xx: Enable common SRIO init code
Add the needed defines and code to utilize the common 8xxx srio init
code to setup LAWs and modify device tree if we have SRIO enabled on a
board.
Signed-off-by: Kumar Gala
---
arch/powerpc/cpu/mpc86xx/fdt.c|9 -
arch/powerpc/include/asm/immap_86xx.h |4 +++-
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/cpu/mpc86xx/fdt.c b/arch/powerpc/cpu/mpc86xx/fdt.c
index ff89ee5..3b96bf5 100644
--- a/arch/powerpc/cpu/mpc86xx/fdt.c
+++ b/arch/powerpc/cpu/mpc86xx/fdt.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2008,2010 Freescale Semiconductor, Inc.
+ * Copyright 2008, 2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@@ -14,6 +14,9 @@
DECLARE_GLOBAL_DATA_PTR;
extern void ft_fixup_num_cores(void *blob);
+#ifdef CONFIG_SYS_HAS_SRIO
+extern void ft_srio_setup(void *blob);
+#endif
void ft_cpu_setup(void *blob, bd_t *bd)
{
@@ -58,4 +61,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
ft_fixup_num_cores(blob);
#endif
+
+#ifdef CONFIG_SYS_HAS_SRIO
+ ft_srio_setup(blob);
+#endif
}
diff --git a/arch/powerpc/include/asm/immap_86xx.h
b/arch/powerpc/include/asm/immap_86xx.h
index 4e60cbb..cc338e4 100644
--- a/arch/powerpc/include/asm/immap_86xx.h
+++ b/arch/powerpc/include/asm/immap_86xx.h
@@ -1,7 +1,7 @@
/*
* MPC86xx Internal Memory Map
*
- * Copyright 2004 Freescale Semiconductor
+ * Copyright 2004, 2011 Freescale Semiconductor
* Jeff Brown (jeff...@freescale.com)
* Srikanth Srinivasan (srikanth.sriniva...@freescale.com)
*
@@ -1205,6 +1205,8 @@ typedef struct ccsr_gur {
#define MPC86xx_DEVDISR_PCI1 0x8000
#define MPC86xx_DEVDISR_PCIE1 0x4000
#define MPC86xx_DEVDISR_PCIE2 0x2000
+#define MPC86xx_DEVDISR_SRIO 0x0008
+#define MPC86xx_DEVDISR_RMSG 0x0004
#define MPC86xx_DEVDISR_CPU0 0x8000
#define MPC86xx_DEVDISR_CPU1 0x4000
#define MPC86xx_RSTCR_HRST_REQ 0x0002
--
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[U-Boot] [PATCH 6/7] powerpc/86xx: Convert MPC8641HPCN to use common SRIO init code
Signed-off-by: Kumar Gala
---
board/freescale/mpc8641hpcn/law.c |5 +
include/configs/MPC8641HPCN.h | 30 +-
2 files changed, 14 insertions(+), 21 deletions(-)
diff --git a/board/freescale/mpc8641hpcn/law.c
b/board/freescale/mpc8641hpcn/law.c
index 30a7b70..08f1eb2 100644
--- a/board/freescale/mpc8641hpcn/law.c
+++ b/board/freescale/mpc8641hpcn/law.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2008,2010 Freescale Semiconductor, Inc.
+ * Copyright 2008,2010-2011 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, w...@denx.de.
@@ -53,9 +53,6 @@ struct law_entry law_table[] = {
#if !defined(CONFIG_SPD_EEPROM)
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
#endif
-#if defined(CONFIG_RIO)
- SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
-#endif
SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_LBC),
};
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index fea0876..dc3b1d7 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2006, 2010 Freescale Semiconductor.
+ * Copyright 2006, 2010-2011 Freescale Semiconductor.
*
* Srikanth Srinivasan (srikanth.sriniva...@freescale.com)
*
@@ -57,18 +57,14 @@
*/
#define CONFIG_SYS_SCRATCH_VA 0xe000
-/*
- * set this to enable Rapid IO. PCI and RIO are mutually exclusive
- */
-/*#define CONFIG_RIO 1*/
+#define CONFIG_SYS_HAS_SRIO
+#define CONFIG_SRIO1 /* SRIO port 1 */
-#ifndef CONFIG_RIO /* RIO/PCI are mutually exclusive */
#define CONFIG_PCI 1 /* Enable PCI/PCIE */
#define CONFIG_PCIE1 1 /* PCIE controler 1 (ULI bridge) */
#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot) */
#define CONFIG_FSL_PCI_INIT1 /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-#endif
#define CONFIG_FSL_LAW 1 /* Use common FSL law init code */
#define CONFIG_TSEC_ENET /* tsec ethernet support */
@@ -319,13 +315,13 @@ extern unsigned long get_board_sys_clk(unsigned long
dummy);
/*
* RapidIO MMU
*/
-#define CONFIG_SYS_RIO_MEM_BASE0x8000 /* base address */
+#define CONFIG_SYS_SRIO1_MEM_BASE 0x8000 /* base address */
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_RIO_MEM_PHYS 0x000cULL
+#define CONFIG_SYS_SRIO1_MEM_PHYS 0x000cULL
#else
-#define CONFIG_SYS_RIO_MEM_PHYSCONFIG_SYS_RIO_MEM_BASE
+#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BASE
#endif
-#define CONFIG_SYS_RIO_MEM_SIZE0x2000 /* 128M */
+#define CONFIG_SYS_SRIO1_MEM_SIZE 0x2000 /* 128M */
/*
* General PCI
@@ -514,18 +510,18 @@ extern unsigned long get_board_sys_clk(unsigned long
dummy);
| BATL_PP_RW | BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
#else /* CONFIG_RIO */
-#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \
+#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS) \
| BATL_PP_RW | BATL_CACHEINHIBIT | \
BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M \
+#define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \
| BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \
+#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS) \
| BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW \
+#define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_PHYS | BATL_PP_RW \
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_PHYS | BATU_BL_512M |
BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW |
BATL_CACHEINHIBIT)
+#define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_PHYS | BATU_BL_512M |
BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_PHYS | BATL_PP_RW |
BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
#endif
--
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[U-Boot] [PATCH 7/7] powerpc/86xx: Convert SBC8641 to use common SRIO init code
Signed-off-by: Kumar Gala
CC: Paul Gortmaker
---
board/sbc8641d/law.c |1 -
include/configs/sbc8641d.h | 15 +--
2 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/board/sbc8641d/law.c b/board/sbc8641d/law.c
index a6f60ee..14259d6 100644
--- a/board/sbc8641d/law.c
+++ b/board/sbc8641d/law.c
@@ -51,7 +51,6 @@ struct law_entry law_table[] = {
#endif
SET_LAW(0xf800, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
SET_LAW(0xfe00, LAW_SIZE_32M, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO)
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index 90d84eb..f425150 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -57,6 +57,9 @@
*/
#define CONFIG_SYS_SCRATCH_VA 0xe800
+#define CONFIG_SYS_HAS_SRIO
+#define CONFIG_SRIO1 /* SRIO port 1 */
+
#define CONFIG_PCI 1 /* Enable PCIE */
#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
@@ -297,9 +300,9 @@
/*
* RapidIO MMU
*/
-#define CONFIG_SYS_RIO_MEM_BASE0xc000 /* base address */
-#define CONFIG_SYS_RIO_MEM_PHYSCONFIG_SYS_RIO_MEM_BASE
-#define CONFIG_SYS_RIO_MEM_SIZE0x2000 /* 128M */
+#define CONFIG_SYS_SRIO1_MEM_BASE 0xc000 /* base address */
+#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BASE
+#define CONFIG_SYS_SRIO1_MEM_SIZE 0x2000 /* 128M */
/*
* General PCI
@@ -417,10 +420,10 @@
* BAT2 512M Cache-inhibited, guarded
* 0xc000_ 512M RapidIO Memory
*/
-#define CONFIG_SYS_DBAT2L (CONFIG_SYS_RIO_MEM_BASE | BATL_PP_RW \
+#define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \
| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M |
BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_RIO_MEM_BASE | BATL_PP_RW |
BATL_CACHEINHIBIT)
+#define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M |
BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW |
BATL_CACHEINHIBIT)
#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
/*
--
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[U-Boot] [PATCH] powerpc/85xx: Add SRIO support to P2020DS
From: Li Yang The P2020 has 2 SRIO ports and they are useable on the P2020 DS board. Enable them using the common SRIO init code. Signed-off-by: Li Yang Signed-off-by: Kumar Gala --- include/configs/P2020DS.h | 24 +++- 1 files changed, 23 insertions(+), 1 deletions(-) diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index 24f2498..ca093d8 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -1,5 +1,5 @@ /* - * Copyright 2007-2010 Freescale Semiconductor, Inc. + * Copyright 2007-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -45,6 +45,10 @@ #define CONFIG_SYS_TEXT_BASE 0xeff8 #endif +#define CONFIG_SYS_HAS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ +#define CONFIG_SRIO2 /* SRIO port 2 */ + #define CONFIG_FSL_ELBC1 /* Has Enhanced localbus controller */ #define CONFIG_PCI 1 /* Enable PCI/PCIE */ #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ @@ -472,6 +476,24 @@ #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET #endif +/* SRIO1 uses the same window as PCIE2 mem window */ +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc2000ull +#else +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa000 +#endif +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x2000 /* 512M */ + +/* SRIO2 uses the same window as PCIE1 mem window */ +#define CONFIG_SYS_SRIO2_MEM_VIRT 0xc000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc4000ull +#else +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc000 +#endif +#define CONFIG_SYS_SRIO2_MEM_SIZE 0x2000 /* 512M */ + #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ -- 1.6.0.6 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] fsl_pci: Update PCIe boot ouput
On Tue, Dec 28, 2010 at 6:47 PM, Peter Tyser wrote: > This change does the following: > - Adds printing of negotiated link width. This information can be > useful when debugging PCIe issues. > - Makes it optional for boards to implement board_serdes_name(). > Previously boards that did not implement it would print unsightly > output such as "PCIE1: Connected to ..." > - Rewords the PCIe boot output to reduce line length and to make it > clear that the "base address XYZ" value refers to the base address of > the internal processor PCIe registers and not a standard PCI BAR > value. > - Changes "PCIE" output to the standard "PCIe" > > Before change: > PCIE1: connected to as Root Complex (base addr ef008000) > 01:00.0 - 10b5:8518 - Bridge device > 02:01.0 - 10b5:8518 - Bridge device > 02:02.0 - 10b5:8518 - Bridge device > 02:03.0 - 10b5:8518 - Bridge device > PCIE1: Bus 00 - 05 > PCIE2: connected to as Endpoint (base addr ef009000) > PCIE2: Bus 06 - 06 > > After change: > PCIe1: Root Complex of PEX8518 Switch, x4, regs @ 0xef008000 > 01:00.0 - 10b5:8518 - Bridge device > 02:01.0 - 10b5:8518 - Bridge device > 02:02.0 - 10b5:8518 - Bridge device > 02:03.0 - 10b5:8518 - Bridge device > PCIe1: Bus 00 - 05 > PCIe2: Endpoint of VPX Fabric A, x2, regs @ 0xef009000 > PCIe2: Bus 06 - 06 > > Signed-off-by: Peter Tyser Tested-by: Paul Gortmaker The sbc8641d had the same issue; I've put the before and after below for reference. Paul. --- Board: Wind River SBC8641D I2C: ready DRAM: DDR: 512 MiB FLASH: 16 MiB PCIE1: connected to as Root Complex (base addr f8008000) 01:00.0 - 1148:9e00 - Network controller PCIE1: Bus 00 - 01 PCIE2: connected to as Root Complex (base addr f8009000) PCIE2: Bus 02 - 02 In:serial Out: serial Err: serial Net: eTSEC1, eTSEC2, eTSEC3, eTSEC4 - Board: Wind River SBC8641D I2C: ready DRAM: DDR: 512 MiB FLASH: 16 MiB PCIe1: Root Complex, x1, regs @ 0xf8008000 01:00.0 - 1148:9e00 - Network controller PCIe1: Bus 00 - 01 PCIe2: Root Complex, no link, regs @ 0xf8009000 PCIe2: Bus 02 - 02 In:serial Out: serial Err: serial Net: eTSEC1, eTSEC2, eTSEC3, eTSEC4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 7/7] powerpc/86xx: Convert SBC8641 to use common SRIO init code
[[PATCH 7/7] powerpc/86xx: Convert SBC8641 to use common SRIO init code] On
06/01/2011 (Thu 10:58) Kumar Gala wrote:
> Signed-off-by: Kumar Gala
> CC: Paul Gortmaker
Tested in conjuntion with the mpc85xx dev branch and Peter's patch.
For some reason flash erase doesn't work, but I'm guessing that is a
completely unrelated regression that I'll need to track down.
Tested-by: Paul Gortmaker
P.
> ---
> board/sbc8641d/law.c |1 -
> include/configs/sbc8641d.h | 15 +--
> 2 files changed, 9 insertions(+), 7 deletions(-)
>
> diff --git a/board/sbc8641d/law.c b/board/sbc8641d/law.c
> index a6f60ee..14259d6 100644
> --- a/board/sbc8641d/law.c
> +++ b/board/sbc8641d/law.c
> @@ -51,7 +51,6 @@ struct law_entry law_table[] = {
> #endif
> SET_LAW(0xf800, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
> SET_LAW(0xfe00, LAW_SIZE_32M, LAW_TRGT_IF_LBC),
> - SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO)
> };
>
> int num_law_entries = ARRAY_SIZE(law_table);
> diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
> index 90d84eb..f425150 100644
> --- a/include/configs/sbc8641d.h
> +++ b/include/configs/sbc8641d.h
> @@ -57,6 +57,9 @@
> */
> #define CONFIG_SYS_SCRATCH_VA0xe800
>
> +#define CONFIG_SYS_HAS_SRIO
> +#define CONFIG_SRIO1 /* SRIO port 1 */
> +
> #define CONFIG_PCI 1 /* Enable PCIE */
> #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
> #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
> @@ -297,9 +300,9 @@
> /*
> * RapidIO MMU
> */
> -#define CONFIG_SYS_RIO_MEM_BASE 0xc000 /* base address */
> -#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
> -#define CONFIG_SYS_RIO_MEM_SIZE 0x2000 /* 128M */
> +#define CONFIG_SYS_SRIO1_MEM_BASE0xc000 /* base address */
> +#define CONFIG_SYS_SRIO1_MEM_PHYSCONFIG_SYS_SRIO1_MEM_BASE
> +#define CONFIG_SYS_SRIO1_MEM_SIZE0x2000 /* 128M */
>
> /*
> * General PCI
> @@ -417,10 +420,10 @@
> * BAT2 512M Cache-inhibited, guarded
> * 0xc000_ 512M RapidIO Memory
> */
> -#define CONFIG_SYS_DBAT2L(CONFIG_SYS_RIO_MEM_BASE | BATL_PP_RW \
> +#define CONFIG_SYS_DBAT2L(CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \
> | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
> -#define CONFIG_SYS_DBAT2U(CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M |
> BATU_VS | BATU_VP)
> -#define CONFIG_SYS_IBAT2L(CONFIG_SYS_RIO_MEM_BASE | BATL_PP_RW |
> BATL_CACHEINHIBIT)
> +#define CONFIG_SYS_DBAT2U(CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M |
> BATU_VS | BATU_VP)
> +#define CONFIG_SYS_IBAT2L(CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW |
> BATL_CACHEINHIBIT)
> #define CONFIG_SYS_IBAT2UCONFIG_SYS_DBAT2U
>
> /*
> --
> 1.7.2.3
>
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[U-Boot] ATTN
Your email address has made you a winner of 11,000,000 USD, Contact our Agent Mr. Datson Galleon via: e-mail, datsongall...@bigstring.com, Tel: +1404-566-0625 for immediate response/details. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 15/15] powerpc/85xx: Rework SBC8548 pci_init_board to use common FSL PCIe code
[[PATCH 15/15] powerpc/85xx: Rework SBC8548 pci_init_board to use common FSL PCIe code] On 17/12/2010 (Fri 17:50) Kumar Gala wrote: > Remove duplicated code in SBC8548 board and utliize the common > fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI > controllers based on which PCIe controllers are enabled. > > Signed-off-by: Kumar Gala > CC: Paul Gortmaker Tested-by: Paul Gortmaker Tested with Peter's anti-NULL patch on top of the mpc85xx dev branch. Board has both PCI-X and PCI-e slots, with e1000 and skge respectively. P. --- U-Boot 2010.12-00426-ged7ea8f (Jan 06 2011 - 15:43:08) CPU: 8548E, Version: 2.0, (0x80390020) Core: E500, Version: 2.0, (0x80210020) Clock Configuration: CPU0:990 MHz, CCB:396 MHz, DDR:198 MHz (396 MT/s data rate), LBC:99 MHz L1:D-cache 32 kB enabled I-cache 32 kB enabled Board: Wind River SBC8548 Rev. 0x2 I2C: ready DRAM: SDRAM: 128 MiB DDR: 256 MiB (DDR2, 64-bit, CL=4, ECC off) DDR Chip-Select Interleaving Mode: CS0+CS1 FLASH: 72 MiB L2:512 KB already enabled *** Warning - bad CRC, using default environment PCI: Host, 64 bit, 66 MHz, sync, arbiter 00:01.0 - 8086:1026 - Network controller PCI1: Bus 00 - 00 PCIe1: Root Complex, x1, regs @ 0xe000a000 02:00.0 - 1148:9e00 - Network controller PCIe1: Bus 01 - 02 In:serial Out: serial Err: serial Net: eTSEC0, eTSEC1 Hit any key to stop autoboot: 0 => pci 0 Scanning PCI devices on bus 0 BusDevFun VendorId DeviceId Device Class Sub-Class _ 00.00.00 0x1057 0x0012 Processor 0x20 00.01.00 0x8086 0x1026 Network controller 0x00 => pci 1 Scanning PCI devices on bus 1 BusDevFun VendorId DeviceId Device Class Sub-Class _ 01.00.00 0x1957 0x0012 Processor 0x20 => pci 2 Scanning PCI devices on bus 2 BusDevFun VendorId DeviceId Device Class Sub-Class _ 02.00.00 0x1148 0x9e00 Network controller 0x00 => ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] SunnyVision Colud Server
SunnyVision Cloud Server雲端伺服器 To view it online, please go here: http://sv-edm-001.hkcolocation.com/emailmarketer/display.php?M=328181&C=d90bfe70658c39d20abe5d82c7c12bdc&S=57&L=38&N=24 Advantages of Cloud Server 雲端伺服器服務優勢 Cloud Server provides you with the same function as a traditional dedicated server, plus the high availability, scalability and flexibility that a dedicated server cannot offer to you. 雲端伺服器提供與傳統專屬伺服器同等的效能，而且額外的高可用性、擴展性及彈性給您比傳統專屬伺服器更多的方便。 a. Costing Saving 節省成本 b. High Flexibility & Scalability 高彈性及擴展性 c. High Availability & Reliability 高可用性及可靠性 d. Self-owned World-class Data Center 自建國際級數據中心 Linux Cloud Server Windows Cloud Server Your prompt feedback and response will be highly appreciated. Best Regards, Kevin SunnyVision Limited Email: ke...@sunnyvision.comWeb Site: http://sv-edm-001.hkcolocation.com/emailmarketer/link.php?M=328181&N=57&L=2&F=T Click this link to unsubscribe: http://sv-edm-001.hkcolocation.com/emailmarketer/unsubscribe.php?M=328181&C=d90bfe70658c39d20abe5d82c7c12bdc&L=38&N=57 <<4a0e84d7d6f437ad4fd4784c7ef9e9fe>>___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] getenv_yesno() and autostart
Commit 5a442c0addc69d0c4b58e98e5aec1cf07576debb switched NAND (among other things) from explicitly checking autostart for "yes" to using getenv_yesno(). Instead of checking for "yes", getenv_yesno() checks for "no", and assumes "yes" if it can't find anything. This changes the default behavior, with no autostart environment variable defined, from "no" to "yes". I don't think "yes" is a desireable default for autostart[1]. README does not specify the default behavior. It also doesn't specify that autostart applies to NAND commands at all, for that matter. Should getenv_yesno()'s behavior be changed? Are there cases where a default of "yes" is legitimately wanted (if so, a parameter could be added for the requested default)? -Scott [1] I'm not sure that the feature makes sense at all, as often one would need to load an RFS and/or a device tree first, not to mention that you may be trying to update U-Boot itself. Autostart doesn't do anything that you couldn't do yourself by following the load command with "bootm $fileaddr". ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-BOOT] [PATCH V3] mtd: nand: Allow caller to pass alternative ID table to nand_scan_ident()
On Thu, Jan 06, 2011 at 09:48:18AM +0800, Lei Wen wrote: > This patch sync with David's patch on Linux for handling nand_scan_ident. > > commit 5e81e88a4c140586d9212999cea683bcd66a15c6 > Author: David Woodhouse > Date: Fri Feb 26 18:32:56 2010 + > > mtd: nand: Allow caller to pass alternative ID table to > nand_scan_ident() > > Signed-off-by: David Woodhouse > > Signed-off-by: Lei Wen > --- > V2: Add original patch owner signature, and fix that patch accoring to > comments on const type. > V3: Fix nand_scan_ident parameter as const Applied to u-boot-nand-flash. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] getenv_yesno() and autostart
On Thu, Jan 6, 2011 at 4:56 PM, Scott Wood wrote: > Commit 5a442c0addc69d0c4b58e98e5aec1cf07576debb switched NAND > (among other things) from explicitly checking autostart for "yes" > to using getenv_yesno(). this has been discussed twice so far on the list. Wolfgang plans on reverting it at some point. -mike ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] "b reset" does not work in u-boot_v2010.12-rc3 with eldk4.2
Hi,when i upgrade uboot from 1.1.2 to v2010.12-rc3 i met a great number of problems. Before, i use skyeye to simulate uboot. furthermore i use "arm-linux-gdb u-boot"(eldk-4.2) to step by step executes u-boot the result like below: (gdb) tar remote :12345 Remote debugging using :12345 _start () at start.S:40 40 start.S: No such file or directory. in start.S Current language: auto; currently asm (gdb) (gdb) step _start () at start.S:41 41 in start.S (gdb) _start () at start.S:42 42 in start.S (gdb) _start () at start.S:43 43 in start.S (gdb) _start () at start.S:44 44 in start.S (gdb) _start () at start.S:45 45 in start.S (gdb) _start () at start.S:46 46 in start.S (gdb) _start () at start.S:47 47 in start.S (gdb) reset () at start.S:108 108 in start.S (gdb) reset () at start.S:109 109 in start.S (gdb) reset () at start.S:110 110 in start.S (gdb) reset () at start.S:111 111 in start.S (gdb) reset () at start.S:118 118 in start.S (gdb) reset () at start.S:124 124 in start.S (gdb) call_board_init_f () at start.S:129 129 in start.S (gdb) call_board_init_f () at start.S:130 130 in start.S (gdb) call_board_init_f () at start.S:131 131 in start.S (gdb) call_board_init_f () at start.S:132 132 in start.S (gdb) These indicate that in start.S,first instruction:b reset not jump success The process just go from one instruction to the next. What may be the problem?any suggestions is appreciate. MrGates ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] Divides variable of linker flags to LDFLAGS-u-boot and LDFLAGS
On Wednesday, January 05, 2011 20:23:54 Nobuhiro Iwamatsu wrote: > --- a/arch/i386/config.mk > +++ b/arch/i386/config.mk > @@ -35,5 +35,6 @@ PLATFORM_CPPFLAGS += $(call cc-option, > -fno-stack-protector) PLATFORM_CPPFLAGS += $(call cc-option, > -mpreferred-stack-boundary=2) PLATFORM_CPPFLAGS += -DCONFIG_I386 > -D__I386__ > > -LDFLAGS += --cref --gc-sections > +LDFLAGS += --cref this adds a trailing space otherwise, this makes Blackfin work better ... i'll s-o-b the v3 patch ;) -mike signature.asc Description: This is a digitally signed message part. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Entry point for uncompressed kernel image
Hi , I am trying to put uncompressed kernel image to SDRAM for my s3c2440 development board. The uncompressed kernel image is made from 'Image' inside arch/arm/boot folder using the mkimage tool. What should be the entry point and load address for the uncompressed kernel image ? The physical address of my RAM is 0x3000 and the zImage is loaded to the address 0x30008000. thanks & regardsGIGIN ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 8/8] armv7: adapt s5pc1xx to the new cache maintenance framework
Dear Aneesh V,
On 27 December 2010 20:22, Aneesh V wrote:
> Dear Minkyu Kang,
>
> On Monday 27 December 2010 12:55 PM, Minkyu Kang wrote:
> < snip >
>>>
>>> +
>>> +#ifndef CONFIG_SYS_NO_DCACHE
>>> +void v7_setup_outer_cache_ops(void)
>>> +{
>>> +#ifndef CONFIG_L2_OFF
>>> + v7_outer_cache.enable = ca8_l2_cache_enable;
>>> + v7_outer_cache.disable = ca8_l2_cache_disable;
>>> +#endif
>>> +}
>>> +#endif
>>
>> I don't agree with add this function at clock.c.
>> If need we can make new file as omap3/4 case.
>
> I didn't want to add a new file just for this small function. But no
> problem, I will do that in the next revision.
>
OK, please make soc.c.
I have plan to move reset.S to this file.
Thanks.
Minkyu Kang
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Re: [U-Boot] Entry point for uncompressed kernel image
Hi , I am getting an exception once I try to boot the image with bootm command. Boardcon> bootm 30008000 ## Booting image at 30008000 ... Image Name: Created: 2011-01-07 6:04:55 UTC Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 3035360 Bytes = 2.9 MB Load Address: 30008000 Entry Point: 30008000 Verifying Checksum ... OK XIP Kernel Image ... OK initrd_start:0 ,initrd_end : 0 ## Transferring control to Linux (at address 30008000) ... Starting kernel ...30008000 bd->bi_arch_number:168 , bd->bi_boot_params:805306624data abort pc : [<30008010>] lr : [<33d9f098>] sp : 33d3da98 ip : fp : r10: 0001 r9 : r8 : 33d3ffdc r7 : r6 : 33de2f84 r5 : 33d409e2 r4 : r3 : 30008000 r2 : 3100 r1 : 00a8 r0 : ea16 Flags: nZCv IRQs off FIQs off Mode SVC_32 Resetting CPU ... The above is an uncompressed kernel image with load and entry point as 30008000. Can you suggest with how I can debug the issue. thanks & regardsGIGIN --- On Fri, 7/1/11, Pankaj Pandey wrote: From: Pankaj Pandey Subject: Re: [U-Boot] Entry point for uncompressed kernel image To: "Gigin Jose" Date: Friday, 7 January, 2011, 10:52 AM hi u can define same 0x30008000 as entry and load address. Regards, Pankaj Pandey On Fri, Jan 7, 2011 at 2:07 PM, Gigin Jose wrote: Hi , I am trying to put uncompressed kernel image to SDRAM for my s3c2440 development board. The uncompressed kernel image is made from 'Image' inside arch/arm/boot folder using the mkimage tool. What should be the entry point and load address for the uncompressed kernel image ? The physical address of my RAM is 0x3000 and the zImage is loaded to the address 0x30008000. thanks & regardsGIGIN ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Entry point for uncompressed kernel image
Hi , Here goes my bootargs ..bootargs=noinitrd root=/dev/mtdblock2 init=/linuxrc console=ttySAC0. >From the exception, I was able to understand that a data abort >has occurred and my is stopping at 30008010 address. But I was not able >to locate this address in System.map. My System.map starts from 33d8 and >ends in 33de3918. Is there any software package tool for JTAG debugging. thanks & regardsGIGIN --- On Fri, 7/1/11, Pankaj Pandey wrote: From: Pankaj Pandey Subject: Re: [U-Boot] Entry point for uncompressed kernel image To: "Gigin Jose" Date: Friday, 7 January, 2011, 11:58 AM hi...can you please share me ur bootargs plz...for debugging this issue u need to connect ur board with hardware debugger through JTAG and start debugging from kernel entry point which at ./arch/arm/kernel/head.S Regards, Pankaj Pandey On Fri, Jan 7, 2011 at 3:15 PM, Gigin Jose wrote: Hi , I am getting an exception once I try to boot the image with bootm command. Boardcon> bootm 30008000 ## Booting image at 30008000 ... Image Name: Created: 2011-01-07 6:04:55 UTC Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 3035360 Bytes = 2.9 MB Load Address: 30008000 Entry Point: 30008000 Verifying Checksum ... OK XIP Kernel Image ... OK initrd_start:0 ,initrd_end : 0 ## Transferring control to Linux (at address 30008000) ... Starting kernel ...30008000 bd->bi_arch_number:168 , bd->bi_boot_params:805306624data abort pc : [<30008010>] lr : [<33d9f098>] sp : 33d3da98 ip : fp : r10: 0001 r9 : r8 : 33d3ffdc r7 : r6 : 33de2f84 r5 : 33d409e2 r4 : r3 : 30008000 r2 : 3100 r1 : 00a8 r0 : ea16 Flags: nZCv IRQs off FIQs off Mode SVC_32 Resetting CPU ... The above is an uncompressed kernel image with load and entry point as 30008000. Can you suggest with how I can debug the issue. thanks & regardsGIGIN --- On Fri, 7/1/11, Pankaj Pandey wrote: From: Pankaj Pandey Subject: Re: [U-Boot] Entry point for uncompressed kernel image To: "Gigin Jose" Date: Friday, 7 January, 2011, 10:52 AM hi u can define same 0x30008000 as entry and load address. Regards, Pankaj Pandey On Fri, Jan 7, 2011 at 2:07 PM, Gigin Jose wrote: Hi , I am trying to put uncompressed kernel image to SDRAM for my s3c2440 development board. The uncompressed kernel image is made from 'Image' inside arch/arm/boot folder using the mkimage tool. What should be the entry point and load address for the uncompressed kernel image ? The physical address of my RAM is 0x3000 and the zImage is loaded to the address 0x30008000. thanks & regardsGIGIN ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3] mpq101: initial support for Mercury Computer Systems MPQ101 board
Mpq101 is a RapidIO development board in AMC form factor, featuring MPC8548 processor, 512MB of hardwired DDR2 RAM, 128MB of hardwired NAND flash memory, real time clock and additional serial EEPROM on i2c bus (enabled). USB controller is available, but not presently enabled. Additional board information is available at: http://www.mc.com/products/boards/ensemble_mpq101_rapidio_powerquicc_iii.aspx Environment is configured to preceed the actual u-boot image so that it's located at the beginning of flash erase block (made necessary by the recent changes to the embedded environment handling). Signed-off-by: Alex Dubov --- MAINTAINERS|3 + board/mercury/mpq101/Makefile | 53 + board/mercury/mpq101/config.mk |6 + board/mercury/mpq101/law.c | 55 ++ board/mercury/mpq101/mpq101.c | 146 ++ board/mercury/mpq101/tlb.c | 82 boards.cfg |1 + include/configs/mpq101.h | 410 8 files changed, 756 insertions(+), 0 deletions(-) create mode 100644 board/mercury/mpq101/Makefile create mode 100644 board/mercury/mpq101/config.mk create mode 100644 board/mercury/mpq101/law.c create mode 100644 board/mercury/mpq101/mpq101.c create mode 100644 board/mercury/mpq101/tlb.c create mode 100644 include/configs/mpq101.h diff --git a/MAINTAINERS b/MAINTAINERS index 9258cb1..e31fc5e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -138,6 +138,9 @@ Jon Diekema sbc8260 MPC8260 +Alex Dubov + mpq101 MPC8548 + Dirk Eibach devconcenterPPC460EX diff --git a/board/mercury/mpq101/Makefile b/board/mercury/mpq101/Makefile new file mode 100644 index 000..58bc1b3 --- /dev/null +++ b/board/mercury/mpq101/Makefile @@ -0,0 +1,53 @@ +# +# Copyright 2007 Freescale Semiconductor, Inc. +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).o + +COBJS-y+= $(BOARD).o +COBJS-y+= law.o +COBJS-y+= tlb.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB):$(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/board/mercury/mpq101/config.mk b/board/mercury/mpq101/config.mk new file mode 100644 index 000..1d83f9a --- /dev/null +++ b/board/mercury/mpq101/config.mk @@ -0,0 +1,6 @@ +# +# mpq101 board +# + +# Make room for environment at the beginning of flash sector +LDFLAGS += --section-start=.ppcenv=$(CONFIG_ENV_ADDR) diff --git a/board/mercury/mpq101/law.c b/board/mercury/mpq101/law.c new file mode 100644 index 000..726b5c2 --- /dev/null +++ b/board/mercury/mpq101/law.c @@ -0,0 +1,55 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, w...@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * LAW(Local Access
