Re: [U-Boot] RAM burst mode problem
On Thu, Sep 17, 2009 at 5:42 PM, Mikhail Zaturenskiy wrote: > We finally solved our DRAM timing problem so I wanted to follow up on > my question. > > On Fri, Sep 4, 2009 at 1:41 AM, Frank Svendsbøe > wrote: >> Hi Mikhail, >> Burst mode UPM setup is not trivial, and it is quite amount of work to >> go through your table, so >> I'm not surprised nobody has replied. > > I know, I'm not too surprised either :) > > >> I assume you've verified the generated waveforms using a logic >> analyzer/scope, and compared >> them to the DRAMs datasheet (?). > > Unfortunately we do not have access to a decent scope nor a logic > analyzer, that would certainly have been helpful. > > >> If you have access to a Windows >> machine, you could try an >> ancient Motorola tool called UPM860. It might be helpful when >> verifying your UPM program. > > Did take a look at that, though it did not appear to be as helpful as I hoped. > > >> Good luck! >> - Frank > > Thanks for your suggestions Frank, They did provide me with some food > for thought. > > What the issue ended up being was us incorrectly setting the amx0/amx1 > bits of the "Exception" RAM word. After we fixed that we also found a > nice document from Micron on DRAM timings which had slightly more > efficient read/write section values than what we came up with, for > those interested here is the link > http://download.micron.com/pdf/technotes/TN4812.pdf . Now RAM burst > reads/writes are finally working properly :) > > Mikhail Zaturenskiy > I'm impressed! You've solved your burst problem working in blind ;-) Next time, consider buying/renting an analyzer/MSO. It's strange you mentioned this certain Micron datasheet. It was the same document that finally made me understand how address multiplexing works on the 8xx. Far easier to understand than the Freescale ref. manual. Now, consider supporting the community by commiting a patch containing the working UPM table for this SDRAM ;-) - Frank ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] Remove deprecated 'autoscr' command/variables
Peter, On Wed, 2009-09-16 at 21:38 -0500, Peter Tyser wrote: > The more standard 'source' command provides identical functionality to > the autoscr command. > > Environment variable names/values on the MVBC_P, MVBML7, kmeter1, > mgcoge, and km8xx boards are updated to no longer refernce 'autoscr'. > > The 'autoscript' and 'autoscript_uname' environment variables are > also removed. > > Signed-off-by: Peter Tyser > --- > Changes since v1: > - Removed all references to autoscript and autoscript_uname, previously > just the autoscr command was removed. > > README |8 > board/LEOX/elpt860/README.LEOX |2 +- > board/matrix_vision/mvbc_p/mvbc_p_autoscript |4 ++-- > board/matrix_vision/mvblm7/mvblm7_autoscript |4 ++-- > board/musenki/README |2 +- > board/pn62/cmd_pn62.c| 18 -- > common/cmd_load.c| 18 -- > common/cmd_net.c | 15 --- > common/cmd_source.c | 18 -- > doc/README.IPHASE4539|2 +- > doc/README.m52277evb |2 +- > doc/README.m5373evb |2 +- > doc/README.m54455evb |2 +- > doc/README.m5475evb |2 +- > doc/feature-removal-schedule.txt | 19 --- > include/configs/MVBC_P.h | 14 +++--- > include/configs/MVBLM7.h | 14 +++--- > include/configs/keymile-common.h |6 +++--- > 18 files changed, 28 insertions(+), 124 deletions(-) looks ok for mvBC-P and mvBL-M7. Acked-by: Andre Schwarz Thanks, André MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner, Hans-Joachim Reich ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] SPARC standalone app fix
Hi Sergey, Thank you for your work. I have updated the sparc repository with your patch. And, yes, you are probably the first one to use the standalone app feature :) Please CC me next time. Thanks, Daniel Сергей Миронов wrote: >Hi! Thanks for the beautiful project! Ive tried to launch standalone >app 'hello_world' on my SPARC leon3 board (ml-402) and found that >application says 'boom' and halts. So here is the patch to solve the >problem. Seems, that i am the first who ever launched Sparc'ish >standalone code :) > > > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Details of fw_env.config file
Dear Rahanesh, In message <4ab30cd8.7020...@tataelxsi.co.in> you wrote: > > I wanted to know the meaning of Device Offset in the config file > (fw_env.config). Please see "tools/env/README". Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de "The whole problem with the world is that fools and fanatics are always so certain of themselves, but wiser people so full of doubts." - Bertrand Russell ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/1] SPARC: fixes exported function stub for standalone applications.
Hello Wolfgang, Please pull the u-boot-sparc.git master branch. This patch fixes the SPARC support for standalone u-boot applications. The problem was that I neve finished the implementation in the first place. jmp ensures we get back to the location we came from, size(void *) make sure we get the function addresses correctly from the table (entry*4 instead of entry*1). SPARC/LEON3 => tftpboot 0x4100 192.168.0.47:hello_world.bin Using GRETH 10/100 device TFTP from server 192.168.0.47; our IP address is 192.168.0.206 Filename 'hello_world.bin'. Load address: 0x4100 Loading: # done Bytes transferred = 1232 (4d0 hex) => go 4108 hej ## Starting application at 0x4108 ... Example expects ABI version 5 Actual U-Boot ABI version 5 Hello World argc = 2 argv[0] = "4108" argv[1] = "hej" argv[2] = "" Hit any key to exit ... ## Application terminated, rc = 0x0 => - Best Regards, Daniel Hellstrom Signed-off-by: Daniel Hellstrom --- examples/standalone/stubs.c |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c index 339bbf9..ce3371d 100644 --- a/examples/standalone/stubs.c +++ b/examples/standalone/stubs.c @@ -181,9 +181,9 @@ gd_t *global_data; " or %%g1, %%g7, %%g1\n" \ " ld [%%g1], %%g1\n" \ " ld [%%g1 + %1], %%g1\n" \ -" call %%g1\n"\ +" jmp %%g1\n" \ " nop\n" \ - : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x) : "g1" ); + : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "g1" ); #else #error stubs definition missing for this architecture -- 1.5.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH][v4] FDT: remove obsolete OF_CPU and OF_SOC macros.
Signed-off-by: Marcel Ziswiler Acked-by: Guennadi Liakhovetski Acked-by: Heiko Schocher --- Changes since v1: - CC all respective board maintainers Changes since v2: - Added Guennadi Liakhovetski's ack Changes since v3: - Added Heiko's ack for IDS8247, mgcoge and muas3001 README|6 -- include/configs/IDS8247.h |2 -- include/configs/MPC8260ADS.h |1 - include/configs/linkstation.h |2 -- include/configs/mgcoge.h |2 -- include/configs/mpc7448hpc2.h |1 - include/configs/muas3001.h|2 -- include/configs/stxxtc.h |1 - 8 files changed, 4 insertions(+), 13 deletions(-) diff --git a/README b/README index ff4ed8b..3cb7786 100644 --- a/README +++ b/README @@ -368,8 +368,10 @@ The following options need to be configured: * Adds the "fdt" command * The bootm command automatically updates the fdt - OF_CPU - The proper name of the cpus node. - OF_SOC - The proper name of the soc node. + OF_CPU - The proper name of the cpus node (only required for + MPC512X and MPC5xxx based boards). + OF_SOC - The proper name of the soc node (only required for + MPC512X and MPC5xxx based boards). OF_TBCLK - The timebase frequency. OF_STDOUT_PATH - The path to the console device diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h index 4c4af05..147a8b2 100644 --- a/include/configs/IDS8247.h +++ b/include/configs/IDS8247.h @@ -125,8 +125,6 @@ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -#define OF_CPU "PowerPC,8...@0" -#define OF_SOC "s...@f000" #define OF_TBCLK (bd->bi_busfreq / 4) #define OF_STDOUT_PATH "/s...@f000/serial8...@e0008000" diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h index 942a4cc..677a143 100644 --- a/include/configs/MPC8260ADS.h +++ b/include/configs/MPC8260ADS.h @@ -209,7 +209,6 @@ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 #if defined(CONFIG_OF_LIBFDT) -#define OF_CPU "c...@0" #define OF_TBCLK (bd->bi_busfreq / 4) #endif diff --git a/include/configs/linkstation.h b/include/configs/linkstation.h index 2feb3ae..16b464c 100644 --- a/include/configs/linkstation.h +++ b/include/configs/linkstation.h @@ -96,8 +96,6 @@ #define CONFIG_OF_LIBFDT 1 -#define OF_CPU "PowerPC,603e" -#define OF_SOC "soc...@8000" #define OF_STDOUT_PATH "/soc10x/ser...@80004600" /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ diff --git a/include/configs/mgcoge.h b/include/configs/mgcoge.h index b955749..55d1fc9 100644 --- a/include/configs/mgcoge.h +++ b/include/configs/mgcoge.h @@ -347,8 +347,6 @@ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -#define OF_CPU "PowerPC,8...@0" -#define OF_SOC "s...@f000" #define OF_TBCLK (bd->bi_busfreq / 4) #define OF_STDOUT_PATH "/soc/cpm/ser...@11a90" diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h index 4f98ba4..be12186 100644 --- a/include/configs/mpc7448hpc2.h +++ b/include/configs/mpc7448hpc2.h @@ -79,7 +79,6 @@ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -#define OF_CPU "PowerPC,7...@0" #define OF_TSI "tsi...@c000" #define OF_TBCLK (bd->bi_busfreq / 8) #define OF_STDOUT_PATH "/tsi...@c000/ser...@7808" diff --git a/include/configs/muas3001.h b/include/configs/muas3001.h index ae033b2..c94daa3 100644 --- a/include/configs/muas3001.h +++ b/include/configs/muas3001.h @@ -405,8 +405,6 @@ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -#define OF_CPU "PowerPC,8...@0" -#define OF_SOC "s...@f000" #define OF_TBCLK (bd->bi_busfreq / 4) #if defined(CONFIG_MUAS_DEV_BOARD) #define OF_STDOUT_PATH "/soc/cpm/ser...@11a90" diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h index d16262b..5854366 100644 --- a/include/configs/stxxtc.h +++ b/include/configs/stxxtc.h @@ -509,7 +509,6 @@ typedef unsigned int led_id_t; /* pass open firmware flattened device tree */ #define CONFIG_OF_LIBFDT 1 -#define OF_CPU "PowerPC,mpc...@0" #define OF_TBCLK (MPC8XX_HZ / 16) #endif /* __CONFIG_H */ -- 1.6.4.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [TESTING PATCH] ppc: Relocation test patch
Peter Tyser wrote on 17/09/2009 19:29:18:
> From:
>
> Peter Tyser
>
> To:
>
> Joakim Tjernlund
>
> Cc:
>
> pieter.voorthuij...@prodrive.nl, u-boot@lists.denx.de, Wolfgang Denk
>
>
> Date:
>
> 17/09/2009 19:29
>
> Subject:
>
> Re: [U-Boot] [TESTING PATCH] ppc: Relocation test patch
>
> On Thu, 2009-09-17 at 09:06 +0200, Joakim Tjernlund wrote:
> > >
> > > When preparing the ppc relocation patches I noticed that the gcc
> > > -mrelocatable compiler flag increases the .reloc section by 3 or 4
> > > Kbytes. I did a compile test, and this increase pushes the ALPR board
> > > back over 256K (it recently had the same size issue, see "ppc4xx: Remove
> > > some features from ALPR to fit into 256k again"). No other boards
> > > appear to break size-wise.
> > >
> > > So I guess I had 2 questions:
> > > 1. Is enabling proper relocation worth the 3/4KB that will be added to
> > > every ppc binary? I personally think so as the manual relocation fixups
> > > that currently litter the code can be removed and true relocation is
> > > much less hokey in the long run. X-ES's U-Boot binaries also are
> > > generally much smaller than their allocated 512KB, so this increase
> > > doesn't affect me much:)
> >
> > You can get some of this space back by just #ifdef:ing out the manual
> > relocation
> > code. Removing it completely is OK by me though.
>
> The original patchset I had planned on submitting completely removed all
> PPC-specific manual relocation fixups, but didn't do anything with the
> references to gd->reloc_off in common files. The thought was that we
> could get other architectures to properly relocate, then get rid of
> gd->reloc_off globally. Otherwise there's going to be a fair number of
> #ifdef CONFIG_RELOC_FIXUP_WORKS littering the code until all arches
> support proper relocation which is a bit ugly.
>
> With all PPC-specific relocation manual fixups removed, the ALPR still
> didn't fit. However, I just removed all relocation fixups in the common
> fpga code as well as added some #ifdef CONFIG_RELOC_FIXUP_WORKS in
> common code, and now the ALPR fits in its designated 256KB. It looks to
> be 1.8KB larger than the original, non-relocatable code.
>
> I'll submit this patch for review shortly. I'm assuming people are OK
> with the 1.8KB image size increase? Perhaps some of Jocke's suggestions
> below can decrease the size as well.
I remembered one thing, the reloc asm has a bug, one should not
relocate NULL values, pasting in an email from me sent to the list
some time ago about this:
On Thu, 2008-12-04 at 13:35 +0100, Jean-Christophe PLAGNIOL-VILLARD
wrote:
> introduce 3 new weak functions board_bdinfo, cpu_bdinfo and soc_bdinfo to
> allow
> board, cpu and soc to print more information
>
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD
> ---
> diff with V3
> rename cpu_bdinfo to soc_bdinfo for soc
>
> Best Regards,
> J.
Since you are starting to use weak function I think you really need to fix the
relocation procedure not to relocate
NULL values too. Othervise you risk running into hard to debug problems,
possibly one should do the same
for __eabi_uconvert(). The function below could be written a bit cleaner though:
void __eabi_convert(unsigned long *low, unsigned long *high,
unsigned long addend)
{
unsigned long len = high - low, val;
for(--low; len; --len) {
val = *++low;
if (!val)
continue;
*low = val + addend;
}
}
void __eabi_uconvert(unsigned long *low, unsigned long *high,
unsigned long addend)
{
unsigned long len = high - low, val, *v2p;
for(--low; len; --len) {
val = *++low;
val += addend;
v2p = (unsigned long *)val;
*low = val;
*v2p += added;
}
}
Pasting part of an earlier mail:
And you need to fix the relocation not to relocate NULL values, see
http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/config/rs6000/eabi.asm?rev=1.13&content-type=text/x-cvsweb-markup
look for __eabi_uconvert.
For fun I once tried to rewrite these functions i C, not tested though:
void __eabi_convert(unsigned long *low, unsigned long *high,
unsigned long addend)
{
unsigned long len = high - low, val;
if (!len)
return;
low--;
do {
val = *++low;
if (!val)
continue;
*low = val + addend;
} while(--len);
}
void __eabi_uconvert(unsigned long *low, unsigned long *high,
unsigned long addend)
{
unsigned long len = high - low, val, val2, *v2p;
if (!len)
return;
low--;
do {
val = *++low;
val += addend;
v2p = (unsigned long *)val;
*low = val;
val2 = *v2p;
val2
Re: [U-Boot] U-Boot load and run via NAND flash - ARM926EJ-S
> -Original Message- > From: u-boot-boun...@lists.denx.de > [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Wolfgang Denk > Sent: Thursday, September 17, 2009 1:14 PM > To: Thomas Jackson > Cc: u-boot@lists.denx.de > Subject: Re: [U-Boot] U-Boot load and run via NAND flash - ARM926EJ-S > > Dear Thomas Jackson, > > In message <25484494.p...@talk.nabble.com> you wrote: > > > > I understand NOR-based flash memory devices have > traditionally been used for > > non-volatile storage for a bootloader and other various > advantages including > > support for execute-in-place code, random access to memory, > and zero error > > rate, etc. However, we have a project that we would like > to have U-Boot > > bootloader run via NAND Flash memory device on a ARM926EJ-S > based board. I > > searched the mailing list for this and didn't see anything. > I only found a > > I have no idea how you performed that search, but it seems you have a > special aptitude to avoid all the obvious hits. > > > question posted in 2006 where it was asked if the kernel > based on ARM926EJ-S > > can boot from NAND flash. Which I know is ok. Does the > community know of > > any existing mechanisms for this type of configuration to > enable U-Boot load > > and run via NAND flash? > > It's a standard feature and available on many (most?) boards that > support booting from NAND. Dunno if this includes AT91 boards. On Kirkwood there is internal BootROM which takes care of this. In this case you need to add some header on the top of u-boot binary Pls go through doc/README.kwbimage On Nomadik platforms there is intermediate binary sits on the very first sector which does DRAM initialization ,some other basic system setup and loads u-boot into DRAM. I am not familiar with AT91, but there must be similar approach. May be new mkimage structure may find useful for you Regards.. Prafulla . . > > Jean-Christophe should be able to answer this, but he is currently > off this planet. > > Best regards, > > Wolfgang Denk > > -- > DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany > Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de > Anyone can count the seeds in an apple. > No one can count the apples in a seed. > ___ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] Remove deprecated 'autoscr' command/variables
Hello Peter, On Wed, 2009-09-16 at 21:38 -0500, Peter Tyser wrote: > The more standard 'source' command provides identical functionality to > the autoscr command. > > Environment variable names/values on the MVBC_P, MVBML7, kmeter1, > mgcoge, and km8xx boards are updated to no longer refernce 'autoscr'. > > The 'autoscript' and 'autoscript_uname' environment variables are > also removed. > > Signed-off-by: Peter Tyser > --- > Changes since v1: > - Removed all references to autoscript and autoscript_uname, previously > just the autoscr command was removed. > > README |8 > board/LEOX/elpt860/README.LEOX |2 +- > board/matrix_vision/mvbc_p/mvbc_p_autoscript |4 ++-- > board/matrix_vision/mvblm7/mvblm7_autoscript |4 ++-- > board/musenki/README |2 +- > board/pn62/cmd_pn62.c| 18 -- > common/cmd_load.c| 18 -- > common/cmd_net.c | 15 --- > common/cmd_source.c | 18 -- > doc/README.IPHASE4539|2 +- > doc/README.m52277evb |2 +- > doc/README.m5373evb |2 +- > doc/README.m54455evb |2 +- > doc/README.m5475evb |2 +- > doc/feature-removal-schedule.txt | 19 --- > include/configs/MVBC_P.h | 14 +++--- > include/configs/MVBLM7.h | 14 +++--- > include/configs/keymile-common.h |6 +++--- > 18 files changed, 28 insertions(+), 124 deletions(-) Thanks. Looks fine for the keymile boards. Acked-by: Heiko Schocher bye Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/1] SPARC: fixes exported function stub for standalone applications. jmp ensures we get back to the location we came from, size(void *) make sure we get the function addresses correct
Hello Wolfgang, This patch fixes the SPARC support for standalone u-boot applications. SPARC/LEON3 => tftpboot 0x4100 192.168.0.47:hello_world.bin Using GRETH 10/100 device TFTP from server 192.168.0.47; our IP address is 192.168.0.206 Filename 'hello_world.bin'. Load address: 0x4100 Loading: # done Bytes transferred = 1232 (4d0 hex) => go 4108 hej ## Starting application at 0x4108 ... Example expects ABI version 5 Actual U-Boot ABI version 5 Hello World argc = 2 argv[0] = "4108" argv[1] = "hej" argv[2] = "" Hit any key to exit ... ## Application terminated, rc = 0x0 => - Best Regards, Daniel Hellstrom Signed-off-by: Daniel Hellstrom --- examples/standalone/stubs.c |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c index 339bbf9..ce3371d 100644 --- a/examples/standalone/stubs.c +++ b/examples/standalone/stubs.c @@ -181,9 +181,9 @@ gd_t *global_data; " or %%g1, %%g7, %%g1\n" \ " ld [%%g1], %%g1\n" \ " ld [%%g1 + %1], %%g1\n" \ -" call %%g1\n"\ +" jmp %%g1\n" \ " nop\n" \ - : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x) : "g1" ); + : : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "g1" ); #else #error stubs definition missing for this architecture -- 1.5.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 1/3] NAND boot: MPC8536DS support
Looks good. Any plans on adding support on 8572 and/or p2020? - k ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] OMAP3, RFBI, splash screen
Hi, all! I'm trying to implement splash screen on OMAP35xx-based device with 128x128 1bpp display connected using RFBI, plain parallel interface. Display has controller and own memory, and is controlled with parallel interface, 8-bit wide data bus and signals. This display works under Linux, but I can't implement that using u-boot, display just doesn't power on, while I see that data is on bus with oscilloscope. Linux version works using interrupts, so I can't do this with u-boot, and that'd be simply overkill using this in u-boot. I think I miss something simple. Have anybody implemented such a thing, I just need to make it into dumb parallel mode, just to display simple image. Any examples, ideas? All the best, S. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [TESTING PATCH] ppc: Relocation test patch
> > On Thu, 2009-09-17 at 09:06 +0200, Joakim Tjernlund wrote:
> > > >
> > > > When preparing the ppc relocation patches I noticed that the gcc
> > > > -mrelocatable compiler flag increases the .reloc section by 3 or 4
> > > > Kbytes. I did a compile test, and this increase pushes the ALPR board
> > > > back over 256K (it recently had the same size issue, see "ppc4xx: Remove
> > > > some features from ALPR to fit into 256k again"). No other boards
> > > > appear to break size-wise.
> > > >
> > > > So I guess I had 2 questions:
> > > > 1. Is enabling proper relocation worth the 3/4KB that will be added to
> > > > every ppc binary? I personally think so as the manual relocation fixups
> > > > that currently litter the code can be removed and true relocation is
> > > > much less hokey in the long run. X-ES's U-Boot binaries also are
> > > > generally much smaller than their allocated 512KB, so this increase
> > > > doesn't affect me much:)
> > >
> > > You can get some of this space back by just #ifdef:ing out the manual
> > > relocation
> > > code. Removing it completely is OK by me though.
> >
> > The original patchset I had planned on submitting completely removed all
> > PPC-specific manual relocation fixups, but didn't do anything with the
> > references to gd->reloc_off in common files. The thought was that we
> > could get other architectures to properly relocate, then get rid of
> > gd->reloc_off globally. Otherwise there's going to be a fair number of
> > #ifdef CONFIG_RELOC_FIXUP_WORKS littering the code until all arches
> > support proper relocation which is a bit ugly.
> >
> > With all PPC-specific relocation manual fixups removed, the ALPR still
> > didn't fit. However, I just removed all relocation fixups in the common
> > fpga code as well as added some #ifdef CONFIG_RELOC_FIXUP_WORKS in
> > common code, and now the ALPR fits in its designated 256KB. It looks to
> > be 1.8KB larger than the original, non-relocatable code.
> >
> > I'll submit this patch for review shortly. I'm assuming people are OK
> > with the 1.8KB image size increase? Perhaps some of Jocke's suggestions
> > below can decrease the size as well.
>
> I remembered one thing, the reloc asm has a bug, one should not
> relocate NULL values, pasting in an email from me sent to the list
> some time ago about this:
Hi Jocke,
Do you have a C snippet that would bring this issue out? I would assume
gcc would not emit relocation fixup information for NULL values.
Variables initialized to NULL should be put in the bss segment, which
just get zeroed out, not relocated. For example, I just tested:
char *reloc_test = NULL;
/* After relocation to RAM */
printf("RAM test_reloc @ %p\n", test_reloc);
Which prints out the correct address:
RAM test_reloc @ (null)
Let me know if I'm missing something.
Best,
Peter
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Re: [U-Boot] [TESTING PATCH] ppc: Relocation test patch
Peter Tyser wrote on 18/09/2009 16:28:35: > > > > > On Thu, 2009-09-17 at 09:06 +0200, Joakim Tjernlund wrote: > > > > > > > > > > When preparing the ppc relocation patches I noticed that the gcc > > > > > -mrelocatable compiler flag increases the .reloc section by 3 or 4 > > > > > Kbytes. I did a compile test, and this increase pushes the ALPR board > > > > > back over 256K (it recently had the same size issue, see "ppc4xx: > > > > > Remove > > > > > some features from ALPR to fit into 256k again"). No other boards > > > > > appear to break size-wise. > > > > > > > > > > So I guess I had 2 questions: > > > > > 1. Is enabling proper relocation worth the 3/4KB that will be added to > > > > > every ppc binary? I personally think so as the manual relocation > > > > > fixups > > > > > that currently litter the code can be removed and true relocation is > > > > > much less hokey in the long run. X-ES's U-Boot binaries also are > > > > > generally much smaller than their allocated 512KB, so this increase > > > > > doesn't affect me much:) > > > > > > > > You can get some of this space back by just #ifdef:ing out the manual > > > > relocation > > > > code. Removing it completely is OK by me though. > > > > > > The original patchset I had planned on submitting completely removed all > > > PPC-specific manual relocation fixups, but didn't do anything with the > > > references to gd->reloc_off in common files. The thought was that we > > > could get other architectures to properly relocate, then get rid of > > > gd->reloc_off globally. Otherwise there's going to be a fair number of > > > #ifdef CONFIG_RELOC_FIXUP_WORKS littering the code until all arches > > > support proper relocation which is a bit ugly. > > > > > > With all PPC-specific relocation manual fixups removed, the ALPR still > > > didn't fit. However, I just removed all relocation fixups in the common > > > fpga code as well as added some #ifdef CONFIG_RELOC_FIXUP_WORKS in > > > common code, and now the ALPR fits in its designated 256KB. It looks to > > > be 1.8KB larger than the original, non-relocatable code. > > > > > > I'll submit this patch for review shortly. I'm assuming people are OK > > > with the 1.8KB image size increase? Perhaps some of Jocke's suggestions > > > below can decrease the size as well. > > > > I remembered one thing, the reloc asm has a bug, one should not > > relocate NULL values, pasting in an email from me sent to the list > > some time ago about this: > > Hi Jocke, > Do you have a C snippet that would bring this issue out? I would assume > gcc would not emit relocation fixup information for NULL values. > Variables initialized to NULL should be put in the bss segment, which > just get zeroed out, not relocated. Sorry, I don't have an example. Just a guess, weak function references: void weak_fun(void) __attribute__ ((weak)); if (weak_fun) weak_fun(); On the other hand it is clear that gcc test for NULL and skips the reloc. It is obvious why, NULL is a absolute value and should stay that way even after relocation. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [TESTING PATCH] ppc: Relocation test patch
On Fri, 2009-09-18 at 16:52 +0200, Joakim Tjernlund wrote: > Peter Tyser wrote on 18/09/2009 16:28:35: > > > > > > > > On Thu, 2009-09-17 at 09:06 +0200, Joakim Tjernlund wrote: > > > > > > > > > > > > When preparing the ppc relocation patches I noticed that the gcc > > > > > > -mrelocatable compiler flag increases the .reloc section by 3 or 4 > > > > > > Kbytes. I did a compile test, and this increase pushes the ALPR > > > > > > board > > > > > > back over 256K (it recently had the same size issue, see "ppc4xx: > > > > > > Remove > > > > > > some features from ALPR to fit into 256k again"). No other boards > > > > > > appear to break size-wise. > > > > > > > > > > > > So I guess I had 2 questions: > > > > > > 1. Is enabling proper relocation worth the 3/4KB that will be added > > > > > > to > > > > > > every ppc binary? I personally think so as the manual relocation > > > > > > fixups > > > > > > that currently litter the code can be removed and true relocation is > > > > > > much less hokey in the long run. X-ES's U-Boot binaries also are > > > > > > generally much smaller than their allocated 512KB, so this increase > > > > > > doesn't affect me much:) > > > > > > > > > > You can get some of this space back by just #ifdef:ing out the manual > > > > > relocation > > > > > code. Removing it completely is OK by me though. > > > > > > > > The original patchset I had planned on submitting completely removed all > > > > PPC-specific manual relocation fixups, but didn't do anything with the > > > > references to gd->reloc_off in common files. The thought was that we > > > > could get other architectures to properly relocate, then get rid of > > > > gd->reloc_off globally. Otherwise there's going to be a fair number of > > > > #ifdef CONFIG_RELOC_FIXUP_WORKS littering the code until all arches > > > > support proper relocation which is a bit ugly. > > > > > > > > With all PPC-specific relocation manual fixups removed, the ALPR still > > > > didn't fit. However, I just removed all relocation fixups in the common > > > > fpga code as well as added some #ifdef CONFIG_RELOC_FIXUP_WORKS in > > > > common code, and now the ALPR fits in its designated 256KB. It looks to > > > > be 1.8KB larger than the original, non-relocatable code. > > > > > > > > I'll submit this patch for review shortly. I'm assuming people are OK > > > > with the 1.8KB image size increase? Perhaps some of Jocke's suggestions > > > > below can decrease the size as well. > > > > > > I remembered one thing, the reloc asm has a bug, one should not > > > relocate NULL values, pasting in an email from me sent to the list > > > some time ago about this: > > > > Hi Jocke, > > Do you have a C snippet that would bring this issue out? I would assume > > gcc would not emit relocation fixup information for NULL values. > > Variables initialized to NULL should be put in the bss segment, which > > just get zeroed out, not relocated. > > Sorry, I don't have an example. Just a guess, weak function references: > > void weak_fun(void) __attribute__ ((weak)); > if (weak_fun) > weak_fun(); Using default weak functions as well as overridden weak functions both definitely work. So the pointers must be being updated correctly. I guess I'm not sure where specifically a problem could arise. Let me know if you have any additional details. I'm hoping to send the patches out later today, maybe some review/testing will make things clearer. Best, Peter ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [TESTING PATCH] ppc: Relocation test patch
Peter Tyser wrote on 18/09/2009 17:21:57:
> >
> > Sorry, I don't have an example. Just a guess, weak function references:
> >
> > void weak_fun(void) __attribute__ ((weak));
> > if (weak_fun)
> >weak_fun();
>
> Using default weak functions as well as overridden weak functions both
> definitely work. So the pointers must be being updated correctly. I
> guess I'm not sure where specifically a problem could arise. Let me
> know if you have any additional details. I'm hoping to send the patches
> out later today, maybe some review/testing will make things clearer.
This does not work:
void weak_fun(void) __attribute__ ((weak));
printf("weak_fun:%p\n", weak_fun);
prints "weak 17f9c000" after relocation
for me, should be NULL when weak_fun is undefined.
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[U-Boot] [PATCH v2 1/3] ppc/85xx: Simplify the top makefile for 36-bit config for MPC8572DS
Signed-off-by: Kumar Gala --- * Updated for new -t option Makefile|7 +-- include/configs/MPC8572DS.h |4 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/Makefile b/Makefile index 99837a3..8672336 100644 --- a/Makefile +++ b/Makefile @@ -2514,12 +2514,7 @@ MPC8569MDS_config: unconfig MPC8572DS_36BIT_config \ MPC8572DS_config: unconfig - @mkdir -p $(obj)include - @if [ "$(findstring _36BIT_,$@)" ] ; then \ - echo "#define CONFIG_PHYS_64BIT" >>$(obj)include/config.h ; \ - $(XECHO) "... enabling 36-bit physical addressing." ; \ - fi - @$(MKCONFIG) -a MPC8572DS ppc mpc85xx mpc8572ds freescale + @$(MKCONFIG) -t $(@:_config=) MPC8572DS ppc mpc85xx mpc8572ds freescale P2020DS_36BIT_config \ P2020DS_config:unconfig diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 55c1f29..000f8f6 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -27,6 +27,10 @@ #ifndef __CONFIG_H #define __CONFIG_H +#ifdef CONFIG_MK_36BIT +#define CONFIG_PHYS_64BIT +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E5001 /* BOOKE e500 family */ -- 1.6.0.6 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 2/3] ppc/85xx: Simplify the top makefile for 36-bit config for P2020DS
Signed-off-by: Kumar Gala --- * Updated for new -t option Makefile |7 +-- include/configs/P2020DS.h |4 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/Makefile b/Makefile index 8672336..1e25669 100644 --- a/Makefile +++ b/Makefile @@ -2518,12 +2518,7 @@ MPC8572DS_config: unconfig P2020DS_36BIT_config \ P2020DS_config:unconfig - @mkdir -p $(obj)include - @if [ "$(findstring _36BIT_,$@)" ] ; then \ - echo "#define CONFIG_PHYS_64BIT" >>$(obj)include/config.h ; \ - $(XECHO) "... enabling 36-bit physical addressing." ; \ - fi - @$(MKCONFIG) -a P2020DS ppc mpc85xx p2020ds freescale + @$(MKCONFIG) -t $(@:_config=) P2020DS ppc mpc85xx p2020ds freescale P1011RDB_config: unconfig @mkdir -p $(obj)include diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index 2a2b9ac..b48c199 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -27,6 +27,10 @@ #ifndef __CONFIG_H #define __CONFIG_H +#ifdef CONFIG_MK_36BIT +#define CONFIG_PHYS_64BIT +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E5001 /* BOOKE e500 family */ -- 1.6.0.6 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 3/3] ppc/85xx: Simplify the top makefile for P1_P2_RDB boards
Signed-off-by: Kumar Gala --- * Updated for new -t option Makefile| 22 -- include/configs/P1_P2_RDB.h | 13 + 2 files changed, 17 insertions(+), 18 deletions(-) diff --git a/Makefile b/Makefile index 1e25669..d8daa89 100644 --- a/Makefile +++ b/Makefile @@ -2520,25 +2520,11 @@ P2020DS_36BIT_config \ P2020DS_config:unconfig @$(MKCONFIG) -t $(@:_config=) P2020DS ppc mpc85xx p2020ds freescale -P1011RDB_config: unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_P1011" >>$(obj)include/config.h ; - @$(MKCONFIG) -a P1_P2_RDB ppc mpc85xx p1_p2_rdb freescale - -P1020RDB_config: unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_P1020" >>$(obj)include/config.h ; - @$(MKCONFIG) -a P1_P2_RDB ppc mpc85xx p1_p2_rdb freescale - -P2010RDB_config: unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_P2010" >>$(obj)include/config.h ; - @$(MKCONFIG) -a P1_P2_RDB ppc mpc85xx p1_p2_rdb freescale - +P1011RDB_config\ +P1020RDB_config\ +P2010RDB_config \ P2020RDB_config: unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_P2020" >>$(obj)include/config.h ; - @$(MKCONFIG) -a P1_P2_RDB ppc mpc85xx p1_p2_rdb freescale + @$(MKCONFIG) -t $(@:_config=) P1_P2_RDB ppc mpc85xx p1_p2_rdb freescale PM854_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx pm854 diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 6d44d6c..8e97ad0 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -30,6 +30,19 @@ #ifndef __CONFIG_H #define __CONFIG_H +#ifdef CONFIG_MK_P1011RDB +#define CONFIG_P1011 +#endif +#ifdef CONFIG_MK_P1020RDB +#define CONFIG_P1020 +#endif +#ifdef CONFIG_MK_P2010RDB +#define CONFIG_P2010 +#endif +#ifdef CONFIG_MK_P2020RDB +#define CONFIG_P2020 +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E5001 /* BOOKE e500 family */ -- 1.6.0.6 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] OMAP3, RFBI, splash screen
Sergey Lapin wrote: > Hi, all! > > I'm trying to implement splash screen on OMAP35xx-based device > with 128x128 1bpp display connected using RFBI, plain parallel interface. > Display has controller and own memory, and is controlled with parallel > interface, 8-bit wide data bus and signals. > > This display works under Linux, but I can't implement > that using u-boot, display just doesn't power on, while I see > that data is on bus with oscilloscope. Linux version works > using interrupts, so I can't do this with u-boot, and that'd be simply > overkill using this in u-boot. I think I miss something simple. > > Have anybody implemented such a thing, I just need to make > it into dumb parallel mode, just to display simple image. > Any examples, ideas? Most probably it won't help you, as it seems you have some HW configuration issues. But for OMAP3 splash screen example see http://groups.google.com/group/beagleboard/browse_thread/thread/3ad9b803a3418624 Best regards Dirk ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [TESTING PATCH] ppc: Relocation test patch
> > > Sorry, I don't have an example. Just a guess, weak function references:
> > >
> > > void weak_fun(void) __attribute__ ((weak));
> > > if (weak_fun)
> > >weak_fun();
> >
> > Using default weak functions as well as overridden weak functions both
> > definitely work. So the pointers must be being updated correctly. I
> > guess I'm not sure where specifically a problem could arise. Let me
> > know if you have any additional details. I'm hoping to send the patches
> > out later today, maybe some review/testing will make things clearer.
>
> This does not work:
>
> void weak_fun(void) __attribute__ ((weak));
> printf("weak_fun:%p\n", weak_fun);
>
> prints "weak 17f9c000" after relocation
> for me, should be NULL when weak_fun is undefined.
Ahh, I see. I see the same thing. In general U-Boot declares weak
functions by either using the 'alias' attribute:
static int __def_eth_init(bd_t *bis)
{
return -1;
}
int cpu_eth_init(bd_t *bis) __attribute__((weak, alias("__def_eth_init")));
or by declaring a function as weak:
void __attribute__((weak)) _machine_restart(void)
{
}
Both these scenarios work with the current relocation fixup scheme.
What is a real world scenario (such as your example) when someone would
declare a weak function, but not actually implement a default. Doesn't
that defeat the purpose of having a weak function in the first place?
Eg why would someone use your example of:
void weak_fun(void) __attribute__ ((weak));
...
if (weak_fun)
weak_fun();
...
over:
void weak_fun(void) __attribute__ ((weak))
{
};
...
weak_fun();
...
(or the alias implementation)
I'm trying to grasp the limitations of the current relocation mechanism
as I'm afraid I don't have time to dig through all PPC architectures'
start.S files to fix their relocation code right now:)
Thanks,
Peter
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Re: [U-Boot] [PATCH v3 1/3] NAND boot: MPC8536DS support
On Fri, Sep 18, 2009 at 11:35:33AM +0800, Mingkai Hu wrote:
> diff --git a/Makefile b/Makefile
> index 99837a3..4d18a9f 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -2446,6 +2446,7 @@ vme8349_config: unconfig
> ATUM8548_config: unconfig
> @$(MKCONFIG) $(@:_config=) ppc mpc85xx atum8548
>
> +MPC8536DS_NAND_config \
> MPC8536DS_36BIT_config \
> MPC8536DS_config: unconfig
NAND and 36BIT are orthogonal.
How about changing it to:
# Options: NAND, 36BIT
MPC8536DS_%_config MPC8536DS_config: unconfig
> +#if defined(CONFIG_NAND_BR_PRELIM) \
> + && defined(CONFIG_NAND_OR_PRELIM)
> + out_be32(&lbc->br0, CONFIG_NAND_BR_PRELIM);
> + out_be32(&lbc->or0, CONFIG_NAND_OR_PRELIM);
> + /* for FPGA */
> + out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM);
> + out_be32(&lbc->or3, CONFIG_SYS_OR3_PRELIM);
Those last two lines should probably be #ifdef CONFIG_SYS_BR3_PRELIM.
> +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
> + ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
> + uint l2srbar;
> + int i;
> +
> + l2srbar = CONFIG_SYS_INIT_L2_ADDR;
> + out_be32(&l2cache->l2srbar0, l2srbar);
> +
> + /* set MBECCDIS=1, SBECCDIS=1 */
> + out_be32(&l2cache->l2errdis,
> + (MPC85xx_L2ERRDIS_MBECC |
> + MPC85xx_L2ERRDIS_SBECC));
> +
> + /* set L2E=1 & L2SRAM=001 */
> + out_be32(&l2cache->l2ctl,
> + (MPC85xx_L2CTL_L2E |
> + MPC85xx_L2CTL_L2SRAM_ENTIRE));
> +
> + /* Initialize L2 SRAM to zero */
> + for (i = 0; i < CONFIG_SYS_L2_SIZE; i++)
> + ((char *)l2srbar)[i] = 0;
"uint" is not a valid type for either virtual or physical addresses.
Use a pointer (or uintptr_t if you must) for the former, and phys_addr_t for
the latter.
You're using it as char *, so why not just declare it that way?
> +void board_init_f(ulong bootflag)
> +{
> + u8 sysclk_ratio;
You're not saving any space over plain int/uint...
> + uint plat_ratio, bus_clk, sys_clk;
> + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> +
> + /* initialize selected port with appropriate baud rate */
> + sysclk_ratio = *((volatile unsigned char *)(PIXIS_BASE + PIXIS_SPD));
> + sysclk_ratio &= 0x7;
> + switch (sysclk_ratio) {
> + case 0:
> + sys_clk = 3000;
> + break;
> + case 1:
> + sys_clk = 3600;
> + break;
> + case 2:
> + sys_clk = 4500;
> + break;
> + case 3:
> + sys_clk = 6000;
> + break;
> + case 4:
> + sys_clk = 83332500;
> + break;
> + case 5:
> + sys_clk = 9000;
> + break;
> + case 6:
> + sys_clk = 12000;
> + break;
> + case 7:
> + sys_clk = 15000;
> + break;
> + default:
> + sys_clk = 0;
This default: case is impossible to reach.
> + break;
> + }
We could save some space by putting this in a table.
> + plat_ratio = (gur->porpllsr) & 0x003e;
Unnecessary parens.
> + plat_ratio >>= 1;
plat_ratio /= 2 is more readable and should generate identical code.
-Scott
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Re: [U-Boot] [TESTING PATCH] ppc: Relocation test patch
Peter Tyser wrote on 18/09/2009 18:24:48:
>
>
> > > > Sorry, I don't have an example. Just a guess, weak function references:
> > > >
> > > > void weak_fun(void) __attribute__ ((weak));
> > > > if (weak_fun)
> > > >weak_fun();
> > >
> > > Using default weak functions as well as overridden weak functions both
> > > definitely work. So the pointers must be being updated correctly. I
> > > guess I'm not sure where specifically a problem could arise. Let me
> > > know if you have any additional details. I'm hoping to send the patches
> > > out later today, maybe some review/testing will make things clearer.
> >
> > This does not work:
> >
> > void weak_fun(void) __attribute__ ((weak));
> > printf("weak_fun:%p\n", weak_fun);
> >
> > prints "weak 17f9c000" after relocation
> > for me, should be NULL when weak_fun is undefined.
>
> Ahh, I see. I see the same thing. In general U-Boot declares weak
> functions by either using the 'alias' attribute:
>
> static int __def_eth_init(bd_t *bis)
> {
>return -1;
> }
> int cpu_eth_init(bd_t *bis) __attribute__((weak, alias("__def_eth_init")));
>
> or by declaring a function as weak:
>
> void __attribute__((weak)) _machine_restart(void)
> {
> }
>
> Both these scenarios work with the current relocation fixup scheme.
> What is a real world scenario (such as your example) when someone would
> declare a weak function, but not actually implement a default. Doesn't
> that defeat the purpose of having a weak function in the first place?
> Eg why would someone use your example of:
>
> void weak_fun(void) __attribute__ ((weak));
> ...
>if (weak_fun)
> weak_fun();
> ...
>
> over:
>
> void weak_fun(void) __attribute__ ((weak))
> {
> };
> ...
>weak_fun();
> ...
> (or the alias implementation)
Instead of defining empty board function you could have in generic code
if (board_init_whatever)
board_init_whatever()
>
> I'm trying to grasp the limitations of the current relocation mechanism
> as I'm afraid I don't have time to dig through all PPC architectures'
> start.S files to fix their relocation code right now:)
Sure, I am not saying that you need to do this to make current u-boot
work. I am just saying that the reloc funs are not complete and will
bug if someone in the future wants to use weak functions( or something else
that needs the same) in the above manner, it won't work. So these should be
fixed at
some point but it should be a separate patch as it has nothing to do with your
reloc patch,
it is broken as is even without your patch. I just mentioned it because I
remembered it now
that you were working on relocation in general. I also think the relocation
funs should be
in C ( as I posted ) as this is much easier to understand. Instead of just
fixing all
the reloc assembler one should replace these with calls to generic C code.
If you want to work on making u-boot fully relocatable, I have some hints for
you.
Jocke
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Re: [U-Boot] Hanging in kmalloc of nand_scan_tail() function
On Fri, Sep 18, 2009 at 01:17:48PM +0900, J.Hwan.Kim wrote:
> Hi, everyone
>
> I'm using U-boot 2009-03.
> U-boot hangs in nand_init() function.
> I found the routine kmalloc in nand_scan_tail() cause U-boot reset.
>
>
> int nand_scan_tail(struct mtd_info *mtd)
> {
> int i;
> struct nand_chip *chip = mtd->priv;
>
> if (!(chip->options & NAND_OWN_BUFFERS)) {
> chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
> }
>
> if (!chip->buffers)
> return -ENOMEM;
>
>
>
> U-boot displays message as follows :
>
> NAND: data abort
> pc : [<31f902b4>]\0x09 lr : [<31fa084c>]
> sp : 31f5bee0 ip : 0076\0x09 fp :
> r10: 1188 r9 : 0002\0x09 r8 : 31f5bfdc
> r7 : 0001 r6 : \0x09 r5 : 31fa42b8 r4 : 31fa4364
> r3 : 31fa052c r2 : 0064\0x09 r1 : 0063 r0 :
> Flags: NzCv IRQs off FIQs off Mode SVC_32
> Resetting CPU ...
>
>
> Where the malloc function is defined?
> Why the kmalloc() hangs the u-boot?
> Is there any configuation definition needed?
What specific source lines do 0x31f902b4 and 0x31fa0840 correspond to,
and can you disassemble the former?
-Scott
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Re: [U-Boot] OMAP3, RFBI, splash screen
Try2: to list.. On Fri, Sep 18, 2009 at 11:08 AM, Dirk Behme wrote: > > Sergey Lapin wrote: > > Hi, all! > > > > I'm trying to implement splash screen on OMAP35xx-based device > > with 128x128 1bpp display connected using RFBI, plain parallel interface. > > Display has controller and own memory, and is controlled with parallel > > interface, 8-bit wide data bus and signals. > > > > This display works under Linux, but I can't implement > > that using u-boot, display just doesn't power on, while I see > > that data is on bus with oscilloscope. Linux version works > > using interrupts, so I can't do this with u-boot, and that'd be simply > > overkill using this in u-boot. I think I miss something simple. > > > > Have anybody implemented such a thing, I just need to make > > it into dumb parallel mode, just to display simple image. > > Any examples, ideas? > > Most probably it won't help you, as it seems you have some HW > configuration issues. But for OMAP3 splash screen example see > > http://groups.google.com/group/beagleboard/browse_thread/thread/3ad9b803a3418624 Just FYI -> RFBI is pretty easy to configure up.. I dont recollect seeing (Display Sub System) DSS support in mainline u-boot though.. Usually for RFBI display, there is a few configuration sequences you need to do using RFBI CMD reg and is very display specific, followed by filling up the screen with the data you need -> also note for backlight, based on the board, you may need to look at the schematics for required gpio line to toggle to the right position.. you can usually reverse engineer it from the corresponding linux driver for the same.. if you have it.. also ensure you have the pin mux done correctly.. Regards, Nishanth Menon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 1/3] NAND boot: MPC8536DS support
On Sep 17, 2009, at 10:35 PM, Mingkai Hu wrote: > nand_spl/board/freescale/mpc8536ds/u-boot.lds | 67 + Can we move this to some common location? cpu/mpc85xx/u- boot_nand_spl.lds? - k ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 1/3] NAND boot: MPC8536DS support
On Sep 17, 2009, at 10:35 PM, Mingkai Hu wrote:
> diff --git a/cpu/mpc85xx/cpu_init_nand.c b/cpu/mpc85xx/cpu_init_nand.c
> new file mode 100644
> index 000..e62f8d3
> --- /dev/null
> +++ b/cpu/mpc85xx/cpu_init_nand.c
> @@ -0,0 +1,69 @@
> +/*
> + * Copyright 2009 Freescale Semiconductor, Inc.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include
> +#include
> +
> +void cpu_init_f(void)
> +{
> + ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
> +
> + /*
> + * LCRR - Clock Ratio Register - set up local bus timing
> + * when needed
> + */
> + out_be32(&lbc->lcrr, LCRR_DBYP | LCRR_CLKDIV_8);
> +
> +#if defined(CONFIG_NAND_BR_PRELIM) \
> + && defined(CONFIG_NAND_OR_PRELIM)
> + out_be32(&lbc->br0, CONFIG_NAND_BR_PRELIM);
> + out_be32(&lbc->or0, CONFIG_NAND_OR_PRELIM);
> + /* for FPGA */
> + out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM);
> + out_be32(&lbc->or3, CONFIG_SYS_OR3_PRELIM);
> +#else
> +#error CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must be defined
> +#endif
> +
Should we not have br/or1, br/or2, etc?
- k
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Re: [U-Boot] [PATCH v2] MIPS: VCT: Remove read_spareram reference
On Sat, Sep 12, 2009 at 06:01:40PM +0900, Shinya Kuribayashi wrote: > The commit ecad289fc6bd9d89ef4d5093cc7b6fd712fd0d29 (OneNAND: Remove > unused read_spareram and add unlock_all as kernel does) forgot to remove > a local reference to read_spareram in board/micronas/vct/ebi_onenand.c, > which causes the following build failure when configured with OneNAND: > > ebi_onenand.c: In function 'onenand_board_init': > ebi_onenand.c:196: error: 'struct onenand_chip' has no member named > 'read_spareram' > make[1]: *** [ebi_onenand.o] Error 1 > make[1]: *** Waiting for unfinished jobs > make: *** [board/micronas/vct/libvct.a] Error 2 > > Signed-off-by: Shinya Kuribayashi > Acked-by: Stefan Roese > Cc: Kyungmin Park Applied to u-boot-nand-flash. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] mpc512x. Micron nand flash needs a reset before a read command is issued
On Wed, Sep 16, 2009 at 02:26:53PM +1000, Paul Gibson wrote: > Micron nand flash needs a reset before a read command is issued. > The current mpc5121_nfc driver ignores the reset command. > > Signed-off-by: Paul Gibson > > --- > drivers/mtd/nand/mpc5121_nfc.c |1 + > 1 files changed, 1 insertions(+), 0 deletions(-) > > diff --git a/drivers/mtd/nand/mpc5121_nfc.c b/drivers/mtd/nand/mpc5121_nfc.c > index 856cb36..7fd8a35 100644 > --- a/drivers/mtd/nand/mpc5121_nfc.c > +++ b/drivers/mtd/nand/mpc5121_nfc.c > @@ -334,6 +334,7 @@ static void mpc5121_nfc_command(struct mtd_info > *mtd, unsigned command, Applied to u-boot-nand-flash, but in the future please get your mail client to not wrap lines as above. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ppc/85xx: simplify the top makefile for 36-bit config for mpc8536ds
On Sep 17, 2009, at 10:45 PM, Mingkai Hu wrote: > Signed-off-by: Mingkai Hu > --- > > Sorry for the spam, ingnor the [PATCH] mpc8536: simplify the top > makefile for 36-bit config, > this is the new version. > > Makefile|4 +--- > include/configs/MPC8536DS.h |2 +- > 2 files changed, 2 insertions(+), 4 deletions(-) applied to 85xx - k ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] [OneNAND IPL] OneNAND board init support
On Sat, Aug 29, 2009 at 01:00:59PM +0900, Kyungmin Park wrote:
> #define READ_INTERRUPT()\
> - onenand_readw(THIS_ONENAND(ONENAND_REG_INTERRUPT))
> + onenand_readw(ONENAND_REG_INTERRUPT)
You could get rid of the newline now...
> +enum {
> + ONENAND_USE_DEFAULT,
> + ONENAND_USE_GENERIC,
> +};
What is this? Add a comment, and possibly more specific names.
> +extern int (*onenand_read_page)(ulong block, ulong page,
> + u_char *buf, int pagesize);
Maybe use a weak function instead? Or an #ifdef
CONFIG_SYS_ONENAND_BOARD_READ_PAGE that will keep the code for the
generic version from being in the image (it'd be nice if we could
optimize out replaced weak functions). It seems especially odd that you
use one method for init and another for read page.
> /* read a page with ECC */
> -static inline int onenand_read_page(ulong block, ulong page,
> +static int generic_onenand_read_page(ulong block, ulong page,
> u_char * buf, int pagesize)
Is the "generic" code really generic, or is it just one specific
controller?
> +#ifdef CONFIG_ONENAND_BOARD_INIT
This should probably be CONFIG_SYS_ONENAND_BOARD_INIT -- it's not
tweakable by the end user.
How is this different from the existing CONFIG_USE_ONENAND_BOARD_INIT?
> + onenand_board_init(&page_is_4KiB, &page);
> +#else
> + onenand_generic_init(&page_is_4KiB, &page);
> +#endif
>
> - if (onenand_readw(ONENAND_REG_TECHNOLOGY)) {
> - pagesize = 4096; /* MLC OneNAND has 4KiB pagesize */
> + if (page_is_4KiB) {
> + pagesize = 4096; /* OneNAND has 4KiB pagesize */
> erase_shift = 18;
> - } else {
> - pagesize = 2048;
> - erase_shift = 17;
> }
I don't understand why you move the pagesize/erase_shift init before
onenand_board_init, suggesting that the init code change it if it needs
changing -- but then leave the page_is_4KiB stuff in the generic code.
This should probably just be filled in by the init code without anything
here.
-Scott
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Re: [U-Boot] [PATCH] [OneNAND] Board can override OneNAND IPL image
On Wed, Sep 02, 2009 at 06:05:03PM +0900, Kyungmin Park wrote: > Some board use more then 2KiB OneNAND IPL. > E.G., S5PC100 loads 16KiB OneNAND IPL Why do we need a different image name based on how large the loader is? -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/7] ppc/p4080: CoreNet platfrom style CCSRBAR setting
On CoreNet based platforms the CCSRBAR address is split between an high & low register and we no longer shift the address. Signed-off-by: Kumar Gala Signed-off-by: Scott Wood --- cpu/mpc85xx/cpu_init_early.c | 27 +++ 1 files changed, 27 insertions(+), 0 deletions(-) diff --git a/cpu/mpc85xx/cpu_init_early.c b/cpu/mpc85xx/cpu_init_early.c index 7886f86..bb31709 100644 --- a/cpu/mpc85xx/cpu_init_early.c +++ b/cpu/mpc85xx/cpu_init_early.c @@ -54,6 +54,9 @@ void cpu_init_early_f(void) u32 temp; volatile u32 *ccsr_virt = (volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000); +#ifdef CONFIG_FSL_CORENET + volatile ccsr_local_t *ccm; +#endif mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(1); /* mas1 is the same as above */ @@ -64,9 +67,33 @@ void cpu_init_early_f(void) write_tlb(mas0, mas1, mas2, mas3, mas7); +#ifdef CONFIG_FSL_CORENET + /* +* We can't call set_law() because we haven't moved +* CCSR yet. +*/ + ccm = (void *)ccsr_virt; + + out_be32(&ccm->lawbarh0, (u64)CONFIG_SYS_CCSRBAR_PHYS >> 32); + out_be32(&ccm->lawbarl0, (u32)CONFIG_SYS_CCSRBAR_PHYS); + out_be32(&ccm->lawar0, LAWAR_EN | (0x1e << 20) | LAW_SIZE_4K); + + in_be32((u32 *)(ccsr_virt + 0)); + in_be32((u32 *)(ccsr_virt + 1)); + isync(); + + ccm = (void *)CONFIG_SYS_CCSRBAR; + /* Now use the temporary LAW to move CCSR */ + out_be32(&ccm->ccsrbarh, (u64)CONFIG_SYS_CCSRBAR_PHYS >> 32); + out_be32(&ccm->ccsrbarl, (u32)CONFIG_SYS_CCSRBAR_PHYS); + out_be32(&ccm->ccsrar, CCSRAR_C); + temp = in_be32(&ccm->ccsrar); + disable_law(0); +#else temp = in_be32(ccsr_virt); out_be32(ccsr_virt, CONFIG_SYS_CCSRBAR_PHYS >> 12); temp = in_be32((volatile u32 *)CONFIG_SYS_CCSRBAR); +#endif } #endif -- 1.6.0.6 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/7] ppc/p4080: Add p4080 platform immap definitions
The p4080 SoC has a significant amount of commonality with the 85xx/PQ3
platform. We reuse the 85xx immap and just add new definitions for
local access and global utils. The global utils is now broken into
global utils, clocking and run control/power management.
The offsets from CCSR for a number of blocks have also changed. We
introduce the CONFIG_FSL_CORENET define to distinquish the PQ3 style of
platform from the new p4080 platform. We don't use QoirQ as there are
products (like p2020) that are PQ3 based platforms but have the QoirQ
name.
Signed-off-by: Kumar Gala
---
include/asm-ppc/fsl_lbc.h|4 +
include/asm-ppc/immap_85xx.h | 408 +++--
2 files changed, 392 insertions(+), 20 deletions(-)
diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h
index 08d31e1..5723de6 100644
--- a/include/asm-ppc/fsl_lbc.h
+++ b/include/asm-ppc/fsl_lbc.h
@@ -317,6 +317,10 @@
#define LCRR_CLKDIV_2 0x0002
#define LCRR_CLKDIV_4 0x0004
#define LCRR_CLKDIV_8 0x0008
+#elif defined(CONFIG_FSL_CORENET)
+#define LCRR_CLKDIV_8 0x0002
+#define LCRR_CLKDIV_16 0x0004
+#define LCRR_CLKDIV_32 0x0008
#else
#define LCRR_CLKDIV_4 0x0002
#define LCRR_CLKDIV_8 0x0004
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index e7d412d..cfcfa5d 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -16,6 +16,150 @@
#include
#include
+typedef struct ccsr_local {
+ u32 ccsrbarh; /* 0x0 - Control Configuration Status Registers
Base Address Register High */
+ u32 ccsrbarl; /* 0x4 - Control Configuration Status Registers
Base Address Register Low */
+ u32 ccsrar; /* 0x8 - Configuration, Control, and Status
Attribute Register */
+#define CCSRAR_C 0x8000 /* Commit */
+ u8 res1[4];
+ u32 altcbarh; /* 0x10 - Alternate Configuration Base Address
Register High */
+ u32 altcbarl; /* 0x14 - Alternate Configuration Base Address
Register Low */
+ u32 altcar; /* 0x18 - Alternate Configuration Attribute
Register */
+ u8 res2[4];
+ u32 bstrh; /* 0x20 - Boot space translation register high
*/
+ u32 bstrl; /* 0x24 - Boot space translation register Low */
+ u32 bstrar; /* 0x28 - Boot space translation attributes
register */
+ u8 res3[0xbd4];
+ u32 lawbarh0; /* 0xc00 - LAW0 base address register high */
+ u32 lawbarl0; /* 0xc04 - LAW0 base address register low */
+ u32 lawar0; /* 0xc08 - LAW0 attributes register */
+ u8 res4[4];
+ u32 lawbarh1; /* 0xc10 - LAW1 base address register high */
+ u32 lawbarl1; /* 0xc14 - LAW1 base address register low */
+ u32 lawar1; /* 0xc18 - LAW1 attributes register */
+ u8 res5[4];
+ u32 lawbarh2; /* 0xc20 - LAW2 base address register high */
+ u32 lawbarl2; /* 0xc24 - LAW2 base address register low */
+ u32 lawar2; /* 0xc28 - LAW2 attributes register */
+ u8 res6[4];
+ u32 lawbarh3; /* 0xc30 - LAW3 base address register high */
+ u32 lawbarl3; /* 0xc34 - LAW3 base address register low */
+ u32 lawar3; /* 0xc38 - LAW3 attributes register */
+ u8 res7[4];
+ u32 lawbarh4; /* 0xc40 - LAW4 base address register high */
+ u32 lawbarl4; /* 0xc44 - LAW4 base address register low */
+ u32 lawar4; /* 0xc48 - LAW4 attributes register */
+ u8 res8[4];
+ u32 lawbarh5; /* 0xc50 - LAW5 base address register high */
+ u32 lawbarl5; /* 0xc54 - LAW5 base address register low */
+ u32 lawar5; /* 0xc58 - LAW5 attributes register */
+ u8 res9[4];
+ u32 lawbarh6; /* 0xc60 - LAW6 base address register high */
+ u32 lawbarl6; /* 0xc64 - LAW6 base address register low */
+ u32 lawar6; /* 0xc68 - LAW6 attributes register */
+ u8 res10[4];
+ u32 lawbarh7; /* 0xc70 - LAW7 base address register high */
+ u32 lawbarl7; /* 0xc74 - LAW7 base address register low */
+ u32 lawar7; /* 0xc78 - LAW7 attributes register */
+ u8 res11[4];
+ u32 lawbarh8; /* 0xc80 - LAW8 base address register high */
+ u32 lawbarl8; /* 0xc84 - LAW8 base address register low */
+ u32 lawar8; /* 0xc88 - LAW8 attributes register */
+ u8 res12[4];
+ u32 lawbarh9; /* 0xc90 - LAW9 base address register high */
+ u32 lawbarl9; /* 0x
[U-Boot] [PATCH 4/7] ppc/p4080: CoreNet platfrom style secondary core release
The CoreNet platform style of bringing secondary cores out of reset is
a bit different that the PQ3 style. Mostly the registers that we use
to setup boot translation, enable time bases, and boot release the cores
have moved around.
Signed-off-by: Kumar Gala
---
cpu/mpc85xx/mp.c | 68 +-
1 files changed, 67 insertions(+), 1 deletions(-)
diff --git a/cpu/mpc85xx/mp.c b/cpu/mpc85xx/mp.c
index fa65bed..b474218 100644
--- a/cpu/mpc85xx/mp.c
+++ b/cpu/mpc85xx/mp.c
@@ -26,6 +26,7 @@
#include
#include
#include
+#include
#include "mp.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -135,6 +136,66 @@ ulong get_spin_addr(void)
return addr;
}
+#ifdef CONFIG_FSL_CORENET
+static void corenet_mp_up(unsigned long bootpg)
+{
+ u32 up, cpu_up_mask, whoami;
+ u32 *table = (u32 *)get_spin_addr();
+ volatile ccsr_gur_t *gur;
+ volatile ccsr_local_t *ccm;
+ volatile ccsr_rcpm_t *rcpm;
+ volatile ccsr_pic_t *pic;
+ int timeout = 10;
+ u32 nr_cpus;
+ struct law_entry e;
+
+ gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
+ rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
+ pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
+
+ nr_cpus = ((in_be32(&pic->frr) >> 8) & 0xff) + 1;
+
+ whoami = in_be32(&pic->whoami);
+ cpu_up_mask = 1 << whoami;
+ out_be32(&ccm->bstrl, bootpg);
+
+ e = find_law(bootpg);
+ out_be32(&ccm->bstrar, LAWAR_EN | e.trgt_id << 20 | LAWAR_SIZE_4K);
+
+ /* disable time base at the platform */
+ out_be32(&rcpm->ctbenrl, cpu_up_mask);
+
+ /* release the hounds */
+ up = ((1 << nr_cpus) - 1);
+ out_be32(&gur->brrl, up);
+
+ /* wait for everyone */
+ while (timeout) {
+ int i;
+ for (i = 0; i < nr_cpus; i++) {
+ if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
+ cpu_up_mask |= (1 << i);
+ };
+
+ if ((cpu_up_mask & up) == up)
+ break;
+
+ udelay(100);
+ timeout--;
+ }
+
+ if (timeout == 0)
+ printf("CPU up timeout. CPU up mask is %x should be %x\n",
+ cpu_up_mask, up);
+
+ /* enable time base at the platform */
+ out_be32(&rcpm->ctbenrl, 0);
+ mtspr(SPRN_TBWU, 0);
+ mtspr(SPRN_TBWL, 0);
+ out_be32(&rcpm->ctbenrl, (1 << nr_cpus) - 1);
+}
+#else
static void pq3_mp_up(unsigned long bootpg)
{
u32 up, cpu_up_mask, whoami;
@@ -196,6 +257,7 @@ static void pq3_mp_up(unsigned long bootpg)
devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1);
out_be32(&gur->devdisr, devdisr);
}
+#endif
void cpu_mp_lmb_reserve(struct lmb *lmb)
{
@@ -217,7 +279,7 @@ void setup_mp(void)
if (i != -1) {
/* map reset page to bootpg so we can copy code there */
disable_tlb(i);
-
+
set_tlb(1, 0xf000, bootpg, /* tlb, epn, rpn */
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, /* perms, wimge */
0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
@@ -234,7 +296,11 @@ void setup_mp(void)
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, /* perms, wimge */
0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
+#ifdef CONFIG_FSL_CORENET
+ corenet_mp_up(bootpg);
+#else
pq3_mp_up(bootpg);
+#endif
} else {
puts("WARNING: No reset page TLB. "
"Skipping secondary core setup\n");
--
1.6.0.6
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[U-Boot] [PATCH 2/7] ppc/p4080: Add support for CoreNet style platform LAWs
On CoreNet based platforms the LAW address is split between an high &
low register and we no longer shift the address. Also, the target IDs
on CoreNet platforms have been completely re-assigned.
Additionally, added a new find_law() API to which LAW an address hits in.
This is need for the CoreNet style boot release code since it will need
to determine what the target ID should be set to for boot window
translation.
Signed-off-by: Kumar Gala
---
drivers/misc/fsl_law.c| 99 -
include/asm-ppc/fsl_law.h | 29 +
2 files changed, 127 insertions(+), 1 deletions(-)
diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c
index aa877c6..fba16ed 100644
--- a/drivers/misc/fsl_law.c
+++ b/drivers/misc/fsl_law.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008-2009 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, w...@denx.de.
@@ -48,6 +48,24 @@ DECLARE_GLOBAL_DATA_PTR;
void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
{
+#ifdef CONFIG_FSL_CORENET
+ volatile ccsr_local_t *ccm;
+ volatile u32 *base, *lawbarh, *lawbarl, *lawar;
+
+ ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
+
+ base = &(ccm->lawbarh0);
+ lawbarh = base + idx * 4;
+ lawbarl = lawbarh + 1;
+ lawar = lawbarl + 1;
+
+ gd->used_laws |= (1 << idx);
+
+ out_be32(lawar, 0);
+ out_be32(lawbarh, ((u64)addr >> 32));
+ out_be32(lawbarl, addr & 0x);
+ out_be32(lawar, LAWAR_EN | ((u32)id << 20) | (u32)sz);
+#else
volatile u32 *base = (volatile u32 *)(CONFIG_SYS_IMMR + 0xc08);
volatile u32 *lawbar = base + 8 * idx;
volatile u32 *lawar = base + 8 * idx + 2;
@@ -57,6 +75,7 @@ void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum
law_trgt_if id)
out_be32(lawar, 0);
out_be32(lawbar, addr >> 12);
out_be32(lawar, LAWAR_EN | ((u32)id << 20) | (u32)sz);
+#endif
/* Read back so that we sync the writes */
in_be32(lawar);
@@ -96,6 +115,23 @@ int set_last_law(phys_addr_t addr, enum law_size sz, enum
law_trgt_if id)
void disable_law(u8 idx)
{
+#ifdef CONFIG_FSL_CORENET
+ volatile ccsr_local_t *ccm;
+ volatile u32 *base, *lawbarh, *lawbarl, *lawar;
+
+ ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
+
+ base = &(ccm->lawbarh0);
+ lawbarh = base + idx * 4;
+ lawbarl = lawbarh + 1;
+ lawar = lawbarl + 1;
+
+ gd->used_laws &= ~(1 << idx);
+
+ out_be32(lawar, 0);
+ out_be32(lawbarh, 0);
+ out_be32(lawbarl, 0);
+#else
volatile u32 *base = (volatile u32 *)(CONFIG_SYS_IMMR + 0xc08);
volatile u32 *lawbar = base + 8 * idx;
volatile u32 *lawar = base + 8 * idx + 2;
@@ -104,10 +140,65 @@ void disable_law(u8 idx)
out_be32(lawar, 0);
out_be32(lawbar, 0);
+#endif
return;
}
+#ifdef CONFIG_FSL_CORENET
+#define GET_LAW_ADDR ((u64)in_be32(lawbarh) << 32) | in_be32(lawbarl)
+#else
+#define GET_LAW_ADDR ((u64)in_be32(lawbar) << 12)
+#endif
+
+struct law_entry find_law(phys_addr_t addr)
+{
+ struct law_entry entry;
+ int i;
+
+ entry.index = -1;
+ entry.addr = 0;
+ entry.size = 0;
+ entry.trgt_id = 0;
+
+ for(i = 0; i < FSL_HW_NUM_LAWS; i++) {
+
+ u64 upper;
+ u32 temp;
+#ifdef CONFIG_FSL_CORENET
+ volatile ccsr_local_t *ccm;
+ volatile u32 *base, *lawbarh, *lawbarl, *lawar;
+
+ ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
+
+ base = &(ccm->lawbarh0);
+ lawbarh = base + i * 4;
+ lawbarl = lawbarh + 1;
+ lawar = lawbarl + 1;
+#else
+ volatile u32 *base = (volatile u32 *)(CONFIG_SYS_IMMR + 0xc08);
+ volatile u32 *lawbar = base + 8 * i;
+ volatile u32 *lawar = base + 8 * i + 2;
+#endif
+ temp = in_be32(lawar);
+
+ if (!(temp & LAWAR_EN))
+ continue;
+
+ entry.addr = GET_LAW_ADDR;
+ entry.size = temp & 0x3f;
+ entry.trgt_id = (temp >> 20) & 0xff;
+
+ upper = entry.addr + (2ull << entry.size);
+ if ((addr >= entry.addr) && (addr < upper)) {
+ entry.index = i;
+ break;
+ }
+ }
+
+ return entry;
+}
+
void print_laws(void)
{
volatile u32 *base = (volatile u32 *)(CONFIG_SYS_IMMR + 0xc08);
@@ -173,7 +264,13 @@ void init_laws(void)
{
int i;
+#if FSL_HW_NUM_LAWS < 32
gd->used_laws = ~((1 << FSL_HW_NUM_LAWS) - 1);
+#elif FSL_HW_NUM_LAWS == 32
+ gd->used_laws = 0;
+#else
+#error FSL_HW_NUM_LAWS can not be greater than 32 w/o code changes
+#endif
for (i = 0; i < num_law_entries; i++) {
[U-Boot] [PATCH 6/7] ppc/p4080: Handle timebase enabling and frequency reporting
On CoreNet style platforms the timebase frequency is the bus frequency
defined by 16 (on PQ3 it is divide by 8). Also on the CoreNet platforms
the core not longer controls the enabling of the timebase. We now need
to enable the boot core's timebase via CCSR register writes.
Signed-off-by: Kumar Gala
---
cpu/mpc85xx/cpu.c |4
cpu/mpc85xx/cpu_init.c | 12
cpu/mpc85xx/fdt.c |7 ++-
3 files changed, 22 insertions(+), 1 deletions(-)
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index bdd9ee4..25c0416 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -184,7 +184,11 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int
argc, char *argv[])
*/
unsigned long get_tbclk (void)
{
+#ifdef CONFIG_FSL_CORENET
+ return (gd->bus_clk + 8) / 16;
+#else
return (gd->bus_clk + 4UL)/8UL;
+#endif
}
diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index a6d1e99..428b461 100644
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -229,6 +229,18 @@ void cpu_init_f (void)
#if defined(CONFIG_FSL_DMA)
dma_init();
#endif
+#ifdef CONFIG_FSL_CORENET
+ {
+ volatile ccsr_rcpm_t *rcpm =
+ (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
+ volatile ccsr_pic_t *pic =
+ (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
+ u32 whoami = in_be32(&pic->whoami);
+
+ /* Enable the timebase register for this core */
+ out_be32(&rcpm->ctbenrl, (1 << whoami));
+ }
+#endif
}
diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c
index 723f473..ff5824b 100644
--- a/cpu/mpc85xx/fdt.c
+++ b/cpu/mpc85xx/fdt.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2007 Freescale Semiconductor, Inc.
+ * Copyright 2007-2009 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, w...@denx.de.
@@ -286,8 +286,13 @@ void ft_cpu_setup(void *blob, bd_t *bd)
fdt_add_enet_stashing(blob);
+#ifdef CONFIG_FSL_CORENET
+ do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
+ "timebase-frequency", bd->bi_busfreq / 16, 1);
+#else
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"timebase-frequency", bd->bi_busfreq / 8, 1);
+#endif
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"bus-frequency", bd->bi_busfreq, 1);
get_sys_info(&sysinfo);
--
1.6.0.6
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[U-Boot] [PATCH 5/7] ppc/p4080: Add various p4080 related defines (and p4040)
There are various locations that we have chip specific info:
* Makefile for which ddr code to build
* Added p4080 & p4040 to cpu_type_list and SVR list
* Added number of LAWs for p4080
* Set CONFIG_MAX_CPUS to 8 for p4080
Signed-off-by: Kumar Gala
---
cpu/mpc85xx/Makefile|1 +
cpu/mpc8xxx/cpu.c |4
drivers/misc/fsl_law.c |2 ++
include/asm-ppc/config.h|6 --
include/asm-ppc/processor.h |4
5 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile
index 3ef00e8..56de7eb 100644
--- a/cpu/mpc85xx/Makefile
+++ b/cpu/mpc85xx/Makefile
@@ -53,6 +53,7 @@ COBJS-$(CONFIG_P1011) += ddr-gen3.o
COBJS-$(CONFIG_P1020) += ddr-gen3.o
COBJS-$(CONFIG_P2010) += ddr-gen3.o
COBJS-$(CONFIG_P2020) += ddr-gen3.o
+COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o
COBJS-$(CONFIG_CPM2) += ether_fcc.o
COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
diff --git a/cpu/mpc8xxx/cpu.c b/cpu/mpc8xxx/cpu.c
index 00791e1..d191263 100644
--- a/cpu/mpc8xxx/cpu.c
+++ b/cpu/mpc8xxx/cpu.c
@@ -72,6 +72,10 @@ struct cpu_type cpu_type_list [] = {
CPU_TYPE_ENTRY(P2010, P2010_E, 1),
CPU_TYPE_ENTRY(P2020, P2020, 2),
CPU_TYPE_ENTRY(P2020, P2020_E, 2),
+ CPU_TYPE_ENTRY(P4040, P4040, 4),
+ CPU_TYPE_ENTRY(P4040, P4040_E, 4),
+ CPU_TYPE_ENTRY(P4080, P4080, 8),
+ CPU_TYPE_ENTRY(P4080, P4080_E, 8),
#elif defined(CONFIG_MPC86xx)
CPU_TYPE_ENTRY(8610, 8610, 1),
CPU_TYPE_ENTRY(8641, 8641, 2),
diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c
index fba16ed..626bab2 100644
--- a/drivers/misc/fsl_law.c
+++ b/drivers/misc/fsl_law.c
@@ -42,6 +42,8 @@ DECLARE_GLOBAL_DATA_PTR;
defined(CONFIG_P1011) || defined(CONFIG_P1020) || \
defined(CONFIG_P2010) || defined(CONFIG_P2020)
#define FSL_HW_NUM_LAWS 12
+#elif defined(CONFIG_PPC_P4080)
+#define FSL_HW_NUM_LAWS 32
#else
#error FSL_HW_NUM_LAWS not defined for this platform
#endif
diff --git a/include/asm-ppc/config.h b/include/asm-ppc/config.h
index 5670d06..e35b0b7 100644
--- a/include/asm-ppc/config.h
+++ b/include/asm-ppc/config.h
@@ -40,9 +40,11 @@
#if defined(CONFIG_MPC8572) || defined(CONFIG_P1020) || \
defined(CONFIG_P2020) || defined(CONFIG_MPC8641)
-#define CONFIG_MAX_CPUS2
+#define CONFIG_MAX_CPUS2
+#elif defined(CONFIG_PPC_P4080)
+#define CONFIG_MAX_CPUS8
#else
-#define CONFIG_MAX_CPUS1
+#define CONFIG_MAX_CPUS1
#endif
#endif /* _ASM_CONFIG_H_ */
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 3764a5a..d009957 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -1031,6 +1031,10 @@
#define SVR_P2010_E0x80EB00
#define SVR_P2020 0x80E200
#define SVR_P2020_E0x80EA00
+#define SVR_P4040 0x820100
+#define SVR_P4040_E0x820900
+#define SVR_P4080 0x82
+#define SVR_P4080_E0x820800
#define SVR_8610 0x80A000
#define SVR_8641 0x809000
--
1.6.0.6
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[U-Boot] [PATCH 0/7] ppc/p4080: infrastructure patches
This patch series includes the underpinings for the p4080 support. Its mostly focussed on the differenes in cpu/mpc85xx code between a PQ3/85xx platform and the p4080/CoreNet platforms. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 7/7] ppc/p4080: Determine various chip frequencies on CoreNet platforms
The means to determine the core, bus, and DDR frequencies are completely
new on CoreNet style platforms. Additionally on p4080 we can have
different frequencies for FMAN and PME IP blocks. We need to keep track
of the FMAN & PME frequencies since they are used for time stamping
capabilities inside each block.
Signed-off-by: Kumar Gala
---
cpu/mpc85xx/cpu.c | 29 +
cpu/mpc85xx/speed.c | 85 +++
include/e500.h |6 +++
3 files changed, 120 insertions(+), 0 deletions(-)
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index 25c0416..1c0f2b2 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -46,11 +46,20 @@ int checkcpu (void)
char buf1[32], buf2[32];
#ifdef CONFIG_DDR_CLK_FREQ
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#ifdef CONFIG_FSL_CORENET
+ u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
+ >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
+#else
u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
+#endif
+#else
+#ifdef CONFIG_FSL_CORENET
+ u32 ddr_sync = 0;
#else
u32 ddr_ratio = 0;
#endif
+#endif
int i;
svr = get_svr();
@@ -111,6 +120,16 @@ int checkcpu (void)
}
printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
+#ifdef CONFIG_FSL_CORENET
+ if (ddr_sync == 1)
+ printf(" DDR:%-4s MHz (%s MT/s data rate) (Synchronous),
",
+ strmhz(buf1, sysinfo.freqDDRBus/2),
+ strmhz(buf2, sysinfo.freqDDRBus));
+ else
+ printf(" DDR:%-4s MHz (%s MT/s data rate) (Asynchronous),
",
+ strmhz(buf1, sysinfo.freqDDRBus/2),
+ strmhz(buf2, sysinfo.freqDDRBus));
+#else
switch (ddr_ratio) {
case 0x0:
printf(" DDR:%-4s MHz (%s MT/s data rate), ",
@@ -128,6 +147,7 @@ int checkcpu (void)
strmhz(buf2, sysinfo.freqDDRBus));
break;
}
+#endif
if (sysinfo.freqLocalBus > LCRR_CLKDIV)
printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
@@ -143,6 +163,15 @@ int checkcpu (void)
printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE));
#endif
+#ifdef CONFIG_SYS_DPAA_FMAN
+ for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++)
+ printf(" FMAN%d: %s MHz\n", i, strmhz(buf1,
sysinfo.freqFMan[i]));
+#endif
+
+#ifdef CONFIG_SYS_DPAA_PME
+ printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME));
+#endif
+
puts("L1:D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
return 0;
diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c
index 2fdcefb..dc18798 100644
--- a/cpu/mpc85xx/speed.c
+++ b/cpu/mpc85xx/speed.c
@@ -1,5 +1,6 @@
/*
* Copyright 2004, 2007-2009 Freescale Semiconductor, Inc.
+ *
* (C) Copyright 2003 Motorola Inc.
* Xianghua Xiao, (x.x...@motorola.com)
*
@@ -37,6 +38,89 @@ DECLARE_GLOBAL_DATA_PTR;
void get_sys_info (sys_info_t * sysInfo)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#ifdef CONFIG_FSL_CORENET
+ volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
+
+ const u8 core_cplx_PLL[16] = {
+ [ 0] = 0, /* CC1 PPL / 1 */
+ [ 1] = 0, /* CC1 PPL / 2 */
+ [ 2] = 0, /* CC1 PPL / 4 */
+ [ 4] = 1, /* CC2 PPL / 1 */
+ [ 5] = 1, /* CC2 PPL / 2 */
+ [ 6] = 1, /* CC2 PPL / 4 */
+ [ 8] = 2, /* CC3 PPL / 1 */
+ [ 9] = 2, /* CC3 PPL / 2 */
+ [10] = 2, /* CC3 PPL / 4 */
+ [12] = 3, /* CC4 PPL / 1 */
+ [13] = 3, /* CC4 PPL / 2 */
+ [14] = 3, /* CC4 PPL / 4 */
+ };
+
+ const u8 core_cplx_PLL_div[16] = {
+ [ 0] = 1, /* CC1 PPL / 1 */
+ [ 1] = 2, /* CC1 PPL / 2 */
+ [ 2] = 4, /* CC1 PPL / 4 */
+ [ 4] = 1, /* CC2 PPL / 1 */
+ [ 5] = 2, /* CC2 PPL / 2 */
+ [ 6] = 4, /* CC2 PPL / 4 */
+ [ 8] = 1, /* CC3 PPL / 1 */
+ [ 9] = 2, /* CC3 PPL / 2 */
+ [10] = 4, /* CC3 PPL / 4 */
+ [12] = 1, /* CC4 PPL / 1 */
+ [13] = 2, /* CC4 PPL / 2 */
+ [14] = 4, /* CC4 PPL / 4 */
+ };
+ uint lcrr_div, i, freqCC_PLL[4], rcw_tmp;
+ unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
+
+ sysInfo->freqSystemBus = sysclk;
+ sysInfo->freqDDRBus = sysclk;
+ freqCC_PLL[0] = sysclk;
+ freqCC_PLL[1] = sysclk;
+ freqCC_PLL[2] = sysclk;
+ freqCC_PLL[3] = sysclk;
Re: [U-Boot] [PATCH] TI: DaVinci: DM355 Leopard board support
> From: Sandeep Paulraj > > This patch adds support for the leopard board which is > based on the DM355 SOC. > > Signed-off-by: Sandeep Paulraj > --- > Makefile |3 + > board/davinci/dm355leopard/Makefile | 52 + > board/davinci/dm355leopard/config.mk |6 + > board/davinci/dm355leopard/dm355leopard.c | 84 +++ > include/configs/davinci_dm355leopard.h| 162 > + > 5 files changed, 307 insertions(+), 0 deletions(-) > create mode 100644 board/davinci/dm355leopard/Makefile > create mode 100644 board/davinci/dm355leopard/config.mk > create mode 100644 board/davinci/dm355leopard/dm355leopard.c > create mode 100644 include/configs/davinci_dm355leopard.h Pushed to u-boot-ti ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] TI: DaVinci DM365: Enabling net support on DM365
> From: Sandeep Paulraj > > This patch enables EMAC on the DM365 EVM. > > Signed-off-by: Sandeep Paulraj > --- > board/davinci/dm365evm/dm365evm.c | 38 > + > 1 files changed, 38 insertions(+), 0 deletions(-) > Pushed to u-boot-ti ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/7] ppc/p4080: Add p4080 platform immap definitions
Kumar Gala wrote: > + u32 lawbarh0; /* 0xc00 - LAW0 base address register high */ > + u32 lawbarl0; /* 0xc04 - LAW0 base address register low */ > + u32 lawar0; /* 0xc08 - LAW0 attributes register */ > + u8 res4[4]; > + u32 lawbarh1; /* 0xc10 - LAW1 base address register high */ > + u32 lawbarl1; /* 0xc14 - LAW1 base address register low */ > + u32 lawar1; /* 0xc18 - LAW1 attributes register */ > + u8 res5[4]; > + u32 lawbarh2; /* 0xc20 - LAW2 base address register high */ > + u32 lawbarl2; /* 0xc24 - LAW2 base address register low */ > + u32 lawar2; /* 0xc28 - LAW2 attributes register */ > + u8 res6[4]; > + u32 lawbarh3; /* 0xc30 - LAW3 base address register high */ > + u32 lawbarl3; /* 0xc34 - LAW3 base address register low */ > + u32 lawar3; /* 0xc38 - LAW3 attributes register */ > + u8 res7[4]; > + u32 lawbarh4; /* 0xc40 - LAW4 base address register high */ > + u32 lawbarl4; /* 0xc44 - LAW4 base address register low */ > + u32 lawar4; /* 0xc48 - LAW4 attributes register */ > + u8 res8[4]; > + u32 lawbarh5; /* 0xc50 - LAW5 base address register high */ > + u32 lawbarl5; /* 0xc54 - LAW5 base address register low */ > + u32 lawar5; /* 0xc58 - LAW5 attributes register */ Can we use an array for this? Likewise many other parts. > + charres7[12]; > + uintpowmgtcsr; /* 0xe0080 - Power management status and > control register */ > + charres8[12]; > + uintcoredisru; /* 0xe0090 - uppper portion for support of 64 > cores */ > + uintcoredisrl; /* 0xe0094 - lower portion for support of 64 > cores */ > + charres9[8]; > + uintpvr;/* 0xe00a0 - Processor version register */ > + uintsvr;/* 0xe00a4 - System version register */ > + charres10[8]; > + uintrstcr; /* 0xe00b0 - Reset control register */ > + uintrstrqpblsr; /* 0xe00b4 - Reset request preboot loader > status register */ > + charres11[8]; > + uintrstrqmr1; /* 0xe00c0 - Reset request mask register */ > + charres12[4]; /* Reserved: RSTRQMR2 */ > + uintrstrqsr1; /* 0xe00c8 - Reset request status register */ > + charres13[4]; /* Reserved: RSTRQSR2 */ > + charres14[4]; /* Reserved: RSTRQWDTMRU */ > + uintrstrqwdtmrl;/* 0xe00d4 - Reset request WDT mask register */ > + charres15[4]; /* Reserved: RSTRQWDTSRU */ > + uintrstrqwdtsrl;/* 0xe00dc - Reset request WDT status register > */ > + charres16[4]; /* Reserved: BRRU max total of 2 for up to 64 > cores */ If those fields have a name, why not use the name instead of "res13" etc? If all these fields are 32 bit, why are the reserved fields char[4] rather than u32? It's very visually distracting. For that matter, s/uint/u32/. > -#define CONFIG_SYS_MPC85xx_GUTS_OFFSET (0xE) > +#ifdef CONFIG_FSL_CORENET > +#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET(0x) > +#define CONFIG_SYS_MPC85xx_DDR_OFFSET(0x8000) > +#define CONFIG_SYS_MPC85xx_DDR2_OFFSET (0x9000) > +#define CONFIG_SYS_FSL_CORENET_CLK_OFFSET(0xE1000) > +#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET (0xE2000) > +#define CONFIG_SYS_MPC85xx_DMA_OFFSET(0x10) > +#define CONFIG_SYS_MPC85xx_ESPI_OFFSET (0x11) > +#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET (0x114000) > +#define CONFIG_SYS_MPC85xx_LBC_OFFSET(0x124000) > +#define CONFIG_SYS_MPC85xx_GPIO_OFFSET (0x13) > +#define CONFIG_SYS_MPC85xx_QMAN_OFFSET (0x318000) > +#define CONFIG_SYS_MPC85xx_BMAN_OFFSET (0x31a000) > +#else > +#define CONFIG_SYS_MPC85xx_ECM_OFFSET(0x) > +#define CONFIG_SYS_MPC85xx_DDR_OFFSET(0x2000) > +#define CONFIG_SYS_MPC85xx_LBC_OFFSET(0x5000) > +#define CONFIG_SYS_MPC85xx_DDR2_OFFSET (0x6000) > +#define CONFIG_SYS_MPC85xx_ESPI_OFFSET (0x7000) > +#define CONFIG_SYS_MPC85xx_PCIX_OFFSET (0x8000) > +#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET (0x9000) > +#define CONFIG_SYS_MPC85xx_GPIO_OFFSET (0xF000) > +#define CONFIG_SYS_MPC85xx_SATA1_OFFSET (0x18000) > +#define CONFIG_SYS_MPC85xx_SATA2_OFFSET (0x19000) > +#define CONFIG_SYS_MPC85xx_L2_OFFSET (0x2) > +#define CONFIG_SYS_MPC85xx_DMA_OFFSET(0x21000) > +#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET (0x2e000) > +#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET(0xE3100) > +#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET(0xE3000) > +#define CONFIG_SYS_MPC
Re: [U-Boot] [PATCH v2] kwbimage.c: Fix compile warning when building on 64 bit systems (again)
In message <1253043494-11436-1-git-send-email...@denx.de> you wrote: > Commit 51003b89 attempted to fix a build problem on 64 bit systems, > but just turned it into a build problem on 32 bit systems (silly me). > > Now do the Right Thing (TM) and use a "%zu" printf format. > > Also fix spelling error. > > Signed-off-by: Wolfgang Denk > --- > v2: Also fix spelling error; cudos Mike Frysinger > > tools/kwbimage.c |2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) Applied. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Those who do not understand Unix are condemned to reinvent it, poorly. - Henry Spencer, University of Toronto Unix hack ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] board/flagadm/flash.c: fix compile warning
In message <1252966161-14156-1-git-send-email...@denx.de> you wrote: > Fix warning: flash.c:531: warning: dereferencing type-punned pointer > will break strict-aliasing rules > > Signed-off-by: Wolfgang Denk > Cc: Kári Davíðsson > --- > v2: change implementation as suggested by Scott Wood in > http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/67828/focus=67900 > > board/flagadm/flash.c | 12 +--- > 1 files changed, 9 insertions(+), 3 deletions(-) Applied. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de This cultural mystique surrounding the biological function -- you realize humans are overly preoccupied with the subject. -- Kelinda the Kelvan, "By Any Other Name", stardate 4658.9 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] TI: DaVinci: DM646x: Update flag used to represent DM646x SOC's
From: Sandeep Paulraj
In the DaVinci specific code, we use both CONFIG_SOC_DM646X and
CONFIG_SOC_DM646x to represent DM646x specific code.
This patch changes occurrences of CONFIG_SOC_DM646x to
CONFIG_SOC_DM646X. This is because for DM644x series of SOCs we use
the flag CONFIG_SOC_DM644X. We want some uniformity.
Signed-off-by: Sandeep Paulraj
---
include/asm-arm/arch-davinci/emac_defs.h |4 ++--
include/asm-arm/arch-davinci/nand_defs.h |2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/asm-arm/arch-davinci/emac_defs.h
b/include/asm-arm/arch-davinci/emac_defs.h
index ae75f84..96bc80e 100644
--- a/include/asm-arm/arch-davinci/emac_defs.h
+++ b/include/asm-arm/arch-davinci/emac_defs.h
@@ -50,7 +50,7 @@
#define EMAC_MDIO_BASE_ADDR(0x01c84000)
#endif
-#ifdef CONFIG_SOC_DM646x
+#ifdef CONFIG_SOC_DM646X
/* MDIO module input frequency */
#define EMAC_MDIO_BUS_FREQ 7650
/* MDIO clock output frequency */
@@ -283,7 +283,7 @@ typedef struct {
/* EMAC Wrapper Registers Structure */
typedef struct {
-#if defined(CONFIG_SOC_DM646x) || defined(CONFIG_SOC_DM365)
+#if defined(CONFIG_SOC_DM646X) || defined(CONFIG_SOC_DM365)
dv_reg IDVER;
dv_reg SOFTRST;
dv_reg EMCTRL;
diff --git a/include/asm-arm/arch-davinci/nand_defs.h
b/include/asm-arm/arch-davinci/nand_defs.h
index 386540e..10f3a39 100644
--- a/include/asm-arm/arch-davinci/nand_defs.h
+++ b/include/asm-arm/arch-davinci/nand_defs.h
@@ -28,7 +28,7 @@
#include
-#ifdef CONFIG_SOC_DM646x
+#ifdef CONFIG_SOC_DM646X
#defineMASK_CLE0x8
#defineMASK_ALE0x4
#else
--
1.6.0.4
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Re: [U-Boot] [STATUS] RFC: stretch merge window?
In message <20090916133226.bcd3d832e...@gemini.denx.de> I wrote: > Hi everybody... > > The reorganization of the ARM custodian setup has caused some changes > to the workflow, and I wonder if we should allow for a longer merge > window? > > What do you think about stretching the MW by another week (with or > without also shifting the release date) ? The feedback was pretty clear: we stretch the MW by one week, i. e. until Monday, September 28. The schedule for the release (Nov 18) does not change. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Be kind to unkind people - they need it the most. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/7] ppc/p4080: Add p4080 platform immap definitions
On Sep 18, 2009, at 4:20 PM, Scott Wood wrote:
> Kumar Gala wrote:
>> +u32 lawbarh0; /* 0xc00 - LAW0 base address register high */
>> +u32 lawbarl0; /* 0xc04 - LAW0 base address register low */
>> +u32 lawar0; /* 0xc08 - LAW0 attributes register */
>> +u8 res4[4];
>> +u32 lawbarh1; /* 0xc10 - LAW1 base address register high */
>> +u32 lawbarl1; /* 0xc14 - LAW1 base address register low */
>> +u32 lawar1; /* 0xc18 - LAW1 attributes register */
>> +u8 res5[4];
>> +u32 lawbarh2; /* 0xc20 - LAW2 base address register high */
>> +u32 lawbarl2; /* 0xc24 - LAW2 base address register low */
>> +u32 lawar2; /* 0xc28 - LAW2 attributes register */
>> +u8 res6[4];
>> +u32 lawbarh3; /* 0xc30 - LAW3 base address register high */
>> +u32 lawbarl3; /* 0xc34 - LAW3 base address register low */
>> +u32 lawar3; /* 0xc38 - LAW3 attributes register */
>> +u8 res7[4];
>> +u32 lawbarh4; /* 0xc40 - LAW4 base address register high */
>> +u32 lawbarl4; /* 0xc44 - LAW4 base address register low */
>> +u32 lawar4; /* 0xc48 - LAW4 attributes register */
>> +u8 res8[4];
>> +u32 lawbarh5; /* 0xc50 - LAW5 base address register high */
>> +u32 lawbarl5; /* 0xc54 - LAW5 base address register low */
>> +u32 lawar5; /* 0xc58 - LAW5 attributes register */
>
> Can we use an array for this? Likewise many other parts.
we could, but we didn't do this on PQ3 and I've got some other code
that depends on lawbar{h,l}0.
>> +charres7[12];
>> +uintpowmgtcsr; /* 0xe0080 - Power management status and
>> control
>> register */
>> +charres8[12];
>> +uintcoredisru; /* 0xe0090 - uppper portion for support of 64
>> cores */
>> +uintcoredisrl; /* 0xe0094 - lower portion for support of 64
>> cores */
>> +charres9[8];
>> +uintpvr;/* 0xe00a0 - Processor version register */
>> +uintsvr;/* 0xe00a4 - System version register */
>> +charres10[8];
>> +uintrstcr; /* 0xe00b0 - Reset control register */
>> +uintrstrqpblsr; /* 0xe00b4 - Reset request preboot loader
>> status
>> register */
>> +charres11[8];
>> +uintrstrqmr1; /* 0xe00c0 - Reset request mask register */
>> +charres12[4]; /* Reserved: RSTRQMR2 */
>> +uintrstrqsr1; /* 0xe00c8 - Reset request status register */
>> +charres13[4]; /* Reserved: RSTRQSR2 */
>> +charres14[4]; /* Reserved: RSTRQWDTMRU */
>> +uintrstrqwdtmrl;/* 0xe00d4 - Reset request WDT mask register */
>> +charres15[4]; /* Reserved: RSTRQWDTSRU */
>> +uintrstrqwdtsrl;/* 0xe00dc - Reset request WDT status register
>> */
>> +charres16[4]; /* Reserved: BRRU max total of 2 for up to 64
>> cores */
>
> If those fields have a name, why not use the name instead of "res13"
> etc?
For right now I'm leaving this alone. These registers are architected
but we just dont implement them in p4080. To catch any issues I'll
stick with it as is for now.
> If all these fields are 32 bit, why are the reserved fields char[4]
> rather than u32? It's very visually distracting.
I'll change char -> u8. However I'm not making u8[4] -> u32. For
historically reasons we used u8 since we autogen'd these in the past.
I'm sticking with u8 for reserved fields.
> For that matter, s/uint/u32/.
I'll make this change.
>
>> -#define CONFIG_SYS_MPC85xx_GUTS_OFFSET (0xE)
>> +#ifdef CONFIG_FSL_CORENET
>> +#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET (0x)
>> +#define CONFIG_SYS_MPC85xx_DDR_OFFSET (0x8000)
>> +#define CONFIG_SYS_MPC85xx_DDR2_OFFSET (0x9000)
>> +#define CONFIG_SYS_FSL_CORENET_CLK_OFFSET (0xE1000)
>> +#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET (0xE2000)
>> +#define CONFIG_SYS_MPC85xx_DMA_OFFSET (0x10)
>> +#define CONFIG_SYS_MPC85xx_ESPI_OFFSET (0x11)
>> +#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET (0x114000)
>> +#define CONFIG_SYS_MPC85xx_LBC_OFFSET (0x124000)
>> +#define CONFIG_SYS_MPC85xx_GPIO_OFFSET (0x13)
>> +#define CONFIG_SYS_MPC85xx_QMAN_OFFSET (0x318000)
>> +#define CONFIG_SYS_MPC85xx_BMAN_OFFSET (0x31a000)
>> +#else
>> +#define CONFIG_SYS_MPC85xx_ECM_OFFSET (0x)
>> +#define CONFIG_SYS_MPC85xx_DDR_OFFSET (0x2000)
>> +#define CONFIG_SYS_MPC85xx_LBC_OFFSET (0x5000)
>> +#define CONFIG_SYS_MPC85xx_DDR2_OFFSET (0x6000)
>> +#define CONFIG_SYS_MPC85xx_ESPI_OFFSET (0x7000)
>> +#define CONFIG_SYS_MPC85xx_PCIX_OFFSET (0x8000)
>> +#define CONFIG_
[U-Boot] [PATCH v2] ppc/p4080: Add p4080 platform immap definitions
The p4080 SoC has a significant amount of commonality with the 85xx/PQ3
platform. We reuse the 85xx immap and just add new definitions for
local access and global utils. The global utils is now broken into
global utils, clocking and run control/power management.
The offsets from CCSR for a number of blocks have also changed. We
introduce the CONFIG_FSL_CORENET define to distinquish the PQ3 style of
platform from the new p4080 platform. We don't use QoirQ as there are
products (like p2020) that are PQ3 based platforms but have the QoirQ
name.
Signed-off-by: Kumar Gala
---
* Removed parnes from _OFFSET
* Changed char -> u8
* Changed uint -> u32
include/asm-ppc/fsl_lbc.h|4 +
include/asm-ppc/immap_85xx.h | 408 +++--
2 files changed, 392 insertions(+), 20 deletions(-)
diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h
index 08d31e1..5723de6 100644
--- a/include/asm-ppc/fsl_lbc.h
+++ b/include/asm-ppc/fsl_lbc.h
@@ -317,6 +317,10 @@
#define LCRR_CLKDIV_2 0x0002
#define LCRR_CLKDIV_4 0x0004
#define LCRR_CLKDIV_8 0x0008
+#elif defined(CONFIG_FSL_CORENET)
+#define LCRR_CLKDIV_8 0x0002
+#define LCRR_CLKDIV_16 0x0004
+#define LCRR_CLKDIV_32 0x0008
#else
#define LCRR_CLKDIV_4 0x0002
#define LCRR_CLKDIV_8 0x0004
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index e7d412d..dc2093b 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -16,6 +16,150 @@
#include
#include
+typedef struct ccsr_local {
+ u32 ccsrbarh; /* 0x0 - Control Configuration Status Registers
Base Address Register High */
+ u32 ccsrbarl; /* 0x4 - Control Configuration Status Registers
Base Address Register Low */
+ u32 ccsrar; /* 0x8 - Configuration, Control, and Status
Attribute Register */
+#define CCSRAR_C 0x8000 /* Commit */
+ u8 res1[4];
+ u32 altcbarh; /* 0x10 - Alternate Configuration Base Address
Register High */
+ u32 altcbarl; /* 0x14 - Alternate Configuration Base Address
Register Low */
+ u32 altcar; /* 0x18 - Alternate Configuration Attribute
Register */
+ u8 res2[4];
+ u32 bstrh; /* 0x20 - Boot space translation register high
*/
+ u32 bstrl; /* 0x24 - Boot space translation register Low */
+ u32 bstrar; /* 0x28 - Boot space translation attributes
register */
+ u8 res3[0xbd4];
+ u32 lawbarh0; /* 0xc00 - LAW0 base address register high */
+ u32 lawbarl0; /* 0xc04 - LAW0 base address register low */
+ u32 lawar0; /* 0xc08 - LAW0 attributes register */
+ u8 res4[4];
+ u32 lawbarh1; /* 0xc10 - LAW1 base address register high */
+ u32 lawbarl1; /* 0xc14 - LAW1 base address register low */
+ u32 lawar1; /* 0xc18 - LAW1 attributes register */
+ u8 res5[4];
+ u32 lawbarh2; /* 0xc20 - LAW2 base address register high */
+ u32 lawbarl2; /* 0xc24 - LAW2 base address register low */
+ u32 lawar2; /* 0xc28 - LAW2 attributes register */
+ u8 res6[4];
+ u32 lawbarh3; /* 0xc30 - LAW3 base address register high */
+ u32 lawbarl3; /* 0xc34 - LAW3 base address register low */
+ u32 lawar3; /* 0xc38 - LAW3 attributes register */
+ u8 res7[4];
+ u32 lawbarh4; /* 0xc40 - LAW4 base address register high */
+ u32 lawbarl4; /* 0xc44 - LAW4 base address register low */
+ u32 lawar4; /* 0xc48 - LAW4 attributes register */
+ u8 res8[4];
+ u32 lawbarh5; /* 0xc50 - LAW5 base address register high */
+ u32 lawbarl5; /* 0xc54 - LAW5 base address register low */
+ u32 lawar5; /* 0xc58 - LAW5 attributes register */
+ u8 res9[4];
+ u32 lawbarh6; /* 0xc60 - LAW6 base address register high */
+ u32 lawbarl6; /* 0xc64 - LAW6 base address register low */
+ u32 lawar6; /* 0xc68 - LAW6 attributes register */
+ u8 res10[4];
+ u32 lawbarh7; /* 0xc70 - LAW7 base address register high */
+ u32 lawbarl7; /* 0xc74 - LAW7 base address register low */
+ u32 lawar7; /* 0xc78 - LAW7 attributes register */
+ u8 res11[4];
+ u32 lawbarh8; /* 0xc80 - LAW8 base address register high */
+ u32 lawbarl8; /* 0xc84 - LAW8 base address register low */
+ u32 lawar8; /* 0xc88 - LAW8 attributes register */
+ u8 res12[4];
+ u32 lawbarh9; /* 0xc90
Re: [U-Boot] [PATCH 2/7] ppc/p4080: Add support for CoreNet style platform LAWs
Kumar Gala wrote:
> void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
> {
> +#ifdef CONFIG_FSL_CORENET
> + volatile ccsr_local_t *ccm;
> + volatile u32 *base, *lawbarh, *lawbarl, *lawar;
We don't really need the volatile...
> void disable_law(u8 idx)
> {
> +#ifdef CONFIG_FSL_CORENET
> + volatile ccsr_local_t *ccm;
> + volatile u32 *base, *lawbarh, *lawbarl, *lawar;
> +
> + ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
> +
> + base = &(ccm->lawbarh0);
Use in_be32(). Likewise in find_law.
> +struct law_entry find_law(phys_addr_t addr)
> +{
> + struct law_entry entry;
> + int i;
> +
> + entry.index = -1;
> + entry.addr = 0;
> + entry.size = 0;
> + entry.trgt_id = 0;
> +
> + for(i = 0; i < FSL_HW_NUM_LAWS; i++) {
> +
> + u64 upper;
> + u32 temp;
> +#ifdef CONFIG_FSL_CORENET
> + volatile ccsr_local_t *ccm;
> + volatile u32 *base, *lawbarh, *lawbarl, *lawar;
> +
> + ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
> +
> + base = &(ccm->lawbarh0);
> + lawbarh = base + i * 4;
> + lawbarl = lawbarh + 1;
> + lawar = lawbarl + 1;
So the consequence of not using an array in the reg struct, is that we
don't use the reg struct. :-(
-Scott
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Re: [U-Boot] [PATCH 2/7] ppc/p4080: Add support for CoreNet style platform LAWs
Scott Wood wrote: >> +base = &(ccm->lawbarh0); > > Use in_be32(). Likewise in find_law. Grr, ignore me. I just had my brain baked by an ISO9000 presentation. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/7] ppc/p4080: Add support for CoreNet style platform LAWs
Scott Wood wrote: > Scott Wood wrote: > >>> +base = &(ccm->lawbarh0); >>> >> Use in_be32(). Likewise in find_law. >> > > Grr, ignore me. I just had my brain baked by an ISO9000 presentation. > > You should always just go home after those things. Let someone else drive, though :) Ben ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 6/7] ppc/p4080: Handle timebase enabling and frequency reporting
Kumar Gala wrote:
> On CoreNet style platforms the timebase frequency is the bus frequency
> defined by 16 (on PQ3 it is divide by 8). Also on the CoreNet platforms
> the core not longer controls the enabling of the timebase. We now need
> to enable the boot core's timebase via CCSR register writes.
>
> Signed-off-by: Kumar Gala
> ---
> cpu/mpc85xx/cpu.c |4
> cpu/mpc85xx/cpu_init.c | 12
> cpu/mpc85xx/fdt.c |7 ++-
> 3 files changed, 22 insertions(+), 1 deletions(-)
>
> diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
> index bdd9ee4..25c0416 100644
> --- a/cpu/mpc85xx/cpu.c
> +++ b/cpu/mpc85xx/cpu.c
> @@ -184,7 +184,11 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int
> argc, char *argv[])
> */
> unsigned long get_tbclk (void)
> {
> +#ifdef CONFIG_FSL_CORENET
> + return (gd->bus_clk + 8) / 16;
> +#else
> return (gd->bus_clk + 4UL)/8UL;
> +#endif
> }
[snip]
> +#ifdef CONFIG_FSL_CORENET
> + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
> + "timebase-frequency", bd->bi_busfreq / 16, 1);
> +#else
> do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
> "timebase-frequency", bd->bi_busfreq / 8, 1);
> +#endif
We could just use get_tbclk() here and not have to maintain the
knowledge in two places.
-Scott
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Re: [U-Boot] [PATCH v2] mx27ads: add support for iMX27ADS board from Freescale
Hi Javier, On 9/17/09, javier Martin wrote: > Has anyone tested ethernet connection in this board? > yes, it is working fine! Best Regards, Alan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] MAKEALL: Add summary information
This change adds some basic summary information to the MAKEALL script.
The summary information includes how many boards were compiled, how many
boards had compile warnings or errors, and which specific boards had
compile warnings or errors.
This information is useful when doing compile testing to quickly
determine which boards are broken.
As a side benefit, no empty $BOARD.ERR files are generated by MAKEALL.
Previously, each board had a corresponding $BOARD.ERR file, even if the
board compiled cleanly.
Signed-off-by: Peter Tyser
---
MAKEALL | 30 --
1 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/MAKEALL b/MAKEALL
index 1d50c34..d7c90ec 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -1,5 +1,8 @@
#!/bin/sh
+# Print statistics when ctrl-c is pressed
+trap "print_stats; exit " 2
+
# Determine number of CPU cores if no default was set
: ${BUILD_NCPUS:="`getconf _NPROCESSORS_ONLN`"}
@@ -31,6 +34,11 @@ fi
LIST=""
+# Keep track of the number of builds and errors
+ERR_CNT=0
+ERR_LIST=""
+TOTAL_CNT=0
+
#
## MPC5xx Systems
#
@@ -898,8 +906,14 @@ build_target() {
${MAKE} distclean >/dev/null
${MAKE} ${target}_config
- ${MAKE} ${JOBS} all 2>&1 >${LOG_DIR}/$target.MAKELOG \
- | tee ${LOG_DIR}/$target.ERR
+ ERR=$(${MAKE} ${JOBS} all 2>&1 > ${LOG_DIR}/$target.MAKELOG)
+ if [ "${ERR}" ] ; then
+ echo "$ERR" | tee ${LOG_DIR}/$target.ERR
+ ERR_CNT=`expr ${ERR_CNT} + 1`
+ ERR_LIST="${ERR_LIST} $target"
+ fi
+
+ TOTAL_CNT=`expr ${TOTAL_CNT} + 1`
${CROSS_COMPILE}size ${BUILD_DIR}/u-boot \
| tee -a ${LOG_DIR}/$target.MAKELOG
@@ -907,7 +921,17 @@ build_target() {
#---
+print_stats() {
+ echo ""
+ echo "- SUMMARY "
+ echo "Boards compiled: ${TOTAL_CNT}"
+ if [ ${ERR_CNT} -gt 0 ] ; then
+ echo "Boards with warnings or errors: ${ERR_CNT} (${ERR_LIST} )"
+ fi
+ echo "--"
+}
+#---
for arg in $@
do
case "$arg" in
@@ -931,4 +955,6 @@ do
*) build_target ${arg}
;;
esac
+
+ print_stats
done
--
1.6.2.1
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Re: [U-Boot] [PATCH 4/5] mpc83xx: mpc8360emds: Use RGMII mode, add workarounds for rev. 2.1 CPUs
On Wed, 16 Sep 2009 23:21:59 +0400 Anton Vorontsov wrote: > This patch fixes various ethernet issues with gigabit links handling > in U-Boot. The workarounds originally implemented by Kim Phillips for > Linux kernel. > > Signed-off-by: Anton Vorontsov > --- sorry, can't accept - this breaks r1.1 based boards: U-Boot 2009.08-00210-g089732e (Sep 18 2009 - 17:25:22) MPC83XX Reset Status: Software Hard, External/Internal Soft, External/Internal Hard CPU: e300c1, MPC8360E, Rev: 1.1 at 528 MHz, CSB: 264 MHz Board: Freescale MPC8360EMDS I2C: ready DRAM: 256 MB (DDR1, 64-bit, ECC off, 264 MHz) SDRAM: 64 MB (local bus) FLASH: 16 MB In:serial Out: serial Err: serial Net: FSL UEC0, FSL UEC1 Hit any key to stop autoboot: 0 => tftp $loadaddr $uboot UEC: PHY is Marvell 88E11x1 (1410cc2) FSL UEC0: Full Duplex FSL UEC0: Speed 1000BT FSL UEC0: Link is up Using FSL UEC0 device TFTP from server 192.168.1.1; our IP address is 192.168.1.118 Filename 'kimphill/u-boot.MPC8360EMDS'. Load address: 0x80 Loading: T T T T T T T T T T Retry count exceeded; starting again UEC: PHY is Marvell 88E11x1 (1410cc2) warning: FSL UEC1: timeout on PHY link FSL UEC0: Link is down Kim ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/7] ppc/p4080: Add support for CoreNet style platform LAWs
On Sep 18, 2009, at 4:55 PM, Scott Wood wrote: >> +#ifdef CONFIG_FSL_CORENET >> +volatile ccsr_local_t *ccm; >> +volatile u32 *base, *lawbarh, *lawbarl, *lawar; >> + >> +ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR); >> + >> +base = &(ccm->lawbarh0); >> +lawbarh = base + i * 4; >> +lawbarl = lawbarh + 1; >> +lawar = lawbarl + 1; > > So the consequence of not using an array in the reg struct, is that > we don't use the reg struct. :-( Maybe I'll get motivated and rework the code to have this as an array. (The thought did cross my mind about how it would have been nicer if there was an array. :) I think the reason we didn't have an array on PQ3 was the # kept growing. However I'm pretty sure 32 will be the max # for a while on CoreNet platforms. - k ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/5] mpc83xx: mpc8360emds: Use RGMII mode, add workarounds for rev. 2.1 CPUs
On Fri, Sep 18, 2009 at 05:40:45PM -0500, Kim Phillips wrote: > On Wed, 16 Sep 2009 23:21:59 +0400 > Anton Vorontsov wrote: > > > This patch fixes various ethernet issues with gigabit links handling > > in U-Boot. The workarounds originally implemented by Kim Phillips for > > Linux kernel. > > > > Signed-off-by: Anton Vorontsov > > --- > > sorry, can't accept - this breaks r1.1 based boards: Oops. Thanks a lot for testing. I think I know why it breaks, we should use RGMII_ID for < 2.1 revs (at least that's what we have in Linux by default). I don't have r1.1 CPUs, can you please try this patch on top of the current patch set? If it'll work, I'll repost a fixed version of this patch. diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index dab0173..62cf13b 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -399,7 +399,7 @@ #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC1_PHY_ADDR 0 -#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII +#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_ID #endif #define CONFIG_UEC_ETH2/* GETH2 */ @@ -410,7 +410,7 @@ #define CONFIG_SYS_UEC2_TX_CLK QE_CLK4 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC2_PHY_ADDR 1 -#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII +#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID #endif /* ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] MAKEALL: Add summary information
On Friday 18 September 2009 18:36:54 Peter Tyser wrote:
> +TOTAL_CNT=0
> + TOTAL_CNT=`expr ${TOTAL_CNT} + 1`
do you have an aversion to using POSIX math ?
: $((TOTAL_CNT += 1))
-mike
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[U-Boot] [PATCH v2] MAKEALL: Add summary information
This change adds some basic summary information to the MAKEALL script.
The summary information includes how many boards were compiled, how many
boards had compile warnings or errors, and which specific boards had
compile warnings or errors.
This information is useful when doing compile testing to quickly
determine which boards are broken.
As a side benefit, no empty $BOARD.ERR files are generated by MAKEALL.
Previously, each board had a corresponding $BOARD.ERR file, even if the
board compiled cleanly.
Signed-off-by: Peter Tyser
---
Changes since v1:
- Fix issue where summary was printed multiple times when a list
was composed of sublists
MAKEALL | 30 --
1 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/MAKEALL b/MAKEALL
index 1d50c34..a63d028 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -1,5 +1,8 @@
#!/bin/sh
+# Print statistics when ctrl-c is pressed
+trap "print_stats; exit " 2
+
# Determine number of CPU cores if no default was set
: ${BUILD_NCPUS:="`getconf _NPROCESSORS_ONLN`"}
@@ -31,6 +34,11 @@ fi
LIST=""
+# Keep track of the number of builds and errors
+ERR_CNT=0
+ERR_LIST=""
+TOTAL_CNT=0
+
#
## MPC5xx Systems
#
@@ -898,8 +906,14 @@ build_target() {
${MAKE} distclean >/dev/null
${MAKE} ${target}_config
- ${MAKE} ${JOBS} all 2>&1 >${LOG_DIR}/$target.MAKELOG \
- | tee ${LOG_DIR}/$target.ERR
+ ERR=$(${MAKE} ${JOBS} all 2>&1 > ${LOG_DIR}/$target.MAKELOG)
+ if [ "${ERR}" ] ; then
+ echo "$ERR" | tee ${LOG_DIR}/$target.ERR
+ ERR_CNT=`expr ${ERR_CNT} + 1`
+ ERR_LIST="${ERR_LIST} $target"
+ fi
+
+ TOTAL_CNT=`expr ${TOTAL_CNT} + 1`
${CROSS_COMPILE}size ${BUILD_DIR}/u-boot \
| tee -a ${LOG_DIR}/$target.MAKELOG
@@ -907,7 +921,17 @@ build_target() {
#---
+print_stats() {
+ echo ""
+ echo "- SUMMARY "
+ echo "Boards compiled: ${TOTAL_CNT}"
+ if [ ${ERR_CNT} -gt 0 ] ; then
+ echo "Boards with warnings or errors: ${ERR_CNT} (${ERR_LIST} )"
+ fi
+ echo "--"
+}
+#---
for arg in $@
do
case "$arg" in
@@ -932,3 +956,5 @@ do
;;
esac
done
+
+print_stats
--
1.6.2.1
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[U-Boot] [PATCH v3] MAKEALL: Add summary information
This change adds some basic summary information to the MAKEALL script.
The summary information includes how many boards were compiled, how many
boards had compile warnings or errors, and which specific boards had
compile warnings or errors.
This information is useful when doing compile testing to quickly
determine which boards are broken.
As a side benefit, no empty $BOARD.ERR files are generated by MAKEALL.
Previously, each board had a corresponding $BOARD.ERR file, even if the
board compiled cleanly.
Signed-off-by: Peter Tyser
---
Changes since v1:
- Fix issue where summary was printed multiple times when a list
was composed of sublists
Changes since v2:
- Update script to only use POSIX arithmetic
MAKEALL | 32 +---
1 files changed, 29 insertions(+), 3 deletions(-)
diff --git a/MAKEALL b/MAKEALL
index 1d50c34..e7bdbc4 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -1,11 +1,14 @@
#!/bin/sh
+# Print statistics when ctrl-c is pressed
+trap "print_stats; exit " 2
+
# Determine number of CPU cores if no default was set
: ${BUILD_NCPUS:="`getconf _NPROCESSORS_ONLN`"}
if [ "$BUILD_NCPUS" -gt 1 ]
then
- JOBS=-j`expr "$BUILD_NCPUS" + 1`
+ JOBS="-j $(($BUILD_NCPUS + 1))"
else
JOBS=""
fi
@@ -31,6 +34,11 @@ fi
LIST=""
+# Keep track of the number of builds and errors
+ERR_CNT=0
+ERR_LIST=""
+TOTAL_CNT=0
+
#
## MPC5xx Systems
#
@@ -898,8 +906,14 @@ build_target() {
${MAKE} distclean >/dev/null
${MAKE} ${target}_config
- ${MAKE} ${JOBS} all 2>&1 >${LOG_DIR}/$target.MAKELOG \
- | tee ${LOG_DIR}/$target.ERR
+ ERR=$(${MAKE} ${JOBS} all 2>&1 > ${LOG_DIR}/$target.MAKELOG)
+ if [ "${ERR}" ] ; then
+ echo "$ERR" | tee ${LOG_DIR}/$target.ERR
+ ERR_CNT=$(($ERR_CNT + 1))
+ ERR_LIST="${ERR_LIST} $target"
+ fi
+
+ TOTAL_CNT=$(($TOTAL_CNT + 1))
${CROSS_COMPILE}size ${BUILD_DIR}/u-boot \
| tee -a ${LOG_DIR}/$target.MAKELOG
@@ -907,7 +921,17 @@ build_target() {
#---
+print_stats() {
+ echo ""
+ echo "- SUMMARY "
+ echo "Boards compiled: ${TOTAL_CNT}"
+ if [ ${ERR_CNT} -gt 0 ] ; then
+ echo "Boards with warnings or errors: ${ERR_CNT} (${ERR_LIST} )"
+ fi
+ echo "--"
+}
+#---
for arg in $@
do
case "$arg" in
@@ -932,3 +956,5 @@ do
;;
esac
done
+
+print_stats
--
1.6.2.1
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Re: [U-Boot] [PATCH v3 1/3] NAND boot: MPC8536DS support
> > diff --git a/cpu/mpc85xx/cpu_init_nand.c
> > +void cpu_init_f(void)
> > +{
> > + ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
> > +
> > + /*
> > +* LCRR - Clock Ratio Register - set up local bus timing
> > +* when needed
> > +*/
> > + out_be32(&lbc->lcrr, LCRR_DBYP | LCRR_CLKDIV_8);
> > +
> > +#if defined(CONFIG_NAND_BR_PRELIM) \
> > + && defined(CONFIG_NAND_OR_PRELIM)
> > + out_be32(&lbc->br0, CONFIG_NAND_BR_PRELIM);
> > + out_be32(&lbc->or0, CONFIG_NAND_OR_PRELIM);
> > + /* for FPGA */
> > + out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM);
> > + out_be32(&lbc->or3, CONFIG_SYS_OR3_PRELIM);
> > +#else
> > +#error CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must
> be defined
> > +#endif
> > +
>
> Should we not have br/or1, br/or2, etc?
>
And FPGA stuff put here cpu/mpc85xx.
It is *not* good practice and should be move out from here.
I know the FPGA is for UART clock.
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Re: [U-Boot] [PATCH] [OneNAND] Board can override OneNAND IPL image
On Sat, Sep 19, 2009 at 4:37 AM, Scott Wood wrote: > On Wed, Sep 02, 2009 at 06:05:03PM +0900, Kyungmin Park wrote: >> Some board use more then 2KiB OneNAND IPL. >> E.G., S5PC100 loads 16KiB OneNAND IPL > > Why do we need a different image name based on how large the loader is? > Actually, S5PC100 has no problem to use 1KiB IPL. Internal boot ROM code read first 16KiB at OneNAND. We it's enough to use 1KiB. However, S5PC110 is different. It checks the 16KIB checksum located at latest 16KiB - 4 bytes. In compatible issue, we conclude that use 16KiB for both cpus. Thank you, Kyungmin Park ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] [OneNAND IPL] OneNAND board init support
On Sat, Sep 19, 2009 at 4:26 AM, Scott Wood wrote:
> On Sat, Aug 29, 2009 at 01:00:59PM +0900, Kyungmin Park wrote:
>> #define READ_INTERRUPT() \
>> - onenand_readw(THIS_ONENAND(ONENAND_REG_INTERRUPT))
>> + onenand_readw(ONENAND_REG_INTERRUPT)
>
> You could get rid of the newline now...
It exceeds the 80 columns.
>
>> +enum {
>> + ONENAND_USE_DEFAULT,
>> + ONENAND_USE_GENERIC,
>> +};
>
> What is this? Add a comment, and possibly more specific names.
I see redefine the specific names and comments.
>
>> +extern int (*onenand_read_page)(ulong block, ulong page,
>> + u_char *buf, int pagesize);
>
> Maybe use a weak function instead? Or an #ifdef
> CONFIG_SYS_ONENAND_BOARD_READ_PAGE that will keep the code for the
> generic version from being in the image (it'd be nice if we could
> optimize out replaced weak functions). It seems especially odd that you
> use one method for init and another for read page.
I tried to use weak function but it produces more than expected. as
you know it got size limitation.
When use the weak function. the apollon board will be broken.
and I don't want to use #ifdef. since Now we support two different
CPUs, s5pc100, s5pc110. these accesses different way. s5pc100 use own
OneNAND controller. but s5pc110 use generic OneNAND method.
That's reason to define the function pointer.
>
>> /* read a page with ECC */
>> -static inline int onenand_read_page(ulong block, ulong page,
>> +static int generic_onenand_read_page(ulong block, ulong page,
>> u_char * buf, int pagesize)
>
> Is the "generic" code really generic, or is it just one specific
> controller?
The 'generic' means the original OneNAND access method. Use NOR
interface and use OneNAND registers.
Most and Most generic method.
Only Samsung SoCs, s3c64xx series, and s5pc100 uses their own OneNAND
controller.
>
>> +#ifdef CONFIG_ONENAND_BOARD_INIT
>
> This should probably be CONFIG_SYS_ONENAND_BOARD_INIT -- it's not
> tweakable by the end user.
>
> How is this different from the existing CONFIG_USE_ONENAND_BOARD_INIT?
Okay l try to consider how to use same configurations.
>
>> + onenand_board_init(&page_is_4KiB, &page);
>> +#else
>> + onenand_generic_init(&page_is_4KiB, &page);
>> +#endif
>>
>> - if (onenand_readw(ONENAND_REG_TECHNOLOGY)) {
>> - pagesize = 4096; /* MLC OneNAND has 4KiB pagesize */
>> + if (page_is_4KiB) {
>> + pagesize = 4096; /* OneNAND has 4KiB pagesize */
>> erase_shift = 18;
>> - } else {
>> - pagesize = 2048;
>> - erase_shift = 17;
>> }
>
> I don't understand why you move the pagesize/erase_shift init before
> onenand_board_init, suggesting that the init code change it if it needs
> changing -- but then leave the page_is_4KiB stuff in the generic code.
>
> This should probably just be filled in by the init code without anything
> here.
No different. basically I assume OneNAND has 2KiB pagesize and
In special case, MLC, and 4KiB pagesize OneNAND set the 4KiB pagesize.
If you want to leave as before. no problem.
Please consider the code size and don't want to break exsiting board support.
That's reason I can't use weak function and use #ifdef at onenand_board_init.
Thank you,
Kyungmin Park
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[U-Boot] [PATCH 4/6] OMAP3: fix warnings when NAND/ONENAND is not used
Fix build warnings by putting specific used variables
under required #ifdefs for removing:
mem.c:227: warning: unused variable 'f_sec'
mem.c:226: warning: unused variable 'f_off'
mem.c:225: warning: unused variable 'size'
mem.c:224: warning: unused variable 'base'
mem.c:222: warning: unused variable 'gpmc_config'
Signed-off-by: Nishanth Menon
---
cpu/arm_cortexa8/omap3/mem.c |6 +-
1 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/cpu/arm_cortexa8/omap3/mem.c b/cpu/arm_cortexa8/omap3/mem.c
index 8d64478..e93343c 100644
--- a/cpu/arm_cortexa8/omap3/mem.c
+++ b/cpu/arm_cortexa8/omap3/mem.c
@@ -219,12 +219,16 @@ void enable_gpmc_cs_config(const u32 *gpmc_config, struct
gpmc_cs *cs, u32 base,
void gpmc_init(void)
{
/* putting a blanket check on GPMC based on ZeBu for now */
- u32 *gpmc_config = NULL;
gpmc_cfg = (struct gpmc *)GPMC_BASE;
+#if defined(CONFIG_CMD_NAND) || defined(CONFIG_CMD_ONENAND)
+ u32 *gpmc_config = NULL;
u32 base = 0;
u32 size = 0;
+#if defined(CONFIG_ENV_IS_IN_NAND) || defined(CONFIG_ENV_IS_IN_ONENAND)
u32 f_off = CONFIG_SYS_MONITOR_LEN;
u32 f_sec = 0;
+#endif
+#endif
u32 config = 0;
/* global settings */
--
1.6.0.4
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[U-Boot] [PATCH 2/6] OMAP3: export enable_gpmc_cs_config to board files
Export enable_gpmc_cs_config into common header to prevent warning: warning: implicit declaration of function 'enable_gpmc_cs_config' Signed-off-by: Nishanth Menon --- include/asm-arm/arch-omap3/sys_proto.h |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/include/asm-arm/arch-omap3/sys_proto.h b/include/asm-arm/arch-omap3/sys_proto.h index 2246f80..e59021e 100644 --- a/include/asm-arm/arch-omap3/sys_proto.h +++ b/include/asm-arm/arch-omap3/sys_proto.h @@ -34,6 +34,8 @@ void memif_init(void); void sdrc_init(void); void do_sdrc_init(u32, u32); void gpmc_init(void); +void enable_gpmc_cs_config(u32 *gpmc_config, struct gpmc_cs *cs, u32 base, + u32 size); void watchdog_init(void); void set_muxconf_regs(void); -- 1.6.0.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/6] OMAP3: Fix SDRC init
Defaults are for infenion DDR timings.
Since none of the supported boards currently do
XIP boot, these seem to be faulty. fix the values
as per the calculations(ACTIMA,B), conf
the sdrc power with pwdnen and wakeupproc bits
Signed-off-by: Nishanth Menon
---
cpu/arm_cortexa8/omap3/mem.c |3 ++-
include/asm-arm/arch-omap3/cpu.h |1 +
include/asm-arm/arch-omap3/mem.h |8
3 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/cpu/arm_cortexa8/omap3/mem.c b/cpu/arm_cortexa8/omap3/mem.c
index 079c848..8731c9d 100644
--- a/cpu/arm_cortexa8/omap3/mem.c
+++ b/cpu/arm_cortexa8/omap3/mem.c
@@ -164,7 +164,8 @@ void do_sdrc_init(u32 cs, u32 early)
writel(SDP_SDRC_SHARING, &sdrc_base->sharing);
/* Disable Power Down of CKE cuz of 1 CKE on combo part */
- writel(SRFRONRESET | PAGEPOLICY_HIGH, &sdrc_base->power);
+ writel(WAKEUPPROC | PWDNEN | SRFRONRESET | PAGEPOLICY_HIGH,
+ &sdrc_base->power);
writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
sdelay(0x2);
diff --git a/include/asm-arm/arch-omap3/cpu.h b/include/asm-arm/arch-omap3/cpu.h
index 8ab2e39..e51c4f3 100644
--- a/include/asm-arm/arch-omap3/cpu.h
+++ b/include/asm-arm/arch-omap3/cpu.h
@@ -222,6 +222,7 @@ struct sdrc {
#define PAGEPOLICY_HIGH(0x1 << 0)
#define SRFRONRESET(0x1 << 7)
+#define PWDNEN (0x1 << 2)
#define WAKEUPPROC (0x1 << 26)
#define DDR_SDRAM (0x1 << 0)
diff --git a/include/asm-arm/arch-omap3/mem.h b/include/asm-arm/arch-omap3/mem.h
index 5b9ac75..31cbdef 100644
--- a/include/asm-arm/arch-omap3/mem.h
+++ b/include/asm-arm/arch-omap3/mem.h
@@ -78,16 +78,16 @@ enum {
#define TRP_1653
#define TRAS_165 7
#define TRC_16510
-#define TRFC_165 21
+#define TRFC_165 12
#define V_ACTIMA_165 ((TRFC_165 << 27) | (TRC_165 << 22) | \
(TRAS_165 << 18) | (TRP_165 << 15) | \
(TRCD_165 << 12) | (TRRD_165 << 9) | \
(TDPL_165 << 6) | (TDAL_165))
#define TWTR_165 1
-#define TCKE_165 1
-#define TXP_1655
-#define XSR_16523
+#define TCKE_165 2
+#define TXP_1652
+#define XSR_16520
#define V_ACTIMB_165 (((TCKE_165 << 12) | (XSR_165 << 0)) | \
(TXP_165 << 8) | (TWTR_165 << 16))
--
1.6.0.4
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[U-Boot] [PATCH 6/6] ARM:OMAP3:SDP3430: initial support
From: David Brownell Start of SDP3430 support in "mainline" u-boot mainline code Original Patch written by David Brownell Support default jumpering and: - UART1/ttyS0 console(legacy sdp3430 u-boot) - UART3/ttyS2 console (matching other boards, and SDP HW docs) - Ethernet - mmc0 - NOR boot TODO: - mmc1 - NAND (boot or 128M storage) - OneNAND (boot or 256M storage) - Fix NOR env variable load - Review SDRC timing configuration/DPLL configuration - Dynamically read FPGA dip switch settings and map NOR/NAND/ONENAND devices to right chipselects Currently the UART1 is enabled by default. for compatibility with other OMAP3 u-boot platforms, enable the #define of CONSOLE_J9. Ref: SDP3430: http://focus.ti.com/general/docs/wtbu/wtbugencontent.tsp?templateId=6123&navigationId=12013&contentId=28741 Signed-off-by: David Brownell Signed-off-by: Nishanth Menon --- MAINTAINERS |1 + MAKEALL |1 + Makefile|3 + board/ti/sdp3430/Makefile | 49 ++ board/ti/sdp3430/config.mk | 33 board/ti/sdp3430/sdp.c | 194 ++ board/ti/sdp3430/sdp.h | 376 +++ board/ti/sdp3430/u-boot.lds | 63 +++ include/configs/omap3_sdp.h | 367 + 9 files changed, 1087 insertions(+), 0 deletions(-) create mode 100644 board/ti/sdp3430/Makefile create mode 100644 board/ti/sdp3430/config.mk create mode 100644 board/ti/sdp3430/sdp.c create mode 100644 board/ti/sdp3430/sdp.h create mode 100644 board/ti/sdp3430/u-boot.lds create mode 100644 include/configs/omap3_sdp.h diff --git a/MAINTAINERS b/MAINTAINERS index e9db278..adc8a63 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -619,6 +619,7 @@ Guennadi Liakhovetski Nishanth Menon omap3_zoom1 ARM CORTEX-A8 (OMAP3xx SoC) + omap3_sdp ARM CORTEX-A8 (OMAP3xx SoC) David Müller diff --git a/MAKEALL b/MAKEALL index f0ed8ea..53620eb 100755 --- a/MAKEALL +++ b/MAKEALL @@ -588,6 +588,7 @@ LIST_ARM_CORTEX_A8="\ omap3_pandora \ omap3_zoom1 \ omap3_zoom2 \ + omap3_sdp \ " # diff --git a/Makefile b/Makefile index 5a4a109..2626147 100644 --- a/Makefile +++ b/Makefile @@ -3172,6 +3172,9 @@ omap3_zoom1_config : unconfig omap3_zoom2_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 zoom2 logicpd omap3 +omap3_sdp_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 sdp3430 ti omap3 + # ## XScale Systems # diff --git a/board/ti/sdp3430/Makefile b/board/ti/sdp3430/Makefile new file mode 100644 index 000..2554c7b --- /dev/null +++ b/board/ti/sdp3430/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).a + +COBJS := sdp.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB):$(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/board/ti/sdp3430/config.mk b/board/ti/sdp3430/config.mk new file mode 100644 index 000..3726634 --- /dev/null +++ b/board/ti/sdp3430/config.mk @@ -0,0 +1,33 @@ +# +# (C) Copyright 2006-2009 +# Texas Instruments, +# +# OMAP 3430 SDP uses OMAP3 (ARM-CortexA8) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; yo
[U-Boot] [PATCH 5/6] DLMALLOC:!X86: add av_ initialization
This is questionable if this is really required
as the av_ static initalized values should have
been loaded to sdram as part of the boot process
and initialization should have been done.
Signed-off-by: Nishanth Menon
---
common/dlmalloc.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/common/dlmalloc.c b/common/dlmalloc.c
index 241db8c..bd509db 100644
--- a/common/dlmalloc.c
+++ b/common/dlmalloc.c
@@ -1527,6 +1527,11 @@ void *sbrk(ptrdiff_t increment)
*/
void mem_malloc_init(ulong start, ulong size)
{
+ u8 i;
+ av_[0] = av_[1] = 0;
+ for (i = 0; i < 128; i++)
+ av_[2 + i * 2] = av_[2 + i * 2 + 1] = bin_at(i);
+
mem_malloc_start = start;
mem_malloc_end = start + size;
mem_malloc_brk = start;
--
1.6.0.4
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[U-Boot] [PATCH 0/6] ARM:OMAP3:SDP3430 initial support
Hi, This series of patch provides minimal support for OMAP3430 based OMAP3 platform Ref: http://focus.ti.com/general/docs/wtbu/wtbugencontent.tsp?templateId=6123&navigationId=12013&contentId=28741 David Brownell (1): ARM:OMAP3:SDP3430: initial support Nishanth Menon (5): OMAP3: Fix SDRC init OMAP3: export enable_gpmc_cs_config to board files OMAP3: make gpmc_config as const OMAP3: fix warnings when NAND/ONENAND is not used DLMALLOC:!X86: add av_ initialization MAINTAINERS|1 + MAKEALL|1 + Makefile |3 + board/ti/sdp3430/Makefile | 49 board/ti/sdp3430/config.mk | 33 +++ board/ti/sdp3430/sdp.c | 194 board/ti/sdp3430/sdp.h | 376 board/ti/sdp3430/u-boot.lds| 63 ++ common/dlmalloc.c |5 + cpu/arm_cortexa8/omap3/mem.c | 15 +- include/asm-arm/arch-omap3/cpu.h |1 + include/asm-arm/arch-omap3/mem.h |8 +- include/asm-arm/arch-omap3/sys_proto.h |2 + include/configs/omap3_sdp.h| 367 +++ 14 files changed, 1109 insertions(+), 9 deletions(-) create mode 100644 board/ti/sdp3430/Makefile create mode 100644 board/ti/sdp3430/config.mk create mode 100644 board/ti/sdp3430/sdp.c create mode 100644 board/ti/sdp3430/sdp.h create mode 100644 board/ti/sdp3430/u-boot.lds create mode 100644 include/configs/omap3_sdp.h Regards, Nishanth Menon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/6] OMAP3: make gpmc_config as const
gpmc_config should not be a variant as it is board specific
hence make it a const parameter
Signed-off-by: Nishanth Menon
---
cpu/arm_cortexa8/omap3/mem.c |6 +++---
include/asm-arm/arch-omap3/sys_proto.h |2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/cpu/arm_cortexa8/omap3/mem.c b/cpu/arm_cortexa8/omap3/mem.c
index 8731c9d..8d64478 100644
--- a/cpu/arm_cortexa8/omap3/mem.c
+++ b/cpu/arm_cortexa8/omap3/mem.c
@@ -44,7 +44,7 @@ volatile unsigned int boot_flash_env_addr;
struct gpmc *gpmc_cfg;
#if defined(CONFIG_CMD_NAND)
-static u32 gpmc_m_nand[GPMC_MAX_REG] = {
+static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
M_NAND_GPMC_CONFIG1,
M_NAND_GPMC_CONFIG2,
M_NAND_GPMC_CONFIG3,
@@ -62,7 +62,7 @@ static u32 gpmc_m_nand[GPMC_MAX_REG] = {
#endif
#if defined(CONFIG_CMD_ONENAND)
-static u32 gpmc_onenand[GPMC_MAX_REG] = {
+static const u32 gpmc_onenand[GPMC_MAX_REG] = {
ONENAND_GPMC_CONFIG1,
ONENAND_GPMC_CONFIG2,
ONENAND_GPMC_CONFIG3,
@@ -193,7 +193,7 @@ void do_sdrc_init(u32 cs, u32 early)
writel(0, &sdrc_base->cs[cs].mcfg);
}
-void enable_gpmc_cs_config(u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
+void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32
base,
u32 size)
{
writel(0, &cs->config7);
diff --git a/include/asm-arm/arch-omap3/sys_proto.h
b/include/asm-arm/arch-omap3/sys_proto.h
index e59021e..34bd515 100644
--- a/include/asm-arm/arch-omap3/sys_proto.h
+++ b/include/asm-arm/arch-omap3/sys_proto.h
@@ -34,7 +34,7 @@ void memif_init(void);
void sdrc_init(void);
void do_sdrc_init(u32, u32);
void gpmc_init(void);
-void enable_gpmc_cs_config(u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
+void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32
base,
u32 size);
void watchdog_init(void);
--
1.6.0.4
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[U-Boot] [PATCH 2/8] sbc8548: get_clock_freq is not valid for this board
The get_clock_freq() comes from freescale/common/cadmus.c and is
only valid for the CDS based 85xx reference platforms. It would
be nice if we could read the 33 vs. 66MHz status somehow, but in
the meantime, tie it to CONFIG_SYS_CLK_FREQ like all the other
non-CDS boards do.
Signed-off-by: Paul Gortmaker
---
board/sbc8548/sbc8548.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index f4fd204..3104d37 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -336,13 +336,13 @@ pci_init_board(void)
uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /*
PORDEVSR[14] */
uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /*
PORPLLSR[16] */
- uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
+ uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */
if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
printf ("PCI host: %d bit, %s MHz, %s, %s\n",
(pci_32) ? 32 : 64,
- (pci_speed == 3000) ? "33" :
- (pci_speed == 6000) ? "66" : "unknown",
+ (pci_speed == 3300) ? "33" :
+ (pci_speed == 6600) ? "66" : "unknown",
pci_clk_sel ? "sync" : "async",
pci_arb ? "arbiter" : "external-arbiter"
);
--
1.6.4.1
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[U-Boot] [PATCH 6/8] sbc8548: enable use of PCI network cards
Create a board_eth_init to allow a place to hook in
the PCI ethernet init after all the eTSEC are up
and configured.
Signed-off-by: Paul Gortmaker
---
board/sbc8548/sbc8548.c |9 +
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index 0387140..c4dc5c5 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -32,6 +32,8 @@
#include
#include
#include
+#include
+#include
#include
#include
#include
@@ -446,6 +448,13 @@ pci_init_board(void)
}
+int board_eth_init(bd_t *bis)
+{
+ tsec_standard_init(bis);
+ pci_eth_init(bis);
+ return 0; /* otherwise cpu_eth_init gets run */
+}
+
int last_stage_init(void)
{
return 0;
--
1.6.4.1
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[U-Boot] [PATCH 0/8] Update/enhance sbc8548 support
This series represents a significant usability improvement to the sbc8548 board, by delivering: -64MB SODIMM flash now usable from u-boot -PCI and PCI-e properly configured and functional -twice the size of LBC SDRAM available -easy selection of configuration via Makefile target rules -a README file that sucks less. I've also cleaned up a bunch of stuff that was left over from when this board support was cloned off of the MPC8548CDS. There are still a couple things I'd like to get working on this board, like DDR config via SPD, and booting from the alternate flash bank (for ease of recovery), but what is here now is validated and complete, so no point in me sitting on these bits. Patches are in e-mail for review, or can be pulled as per below. Thanks, Paul. The following changes since commit 15fba3279b56333bdb65ead366f82c945ed320d1: Kumar Gala (1): ppc/85xx: Disable all async interrupt sources when we boot are available in the git repository at: git://openlinux.windriver.com/people/paulg/u-boot sbc8548 Paul Gortmaker (8): sbc8548: delete unused MPC8548CDS info carried over from port sbc8548: get_clock_freq is not valid for this board sbc8548: enable access to second bank of flash sbc8548: correct local bus SDRAM size from 64M to 128M sbc8548: update PCI/PCI-e support code sbc8548: enable use of PCI network cards sbc8548: allow enabling PCI via a make config option sbc8548: replace README with completely new document MAKEALL |4 + Makefile | 26 ++- board/sbc8548/Makefile|4 +- board/sbc8548/law.c | 12 +++- board/sbc8548/sbc8548.c | 98 board/sbc8548/tlb.c | 64 ++- doc/README.sbc8548| 189 - include/configs/sbc8548.h | 114 +-- 8 files changed, 356 insertions(+), 155 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/8] sbc8548: enable access to second bank of flash
The sbc8548 has a 64MB SODIMM flash module off of CS6 that
previously wasn't enumerated by u-boot. There were already
BR6/OR6 settings for it [used by cpu_init_f()] but there
was no TLB entry and it wasn't in the list of flash banks
reported to u-boot.
The location of the 64MB flash is "pulled back" 8MB from
a 64MB boundary, in order to allow address space for the
8MB boot flash that is at the end of 32 bit address space.
This means creating two 4MB TLB entries for the 8MB chunk,
and then expanding the original boot flash entry to 64MB
in order to cover the 8MB boot flash and the remainder
(56MB) of the user flash.
Signed-off-by: Paul Gortmaker
---
board/sbc8548/tlb.c | 26 ++
include/configs/sbc8548.h |7 ---
2 files changed, 26 insertions(+), 7 deletions(-)
diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c
index 18d11f6..dbb9ba8 100644
--- a/board/sbc8548/tlb.c
+++ b/board/sbc8548/tlb.c
@@ -42,13 +42,14 @@ struct fsl_e_tlb_entry tlb_table[] = {
0, 0, BOOKE_PAGESZ_4K, 0),
/*
-* TLB 0: 16M Non-cacheable, guarded
-* 0xff80 16M TLB for 8MB FLASH
+* TLB 0: 64M Non-cacheable, guarded
+* 0xfc00 56M 8MB -> 64MB of user flash
+* 0xff80 8M boot FLASH
* Out of reset this entry is only 4K.
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
+ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x80, CONFIG_SYS_ALT_FLASH
+ 0x80,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_16M, 1),
+ 0, 0, BOOKE_PAGESZ_64M, 1),
/*
* TLB 1: 256MNon-cacheable, guarded
@@ -103,6 +104,23 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_16M, 1),
+
+ /*
+* TLB 7: 4M Non-cacheable, guarded
+* 0xfb80 4M 1st 4MB block of 64MB user FLASH
+*/
+ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_4M, 1),
+
+ /*
+* TLB 8: 4M Non-cacheable, guarded
+* 0xfbc0 4M 2nd 4MB block of 64MB user FLASH
+*/
+ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x40, CONFIG_SYS_ALT_FLASH
+ 0x40,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 8, BOOKE_PAGESZ_4M, 1),
+
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index 3d05afb..8edba20 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -163,6 +163,7 @@
*/
#define CONFIG_SYS_BOOT_BLOCK 0xff80 /* start of 8MB Flash */
+#define CONFIG_SYS_ALT_FLASH 0xfb80 /* 64MB "user" flash */
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of
FLASH 16M */
#define CONFIG_SYS_BR0_PRELIM 0xff800801
@@ -171,9 +172,9 @@
#defineCONFIG_SYS_OR0_PRELIM 0xff806e65
#defineCONFIG_SYS_OR6_PRELIM 0xf8006e65
-#define CONFIG_SYS_FLASH_BANKS_LIST{CONFIG_SYS_FLASH_BASE}
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
+#define CONFIG_SYS_FLASH_BANKS_LIST{CONFIG_SYS_FLASH_BASE,
CONFIG_SYS_ALT_FLASH}
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT6 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT500 /* Flash Write Timeout (ms) */
--
1.6.4.1
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[U-Boot] [PATCH 7/8] sbc8548: allow enabling PCI via a make config option
Prior to this commit, to enable PCI, you had to go manually
edit the board config header, and if you had 33MHz PCI, you
had to manually change CONFIG_SYS_NS16550_CLK too, which was
not real user friendly,
This adds the typical PCI and clock speed make targets to the
toplevel Makefile in accordance with what is being done with
other boards.
Signed-off-by: Paul Gortmaker
---
MAKEALL |4
Makefile | 26 --
include/configs/sbc8548.h | 13 -
3 files changed, 36 insertions(+), 7 deletions(-)
diff --git a/MAKEALL b/MAKEALL
index 1d50c34..b394adb 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -399,6 +399,10 @@ LIST_85xx="\
PM856 \
sbc8540 \
sbc8548 \
+ sbc8548_PCI_33 \
+ sbc8548_PCI_66 \
+ sbc8548_PCI_33_PCIE \
+ sbc8548_PCI_66_PCIE \
sbc8560 \
socrates\
stxgp3 \
diff --git a/Makefile b/Makefile
index 0b61d05..28b20af 100644
--- a/Makefile
+++ b/Makefile
@@ -2570,8 +2570,30 @@ sbc8540_66_config: unconfig
fi
@$(MKCONFIG) -a SBC8540 ppc mpc85xx sbc8560
-sbc8548_config:unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc85xx sbc8548
+sbc8548_config \
+sbc8548_PCI_33_config \
+sbc8548_PCI_66_config \
+sbc8548_PCI_33_PCIE_config \
+sbc8548_PCI_66_PCIE_config: unconfig
+ @mkdir -p $(obj)include
+ @if [ "$(findstring _PCI_,$@)" ] ; then \
+ $(XECHO) -n "... PCI HOST at " ; \
+ echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \
+ echo "#define CONFIG_PCI1" >>$(obj)include/config.h ; \
+ fi ; \
+ if [ "$(findstring _33_,$@)" ] ; then \
+ $(XECHO) -n "33MHz ..." ; \
+ echo "#define CONFIG_SYS_CLK_DIV 2" >>$(obj)include/config.h ; \
+ fi ; \
+ if [ "$(findstring _66_,$@)" ] ; then \
+ $(XECHO) -n "66MHz" ; \
+ echo "#define CONFIG_SYS_CLK_DIV 1" >>$(obj)include/config.h ; \
+ fi ; \
+ if [ "$(findstring _PCIE_,$@)" ] ; then \
+ $(XECHO) -n " with PCI-e ... " ; \
+ echo "#define CONFIG_PCIE1" >>$(obj)include/config.h ; \
+ fi
+ @$(MKCONFIG) -a sbc8548 ppc mpc85xx sbc8548
sbc8560_config \
sbc8560_33_config \
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index e77e9e9..8eb5b4c 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -38,9 +38,6 @@
#define CONFIG_MPC8548 1 /* MPC8548 specific */
#define CONFIG_SBC8548 1 /* SBC8548 board specific */
-#undef CONFIG_PCI /* enable any pci type devices */
-#undef CONFIG_PCI1 /* PCI controller 1 */
-#undef CONFIG_PCIE1/* PCIE controler 1 (slot 1) */
#undef CONFIG_RIO
#ifdef CONFIG_PCI
@@ -58,7 +55,13 @@
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
-#define CONFIG_SYS_CLK_FREQ6600 /* SBC8548 default SYSCLK */
+/*
+ * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4]
+ */
+#ifndef CONFIG_SYS_CLK_DIV
+#define CONFIG_SYS_CLK_DIV 1 /* 2, if 33MHz PCI card installed */
+#endif
+#define CONFIG_SYS_CLK_FREQ(6600 / CONFIG_SYS_CLK_DIV)
/*
* These can be toggled for performance analysis, otherwise use default.
@@ -315,7 +318,7 @@
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE1
-#define CONFIG_SYS_NS16550_CLK 4 /* get_bus_freq(0) */
+#define CONFIG_SYS_NS16550_CLK (4 / CONFIG_SYS_CLK_DIV)
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
--
1.6.4.1
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[U-Boot] [PATCH 1/8] sbc8548: delete unused MPC8548CDS info carried over from port
There are a couple defines and PCI bridge quirks related to the PCI
backplane of the MPC8548CDS that have no meaning in the context of
the port to the sbc8548 board, so delete them.
Also, the form factor of the sbc8548 is a standalone board with a
single PCI-X and a single PCI-e slot. That pretty much guarantees
that it will never be a PCI agent itself, so the host/agent and root
complex/end node distinctions have been removed.
Similarly, since there is no physical connector mapping to PCI2, so
all references of PCI2 in the board support files have been removed
as well.
Signed-off-by: Paul Gortmaker
---
board/sbc8548/sbc8548.c | 63
include/configs/sbc8548.h |9 --
2 files changed, 6 insertions(+), 66 deletions(-)
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index e5b21b5..f4fd204 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -311,35 +311,9 @@ long int fixed_sdram (void)
}
#endif
-#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
-/* For some reason the Tundra PCI bridge shows up on itself as a
- * different device. Work around that by refusing to configure it.
- */
-void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct
pci_config_table *tab) { }
-
-static struct pci_config_table pci_sbc8548_config_table[] = {
- {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
- {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
- {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
- mpc85xx_config_via_usbide, {0,0,0}},
- {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
- mpc85xx_config_via_usb, {0,0,0}},
- {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
- mpc85xx_config_via_usb2, {0,0,0}},
- {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
- mpc85xx_config_via_power, {0,0,0}},
- {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
- mpc85xx_config_via_ac97, {0,0,0}},
- {},
-};
-
-static struct pci_controller pci1_hose = {
- config_table: pci_sbc8548_config_table};
-#endif /* CONFIG_PCI */
-
-#ifdef CONFIG_PCI2
-static struct pci_controller pci2_hose;
-#endif /* CONFIG_PCI2 */
+#ifdef CONFIG_PCI1
+static struct pci_controller pci1_hose;
+#endif /* CONFIG_PCI1 */
#ifdef CONFIG_PCIE1
static struct pci_controller pcie1_hose;
@@ -356,24 +330,20 @@ pci_init_board(void)
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
struct pci_controller *hose = &pci1_hose;
- struct pci_config_table *table;
struct pci_region *r = hose->regions;
uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /*
PORDEVSR[15] */
uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /*
PORDEVSR[14] */
uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /*
PORPLLSR[16] */
- uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent);
-
uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
- printf ("PCI: %d bit, %s MHz, %s, %s, %s\n",
+ printf ("PCI host: %d bit, %s MHz, %s, %s\n",
(pci_32) ? 32 : 64,
(pci_speed == 3000) ? "33" :
(pci_speed == 6000) ? "66" : "unknown",
pci_clk_sel ? "sync" : "async",
- pci_agent ? "agent" : "host",
pci_arb ? "arbiter" : "external-arbiter"
);
@@ -392,12 +362,6 @@ pci_init_board(void)
PCI_REGION_IO);
hose->region_count = r - hose->regions;
- /* relocate config table pointers */
- hose->config_table = \
- (struct pci_config_table *)((uint)hose->config_table +
gd->reloc_off);
- for (table = hose->config_table; table && table->vendor;
table++)
- table->config_device += gd->reloc_off;
-
hose->first_busno=first_free_busno;
fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
@@ -422,33 +386,18 @@ pci_init_board(void)
gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
#endif
-#ifdef CONFIG_PCI2
-{
- uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
- uint pci_dual = get_pci_dual ();/* PCI DUAL in CM_PCI[3] */
- if (pci_dual) {
- printf ("PCI2: 32 bit, 66 MHz, %s\n",
- pci2_clk_sel ? "sync" : "async");
- } else {
- printf ("PCI2: disabled\n");
- }
-}
-#else
- gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */
-#endif /* CONFIG_PCI2 */
+ gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable PCI2 */
#ifdef CONFIG_PCIE1
{
volatile ccsr_fsl_pci_t *pci = (cc
[U-Boot] [PATCH 4/8] sbc8548: correct local bus SDRAM size from 64M to 128M
The size of the LB SDRAM on this board is 128MB, spanning CS3
and CS4. It was previously only being configured for 64MB on
CS3, since that was what the original codebase of the MPC8548CDS
had. In addition to setting up BR4/OR4, this also adds the TLB
entry for the second half of the SDRAM.
Signed-off-by: Paul Gortmaker
---
board/sbc8548/sbc8548.c |8 +++-
board/sbc8548/tlb.c | 22 +++---
include/configs/sbc8548.h | 42 ++
3 files changed, 60 insertions(+), 12 deletions(-)
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index 3104d37..1db32ec 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -152,7 +152,7 @@ local_bus_init(void)
void
sdram_init(void)
{
-#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
+#if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
uint idx;
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
@@ -172,6 +172,12 @@ sdram_init(void)
lbc->br3 = CONFIG_SYS_BR3_PRELIM;
asm("msync");
+ lbc->or4 = CONFIG_SYS_OR4_PRELIM;
+ asm("msync");
+
+ lbc->br4 = CONFIG_SYS_BR4_PRELIM;
+ asm("msync");
+
lbc->lbcr = CONFIG_SYS_LBC_LBCR;
asm("msync");
diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c
index dbb9ba8..e173245 100644
--- a/board/sbc8548/tlb.c
+++ b/board/sbc8548/tlb.c
@@ -88,14 +88,22 @@ struct fsl_e_tlb_entry tlb_table[] = {
/*
* TLB 5: 64M Cacheable, non-guarded
-* 0xf000 64M LBC SDRAM
+* 0xf000 64M LBC SDRAM First half
*/
SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 5, BOOKE_PAGESZ_64M, 1),
/*
-* TLB 6: 16M Cacheable, non-guarded
+* TLB 6: 64M Cacheable, non-guarded
+* 0xf400 64M LBC SDRAM Second half
+*/
+ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x400,
CONFIG_SYS_LBC_SDRAM_BASE + 0x400,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 6, BOOKE_PAGESZ_64M, 1),
+
+ /*
+* TLB 7: 16M Cacheable, non-guarded
* 0xf800 1M 7-segment LED display
* 0xf810 1M User switches
* 0xf830 1M Board revision
@@ -103,23 +111,23 @@ struct fsl_e_tlb_entry tlb_table[] = {
*/
SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_16M, 1),
+ 0, 7, BOOKE_PAGESZ_16M, 1),
/*
-* TLB 7: 4M Non-cacheable, guarded
+* TLB 8: 4M Non-cacheable, guarded
* 0xfb80 4M 1st 4MB block of 64MB user FLASH
*/
SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_4M, 1),
+ 0, 8, BOOKE_PAGESZ_4M, 1),
/*
-* TLB 8: 4M Non-cacheable, guarded
+* TLB 9: 4M Non-cacheable, guarded
* 0xfbc0 4M 2nd 4MB block of 64MB user FLASH
*/
SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x40, CONFIG_SYS_ALT_FLASH
+ 0x40,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 8, BOOKE_PAGESZ_4M, 1),
+ 0, 9, BOOKE_PAGESZ_4M, 1),
};
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index 8edba20..4751013 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -196,13 +196,13 @@
#define CONFIG_SYS_EEPROM_BASE 0xf8b0
/*
- * SDRAM on the Local Bus
+ * SDRAM on the Local Bus (CS3 and CS4)
*/
#define CONFIG_SYS_LBC_SDRAM_BASE 0xf000 /* Localbus SDRAM */
-#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
+#define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */
/*
- * Base Register 3 and Option Register 3 configure SDRAM.
+ * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM.
* The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf000.
*
* For BR3, need:
@@ -220,7 +220,7 @@
#define CONFIG_SYS_BR3_PRELIM 0xf0001861
/*
- * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
+ * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
*
* For OR3, need:
*64MB mask for AM, OR3[0:7] = 1100
@@ -235,6 +235,40 @@
#define CONFIG_SYS_OR3_PRELIM 0xfc006cc0
+/*
+ * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM.
+ * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf400.
+ *
+ * For BR4, need:
+ *Base address of 0xf400 = BR[0:16] = 0100 0
+ *
[U-Boot] [PATCH 8/8] sbc8548: replace README with completely new document
The previous README.sbc8548 was pretty much content-free. Replace it with something that actually gives the end user some relevant hardware details, and also lists the u-boot configuration choices. Also in the cosmetic department, fix the bogus line in the Makefile that was carried over from the SBC8560 Makefile, and the typo in the sbc8548.c copyright. Signed-off-by: Paul Gortmaker --- board/sbc8548/Makefile |4 +- board/sbc8548/sbc8548.c |3 +- doc/README.sbc8548 | 189 ++- 3 files changed, 173 insertions(+), 23 deletions(-) diff --git a/board/sbc8548/Makefile b/board/sbc8548/Makefile index 9919a6e..09e5c2e 100644 --- a/board/sbc8548/Makefile +++ b/board/sbc8548/Makefile @@ -2,8 +2,8 @@ # (C) Copyright 2004-2006 # Wolfgang Denk, DENX Software Engineering, w...@denx.de. # -# (C) Copyright 2004 Wind River Systems Inc . -# Added support for Wind River SBC8560 board +# (C) Copyright 2007 Wind River Systems Inc . +# Added support for Wind River SBC8548 board # # See file CREDITS for list of people who contributed to this # project. diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index c4dc5c5..2978884 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -1,5 +1,6 @@ /* - * Copyright 2007 Wind River Systemes, Inc. + * Copyright 2007,2009 Wind River Systems, Inc. + * * Copyright 2007 Embedded Specialties, Inc. * * Copyright 2004, 2007 Freescale Semiconductor. diff --git a/doc/README.sbc8548 b/doc/README.sbc8548 index b34d040..d72d97d 100644 --- a/doc/README.sbc8548 +++ b/doc/README.sbc8548 @@ -1,27 +1,176 @@ -Wind River SBC8548 reference board -=== +Intro: +== -Copyright 2007, Embedded Specialties, Inc. -Copyright 2007 Wind River Systemes, Inc. -- +The SBC8548 is a stand alone single board computer with a 1GHz +MPC8548 CPU, 8MB boot flash, 64MB user flash and, 256MB DDR2 400MHz +memory. It also has 128MB SDRAM 100MHz LBC memory, with both a PCI-e, +and a PCI-X slot, dual mini-DB9 for UART, and dual RJ-45 for eTSEC +ethernet connections. -1. Building U-Boot --- -The SBC8548 code is known to build using ELDK 4.1. +U-boot Configuration: += -$ make sbc8548_config -Configuring for sbc8548 board... +The following possible u-boot configuration targets are available: -$ make + 1) sbc8548_config + 2) sbc8548_PCI_33_config + 3) sbc8548_PCI_66_config + 4) sbc8548_PCI_33_PCIE_config + 5) sbc8548_PCI_66_PCIE_config +Generally speaking, most people should choose to use #5. Details +of each choice are listed below. -2. Switch and Jumper Settings -- -All Jumpers & Switches are in their default positions. Please refer to -the board documentation for details. Some settings control CPU voltages -and settings may change with board revisions. +Choice #1 does not enable CONFIG_PCI, and assumes that the PCI slot +will be left empty (M66EN high), and so the board will operate with +a base clock of 66MHz. Note that you need both PCI enabled in u-boot +and linux in order to have functional PCI under linux. -3. Known limitations - -PCI: - The code to support PCI is currently disabled and has not been verified. +The second enables PCI support and builds for a 33MHz clock rate. Note +that if a 33MHz 32bit card is inserted in the slot, then the whole board +will clock down to a 33MHz base clock instead of the default 66MHz. This +will change the baud clocks and mess up your serial console output if you +were previously running at 66MHz. If you want to use a 33MHz PCI card, +then you should build a U-Boot with a _PCI_33_ config and store this +to flash prior to powering down the board and inserting the 33MHz PCI +card. [The above discussion assumes that the SW2[1-4] has not been changed +to reflect a different CCB:SYSCLK ratio] + +The third option builds PCI support in, and leaves the clocking at the +default 66MHz. Options four and five are just repeats of option two +and three, but with PCI-e support enabled as well. + +PCI output listing with an intel e1000 PCI-x and a Syskonnect SK-9Exx +is shown below for sbc8548_PCI_66_PCIE_config. (Note that PCI-e with +a 33MHz PCI configuration is currently untested.) + +=> pci 0 +Scanning PCI devices on bus 0 +BusDevFun VendorId DeviceId Device Class Sub-Class +_ +00.00.00 0x1057 0x0012 Processor 0x20 +00.01.00 0x8086 0x1026 Network controller 0x00 +=> pci 1 +Scanning PCI devices on bus 1 +BusDevFun VendorId DeviceId Device Class Sub-Class +_ +01.00.00 0x1957 0x0012 Processor 0x20 +=> pci 2 +Scanning PCI devices on bus 2 +BusDe
[U-Boot] [PATCH 5/8] sbc8548: update PCI/PCI-e support code
The PCI/PCI-e support for the sbc8548 was based on an earlier
version of what the MPC8548CDS board was using, and in its
current state it won't even compile. This re-syncs it to match
current MPC85xxCDS/MDS PCI-e support.
It borrows from the MPC8568MDS, in that it pulls the PCI-e I/O
back to 0xe280_ (where PCI2 would be on MPC8548CDS), and
similarly it coalesces the PCI and PCI-e mem into one single TLB.
Both PCI-x and PCI-e have been tested with intel e1000 cards
under linux (with an accompanying dts change in place)
Signed-off-by: Paul Gortmaker
---
board/sbc8548/law.c | 12 +-
board/sbc8548/sbc8548.c |9 ---
board/sbc8548/tlb.c | 48 +++-
include/configs/sbc8548.h | 43 +--
4 files changed, 59 insertions(+), 53 deletions(-)
diff --git a/board/sbc8548/law.c b/board/sbc8548/law.c
index e8c7ae2..6d1efc0 100644
--- a/board/sbc8548/law.c
+++ b/board/sbc8548/law.c
@@ -32,8 +32,10 @@
*
* 0x_ 0x0fff_ DDR 256M
* 0x8000_ 0x9fff_ PCI1 MEM512M
+ * 0xa000_ 0xbfff_ PCIe MEM512M
* 0xe000_ 0xe000_ CCSR1M
- * 0xe200_ 0xe2ff_ PCI1 IO 16M
+ * 0xe200_ 0xe27f_ PCI1 IO 8M
+ * 0xe280_ 0xe2ff_ PCIe IO 8M
* 0xf000_ 0xf7ff_ SDRAM 128M
* 0xf8b0_ 0xf80f_ EEPROM 1M
* 0xfb80_ 0xff7f_ FLASH (2nd bank)64M
@@ -48,8 +50,14 @@ struct law_entry law_table[] = {
#ifndef CONFIG_SPD_EEPROM
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
#endif
+#ifdef CONFIG_SYS_PCI1_MEM_PHYS
SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
- SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
+ SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI),
+#endif
+#ifdef CONFIG_SYS_PCIE1_MEM_PHYS
+ SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
+ SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
+#endif
/* LBC window - maps 256M 0xf000 -> 0x */
SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
};
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index 1db32ec..0387140 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -355,14 +355,14 @@ pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
- CONFIG_SYS_PCI1_MEM_BASE,
+ CONFIG_SYS_PCI1_MEM_BUS,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
- CONFIG_SYS_PCI1_IO_BASE,
+ CONFIG_SYS_PCI1_IO_BUS,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
@@ -400,6 +400,7 @@ pci_init_board(void)
struct pci_controller *hose = &pcie1_hose;
struct pci_region *r = hose->regions;
+ uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
@@ -414,14 +415,14 @@ pci_init_board(void)
/* outbound memory */
pci_set_region(r++,
- CONFIG_SYS_PCIE1_MEM_BASE,
+ CONFIG_SYS_PCIE1_MEM_BUS,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
- CONFIG_SYS_PCIE1_IO_BASE,
+ CONFIG_SYS_PCIE1_IO_BUS,
CONFIG_SYS_PCIE1_IO_PHYS,
CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c
index e173245..dab0eb1 100644
--- a/board/sbc8548/tlb.c
+++ b/board/sbc8548/tlb.c
@@ -52,58 +52,52 @@ struct fsl_e_tlb_entry tlb_table[] = {
0, 0, BOOKE_PAGESZ_64M, 1),
/*
-* TLB 1: 256MNon-cacheable, guarded
-* 0x8000 256MPCI1 MEM First half
+* TLB 1: 1G Non-cacheable, guarded
+* 0x8000 512MPCI1 MEM
+* 0xa000 512MPCIe MEM
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_
Re: [U-Boot] [PATCH 1/8] sbc8548: delete unused MPC8548CDS info carried over from port
On Sep 18, 2009, at 6:08 PM, Paul Gortmaker wrote: > There are a couple defines and PCI bridge quirks related to the PCI > backplane of the MPC8548CDS that have no meaning in the context of > the port to the sbc8548 board, so delete them. > > Also, the form factor of the sbc8548 is a standalone board with a > single PCI-X and a single PCI-e slot. That pretty much guarantees > that it will never be a PCI agent itself, so the host/agent and root > complex/end node distinctions have been removed. > > Similarly, since there is no physical connector mapping to PCI2, so > all references of PCI2 in the board support files have been removed > as well. > > Signed-off-by: Paul Gortmaker > --- > board/sbc8548/sbc8548.c | 63 +++ > + > include/configs/sbc8548.h |9 -- > 2 files changed, 6 insertions(+), 66 deletions(-) Can we look at using fsl_pci_init_port()? See my recent patches for p2020/mpc8572ds/mpc8536ds - k ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
