[Qemu-devel] [PATCH] linux-user: Update MIPS specific prctl() implementation
From: Stefan Markovic
Perform needed checks before actual prctl() PR_SET_FP_MODE and
PR_GET_FP_MODE work based on kernel implementation. Also, update
necessary hflags.
Signed-off-by: Stefan Markovic
---
linux-user/syscall.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 810a58b..10db8b7 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -9544,9 +9544,25 @@ static abi_long do_syscall1(void *cpu_env, int num,
abi_long arg1,
{
CPUMIPSState *env = ((CPUMIPSState *)cpu_env);
bool old_fr = env->CP0_Status & (1 << CP0St_FR);
+bool old_fre = env->CP0_Config5 & (1 << CP0C5_FRE);
bool new_fr = arg2 & TARGET_PR_FP_MODE_FR;
bool new_fre = arg2 & TARGET_PR_FP_MODE_FRE;
+const unsigned int known_bits = TARGET_PR_FP_MODE_FR |
+TARGET_PR_FP_MODE_FRE;
+
+/* If nothing to change, return right away, successfully. */
+if (old_fr == new_fr && old_fre == new_fre) {
+return 0;
+}
+/* Check the value is valid */
+if (arg2 & ~known_bits) {
+return -TARGET_EOPNOTSUPP;
+}
+/* Setting FRE without FR is not supported. */
+if (new_fre && !new_fr) {
+return -TARGET_EOPNOTSUPP;
+}
if (new_fr && !(env->active_fpu.fcr0 & (1 << FCR0_F64))) {
/* FR1 is not supported */
return -TARGET_EOPNOTSUPP;
@@ -9576,6 +9592,7 @@ static abi_long do_syscall1(void *cpu_env, int num,
abi_long arg1,
env->hflags |= MIPS_HFLAG_F64;
} else {
env->CP0_Status &= ~(1 << CP0St_FR);
+env->hflags &= ~MIPS_HFLAG_F64;
}
if (new_fre) {
env->CP0_Config5 |= (1 << CP0C5_FRE);
@@ -9584,6 +9601,7 @@ static abi_long do_syscall1(void *cpu_env, int num,
abi_long arg1,
}
} else {
env->CP0_Config5 &= ~(1 << CP0C5_FRE);
+env->hflags &= ~MIPS_HFLAG_FRE;
}
return 0;
--
1.9.1
Re: [Qemu-devel] [PATCH] MAINTAINERS: Add Stefan Markovic as a MIPS reviewer
On 15.11.18. 16:59, Aleksandar Markovic wrote: > From: Aleksandar Markovic > > Add Stefan Markovic as a MIPS reviewer. He had several key > contributions to QEMU for MIPS this year. He is a meticulous > person with the ability to think and act on many levels. > > Signed-off-by: Aleksandar Markovic > --- > MAINTAINERS | 9 + > 1 file changed, 9 insertions(+) Reviewed-by: Stefan Markovic > diff --git a/MAINTAINERS b/MAINTAINERS > index 4b8db61..f718264 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -190,6 +190,7 @@ F: disas/microblaze.c > MIPS > M: Aurelien Jarno > M: Aleksandar Markovic > +R: Stefan Markovic > S: Maintained > F: target/mips/ > F: hw/mips/ > @@ -336,6 +337,7 @@ F: target/arm/kvm.c > > MIPS > M: James Hogan > +R: Stefan Markovic > S: Maintained > F: target/mips/kvm.c > > @@ -741,27 +743,32 @@ MIPS Machines > - > Jazz > M: Hervé Poussineau > +R: Stefan Markovic > S: Maintained > F: hw/mips/mips_jazz.c > > Malta > M: Aurelien Jarno > +R: Stefan Markovic > S: Maintained > F: hw/mips/mips_malta.c > > Mipssim > M: Aleksandar Markovic > +R: Stefan Markovic > S: Odd Fixes > F: hw/mips/mips_mipssim.c > F: hw/net/mipsnet.c > > R4000 > M: Aurelien Jarno > +R: Stefan Markovic > S: Maintained > F: hw/mips/mips_r4k.c > > Fulong 2E > M: Aleksandar Markovic > +R: Stefan Markovic > S: Odd Fixes > F: hw/mips/mips_fulong2e.c > F: hw/isa/vt82c686.c > @@ -770,6 +777,7 @@ F: include/hw/isa/vt82c686.h > > Boston > M: Paul Burton > +R: Stefan Markovic > S: Maintained > F: hw/core/loader-fit.c > F: hw/mips/boston.c > @@ -1992,6 +2000,7 @@ F: disas/i386.c > > MIPS target > M: Aurelien Jarno > +R: Stefan Markovic > S: Maintained > F: tcg/mips/ > F: disas/mips.c
Re: [Qemu-devel] [PATCH 1/3] target/mips: Add a comment with an overview of CP0 registers
On 15.10.2018. 12:50, Aleksandar Markovic wrote:
From: Aleksandar Markovic
Add a comment with an overview of CP0 registers close to the
definition of their corresponding fields in CPUMIPSState.
Signed-off-by: Aleksandar Markovic
---
target/mips/cpu.h | 109 ++
1 file changed, 109 insertions(+)
Reviewed-by: Stefan Markovic
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 28af4d1..cd54073 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -195,6 +195,115 @@ struct CPUMIPSState {
#define MSAIR_ProcID8
#define MSAIR_Rev 0
+/*
+ * Summary of CP0 registers
+ *
+ *
+ *
+ * Register 0Register 1Register 2Register 3
+ * --------
+ *
+ * 0 Index RandomEntryLo0 EntryLo1
+ * 1 MVPControlVPEControlTCStatus GlobalNumber
+ * 2 MVPConf0 VPEConf0 TCBind
+ * 3 MVPConf1 VPEConf1 TCRestart
+ * 4 VPControl YQMaskTCHalt
+ * 5 VPESchedule TCContext
+ * 6 VPEScheFBack TCSchedule
+ * 7 VPEOptTCScheFBack TCOpt
+ *
+ *
+ * Register 4Register 5Register 6Register 7
+ * --------
+ *
+ * 0 Context PageMask Wired HWREna
+ * 1 ContextConfig PageGrain SRSConf0
+ * 2 UserLocal SegCtl0 SRSConf1
+ * 3 XContextConfigSegCtl1 SRSConf2
+ * 4 DebugContextIDSegCtl2 SRSConf3
+ * 5 MemoryMapID PWBaseSRSConf4
+ * 6 PWField PWCtl
+ * 7 PWSize
+ *
+ *
+ * Register 8Register 9Register 10 Register 11
+ * ------- ---
+ *
+ * 0 BadVAddr Count EntryHi Compare
+ * 1 BadInstr
+ * 2 BadInstrP
+ * 3 BadInstrX
+ * 4 GuestCtl1 GuestCtl0Ext
+ * 5 GuestCtl2
+ * 6 GuestCtl3
+ * 7
+ *
+ *
+ * Register 12 Register 13 Register 14 Register 15
+ * --- --- --- ---
+ *
+ * 0 StatusCause EPC PRId
+ * 1 IntCtlEBase
+ * 2 SRSCtl NestedEPC CDMMBase
+ * 3 SRSMapCMGCRBase
+ * 4 View_IPL View_RIPL BEVVA
+ * 5 SRSMap2 NestedExc
+ * 6 GuestCtl0
+ * 7 GTOffset
+ *
+ *
+ * Register 16 Register 17 Register 18 Register 19
+ * --- --- --- ---
+ *
+ * 0 ConfigLLAddrWatchLo WatchHi
+ * 1 Config1 MAAR WatchLo WatchHi
+ * 2 Config2 MAARI WatchLo WatchHi
+ * 3 Config3 WatchLo WatchHi
+ * 4 Config4 WatchLo WatchHi
+ * 5 Config5 WatchLo WatchHi
+ * 6 WatchLo WatchHi
+ * 7 WatchLo WatchHi
+ *
+ *
+ * Register 20 Register 21 Register 22 Register 23
+ * --- --- --- ---
+ *
+ * 0 XContext Debug
+ * 1 TraceControl
+ * 2 TraceControl2
+ * 3 UserTraceData1
+ * 4 TraceIBPC
+ * 5 TraceDBPC
+ * 6 Debug2
+ * 7
+ *
+ *
+ * Register 24 Register 25 Register 26 Register 27
+ * --- --- --- ---
+ *
+ * 0 DEPC PerfCntErrCtl CacheErr
+ * 1 PerfCnt
+ * 2 TraceControl3 PerfCnt
+ * 3 UserTraceData2PerfCnt
+ * 4 PerfCnt
+ * 5 PerfCnt
+ * 6 PerfCnt
+ * 7 PerfCnt
+ *
+ *
+ * Register 28 Register 29 Register 30 Register 31
+ * --- --- --- ---
+ *
+ * 0 DataLo
Re: [Qemu-devel] [PATCH 3/3] mailmap: Add an item for Yongbok Kim
On 15.10.2018. 12:50, Aleksandar Markovic wrote: From: Aleksandar Markovic Yongbok Kim used two email adresses for QEMU contributions - his company changed its ownership/name. Signed-off-by: Aleksandar Markovic --- .mailmap | 1 + 1 file changed, 1 insertion(+) Reviewed-by: Stefan Markovic diff --git a/.mailmap b/.mailmap index 2c2b9b1..0d886a1 100644 --- a/.mailmap +++ b/.mailmap @@ -12,6 +12,7 @@ Fabrice Bellard bellard Jocelyn Mayer j_mayer Paul Brook pbrook +Yongbok Kim Aleksandar Markovic Aleksandar Markovic Paul Burton
Re: [Qemu-devel] [PATCH 1/4] target/mips: Add basic description of MXU ASE
On 16.10.18. 14:14, Aleksandar Markovic wrote:
From: Aleksandar Markovic
Add a comment that contains a basic description of MXU ASE.
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 20
1 file changed, 20 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index ab16cdb..23e21c5 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1389,6 +1389,26 @@ enum {
OPC_BINSRI_df = (0x7 << 23) | OPC_MSA_BIT_09,
};
+
+/*
+ *AN OVERVIEW OF MXU EXTENSTION INSTRUCTION SET
+ *=
Misspelled EXTENSION. Otherwise:
Reviewed-by: Stefan Markovic
+ *
+ * MXU (full name: MIPS eXtension/enhanced Unit) is an SIMD extension of MIPS32
+ * instructions set. It is designed to fit the needs of signal, graphical and
+ * video processing applications. MXU instruction set is used in Xburst family
+ * of microprocessors by Ingenic.
+ *
+ * MXU unit contains 17 registers called X0-X16. X0 is always zero, and X16 is
+ * the control register.
+ *
+ * Compiled after:
+ *
+ * "XBurst® Instruction Set Architecture MIPS eXtension/enhanced Unit
+ * Programming Manual", Ingenic Semiconductor Co, Ltd., 2017
+ */
+
+
/* global register indices */
static TCGv cpu_gpr[32], cpu_PC;
static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
Re: [Qemu-devel] [PATCH 2/4] target/mips: Add assembler mnemonics list for MXU ASE
On 16.10.18. 14:14, Aleksandar Markovic wrote:
From: Aleksandar Markovic
Add a comment that contains a list all MXU instructions,
expressed in assembler mnemonics.
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 88 +
1 file changed, 88 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 23e21c5..73d971e 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1402,6 +1402,94 @@ enum {
* MXU unit contains 17 registers called X0-X16. X0 is always zero, and X16 is
* the control register.
*
+ * The notation used in MXU assembler mnemonics:
+ *
+ * XRa, XRb, XRa, XRb - MXU registers
XRa and XRb duplicated. Did You mean XRc and XRd instead? Otherwise:
Reviewed-by: Stefan Markovic
+ * Rb, Rc, Rd, Rs, Rt - general purpose MIPS registers
+ * s12- a subfield of an instruction code
+ * strd2 - a subfield of an instruction code
+ * eptn2 - a subfield of an instruction code
+ * eptn3 - a subfield of an instruction code
+ * optn2 - a subfield of an instruction code
+ * optn3 - a subfield of an instruction code
+ * sft4 - a subfield of an instruction code
+ *
+ * Load/Store instructions Multiplication instructions
+ * --- ---
+ *
+ * S32LDD XRa, Rb, s12 S32MADD XRa, XRd, Rs, Rt
+ * S32STD XRa, Rb, s12 S32MADDU XRa, XRd, Rs, Rt
+ * S32LDDV XRa, Rb, rc, strd2S32SUB XRa, XRd, Rs, Rt
+ * S32STDV XRa, Rb, rc, strd2S32SUBU XRa, XRd, Rs, Rt
+ * S32LDI XRa, Rb, s12 S32MUL XRa, XRd, Rs, Rt
+ * S32SDI XRa, Rb, s12 S32MULU XRa, XRd, Rs, Rt
+ * S32LDIV XRa, Rb, rc, strd2D16MUL XRa, XRb, XRc, XRd, optn2
+ * S32SDIV XRa, Rb, rc, strd2D16MULE XRa, XRb, XRc, optn2
+ * S32LDDR XRa, Rb, s12 D16MULF XRa, XRb, XRc, optn2
+ * S32STDR XRa, Rb, s12 D16MAC XRa, XRb, XRc, XRd, aptn2, optn2
+ * S32LDDVR XRa, Rb, rc, strd2 D16MACE XRa, XRb, XRc, XRd, aptn2, optn2
+ * S32STDVR XRa, Rb, rc, strd2 D16MACF XRa, XRb, XRc, XRd, aptn2, optn2
+ * S32LDIR XRa, Rb, s12 D16MADL XRa, XRb, XRc, XRd, aptn2, optn2
+ * S32SDIR XRa, Rb, s12 S16MAD XRa, XRb, XRc, XRd, aptn1, optn2
+ * S32LDIVR XRa, Rb, rc, strd2 Q8MUL XRa, XRb, XRc, XRd
+ * S32SDIVR XRa, Rb, rc, strd2 Q8MULSU XRa, XRb, XRc, XRd
+ * S16LDD XRa, Rb, s10, eptn2Q8MAC XRa, XRb, XRc, XRd, aptn2
+ * S16STD XRa, Rb, s10, eptn2Q8MACSU XRa, XRb, XRc, XRd, aptn2
+ * S16LDI XRa, Rb, s10, eptn2Q8MADL XRa, XRb, XRc, XRd, aptn2
+ * S16SDI XRa, Rb, s10, eptn2
+ * S8LDD XRa, Rb, s8, eptn3
+ * S8STD XRa, Rb, s8, eptn3 Addition and subtraction instructions
+ * S8LDI XRa, Rb, s8, eptn3 -
+ * S8SDI XRa, Rb, s8, eptn3
+ * LXW Rd, Rs, Rt, strd2 D32ADD XRa, XRb, XRc, XRd, eptn2
+ * LXH Rd, Rs, Rt, strd2 D32ADDC XRa, XRb, XRc, XRd
+ * LXHU Rd, Rs, Rt, strd2D32ACC XRa, XRb, XRc, XRd, eptn2
+ * LXB Rd, Rs, Rt, strd2 D32ACCM XRa, XRb, XRc, XRd, eptn2
+ * LXBU Rd, Rs, Rt, strd2D32ASUM XRa, XRb, XRc, XRd, eptn2
+ *S32CPS XRa, XRb, XRc
+ *Q16ADD XRa, XRb, XRc, XRd, eptn2, optn2
+ * Comparison instructionsQ16ACC XRa, XRb, XRc, XRd, eptn2
+ * ---Q16ACCM XRa, XRb, XRc, XRd, eptn2
+ *D16ASUM XRa, XRb, XRc, XRd, eptn2
+ * S32MAX XRa, XRb, XRc D16CPS XRa, XRb,
+ * S32MIN XRa, XRb, XRc D16AVG XRa, XRb, XRc
+ * S32SLT XRa, XRb, XRc D16AVGR XRa, XRb, XRc
+ * S32MOVZ XRa, XRb, XRc Q8ADD XRa, XRb, XRc, eptn2
+ * S32MOVN XRa, XRb, XRc Q8ADDE XRa, XRb, XRc, XRd, eptn2
+ * D16MAX XRa, XRb, XRc Q8ACCE XRa, XRb, XRc, XRd, eptn2
+ * D16MIN XRa, XRb, XRc Q8ABD XRa, XRb, XRc
+ * D16SLT XRa, XRb, XRc Q8SAD XRa, XRb, XRc, XRd
+ * D16MOVZ XRa, XRb, XRc Q8AVG XRa, XRb, XRc
+ * D16MOVN XRa, XRb, XRc Q8AVGR XRa, XRb, XRc
+ * Q8MAX XRa, XRb, XRc D8SUM XRa, XRb, XRc, XRd
+ * Q8MIN XRa, XRb, XRc D8SUMC XRa, XRb, XRc, XRd
+ * Q8SLT XRa, XRb, XRc
+ * Q8SLTU XRa, XRb, XRc
+ * Q8MOVZ XRa, XRb, XRc Shift instructions
+ * Q8MOVN XRa, XRb, XRc --
+ *
+ *D32SLL XRa, XRb, XRc, XRd, sft4
+ * Bitwise instructions D32SLR XRa, XRb, XRc, XRd, sft4
+ * D32SAR XRa, XRb, XRc, XRd, sft4
+ *D32SARL XRa, XRb, XRc, sft4
+ * S32NOR XRa, XRb, XRc D32SLLV
Re: [Qemu-devel] [PATCH 3/4] target/mips: Add organizational chart of MXU ASE
On 16.10.18. 14:14, Aleksandar Markovic wrote:
From: Aleksandar Markovic
Add a comment that contains an organizational chart of MXU ASE
instructions.
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 156
1 file changed, 156 insertions(+)
Reviewed-by: Stefan Markovic
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 73d971e..4dfc360 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1490,6 +1490,162 @@ enum {
* Q16SCOP XRa, XRb, XRc, XRdS32M2I XRa, Rb
* Q16SAT XRa, XRb, XRc S32I2M XRa, Rb
*
+ *
+ * bits
+ * 05..00
+ *
+ * ┌─ 00 ─ OPC_MXU_S32MADD
+ * ├─ 01 ─ OPC_MXU_S32MADDU
+ * ├─ 10 ─
+ * │ 20..18 (25..21 must be 0)
+ * ├─ 11 ─ OPC_MXU__POOL00 ─┬─ 000 ─ OPC_MXU_S32MAX
+ * │├─ 001 ─ OPC_MXU_S32MIN
+ * │├─ 010 ─ OPC_MXU_D16MAX
+ * │├─ 011 ─ OPC_MXU_D16MIN
+ * │├─ 100 ─ OPC_MXU_Q8MAX
+ * │├─ 101 ─ OPC_MXU_Q8MIN
+ * │├─ 110 ─ OPC_MXU_Q8SLT
+ * │└─ 111 ─ OPC_MXU_Q8SLTU
+ * ├─ 000100 ─ OPC_MXU_S32MSUB
+ * ├─ 000101 ─ OPC_MXU_S32MSUBU20..18 (25..21 must be 0,
+ * │ except for Q8ADD)
+ * ├─ 000110 ─ OPC_MXU__POOL01 ─┬─ 000 ─ OPC_MXU_S32SLT
+ * │├─ 001 ─ OPC_MXU_D16SLT
+ * │├─ 010 ─ OPC_MXU_D16AVG
+ * │├─ 011 ─ OPC_MXU_D16AVGR
+ * │├─ 100 ─ OPC_MXU_Q8AVG
+ * │├─ 101 ─ OPC_MXU_Q8AVGR
+ * │└─ 111 ─ OPC_MXU_Q8ADD
+ * │
+ * │ 20..18 (25..21 must be 0)
+ * ├─ 000111 ─ OPC_MXU__POOL02 ─┬─ 000 ─ OPC_MXU_S32CPS
+ * │├─ 010 ─ OPC_MXU_D16CPS
+ * │├─ 100 ─ OPC_MXU_Q8ABD
+ * │└─ 110 ─ OPC_MXU_Q16SAT
+ * ├─ 001000 ─ OPC_MXU_D16MUL
+ * │ 25..24
+ * ├─ 001001 ─ OPC_MXU__POOL03 ─┬─ 00 ─ OPC_MXU_D16MULF
+ * │└─ 01 ─ OPC_MXU_D16MULE
+ * ├─ 001010 ─ OPC_MXU_D16MAC
+ * ├─ 001011 ─ OPC_MXU_D16MACF
+ * ├─ 001100 ─ OPC_MXU_D16MADL
+ * │ 25..24
+ * ├─ 001101 ─ OPC_MXU__POOL04 ─┬─ 00 ─ OPC_MXU_S16MAD
+ * │└─ 01 ─ OPC_MXU_S16MAD_1
+ * ├─ 001110 ─ OPC_MXU_Q16ADD
+ * ├─ 00 ─ OPC_MXU_D16MACE
+ * │ 23
+ * ├─ 01 ─ OPC_MXU__POOL05 ─┬─ 0 ─ OPC_MXU_S32LDD
+ * │└─ 1 ─ OPC_MXU_S32LDDR
+ * │
+ * │ 23
+ * ├─ 010001 ─ OPC_MXU__POOL06 ─┬─ 0 ─ OPC_MXU_S32STD
+ * │└─ 1 ─ OPC_MXU_S32STDR
+ * │
+ * │ 13..10
+ * ├─ 010010 ─ OPC_MXU__POOL07 ─┬─ ─ OPC_MXU_S32LDDV
+ * │└─ 0001 ─ OPC_MXU_S32LDDVR
+ * │
+ * │ 13..10
+ * ├─ 010011 ─ OPC_MXU__POOL08 ─┬─ ─ OPC_MXU_S32TDV
+ * │└─ 0001 ─ OPC_MXU_S32TDVR
+ * │
+ * │ 23
+ * ├─ 010100 ─ OPC_MXU__POOL09 ─┬─ 0 ─ OPC_MXU_S32LDI
+ * │└─ 1 ─ OPC_MXU_S32LDIR
+ * │
+ * │ 23
+ * ├─ 010101 ─ OPC_MXU__POOL10 ─┬─ 0 ─ OPC_MXU_S32SDI
+ * │└─ 1 ─ OPC_MXU_S32SDIR
+ * │
+ * │ 13..10
+ * ├─ 010110 ─ OPC_MXU__POOL11 ─┬─ ─ OPC_MXU_S32LDIV
+ * │└─ 0001 ─ OPC_MXU_S32LDIVR
+ * │
+ * │ 13..10
+ * ├─ 010111 ─ OPC_MXU__POOL12 ─┬─ ─ OPC_MXU_S32SDIV
+ * │└─ 0001 ─ OPC_MXU_S32SDIVR
+ * ├─ 011000 ─ OPC_MXU_D32ADD
+ * │
+ * MXU├─ 011001 ─ OPC_MXU__POOL13 ─┬─ 00 ─ OPC_MXU_D32ACC
+ * opcodes ─┤├─ 01 ─ OPC_MXU_D32ACCM
+ * │└─ 10 ─ OPC_MXU_D32ASUM
+ * ├─ 011010 ─
+ * │
+ * ├─ 011011 ─ OPC_MXU__POOL14 ─┬─ 00 ─ OPC_MXU_Q16ACC
+ * │├─ 01
Re: [Qemu-devel] [PATCH 4/4] target/mips: Add opcode values of MXU ASE
On 16.10.18. 14:14, Aleksandar Markovic wrote:
From: Aleksandar Markovic
Add opcode values for all instructions in MXU ASE.
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 276
1 file changed, 276 insertions(+)
Reviewed-by: Stefan Markovic
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 4dfc360..941b546 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1652,6 +1652,282 @@ enum {
* Programming Manual", Ingenic Semiconductor Co, Ltd., 2017
*/
+enum {
+OPC_MXU_S32MADD = 0x00,
+OPC_MXU_S32MADDU = 0x01,
+/* not assigned 0x02 */
+OPC_MXU__POOL00 = 0x03,
+OPC_MXU_S32MSUB = 0x04,
+OPC_MXU_S32MSUBU = 0x05,
+OPC_MXU__POOL01 = 0x06,
+OPC_MXU__POOL02 = 0x07,
+OPC_MXU_D16MUL = 0x08,
+OPC_MXU__POOL03 = 0x09,
+OPC_MXU_D16MAC = 0x0A,
+OPC_MXU_D16MACF = 0x0B,
+OPC_MXU_D16MADL = 0x0C,
+OPC_MXU__POOL04 = 0x0D,
+OPC_MXU_Q16ADD = 0x0E,
+OPC_MXU_D16MACE = 0x0F,
+OPC_MXU__POOL05 = 0x10,
+OPC_MXU__POOL06 = 0x11,
+OPC_MXU__POOL07 = 0x12,
+OPC_MXU__POOL08 = 0x13,
+OPC_MXU__POOL09 = 0x14,
+OPC_MXU__POOL10 = 0x15,
+OPC_MXU__POOL11 = 0x16,
+OPC_MXU__POOL12 = 0x17,
+OPC_MXU_D32ADD = 0x18,
+OPC_MXU__POOL13 = 0x19,
+/* not assigned 0x1A */
+OPC_MXU__POOL14 = 0x1B,
+OPC_MXU__POOL15 = 0x1C,
+OPC_MXU_Q8ACCE = 0x1D,
+/* not assigned 0x1E */
+/* not assigned 0x1F */
+/* not assigned 0x20 */
+/* not assigned 0x21 */
+OPC_MXU_S8LDD= 0x22,
+OPC_MXU_S8STD= 0x23,
+OPC_MXU_S8LDI= 0x24,
+OPC_MXU_S8SDI= 0x25,
+OPC_MXU__POOL16 = 0x26,
+OPC_MXU__POOL17 = 0x27,
+OPC_MXU_LXB = 0x28,
+/* not assigned 0x29 */
+OPC_MXU_S16LDD = 0x2A,
+OPC_MXU_S16STD = 0x2B,
+OPC_MXU_S16LDI = 0x2C,
+OPC_MXU_S16SDI = 0x2D,
+OPC_MXU_S32M2I = 0x2E,
+OPC_MXU_S32I2M = 0x2F,
+OPC_MXU_D32SLL = 0x30,
+OPC_MXU_D32SLR = 0x31,
+OPC_MXU_D32SARL = 0x32,
+OPC_MXU_D32SAR = 0x33,
+OPC_MXU_Q16SLL = 0x34,
+OPC_MXU_Q16SLR = 0x35,
+OPC_MXU__POOL18 = 0x36,
+OPC_MXU_Q16SAR = 0x37,
+OPC_MXU__POOL19 = 0x38,
+OPC_MXU__POOL20 = 0x39,
+OPC_MXU__POOL21 = 0x3A,
+OPC_MXU_Q16SCOP = 0x3B,
+OPC_MXU_Q8MADL = 0x3C,
+OPC_MXU_S32SFL = 0x3D,
+OPC_MXU_Q8SAD= 0x3E,
+/* not assigned 0x3F */
+};
+
+
+/*
+ * MXU pool 00
+ */
+enum {
+OPC_MXU_S32MAX = 0x00,
+OPC_MXU_S32MIN = 0x01,
+OPC_MXU_D16MAX = 0x02,
+OPC_MXU_D16MIN = 0x03,
+OPC_MXU_Q8MAX= 0x04,
+OPC_MXU_Q8MIN= 0x05,
+OPC_MXU_Q8SLT= 0x06,
+OPC_MXU_Q8SLTU = 0x07,
+};
+
+/*
+ * MXU pool 01
+ */
+enum {
+OPC_MXU_S32SLT = 0x00,
+OPC_MXU_D16SLT = 0x01,
+OPC_MXU_D16AVG = 0x02,
+OPC_MXU_D16AVGR = 0x03,
+OPC_MXU_Q8AVG= 0x04,
+OPC_MXU_Q8AVGR = 0x05,
+OPC_MXU_Q8ADD= 0x07,
+};
+
+/*
+ * MXU pool 02
+ */
+enum {
+OPC_MXU_S32CPS = 0x00,
+OPC_MXU_D16CPS = 0x02,
+OPC_MXU_Q8ABD= 0x04,
+OPC_MXU_Q16SAT = 0x06,
+};
+
+/*
+ * MXU pool 03
+ */
+enum {
+OPC_MXU_D16MULF = 0x00,
+OPC_MXU_D16MULE = 0x01,
+};
+
+/*
+ * MXU pool 04
+ */
+enum {
+OPC_MXU_S16MAD = 0x00,
+OPC_MXU_S16MAD_1 = 0x01,
+};
+
+/*
+ * MXU pool 05
+ */
+enum {
+OPC_MXU_S32LDD = 0x00,
+OPC_MXU_S32LDDR = 0x01,
+};
+
+/*
+ * MXU pool 06
+ */
+enum {
+OPC_MXU_S32STD = 0x00,
+OPC_MXU_S32STDR = 0x01,
+};
+
+/*
+ * MXU pool 07
+ */
+enum {
+OPC_MXU_S32LDDV = 0x00,
+OPC_MXU_S32LDDVR = 0x01,
+};
+
+/*
+ * MXU pool 08
+ */
+enum {
+OPC_MXU_S32TDV = 0x00,
+OPC_MXU_S32TDVR = 0x01,
+};
+
+/*
+ * MXU pool 09
+ */
+enum {
+OPC_MXU_S32LDI = 0x00,
+OPC_MXU_S32LDIR = 0x01,
+};
+
+/*
+ * MXU pool 10
+ */
+enum {
+OPC_MXU_S32SDI = 0x00,
+OPC_MXU_S32SDIR = 0x01,
+};
+
+/*
+ * MXU pool 11
+ */
+enum {
+OPC_MXU_S32LDIV = 0x00,
+OPC_MXU_S32LDIVR = 0x01,
+};
+
+/*
+ * MXU pool 12
+ */
+enum {
+OPC_MXU_S32SDIV = 0x00,
+OPC_MXU_S32SDIVR = 0x01,
+};
+
+/*
+ * MXU pool 13
+ */
+enum {
+OPC_MXU_D32ACC = 0x00,
+OPC_MXU_D32ACCM = 0x01,
+OPC_MXU_D32ASUM = 0x02,
+};
+
+/*
+ * MXU pool 14
+ */
+enum {
+OPC_MXU_Q16ACC = 0x00,
+OPC_MXU_Q16ACCM = 0x01,
+OPC_MXU_Q16ASUM = 0x02,
+};
+
+/*
+ * MXU pool 15
+ */
+enum {
+OPC_MXU_Q8ADDE = 0x00,
+OPC_MXU_D8SUM= 0x01,
+OPC_MXU_D8SUMC = 0x02,
+};
+
+/*
+ * MXU pool 16
+ */
+enum {
+OPC_MXU_S32MUL = 0x00,
+OPC_MXU_S32MULU = 0x01,
+OPC_MXU_S32EXTR = 0x02,
+OPC_MXU_S32EXTRV = 0x03,
+};
+
+/*
+ * MXU pool 17
+ */
+enum {
+OPC_MXU_D32SARW = 0x00,
+OPC_MXU_S32ALN = 0x01,
+OPC_MXU_S32ALNI = 0x02,
+OPC_MXU_S32NOR = 0x03,
+OPC_MXU_S32AND = 0x04,
+OPC_MXU_S32OR= 0x05,
+OPC_MXU_S32XOR = 0x06,
+OPC_MXU_S
Re: [Qemu-devel] [PULL v4 29/46] target/mips: Add emulation of DSP ASE for nanoMIPS - part 1
On 16.10.18. 16:00, Peter Maydell wrote:
On 23 August 2018 at 14:34, Aleksandar Markovic
wrote:
From: Stefan Markovic
Add emulation of DSP ASE instructions for nanoMIPS - part 1.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
Hi. Coverity points out a bug in this patch (CID 1395627):
---
target/mips/translate.c | 554
1 file changed, 554 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 95632dd..d3635e7 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -18061,6 +18061,554 @@ static void gen_pool32f_nanomips_insn(DisasContext
*ctx)
}
}
+static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
+ int rd, int rs, int rt)
+{
[...]
+case NM_SHRA_R_PH:
+check_dsp(ctx);
+tcg_gen_movi_tl(t0, rd >> 1);
+switch (extract32(ctx->opcode, 10, 1)) {
+case 0:
+/* SHRA_PH */
+gen_helper_shra_ph(v1_t, t0, v1_t);
+break;
+gen_store_gpr(v1_t, rt);
This gen_store_gpr() call is unreachable because it
is after the 'break'. Should the two lines be in the
other order?
Yes, those two lines should be in the other order:
+case 0:
+/* SHRA_PH */
+gen_helper_shra_ph(v1_t, t0, v1_t);
+gen_store_gpr(v1_t, rt);
+break;
+case 1:
+/* SHRA_R_PH */
+gen_helper_shra_r_ph(v1_t, t0, v1_t);
+gen_store_gpr(v1_t, rt);
+break;
+}
+break;
thanks
-- PMM
Re: [Qemu-devel] [PATCH 1/2] target/mips: Fix the title of translate.c
On 22.10.18. 13:57, Aleksandar Markovic wrote: From: Aleksandar Markovic Replace MIPS32 with MIPS, since the file covers all generations of MIPS architectures. Signed-off-by: Aleksandar Markovic --- target/mips/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Stefan Markovic diff --git a/target/mips/translate.c b/target/mips/translate.c index 74ef160..1afb105 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1,5 +1,5 @@ /* - * MIPS32 emulation for qemu: main translation routines. + * MIPS emulation for QEMU: main translation routines. * * Copyright (c) 2004-2005 Jocelyn Mayer * Copyright (c) 2006 Marius Groeger (FPU operations)
Re: [Qemu-devel] [PATCH 2/2] target/mips: Fix decoding of ALIGN and DALIGN instructions
On 22.10.18. 13:57, Aleksandar Markovic wrote:
From: Aleksandar Markovic
Opcode for ALIGN and DALIGN must be in fact ranges of opcodes, to
allow paremeter 'bp' to occupy two and three bits, respectively.
Signed-off-by: Aleksandar Markovic
---
target/mips/translate.c | 40
1 file changed, 32 insertions(+), 8 deletions(-)
Reviewed-by: Stefan Markovic
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 1afb105..e5db92e 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -463,8 +463,10 @@ enum {
OPC_WSBH = (0x02 << 6) | OPC_BSHFL,
OPC_SEB = (0x10 << 6) | OPC_BSHFL,
OPC_SEH = (0x18 << 6) | OPC_BSHFL,
-OPC_ALIGN = (0x08 << 6) | OPC_BSHFL, /* 010.bp */
-OPC_ALIGN_END = (0x0B << 6) | OPC_BSHFL, /* 010.00 to 010.11 */
+OPC_ALIGN = (0x08 << 6) | OPC_BSHFL, /* 010.bp (010.00 to 010.11) */
+OPC_ALIGN_1 = (0x09 << 6) | OPC_BSHFL,
+OPC_ALIGN_2 = (0x0A << 6) | OPC_BSHFL,
+OPC_ALIGN_3 = (0x0B << 6) | OPC_BSHFL,
OPC_BITSWAP = (0x00 << 6) | OPC_BSHFL /* 0 */
};
@@ -474,8 +476,14 @@ enum {
enum {
OPC_DSBH = (0x02 << 6) | OPC_DBSHFL,
OPC_DSHD = (0x05 << 6) | OPC_DBSHFL,
-OPC_DALIGN = (0x08 << 6) | OPC_DBSHFL, /* 01.bp */
-OPC_DALIGN_END = (0x0F << 6) | OPC_DBSHFL, /* 01.000 to 01.111 */
+OPC_DALIGN = (0x08 << 6) | OPC_DBSHFL, /* 01.bp (01.000 to 01.111) */
+OPC_DALIGN_1 = (0x09 << 6) | OPC_DBSHFL,
+OPC_DALIGN_2 = (0x0A << 6) | OPC_DBSHFL,
+OPC_DALIGN_3 = (0x0B << 6) | OPC_DBSHFL,
+OPC_DALIGN_4 = (0x0C << 6) | OPC_DBSHFL,
+OPC_DALIG
Reviewed-by: Stefan Markovic
N_5 = (0x0D << 6) | OPC_DBSHFL,
+OPC_DALIGN_6 = (0x0E << 6) | OPC_DBSHFL,
+OPC_DALIGN_7 = (0x0F << 6) | OPC_DBSHFL,
OPC_DBITSWAP = (0x00 << 6) | OPC_DBSHFL, /* 0 */
};
@@ -23957,7 +23965,9 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
op2 = MASK_BSHFL(ctx->opcode);
switch (op2) {
case OPC_ALIGN:
-case OPC_ALIGN_END:
+case OPC_ALIGN_1:
+case OPC_ALIGN_2:
+case OPC_ALIGN_3:
gen_align(ctx, 32, rd, rs, rt, sa & 3);
break;
case OPC_BITSWAP:
@@ -23983,7 +23993,13 @@ static void decode_opc_special3_r6(CPUMIPSState *env,
DisasContext *ctx)
op2 = MASK_DBSHFL(ctx->opcode);
switch (op2) {
case OPC_DALIGN:
-case OPC_DALIGN_END:
+case OPC_DALIGN_1:
+case OPC_DALIGN_2:
+case OPC_DALIGN_3:
+case OPC_DALIGN_4:
+case OPC_DALIGN_5:
+case OPC_DALIGN_6:
+case OPC_DALIGN_7:
gen_align(ctx, 64, rd, rs, rt, sa & 7);
break;
case OPC_DBITSWAP:
@@ -24843,7 +24859,9 @@ static void decode_opc_special3(CPUMIPSState *env,
DisasContext *ctx)
op2 = MASK_BSHFL(ctx->opcode);
switch (op2) {
case OPC_ALIGN:
-case OPC_ALIGN_END:
+case OPC_ALIGN_1:
+case OPC_ALIGN_2:
+case OPC_ALIGN_3:
case OPC_BITSWAP:
check_insn(ctx, ISA_MIPS32R6);
decode_opc_special3_r6(env, ctx);
@@ -24869,7 +24887,13 @@ static void decode_opc_special3(CPUMIPSState *env,
DisasContext *ctx)
op2 = MASK_DBSHFL(ctx->opcode);
switch (op2) {
case OPC_DALIGN:
-case OPC_DALIGN_END:
+case OPC_DALIGN_1:
+case OPC_DALIGN_2:
+case OPC_DALIGN_3:
+case OPC_DALIGN_4:
+case OPC_DALIGN_5:
+case OPC_DALIGN_6:
+case OPC_DALIGN_7:
case OPC_DBITSWAP:
check_insn(ctx, ISA_MIPS32R6);
decode_opc_special3_r6(env, ctx);
Re: [Qemu-devel] [PATCH v7 03/20] target/mips: Amend MXU instruction opcodes
On 24.10.18. 14:18, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Amend MXU instruction opcodes. Pool04 is actually only instruction
> OPC_MXU_S16MAD. Two cases within S16MAD are recognized by 1-bit
> subfield 'aptn1'.
>
> Signed-off-by: Aleksandar Markovic
> ---
> target/mips/translate.c | 142
> +---
> 1 file changed, 63 insertions(+), 79 deletions(-)
>
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index c1f692c..fefe9ac 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -1486,7 +1486,7 @@ enum {
>* S32OR XRa, XRb, XRc D32SARW XRa, XRb, XRc, Rb
>*Q16SLL XRa, XRb, XRc, XRd, sft4
>*Q16SLR XRa, XRb, XRc, XRd, sft4
> - * Miscelaneous instructions Q16SAR XRa, XRb, XRc, XRd, sft4
> + * Miscellaneous instructions Q16SAR XRa, XRb, XRc, XRd, sft4
>* - Q16SLLV XRa, XRb, Rb
>*Q16SLRV XRa, XRb, Rb
>* S32SFL XRa, XRb, XRc, XRd, optn2 Q16SARV XRa, XRb, Rb
> @@ -1504,7 +1504,7 @@ enum {
>*
>* ┌─ 00 ─ OPC_MXU_S32MADD
>* ├─ 01 ─ OPC_MXU_S32MADDU
> - * ├─ 10 ─
> + * ├─ 10 ─ (non-MXU OPC_MULL)
OPC_MUL instead of OPC_MULL.
Otherwise:
Reviewed-by: Stefan Markovic
>* │ 20..18
>* ├─ 11 ─ OPC_MXU__POOL00 ─┬─ 000 ─ OPC_MXU_S32MAX
>* │├─ 001 ─ OPC_MXU_S32MIN
> @@ -1536,55 +1536,53 @@ enum {
>* ├─ 001010 ─ OPC_MXU_D16MAC
>* ├─ 001011 ─ OPC_MXU_D16MACF
>* ├─ 001100 ─ OPC_MXU_D16MADL
> - * │ 25..24
> - * ├─ 001101 ─ OPC_MXU__POOL04 ─┬─ 00 ─ OPC_MXU_S16MAD
> - * │└─ 01 ─ OPC_MXU_S16MAD_1
> + * ├─ 001101 ─ OPC_MXU_S16MAD
>* ├─ 001110 ─ OPC_MXU_Q16ADD
>* ├─ 00 ─ OPC_MXU_D16MACE
>* │ 23
> - * ├─ 01 ─ OPC_MXU__POOL05 ─┬─ 0 ─ OPC_MXU_S32LDD
> + * ├─ 01 ─ OPC_MXU__POOL04 ─┬─ 0 ─ OPC_MXU_S32LDD
>* │└─ 1 ─ OPC_MXU_S32LDDR
>* │
>* │ 23
> - * ├─ 010001 ─ OPC_MXU__POOL06 ─┬─ 0 ─ OPC_MXU_S32STD
> + * ├─ 010001 ─ OPC_MXU__POOL05 ─┬─ 0 ─ OPC_MXU_S32STD
>* │└─ 1 ─ OPC_MXU_S32STDR
>* │
>* │ 13..10
> - * ├─ 010010 ─ OPC_MXU__POOL07 ─┬─ ─ OPC_MXU_S32LDDV
> + * ├─ 010010 ─ OPC_MXU__POOL06 ─┬─ ─ OPC_MXU_S32LDDV
>* │└─ 0001 ─ OPC_MXU_S32LDDVR
>* │
>* │ 13..10
> - * ├─ 010011 ─ OPC_MXU__POOL08 ─┬─ ─ OPC_MXU_S32STDV
> + * ├─ 010011 ─ OPC_MXU__POOL07 ─┬─ ─ OPC_MXU_S32STDV
>* │└─ 0001 ─ OPC_MXU_S32STDVR
>* │
>* │ 23
> - * ├─ 010100 ─ OPC_MXU__POOL09 ─┬─ 0 ─ OPC_MXU_S32LDI
> + * ├─ 010100 ─ OPC_MXU__POOL08 ─┬─ 0 ─ OPC_MXU_S32LDI
>* │└─ 1 ─ OPC_MXU_S32LDIR
>* │
>* │ 23
> - * ├─ 010101 ─ OPC_MXU__POOL10 ─┬─ 0 ─ OPC_MXU_S32SDI
> + * ├─ 010101 ─ OPC_MXU__POOL09 ─┬─ 0 ─ OPC_MXU_S32SDI
>* │└─ 1 ─ OPC_MXU_S32SDIR
>* │
>* │ 13..10
> - * ├─ 010110 ─ OPC_MXU__POOL11 ─┬─ ─ OPC_MXU_S32LDIV
> + * ├─ 010110 ─ OPC_MXU__POOL10 ─┬─ ─ OPC_MXU_S32LDIV
>* │└─ 0001 ─ OPC_MXU_S32LDIVR
>* │
>* │ 13..10
> - * ├─ 010111 ─ OPC_MXU__POOL12 ─┬─ ─ OPC_MXU_S32SDIV
> + * ├─ 010111 ─ OPC_MXU__POOL11 ─┬─ ─ OPC_MXU_S32SDIV
>* │└─ 0001 ─ OPC_MXU_S32SDIVR
>* ├─ 011000 ─ OPC_MXU_D32ADD
>* │ 23..22
> - * MXU├─ 011001 ─ OPC_MXU__POOL13 ─┬─ 00 ─ OPC_MXU_D32ACC
> + * MXU├─ 011001 ─ OPC_MXU__POOL12 ─┬─ 00 ─ OPC_MXU_D32ACC
>* opcodes ─┤├─ 01 ─ OPC_MXU_D32ACCM
>* │└─ 10 ─ OPC_MXU_D32ASUM
>*
Re: [Qemu-devel] [PATCH v2 1/3] target/mips: Add nanoMIPS CRC32 instruction pool
On 25.10.18. 10:49, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Add nanoMIPS CRC32 instruction pool.
>
> Signed-off-by: Aleksandar Markovic
> ---
> target/mips/translate.c | 10 ++
> 1 file changed, 10 insertions(+)
Reviewed-by: Stefan Markovic
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index c44a751..4338b9a 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -17475,6 +17475,16 @@ enum {
> NM_SOV = 0x7a,
> };
>
> +/* CRC32 instruction pool */
> +enum {
> +NM_CRC32B = 0x00,
> +NM_CRC32H = 0x01,
> +NM_CRC32W = 0x02,
> +NM_CRC32CB = 0x04,
> +NM_CRC32CH = 0x05,
> +NM_CRC32CW = 0x06,
> +};
> +
> /* POOL32A5 instruction pool */
> enum {
> NM_CMP_EQ_PH= 0x00,
Re: [Qemu-devel] [PATCH v2 2/3] target/mips: Implement emulation of nanoMIPS EVA instructions
On 25.10.18. 10:49, Aleksandar Markovic wrote:
> From: Dimitrije Nikolic
>
> Implement emulation of nanoMIPS EVA instructions. They are all
> part of P.LS.E0 instruction pool, or one of its subpools.
>
> Signed-off-by: Dimitrije Nikolic
> Signed-off-by: Aleksandar Markovic
> ---
> target/mips/translate.c | 128
>
> 1 file changed, 128 insertions(+)
>
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index 4338b9a..60964c9 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -2989,6 +2989,35 @@ static inline void check_nms(DisasContext *ctx)
> }
> }
>
> +/*
> + * This code generates a "reserved instruction" exception if the
> + * Config5 NMS bit is set, and Config1 DL, Config1 IL, Config2 SL,
> + * Config2 TL, and Config5 L2C are unset.
> + */
> +static inline void check_nms_dl_il_sl_tl_l2c(DisasContext *ctx)
> +{
> +if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_NMS)) &&
> +!(ctx->CP0_Config1 & (1 << CP0C1_DL)) &&
> +!(ctx->CP0_Config1 & (1 << CP0C1_IL)) &&
> +!(ctx->CP0_Config2 & (1 << CP0C2_SL)) &&
> +!(ctx->CP0_Config2 & (1 << CP0C2_TL)) &&
> +!(ctx->CP0_Config5 & (1 << CP0C5_L2C)))
> +{
> +generate_exception_end(ctx, EXCP_RI);
> +}
> +}
> +
> +/*
> + * This code generates a "reserved instruction" exception if the
> + * Config5 EVA bit is NOT set.
> + */
> +static inline void check_eva(DisasContext *ctx)
> +{
> +if (!unlikely(ctx->CP0_Config5 & (1 << CP0C5_EVA))) {
Proper condition would be:
unlikely(!(ctx->CP0_Config5 & (1 << CP0C5_EVA
Otherwise:
Reviewed-by: Stefan Markovic
> +generate_exception_end(ctx, EXCP_RI);
> +}
> +}
> +
>
> /* Define small wrappers for gen_load_fpr* so that we have a uniform
> calling interface for 32 and 64-bit FPRs. No sense in changing
> @@ -21218,6 +21247,105 @@ static int decode_nanomips_32_48_opc(CPUMIPSState
> *env, DisasContext *ctx)
> break;
> }
> break;
> +case NM_P_LS_E0:
> +switch (extract32(ctx->opcode, 11, 4)) {
> +case NM_LBE:
> +check_eva(ctx);
> +check_cp0_enabled(ctx);
> +gen_ld(ctx, OPC_LBE, rt, rs, s);
> +break;
> +case NM_SBE:
> +check_eva(ctx);
> +check_cp0_enabled(ctx);
> +gen_st(ctx, OPC_SBE, rt, rs, s);
> +break;
> +case NM_LBUE:
> +check_eva(ctx);
> +check_cp0_enabled(ctx);
> +gen_ld(ctx, OPC_LBUE, rt, rs, s);
> +break;
> +case NM_P_PREFE:
> +if (rt == 31) {
> +/* case NM_SYNCIE */
> +check_eva(ctx);
> +check_cp0_enabled(ctx);
> +/* Break the TB to be able to sync copied
> instructions
> + immediately */
> +ctx->base.is_jmp = DISAS_STOP;
> +} else {
> +/* case NM_PREFE */
> +check_eva(ctx);
> +check_cp0_enabled(ctx);
> +/* Treat as NOP. */
> +}
> +break;
> +case NM_LHE:
> +check_eva(ctx);
> +check_cp0_enabled(ctx);
> +gen_ld(ctx, OPC_LHE, rt, rs, s);
> +break;
> +case NM_SHE:
> +check_eva(ctx);
> +check_cp0_enabled(ctx);
> +gen_st(ctx, OPC_SHE, rt, rs, s);
> +break;
> +case NM_LHUE:
> +check_eva(ctx);
> +check_cp0_enabled(ctx);
> +gen_ld(ctx, OPC_LHUE, rt, rs, s);
> +break;
> +case NM_CACHEE:
> +check_nms_dl_il_sl_tl_l2c(ctx);
> +gen_cache_operation(ctx, rt, rs, s);
> +break;
> +case NM_LWE:
> +check_eva(ctx);
> +check_cp0_enabled(ctx);
> +gen_ld(ctx, OPC_LWE, rt, rs, s);
> +break;
> +
Re: [Qemu-devel] [PATCH v7 04/20] target/mips: Add and integrate MXU decoding engine placeholder
On 24.10.18. 14:18, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Provide the placeholder and add the invocation logic for MXU
> decoding engine.
>
> Signed-off-by: Aleksandar Markovic
> ---
> target/mips/translate.c | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index fefe9ac..128cabe 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -23844,6 +23844,12 @@ static void decode_opc_special(CPUMIPSState *env,
> DisasContext *ctx)
> }
> }
>
> +static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
> +{
> +MIPS_INVAL("decode_opc_mxu");
> +generate_exception_end(ctx, EXCP_RI);
> +}
> +
> static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
> {
> int rs, rt, rd;
> @@ -26087,6 +26093,8 @@ static void decode_opc(CPUMIPSState *env,
> DisasContext *ctx)
> case OPC_SPECIAL2:
> if ((ctx->insn_flags & INSN_R5900) && (ctx->insn_flags & ASE_MMI)) {
> decode_tx79_mmi(env, ctx);
> +} else if (ctx->insn_flags & ASE_MXU) {
> +decode_opc_mxu(env, ctx);
Is the best way to implement this to include processing of MUL, CLZ,
CLO, SDDP instructions into decode_opc_mxu as their encodings aren't
overlaid by MXU instructions
considering MIPS SPECIAL2 instruction pool and MXU Instruction Set?
> } else {
> decode_opc_special2_legacy(env, ctx);
> }
Re: [Qemu-devel] [PATCH v7 05/20] target/mips: Add MXU decoding engine
On 24.10.18. 14:18, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Add MXU decoding engine: add handlers for all instruction pools,
> and main decode handler. The handlers, for now, for the purpose
> of this patch, contain only sceleton in the form of a single
> switch statement.
>
> Signed-off-by: Aleksandar Markovic
> ---
> target/mips/translate.c | 1143
> ++-
> 1 file changed, 1141 insertions(+), 2 deletions(-)
>
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index 128cabe..ed72b32 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -23844,12 +23844,1151 @@ static void decode_opc_special(CPUMIPSState *env,
> DisasContext *ctx)
> }
> }
>
> +/*
> + *
> + * Decode MXU pool00
> + *
> + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
> + * +---+-+-+---+---+---+---+
> + * | SPECIAL2 |0 0 0 0 0|x x x| XRc | XRb | XRa |MXU__POOL00|
> + * +---+-+-+---+---+---+---+
> + *
> + */
> +static void decode_opc_mxu__pool00(CPUMIPSState *env, DisasContext *ctx)
> +{
> +uint32_t opcode = extract32(ctx->opcode, 18, 3);
> +
> +switch (opcode) {
> +case OPC_MXU_S32MAX:
> +/* TODO: Implement emulation of S32MAX instruction. */
> +MIPS_INVAL("OPC_MXU_S32MAX");
> +generate_exception_end(ctx, EXCP_RI);
> +break;
> +case OPC_MXU_S32MIN:
> +/* TODO: Implement emulation of S32MIN instruction. */
> +MIPS_INVAL("OPC_MXU_S32MIN");
> +generate_exception_end(ctx, EXCP_RI);
> +break;
> +case OPC_MXU_D16MAX:
> +/* TODO: Implement emulation of D16MAX instruction. */
> +MIPS_INVAL("OPC_MXU_D16MAX");
> +generate_exception_end(ctx, EXCP_RI);
> +break;
> +case OPC_MXU_D16MIN:
> +/* TODO: Implement emulation of D16MIN instruction. */
> +MIPS_INVAL("OPC_MXU_D16MIN");
> +generate_exception_end(ctx, EXCP_RI);
> +break;
> +case OPC_MXU_Q8MAX:
> +/* TODO: Implement emulation of Q8MAX instruction. */
> +MIPS_INVAL("OPC_MXU_Q8MAX");
> +generate_exception_end(ctx, EXCP_RI);
> +break;
> +case OPC_MXU_Q8MIN:
> +/* TODO: Implement emulation of Q8MIN instruction. */
> +MIPS_INVAL("OPC_MXU_Q8MIN");
> +generate_exception_end(ctx, EXCP_RI);
> +break;
> +case OPC_MXU_Q8SLT:
> +/* TODO: Implement emulation of Q8SLT instruction. */
> +MIPS_INVAL("OPC_MXU_Q8SLT");
> +generate_exception_end(ctx, EXCP_RI);
> +break;
> +case OPC_MXU_Q8SLTU:
> +/* TODO: Implement emulation of Q8SLTU instruction. */
> +MIPS_INVAL("OPC_MXU_Q8SLTU");
> +generate_exception_end(ctx, EXCP_RI);
> +break;
> +default:
> +MIPS_INVAL("decode_opc_mxu");
> +generate_exception_end(ctx, EXCP_RI);
> +break;
> +}
> +}
> +
> +/*
> + *
> + * Decode MXU pool01
> + *
> + * S32SLT, D16SLT, D16AVG, D16AVGR, Q8AVG, Q8AVGR:
> + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
> + * +---+-+-+---+---+---+---+
> + * | SPECIAL2 |0 0 0 0 0|x x x| XRc | XRb | XRa |MXU__POOL01|
> + * +---+-+-+---+---+---+---+
> + *
> + * Q8MADD:
Q8ADD, instead of Q8MADD.
Otherwise:
Reviewed-by: Stefan Markovic
> + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
> + * +---+---+-+-+---+---+---+---+
> + * | SPECIAL2 |en2|0 0 0|x x x| XRc | XRb | XRa |MXU__POOL01|
> + * +---+---+-+-+---+---+---+---+
> + *
> + */
> +static void decode_opc_mxu__pool01(CPUMIPSState *env, DisasContext *ctx)
> +{
> +uint32_t opcode = extract32(ctx->opcode, 18, 3);
> +
> +switch (opcode) {
> +case OPC_MXU_S32SLT:
> +/* TODO: Implement emulation of S32SLT instruction. */
> +MIPS_INVAL("OPC_MXU_S32SLT");
> +generate_exception_end(ctx, EXCP_RI);
> +break;
> +case OPC_MXU_D16SLT:
> +/* TODO: Implement emulation of D16SLT instruction. */
> +MIPS_INVAL("OPC_MXU_D16SLT");
> +generate_exception_end(ctx, EXCP_RI);
> +break;
> +case OPC_MXU_D16AVG:
> +/* TODO: Implement emulation of D16AVG instruction. */
> +MIPS_INVAL("OPC_MXU_D
Re: [Qemu-devel] [PATCH v7 06/20] target/mips: Add bit encoding for MXU accumulate add/sub 1-bit pattern 'aptn1'
On 24.10.18. 14:18, Aleksandar Markovic wrote: > From: Aleksandar Markovic > > Add bit encoding for MXU accumulate add/subtract 1-bit pattern > 'aptn1'. > > Signed-off-by: Aleksandar Markovic > --- > target/mips/translate.c | 6 ++ > 1 file changed, 6 insertions(+) Reviewed-by: Stefan Markovic > diff --git a/target/mips/translate.c b/target/mips/translate.c > index ed72b32..f274ac1 100644 > --- a/target/mips/translate.c > +++ b/target/mips/translate.c > @@ -23844,6 +23844,12 @@ static void decode_opc_special(CPUMIPSState *env, > DisasContext *ctx) > } > } > > + > +/* MXU accumulate add/subtract 1-bit pattern 'aptn1' */ > +#define MXU_APTN1_A0 > +#define MXU_APTN1_S1 > + > + > /* >* >* Decode MXU pool00
Re: [Qemu-devel] [PATCH v7 08/20] target/mips: Add bit encoding for MXU execute add/sub pattern 'eptn2'
On 24.10.18. 14:18, Aleksandar Markovic wrote: > From: Aleksandar Markovic > > Add bit encoding for MXU execute 2-bit add/subtract pattern 'eptn2'. > > Signed-off-by: Aleksandar Markovic > --- > target/mips/translate.c | 6 ++ > 1 file changed, 6 insertions(+) Reviewed-by: Stefan Markovic > diff --git a/target/mips/translate.c b/target/mips/translate.c > index 97fb2e0..665a584 100644 > --- a/target/mips/translate.c > +++ b/target/mips/translate.c > @@ -23855,6 +23855,12 @@ static void decode_opc_special(CPUMIPSState *env, > DisasContext *ctx) > #define MXU_APTN2_SA2 > #define MXU_APTN2_SS3 > > +/* MXU execute add/subtract 2-bit pattern 'eptn2' */ > +#define MXU_EPTN2_AA0 > +#define MXU_EPTN2_AS1 > +#define MXU_EPTN2_SA2 > +#define MXU_EPTN2_SS3 > + > > /* >*
Re: [Qemu-devel] [PATCH v7 13/20] target/mips: Move MUL, S32M2I, S32I2M handling out of main MXU switch
On 24.10.18. 14:18, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Move MUL, S32M2I, S32I2M handling out of switch. These are all
> instructions that do not depend on MXU_EN flag of MXU_CR.
>
> Signed-off-by: Aleksandar Markovic
> ---
> target/mips/translate.c | 41 +++--
> 1 file changed, 23 insertions(+), 18 deletions(-)
See my comment for patch 04/20.
CLZ, CLO, SDDP are missing?
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index c8c71c4..111affb 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -24859,6 +24859,29 @@ static void decode_opc_mxu(CPUMIPSState *env,
> DisasContext *ctx)
> {
> uint32_t opcode = extract32(ctx->opcode, 0, 6);
>
> +if (opcode == OPC__MXU_MUL) {
> +uint32_t rs, rt, rd, op1;
> +
> +rs = extract32(ctx->opcode, 21, 5);
> +rt = extract32(ctx->opcode, 16, 5);
> +rd = extract32(ctx->opcode, 11, 5);
> +op1 = MASK_SPECIAL2(ctx->opcode);
> +
> +gen_arith(ctx, op1, rd, rs, rt);
> +
> +return;
> +}
> +
> +if (opcode == OPC_MXU_S32M2I) {
> +gen_mxu_s32m2i(ctx);
> +return;
> +}
> +
> +if (opcode == OPC_MXU_S32I2M) {
> +gen_mxu_s32i2m(ctx);
> +return;
> +}
> +
> switch (opcode) {
> case OPC_MXU_S32MADD:
> /* TODO: Implement emulation of S32MADD instruction. */
> @@ -24870,18 +24893,6 @@ static void decode_opc_mxu(CPUMIPSState *env,
> DisasContext *ctx)
> MIPS_INVAL("OPC_MXU_S32MADDU");
> generate_exception_end(ctx, EXCP_RI);
> break;
> -case OPC__MXU_MUL: /* 0x2 - unused in MXU specs */
> -{
> -uint32_t rs, rt, rd, op1;
> -
> -rs = extract32(ctx->opcode, 21, 5);
> -rt = extract32(ctx->opcode, 16, 5);
> -rd = extract32(ctx->opcode, 11, 5);
> -op1 = MASK_SPECIAL2(ctx->opcode);
> -
> -gen_arith(ctx, op1, rd, rs, rt);
> -}
> -break;
> case OPC_MXU__POOL00:
> decode_opc_mxu__pool00(env, ctx);
> break;
> @@ -25033,12 +25044,6 @@ static void decode_opc_mxu(CPUMIPSState *env,
> DisasContext *ctx)
> MIPS_INVAL("OPC_MXU_S16SDI");
> generate_exception_end(ctx, EXCP_RI);
> break;
> -case OPC_MXU_S32M2I:
> -gen_mxu_s32m2i(ctx);
> -break;
> -case OPC_MXU_S32I2M:
> -gen_mxu_s32i2m(ctx);
> -break;
> case OPC_MXU_D32SLL:
> /* TODO: Implement emulation of D32SLL instruction. */
> MIPS_INVAL("OPC_MXU_D32SLL");
Re: [Qemu-devel] [PATCH v7 19/20] target/mips: Move MXU_EN check one level higher
On 24.10.18. 14:18, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Move MXU_EN check to the main MXU decoding function, to avoid code
> repetition.
>
> Signed-off-by: Aleksandar Markovic
> ---
> target/mips/translate.c | 509
> ++--
> 1 file changed, 238 insertions(+), 271 deletions(-)
Reviewed-by: Stefan Markovic
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index 61c1662..3620ae5 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -23960,23 +23960,16 @@ static void gen_mxu_s32m2i(DisasContext *ctx)
> static void gen_mxu_s8ldd(DisasContext *ctx)
> {
> TCGv t0, t1;
> -TCGLabel *l0;
> uint32_t XRa, Rb, s8, optn3;
>
> t0 = tcg_temp_new();
> t1 = tcg_temp_new();
>
> -l0 = gen_new_label();
> -
> XRa = extract32(ctx->opcode, 6, 4);
> s8 = extract32(ctx->opcode, 10, 8);
> optn3 = extract32(ctx->opcode, 18, 3);
> Rb = extract32(ctx->opcode, 21, 5);
>
> -gen_load_mxu_cr(t0);
> -tcg_gen_andi_tl(t0, t0, MXU_CR_MXU_EN);
> -tcg_gen_brcondi_tl(TCG_COND_NE, t0, MXU_CR_MXU_EN, l0);
> -
> gen_load_gpr(t0, Rb);
> tcg_gen_addi_tl(t0, t0, (int8_t)s8);
>
> @@ -24034,8 +24027,6 @@ static void gen_mxu_s8ldd(DisasContext *ctx)
>
> gen_store_mxu_gpr(t0, XRa);
>
> -gen_set_label(l0);
> -
> tcg_temp_free(t0);
> tcg_temp_free(t1);
> }
> @@ -24046,7 +24037,6 @@ static void gen_mxu_s8ldd(DisasContext *ctx)
> static void gen_mxu_d16mul(DisasContext *ctx)
> {
> TCGv t0, t1, t2, t3;
> -TCGLabel *l0;
> uint32_t XRa, XRb, XRc, XRd, optn2;
>
> t0 = tcg_temp_new();
> @@ -24054,18 +24044,12 @@ static void gen_mxu_d16mul(DisasContext *ctx)
> t2 = tcg_temp_new();
> t3 = tcg_temp_new();
>
> -l0 = gen_new_label();
> -
> XRa = extract32(ctx->opcode, 6, 4);
> XRb = extract32(ctx->opcode, 10, 4);
> XRc = extract32(ctx->opcode, 14, 4);
> XRd = extract32(ctx->opcode, 18, 4);
> optn2 = extract32(ctx->opcode, 22, 2);
>
> -gen_load_mxu_cr(t0);
> -tcg_gen_andi_tl(t0, t0, MXU_CR_MXU_EN);
> -tcg_gen_brcondi_tl(TCG_COND_NE, t0, MXU_CR_MXU_EN, l0);
> -
> gen_load_mxu_gpr(t1, XRb);
> tcg_gen_sextract_tl(t0, t1, 0, 16);
> tcg_gen_sextract_tl(t1, t1, 16, 16);
> @@ -24094,8 +24078,6 @@ static void gen_mxu_d16mul(DisasContext *ctx)
> gen_store_mxu_gpr(t3, XRa);
> gen_store_mxu_gpr(t2, XRd);
>
> -gen_set_label(l0);
> -
> tcg_temp_free(t0);
> tcg_temp_free(t1);
> tcg_temp_free(t2);
> @@ -24109,7 +24091,6 @@ static void gen_mxu_d16mul(DisasContext *ctx)
> static void gen_mxu_d16mac(DisasContext *ctx)
> {
> TCGv t0, t1, t2, t3;
> -TCGLabel *l0;
> uint32_t XRa, XRb, XRc, XRd, optn2, aptn2;
>
> t0 = tcg_temp_new();
> @@ -24117,8 +24098,6 @@ static void gen_mxu_d16mac(DisasContext *ctx)
> t2 = tcg_temp_new();
> t3 = tcg_temp_new();
>
> -l0 = gen_new_label();
> -
> XRa = extract32(ctx->opcode, 6, 4);
> XRb = extract32(ctx->opcode, 10, 4);
> XRc = extract32(ctx->opcode, 14, 4);
> @@ -24126,10 +24105,6 @@ static void gen_mxu_d16mac(DisasContext *ctx)
> optn2 = extract32(ctx->opcode, 22, 2);
> aptn2 = extract32(ctx->opcode, 24, 2);
>
> -gen_load_mxu_cr(t0);
> -tcg_gen_andi_tl(t0, t0, MXU_CR_MXU_EN);
> -tcg_gen_brcondi_tl(TCG_COND_NE, t0, MXU_CR_MXU_EN, l0);
> -
> gen_load_mxu_gpr(t1, XRb);
> tcg_gen_sextract_tl(t0, t1, 0, 16);
> tcg_gen_sextract_tl(t1, t1, 16, 16);
> @@ -24180,8 +24155,6 @@ static void gen_mxu_d16mac(DisasContext *ctx)
> gen_store_mxu_gpr(t3, XRa);
> gen_store_mxu_gpr(t2, XRd);
>
> -gen_set_label(l0);
> -
> tcg_temp_free(t0);
> tcg_temp_free(t1);
> tcg_temp_free(t2);
> @@ -24195,7 +24168,6 @@ static void gen_mxu_d16mac(DisasContext *ctx)
> static void gen_mxu_q8mul_q8mulsu(DisasContext *ctx)
> {
> TCGv t0, t1, t2, t3, t4, t5, t6, t7;
> -TCGLabel *l0;
> uint32_t XRa, XRb, XRc, XRd, sel;
>
> t0 = tcg_temp_new();
> @@ -24207,18 +24179,12 @@ static void gen_mxu_q8mul_q8mulsu(DisasContext *ctx)
> t6 = tcg_temp_new();
> t7 = tcg_temp_new();
>
> -l0 = gen_new_label();
> -
> XRa = extract32(ctx->opcode, 6, 4);
> XRb = extract32(ctx->opcode, 10, 4);
> XRc = extract32(ctx->opcode, 14, 4);
> XRd = extract32(ct
Re: [Qemu-devel] [PATCH v7 20/20] target/mips: Amend MXU ASE overview note
On 24.10.18. 14:18, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Add prefix, suffix, operation descriptions, and other corrections
> and amendments to the comment that describes MXU ASE.
>
> Signed-off-by: Aleksandar Markovic
> ---
> target/mips/translate.c | 84
> +++--
> 1 file changed, 74 insertions(+), 10 deletions(-)
Reviewed-by: Stefan Markovic
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index 3620ae5..9bd5f27 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -1410,25 +1410,89 @@ enum {
>* MXU unit contains 17 registers called X0-X16. X0 is always zero, and X16
> is
>* the control register.
>*
> - * The notation used in MXU assembler mnemonics:
> + * The notation used in MXU assembler mnemonics
> + *
> + *
> + * Registers:
>*
>* XRa, XRb, XRc, XRd - MXU registers
>* Rb, Rc, Rd, Rs, Rt - general purpose MIPS registers
> - * s12- a subfield of an instruction code
> - * strd2 - a subfield of an instruction code
> - * eptn2 - a subfield of an instruction code
> - * eptn3 - a subfield of an instruction code
> - * optn2 - a subfield of an instruction code
> - * optn3 - a subfield of an instruction code
> - * sft4 - a subfield of an instruction code
> + *
> + * Subfields:
> + *
> + * aptn1 - 1-bit accumulate add/subtract pattern
> + * aptn2 - 2-bit accumulate add/subtract pattern
> + * eptn2 - 2-bit execute add/subtract pattern
> + * optn2 - 2-bit operand pattern
> + * optn3 - 3-bit operand pattern
> + * sft4 - 4-bit shift amount
> + * strd2 - 2-bit stride amount
> + *
> + * Prefixes:
> + *
> + *
> + * S 32
> + * D 16
> + * Q 8
> + *
> + * Suffixes:
> + *
> + * E - Expand results
> + * F - Fixed point multiplication
> + * L - Low part result
> + * R - Doing rounding
> + * V - Variable instead of immediate
> + * W - Combine above L and V
> + *
> + * Operations:
> + *
> + * ADD - Add or subtract
> + * ADDC - Add with carry-in
> + * ACC - Accumulate
> + * ASUM - Sum together then accumulate (add or subtract)
> + * ASUMC - Sum together then accumulate (add or subtract) with carry-in
> + * AVG - Average between 2 operands
> + * ABD - Absolute difference
> + * ALN - Align data
> + * AND - Logical bitwise 'and' operation
> + * CPS - Copy sign
> + * EXTR - Extract bits
> + * I2M - Move from GPR register to MXU register
> + * LDD - Load data from memory to XRF
> + * LDI - Load data from memory to XRF (and increase the address base)
> + * LUI - Load unsigned immediate
> + * MUL - Multiply
> + * MULU - Unsigned multiply
> + * MADD - 64-bit operand add 32x32 product
> + * MSUB - 64-bit operand subtract 32x32 product
> + * MAC - Multiply and accumulate (add or subtract)
> + * MAD - Multiply and add or subtract
> + * MAX - Maximum between 2 operands
> + * MIN - Minimum between 2 operands
> + * M2I - Move from MXU register to GPR register
> + * MOVZ - Move if zero
> + * MOVN - Move if non-zero
> + * NOR - Logical bitwise 'nor' operation
> + * OR- Logical bitwise 'or' operation
> + * STD - Store data from XRF to memory
> + * SDI - Store data from XRF to memory (and increase the address base)
> + * SLT - Set of less than comparison
> + * SAD - Sum of absolute differences
> + * SLL - Logical shift left
> + * SLR - Logical shift right
> + * SAR - Arithmetic shift right
> + * SAT - Saturation
> + * SFL - Shuffle
> + * SCOP - Calculate x’s scope (-1, means x<0; 0, means x==0; 1, means x>0)
> + * XOR - Logical bitwise 'exclusive or' operation
>*
>* Load/Store instructions Multiplication instructions
>* --- ---
>*
>* S32LDD XRa, Rb, s12 S32MADD XRa, XRd, Rs, Rt
>* S32STD XRa, Rb, s12 S32MADDU XRa, XRd, Rs, Rt
> - * S32LDDV XRa, Rb, rc, strd2S32SUB XRa, XRd, Rs, Rt
> - * S32STDV XRa, Rb, rc, strd2S32SUBU XRa, XRd, Rs, Rt
> + * S32LDDV XRa, Rb, rc, strd2S32MSUB XRa, XRd, Rs, Rt
> + * S32STDV XRa, Rb, rc, strd2S32MSUBU XRa, XRd, Rs, Rt
>* S32LDI XRa, Rb, s12 S32MUL XRa, XRd, Rs, Rt
>* S32SDI XRa, Rb, s12 S32MULU XRa, XRd, Rs, Rt
>* S32LDIV XRa, Rb, rc, strd2D16MUL XRa, XRb, XRc, XRd, optn2
[Qemu-devel] [PATCH 0/6] target/mips: Add support for prctl() PR_GET_FP_MODE and PR_SET_FP_MODE
From: Stefan Markovic This series includes support for prctl() PR_GET_FP_MODE and PR_SET_FP_MODE. This requires extracting MIPS.abiflags section from ELF file and fp_abi value handling. Stefan Markovic (6): Define MIPS_ABI_FP_UNKNOWN macro Extend image_info struct with MIPS specific fp_abi and interp_fp_abi fields Extract MIPS abiflags from ELF file Read and set FP ABI value from MIPS abiflags Determine the desired FPU mode Add prctl() PR_SET_FP_MODE and PR_GET_FP_MODE implementations include/elf.h | 2 + linux-user/elfload.c | 37 +++ linux-user/mips/cpu_loop.c | 75 ++ linux-user/mips/target_syscall.h | 2 + linux-user/mips64/target_syscall.h | 2 + linux-user/qemu.h | 4 ++ linux-user/syscall.c | 62 +-- 7 files changed, 180 insertions(+), 4 deletions(-) -- 1.9.1
[Qemu-devel] [PATCH 2/6] Extend image_info struct with MIPS specific fp_abi and interp_fp_abi fields
From: Stefan Markovic
Signed-off-by: Stefan Markovic
---
linux-user/qemu.h | 4
1 file changed, 4 insertions(+)
diff --git a/linux-user/qemu.h b/linux-user/qemu.h
index 1beb6a2..a752c1c 100644
--- a/linux-user/qemu.h
+++ b/linux-user/qemu.h
@@ -61,6 +61,10 @@ struct image_info {
abi_ulong interpreter_loadmap_addr;
abi_ulong interpreter_pt_dynamic_addr;
struct image_info *other_info;
+#ifdef TARGET_MIPS
+int fp_abi;
+int interp_fp_abi;
+#endif
};
#ifdef TARGET_I386
--
1.9.1
[Qemu-devel] [PATCH 5/6] Determine the desired FPU mode
From: Stefan Markovic
Floating-point mode is calculated from MIPS.abiflags FP ABI value
(based on kernel implementation). Illegal combinations are rejected.
Signed-off-by: Stefan Markovic
---
linux-user/mips/cpu_loop.c | 75 ++
1 file changed, 75 insertions(+)
diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c
index c9c20cf..fd96e46 100644
--- a/linux-user/mips/cpu_loop.c
+++ b/linux-user/mips/cpu_loop.c
@@ -740,6 +740,34 @@ void target_cpu_copy_regs(CPUArchState *env, struct
target_pt_regs *regs)
struct image_info *info = ts->info;
int i;
+struct mode_req {
+bool single;
+bool soft;
+bool fr1;
+bool frdefault;
+bool fre;
+};
+
+static const struct mode_req fpu_reqs[] = {
+[MIPS_ABI_FP_ANY]= { true, true, true, true, true },
+[MIPS_ABI_FP_DOUBLE] = { false, false, false, true, true },
+[MIPS_ABI_FP_SINGLE] = { true, false, false, false, false },
+[MIPS_ABI_FP_SOFT] = { false, true, false, false, false },
+[MIPS_ABI_FP_OLD_64] = { false, false, false, false, false },
+[MIPS_ABI_FP_XX] = { false, false, true, true, true },
+[MIPS_ABI_FP_64] = { false, false, true, false, false },
+[MIPS_ABI_FP_64A]= { false, false, true, false, true }
+};
+
+/*
+ * Mode requirements when .MIPS.abiflags is not present in the ELF.
+ * Not present means that everything is acceptable except FR1.
+ */
+static struct mode_req none_req = { true, true, false, true, true };
+
+struct mode_req prog_req;
+struct mode_req interp_req;
+
for(i = 0; i < 32; i++) {
env->active_tc.gpr[i] = regs->regs[i];
}
@@ -747,6 +775,53 @@ void target_cpu_copy_regs(CPUArchState *env, struct
target_pt_regs *regs)
if (regs->cp0_epc & 1) {
env->hflags |= MIPS_HFLAG_M16;
}
+
+#ifdef TARGET_ABI_MIPSO32
+# define MAX_FP_ABI MIPS_ABI_FP_64A
+#else
+# define MAX_FP_ABI MIPS_ABI_FP_SOFT
+#endif
+ if ((info->fp_abi > MAX_FP_ABI && info->fp_abi != MIPS_ABI_FP_UNKNOWN)
+|| (info->interp_fp_abi > MAX_FP_ABI &&
+info->interp_fp_abi != MIPS_ABI_FP_UNKNOWN)) {
+fprintf(stderr, "qemu: Program and interpreter have "
+"unexpected FPU modes\n");
+exit(137);
+}
+
+prog_req = (info->fp_abi == MIPS_ABI_FP_UNKNOWN) ? none_req
+: fpu_reqs[info->fp_abi];
+interp_req = (info->interp_fp_abi == MIPS_ABI_FP_UNKNOWN) ? none_req
+: fpu_reqs[info->interp_fp_abi];
+
+prog_req.single &= interp_req.single;
+prog_req.soft &= interp_req.soft;
+prog_req.fr1 &= interp_req.fr1;
+prog_req.frdefault &= interp_req.frdefault;
+prog_req.fre &= interp_req.fre;
+
+bool cpu_has_mips_r2_r6 = env->insn_flags & ISA_MIPS32R2 ||
+ env->insn_flags & ISA_MIPS64R2 ||
+ env->insn_flags & ISA_MIPS32R6 ||
+ env->insn_flags & ISA_MIPS64R6;
+
+if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) {
+env->CP0_Config5 |= (1 << CP0C5_FRE);
+if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
+env->hflags |= MIPS_HFLAG_FRE;
+}
+} else if ((prog_req.fr1 && prog_req.frdefault) ||
+ (prog_req.single && !prog_req.frdefault)) {
+if ((env->active_fpu.fcr0 & (1 << FCR0_F64)
+&& cpu_has_mips_r2_r6) || prog_req.fr1) {
+env->CP0_Status |= (1 << CP0St_FR);
+env->hflags |= MIPS_HFLAG_F64;
+}
+} else if (!prog_req.fre && !prog_req.frdefault &&
+ !prog_req.fr1 && !prog_req.single && !prog_req.soft) {
+exit(137);
+}
+
if (env->insn_flags & ISA_NANOMIPS32) {
return;
}
--
1.9.1
[Qemu-devel] [PATCH 4/6] Read and set FP ABI value from MIPS abiflags
From: Stefan Markovic Signed-off-by: Stefan Markovic --- linux-user/elfload.c | 4 1 file changed, 4 insertions(+) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 5881233..5bccd2e 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -2396,6 +2396,7 @@ static void load_elf_image(const char *image_name, int image_fd, } } bswap_mips_abiflags(&abiflags); +info->fp_abi = abiflags.fp_abi; #endif } } @@ -2708,6 +2709,9 @@ int load_elf_binary(struct linux_binprm *bprm, struct image_info *info) target_mmap(0, qemu_host_page_size, PROT_READ | PROT_EXEC, MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); } +#ifdef TARGET_MIPS +info->interp_fp_abi = interp_info.fp_abi; +#endif } bprm->p = create_elf_tables(bprm->p, bprm->argc, bprm->envc, &elf_ex, -- 1.9.1
[Qemu-devel] [PATCH 3/6] Extract MIPS abiflags from ELF file
From: Stefan Markovic
Signed-off-by: Stefan Markovic
---
linux-user/elfload.c | 33 +
1 file changed, 33 insertions(+)
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 055f6a9..5881233 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -1517,11 +1517,25 @@ static void bswap_sym(struct elf_sym *sym)
bswaptls(&sym->st_size);
bswap16s(&sym->st_shndx);
}
+
+#ifdef TARGET_MIPS
+static void bswap_mips_abiflags(Mips_elf_abiflags_v0 *abiflags)
+{
+bswap16s(&abiflags->version);
+bswap32s(&abiflags->ases);
+bswap32s(&abiflags->isa_ext);
+bswap32s(&abiflags->flags1);
+bswap32s(&abiflags->flags2);
+}
+#endif
#else
static inline void bswap_ehdr(struct elfhdr *ehdr) { }
static inline void bswap_phdr(struct elf_phdr *phdr, int phnum) { }
static inline void bswap_shdr(struct elf_shdr *shdr, int shnum) { }
static inline void bswap_sym(struct elf_sym *sym) { }
+#ifdef TARGET_MIPS
+static inline void bswap_mips_abiflags(Mips_elf_abiflags_v0 *abiflags) { }
+#endif
#endif
#ifdef USE_ELF_CORE_DUMP
@@ -2364,6 +2378,25 @@ static void load_elf_image(const char *image_name, int
image_fd,
goto exit_errmsg;
}
*pinterp_name = interp_name;
+#ifdef TARGET_MIPS
+} else if (eppnt->p_type == PT_MIPS_ABIFLAGS) {
+Mips_elf_abiflags_v0 abiflags;
+if (eppnt->p_filesz < sizeof(Mips_elf_abiflags_v0)) {
+errmsg = "Invalid PT_MIPS_ABIFLAGS entry";
+goto exit_errmsg;
+}
+if (eppnt->p_offset + eppnt->p_filesz <= BPRM_BUF_SIZE) {
+memcpy(&abiflags, bprm_buf + eppnt->p_offset,
+ sizeof(Mips_elf_abiflags_v0));
+} else {
+retval = pread(image_fd, &abiflags,
sizeof(Mips_elf_abiflags_v0),
+ eppnt->p_offset);
+if (retval != sizeof(Mips_elf_abiflags_v0)) {
+goto exit_perror;
+}
+}
+bswap_mips_abiflags(&abiflags);
+#endif
}
}
--
1.9.1
[Qemu-devel] [PATCH 6/6] Add prctl() PR_SET_FP_MODE and PR_GET_FP_MODE implementations
From: Stefan Markovic
Signed-off-by: Stefan Markovic
---
linux-user/mips/target_syscall.h | 2 ++
linux-user/mips64/target_syscall.h | 2 ++
linux-user/syscall.c | 62 +++---
3 files changed, 62 insertions(+), 4 deletions(-)
diff --git a/linux-user/mips/target_syscall.h b/linux-user/mips/target_syscall.h
index 33177af..fa075c9 100644
--- a/linux-user/mips/target_syscall.h
+++ b/linux-user/mips/target_syscall.h
@@ -247,5 +247,7 @@ static inline abi_ulong target_shmlba(CPUMIPSState *env)
/* MIPS-specific prctl() options */
#define TARGET_PR_SET_FP_MODE 45
#define TARGET_PR_GET_FP_MODE 46
+#define TARGET_PR_FP_MODE_FR (1 << 0)
+#define TARGET_PR_FP_MODE_FRE (1 << 1)
#endif /* MIPS_TARGET_SYSCALL_H */
diff --git a/linux-user/mips64/target_syscall.h
b/linux-user/mips64/target_syscall.h
index c1160e6..c8a9027 100644
--- a/linux-user/mips64/target_syscall.h
+++ b/linux-user/mips64/target_syscall.h
@@ -244,5 +244,7 @@ static inline abi_ulong target_shmlba(CPUMIPSState *env)
/* MIPS-specific prctl() options */
#define TARGET_PR_SET_FP_MODE 45
#define TARGET_PR_GET_FP_MODE 46
+#define TARGET_PR_FP_MODE_FR (1 << 0)
+#define TARGET_PR_FP_MODE_FRE (1 << 1)
#endif /* MIPS64_TARGET_SYSCALL_H */
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 15b03e1..810a58b 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -9529,11 +9529,65 @@ static abi_long do_syscall1(void *cpu_env, int num,
abi_long arg1,
#endif
#ifdef TARGET_MIPS
case TARGET_PR_GET_FP_MODE:
-/* TODO: Implement TARGET_PR_SET_FP_MODE handling.*/
-return -TARGET_EINVAL;
+{
+CPUMIPSState *env = ((CPUMIPSState *)cpu_env);
+ret = 0;
+if (env->CP0_Status & (1 << CP0St_FR)) {
+ret |= TARGET_PR_FP_MODE_FR;
+}
+if (env->CP0_Config5 & (1 << CP0C5_FRE)) {
+ret |= TARGET_PR_FP_MODE_FRE;
+}
+return ret;
+}
case TARGET_PR_SET_FP_MODE:
-/* TODO: Implement TARGET_PR_GET_FP_MODE handling.*/
-return -TARGET_EINVAL;
+{
+CPUMIPSState *env = ((CPUMIPSState *)cpu_env);
+bool old_fr = env->CP0_Status & (1 << CP0St_FR);
+bool new_fr = arg2 & TARGET_PR_FP_MODE_FR;
+bool new_fre = arg2 & TARGET_PR_FP_MODE_FRE;
+
+if (new_fr && !(env->active_fpu.fcr0 & (1 << FCR0_F64))) {
+/* FR1 is not supported */
+return -TARGET_EOPNOTSUPP;
+}
+if (!new_fr && (env->active_fpu.fcr0 & (1 << FCR0_F64))
+&& !(env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) {
+/* cannot set FR=0 */
+return -TARGET_EOPNOTSUPP;
+}
+if (new_fre && !(env->active_fpu.fcr0 & (1 << FCR0_FREP))) {
+/* Cannot set FRE=1 */
+return -TARGET_EOPNOTSUPP;
+}
+
+int i;
+fpr_t *fpr = env->active_fpu.fpr;
+for (i = 0; i < 32 ; i += 2) {
+if (!old_fr && new_fr) {
+fpr[i].w[!FP_ENDIAN_IDX] = fpr[i + 1].w[FP_ENDIAN_IDX];
+} else if (old_fr && !new_fr) {
+fpr[i + 1].w[FP_ENDIAN_IDX] = fpr[i].w[!FP_ENDIAN_IDX];
+}
+}
+
+if (new_fr) {
+env->CP0_Status |= (1 << CP0St_FR);
+env->hflags |= MIPS_HFLAG_F64;
+} else {
+env->CP0_Status &= ~(1 << CP0St_FR);
+}
+if (new_fre) {
+env->CP0_Config5 |= (1 << CP0C5_FRE);
+if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
+env->hflags |= MIPS_HFLAG_FRE;
+}
+} else {
+env->CP0_Config5 &= ~(1 << CP0C5_FRE);
+}
+
+return 0;
+}
#endif /* MIPS */
#ifdef TARGET_AARCH64
case TARGET_PR_SVE_SET_VL:
--
1.9.1
[Qemu-devel] [PATCH 1/6] Define MIPS_ABI_FP_UNKNOWN macro
From: Stefan Markovic Signed-off-by: Stefan Markovic --- include/elf.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/elf.h b/include/elf.h index 5f45f9b..c151164 100644 --- a/include/elf.h +++ b/include/elf.h @@ -87,6 +87,8 @@ typedef int64_t Elf64_Sxword; #define EF_MIPS_MACH_LS3A 0x00a2 /* ST Microelectronics Loongson 3A */ #define EF_MIPS_MACH 0x00ff /* EF_MIPS_MACH_xxx selection mask */ +#define MIPS_ABI_FP_UNKNOWN (-1)/* Unknown FP ABI (internal) */ + #define MIPS_ABI_FP_ANY 0x0 /* FP ABI doesn't matter */ #define MIPS_ABI_FP_DOUBLE0x1 /* -mdouble-float */ #define MIPS_ABI_FP_SINGLE0x2 /* -msingle-float */ -- 1.9.1
Re: [Qemu-devel] [PATCH v7 04/20] target/mips: Add and integrate MXU decoding engine placeholder
In that case, I guess this should be OK for now, as MXU support is initiated by Craig and this will be an easy add-on when he provide necessary information. Reviewed-by: Stefan Markovic On 28.10.18. 19:39, Aleksandar Markovic wrote: >> Subject: Re: [PATCH v7 04/20] target/mips: Add and integrate MXU decoding >> engine > placeholder >> >>> Is the best way to implement this to include processing of MUL, CLZ, >>> CLO, SDBBP instructions into decode_opc_mxu as their encodings aren't >>> overlaid by MXU instructions considering MIPS SPECIAL2 instruction >>> pool and MXU Instruction Set? >> The problem is that we don't have the documentation for Ingenic's base >> instruction set. My understanding is that Craig established necessity of >> including non-MXU MUL into decode_opc_mxu() by experimentation, >> or by looking at Ingenic's toolchain source code. >> >> Note that CLZ, CLO, SDBBP are moved from SPECIAL2 to another >> place in opcode space in MIPS R6. >> >> Craig, can you offer any insight on CLZ, CLO, SDBBP in Ingenic's base >> instruction set? They are in SPECIAL2 opcode space for MIPS pre-R6. >> >> Worse come to worst, I recommend adding "TODO" comment to an >> appropriate place in decode_opc_mxu(), and go forward without handling >> CLZ, CLO, SDBBP - given that all changes in this series are just the first >> phase of implementing MXU support - they won't affect any production >> code at this moment. >> > I think this comment should be added to the decode_opc_mxu(), within patch 11: > > /* > * TODO: Investigate necessity of including handling of > * CLZ, CLO, SDBB in this function, as they belong to > * SPECIAL2 opcode space for regular pre-R6 MIPS ISAs. > */ > > Thanks, > Aleksandar
Re: [Qemu-devel] [PATCH v7 13/20] target/mips: Move MUL, S32M2I, S32I2M handling out of main MXU switch
Following the patch 04/20 discussion:
Reviewed-by: Stefan Markovic
On 26.10.18. 11:45, Stefan Markovic wrote:
>
> On 24.10.18. 14:18, Aleksandar Markovic wrote:
>> From: Aleksandar Markovic
>>
>> Move MUL, S32M2I, S32I2M handling out of switch. These are all
>> instructions that do not depend on MXU_EN flag of MXU_CR.
>>
>> Signed-off-by: Aleksandar Markovic
>> ---
>> target/mips/translate.c | 41 +++--
>> 1 file changed, 23 insertions(+), 18 deletions(-)
>
>
> See my comment for patch 04/20.
>
> CLZ, CLO, SDDP are missing?
>
>
>> diff --git a/target/mips/translate.c b/target/mips/translate.c
>> index c8c71c4..111affb 100644
>> --- a/target/mips/translate.c
>> +++ b/target/mips/translate.c
>> @@ -24859,6 +24859,29 @@ static void decode_opc_mxu(CPUMIPSState
>> *env, DisasContext *ctx)
>> {
>> uint32_t opcode = extract32(ctx->opcode, 0, 6);
>> + if (opcode == OPC__MXU_MUL) {
>> + uint32_t rs, rt, rd, op1;
>> +
>> + rs = extract32(ctx->opcode, 21, 5);
>> + rt = extract32(ctx->opcode, 16, 5);
>> + rd = extract32(ctx->opcode, 11, 5);
>> + op1 = MASK_SPECIAL2(ctx->opcode);
>> +
>> + gen_arith(ctx, op1, rd, rs, rt);
>> +
>> + return;
>> + }
>> +
>> + if (opcode == OPC_MXU_S32M2I) {
>> + gen_mxu_s32m2i(ctx);
>> + return;
>> + }
>> +
>> + if (opcode == OPC_MXU_S32I2M) {
>> + gen_mxu_s32i2m(ctx);
>> + return;
>> + }
>> +
>> switch (opcode) {
>> case OPC_MXU_S32MADD:
>> /* TODO: Implement emulation of S32MADD instruction. */
>> @@ -24870,18 +24893,6 @@ static void decode_opc_mxu(CPUMIPSState
>> *env, DisasContext *ctx)
>> MIPS_INVAL("OPC_MXU_S32MADDU");
>> generate_exception_end(ctx, EXCP_RI);
>> break;
>> - case OPC__MXU_MUL: /* 0x2 - unused in MXU specs */
>> - {
>> - uint32_t rs, rt, rd, op1;
>> -
>> - rs = extract32(ctx->opcode, 21, 5);
>> - rt = extract32(ctx->opcode, 16, 5);
>> - rd = extract32(ctx->opcode, 11, 5);
>> - op1 = MASK_SPECIAL2(ctx->opcode);
>> -
>> - gen_arith(ctx, op1, rd, rs, rt);
>> - }
>> - break;
>> case OPC_MXU__POOL00:
>> decode_opc_mxu__pool00(env, ctx);
>> break;
>> @@ -25033,12 +25044,6 @@ static void decode_opc_mxu(CPUMIPSState
>> *env, DisasContext *ctx)
>> MIPS_INVAL("OPC_MXU_S16SDI");
>> generate_exception_end(ctx, EXCP_RI);
>> break;
>> - case OPC_MXU_S32M2I:
>> - gen_mxu_s32m2i(ctx);
>> - break;
>> - case OPC_MXU_S32I2M:
>> - gen_mxu_s32i2m(ctx);
>> - break;
>> case OPC_MXU_D32SLL:
>> /* TODO: Implement emulation of D32SLL instruction. */
>> MIPS_INVAL("OPC_MXU_D32SLL");
Re: [Qemu-devel] [PATCH] target/mips: Add two missing breaks for NM_LLWPE and NM_SCWPE decoder cases
On 29.10.18. 12:15, Aleksandar Markovic wrote: > From: Aleksandar Markovic > > Coverity found two fallthroughs that lack break statements. Fix them. > > Signed-off-by: Aleksandar Markovic > --- > target/mips/translate.c | 2 ++ > 1 file changed, 2 insertions(+) Reviewed-by: Stefan Markovic > diff --git a/target/mips/translate.c b/target/mips/translate.c > index b8ace0b..813ad19 100644 > --- a/target/mips/translate.c > +++ b/target/mips/translate.c > @@ -21402,6 +21402,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState > *env, DisasContext *ctx) > check_eva(ctx); > check_cp0_enabled(ctx); > gen_llwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, > 5)); > +break; > default: > generate_exception_end(ctx, EXCP_RI); > break; > @@ -21420,6 +21421,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState > *env, DisasContext *ctx) > check_eva(ctx); > check_cp0_enabled(ctx); > gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, > 5)); > +break; > default: > generate_exception_end(ctx, EXCP_RI); > break;
Re: [Qemu-devel] ?==?utf-8?q? ?==?utf-8?q? [PATCH 5/6] Determine the desired FPU mode
exit() error codes are taken and left over from related kernel code. Will be
set to 1 in next series version. Also, appropriate error messages printing will
be added.
Regards,
Stefan
Original Message
Subject: Re: [Qemu-devel] [PATCH 5/6] Determine the desired FPU mode
Date: Friday, October 26, 2018 20:12 CEST
From: Peter Maydell
To: Stefan Markovic
CC: QEMU Developers , Petar Jovanovic
, Riku Voipio , Aleksandar
Markovic , Aurelien Jarno ,
Laurent Vivier
References: <1540563667-23300-1-git-send-email-stefan.marko...@rt-rk.com>
<1540563667-23300-6-git-send-email-stefan.marko...@rt-rk.com>
On 26 October 2018 at 15:21, Stefan Markovic wrote:
> From: Stefan Markovic
>
> Floating-point mode is calculated from MIPS.abiflags FP ABI value
> (based on kernel implementation). Illegal combinations are rejected.
>
> Signed-off-by: Stefan Markovic
> ---
> linux-user/mips/cpu_loop.c | 75 ++
> 1 file changed, 75 insertions(+)
> + if ((info->fp_abi > MAX_FP_ABI && info->fp_abi != MIPS_ABI_FP_UNKNOWN)
> + || (info->interp_fp_abi > MAX_FP_ABI &&
> + info->interp_fp_abi != MIPS_ABI_FP_UNKNOWN)) {
> + fprintf(stderr, "qemu: Program and interpreter have "
> + "unexpected FPU modes\n");
> + exit(137);
Why are we exit()ing with a funny exit status code here?
If this is a "can't happen" case, then we should assert(). If
it is a "can happen if fed an odd binary" case, then we should just
exit(1) as we do already in this function for an unsupported NaN mode.
> + }
> +
> + prog_req = (info->fp_abi == MIPS_ABI_FP_UNKNOWN) ? none_req
> + : fpu_reqs[info->fp_abi];
> + interp_req = (info->interp_fp_abi == MIPS_ABI_FP_UNKNOWN) ? none_req
> + : fpu_reqs[info->interp_fp_abi];
> +
> + prog_req.single &= interp_req.single;
> + prog_req.soft &= interp_req.soft;
> + prog_req.fr1 &= interp_req.fr1;
> + prog_req.frdefault &= interp_req.frdefault;
> + prog_req.fre &= interp_req.fre;
> +
> + bool cpu_has_mips_r2_r6 = env->insn_flags & ISA_MIPS32R2 ||
> + env->insn_flags & ISA_MIPS64R2 ||
> + env->insn_flags & ISA_MIPS32R6 ||
> + env->insn_flags & ISA_MIPS64R6;
> +
> + if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) {
> + env->CP0_Config5 |= (1 << CP0C5_FRE);
> + if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
> + env->hflags |= MIPS_HFLAG_FRE;
> + }
> + } else if ((prog_req.fr1 && prog_req.frdefault) ||
> + (prog_req.single && !prog_req.frdefault)) {
> + if ((env->active_fpu.fcr0 & (1 << FCR0_F64)
> + && cpu_has_mips_r2_r6) || prog_req.fr1) {
> + env->CP0_Status |= (1 << CP0St_FR);
> + env->hflags |= MIPS_HFLAG_F64;
> + }
> + } else if (!prog_req.fre && !prog_req.frdefault &&
> + !prog_req.fr1 && !prog_req.single && !prog_req.soft) {
> + exit(137);
> + }
Ditto here (and we haven't printed any error message here...)
thanks
-- PMM
[Qemu-devel] [PATCH v2 6/6] Add prctl() PR_SET_FP_MODE and PR_GET_FP_MODE implementations
From: Stefan Markovic
Implement MIPS specific prctl() PR_SET_FP_MODE and PR_GET_FP_MODE emulation.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/mips/target_syscall.h | 2 ++
linux-user/mips64/target_syscall.h | 2 ++
linux-user/syscall.c | 62 +++---
3 files changed, 62 insertions(+), 4 deletions(-)
diff --git a/linux-user/mips/target_syscall.h b/linux-user/mips/target_syscall.h
index 33177af..d5509a3 100644
--- a/linux-user/mips/target_syscall.h
+++ b/linux-user/mips/target_syscall.h
@@ -247,5 +247,7 @@ static inline abi_ulong target_shmlba(CPUMIPSState *env)
/* MIPS-specific prctl() options */
#define TARGET_PR_SET_FP_MODE 45
#define TARGET_PR_GET_FP_MODE 46
+#define TARGET_PR_FP_MODE_FR (1 << 0)
+#define TARGET_PR_FP_MODE_FRE (1 << 1)
#endif /* MIPS_TARGET_SYSCALL_H */
diff --git a/linux-user/mips64/target_syscall.h
b/linux-user/mips64/target_syscall.h
index c1160e6..8ccc468 100644
--- a/linux-user/mips64/target_syscall.h
+++ b/linux-user/mips64/target_syscall.h
@@ -244,5 +244,7 @@ static inline abi_ulong target_shmlba(CPUMIPSState *env)
/* MIPS-specific prctl() options */
#define TARGET_PR_SET_FP_MODE 45
#define TARGET_PR_GET_FP_MODE 46
+#define TARGET_PR_FP_MODE_FR (1 << 0)
+#define TARGET_PR_FP_MODE_FRE (1 << 1)
#endif /* MIPS64_TARGET_SYSCALL_H */
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 15b03e1..810a58b 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -9529,11 +9529,65 @@ static abi_long do_syscall1(void *cpu_env, int num,
abi_long arg1,
#endif
#ifdef TARGET_MIPS
case TARGET_PR_GET_FP_MODE:
-/* TODO: Implement TARGET_PR_SET_FP_MODE handling.*/
-return -TARGET_EINVAL;
+{
+CPUMIPSState *env = ((CPUMIPSState *)cpu_env);
+ret = 0;
+if (env->CP0_Status & (1 << CP0St_FR)) {
+ret |= TARGET_PR_FP_MODE_FR;
+}
+if (env->CP0_Config5 & (1 << CP0C5_FRE)) {
+ret |= TARGET_PR_FP_MODE_FRE;
+}
+return ret;
+}
case TARGET_PR_SET_FP_MODE:
-/* TODO: Implement TARGET_PR_GET_FP_MODE handling.*/
-return -TARGET_EINVAL;
+{
+CPUMIPSState *env = ((CPUMIPSState *)cpu_env);
+bool old_fr = env->CP0_Status & (1 << CP0St_FR);
+bool new_fr = arg2 & TARGET_PR_FP_MODE_FR;
+bool new_fre = arg2 & TARGET_PR_FP_MODE_FRE;
+
+if (new_fr && !(env->active_fpu.fcr0 & (1 << FCR0_F64))) {
+/* FR1 is not supported */
+return -TARGET_EOPNOTSUPP;
+}
+if (!new_fr && (env->active_fpu.fcr0 & (1 << FCR0_F64))
+&& !(env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) {
+/* cannot set FR=0 */
+return -TARGET_EOPNOTSUPP;
+}
+if (new_fre && !(env->active_fpu.fcr0 & (1 << FCR0_FREP))) {
+/* Cannot set FRE=1 */
+return -TARGET_EOPNOTSUPP;
+}
+
+int i;
+fpr_t *fpr = env->active_fpu.fpr;
+for (i = 0; i < 32 ; i += 2) {
+if (!old_fr && new_fr) {
+fpr[i].w[!FP_ENDIAN_IDX] = fpr[i + 1].w[FP_ENDIAN_IDX];
+} else if (old_fr && !new_fr) {
+fpr[i + 1].w[FP_ENDIAN_IDX] = fpr[i].w[!FP_ENDIAN_IDX];
+}
+}
+
+if (new_fr) {
+env->CP0_Status |= (1 << CP0St_FR);
+env->hflags |= MIPS_HFLAG_F64;
+} else {
+env->CP0_Status &= ~(1 << CP0St_FR);
+}
+if (new_fre) {
+env->CP0_Config5 |= (1 << CP0C5_FRE);
+if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
+env->hflags |= MIPS_HFLAG_FRE;
+}
+} else {
+env->CP0_Config5 &= ~(1 << CP0C5_FRE);
+}
+
+return 0;
+}
#endif /* MIPS */
#ifdef TARGET_AARCH64
case TARGET_PR_SVE_SET_VL:
--
1.9.1
[Qemu-devel] [PATCH v2 5/6] Determine the desired FPU mode
From: Stefan Markovic
Floating-point mode is calculated from MIPS.abiflags FP ABI value
(based on kernel implementation). Illegal combinations are rejected.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/mips/cpu_loop.c | 75 ++
1 file changed, 75 insertions(+)
diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c
index c9c20cf..97e4957 100644
--- a/linux-user/mips/cpu_loop.c
+++ b/linux-user/mips/cpu_loop.c
@@ -740,6 +740,34 @@ void target_cpu_copy_regs(CPUArchState *env, struct
target_pt_regs *regs)
struct image_info *info = ts->info;
int i;
+struct mode_req {
+bool single;
+bool soft;
+bool fr1;
+bool frdefault;
+bool fre;
+};
+
+static const struct mode_req fpu_reqs[] = {
+[MIPS_ABI_FP_ANY]= { true, true, true, true, true },
+[MIPS_ABI_FP_DOUBLE] = { false, false, false, true, true },
+[MIPS_ABI_FP_SINGLE] = { true, false, false, false, false },
+[MIPS_ABI_FP_SOFT] = { false, true, false, false, false },
+[MIPS_ABI_FP_OLD_64] = { false, false, false, false, false },
+[MIPS_ABI_FP_XX] = { false, false, true, true, true },
+[MIPS_ABI_FP_64] = { false, false, true, false, false },
+[MIPS_ABI_FP_64A]= { false, false, true, false, true }
+};
+
+/*
+ * Mode requirements when .MIPS.abiflags is not present in the ELF.
+ * Not present means that everything is acceptable except FR1.
+ */
+static struct mode_req none_req = { true, true, false, true, true };
+
+struct mode_req prog_req;
+struct mode_req interp_req;
+
for(i = 0; i < 32; i++) {
env->active_tc.gpr[i] = regs->regs[i];
}
@@ -747,6 +775,53 @@ void target_cpu_copy_regs(CPUArchState *env, struct
target_pt_regs *regs)
if (regs->cp0_epc & 1) {
env->hflags |= MIPS_HFLAG_M16;
}
+
+#ifdef TARGET_ABI_MIPSO32
+# define MAX_FP_ABI MIPS_ABI_FP_64A
+#else
+# define MAX_FP_ABI MIPS_ABI_FP_SOFT
+#endif
+ if ((info->fp_abi > MAX_FP_ABI && info->fp_abi != MIPS_ABI_FP_UNKNOWN)
+|| (info->interp_fp_abi > MAX_FP_ABI &&
+info->interp_fp_abi != MIPS_ABI_FP_UNKNOWN)) {
+fprintf(stderr, "qemu: Unexpected FPU mode\n");
+exit(1);
+}
+
+prog_req = (info->fp_abi == MIPS_ABI_FP_UNKNOWN) ? none_req
+: fpu_reqs[info->fp_abi];
+interp_req = (info->interp_fp_abi == MIPS_ABI_FP_UNKNOWN) ? none_req
+: fpu_reqs[info->interp_fp_abi];
+
+prog_req.single &= interp_req.single;
+prog_req.soft &= interp_req.soft;
+prog_req.fr1 &= interp_req.fr1;
+prog_req.frdefault &= interp_req.frdefault;
+prog_req.fre &= interp_req.fre;
+
+bool cpu_has_mips_r2_r6 = env->insn_flags & ISA_MIPS32R2 ||
+ env->insn_flags & ISA_MIPS64R2 ||
+ env->insn_flags & ISA_MIPS32R6 ||
+ env->insn_flags & ISA_MIPS64R6;
+
+if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) {
+env->CP0_Config5 |= (1 << CP0C5_FRE);
+if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
+env->hflags |= MIPS_HFLAG_FRE;
+}
+} else if ((prog_req.fr1 && prog_req.frdefault) ||
+ (prog_req.single && !prog_req.frdefault)) {
+if ((env->active_fpu.fcr0 & (1 << FCR0_F64)
+&& cpu_has_mips_r2_r6) || prog_req.fr1) {
+env->CP0_Status |= (1 << CP0St_FR);
+env->hflags |= MIPS_HFLAG_F64;
+}
+} else if (!prog_req.fre && !prog_req.frdefault &&
+ !prog_req.fr1 && !prog_req.single && !prog_req.soft) {
+fprintf(stderr, "qemu: Can't find a matching FPU mode\n");
+exit(1);
+}
+
if (env->insn_flags & ISA_NANOMIPS32) {
return;
}
--
1.9.1
[Qemu-devel] [PATCH v2 1/6] Define MIPS_ABI_FP_UNKNOWN macro
From: Stefan Markovic Add MIPS_ABI_FP_UNKNOWN as QEMU internal value to represent unknown fp_abi (based on kernel mips/include/asm/elf.h definition) Reviewed-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- include/elf.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/elf.h b/include/elf.h index 5f45f9b..c151164 100644 --- a/include/elf.h +++ b/include/elf.h @@ -87,6 +87,8 @@ typedef int64_t Elf64_Sxword; #define EF_MIPS_MACH_LS3A 0x00a2 /* ST Microelectronics Loongson 3A */ #define EF_MIPS_MACH 0x00ff /* EF_MIPS_MACH_xxx selection mask */ +#define MIPS_ABI_FP_UNKNOWN (-1)/* Unknown FP ABI (internal) */ + #define MIPS_ABI_FP_ANY 0x0 /* FP ABI doesn't matter */ #define MIPS_ABI_FP_DOUBLE0x1 /* -mdouble-float */ #define MIPS_ABI_FP_SINGLE0x2 /* -msingle-float */ -- 1.9.1
[Qemu-devel] [PATCH v2 2/6] Extend image_info struct with MIPS specific fp_abi and interp_fp_abi fields
From: Stefan Markovic
Add MIPS specific image_info struct fields fp_abi and interp_fp_abi
to store executable and interpreter fp_abi values (based on kernel
struct arch_elf_state in mips/include/asm/elf.h).
Reviewed-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/qemu.h | 4
1 file changed, 4 insertions(+)
diff --git a/linux-user/qemu.h b/linux-user/qemu.h
index 1beb6a2..a752c1c 100644
--- a/linux-user/qemu.h
+++ b/linux-user/qemu.h
@@ -61,6 +61,10 @@ struct image_info {
abi_ulong interpreter_loadmap_addr;
abi_ulong interpreter_pt_dynamic_addr;
struct image_info *other_info;
+#ifdef TARGET_MIPS
+int fp_abi;
+int interp_fp_abi;
+#endif
};
#ifdef TARGET_I386
--
1.9.1
[Qemu-devel] [PATCH v2 0/6] target/mips: Add support for prctl() PR_GET_FP_MODE and PR_SET_FP_MODE
From: Stefan Markovic This series includes support for prctl() PR_GET_FP_MODE and PR_SET_FP_MODE. This requires extracting MIPS.abiflags section from ELF file and fp_abi value handling. v1->v2: - added commit messages - fixed exit() error codes and appropriate exit messages printed - minor code alignments Stefan Markovic (6): Define MIPS_ABI_FP_UNKNOWN macro Extend image_info struct with MIPS specific fp_abi and interp_fp_abi fields Extract MIPS abiflags from ELF file Read and set FP ABI value from MIPS abiflags Determine the desired FPU mode Add prctl() PR_SET_FP_MODE and PR_GET_FP_MODE implementations include/elf.h | 2 + linux-user/elfload.c | 37 +++ linux-user/mips/cpu_loop.c | 75 ++ linux-user/mips/target_syscall.h | 2 + linux-user/mips64/target_syscall.h | 2 + linux-user/qemu.h | 4 ++ linux-user/syscall.c | 62 +-- 7 files changed, 180 insertions(+), 4 deletions(-) -- 1.9.1
[Qemu-devel] [PATCH v2 3/6] Extract MIPS abiflags from ELF file
From: Stefan Markovic
Read MIPS.abiflags section from ELF file into Mips_elf_abiflags_v0 struct.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/elfload.c | 33 +
1 file changed, 33 insertions(+)
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 055f6a9..5881233 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -1517,11 +1517,25 @@ static void bswap_sym(struct elf_sym *sym)
bswaptls(&sym->st_size);
bswap16s(&sym->st_shndx);
}
+
+#ifdef TARGET_MIPS
+static void bswap_mips_abiflags(Mips_elf_abiflags_v0 *abiflags)
+{
+bswap16s(&abiflags->version);
+bswap32s(&abiflags->ases);
+bswap32s(&abiflags->isa_ext);
+bswap32s(&abiflags->flags1);
+bswap32s(&abiflags->flags2);
+}
+#endif
#else
static inline void bswap_ehdr(struct elfhdr *ehdr) { }
static inline void bswap_phdr(struct elf_phdr *phdr, int phnum) { }
static inline void bswap_shdr(struct elf_shdr *shdr, int shnum) { }
static inline void bswap_sym(struct elf_sym *sym) { }
+#ifdef TARGET_MIPS
+static inline void bswap_mips_abiflags(Mips_elf_abiflags_v0 *abiflags) { }
+#endif
#endif
#ifdef USE_ELF_CORE_DUMP
@@ -2364,6 +2378,25 @@ static void load_elf_image(const char *image_name, int
image_fd,
goto exit_errmsg;
}
*pinterp_name = interp_name;
+#ifdef TARGET_MIPS
+} else if (eppnt->p_type == PT_MIPS_ABIFLAGS) {
+Mips_elf_abiflags_v0 abiflags;
+if (eppnt->p_filesz < sizeof(Mips_elf_abiflags_v0)) {
+errmsg = "Invalid PT_MIPS_ABIFLAGS entry";
+goto exit_errmsg;
+}
+if (eppnt->p_offset + eppnt->p_filesz <= BPRM_BUF_SIZE) {
+memcpy(&abiflags, bprm_buf + eppnt->p_offset,
+ sizeof(Mips_elf_abiflags_v0));
+} else {
+retval = pread(image_fd, &abiflags,
sizeof(Mips_elf_abiflags_v0),
+ eppnt->p_offset);
+if (retval != sizeof(Mips_elf_abiflags_v0)) {
+goto exit_perror;
+}
+}
+bswap_mips_abiflags(&abiflags);
+#endif
}
}
--
1.9.1
[Qemu-devel] [PATCH v2 4/6] Read and set FP ABI value from MIPS abiflags
From: Stefan Markovic Set fp_abi and interp_fp_abi values to current fp_abi value read from MIPS.abiflags. Reviewed-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- linux-user/elfload.c | 4 1 file changed, 4 insertions(+) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 5881233..5bccd2e 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -2396,6 +2396,7 @@ static void load_elf_image(const char *image_name, int image_fd, } } bswap_mips_abiflags(&abiflags); +info->fp_abi = abiflags.fp_abi; #endif } } @@ -2708,6 +2709,9 @@ int load_elf_binary(struct linux_binprm *bprm, struct image_info *info) target_mmap(0, qemu_host_page_size, PROT_READ | PROT_EXEC, MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); } +#ifdef TARGET_MIPS +info->interp_fp_abi = interp_info.fp_abi; +#endif } bprm->p = create_elf_tables(bprm->p, bprm->argc, bprm->envc, &elf_ex, -- 1.9.1
Re: [Qemu-devel] [PATCH v2 1/5] target/mips: Rename MMI-related masks
On 30.10.18. 12:36, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Rename MMI-related masks.
>
> Signed-off-by: Aleksandar Markovic
> ---
> target/mips/translate.c | 20 ++--
> 1 file changed, 10 insertions(+), 10 deletions(-)
Reviewed-by: Stefan Markovic
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index 51a5488..e38d50d 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -2159,7 +2159,7 @@ enum {
>*7 111 | * | * | * | * | PSLLW | * | PSRLW | PSRAW
>*/
>
> -#define MASK_TX79_MMI(op) (MASK_OP_MAJOR(op) | ((op) & 0x3F))
> +#define MASK_MMI(op) (MASK_OP_MAJOR(op) | ((op) & 0x3F))
> enum {
> TX79_MMI_MADD = 0x00 | TX79_CLASS_MMI, /* Same as OPC_MADD */
> TX79_MMI_MADDU = 0x01 | TX79_CLASS_MMI, /* Same as OPC_MADDU */
> @@ -2210,7 +2210,7 @@ enum {
>*7 111 | * | * | PEXT5 | PPAC5
>*/
>
> -#define MASK_TX79_MMI0(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF))
> +#define MASK_MMI0(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF))
> enum {
> TX79_MMI0_PADDW = (0x00 << 6) | TX79_MMI_CLASS_MMI0,
> TX79_MMI0_PSUBW = (0x01 << 6) | TX79_MMI_CLASS_MMI0,
> @@ -2261,7 +2261,7 @@ enum {
>*7 111 | * | * | * | *
>*/
>
> -#define MASK_TX79_MMI1(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF))
> +#define MASK_MMI1(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF))
> enum {
> TX79_MMI1_PABSW = (0x01 << 6) | TX79_MMI_CLASS_MMI1,
> TX79_MMI1_PCEQW = (0x02 << 6) | TX79_MMI_CLASS_MMI1,
> @@ -2305,7 +2305,7 @@ enum {
>*7 111 | PMULTH| PDIVBW| PEXEW | PROT3W
>*/
>
> -#define MASK_TX79_MMI2(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF))
> +#define MASK_MMI2(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF))
> enum {
> TX79_MMI2_PMADDW = (0x00 << 6) | TX79_MMI_CLASS_MMI2,
> TX79_MMI2_PSLLVW = (0x02 << 6) | TX79_MMI_CLASS_MMI2,
> @@ -2353,7 +2353,7 @@ enum {
>*7 111 | * | * | PEXCW | *
>*/
>
> -#define MASK_TX79_MMI3(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF))
> +#define MASK_MMI3(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF))
> enum {
> TX79_MMI3_PMADDUW = (0x00 << 6) | TX79_MMI_CLASS_MMI3,
> TX79_MMI3_PSRAVW = (0x03 << 6) | TX79_MMI_CLASS_MMI3,
> @@ -24683,7 +24683,7 @@ static void decode_opc_special3_legacy(CPUMIPSState
> *env, DisasContext *ctx)
>
> static void decode_tx79_mmi0(CPUMIPSState *env, DisasContext *ctx)
> {
> -uint32_t opc = MASK_TX79_MMI0(ctx->opcode);
> +uint32_t opc = MASK_MMI0(ctx->opcode);
>
> switch (opc) {
> case TX79_MMI0_PADDW: /* TODO: TX79_MMI0_PADDW */
> @@ -24722,7 +24722,7 @@ static void decode_tx79_mmi0(CPUMIPSState *env,
> DisasContext *ctx)
>
> static void decode_tx79_mmi1(CPUMIPSState *env, DisasContext *ctx)
> {
> -uint32_t opc = MASK_TX79_MMI1(ctx->opcode);
> +uint32_t opc = MASK_MMI1(ctx->opcode);
>
> switch (opc) {
> case TX79_MMI1_PABSW: /* TODO: TX79_MMI1_PABSW */
> @@ -24754,7 +24754,7 @@ static void decode_tx79_mmi1(CPUMIPSState *env,
> DisasContext *ctx)
>
> static void decode_tx79_mmi2(CPUMIPSState *env, DisasContext *ctx)
> {
> -uint32_t opc = MASK_TX79_MMI2(ctx->opcode);
> +uint32_t opc = MASK_MMI2(ctx->opcode);
>
> switch (opc) {
> case TX79_MMI2_PMADDW:/* TODO: TX79_MMI2_PMADDW */
> @@ -24790,7 +24790,7 @@ static void decode_tx79_mmi2(CPUMIPSState *env,
> DisasContext *ctx)
>
> static void decode_tx79_mmi3(CPUMIPSState *env, DisasContext *ctx)
> {
> -uint32_t opc = MASK_TX79_MMI3(ctx->opcode);
> +uint32_t opc = MASK_MMI3(ctx->opcode);
>
> switch (opc) {
> case TX79_MMI3_PMADDUW:/* TODO: TX79_MMI3_PMADDUW */
> @@ -24817,7 +24817,7 @@ static void decode_tx79_mmi3(CPUMIPSState *env,
> DisasContext *ctx)
>
> static void decode_tx79_mmi(CPUMIPSState *env, DisasContext *ctx)
> {
> -uint32_t opc = MASK_TX79_MMI(ctx->opcode);
> +uint32_t opc = MASK_MMI(ctx->opcode);
> int rs = extract32(ctx->opcode, 21, 5);
> int rt = extract32(ctx->opcode, 16, 5);
> int rd = extract32(ctx->opcode, 11, 5);
Re: [Qemu-devel] [PATCH v2 2/5] target/mips: Rename MMI-related opcodes
On 30.10.18. 12:36, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Rename MMI-related opcodes.
>
> Signed-off-by: Aleksandar Markovic
> ---
> target/mips/translate.c | 470
>
> 1 file changed, 235 insertions(+), 235 deletions(-)
Reviewed-by: Stefan Markovic
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index e38d50d..4b008d8 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -2099,7 +2099,7 @@ enum {
>* The TX79-specific Multimedia Instruction encodings
>* ==
>*
> - * TX79 Multimedia Instruction encoding table keys:
> + * MMI Instruction encoding table keys:
>*
>* * This code is reserved for future use. An attempt to execute it
>* causes a Reserved Instruction exception.
> @@ -2110,7 +2110,7 @@ enum {
>* DMULTU, DDIV, DDIVU, LL, LLD, SC, SCD, LWC2 and SWC2. An attempt
>* to execute it causes a Reserved Instruction exception.
>*
> - * TX79 Multimedia Instructions encoded by opcode field (MMI, LQ, SQ):
> + * MMI Instructions encoded by opcode field (MMI, LQ, SQ):
>*
>* 31260
>* +++
> @@ -2132,13 +2132,13 @@ enum {
>*/
>
> enum {
> -TX79_CLASS_MMI = 0x1C << 26,/* Same as OPC_SPECIAL2 */
> -TX79_LQ= 0x1E << 26,/* Same as OPC_MSA */
> -TX79_SQ= 0x1F << 26,/* Same as OPC_SPECIAL3 */
> +MMI_CLASS_MMI = 0x1C << 26,/* Same as OPC_SPECIAL2 */
> +MMI_LQ= 0x1E << 26,/* Same as OPC_MSA */
> +MMI_SQ= 0x1F << 26,/* Same as OPC_SPECIAL3 */
> };
>
> /*
> - * TX79 Multimedia Instructions with opcode field = MMI:
> + * MMI Instructions with opcode field = MMI:
>*
>* 3126 5 0
>* ++---++
> @@ -2161,35 +2161,35 @@ enum {
>
> #define MASK_MMI(op) (MASK_OP_MAJOR(op) | ((op) & 0x3F))
> enum {
> -TX79_MMI_MADD = 0x00 | TX79_CLASS_MMI, /* Same as OPC_MADD */
> -TX79_MMI_MADDU = 0x01 | TX79_CLASS_MMI, /* Same as OPC_MADDU */
> -TX79_MMI_PLZCW = 0x04 | TX79_CLASS_MMI,
> -TX79_MMI_CLASS_MMI0 = 0x08 | TX79_CLASS_MMI,
> -TX79_MMI_CLASS_MMI2 = 0x09 | TX79_CLASS_MMI,
> -TX79_MMI_MFHI1 = 0x10 | TX79_CLASS_MMI, /* Same minor as OPC_MFHI */
> -TX79_MMI_MTHI1 = 0x11 | TX79_CLASS_MMI, /* Same minor as OPC_MTHI */
> -TX79_MMI_MFLO1 = 0x12 | TX79_CLASS_MMI, /* Same minor as OPC_MFLO */
> -TX79_MMI_MTLO1 = 0x13 | TX79_CLASS_MMI, /* Same minor as OPC_MTLO */
> -TX79_MMI_MULT1 = 0x18 | TX79_CLASS_MMI, /* Same minor as OPC_MULT */
> -TX79_MMI_MULTU1 = 0x19 | TX79_CLASS_MMI, /* Same minor as OPC_MULTU
> */
> -TX79_MMI_DIV1 = 0x1A | TX79_CLASS_MMI, /* Same minor as OPC_DIV */
> -TX79_MMI_DIVU1 = 0x1B | TX79_CLASS_MMI, /* Same minor as OPC_DIVU */
> -TX79_MMI_MADD1 = 0x20 | TX79_CLASS_MMI,
> -TX79_MMI_MADDU1 = 0x21 | TX79_CLASS_MMI,
> -TX79_MMI_CLASS_MMI1 = 0x28 | TX79_CLASS_MMI,
> -TX79_MMI_CLASS_MMI3 = 0x29 | TX79_CLASS_MMI,
> -TX79_MMI_PMFHL = 0x30 | TX79_CLASS_MMI,
> -TX79_MMI_PMTHL = 0x31 | TX79_CLASS_MMI,
> -TX79_MMI_PSLLH = 0x34 | TX79_CLASS_MMI,
> -TX79_MMI_PSRLH = 0x36 | TX79_CLASS_MMI,
> -TX79_MMI_PSRAH = 0x37 | TX79_CLASS_MMI,
> -TX79_MMI_PSLLW = 0x3C | TX79_CLASS_MMI,
> -TX79_MMI_PSRLW = 0x3E | TX79_CLASS_MMI,
> -TX79_MMI_PSRAW = 0x3F | TX79_CLASS_MMI,
> +MMI_OPC_MADD = 0x00 | MMI_CLASS_MMI, /* Same as OPC_MADD */
> +MMI_OPC_MADDU = 0x01 | MMI_CLASS_MMI, /* Same as OPC_MADDU */
> +MMI_OPC_PLZCW = 0x04 | MMI_CLASS_MMI,
> +MMI_OPC_CLASS_MMI0 = 0x08 | MMI_CLASS_MMI,
> +MMI_OPC_CLASS_MMI2 = 0x09 | MMI_CLASS_MMI,
> +MMI_OPC_MFHI1 = 0x10 | MMI_CLASS_MMI, /* Same minor as OPC_MFHI */
> +MMI_OPC_MTHI1 = 0x11 | MMI_CLASS_MMI, /* Same minor as OPC_MTHI */
> +MMI_OPC_MFLO1 = 0x12 | MMI_CLASS_MMI, /* Same minor as OPC_MFLO */
> +MMI_OPC_MTLO1 = 0x13 | MMI_CLASS_MMI, /* Same minor as OPC_MTLO */
> +MMI_OPC_MULT1 = 0x18 | MMI_CLASS_MMI, /* Same minor as OPC_MULT */
> +MMI_OPC_MULTU1 = 0x19 | MMI_CLASS_MMI, /* Same minor as OPC_MULTU */
> +MMI_OPC_DIV1 = 0x1A | MMI_CLASS_MMI, /* Same minor as OPC_DIV */
> +MMI_OPC_DIVU1 = 0x1B | MMI_CLASS_MMI, /* Same minor as OPC_DIVU */
> +MMI_OP
Re: [Qemu-devel] [PATCH v2 3/5] target/mips: Rename MMI-related functions
On 30.10.18. 12:36, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Rename MMI-related functions.
>
> Signed-off-by: Aleksandar Markovic
> ---
> target/mips/translate.c | 32
> 1 file changed, 16 insertions(+), 16 deletions(-)
Reviewed-by: Stefan Markovic
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index 4b008d8..155331f 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -24681,7 +24681,7 @@ static void decode_opc_special3_legacy(CPUMIPSState
> *env, DisasContext *ctx)
> }
> }
>
> -static void decode_tx79_mmi0(CPUMIPSState *env, DisasContext *ctx)
> +static void decode_mmi0(CPUMIPSState *env, DisasContext *ctx)
> {
> uint32_t opc = MASK_MMI0(ctx->opcode);
>
> @@ -24720,7 +24720,7 @@ static void decode_tx79_mmi0(CPUMIPSState *env,
> DisasContext *ctx)
> }
> }
>
> -static void decode_tx79_mmi1(CPUMIPSState *env, DisasContext *ctx)
> +static void decode_mmi1(CPUMIPSState *env, DisasContext *ctx)
> {
> uint32_t opc = MASK_MMI1(ctx->opcode);
>
> @@ -24752,7 +24752,7 @@ static void decode_tx79_mmi1(CPUMIPSState *env,
> DisasContext *ctx)
> }
> }
>
> -static void decode_tx79_mmi2(CPUMIPSState *env, DisasContext *ctx)
> +static void decode_mmi2(CPUMIPSState *env, DisasContext *ctx)
> {
> uint32_t opc = MASK_MMI2(ctx->opcode);
>
> @@ -24788,7 +24788,7 @@ static void decode_tx79_mmi2(CPUMIPSState *env,
> DisasContext *ctx)
> }
> }
>
> -static void decode_tx79_mmi3(CPUMIPSState *env, DisasContext *ctx)
> +static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
> {
> uint32_t opc = MASK_MMI3(ctx->opcode);
>
> @@ -24815,7 +24815,7 @@ static void decode_tx79_mmi3(CPUMIPSState *env,
> DisasContext *ctx)
> }
> }
>
> -static void decode_tx79_mmi(CPUMIPSState *env, DisasContext *ctx)
> +static void decode_mmi(CPUMIPSState *env, DisasContext *ctx)
> {
> uint32_t opc = MASK_MMI(ctx->opcode);
> int rs = extract32(ctx->opcode, 21, 5);
> @@ -24824,16 +24824,16 @@ static void decode_tx79_mmi(CPUMIPSState *env,
> DisasContext *ctx)
>
> switch (opc) {
> case MMI_OPC_CLASS_MMI0:
> -decode_tx79_mmi0(env, ctx);
> +decode_mmi0(env, ctx);
> break;
> case MMI_OPC_CLASS_MMI1:
> -decode_tx79_mmi1(env, ctx);
> +decode_mmi1(env, ctx);
> break;
> case MMI_OPC_CLASS_MMI2:
> -decode_tx79_mmi2(env, ctx);
> +decode_mmi2(env, ctx);
> break;
> case MMI_OPC_CLASS_MMI3:
> -decode_tx79_mmi3(env, ctx);
> +decode_mmi3(env, ctx);
> break;
> case MMI_OPC_MULT1:
> case MMI_OPC_MULTU1:
> @@ -24873,12 +24873,12 @@ static void decode_tx79_mmi(CPUMIPSState *env,
> DisasContext *ctx)
> }
> }
>
> -static void decode_tx79_lq(CPUMIPSState *env, DisasContext *ctx)
> +static void decode_mmi_lq(CPUMIPSState *env, DisasContext *ctx)
> {
> generate_exception_end(ctx, EXCP_RI);/* TODO: MMI_LQ */
> }
>
> -static void gen_tx79_sq(DisasContext *ctx, int base, int rt, int offset)
> +static void gen_mmi_sq(DisasContext *ctx, int base, int rt, int offset)
> {
> generate_exception_end(ctx, EXCP_RI);/* TODO: MMI_SQ */
> }
> @@ -24904,7 +24904,7 @@ static void gen_tx79_sq(DisasContext *ctx, int base,
> int rt, int offset)
>* In user mode, QEMU must verify the upper and lower 11 bits to distinguish
>* between SQ and RDHWR, as the Linux kernel does.
>*/
> -static void decode_tx79_sq(CPUMIPSState *env, DisasContext *ctx)
> +static void decode_mmi_sq(CPUMIPSState *env, DisasContext *ctx)
> {
> int base = extract32(ctx->opcode, 21, 5);
> int rt = extract32(ctx->opcode, 16, 5);
> @@ -24922,7 +24922,7 @@ static void decode_tx79_sq(CPUMIPSState *env,
> DisasContext *ctx)
> }
> #endif
>
> -gen_tx79_sq(ctx, base, rt, offset);
> +gen_mmi_sq(ctx, base, rt, offset);
> }
>
> static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
> @@ -26231,14 +26231,14 @@ static void decode_opc(CPUMIPSState *env,
> DisasContext *ctx)
> break;
> case OPC_SPECIAL2:
> if ((ctx->insn_flags & INSN_R5900) && (ctx->insn_flags & ASE_MMI)) {
> -decode_tx79_mmi(env, ctx);
> +decode_mmi(env, ctx);
> } else {
> decode_opc_special2_legacy(env, ctx);
> }
> break;
> case OPC_SPECIAL3:
> if (ctx-&
Re: [Qemu-devel] [PATCH for-3.1 05/25] MAINTAINERS: Add missing entries for the Jazz machine
On 25.11.18. 21:49, Philippe Mathieu-Daudé wrote: > Signed-off-by: Philippe Mathieu-Daudé > --- > MAINTAINERS | 2 ++ > 1 file changed, 2 insertions(+) Reviewed-by: Stefan Markovic > diff --git a/MAINTAINERS b/MAINTAINERS > index 007f89f126..4e396cbe71 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -835,6 +835,8 @@ M: Hervé Poussineau > R: Stefan Markovic > S: Maintained > F: hw/mips/mips_jazz.c > +F: hw/display/jazz_led.c > +F: hw/dma/rc4030.c > > Malta > M: Aurelien Jarno
Re: [Qemu-devel] [PATCH for-3.1 07/25] MAINTAINERS: Add a missing entry for the Fulong 2E machine
On 25.11.18. 21:49, Philippe Mathieu-Daudé wrote: > Signed-off-by: Philippe Mathieu-Daudé > --- > MAINTAINERS | 1 + > 1 file changed, 1 insertion(+) Reviewed-by: Stefan Markovic > diff --git a/MAINTAINERS b/MAINTAINERS > index aa17e9bbd3..81a22b2ccf 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -864,6 +864,7 @@ R: Stefan Markovic > S: Odd Fixes > F: hw/mips/mips_fulong2e.c > F: hw/isa/vt82c686.c > +F: hw/pci-host/bonito.c > > F: include/hw/isa/vt82c686.h >
[Qemu-devel] [PATCH 0/2] qemu-doc: Update MIPS/nanoMIPS info
From: Stefan Markovic Update QEMU documentation with nanoMIPS ISA info and add list of QEMU supported MIPS/nanoMIPS CPU models. Stefan Markovic (2): qemu-doc: Add nanoMIPS ISA information docs/qemu-cpu-models: Add MIPS/nanoMIPS QEMU supported CPU models docs/qemu-cpu-models.texi | 163 +- qemu-doc.texi | 29 + 2 files changed, 190 insertions(+), 2 deletions(-) -- 1.9.1
[Qemu-devel] [PATCH 1/2] qemu-doc: Add nanoMIPS ISA information
From: Stefan Markovic
Add nanoMIPS information in qemu-doc.texi with example of usage
included.
Signed-off-by: Stefan Markovic
---
qemu-doc.texi | 29 +
1 file changed, 29 insertions(+)
diff --git a/qemu-doc.texi b/qemu-doc.texi
index f7ad1df..6ef593d 100644
--- a/qemu-doc.texi
+++ b/qemu-doc.texi
@@ -1994,6 +1994,10 @@ Set the emulated machine type. The default is sun4u.
@section MIPS System emulator
@cindex system emulation (MIPS)
+@menu
+* nanoMIPS System emulator ::
+@end menu
+
Four executables cover simulation of 32 and 64-bit MIPS systems in
both endian options, @file{qemu-system-mips}, @file{qemu-system-mipsel}
@file{qemu-system-mips64} and @file{qemu-system-mips64el}.
@@ -2085,6 +2089,31 @@ SCSI controller
G364 framebuffer
@end itemize
+@node nanoMIPS System emulator
+@subsection nanoMIPS System emulator
+@cindex system emulation (nanoMIPS)
+
+Executable @file{qemu-system-mipsel} also covers simulation of
+32-bit nanoMIPS system in little endian mode:
+
+@itemize @minus
+@item
+nanoMIPS I7200 CPU
+@end itemize
+
+Example of @file{qemu-system-mipsel} usage for nanoMIPS is shown below:
+
+Download @code{} from
@url{https://mipsdistros.mips.com/LinuxDistro/nanomips/buildroot/index.html}.
+
+Download @code{} from
@url{https://mipsdistros.mips.com/LinuxDistro/nanomips/kernels/v4.15.18-432-gb2eb9a8b07a1-20180627102142/index.html}.
+
+Start system emulation of Malta board with nanoMIPS I7200 CPU:
+@example
+qemu-system-mipsel -cpu I7200 -kernel @code{} \
+-M malta -serial stdio -m @code{} -hda
@code{} \
+-append "mem=256m@@0x0 rw console=ttyS0 vga=cirrus vesa=0x111
root=/dev/sda"
+@end example
+
@node ARM System emulator
@section ARM System emulator
--
1.9.1
[Qemu-devel] [PATCH 2/2] docs/qemu-cpu-models: Add MIPS/nanoMIPS QEMU supported CPU models
From: Stefan Markovic
Add list of supported and preferred CPU models for MIPS32, MIPS64
and nanoMIPS hosts.
Signed-off-by: Stefan Markovic
---
docs/qemu-cpu-models.texi | 163 +-
1 file changed, 161 insertions(+), 2 deletions(-)
diff --git a/docs/qemu-cpu-models.texi b/docs/qemu-cpu-models.texi
index 1935f98..475d434 100644
--- a/docs/qemu-cpu-models.texi
+++ b/docs/qemu-cpu-models.texi
@@ -5,8 +5,9 @@ QEMU / KVM CPU model configuration
@c man begin DESCRIPTION
@menu
-* recommendations_cpu_models_x86:: Recommendations for KVM CPU model
configuration on x86 hosts
-* cpu_model_syntax_apps:: Syntax for configuring CPU models
+* recommendations_cpu_models_x86:: Recommendations for KVM CPU model
configuration on x86 hosts
+* recommendations_cpu_models_MIPS:: Supported CPU model configurations on MIPS
hosts
+* cpu_model_syntax_apps:: Syntax for configuring CPU models
@end menu
QEMU / KVM virtualization supports two ways to configure CPU models
@@ -368,6 +369,164 @@ hardware assisted virtualization, that should thus not be
required for
running virtual machines.
@end table
+@node recommendations_cpu_models_MIPS
+@subsection Supported CPU model configurations on MIPS hosts
+
+QEMU supports variety of MIPS CPU models:
+
+@menu
+* cpu_models_MIPS32:: Supported CPU models for MIPS32 hosts
+* cpu_models_MIPS64:: Supported CPU models for MIPS64 hosts
+* cpu_models_nanoMIPS:: Supported CPU models for nanoMIPS hosts
+* preferred_cpu_models_MIPS:: Preferred CPU models for MIPS hosts
+@end menu
+
+@node cpu_models_MIPS32
+@subsubsection Supported CPU models for MIPS32 hosts
+
+The following CPU models are supported for use on MIPS32 hosts. Administrators
/
+applications are recommended to use the CPU model that matches the generation
+of the host CPUs in use. In a deployment with a mixture of host CPU models
+between machines, if live migration compatibility is required, use the newest
+CPU model that is compatible across all desired hosts.
+
+@table @option
+@item @code{mips32r6-generic}
+
+MIPS32 Processor (Release 6, 2015)
+
+
+@item @code{P5600}
+
+MIPS32 Processor (P5600, 2014)
+
+
+@item @code{M14K}
+@item @code{M14Kc}
+
+MIPS32 Processor (M14K, 2009)
+
+
+@item @code{74Kf}
+
+MIPS32 Processor (74K, 2007)
+
+
+@item @code{34Kf}
+
+MIPS32 Processor (34K, 2006)
+
+
+@item @code{24Kc}
+@item @code{24KEc}
+@item @code{24Kf}
+
+MIPS32 Processor (24K, 2003)
+
+
+@item @code{4Kc}
+@item @code{4Km}
+@item @code{4KEcR1}
+@item @code{4KEmR1}
+@item @code{4KEc}
+@item @code{4KEm}
+
+MIPS32 Processor (4K, 1999)
+@end table
+
+@node cpu_models_MIPS64
+@subsubsection Supported CPU models for MIPS64 hosts
+
+The following CPU models are supported for use on MIPS64 hosts. Administrators
/
+applications are recommended to use the CPU model that matches the generation
+of the host CPUs in use. In a deployment with a mixture of host CPU models
+between machines, if live migration compatibility is required, use the newest
+CPU model that is compatible across all desired hosts.
+
+@table @option
+@item @code{I6400}
+
+MIPS64 Processor (Release 6, 2014)
+
+
+@item @code{Loongson-2F}
+
+MIPS64 Processor (Longsoon 2, 2008)
+
+
+@item @code{Loongson-2E}
+
+MIPS64 Processor (Loongson 2, 2006)
+
+
+@item @code{mips64dspr2}
+
+MIPS64 Processor (Release 2, 2006)
+
+
+@item @code{MIPS64R2-generic}
+@item @code{5KEc}
+@item @code{5KEf}
+
+MIPS64 Processor (Release 2, 2002)
+
+
+@item @code{20Kc}
+
+MIPS64 Processor (20K, 2000)
+
+
+@item @code{5Kc}
+@item @code{5Kf}
+
+MIPS64 Processor (5K, 1999)
+
+
+@item @code{VR5432}
+
+MIPS64 Processor (VR, 1998)
+
+
+@item @code{R4000}
+
+MIPS64 Processor (MIPS III, 1991)
+@end table
+
+@node cpu_models_nanoMIPS
+@subsubsection Supported CPU models for nanoMIPS hosts
+
+The following CPU models are supported for use on nanoMIPS hosts.
Administrators /
+applications are recommended to use the CPU model that matches the generation
+of the host CPUs in use. In a deployment with a mixture of host CPU models
+between machines, if live migration compatibility is required, use the newest
+CPU model that is compatible across all desired hosts.
+
+@table @option
+@item @code{I7200}
+
+MIPS I7200 (nanoMIPS, 2018)
+
+@end table
+
+@node preferred_cpu_models_MIPS
+@subsubsection Preferred CPU models for MIPS hosts
+
+The following CPU models are preferred for use on different MIPS hosts:
+
+@table @option
+@item @code{MIPS III}
+R4000
+
+@item @code{MIPS32R2}
+34Kf
+
+@item @code{MIPS64R6}
+I6400
+
+@item @code{nanoMIPS}
+I7200
+@end table
+
@node cpu_model_syntax_apps
@subsection Syntax for configuring CPU models
--
1.9.1
Re: [Qemu-devel] [PATCH 1/2] qemu-doc: Add nanoMIPS ISA information
Hi Philippe,
I'll investigate further running with --enable-debug option to fix this
issue.
In the meantime, we could note enable-debug as 'To Be Done/Work In
Progress' for nanoMIPS in qemu docs .
Thanks,
Stefan
On 28.11.18. 15:31, Philippe Mathieu-Daudé wrote:
> Hi Stefan,
>
> On 28/11/18 14:43, Stefan Markovic wrote:
>> From: Stefan Markovic
>>
>> Add nanoMIPS information in qemu-doc.texi with example of usage
>> included.
>>
>> Signed-off-by: Stefan Markovic
>> ---
>> qemu-doc.texi | 29 +
>> 1 file changed, 29 insertions(+)
>>
>> diff --git a/qemu-doc.texi b/qemu-doc.texi
>> index f7ad1df..6ef593d 100644
>> --- a/qemu-doc.texi
>> +++ b/qemu-doc.texi
>> @@ -1994,6 +1994,10 @@ Set the emulated machine type. The default is sun4u.
>> @section MIPS System emulator
>> @cindex system emulation (MIPS)
>>
>> +@menu
>> +* nanoMIPS System emulator ::
>> +@end menu
>> +
>> Four executables cover simulation of 32 and 64-bit MIPS systems in
>> both endian options, @file{qemu-system-mips}, @file{qemu-system-mipsel}
>> @file{qemu-system-mips64} and @file{qemu-system-mips64el}.
>> @@ -2085,6 +2089,31 @@ SCSI controller
>> G364 framebuffer
>> @end itemize
>>
>> +@node nanoMIPS System emulator
>> +@subsection nanoMIPS System emulator
>> +@cindex system emulation (nanoMIPS)
>> +
>> +Executable @file{qemu-system-mipsel} also covers simulation of
>> +32-bit nanoMIPS system in little endian mode:
>> +
>> +@itemize @minus
>> +@item
>> +nanoMIPS I7200 CPU
>> +@end itemize
>> +
>> +Example of @file{qemu-system-mipsel} usage for nanoMIPS is shown below:
>> +
>> +Download @code{} from
>> @url{https://mipsdistros.mips.com/LinuxDistro/nanomips/buildroot/index.html}.
>> +
>> +Download @code{} from
>> @url{https://mipsdistros.mips.com/LinuxDistro/nanomips/kernels/v4.15.18-432-gb2eb9a8b07a1-20180627102142/index.html}.
>> +
>> +Start system emulation of Malta board with nanoMIPS I7200 CPU:
>> +@example
>> +qemu-system-mipsel -cpu I7200 -kernel @code{} \
>> +-M malta -serial stdio -m @code{} -hda
>> @code{} \
>> +-append "mem=256m@@0x0 rw console=ttyS0 vga=cirrus vesa=0x111
>> root=/dev/sda"
> Trying your example with generic_nano32r6el_page64k_dbg current master
> (c56606684) I'm getting:
>
> IN: cgroup_init_early
> 0x8087ae64: 84f0 8050 LW a3, 0x50(s0)
> 0x8087ae68: a630 2c48 SWM s1, 72(s0), 0x2
> 0x8087ae6c: bb84 BNEZC a3, 0x8087ae72
>
> OP:
> ld_i32 tmp0,env,$0xffe4
> movi_i32 tmp1,$0x0
> brcond_i32 tmp0,tmp1,lt,$L0
>
> 8087ae64
> movi_i32 tmp0,$0x50
> add_i32 tmp0,s0,tmp0
> qemu_ld_i32 tmp0,tmp0,un+leul,0
> mov_i32 a3,tmp0
>
> 8087ae68
> movi_i32 tmp0,$0x48
> add_i32 tmp0,s0,tmp0
> mov_i32 tmp1,s1
> qemu_st_i32 tmp1,tmp0,leul,0
> movi_i32 tmp0,$0x4c
> add_i32 tmp0,s0,tmp0
> mov_i32 tmp1,s2
> qemu_st_i32 tmp1,tmp0,leul,0
>
> 8087ae6c
> mov_i32 tmp0,a3
> movi_i32 tmp1,$0x0
> setcond_i32 bcond,tmp0,tmp1,ne
> movi_i32 tmp0,$0x0
> brcond_i32 bcond,tmp0,ne,$L1
> goto_tb $0x1
> movi_i32 PC,$0x8087ae6e
> exit_tb $0x7f80a2005f01
> set_label $L1
> goto_tb $0x0
> movi_i32 PC,$0x8087ae72
> exit_tb $0x7f80a2005f00
> set_label $L0
> exit_tb $0x7f80a2005f03
>
> qemu-system-mipsel: tcg/tcg-op.c:2607: tcg_gen_goto_tb: Assertion
> `(tcg_ctx->goto_tb_issue_mask & (1 << idx)) == 0' failed.
>
> Richard said on IRC "it means that it has issued two goto_tb with the
> same idx."
>
> I built QEMU on a x86_64 host, using the following options:
>
> ./configure --disable-user \
> --enable-vnc-sasl --enable-trace-backends=log \
> --extra-cflags=-ggdb --enable-debug
>
> Regards,
>
> Phil.
>
>> +@end example
>> +
>>
>> @node ARM System emulator
>> @section ARM System emulator
>>
Re: [Qemu-devel] [PATCH 1/2] qemu-doc: Add nanoMIPS ISA information
Of course. Investigation is in progress. Thanks, Stefan On 29.11.18. 11:23, Peter Maydell wrote: > On Thu, 29 Nov 2018 at 10:18, Stefan Markovic wrote: >> I'll investigate further running with --enable-debug option to fix this >> issue. >> >> In the meantime, we could note enable-debug as 'To Be Done/Work In >> Progress' for nanoMIPS in qemu docs . > This isn't just "--enable-debug doesn't work", it means there's a > definite bug because you've tripped an assert (that's only enabled > in the debug config). It's quite possible that the code will misbehave > at runtime even on the non-debug config... > > thanks > -- PMM
Re: [Qemu-devel] [PATCH 2/2] avoid TABs in files that only contain a few
On 13.12.18. 23:37, Paolo Bonzini wrote: > Most files that have TABs only contain a handful of them. Change > them to spaces so that we don't confuse people. > > disas, standard-headers, linux-headers and libdecnumber are imported > from other projects and probably should be exempted from the check. > Outside those, after this patch the following files still contain both > 8-space and TAB sequences at the beginning of the line. Many of them > have a majority of TABs, or were initially committed with all tabs. > > bsd-user/i386/target_syscall.h > bsd-user/x86_64/target_syscall.h > crypto/aes.c > hw/audio/fmopl.c > hw/audio/fmopl.h > hw/block/tc58128.c > hw/display/cirrus_vga.c > hw/display/xenfb.c > hw/dma/etraxfs_dma.c > hw/intc/sh_intc.c > hw/misc/mst_fpga.c > hw/net/pcnet.c > hw/sh4/sh7750.c > hw/timer/m48t59.c > hw/timer/sh_timer.c > include/crypto/aes.h > include/disas/bfd.h > include/hw/sh4/sh.h > libdecnumber/decNumber.c > linux-headers/asm-generic/unistd.h > linux-headers/linux/kvm.h > linux-user/alpha/target_syscall.h > linux-user/arm/nwfpe/double_cpdo.c > linux-user/arm/nwfpe/fpa11_cpdt.c > linux-user/arm/nwfpe/fpa11_cprt.c > linux-user/arm/nwfpe/fpa11.h > linux-user/flat.h > linux-user/flatload.c > linux-user/i386/target_syscall.h > linux-user/ppc/target_syscall.h > linux-user/sparc/target_syscall.h > linux-user/syscall.c > linux-user/syscall_defs.h > linux-user/x86_64/target_syscall.h > slirp/cksum.c > slirp/if.c > slirp/ip.h > slirp/ip_icmp.c > slirp/ip_icmp.h > slirp/ip_input.c > slirp/ip_output.c > slirp/mbuf.c > slirp/misc.c > slirp/sbuf.c > slirp/socket.c > slirp/socket.h > slirp/tcp_input.c > slirp/tcpip.h > slirp/tcp_output.c > slirp/tcp_subr.c > slirp/tcp_timer.c > slirp/tftp.c > slirp/udp.c > slirp/udp.h > target/cris/cpu.h > target/cris/mmu.c > target/cris/op_helper.c > target/sh4/helper.c > target/sh4/op_helper.c > target/sh4/translate.c > tcg/sparc/tcg-target.inc.c > tests/tcg/cris/check_addo.c > tests/tcg/cris/check_moveq.c > tests/tcg/cris/check_swap.c > tests/tcg/multiarch/test-mmap.c > ui/vnc-enc-hextile-template.h > ui/vnc-enc-zywrle.h > util/envlist.c > util/readline.c > > The following have only TABs: > > bsd-user/i386/target_signal.h > bsd-user/sparc64/target_signal.h > bsd-user/sparc64/target_syscall.h > bsd-user/sparc/target_signal.h > bsd-user/sparc/target_syscall.h > bsd-user/x86_64/target_signal.h > crypto/desrfb.c > hw/audio/intel-hda-defs.h > hw/core/uboot_image.h > hw/sh4/sh7750_regnames.c > hw/sh4/sh7750_regs.h > include/hw/cris/etraxfs_dma.h > linux-user/alpha/termbits.h > linux-user/arm/nwfpe/fpopcode.h > linux-user/arm/nwfpe/fpsr.h > linux-user/arm/syscall_nr.h > linux-user/arm/target_signal.h > linux-user/cris/target_signal.h > linux-user/i386/target_signal.h > linux-user/linux_loop.h > linux-user/m68k/target_signal.h > linux-user/microblaze/target_signal.h > linux-user/mips64/target_signal.h > linux-user/mips/target_signal.h > linux-user/mips/target_syscall.h > linux-user/mips/termbits.h > linux-user/ppc/target_signal.h > linux-user/sh4/target_signal.h > linux-user/sh4/termbits.h > linux-user/sparc64/target_syscall.h > linux-user/sparc/target_signal.h > linux-user/x86_64/target_signal.h > linux-user/x86_64/termbits.h > pc-bios/optionrom/optionrom.h > slirp/mbuf.h > slirp/misc.h > slirp/sbuf.h > slirp/tcp.h > slirp/tcp_timer.h > slirp/tcp_var.h > target/i386/svm.h > target/sparc/asi.h > target/xtensa/core-dc232b/xtensa-modules.inc.c > target/xtensa/core-dc233c/xtensa-modules.inc.c > target/xtensa/core-de212/core-isa.h > target/xtensa/core-de212/xtensa-modules.inc.c > target/xtensa/core-fsf/xtensa-modules.inc.c > target/xtensa/core-sample_controller/core-isa.h > target/xtensa/core-sample_controller/xtensa-modules.inc.c > target/xtensa/core-test_kc705_be/core-isa.h > target/xtensa/core-test_kc705_be/xtensa-modules.inc.c > tests/tcg/cris/check_abs.c > tests/tcg/cris/check_addc.c > tests/tcg/cris/check_addcm.c > tests/tcg/cris/check_addoq.c &g
Re: [Qemu-devel] [PATCH v2 1/5] disas: nanoMIPS: Fix preamble text
On 17.12.18. 18:10, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Fix several mistakes in preambles of nanomips disassembler source
> files.
>
> Signed-off-by: Aleksandar Markovic
> ---
> disas/nanomips.cpp | 7 ---
> disas/nanomips.h | 7 ---
> 2 files changed, 8 insertions(+), 6 deletions(-)
Reviewed-by: Stefan Markovic
> diff --git a/disas/nanomips.cpp b/disas/nanomips.cpp
> index 1238c2ff33..f9ef0a25f4 100644
> --- a/disas/nanomips.cpp
> +++ b/disas/nanomips.cpp
> @@ -1,13 +1,13 @@
> /*
>* Source file for nanoMIPS disassembler component of QEMU
>*
> - * Copyright (C) 2018 Wave Computing
> + * Copyright (C) 2018 Wave Computing, Inc.
>* Copyright (C) 2018 Matthew Fortune
> - * Copyright (C) 2018 Aleksandar Markovic
>
> + * Copyright (C) 2018 Aleksandar Markovic
>*
>* This program is free software: you can redistribute it and/or modify
>* it under the terms of the GNU General Public License as published by
> - * the Free Software Foundation, either version 3 of the License, or
> + * the Free Software Foundation, either version 2 of the License, or
>* (at your option) any later version.
>*
>* This program is distributed in the hope that it will be useful,
> @@ -17,6 +17,7 @@
>*
>* You should have received a copy of the GNU General Public License
>* along with this program. If not, see <https://www.gnu.org/licenses/>.
> + *
>*/
>
> extern "C" {
> diff --git a/disas/nanomips.h b/disas/nanomips.h
> index 84cc9a6dfc..3df138d63f 100644
> --- a/disas/nanomips.h
> +++ b/disas/nanomips.h
> @@ -1,13 +1,13 @@
> /*
>* Header file for nanoMIPS disassembler component of QEMU
>*
> - * Copyright (C) 2018 Wave Computing
> + * Copyright (C) 2018 Wave Computing, Inc.
>* Copyright (C) 2018 Matthew Fortune
> - * Copyright (C) 2018 Aleksandar Markovic
>
> + * Copyright (C) 2018 Aleksandar Markovic
>*
>* This program is free software: you can redistribute it and/or modify
>* it under the terms of the GNU General Public License as published by
> - * the Free Software Foundation, either version 3 of the License, or
> + * the Free Software Foundation, either version 2 of the License, or
>* (at your option) any later version.
>*
>* This program is distributed in the hope that it will be useful,
> @@ -17,6 +17,7 @@
>*
>* You should have received a copy of the GNU General Public License
>* along with this program. If not, see <https://www.gnu.org/licenses/>.
> + *
>*/
>
> #ifndef NANOMIPS_DISASSEMBLER_H
Re: [Qemu-devel] [PATCH v2 3/5] disas: nanoMIPS: Fix a function misnomer
On 17.12.18. 18:10, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Fix wrong name of a function. The convention in this file is that
> names of extraction functions should reflect bit patterns they are
> extracting.
>
> Signed-off-by: Aleksandar Markovic
> ---
> disas/nanomips.cpp | 264 ++---
> disas/nanomips.h | 2 +-
> 2 files changed, 133 insertions(+), 133 deletions(-)
Reviewed-by: Stefan Markovic
> diff --git a/disas/nanomips.cpp b/disas/nanomips.cpp
> index 935c2dee3c..cfad1ec845 100644
> --- a/disas/nanomips.cpp
> +++ b/disas/nanomips.cpp
> @@ -1391,7 +1391,7 @@ uint64 NMD::extr_uil2il2bs16Fmsb17(uint64 instruction)
> }
>
>
> -uint64 NMD::extract_rd_20_19_18_17_16(uint64 instruction)
> +uint64 NMD::extract_rd_15_14_13_12_11(uint64 instruction)
> {
> uint64 value = 0;
> value |= extract_bits(instruction, 11, 5);
> @@ -1579,7 +1579,7 @@ bool NMD::PREFE_cond(uint64 instruction)
>
> bool NMD::SLTU_cond(uint64 instruction)
> {
> -uint64 rd = extract_rd_20_19_18_17_16(instruction);
> +uint64 rd = extract_rd_15_14_13_12_11(instruction);
> return rd != 0;
> }
>
> @@ -1727,7 +1727,7 @@ std::string NMD::ACLR(uint64 instruction)
> std::string NMD::ADD(uint64 instruction)
> {
> uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
> -uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
> +uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
> uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
>
> std::string rd = GPR(copy(rd_value));
> @@ -2039,7 +2039,7 @@ std::string NMD::ADDIUPC_48_(uint64 instruction)
> std::string NMD::ADDQ_PH(uint64 instruction)
> {
> uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
> -uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
> +uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
> uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
>
> std::string rd = GPR(copy(rd_value));
> @@ -2063,7 +2063,7 @@ std::string NMD::ADDQ_PH(uint64 instruction)
> std::string NMD::ADDQ_S_PH(uint64 instruction)
> {
> uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
> -uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
> +uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
> uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
>
> std::string rd = GPR(copy(rd_value));
> @@ -2087,7 +2087,7 @@ std::string NMD::ADDQ_S_PH(uint64 instruction)
> std::string NMD::ADDQ_S_W(uint64 instruction)
> {
> uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
> -uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
> +uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
> uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
>
> std::string rd = GPR(copy(rd_value));
> @@ -2112,7 +2112,7 @@ std::string NMD::ADDQ_S_W(uint64 instruction)
> std::string NMD::ADDQH_PH(uint64 instruction)
> {
> uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
> -uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
> +uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
> uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
>
> std::string rd = GPR(copy(rd_value));
> @@ -2137,7 +2137,7 @@ std::string NMD::ADDQH_PH(uint64 instruction)
> std::string NMD::ADDQH_R_PH(uint64 instruction)
> {
> uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
> -uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
> +uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
> uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
>
> std::string rd = GPR(copy(rd_value));
> @@ -2161,7 +2161,7 @@ std::string NMD::ADDQH_R_PH(uint64 instruction)
> std::string NMD::ADDQH_R_W(uint64 instruction)
> {
> uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
> -uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
> +uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
> uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
>
> std::string rd = GPR(copy(rd_value));
> @@ -2185,7 +2185,7 @@ std::string NMD::ADDQH_R_W(uint64 instruction)
> std::string NMD::ADDQH_W(uint64 instruction)
> {
> uint64 rt_value = extract_rt_25_24_23_22_21(instruction);
> -uint64 rd_value = extract_rd_20_19_18_17_16(instruction);
> +uint64 rd_value = extract_rd_15_14_13_12_11(instruction);
> uint64 rs_value = extract_rs_20_19_18_17_16(instruction);
>
>
Re: [Qemu-devel] [PATCH v2 5/5] disas: nanoMIPS: Name some function in a more descriptive way
On 17.12.18. 18:10, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Rename some functions that have names hard to understand.
>
> Signed-off-by: Aleksandar Markovic
> ---
> disas/nanomips.cpp | 112 ++---
> disas/nanomips.h | 32 ++---
> 2 files changed, 72 insertions(+), 72 deletions(-)
Reviewed-by: Stefan Markovic
> diff --git a/disas/nanomips.cpp b/disas/nanomips.cpp
> index 9e876305f1..477df84d93 100644
> --- a/disas/nanomips.cpp
> +++ b/disas/nanomips.cpp
> @@ -683,7 +683,7 @@ uint64 NMD::extract_shift3_2_1_0(uint64 instruction)
> }
>
>
> -uint64 NMD::extr_uil3il3bs9Fmsb11(uint64 instruction)
> +uint64 NMD::extract_u_11_10_9_8_7_6_5_4_3__s3(uint64 instruction)
> {
> uint64 value = 0;
> value |= extract_bits(instruction, 3, 9) << 3;
> @@ -707,7 +707,7 @@ uint64 NMD::extract_rtz3_9_8_7(uint64 instruction)
> }
>
>
> -uint64 NMD::extr_uil1il1bs17Fmsb17(uint64 instruction)
> +uint64 NMD::extract_u_17_to_1__s1(uint64 instruction)
> {
> uint64 value = 0;
> value |= extract_bits(instruction, 1, 17) << 1;
> @@ -767,7 +767,7 @@ uint64 NMD::extract_shift_4_3_2_1_0(uint64 instruction)
> }
>
>
> -uint64 NMD::extr_shiftxil7il1bs4Fmsb4(uint64 instruction)
> +uint64 NMD::extract_shiftx_10_9_8_7__s1(uint64 instruction)
> {
> uint64 value = 0;
> value |= extract_bits(instruction, 7, 4) << 1;
> @@ -836,7 +836,7 @@ uint64 NMD::extract_rs_20_19_18_17_16(uint64 instruction)
> }
>
>
> -uint64 NMD::extr_uil1il1bs2Fmsb2(uint64 instruction)
> +uint64 NMD::extract_u_2_1__s1(uint64 instruction)
> {
> uint64 value = 0;
> value |= extract_bits(instruction, 1, 2) << 1;
> @@ -934,7 +934,7 @@ uint64 NMD::extract_rs_4_3_2_1_0(uint64 instruction)
> }
>
>
> -uint64 NMD::extr_uil3il3bs18Fmsb20(uint64 instruction)
> +uint64 NMD::extract_u_20_to_3__s3(uint64 instruction)
> {
> uint64 value = 0;
> value |= extract_bits(instruction, 3, 18) << 3;
> @@ -942,7 +942,7 @@ uint64 NMD::extr_uil3il3bs18Fmsb20(uint64 instruction)
> }
>
>
> -uint64 NMD::extr_uil0il2bs4Fmsb5(uint64 instruction)
> +uint64 NMD::extract_u_3_2_1_0__s2(uint64 instruction)
> {
> uint64 value = 0;
> value |= extract_bits(instruction, 0, 4) << 2;
> @@ -958,7 +958,7 @@ uint64 NMD::extract_cofun_25_24_23(uint64 instruction)
> }
>
>
> -uint64 NMD::extr_uil0il2bs3Fmsb4(uint64 instruction)
> +uint64 NMD::extract_u_2_1_0__s2(uint64 instruction)
> {
> uint64 value = 0;
> value |= extract_bits(instruction, 0, 3) << 2;
> @@ -1225,7 +1225,7 @@ uint64 NMD::extract_msbt_10_9_8_7_6(uint64 instruction)
> }
>
>
> -uint64 NMD::extr_uil0il2bs6Fmsb7(uint64 instruction)
> +uint64 NMD::extract_u_5_4_3_2_1_0__s2(uint64 instruction)
> {
> uint64 value = 0;
> value |= extract_bits(instruction, 0, 6) << 2;
> @@ -1259,7 +1259,7 @@ uint64 NMD::extract_rs3_6_5_4(uint64 instruction)
> }
>
>
> -uint64 NMD::extr_uil0il32bs32Fmsb63(uint64 instruction)
> +uint64 NMD::extract_u_31_to_0__s32(uint64 instruction)
> {
> uint64 value = 0;
> value |= extract_bits(instruction, 0, 32) << 32;
> @@ -1307,7 +1307,7 @@ uint64 NMD::extract_op_25_24_23_22_21(uint64
> instruction)
> }
>
>
> -uint64 NMD::extr_uil0il2bs7Fmsb8(uint64 instruction)
> +uint64 NMD::extract_u_6_5_4_3_2_1_0__s2(uint64 instruction)
> {
> uint64 value = 0;
> value |= extract_bits(instruction, 0, 7) << 2;
> @@ -1339,7 +1339,7 @@ uint64 NMD::extract_eu_3_2_1_0(uint64 instruction)
> }
>
>
> -uint64 NMD::extr_uil4il4bs4Fmsb7(uint64 instruction)
> +uint64 NMD::extract_u_7_6_5_4__s4(uint64 instruction)
> {
> uint64 value = 0;
> value |= extract_bits(instruction, 4, 4) << 4;
> @@ -1383,7 +1383,7 @@ uint64 NMD::extract_u_20_19_18_17_16_15_14_13(uint64
> instruction)
> }
>
>
> -uint64 NMD::extr_uil2il2bs16Fmsb17(uint64 instruction)
> +uint64 NMD::extract_u_17_to_2__s2(uint64 instruction)
> {
> uint64 value = 0;
> value |= extract_bits(instruction, 2, 16) << 2;
> @@ -1433,7 +1433,7 @@ uint64 NMD::extract_u_1_0(uint64 instruction)
> }
>
>
> -uint64 NMD::extr_uil3il3bs1_il8il2bs1Fmsb3(uint64 instruction)
> +uint64 NMD::extract_u_3_8__s2(uint64 instruction)
> {
> uint64 value = 0;
> value |= extract_bits(instruction, 3, 1) << 3;
> @@ -1450,7 +1450,7 @@ uint64 NMD::extract_fd_10_9_8_7_6(uint64 instruction)
> }
>
>
> -ui
Re: [Qemu-devel] [PATCH v2 2/5] disas: nanoMIPS: Remove functions that are not used
On 17.12.18. 18:10, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Some functions were not used at all. Compiler doesn't complain
> since they are class memebers. Remove them - no future usage is
> planned.
>
> Signed-off-by: Aleksandar Markovic
> ---
> disas/nanomips.cpp | 208 -
> disas/nanomips.h | 25 --
> 2 files changed, 233 deletions(-)
Reviewed-by: Stefan Markovic
> diff --git a/disas/nanomips.cpp b/disas/nanomips.cpp
> index f9ef0a25f4..935c2dee3c 100644
> --- a/disas/nanomips.cpp
> +++ b/disas/nanomips.cpp
> @@ -852,23 +852,6 @@ uint64 NMD::extract_stripe_6(uint64 instruction)
> }
>
>
> -uint64 NMD::extr_xil17il0bs1Fmsb0(uint64 instruction)
> -{
> -uint64 value = 0;
> -value |= extract_bits(instruction, 17, 1);
> -return value;
> -}
> -
> -
> -uint64 NMD::extr_xil2il0bs1_il15il0bs1Fmsb0(uint64 instruction)
> -{
> -uint64 value = 0;
> -value |= extract_bits(instruction, 2, 1);
> -value |= extract_bits(instruction, 15, 1);
> -return value;
> -}
> -
> -
> uint64 NMD::extract_ac_13_12(uint64 instruction)
> {
> uint64 value = 0;
> @@ -919,14 +902,6 @@ uint64 NMD::extract_shift_5_4_3_2_1_0(uint64 instruction)
> }
>
>
> -uint64 NMD::extr_xil10il0bs6Fmsb5(uint64 instruction)
> -{
> -uint64 value = 0;
> -value |= extract_bits(instruction, 10, 6);
> -return value;
> -}
> -
> -
> uint64 NMD::extract_count_19_18_17_16(uint64 instruction)
> {
> uint64 value = 0;
> @@ -943,15 +918,6 @@ uint64 NMD::extract_code_2_1_0(uint64 instruction)
> }
>
>
> -uint64 NMD::extr_xil10il0bs4_il22il0bs4Fmsb3(uint64 instruction)
> -{
> -uint64 value = 0;
> -value |= extract_bits(instruction, 10, 4);
> -value |= extract_bits(instruction, 22, 4);
> -return value;
> -}
> -
> -
> uint64 NMD::extract_u_11_10_9_8_7_6_5_4_3_2_1_0(uint64 instruction)
> {
> uint64 value = 0;
> @@ -976,14 +942,6 @@ uint64 NMD::extr_uil3il3bs18Fmsb20(uint64 instruction)
> }
>
>
> -uint64 NMD::extr_xil12il0bs1Fmsb0(uint64 instruction)
> -{
> -uint64 value = 0;
> -value |= extract_bits(instruction, 12, 1);
> -return value;
> -}
> -
> -
> uint64 NMD::extr_uil0il2bs4Fmsb5(uint64 instruction)
> {
> uint64 value = 0;
> @@ -1008,14 +966,6 @@ uint64 NMD::extr_uil0il2bs3Fmsb4(uint64 instruction)
> }
>
>
> -uint64 NMD::extr_xil10il0bs1Fmsb0(uint64 instruction)
> -{
> -uint64 value = 0;
> -value |= extract_bits(instruction, 10, 1);
> -return value;
> -}
> -
> -
> uint64 NMD::extract_rd3_3_2_1(uint64 instruction)
> {
> uint64 value = 0;
> @@ -1048,22 +998,6 @@ uint64 NMD::extract_ru_7_6_5_4_3(uint64 instruction)
> }
>
>
> -uint64 NMD::extr_xil21il0bs5Fmsb4(uint64 instruction)
> -{
> -uint64 value = 0;
> -value |= extract_bits(instruction, 21, 5);
> -return value;
> -}
> -
> -
> -uint64 NMD::extr_xil9il0bs3Fmsb2(uint64 instruction)
> -{
> -uint64 value = 0;
> -value |= extract_bits(instruction, 9, 3);
> -return value;
> -}
> -
> -
> uint64 NMD::extract_u_17_to_0(uint64 instruction)
> {
> uint64 value = 0;
> @@ -1072,15 +1006,6 @@ uint64 NMD::extract_u_17_to_0(uint64 instruction)
> }
>
>
> -uint64 NMD::extr_xil14il0bs1_il15il0bs1Fmsb0(uint64 instruction)
> -{
> -uint64 value = 0;
> -value |= extract_bits(instruction, 14, 1);
> -value |= extract_bits(instruction, 15, 1);
> -return value;
> -}
> -
> -
> uint64 NMD::extract_rsz4_4_2_1_0(uint64 instruction)
> {
> uint64 value = 0;
> @@ -1090,14 +1015,6 @@ uint64 NMD::extract_rsz4_4_2_1_0(uint64 instruction)
> }
>
>
> -uint64 NMD::extr_xil24il0bs1Fmsb0(uint64 instruction)
> -{
> -uint64 value = 0;
> -value |= extract_bits(instruction, 24, 1);
> -return value;
> -}
> -
> -
> int64 NMD::extr_sil0il21bs1_il1il1bs20Tmsb21(uint64 instruction)
> {
> int64 value = 0;
> @@ -1150,15 +1067,6 @@ int64 NMD::extract_shift_21_20_19_18_17_16(uint64
> instruction)
> }
>
>
> -uint64 NMD::extr_xil6il0bs3_il10il0bs1Fmsb2(uint64 instruction)
> -{
> -uint64 value = 0;
> -value |= extract_bits(instruction, 6, 3);
> -value |= extract_bits(instruction, 10, 1);
> -return value;
> -}
> -
> -
> uint64 NMD::extract_rd2_3_8(uint64 instruction)
> {
> uint64 value = 0;
> @@ -1168,14 +1076,6 @@ uint64 NMD::extract_rd2_3_8(uint64 instruction)
>
Re: [Qemu-devel] [PATCH 1/6] target/mips: MXU: Add missing opcodes/decoding for LX* instructions
On 17.12.18. 21:04, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Add missing opcodes and decoding engine for LXB, LXH, LXW, LXBU,
> and LXHU instructions. They were for some reason forgotten in
> previous commits. The MXU opcode list and decoding engine should
> be now complete.
>
> Signed-off-by: Aleksandar Markovic
> ---
> target/mips/translate.c | 140 +---
> 1 file changed, 102 insertions(+), 38 deletions(-)
Reviewed-by: Stefan Markovic
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index e9c23a594b..e0c8d8c2f7 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -1663,12 +1663,21 @@ enum {
>* │ 20..18
>* ├─ 100111 ─ OPC_MXU__POOL16 ─┬─ 000 ─ OPC_MXU_D32SARW
>* │├─ 001 ─ OPC_MXU_S32ALN
> - * ├─ 101000 ─ OPC_MXU_LXB ├─ 010 ─ OPC_MXU_S32ALNI
> - * ├─ 101001 ─├─ 011 ─ OPC_MXU_S32NOR
> - * ├─ 101010 ─ OPC_MXU_S16LDD ├─ 100 ─ OPC_MXU_S32AND
> - * ├─ 101011 ─ OPC_MXU_S16STD ├─ 101 ─ OPC_MXU_S32OR
> - * ├─ 101100 ─ OPC_MXU_S16LDI ├─ 110 ─ OPC_MXU_S32XOR
> - * ├─ 101101 ─ OPC_MXU_S16SDI └─ 111 ─ OPC_MXU_S32LUI
> + * │├─ 010 ─ OPC_MXU_S32ALNI
> + * │├─ 011 ─ OPC_MXU_S32NOR
> + * │├─ 100 ─ OPC_MXU_S32AND
> + * │├─ 101 ─ OPC_MXU_S32OR
> + * │├─ 110 ─ OPC_MXU_S32XOR
> + * │└─ 111 ─ OPC_MXU_S32LUI
> + * │
> + * │ 7..5
> + * ├─ 101000 ─ OPC_MXU__POOL17 ─┬─ 000 ─ OPC_MXU_LXB
> + * │├─ 001 ─ OPC_MXU_LXH
> + * ├─ 101001 ─├─ 011 ─ OPC_MXU_LXW
> + * ├─ 101010 ─ OPC_MXU_S16LDD ├─ 100 ─ OPC_MXU_LXBU
> + * ├─ 101011 ─ OPC_MXU_S16STD └─ 101 ─ OPC_MXU_LXHU
> + * ├─ 101100 ─ OPC_MXU_S16LDI
> + * ├─ 101101 ─ OPC_MXU_S16SDI
>* ├─ 101110 ─ OPC_MXU_S32M2I
>* ├─ 10 ─ OPC_MXU_S32I2M
>* ├─ 11 ─ OPC_MXU_D32SLL
> @@ -1678,15 +1687,15 @@ enum {
>* ├─ 110100 ─ OPC_MXU_Q16SLL ├─ 010 ─ OPC_MXU_D32SARV
>* ├─ 110101 ─ OPC_MXU_Q16SLR ├─ 011 ─ OPC_MXU_Q16SLLV
>* │├─ 100 ─ OPC_MXU_Q16SLRV
> - * ├─ 110110 ─ OPC_MXU__POOL17 ─┴─ 101 ─ OPC_MXU_Q16SARV
> + * ├─ 110110 ─ OPC_MXU__POOL18 ─┴─ 101 ─ OPC_MXU_Q16SARV
>* │
>* ├─ 110111 ─ OPC_MXU_Q16SAR
>* │ 23..22
> - * ├─ 111000 ─ OPC_MXU__POOL18 ─┬─ 00 ─ OPC_MXU_Q8MUL
> + * ├─ 111000 ─ OPC_MXU__POOL19 ─┬─ 00 ─ OPC_MXU_Q8MUL
>* │└─ 01 ─ OPC_MXU_Q8MULSU
>* │
>* │ 20..18
> - * ├─ 111001 ─ OPC_MXU__POOL19 ─┬─ 000 ─ OPC_MXU_Q8MOVZ
> + * ├─ 111001 ─ OPC_MXU__POOL20 ─┬─ 000 ─ OPC_MXU_Q8MOVZ
>* │├─ 001 ─ OPC_MXU_Q8MOVN
>* │├─ 010 ─ OPC_MXU_D16MOVZ
>* │├─ 011 ─ OPC_MXU_D16MOVN
> @@ -1694,7 +1703,7 @@ enum {
>* │└─ 101 ─ OPC_MXU_S32MOV
>* │
>* │ 23..22
> - * ├─ 111010 ─ OPC_MXU__POOL20 ─┬─ 00 ─ OPC_MXU_Q8MAC
> + * ├─ 111010 ─ OPC_MXU__POOL21 ─┬─ 00 ─ OPC_MXU_Q8MAC
>* │└─ 10 ─ OPC_MXU_Q8MACSU
>* ├─ 111011 ─ OPC_MXU_Q16SCOP
>* ├─ 00 ─ OPC_MXU_Q8MADL
> @@ -1750,7 +1759,7 @@ enum {
> OPC_MXU_S8SDI= 0x25,
> OPC_MXU__POOL15 = 0x26,
> OPC_MXU__POOL16 = 0x27,
> -OPC_MXU_LXB = 0x28,
> +OPC_MXU__POOL17 = 0x28,
> /* not assigned 0x29 */
> OPC_MXU_S16LDD = 0x2A,
> OPC_MXU_S16STD = 0x2B,
> @@ -1764,11 +1773,11 @@ enum {
> OPC_MXU_D32SAR = 0x33,
> OPC_MXU_Q16SLL = 0x34,
> OPC_MXU_Q16SLR = 0x35,
> -OPC_MXU__POOL17 = 0x36,
> +OPC_MXU__POOL18 = 0x36,
> OPC_MXU_Q16SAR = 0x37,
> -OPC_MXU__POOL18 = 0x38,
> -OPC_MXU__POOL19 = 0x39,
> -OPC_MXU__POOL20 = 0x3A,
> +OPC_MXU__POOL19 = 0x38,
> +OPC_MXU__POOL20 = 0x39,
> +OPC_MXU__POOL21 = 0x3A,
> OPC_MXU_Q16SCOP = 0x3B,
> OPC_MXU_Q8MADL = 0x3C,
> OPC_MXU_S32SFL = 0x3D,
> @@ -1940,6 +1949,1
Re: [Qemu-devel] [PATCH 4/6] target/mips: MXU: Add handlers for logic instructions
On 17.12.18. 21:04, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Add translation handlers for logic MXU instructions.
>
> Signed-off-by: Aleksandar Markovic
> ---
> target/mips/translate.c | 182 +---
> 1 file changed, 170 insertions(+), 12 deletions(-)
Reviewed-by: Stefan Markovic
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index e3a5a73e59..c74a831a17 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -24649,6 +24649,172 @@ static void gen_mxu_s32ldd_s32lddr(DisasContext
> *ctx)
> }
>
>
> +/*
> + * MXU instruction category: logic
> + * ~~~
> + *
> + * S32NORS32ANDS32ORS32XOR
> + */
> +
> +/*
> + * S32NOR XRa, XRb, XRc
> + *Update XRa with the result of logical bitwise 'nor' operation
> + *applied to the content of XRb and XRc.
> + *
> + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
> + * +---+-+-+---+---+---+---+
> + * | SPECIAL2 |0 0 0 0 0| opc | XRc | XRb | XRa |MXU__POOL16|
> + * +---+-+-+---+---+---+---+
> + */
> +static void gen_mxu_S32NOR(DisasContext *ctx)
> +{
> +uint32_t pad, XRc, XRb, XRa;
> +
> +pad = extract32(ctx->opcode, 21, 5);
> +XRc = extract32(ctx->opcode, 14, 4);
> +XRb = extract32(ctx->opcode, 10, 4);
> +XRa = extract32(ctx->opcode, 6, 4);
> +
> +if (unlikely(pad != 0)) {
> +/* opcode padding incorrect -> do nothing */
> +} else if (unlikely(XRa == 0)) {
> +/* destination is zero register -> do nothing */
> +} else if (unlikely((XRb == 0) && (XRc == 0))) {
> +/* both operands zero registers -> just set destination to all 1s */
> +tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0x);
> +} else if (unlikely(XRb == 0)) {
> +/* XRb zero register -> just set destination to the negation of XRc
> */
> +tcg_gen_not_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1]);
> +} else if (unlikely(XRc == 0)) {
> +/* XRa zero register -> just set destination to the negation of XRb
> */
> +tcg_gen_not_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);
> +} else if (unlikely(XRb == XRc)) {
> +/* both operands same -> just set destination to the negation of XRb
> */
> +tcg_gen_not_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);
> +} else {
> +/* the most general case */
> +tcg_gen_nor_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], mxu_gpr[XRc -
> 1]);
> +}
> +}
> +
> +/*
> + * S32AND XRa, XRb, XRc
> + *Update XRa with the result of logical bitwise 'and' operation
> + *applied to the content of XRb and XRc.
> + *
> + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
> + * +---+-+-+---+---+---+---+
> + * | SPECIAL2 |0 0 0 0 0| opc | XRc | XRb | XRa |MXU__POOL16|
> + * +---+-+-+---+---+---+---+
> + */
> +static void gen_mxu_S32AND(DisasContext *ctx)
> +{
> +uint32_t pad, XRc, XRb, XRa;
> +
> +pad = extract32(ctx->opcode, 21, 5);
> +XRc = extract32(ctx->opcode, 14, 4);
> +XRb = extract32(ctx->opcode, 10, 4);
> +XRa = extract32(ctx->opcode, 6, 4);
> +
> +if (unlikely(pad != 0)) {
> +/* opcode padding incorrect -> do nothing */
> +} else if (unlikely(XRa == 0)) {
> +/* destination is zero register -> do nothing */
> +} else if (unlikely((XRb == 0) || (XRc == 0))) {
> +/* one of operands zero register -> just set destination to all 0s */
> +tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0);
> +} else if (unlikely(XRb == XRc)) {
> +/* both operands same -> just set destination to one of them */
> +tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);
> +} else {
> +/* the most general case */
> +tcg_gen_and_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], mxu_gpr[XRc -
> 1]);
> +}
> +}
> +
> +/*
> + * S32OR XRa, XRb, XRc
> + *Update XRa with the result of logical bitwise 'or' operation
> + *applied to the content of XRb and XRc.
> + *
> + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
> + * +---+-+-+---+---+---+---+
> + * | SPECIAL2 |0 0 0 0 0| opc | XRc | XRb | XRa |MXU__POOL16|
> + * +---+-+--+--+---+---+---+---+
> + */
> +static
Re: [Qemu-devel] [PATCH 3/6] target/mips: MXU: Improve textual description
On 17.12.18. 21:04, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Improve textual description of MXU extension. These are mostly
> comment formatting changes.
>
> Signed-off-by: Aleksandar Markovic
> ---
> target/mips/translate.c | 74 -
> 1 file changed, 44 insertions(+), 30 deletions(-)
Reviewed-by: Stefan Markovic
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index 74d16ce52e..e3a5a73e59 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -1399,10 +1399,12 @@ enum {
>
>
> /*
> - *AN OVERVIEW OF MXU EXTENSION INSTRUCTION SET
> - *
>*
> - * MXU (full name: MIPS eXtension/enhanced Unit) is an SIMD extension of
> MIPS32
> + * AN OVERVIEW OF MXU EXTENSION INSTRUCTION SET
> + *
> + *
> + *
> + * MXU (full name: MIPS eXtension/enhanced Unit) is a SIMD extension of
> MIPS32
>* instructions set. It is designed to fit the needs of signal, graphical
> and
>* video processing applications. MXU instruction set is used in Xburst
> family
>* of microprocessors by Ingenic.
> @@ -1410,39 +1412,31 @@ enum {
>* MXU unit contains 17 registers called X0-X16. X0 is always zero, and X16
> is
>* the control register.
>*
> - * The notation used in MXU assembler mnemonics
> - *
>*
> - * Registers:
> + * The notation used in MXU assembler mnemonics
> + *
> + *
> + * Register operands:
>*
>* XRa, XRb, XRc, XRd - MXU registers
>* Rb, Rc, Rd, Rs, Rt - general purpose MIPS registers
>*
> - * Subfields:
> + * Non-register operands:
>*
> - * aptn1 - 1-bit accumulate add/subtract pattern
> - * aptn2 - 2-bit accumulate add/subtract pattern
> - * eptn2 - 2-bit execute add/subtract pattern
> - * optn2 - 2-bit operand pattern
> - * optn3 - 3-bit operand pattern
> - * sft4 - 4-bit shift amount
> - * strd2 - 2-bit stride amount
> + * aptn1 - 1-bit accumulate add/subtract pattern
> + * aptn2 - 2-bit accumulate add/subtract pattern
> + * eptn2 - 2-bit execute add/subtract pattern
> + * optn2 - 2-bit operand pattern
> + * optn3 - 3-bit operand pattern
> + * sft4 - 4-bit shift amount
> + * strd2 - 2-bit stride amount
>*
>* Prefixes:
>*
> - *
> - * S 32
> - * D 16
> - * Q 8
> - *
> - * Suffixes:
> - *
> - * E - Expand results
> - * F - Fixed point multiplication
> - * L - Low part result
> - * R - Doing rounding
> - * V - Variable instead of immediate
> - * W - Combine above L and V
> + * Level of parallelism:Operand size:
> + *S - single operation at a time 32 - word
> + *D - two operations in parallel 16 - half word
> + *Q - four operations in parallel 8 - byte
>*
>* Operations:
>*
> @@ -1486,6 +1480,19 @@ enum {
>* SCOP - Calculate x’s scope (-1, means x<0; 0, means x==0; 1, means
> x>0)
>* XOR - Logical bitwise 'exclusive or' operation
>*
> + * Suffixes:
> + *
> + * E - Expand results
> + * F - Fixed point multiplication
> + * L - Low part result
> + * R - Doing rounding
> + * V - Variable instead of immediate
> + * W - Combine above L and V
> + *
> + *
> + * The list of MXU instructions grouped by functionality
> + * ~
> + *
>* Load/Store instructions Multiplication instructions
>* --- ---
>*
> @@ -1563,6 +1570,13 @@ enum {
>* Q16SAT XRa, XRb, XRc S32I2M XRa, Rb
>*
>*
> + * The opcode organization of MXU instructions
> + * ~~~
> + *
> + * The bits 31..26 of all MXU instructions are equal to 0x1C (also referred
> + * as opcode SPECIAL2 in the base MIPS ISA). The organization and meaning of
> + * other bits up to the instruction level is as follows:
> + *
>* bits
>* 05..00
>*
> @@ -1700,7 +1714,7 @@ enum {
>* │├─ 010 ─ OPC_MXU_D16MOVZ
>* │├─ 011 ─ OPC_MXU_D16MOVN
>* │
Re: [Qemu-devel] [PATCH 5/6] target/mips: MXU: Add handlers for max/min instructions
On 17.12.18. 21:04, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Add translation handlers for max/min MXU instructions.
>
> Signed-off-by: Aleksandar Markovic
> ---
> target/mips/translate.c | 356 +---
> 1 file changed, 335 insertions(+), 21 deletions(-)
Reviewed-by: Stefan Markovic
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index c74a831a17..339de8c32b 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -24815,6 +24815,338 @@ static void gen_mxu_S32XOR(DisasContext *ctx)
> }
>
>
> +/*
> + * MXU instruction category max/min
> + *
> + *
> + * S32MAX D16MAX Q8MAX
> + * S32MIN D16MIN Q8MIN
> + */
> +
> +/*
> + * S32MAX XRa, XRb, XRc
> + *Update XRa with the maximum of signed 32-bit integers contained
> + *in XRb and XRc.
> + *
> + * S32MIN XRa, XRb, XRc
> + *Update XRa with the minimum of signed 32-bit integers contained
> + *in XRb and XRc.
> + *
> + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
> + * +---+-+-+---+---+---+---+
> + * | SPECIAL2 |0 0 0 0 0| opc | XRc | XRb | XRa |MXU__POOL00|
> + * +---+-+-+---+---+---+---+
> + */
> +static void gen_mxu_S32MAX_S32MIN(DisasContext *ctx)
> +{
> +uint32_t pad, opc, XRc, XRb, XRa;
> +
> +pad = extract32(ctx->opcode, 21, 5);
> +opc = extract32(ctx->opcode, 18, 3);
> +XRc = extract32(ctx->opcode, 14, 4);
> +XRb = extract32(ctx->opcode, 10, 4);
> +XRa = extract32(ctx->opcode, 6, 4);
> +
> +if (unlikely(pad != 0)) {
> +/* opcode padding incorrect -> do nothing */
> +} else if (unlikely(XRa == 0)) {
> +/* destination is zero register -> do nothing */
> +} else if (unlikely((XRb == 0) && (XRc == 0))) {
> +/* both operands zero registers -> just set destination to zero */
> +tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0);
> +} else if (unlikely((XRb == 0) || (XRc == 0))) {
> +/* exactly one operand is zero register - find which one is not...*/
> +uint32_t XRx = XRb ? XRb : XRc;
> +/* ...and do max/min operation with one operand 0 */
> +if (opc == OPC_MXU_S32MAX) {
> +tcg_gen_smax_i32(mxu_gpr[XRa - 1], mxu_gpr[XRx - 1], 0);
> +} else {
> +tcg_gen_smin_i32(mxu_gpr[XRa - 1], mxu_gpr[XRx - 1], 0);
> +}
> +} else if (unlikely(XRb == XRc)) {
> +/* both operands same -> just set destination to one of them */
> +tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);
> +} else {
> +/* the most general case */
> +if (opc == OPC_MXU_S32MAX) {
> +tcg_gen_smax_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1],
> + mxu_gpr[XRc - 1]);
> +} else {
> +tcg_gen_smin_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1],
> + mxu_gpr[XRc - 1]);
> +}
> +}
> +}
> +
> +/*
> + * D16MAX
> + *Update XRa with the 16-bit-wise maximums of signed integers
> + *contained in XRb and XRc.
> + *
> + * D16MIN
> + *Update XRa with the 16-bit-wise minimums of signed integers
> + *contained in XRb and XRc.
> + *
> + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
> + * +---+-+-+---+---+---+---+
> + * | SPECIAL2 |0 0 0 0 0| opc | XRc | XRb | XRa |MXU__POOL00|
> + * +---+-+-+---+---+---+---+
> + */
> +static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx)
> +{
> +uint32_t pad, opc, XRc, XRb, XRa;
> +
> +pad = extract32(ctx->opcode, 21, 5);
> +opc = extract32(ctx->opcode, 18, 3);
> +XRc = extract32(ctx->opcode, 14, 4);
> +XRb = extract32(ctx->opcode, 10, 4);
> +XRa = extract32(ctx->opcode, 6, 4);
> +
> +if (unlikely(pad != 0)) {
> +/* opcode padding incorrect -> do nothing */
> +} else if (unlikely(XRc == 0)) {
> +/* destination is zero register -> do nothing */
> +} else if (unlikely((XRb == 0) && (XRa == 0))) {
> +/* both operands zero registers -> just set destination to zero */
> +tcg_gen_movi_i32(mxu_gpr[XRc - 1], 0);
> +} else if (unlikely((XRb == 0) || (XRa == 0))) {
> +/* exactly one operand is zero register - find which one is not...*/
> +uint
Re: [Qemu-devel] [PATCH 6/6] target/mips: MXU: Add handlers for an align instruction
On 17.12.18. 21:04, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Add translation handler for S32ALNI MXU instruction.
>
> Signed-off-by: Aleksandar Markovic
> ---
> target/mips/translate.c | 197 +++-
> 1 file changed, 194 insertions(+), 3 deletions(-)
Reviewed-by: Stefan Markovic
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index 339de8c32b..96905b78ac 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -25147,6 +25147,199 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx)
> }
>
>
> +/*
> + * MXU instruction category: align
> + * ~~~
> + *
> + * S32ALN S32ALNI
> + */
> +
> +/*
> + * S32ALNI XRc, XRb, XRa, optn3
> + *Arrange bytes from XRb and XRc according to one of five sets of
> + *rules determined by optn3, and place the result in XRa.
> + *
> + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
> + * +---+-+---+-+---+---+---+---+
> + * | SPECIAL2 |optn3|0 0|x x x| XRc | XRb | XRa |MXU__POOL16|
> + * +---+-+---+-+---+---+---+---+
> + *
> + */
> +static void gen_mxu_S32ALNI(DisasContext *ctx)
> +{
> +uint32_t optn3, pad, XRc, XRb, XRa;
> +
> +optn3 = extract32(ctx->opcode, 23, 3);
> +pad = extract32(ctx->opcode, 21, 2);
> +XRc = extract32(ctx->opcode, 14, 4);
> +XRb = extract32(ctx->opcode, 10, 4);
> +XRa = extract32(ctx->opcode, 6, 4);
> +
> +if (unlikely(pad != 0)) {
> +/* opcode padding incorrect -> do nothing */
> +} else if (unlikely(XRa == 0)) {
> +/* destination is zero register -> do nothing */
> +} else if (unlikely((XRb == 0) && (XRc == 0))) {
> +/* both operands zero registers -> just set destination to all 0s */
> +tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0);
> +} else if (unlikely(XRb == 0)) {
> +/* XRb zero register -> just appropriatelly shift XRc into XRa */
> +switch (optn3) {
> +case MXU_OPTN3_PTN0:
> +tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0);
> +break;
> +case MXU_OPTN3_PTN1:
> +case MXU_OPTN3_PTN2:
> +case MXU_OPTN3_PTN3:
> +tcg_gen_shri_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1],
> + 8 * (4 - optn3));
> +break;
> +case MXU_OPTN3_PTN4:
> +tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1]);
> +break;
> +}
> +} else if (unlikely(XRc == 0)) {
> +/* XRc zero register -> just appropriatelly shift XRb into XRa */
> +switch (optn3) {
> +case MXU_OPTN3_PTN0:
> +tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);
> +break;
> +case MXU_OPTN3_PTN1:
> +case MXU_OPTN3_PTN2:
> +case MXU_OPTN3_PTN3:
> +tcg_gen_shri_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], 8 * optn3);
> +break;
> +case MXU_OPTN3_PTN4:
> +tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0);
> +break;
> +}
> +} else if (unlikely(XRb == XRc)) {
> +/* both operands same -> just rotation or moving from any of them */
> +switch (optn3) {
> +case MXU_OPTN3_PTN0:
> +case MXU_OPTN3_PTN4:
> +tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);
> +break;
> +case MXU_OPTN3_PTN1:
> +case MXU_OPTN3_PTN2:
> +case MXU_OPTN3_PTN3:
> +tcg_gen_rotli_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], 8 * optn3);
> +break;
> +}
> +} else {
> +/* the most general case */
> +switch (optn3) {
> +case MXU_OPTN3_PTN0:
> +{
> +/* */
> +/* XRbXRc */
> +/* +---+ */
> +/* | A B C D |E F G H */
> +/* +---+---+ */
> +/* | */
> +/* XRa */
> +/* */
> +
> +tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);
> +}
> +break;
> +case MXU_OPTN3_PTN1:
> +{
> +/*
Re: [Qemu-devel] [PATCH 2/8] target/mips: Add preprocessor constants for 32 major CP0 registers
On 3.1.19. 17:34, Aleksandar Markovic wrote: > From: Aleksandar Markovic > > Add preprocessor constants for 32 major CP0 registers. > > Signed-off-by: Aleksandar Markovic > --- > target/mips/cpu.h | 32 > 1 file changed, 32 insertions(+) Reviewed-by: Stefan Markovic > diff --git a/target/mips/cpu.h b/target/mips/cpu.h > index 6c2a7e4..b095422 100644 > --- a/target/mips/cpu.h > +++ b/target/mips/cpu.h > @@ -233,6 +233,38 @@ typedef struct mips_def_t mips_def_t; >* 7 TagLo TagHi KScratch >* >*/ > +#define CPO_REGISTER_00 0 > +#define CPO_REGISTER_01 1 > +#define CPO_REGISTER_02 2 > +#define CPO_REGISTER_03 3 > +#define CPO_REGISTER_04 4 > +#define CPO_REGISTER_05 5 > +#define CPO_REGISTER_06 6 > +#define CPO_REGISTER_07 7 > +#define CPO_REGISTER_08 8 > +#define CPO_REGISTER_09 9 > +#define CPO_REGISTER_1010 > +#define CPO_REGISTER_1111 > +#define CPO_REGISTER_1212 > +#define CPO_REGISTER_1313 > +#define CPO_REGISTER_1414 > +#define CPO_REGISTER_1515 > +#define CPO_REGISTER_1616 > +#define CPO_REGISTER_1717 > +#define CPO_REGISTER_1818 > +#define CPO_REGISTER_1919 > +#define CPO_REGISTER_2020 > +#define CPO_REGISTER_2121 > +#define CPO_REGISTER_2222 > +#define CPO_REGISTER_2323 > +#define CPO_REGISTER_2424 > +#define CPO_REGISTER_2525 > +#define CPO_REGISTER_2626 > +#define CPO_REGISTER_2727 > +#define CPO_REGISTER_2828 > +#define CPO_REGISTER_2929 > +#define CPO_REGISTER_3030 > +#define CPO_REGISTER_3131 > > > typedef struct TCState TCState;
Re: [Qemu-devel] [PATCH 1/8] target/mips: Move comment containing summary of CP0 registers
On 3.1.19. 17:34, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Move comment containing summary of CP0 registers. Checkpatch
> script reported some tabs in the resutling diff, so convert
> these tabs to spaces too.
>
> Signed-off-by: Aleksandar Markovic
> ---
> target/mips/cpu.h | 165
> +++---
> 1 file changed, 84 insertions(+), 81 deletions(-)
Reviewed-by: Stefan Markovic
> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
> index 03c03fd..6c2a7e4 100644
> --- a/target/mips/cpu.h
> +++ b/target/mips/cpu.h
> @@ -123,87 +123,6 @@ typedef struct mips_def_t mips_def_t;
> #define MIPS_KSCRATCH_NUM 6
> #define MIPS_MAAR_MAX 16 /* Must be an even number. */
>
> -typedef struct TCState TCState;
> -struct TCState {
> -target_ulong gpr[32];
> -target_ulong PC;
> -target_ulong HI[MIPS_DSP_ACC];
> -target_ulong LO[MIPS_DSP_ACC];
> -target_ulong ACX[MIPS_DSP_ACC];
> -target_ulong DSPControl;
> -int32_t CP0_TCStatus;
> -#define CP0TCSt_TCU3 31
> -#define CP0TCSt_TCU2 30
> -#define CP0TCSt_TCU1 29
> -#define CP0TCSt_TCU0 28
> -#define CP0TCSt_TMX 27
> -#define CP0TCSt_RNST 23
> -#define CP0TCSt_TDS 21
> -#define CP0TCSt_DT 20
> -#define CP0TCSt_DA 15
> -#define CP0TCSt_A13
> -#define CP0TCSt_TKSU 11
> -#define CP0TCSt_IXMT 10
> -#define CP0TCSt_TASID0
> -int32_t CP0_TCBind;
> -#define CP0TCBd_CurTC21
> -#define CP0TCBd_TBE 17
> -#define CP0TCBd_CurVPE 0
> -target_ulong CP0_TCHalt;
> -target_ulong CP0_TCContext;
> -target_ulong CP0_TCSchedule;
> -target_ulong CP0_TCScheFBack;
> -int32_t CP0_Debug_tcstatus;
> -target_ulong CP0_UserLocal;
> -
> -int32_t msacsr;
> -
> -#define MSACSR_FS 24
> -#define MSACSR_FS_MASK (1 << MSACSR_FS)
> -#define MSACSR_NX 18
> -#define MSACSR_NX_MASK (1 << MSACSR_NX)
> -#define MSACSR_CEF 2
> -#define MSACSR_CEF_MASK (0x << MSACSR_CEF)
> -#define MSACSR_RM 0
> -#define MSACSR_RM_MASK (0x3 << MSACSR_RM)
> -#define MSACSR_MASK (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK |
> \
> -MSACSR_FS_MASK)
> -
> -float_status msa_fp_status;
> -
> -#define NUMBER_OF_MXU_REGISTERS 16
> -target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];
> -target_ulong mxu_cr;
> -#define MXU_CR_LC 31
> -#define MXU_CR_RC 30
> -#define MXU_CR_BIAS 2
> -#define MXU_CR_RD_EN1
> -#define MXU_CR_MXU_EN 0
> -
> -};
> -
> -typedef struct CPUMIPSState CPUMIPSState;
> -struct CPUMIPSState {
> -TCState active_tc;
> -CPUMIPSFPUContext active_fpu;
> -
> -uint32_t current_tc;
> -uint32_t current_fpu;
> -
> -uint32_t SEGBITS;
> -uint32_t PABITS;
> -#if defined(TARGET_MIPS64)
> -# define PABITS_BASE 36
> -#else
> -# define PABITS_BASE 32
> -#endif
> -target_ulong SEGMask;
> -uint64_t PAMask;
> -#define PAMASK_BASE ((1ULL << PABITS_BASE) - 1)
> -
> -int32_t msair;
> -#define MSAIR_ProcID8
> -#define MSAIR_Rev 0
>
> /*
>* Summary of CP0 registers
> @@ -314,6 +233,90 @@ struct CPUMIPSState {
>* 7 TagLo TagHi KScratch
>*
>*/
> +
> +
> +typedef struct TCState TCState;
> +struct TCState {
> +target_ulong gpr[32];
> +target_ulong PC;
> +target_ulong HI[MIPS_DSP_ACC];
> +target_ulong LO[MIPS_DSP_ACC];
> +target_ulong ACX[MIPS_DSP_ACC];
> +target_ulong DSPControl;
> +int32_t CP0_TCStatus;
> +#define CP0TCSt_TCU331
> +#define CP0TCSt_TCU230
> +#define CP0TCSt_TCU129
> +#define CP0TCSt_TCU028
> +#define CP0TCSt_TMX 27
> +#define CP0TCSt_RNST23
> +#define CP0TCSt_TDS 21
> +#define CP0TCSt_DT 20
> +#define CP0TCSt_DA 15
> +#define CP0TCSt_A 13
> +#define CP0TCSt_TKSU11
> +#define CP0TCSt_IXMT10
> +#define CP0TCSt_TASID 0
> +int32_t CP0_TCBind;
> +#define CP0TCBd_CurTC 21
> +#define CP0TCBd_TBE 17
> +#define CP0TCBd_CurVPE 0
> +target_ulong CP0_TCHalt;
> +target_ulong CP0_TCContext;
> +target_ulong CP0_TCSchedule;
> +target_ulong CP0_TCScheFBack;
> +int32_t CP0_Debug_tcstatus;
> +target_ulong CP0_UserLocal;
> +
> +int32_t msacsr;
> +
> +#define MSACSR_FS 24
> +#define MSACSR_FS_MASK (1 << MSACSR_FS)
> +#define MSACSR_NX 18
> +#define MSACSR_NX_MASK (1 << MSACSR_NX)
> +#define MSACSR_CEF 2
> +#define MSACSR_CEF_MASK (0x << MSACSR_CEF)
Re: [Qemu-devel] [PATCH 4/8] target/mips: Add fields for SAARI and SAAR CP0 registers
On 3.1.19. 17:34, Aleksandar Markovic wrote:
> From: Yongbok Kim
>
> Add fields for SAARI and SAAR CP0 registers.
>
> Signed-off-by: Yongbok Kim
> Signed-off-by: Aleksandar Markovic
> ---
> target/mips/cpu.h | 10 --
> target/mips/machine.c | 6 --
> 2 files changed, 12 insertions(+), 4 deletions(-)
Reviewed-by: Stefan Markovic
> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
> index b095422..1c2c682 100644
> --- a/target/mips/cpu.h
> +++ b/target/mips/cpu.h
> @@ -164,8 +164,8 @@ typedef struct mips_def_t mips_def_t;
>* 3 BadInstrX
>* 4 GuestCtl1 GuestCtl0Ext
>* 5 GuestCtl2
> - * 6 GuestCtl3
> - * 7
> + * 6 SAARI GuestCtl3
> + * 7 SAAR
>*
>*
>* Register 12 Register 13 Register 14 Register 15
> @@ -546,6 +546,12 @@ struct CPUMIPSState {
>* CP0 Register 9
>*/
> int32_t CP0_Count;
> +uint32_t CP0_SAARI;
> +#define CP0SAARI_TARGET 0/* 5..0 */
> +uint64_t CP0_SAAR[2];
> +#define CP0SAAR_BASE12 /* 43..12 */
> +#define CP0SAAR_SIZE1/* 5..1 */
> +#define CP0SAAR_EN 0
> /*
>* CP0 Register 10
>*/
> diff --git a/target/mips/machine.c b/target/mips/machine.c
> index 704e9c0..111d7c3 100644
> --- a/target/mips/machine.c
> +++ b/target/mips/machine.c
> @@ -214,8 +214,8 @@ const VMStateDescription vmstate_tlb = {
>
> const VMStateDescription vmstate_mips_cpu = {
> .name = "cpu",
> -.version_id = 15,
> -.minimum_version_id = 15,
> +.version_id = 16,
> +.minimum_version_id = 16,
> .post_load = cpu_post_load,
> .fields = (VMStateField[]) {
> /* Active TC */
> @@ -274,6 +274,8 @@ const VMStateDescription vmstate_mips_cpu = {
> VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU),
> VMSTATE_UINT32(env.CP0_BadInstrX, MIPSCPU),
> VMSTATE_INT32(env.CP0_Count, MIPSCPU),
> +VMSTATE_UINT32(env.CP0_SAARI, MIPSCPU),
> +VMSTATE_UINT64_ARRAY(env.CP0_SAAR, MIPSCPU, 2),
> VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU),
> VMSTATE_INT32(env.CP0_Compare, MIPSCPU),
> VMSTATE_INT32(env.CP0_Status, MIPSCPU),
Re: [Qemu-devel] [PATCH 3/8] target/mips: Use preprocessor constants for 32 major CP0 registers
On 3.1.19. 17:34, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Use preprocessor constants for 32 major CP0 registers.
>
> Signed-off-by: Aleksandar Markovic
> ---
> target/mips/translate.c | 272
>
> 1 file changed, 136 insertions(+), 136 deletions(-)
Reviewed-by: Stefan Markovic
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index e9c23a5..6af292f 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -6476,7 +6476,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int
> reg, int sel)
> const char *rn = "invalid";
>
> switch (reg) {
> -case 2:
> +case CPO_REGISTER_02:
> switch (sel) {
> case 0:
> CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
> @@ -6487,7 +6487,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int
> reg, int sel)
> goto cp0_unimplemented;
> }
> break;
> -case 3:
> +case CPO_REGISTER_03:
> switch (sel) {
> case 0:
> CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
> @@ -6498,7 +6498,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int
> reg, int sel)
> goto cp0_unimplemented;
> }
> break;
> -case 17:
> +case CPO_REGISTER_17:
> switch (sel) {
> case 0:
> gen_mfhc0_load64(arg, offsetof(CPUMIPSState, lladdr),
> @@ -6514,7 +6514,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int
> reg, int sel)
> goto cp0_unimplemented;
> }
> break;
> -case 28:
> +case CPO_REGISTER_28:
> switch (sel) {
> case 0:
> case 2:
> @@ -6544,7 +6544,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int
> reg, int sel)
> uint64_t mask = ctx->PAMask >> 36;
>
> switch (reg) {
> -case 2:
> +case CPO_REGISTER_02:
> switch (sel) {
> case 0:
> CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
> @@ -6556,7 +6556,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int
> reg, int sel)
> goto cp0_unimplemented;
> }
> break;
> -case 3:
> +case CPO_REGISTER_03:
> switch (sel) {
> case 0:
> CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
> @@ -6568,7 +6568,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int
> reg, int sel)
> goto cp0_unimplemented;
> }
> break;
> -case 17:
> +case CPO_REGISTER_17:
> switch (sel) {
> case 0:
> /* LLAddr is read-only (the only exception is bit 0 if LLB is
> @@ -6586,7 +6586,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int
> reg, int sel)
> goto cp0_unimplemented;
> }
> break;
> -case 28:
> +case CPO_REGISTER_28:
> switch (sel) {
> case 0:
> case 2:
> @@ -6626,7 +6626,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
> reg, int sel)
> check_insn(ctx, ISA_MIPS32);
>
> switch (reg) {
> -case 0:
> +case CPO_REGISTER_00:
> switch (sel) {
> case 0:
> gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index));
> @@ -6656,7 +6656,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
> reg, int sel)
> goto cp0_unimplemented;
> }
> break;
> -case 1:
> +case CPO_REGISTER_01:
> switch (sel) {
> case 0:
> CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
> @@ -6702,7 +6702,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
> reg, int sel)
> goto cp0_unimplemented;
> }
> break;
> -case 2:
> +case CPO_REGISTER_02:
> switch (sel) {
> case 0:
> {
> @@ -6760,7 +6760,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
> reg, int sel)
> goto cp0_unimplemented;
> }
> break;
> -case 3:
> +case CPO_REGISTER_03:
> switch (sel) {
> case 0:
> {
> @@ -6788,7 +6788,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
> reg, int sel)
> goto cp0_unimplemented;
> }
> break;
> -case 4:
> +case CPO_REGISTER_04:
> switch (sel) {
> case 0:
> tcg_gen_ld_tl(
Re: [Qemu-devel] [PATCH 8/8] target/mips: Update ITU to handle bus errors
On 3.1.19. 17:34, Aleksandar Markovic wrote:
> From: Yongbok Kim
>
> Update ITU to handle bus errors.
>
> Signed-off-by: Yongbok Kim
> Signed-off-by: Aleksandar Markovic
> ---
> hw/misc/mips_itu.c | 22 ++
> 1 file changed, 22 insertions(+)
Reviewed-by: Stefan Markovic
> diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c
> index 5c49bdd..e8860dc 100644
> --- a/hw/misc/mips_itu.c
> +++ b/hw/misc/mips_itu.c
> @@ -375,6 +375,12 @@ static void view_pv_try_write(ITCStorageCell *c)
> view_pv_common_write(c);
> }
>
> +static void raise_exception(int excp)
> +{
> +current_cpu->exception_index = excp;
> +cpu_loop_exit(current_cpu);
> +}
> +
> static uint64_t itc_storage_read(void *opaque, hwaddr addr, unsigned size)
> {
> MIPSITUState *s = (MIPSITUState *)opaque;
> @@ -382,6 +388,14 @@ static uint64_t itc_storage_read(void *opaque, hwaddr
> addr, unsigned size)
> ITCView view = get_itc_view(addr);
> uint64_t ret = -1;
>
> +switch (size) {
> +case 1:
> +case 2:
> +s->icr0 |= 1 << ITC_ICR0_ERR_AXI;
> +raise_exception(EXCP_DBE);
> +return 0;
> +}
> +
> switch (view) {
> case ITCVIEW_BYPASS:
> ret = view_bypass_read(cell);
> @@ -420,6 +434,14 @@ static void itc_storage_write(void *opaque, hwaddr addr,
> uint64_t data,
> ITCStorageCell *cell = get_cell(s, addr);
> ITCView view = get_itc_view(addr);
>
> +switch (size) {
> +case 1:
> +case 2:
> +s->icr0 |= 1 << ITC_ICR0_ERR_AXI;
> +raise_exception(EXCP_DBE);
> +return;
> +}
> +
> switch (view) {
> case ITCVIEW_BYPASS:
> view_bypass_write(cell, data);
Re: [Qemu-devel] [PATCH 5/8] target/mips: Provide R/W access to SAARI and SAAR CP0 registers
On 3.1.19. 17:34, Aleksandar Markovic wrote:
> From: Yongbok Kim
>
> Provide R/W access to SAARI and SAAR CP0 registers.
>
> Signed-off-by: Yongbok Kim
> Signed-off-by: Aleksandar Markovic
> ---
> target/mips/cpu.h | 1 +
> target/mips/helper.h| 6 +
> target/mips/internal.h | 1 +
> target/mips/op_helper.c | 50 +
> target/mips/translate.c | 66
> ++---
> 5 files changed, 120 insertions(+), 4 deletions(-)
Reviewed-by: Stefan Markovic
> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
> index 1c2c682..185702d 100644
> --- a/target/mips/cpu.h
> +++ b/target/mips/cpu.h
> @@ -901,6 +901,7 @@ struct CPUMIPSState {
> uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
> uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
> uint64_t insn_flags; /* Supported instruction set */
> +int saarp;
>
> /* Fields up to this point are cleared by a CPU reset */
> struct {} end_reset_fields;
> diff --git a/target/mips/helper.h b/target/mips/helper.h
> index c23e4e5..8872c46 100644
> --- a/target/mips/helper.h
> +++ b/target/mips/helper.h
> @@ -65,6 +65,8 @@ DEF_HELPER_1(mftc0_tcschedule, tl, env)
> DEF_HELPER_1(mfc0_tcschefback, tl, env)
> DEF_HELPER_1(mftc0_tcschefback, tl, env)
> DEF_HELPER_1(mfc0_count, tl, env)
> +DEF_HELPER_1(mfc0_saar, tl, env)
> +DEF_HELPER_1(mfhc0_saar, tl, env)
> DEF_HELPER_1(mftc0_entryhi, tl, env)
> DEF_HELPER_1(mftc0_status, tl, env)
> DEF_HELPER_1(mftc0_cause, tl, env)
> @@ -87,6 +89,7 @@ DEF_HELPER_1(dmfc0_tcschefback, tl, env)
> DEF_HELPER_1(dmfc0_lladdr, tl, env)
> DEF_HELPER_1(dmfc0_maar, tl, env)
> DEF_HELPER_2(dmfc0_watchlo, tl, env, i32)
> +DEF_HELPER_1(dmfc0_saar, tl, env)
> #endif /* TARGET_MIPS64 */
>
> DEF_HELPER_2(mtc0_index, void, env, tl)
> @@ -131,6 +134,9 @@ DEF_HELPER_2(mtc0_srsconf4, void, env, tl)
> DEF_HELPER_2(mtc0_hwrena, void, env, tl)
> DEF_HELPER_2(mtc0_pwctl, void, env, tl)
> DEF_HELPER_2(mtc0_count, void, env, tl)
> +DEF_HELPER_2(mtc0_saari, void, env, tl)
> +DEF_HELPER_2(mtc0_saar, void, env, tl)
> +DEF_HELPER_2(mthc0_saar, void, env, tl)
> DEF_HELPER_2(mtc0_entryhi, void, env, tl)
> DEF_HELPER_2(mttc0_entryhi, void, env, tl)
> DEF_HELPER_2(mtc0_compare, void, env, tl)
> diff --git a/target/mips/internal.h b/target/mips/internal.h
> index 8b1b245..8f6fc91 100644
> --- a/target/mips/internal.h
> +++ b/target/mips/internal.h
> @@ -61,6 +61,7 @@ struct mips_def_t {
> target_ulong CP0_EBaseWG_rw_bitmask;
> uint64_t insn_flags;
> enum mips_mmu_types mmu_type;
> +int32_t SAARP;
> };
>
> extern const struct mips_def_t mips_defs[];
> diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
> index d1f1d1a..409c136 100644
> --- a/target/mips/op_helper.c
> +++ b/target/mips/op_helper.c
> @@ -938,6 +938,22 @@ target_ulong helper_mfc0_count(CPUMIPSState *env)
> return count;
> }
>
> +target_ulong helper_mfc0_saar(CPUMIPSState *env)
> +{
> +if ((env->CP0_SAARI & 0x3f) < 2) {
> +return (int32_t) env->CP0_SAAR[env->CP0_SAARI & 0x3f];
> +}
> +return 0;
> +}
> +
> +target_ulong helper_mfhc0_saar(CPUMIPSState *env)
> +{
> +if ((env->CP0_SAARI & 0x3f) < 2) {
> +return env->CP0_SAAR[env->CP0_SAARI & 0x3f] >> 32;
> +}
> +return 0;
> +}
> +
> target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
> {
> int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
> @@ -1059,6 +1075,14 @@ target_ulong helper_dmfc0_watchlo(CPUMIPSState *env,
> uint32_t sel)
> {
> return env->CP0_WatchLo[sel];
> }
> +
> +target_ulong helper_dmfc0_saar(CPUMIPSState *env)
> +{
> +if ((env->CP0_SAARI & 0x3f) < 2) {
> +return env->CP0_SAAR[env->CP0_SAARI & 0x3f];
> +}
> +return 0;
> +}
> #endif /* TARGET_MIPS64 */
>
> void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
> @@ -1598,6 +1622,32 @@ void helper_mtc0_count(CPUMIPSState *env, target_ulong
> arg1)
> qemu_mutex_unlock_iothread();
> }
>
> +void helper_mtc0_saari(CPUMIPSState *env, target_ulong arg1)
> +{
> +uint32_t target = arg1 & 0x3f;
> +if (target <= 1) {
> +env->CP0_SAARI = target;
> +}
> +}
> +
> +void helper_mtc0_saar(CPUMIPSState *env, target_ulong arg1)
> +{
> +uint32_t target = env->CP0_SAARI & 0x3f;
> +if (target < 2) {
> +env->CP0_SAAR[target] = arg
Re: [Qemu-devel] [PATCH 6/8] target/mips: Add field and R/W access to ITU control register ICR0
On 3.1.19. 17:34, Aleksandar Markovic wrote:
> From: Yongbok Kim
>
> Add field and R/W access to ITU control register ICR0.
>
> Signed-off-by: Yongbok Kim
> Signed-off-by: Aleksandar Markovic
> ---
> hw/misc/mips_itu.c | 22 +-
> include/hw/misc/mips_itu.h | 4
> 2 files changed, 25 insertions(+), 1 deletion(-)
Reviewed-by: Stefan Markovic
> diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c
> index 43bbec4..4801958 100644
> --- a/hw/misc/mips_itu.c
> +++ b/hw/misc/mips_itu.c
> @@ -55,9 +55,17 @@ typedef enum ITCView {
> ITCVIEW_EF_SYNC = 2,
> ITCVIEW_EF_TRY = 3,
> ITCVIEW_PV_SYNC = 4,
> -ITCVIEW_PV_TRY = 5
> +ITCVIEW_PV_TRY = 5,
> +ITCVIEW_PV_ICR0 = 15,
> } ITCView;
>
> +#define ITC_ICR0_CELL_NUM16
> +#define ITC_ICR0_BLK_GRAIN 8
> +#define ITC_ICR0_BLK_GRAIN_MASK 0x7
> +#define ITC_ICR0_ERR_AXI 2
> +#define ITC_ICR0_ERR_PARITY 1
> +#define ITC_ICR0_ERR_EXEC0
> +
> MemoryRegion *mips_itu_get_tag_region(MIPSITUState *itu)
> {
> return &itu->tag_io;
> @@ -382,6 +390,9 @@ static uint64_t itc_storage_read(void *opaque, hwaddr
> addr, unsigned size)
> case ITCVIEW_PV_TRY:
> ret = view_pv_try_read(cell);
> break;
> +case ITCVIEW_PV_ICR0:
> +ret = s->icr0;
> +break;
> default:
> qemu_log_mask(LOG_GUEST_ERROR,
> "itc_storage_read: Bad ITC View %d\n", (int)view);
> @@ -417,6 +428,15 @@ static void itc_storage_write(void *opaque, hwaddr addr,
> uint64_t data,
> case ITCVIEW_PV_TRY:
> view_pv_try_write(cell);
> break;
> +case ITCVIEW_PV_ICR0:
> +if (data & 0x7) {
> +/* clear ERROR bits */
> +s->icr0 &= ~(data & 0x7);
> +}
> +/* set BLK_GRAIN */
> +s->icr0 &= ~0x700;
> +s->icr0 |= data & 0x700;
> +break;
> default:
> qemu_log_mask(LOG_GUEST_ERROR,
> "itc_storage_write: Bad ITC View %d\n", (int)view);
> diff --git a/include/hw/misc/mips_itu.h b/include/hw/misc/mips_itu.h
> index 030eb4a..45a0c51 100644
> --- a/include/hw/misc/mips_itu.h
> +++ b/include/hw/misc/mips_itu.h
> @@ -66,6 +66,10 @@ typedef struct MIPSITUState {
> /* ITC Configuration Tags */
> uint64_t ITCAddressMap[ITC_ADDRESSMAP_NUM];
> MemoryRegion tag_io;
> +
> +/* ITU Control Register */
> +uint64_t icr0;
> +
> } MIPSITUState;
>
> /* Get ITC Configuration Tag memory region. */
Re: [Qemu-devel] [PATCH 7/8] target/mips: Update ITU to utilize SAARI and SAAR CP0 registers
On 3.1.19. 17:34, Aleksandar Markovic wrote:
> From: Yongbok Kim
>
> Update ITU to utilize SAARI and SAAR CP0 registers.
>
> Signed-off-by: Yongbok Kim
> Signed-off-by: Aleksandar Markovic
> ---
> hw/mips/cps.c | 8
> hw/misc/mips_itu.c | 28 ++--
> include/hw/misc/mips_itu.h | 4
> target/mips/cpu.h | 5 +
> target/mips/op_helper.c| 14 ++
> 5 files changed, 53 insertions(+), 6 deletions(-)
Reviewed-by: Stefan Markovic
> diff --git a/hw/mips/cps.c b/hw/mips/cps.c
> index 4285d19..fc97f59 100644
> --- a/hw/mips/cps.c
> +++ b/hw/mips/cps.c
> @@ -69,6 +69,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
> Error *err = NULL;
> target_ulong gcr_base;
> bool itu_present = false;
> +bool saar_present = false;
>
> for (i = 0; i < s->num_vp; i++) {
> cpu = MIPS_CPU(cpu_create(s->cpu_type));
> @@ -82,12 +83,14 @@ static void mips_cps_realize(DeviceState *dev, Error
> **errp)
> itu_present = true;
> /* Attach ITC Tag to the VP */
> env->itc_tag = mips_itu_get_tag_region(&s->itu);
> +env->itu = &s->itu;
> }
> qemu_register_reset(main_cpu_reset, cpu);
> }
>
> cpu = MIPS_CPU(first_cpu);
> env = &cpu->env;
> +saar_present = (bool)env->saarp;
>
> /* Inter-Thread Communication Unit */
> if (itu_present) {
> @@ -96,6 +99,11 @@ static void mips_cps_realize(DeviceState *dev, Error
> **errp)
>
> object_property_set_int(OBJECT(&s->itu), 16, "num-fifo", &err);
> object_property_set_int(OBJECT(&s->itu), 16, "num-semaphores",
> &err);
> +object_property_set_bool(OBJECT(&s->itu), saar_present,
> "saar-present",
> + &err);
> +if (saar_present) {
> +qdev_prop_set_ptr(DEVICE(&s->itu), "saar", (void
> *)&env->CP0_SAAR);
> +}
> object_property_set_bool(OBJECT(&s->itu), true, "realized", &err);
> if (err != NULL) {
> error_propagate(errp, err);
> diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c
> index 4801958..5c49bdd 100644
> --- a/hw/misc/mips_itu.c
> +++ b/hw/misc/mips_itu.c
> @@ -84,7 +84,7 @@ static uint64_t itc_tag_read(void *opaque, hwaddr addr,
> unsigned size)
> return tag->ITCAddressMap[index];
> }
>
> -static void itc_reconfigure(MIPSITUState *tag)
> +void itc_reconfigure(MIPSITUState *tag)
> {
> uint64_t *am = &tag->ITCAddressMap[0];
> MemoryRegion *mr = &tag->storage_io;
> @@ -92,6 +92,12 @@ static void itc_reconfigure(MIPSITUState *tag)
> uint64_t size = (1 * KiB) + (am[1] & ITC_AM1_ADDR_MASK_MASK);
> bool is_enabled = (am[0] & ITC_AM0_EN_MASK) != 0;
>
> +if (tag->saar_present) {
> +address = ((*(uint64_t *) tag->saar) & 0xE000ULL) << 4;
> +size = 1 << ((*(uint64_t *) tag->saar >> 1) & 0x1f);
> +is_enabled = *(uint64_t *) tag->saar & 1;
> +}
> +
> memory_region_transaction_begin();
> if (!(size & (size - 1))) {
> memory_region_set_size(mr, size);
> @@ -150,7 +156,12 @@ static inline ITCView get_itc_view(hwaddr addr)
> static inline int get_cell_stride_shift(const MIPSITUState *s)
> {
> /* Minimum interval (for EntryGain = 0) is 128 B */
> -return 7 + (s->ITCAddressMap[1] & ITC_AM1_ENTRY_GRAIN_MASK);
> +if (s->saar_present) {
> +return 7 + ((s->icr0 >> ITC_ICR0_BLK_GRAIN) &
> +ITC_ICR0_BLK_GRAIN_MASK);
> +} else {
> +return 7 + (s->ITCAddressMap[1] & ITC_AM1_ENTRY_GRAIN_MASK);
> +}
> }
>
> static inline ITCStorageCell *get_cell(MIPSITUState *s,
> @@ -499,10 +510,15 @@ static void mips_itu_reset(DeviceState *dev)
> {
> MIPSITUState *s = MIPS_ITU(dev);
>
> -s->ITCAddressMap[0] = 0;
> -s->ITCAddressMap[1] =
> -((ITC_STORAGE_ADDRSPACE_SZ - 1) & ITC_AM1_ADDR_MASK_MASK) |
> -(get_num_cells(s) << ITC_AM1_NUMENTRIES_OFS);
> +if (s->saar_present) {
> +*(uint64_t *) s->saar = 0x11 << 1;
> +s->icr0 = get_num_cells(s) << ITC_ICR0_CELL_NUM;
> +} else {
> +s->ITCAddressMap[0] = 0;
> +s->ITCAddressMap[1] =
> +((ITC_STORAGE_ADDRSPACE_SZ - 1) & ITC_AM1_ADDR_
Re: [Qemu-devel] [PATCH v3 5/8] target/mips: Add CP0 BadInstrX register
Hi Philippe,
Following fix will be added in v4:
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 79a59fd..98ff8d0 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -5354,6 +5354,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
case 3:
CP0_CHECK(ctx->bi);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX));
+tcg_gen_andi_i32(arg, arg, 0x);
rn = "BadInstrX";
break;
default:
@@ -6719,6 +6720,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
case 3:
CP0_CHECK(ctx->bi);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX));
+tcg_gen_andi_i32(arg, arg, 0x);
rn = "BadInstrX";
break;
default:
Regards,
Stefan
From: Philippe Mathieu-Daudé on behalf of
Philippe Mathieu-Daudé
Sent: Wednesday, July 4, 2018 10:31:27 PM
To: Aleksandar Markovic; qemu-devel@nongnu.org; Richard Henderson
Cc: aurel...@aurel32.net; Aleksandar Markovic; Stefan Markovic; Petar
Jovanovic; Paul Burton
Subject: Re: [PATCH v3 5/8] target/mips: Add CP0 BadInstrX register
Hi Aleksandar,
On 07/04/2018 04:30 PM, Aleksandar Markovic wrote:
> From: Stefan Markovic
>
> Add CP0 BadInstrX register. This register will be used in nanoMIPS.
>
> Signed-off-by: Stefan Markovic
> Signed-off-by: Yongbok Kim
> Signed-off-by: Aleksandar Markovic
> Reviewed-by: Aleksandar Markovic
> ---
> target/mips/cpu.h | 1 +
> target/mips/machine.c | 5 +++--
> target/mips/translate.c | 20 +++-
> 3 files changed, 23 insertions(+), 3 deletions(-)
>
> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
> index edbb66d..8ccbc21 100644
> --- a/target/mips/cpu.h
> +++ b/target/mips/cpu.h
> @@ -323,6 +323,7 @@ struct CPUMIPSState {
> target_ulong CP0_BadVAddr;
> uint32_t CP0_BadInstr;
> uint32_t CP0_BadInstrP;
> +uint32_t CP0_BadInstrX;
> int32_t CP0_Count;
> target_ulong CP0_EntryHi;
> #define CP0EnHi_EHINV 10
> diff --git a/target/mips/machine.c b/target/mips/machine.c
> index 20100d5..5ba78ac 100644
> --- a/target/mips/machine.c
> +++ b/target/mips/machine.c
> @@ -212,8 +212,8 @@ const VMStateDescription vmstate_tlb = {
>
> const VMStateDescription vmstate_mips_cpu = {
> .name = "cpu",
> -.version_id = 10,
> -.minimum_version_id = 10,
> +.version_id = 11,
> +.minimum_version_id = 11,
> .post_load = cpu_post_load,
> .fields = (VMStateField[]) {
> /* Active TC */
> @@ -266,6 +266,7 @@ const VMStateDescription vmstate_mips_cpu = {
> VMSTATE_UINTTL(env.CP0_BadVAddr, MIPSCPU),
> VMSTATE_UINT32(env.CP0_BadInstr, MIPSCPU),
> VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU),
> +VMSTATE_UINT32(env.CP0_BadInstrX, MIPSCPU),
> VMSTATE_INT32(env.CP0_Count, MIPSCPU),
> VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU),
> VMSTATE_INT32(env.CP0_Compare, MIPSCPU),
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index 88699ae..0562851 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -5315,7 +5315,12 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
> reg, int sel)
> gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP));
> rn = "BadInstrP";
> break;
> -default:
> +case 3:
> +CP0_CHECK(ctx->bi);
> +gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX));
> +rn = "BadInstrX";
> +break;
> + default:
> goto cp0_unimplemented;
> }
> break;
> @@ -6006,6 +6011,10 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
> reg, int sel)
> /* ignored */
> rn = "BadInstrP";
> break;
> +case 3:
> +/* ignored */
> +rn = "BadInstrX";
> +break;
> default:
> goto cp0_unimplemented;
> }
> @@ -6711,6 +6720,11 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
> reg, int sel)
> gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP));
> rn = "BadInstrP";
> break;
> +case 3:
> +CP0_CHECK(ctx->bi);
> +gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX));
I'm unsure re-using gen_mfc0_load32() is enough, shouldn't we zero the
16 lower bits?
> +rn = "BadInstrX"
Re: [Qemu-devel] [PATCH v3 5/8] target/mips: Add CP0 BadInstrX register
Hi Philippe,
With solved build issues caused by solution previously proposed, this would be
the final fix:
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -5354,6 +5354,11 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
case 3:
CP0_CHECK(ctx->bi);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX));
+#if defined(TARGET_MIPS64)
+tcg_gen_andi_i64(arg, arg, ~0x);
+#else
+tcg_gen_andi_i32(arg, arg, ~0x);
+#endif
rn = "BadInstrX";
break;
default:
@@ -6719,6 +6724,11 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
case 3:
CP0_CHECK(ctx->bi);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX));
+#if defined(TARGET_MIPS64)
+tcg_gen_andi_i64(arg, arg, ~0x);
+#else
+tcg_gen_andi_i32(arg, arg, ~0x);
+#endif
rn = "BadInstrX";
break;
default:
Regards,
Stefan
From: Philippe Mathieu-Daudé on behalf of
Philippe Mathieu-Daudé
Sent: Thursday, July 5, 2018 5:13:42 PM
To: Stefan Markovic; Aleksandar Markovic; qemu-devel@nongnu.org; Richard
Henderson
Cc: Petar Jovanovic; Aleksandar Markovic; aurel...@aurel32.net; Paul Burton
Subject: Re: [Qemu-devel] [PATCH v3 5/8] target/mips: Add CP0 BadInstrX register
On 07/05/2018 10:27 AM, Stefan Markovic wrote:
> Hi Philippe,
>
> Following fix will be added in v4:
>
>
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index 79a59fd..98ff8d0 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -5354,6 +5354,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
> reg, int sel)
> case 3:
> CP0_CHECK(ctx->bi);
> gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX));
> +tcg_gen_andi_i32(arg, arg, 0x);
Correct, maybe easier to read as:
tcg_gen_andi_i32(arg, arg, ~0x);
With these changes in your v4:
Reviewed-by: Philippe Mathieu-Daudé
> rn = "BadInstrX";
> break;
> default:
> @@ -6719,6 +6720,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
> reg, int sel)
> case 3:
> CP0_CHECK(ctx->bi);
> gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX));
> +tcg_gen_andi_i32(arg, arg, 0x);
> rn = "BadInstrX";
> break;
> default:
>
>
> Regards,
> Stefan
>
>
>
> From: Philippe Mathieu-Daudé on behalf of
> Philippe Mathieu-Daudé
> Sent: Wednesday, July 4, 2018 10:31:27 PM
> To: Aleksandar Markovic; qemu-devel@nongnu.org; Richard Henderson
> Cc: aurel...@aurel32.net; Aleksandar Markovic; Stefan Markovic; Petar
> Jovanovic; Paul Burton
> Subject: Re: [PATCH v3 5/8] target/mips: Add CP0 BadInstrX register
>
> Hi Aleksandar,
>
> On 07/04/2018 04:30 PM, Aleksandar Markovic wrote:
>> From: Stefan Markovic
>>
>> Add CP0 BadInstrX register. This register will be used in nanoMIPS.
>>
>> Signed-off-by: Stefan Markovic
>> Signed-off-by: Yongbok Kim
>> Signed-off-by: Aleksandar Markovic
>> Reviewed-by: Aleksandar Markovic
>> ---
>> target/mips/cpu.h | 1 +
>> target/mips/machine.c | 5 +++--
>> target/mips/translate.c | 20 +++-
>> 3 files changed, 23 insertions(+), 3 deletions(-)
>>
>> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
>> index edbb66d..8ccbc21 100644
>> --- a/target/mips/cpu.h
>> +++ b/target/mips/cpu.h
>> @@ -323,6 +323,7 @@ struct CPUMIPSState {
>> target_ulong CP0_BadVAddr;
>> uint32_t CP0_BadInstr;
>> uint32_t CP0_BadInstrP;
>> +uint32_t CP0_BadInstrX;
>> int32_t CP0_Count;
>> target_ulong CP0_EntryHi;
>> #define CP0EnHi_EHINV 10
>> diff --git a/target/mips/machine.c b/target/mips/machine.c
>> index 20100d5..5ba78ac 100644
>> --- a/target/mips/machine.c
>> +++ b/target/mips/machine.c
>> @@ -212,8 +212,8 @@ const VMStateDescription vmstate_tlb = {
>>
>> const VMStateDescription vmstate_mips_cpu = {
>> .name = "cpu",
>> -.version_id = 10,
>> -.minimum_version_id = 10,
>> +.version_id = 11,
>> +.minimum_version_id = 11,
>> .post_load = cpu_post_load,
>> .fields = (VMStateField[]) {
>> /* Active TC */
>> @@ -266,6 +266,7 @@ const VMStateDescription vmstate_mips_cpu = {
>> VMSTATE_UINTTL(env.CP0_BadVAddr, MIPSCPU),
>>
Re: [Qemu-devel] [PATCH v2 32/33] gdbstub: Add XML support for GDB for nanoMIPS
Stefan, Can you clarify here: - Was the intention to implement XML support for nanoMIPS only? - In any case, is there a way to support pre-nanoMIPS MIPS configurations that would require only a reasonable implementation time? Thanks, Aleksandar AFAIR, only nanoMIPS XML support was intended at the time. However, I believe It shouldn't take much time and effort to support pre-nanoMIPS configurations. Regards, Stefan From: Aleksandar Markovic Sent: Tuesday, July 10, 2018 8:48:49 PM To: Aleksandar Markovic; qemu-devel@nongnu.org Cc: f4...@amsat.org; aurel...@aurel32.net; Stefan Markovic; Petar Jovanovic; Paul Burton Subject: Re: [PATCH v2 32/33] gdbstub: Add XML support for GDB for nanoMIPS > Subject: [PATCH v2 32/33] gdbstub: Add XML support for GDB for nanoMIPS > > From: Stefan Markovic > > Add XML support files for GDB for nanoMIPS. > > Signed-off-by: Aleksandar Markovic > Signed-off-by: Stefan Markovic > --- > MAINTAINERS| 3 ++- > gdb-xml/nanomips-cp0.xml | 13 + > gdb-xml/nanomips-cpu.xml | 44 > gdb-xml/nanomips-dsp.xml | 20 > gdb-xml/nanomips-fpu.xml | 45 + > gdb-xml/nanomips-linux.xml | 20 > 6 files changed, 144 insertions(+), 1 deletion(-) > create mode 100644 gdb-xml/nanomips-cp0.xml > create mode 100644 gdb-xml/nanomips-cpu.xml > create mode 100644 gdb-xml/nanomips-dsp.xml > create mode 100644 gdb-xml/nanomips-fpu.xml > create mode 100644 gdb-xml/nanomips-linux.xml > Stefan, Can you clarify here: - Was the intention to implement XML support for nanoMIPS only? - In any case, is there a way to support pre-nanoMIPS MIPS configurations that would require only a reasonable implementation time? Thanks, Aleksandar
[Qemu-devel] [PATCH v3 01/40] target/mips: Add preprocessor constants for nanoMIPS
From: Aleksandar Markovic Add ISA_NANOMIPS32 and CPU_NANOMIPS32 preprocessor constants. Reviewed-by: Richard Henderson Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- target/mips/mips-defs.h | 4 1 file changed, 4 insertions(+) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index d239069..c8e9979 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -39,6 +39,7 @@ #define ISA_MIPS64R5 0x1000 #define ISA_MIPS32R6 0x2000 #define ISA_MIPS64R6 0x4000 +#define ISA_NANOMIPS32 0x8000 /* MIPS ASEs. */ #define ASE_MIPS160x0001 @@ -87,6 +88,9 @@ #define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6) #define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6) +/* Wave Computing: "nanoMIPS" */ +#define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32) + /* Strictly follow the architecture standard: - Disallow "special" instruction handling for PMON/SPIM. Note that we still maintain Count/Compare to match the host clock. */ -- 2.7.4
[Qemu-devel] [PATCH v6 04/11] target/mips: Avoid case statements formulated by ranges
From: Aleksandar Markovic
Remove "range style" case statements to make code analysis easier.
This is needed also for some upcoming nanoMIPS-related refactorings.
Signed-off-by: Aleksandar Markovic
Reviewed-by: Philippe Mathieu-Daudé
---
target/mips/translate.c | 249 ++--
1 file changed, 200 insertions(+), 49 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 20b43c0..051dda5 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -5494,7 +5494,14 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case 18:
switch (sel) {
-case 0 ... 7:
+case 0:
+case 1:
+case 2:
+case 3:
+case 4:
+case 5:
+case 6:
+case 7:
gen_helper_1e0i(mfc0_watchlo, arg, sel);
rn = "WatchLo";
break;
@@ -5504,7 +5511,14 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case 19:
switch (sel) {
-case 0 ...7:
+case 0:
+case 1:
+case 2:
+case 3:
+case 4:
+case 5:
+case 6:
+case 7:
gen_helper_1e0i(mfc0_watchhi, arg, sel);
rn = "WatchHi";
break;
@@ -5630,7 +5644,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case 27:
switch (sel) {
-case 0 ... 3:
+case 0:
+case 1:
+case 2:
+case 3:
tcg_gen_movi_tl(arg, 0); /* unimplemented */
rn = "CacheErr";
break;
@@ -5701,7 +5718,12 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
rn = "DESAVE";
break;
-case 2 ... 7:
+case 2:
+case 3:
+case 4:
+case 5:
+case 6:
+case 7:
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_ld_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
@@ -6167,7 +6189,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case 18:
switch (sel) {
-case 0 ... 7:
+case 0:
+case 1:
+case 2:
+case 3:
+case 4:
+case 5:
+case 6:
+case 7:
gen_helper_0e1i(mtc0_watchlo, arg, sel);
rn = "WatchLo";
break;
@@ -6177,7 +6206,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case 19:
switch (sel) {
-case 0 ... 7:
+case 0:
+case 1:
+case 2:
+case 3:
+case 4:
+case 5:
+case 6:
+case 7:
gen_helper_0e1i(mtc0_watchhi, arg, sel);
rn = "WatchHi";
break;
@@ -6315,7 +6351,10 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case 27:
switch (sel) {
-case 0 ... 3:
+case 0:
+case 1:
+case 2:
+case 3:
/* ignored */
rn = "CacheErr";
break;
@@ -6381,7 +6420,12 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
rn = "DESAVE";
break;
-case 2 ... 7:
+case 2:
+case 3:
+case 4:
+case 5:
+case 6:
+case 7:
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
@@ -6842,7 +6886,14 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case 18:
switch (sel) {
-case 0 ... 7:
+case 0:
+case 1:
+case 2:
+case 3:
+case 4:
+case 5:
+case 6:
+case 7:
gen_helper_1e0i(dmfc0_watchlo, arg, sel);
rn = "WatchLo";
break;
@@ -6852,7 +6903,14 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case 19:
switch (sel) {
-case 0 ... 7:
+case 0:
+case 1:
+case 2:
+case 3:
+case 4:
+case 5:
+case 6:
+case 7:
gen_helper_1e0i(mfc0_watchhi, arg, sel);
rn = "WatchHi";
break;
@@ -6975,7 +7033,10 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
case 27:
switch (sel) {
/* ignored */
-case 0 ... 3:
+case 0:
+case 1:
+case 2:
+case 3:
tcg_gen_movi_tl(arg, 0); /* unimplemented */
rn = "CacheErr";
break;
@
[Qemu-devel] [PATCH v3 27/40] target/mips: Adjust behavior of Config3's ISAOnExc bit for nanoMIPS
From: Yongbok Kim
Config3.ISAOnExc is read only in nanoMIPS.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/op_helper.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index cb83b6d..5e10286 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -1730,7 +1730,8 @@ void helper_mtc0_config2(CPUMIPSState *env, target_ulong
arg1)
void helper_mtc0_config3(CPUMIPSState *env, target_ulong arg1)
{
-if (env->insn_flags & ASE_MICROMIPS) {
+if ((env->insn_flags & ASE_MICROMIPS) &&
+!(env->insn_flags & ISA_NANOMIPS32)) {
env->CP0_Config3 = (env->CP0_Config3 & ~(1 << CP0C3_ISA_ON_EXC)) |
(arg1 & (1 << CP0C3_ISA_ON_EXC));
}
--
2.7.4
[Qemu-devel] [PATCH v6 06/11] target/mips: Don't update BadVAddr register in Debug Mode
From: Yongbok Kim
BadVAddr should not be updated if (env->hflags & MIPS_HFLAG_DM) is
set.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Reviewed-by: Philippe Mathieu-Daudé
---
target/mips/helper.c| 4 +++-
target/mips/op_helper.c | 12 +---
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/target/mips/helper.c b/target/mips/helper.c
index 8cf91ce..e215af9 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -502,7 +502,9 @@ static void raise_mmu_exception(CPUMIPSState *env,
target_ulong address,
break;
}
/* Raise exception */
-env->CP0_BadVAddr = address;
+if (!(env->hflags & MIPS_HFLAG_DM)) {
+env->CP0_BadVAddr = address;
+}
env->CP0_Context = (env->CP0_Context & ~0x007f) |
((address >> 9) & 0x0070);
env->CP0_EntryHi = (env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask) |
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 41d3634..0b2663b 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -271,7 +271,9 @@ static inline hwaddr do_translate_address(CPUMIPSState *env,
target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
{ \
if (arg & almask) { \
-env->CP0_BadVAddr = arg; \
+if (!(env->hflags & MIPS_HFLAG_DM)) { \
+env->CP0_BadVAddr = arg; \
+} \
do_raise_exception(env, EXCP_AdEL, GETPC()); \
} \
env->lladdr = do_translate_address(env, arg, 0, GETPC()); \
@@ -291,7 +293,9 @@ target_ulong helper_##name(CPUMIPSState *env, target_ulong
arg1, \
target_long tmp; \
\
if (arg2 & almask) { \
-env->CP0_BadVAddr = arg2; \
+if (!(env->hflags & MIPS_HFLAG_DM)) { \
+env->CP0_BadVAddr = arg2; \
+} \
do_raise_exception(env, EXCP_AdES, GETPC()); \
} \
if (do_translate_address(env, arg2, 1, GETPC()) == env->lladdr) { \
@@ -2437,7 +2441,9 @@ void mips_cpu_do_unaligned_access(CPUState *cs, vaddr
addr,
int error_code = 0;
int excp;
-env->CP0_BadVAddr = addr;
+if (!(env->hflags & MIPS_HFLAG_DM)) {
+env->CP0_BadVAddr = addr;
+}
if (access_type == MMU_DATA_STORE) {
excp = EXCP_AdES;
--
2.7.4
[Qemu-devel] [PATCH v3 11/40] target/mips: Add emulation of nanoMIPS 48-bit instructions
From: Yongbok Kim
Add emulation of LI48, ADDIU48, ADDIUGP48, ADDIUPC48, LWPC48, and
SWPC48 instructions.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
Reviewed-by: Aleksandar Markovic
---
target/mips/translate.c | 66 +
1 file changed, 66 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 201baf1..c47ee7d 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16682,6 +16682,72 @@ static int decode_nanomips_32_48_opc(CPUMIPSState
*env, DisasContext *ctx)
}
break;
case NM_P48I:
+insn = cpu_lduw_code(env, ctx->base.pc_next + 4);
+switch ((ctx->opcode >> 16) & 0x1f) {
+case NM_LI48:
+if (rt != 0) {
+tcg_gen_movi_tl(cpu_gpr[rt],
+extract32(ctx->opcode, 0, 16) | insn << 16);
+}
+break;
+case NM_ADDIU48:
+if (rt != 0) {
+tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rt],
+extract32(ctx->opcode, 0, 16) | insn << 16);
+tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
+}
+break;
+case NM_ADDIUGP48:
+if (rt != 0) {
+tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[28],
+extract32(ctx->opcode, 0, 16) | insn << 16);
+tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
+}
+break;
+case NM_ADDIUPC48:
+if (rt != 0) {
+int32_t offset = extract32(ctx->opcode, 0, 16) | insn << 16;
+target_long addr = addr_add(ctx, ctx->base.pc_next + 6,
offset);
+
+tcg_gen_movi_tl(cpu_gpr[rt], addr);
+tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]);
+}
+break;
+case NM_LWPC48:
+if (rt != 0) {
+TCGv t0;
+t0 = tcg_temp_new();
+
+int32_t offset = extract32(ctx->opcode, 0, 16) | insn << 16;
+target_long addr = addr_add(ctx, ctx->base.pc_next + 6,
offset);
+
+tcg_gen_movi_tl(t0, addr);
+tcg_gen_qemu_ld_tl(cpu_gpr[rt], t0, ctx->mem_idx, MO_TESL);
+tcg_temp_free(t0);
+}
+break;
+case NM_SWPC48:
+{
+TCGv t0, t1;
+t0 = tcg_temp_new();
+t1 = tcg_temp_new();
+
+int32_t offset = extract32(ctx->opcode, 0, 16) | insn << 16;
+target_long addr = addr_add(ctx, ctx->base.pc_next + 6,
offset);
+
+tcg_gen_movi_tl(t0, addr);
+gen_load_gpr(t1, rt);
+
+tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
+
+tcg_temp_free(t0);
+tcg_temp_free(t1);
+}
+break;
+default:
+generate_exception_end(ctx, EXCP_RI);
+break;
+}
return 6;
case NM_P_U12:
switch ((ctx->opcode >> 12) & 0x0f) {
--
2.7.4
[Qemu-devel] [PATCH v6 08/11] elf: Remove duplicate preprocessor constant definition
From: Aleksandar Markovic Remove duplicate preprocessor constant definition for EF_MIPS_ARCH. The duplicate was introduced in commit 45506bdd. Signed-off-by: Aleksandar Markovic --- include/elf.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/elf.h b/include/elf.h index 934dbbd..c8aaa2a 100644 --- a/include/elf.h +++ b/include/elf.h @@ -33,7 +33,6 @@ typedef int64_t Elf64_Sxword; /* Flags in the e_flags field of the header */ /* MIPS architecture level. */ -#define EF_MIPS_ARCH0xf000 /* Legal values for MIPS architecture level. */ #define EF_MIPS_ARCH_1 0x /* -mips1 code. */ -- 2.7.4
[Qemu-devel] [PATCH v6 10/11] linux-user: Update MIPS syscall numbers up to kernel 4.18 headers
From: Aleksandar Markovic Synchronize content of linux-user/mips/syscall_nr.h and linux-user/mips64/syscall_nr.h with Linux kernel 4.18 headers. This adds 7 new syscall numbers, the last being NR_statx. Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- linux-user/mips/syscall_nr.h | 7 +++ linux-user/mips64/syscall_nr.h | 14 ++ 2 files changed, 21 insertions(+) diff --git a/linux-user/mips/syscall_nr.h b/linux-user/mips/syscall_nr.h index ced3280..6bbca74 100644 --- a/linux-user/mips/syscall_nr.h +++ b/linux-user/mips/syscall_nr.h @@ -363,3 +363,10 @@ #define TARGET_NR_userfaultfd (TARGET_NR_Linux + 357) #define TARGET_NR_membarrier(TARGET_NR_Linux + 358) #define TARGET_NR_mlock2(TARGET_NR_Linux + 359) +#define TARGET_NR_copy_file_range (TARGET_NR_Linux + 360) +#define TARGET_NR_preadv2 (TARGET_NR_Linux + 361) +#define TARGET_NR_pwritev2 (TARGET_NR_Linux + 362) +#define TARGET_NR_pkey_mprotect (TARGET_NR_Linux + 363) +#define TARGET_NR_pkey_alloc(TARGET_NR_Linux + 364) +#define TARGET_NR_pkey_free (TARGET_NR_Linux + 365) +#define TARGET_NR_statx (TARGET_NR_Linux + 366) diff --git a/linux-user/mips64/syscall_nr.h b/linux-user/mips64/syscall_nr.h index 746cc26..2e44eae 100644 --- a/linux-user/mips64/syscall_nr.h +++ b/linux-user/mips64/syscall_nr.h @@ -327,6 +327,13 @@ #define TARGET_NR_userfaultfd (TARGET_NR_Linux + 321) #define TARGET_NR_membarrier(TARGET_NR_Linux + 322) #define TARGET_NR_mlock2(TARGET_NR_Linux + 323) +#define TARGET_NR_copy_file_range (TARGET_NR_Linux + 324) +#define TARGET_NR_preadv2 (TARGET_NR_Linux + 325) +#define TARGET_NR_pwritev2 (TARGET_NR_Linux + 326) +#define TARGET_NR_pkey_mprotect (TARGET_NR_Linux + 327) +#define TARGET_NR_pkey_alloc(TARGET_NR_Linux + 328) +#define TARGET_NR_pkey_free (TARGET_NR_Linux + 329) +#define TARGET_NR_statx (TARGET_NR_Linux + 330) #else /* @@ -653,4 +660,11 @@ #define TARGET_NR_userfaultfd (TARGET_NR_Linux + 317) #define TARGET_NR_membarrier(TARGET_NR_Linux + 318) #define TARGET_NR_mlock2(TARGET_NR_Linux + 319) +#define TARGET_NR_copy_file_range (TARGET_NR_Linux + 320) +#define TARGET_NR_preadv2 (TARGET_NR_Linux + 321) +#define TARGET_NR_pwritev2 (TARGET_NR_Linux + 322) +#define TARGET_NR_pkey_mprotect (TARGET_NR_Linux + 323) +#define TARGET_NR_pkey_alloc(TARGET_NR_Linux + 324) +#define TARGET_NR_pkey_free (TARGET_NR_Linux + 325) +#define TARGET_NR_statx (TARGET_NR_Linux + 326) #endif -- 2.7.4
[Qemu-devel] [PATCH v6 00/11] Mips maintenance and misc fixes and improvements
From: Aleksandar Markovic v5->v6: - patch on updating CP0 register bit definitions expanded to include Config2, Config3, and Config4 registers - added 4 patches: - elf: Remove duplicate preprocessor constant definition - elf: Add ELF flags for MIPS machine variants - linux-user: Update MIPS syscall numbers up to kernel 4.18 - linux-user: Add availability control to some syscalls v4->v5: - patch 5 (Add CP0 BadInstrX) corrected to work for both 32-bit and 64-bit targets, and using correct tcg function - patch 7 (Amend CP0 WatchHi) was removed from the series until it is reimplemented in a better way v3->v4: - accepted suggestion on better format of bit definitions in patch 3 - fixed build errors caused by a mistake in patch 4 - removed spurious comments in patch 4 - added setting lower 16 bits to 0 in patch 5 - used proper email address for a reviewer in patch 7 commit message v2->v3: - replaced invalid @imgtec.com and @mips.com in "From:",, "Signed-off-by:", "Reviewed-by:" lines with the most current email addresses for a particular person - fixed build errors that appeared because of a mistake during integration v1->v2: - fixed recipient's email addresses Maintenance issues, fixes, and improvements collected during recent development. Some of them are related to the upcoming nanoMIPS changes. Aleksandar Markovic (7): target/mips: Update maintainer's email addresses target/mips: Workaround for checkpatch.pl hanging on msa_helper.c target/mips: Update some CP0 registers bit definitions target/mips: Avoid case statements formulated by ranges elf: Remove duplicate preprocessor constant definition elf: Add ELF flags for MIPS machine variants linux-user: Update MIPS syscall numbers up to kernel 4.18 headers Aleksandar Rikalo (1): linux-user: Add availability control to some syscalls Stefan Markovic (1): target/mips: Add CP0 BadInstrX register Yongbok Kim (2): target/mips: Don't update BadVAddr register in Debug Mode target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0 .mailmap | 7 +- MAINTAINERS| 9 +- include/elf.h | 24 +++- linux-user/mips/syscall_nr.h | 7 ++ linux-user/mips64/syscall_nr.h | 14 +++ linux-user/strace.c| 14 ++- linux-user/syscall.c | 25 target/mips/cpu.h | 158 +-- target/mips/helper.c | 4 +- target/mips/machine.c | 5 +- target/mips/msa_helper.c | 4 +- target/mips/op_helper.c| 12 +- target/mips/translate.c| 279 + 13 files changed, 423 insertions(+), 139 deletions(-) -- 2.7.4
[Qemu-devel] [PATCH v3 25/40] target/mips: Add updating CP0 BadInstrX register for nanoMIPs only
From: Stefan Markovic
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/helper.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/mips/helper.c b/target/mips/helper.c
index 5299f21..9535131 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -695,6 +695,12 @@ static inline void set_badinstr_registers(CPUMIPSState
*env)
instr |= cpu_lduw_code(env, env->active_tc.PC + 2);
}
env->CP0_BadInstr = instr;
+
+if ((env->insn_flags & ISA_NANOMIPS32) &&
+((instr & 0xFC00) == 0x6000)) {
+instr = cpu_lduw_code(env, env->active_tc.PC + 4) << 16;
+env->CP0_BadInstrX = instr;
+}
}
if ((env->CP0_Config3 & (1 << CP0C3_BP)) &&
(env->hflags & MIPS_HFLAG_BMASK)) {
--
2.7.4
[Qemu-devel] [PATCH v3 12/40] target/mips: Add emulation of nanoMIPS FP instructions
From: Yongbok Kim
Add emulation of basic floating point arithmetic for nanoMIPS.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
Reviewed-by: Aleksandar Markovic
---
target/mips/translate.c | 300
1 file changed, 300 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index c47ee7d..2c7f62e 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16588,6 +16588,305 @@ static void gen_pool16c_nanomips_insn(DisasContext
*ctx)
}
}
+static void gen_pool32f_nanomips_insn(DisasContext *ctx)
+{
+int rt, rs, rd;
+
+rt = (ctx->opcode >> 21) & 0x1f;
+rs = (ctx->opcode >> 16) & 0x1f;
+rd = (ctx->opcode >> 11) & 0x1f;
+
+if (!(ctx->CP0_Config1 & (1 << CP0C1_FP))) {
+generate_exception_end(ctx, EXCP_RI);
+return;
+}
+check_cp1_enabled(ctx);
+switch (ctx->opcode & 0x07) {
+case NM_POOL32F_0:
+switch ((ctx->opcode >> 3) & 0x7f) {
+case NM_RINT_S:
+gen_farith(ctx, OPC_RINT_S, 0, rt, rs, 0);
+break;
+case NM_RINT_D:
+gen_farith(ctx, OPC_RINT_D, 0, rt, rs, 0);
+break;
+case NM_CLASS_S:
+gen_farith(ctx, OPC_CLASS_S, 0, rt, rs, 0);
+break;
+case NM_CLASS_D:
+gen_farith(ctx, OPC_CLASS_D, 0, rt, rs, 0);
+break;
+case NM_ADD_S:
+gen_farith(ctx, OPC_ADD_S, rt, rs, rd, 0);
+break;
+case NM_ADD_D:
+gen_farith(ctx, OPC_ADD_D, rt, rs, rd, 0);
+break;
+case NM_SUB_S:
+gen_farith(ctx, OPC_SUB_S, rt, rs, rd, 0);
+break;
+case NM_SUB_D:
+gen_farith(ctx, OPC_SUB_D, rt, rs, rd, 0);
+break;
+case NM_MUL_S:
+gen_farith(ctx, OPC_MUL_S, rt, rs, rd, 0);
+break;
+case NM_MUL_D:
+gen_farith(ctx, OPC_MUL_D, rt, rs, rd, 0);
+break;
+case NM_DIV_S:
+gen_farith(ctx, OPC_DIV_S, rt, rs, rd, 0);
+break;
+case NM_DIV_D:
+gen_farith(ctx, OPC_DIV_D, rt, rs, rd, 0);
+break;
+case NM_SELEQZ_S:
+gen_sel_s(ctx, OPC_SELEQZ_S, rd, rt, rs);
+break;
+case NM_SELEQZ_D:
+gen_sel_d(ctx, OPC_SELEQZ_D, rd, rt, rs);
+break;
+case NM_SELNEZ_S:
+gen_sel_s(ctx, OPC_SELNEZ_S, rd, rt, rs);
+break;
+case NM_SELNEZ_D:
+gen_sel_d(ctx, OPC_SELNEZ_D, rd, rt, rs);
+break;
+case NM_SEL_S:
+gen_sel_s(ctx, OPC_SEL_S, rd, rt, rs);
+break;
+case NM_SEL_D:
+gen_sel_d(ctx, OPC_SEL_D, rd, rt, rs);
+break;
+case NM_MADDF_S:
+gen_farith(ctx, OPC_MADDF_S, rt, rs, rd, 0);
+break;
+case NM_MADDF_D:
+gen_farith(ctx, OPC_MADDF_D, rt, rs, rd, 0);
+break;
+case NM_MSUBF_S:
+gen_farith(ctx, OPC_MSUBF_S, rt, rs, rd, 0);
+break;
+case NM_MSUBF_D:
+gen_farith(ctx, OPC_MSUBF_D, rt, rs, rd, 0);
+break;
+default:
+generate_exception_end(ctx, EXCP_RI);
+break;
+}
+break;
+case NM_POOL32F_3:
+switch ((ctx->opcode >> 3) & 0x07) {
+case NM_MIN_FMT:
+switch ((ctx->opcode >> 9) & 1) {
+case FMT_SDPS_S:
+gen_farith(ctx, OPC_MIN_S, rt, rs, rd, 0);
+break;
+case FMT_SDPS_D:
+gen_farith(ctx, OPC_MIN_D, rt, rs, rd, 0);
+break;
+}
+break;
+case NM_MAX_FMT:
+switch ((ctx->opcode >> 9) & 1) {
+case FMT_SDPS_S:
+gen_farith(ctx, OPC_MAX_S, rt, rs, rd, 0);
+break;
+case FMT_SDPS_D:
+gen_farith(ctx, OPC_MAX_D, rt, rs, rd, 0);
+break;
+}
+break;
+case NM_MINA_FMT:
+switch ((ctx->opcode >> 9) & 1) {
+case FMT_SDPS_S:
+gen_farith(ctx, OPC_MINA_S, rt, rs, rd, 0);
+break;
+case FMT_SDPS_D:
+gen_farith(ctx, OPC_MINA_D, rt, rs, rd, 0);
+break;
+}
+break;
+case NM_MAXA_FMT:
+switch ((ctx->opcode >> 9) & 1) {
+case FMT_SDPS_S:
+gen_farith(ctx, OPC_MAXA_S, rt, rs, rd, 0);
+break;
+case FMT_SDPS_D:
+gen_farith(ctx, OPC_MAXA_D, rt, rs, rd, 0);
+break;
+}
+break;
+case NM_POOL32FXF:
+switch ((ctx->
[Qemu-devel] [PATCH v6 09/11] elf: Add ELF flags for MIPS machine variants
From: Aleksandar Markovic Add MIPS machine variants ELF flags so that the emulation behavior can be adjusted if needed. Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- include/elf.h | 23 +++ 1 file changed, 23 insertions(+) diff --git a/include/elf.h b/include/elf.h index c8aaa2a..2c4fe7a 100644 --- a/include/elf.h +++ b/include/elf.h @@ -62,6 +62,29 @@ typedef int64_t Elf64_Sxword; #define EF_MIPS_NAN2008 0x0400 #define EF_MIPS_ARCH 0xf000 +/* MIPS machine variant */ +#define EF_MIPS_MACH_NONE 0x /* A standard MIPS implementation */ +#define EF_MIPS_MACH_3900 0x0081 /* Toshiba R3900 */ +#define EF_MIPS_MACH_4010 0x0082 /* LSI R4010 */ +#define EF_MIPS_MACH_4100 0x0083 /* NEC VR4100 */ +#define EF_MIPS_MACH_4650 0x0085 /* MIPS R4650 */ +#define EF_MIPS_MACH_4120 0x0087 /* NEC VR4120 */ +#define EF_MIPS_MACH_4111 0x0088 /* NEC VR4111/VR4181 */ +#define EF_MIPS_MACH_SB1 0x008a /* Broadcom SB-1 */ +#define EF_MIPS_MACH_OCTEON 0x008b /* Cavium Networks Octeon */ +#define EF_MIPS_MACH_XLR 0x008c /* RMI Xlr */ +#define EF_MIPS_MACH_OCTEON2 0x008d /* Cavium Networks Octeon2 */ +#define EF_MIPS_MACH_OCTEON3 0x008e /* Cavium Networks Octeon3 */ +#define EF_MIPS_MACH_5400 0x0091 /* NEC VR5400 */ +#define EF_MIPS_MACH_5900 0x0092 /* MIPS R5900 */ +#define EF_MIPS_MACH_5500 0x0098 /* NEC VR5500 */ +#define EF_MIPS_MACH_9000 0x0099 /* Unknown */ +#define EF_MIPS_MACH_LS2E 0x00a0 /* ST Microelectronics Loongson 2E */ +#define EF_MIPS_MACH_LS2F 0x00a1 /* ST Microelectronics Loongson 2F */ +#define EF_MIPS_MACH_LS3A 0x00a2 /* Loongson 3A */ +#define EF_MIPS_MACH 0x00ff /* EF_MIPS_MACH_xxx selection mask */ + + /* These constants define the different elf file types */ #define ET_NONE 0 #define ET_REL1 -- 2.7.4
[Qemu-devel] [PATCH v3 13/40] target/mips: Add emulation of misc nanoMIPS instructions (pool32a0)
From: Yongbok Kim
Add emulation of nanoMIPS instructions that are situated in pool32a0.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
Reviewed-by: Aleksandar Markovic
---
target/mips/translate.c | 190
1 file changed, 190 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 2c7f62e..81c2950 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16588,6 +16588,186 @@ static void gen_pool16c_nanomips_insn(DisasContext
*ctx)
}
}
+static void gen_pool32a0_nanomips_insn(DisasContext *ctx)
+{
+int rt = (ctx->opcode >> 21) & 0x1f;
+int rs = (ctx->opcode >> 16) & 0x1f;
+int rd = (ctx->opcode >> 11) & 0x1f;
+
+switch ((ctx->opcode >> 3) & 0x7f) {
+case NM_P_TRAP:
+switch ((ctx->opcode >> 10) & 0x1) {
+case NM_TEQ:
+gen_trap(ctx, OPC_TEQ, rs, rt, -1);
+break;
+case NM_TNE:
+gen_trap(ctx, OPC_TNE, rs, rt, -1);
+break;
+}
+break;
+case NM_RDHWR:
+gen_rdhwr(ctx, rt, rs, extract32(ctx->opcode, 11, 3));
+break;
+case NM_SEB:
+gen_bshfl(ctx, OPC_SEB, rs, rt);
+break;
+case NM_SEH:
+gen_bshfl(ctx, OPC_SEH, rs, rt);
+break;
+case NM_SLLV:
+gen_shift(ctx, OPC_SLLV, rd, rt, rs);
+break;
+case NM_SRLV:
+gen_shift(ctx, OPC_SRLV, rd, rt, rs);
+break;
+case NM_SRAV:
+gen_shift(ctx, OPC_SRAV, rd, rt, rs);
+break;
+case NM_ROTRV:
+gen_shift(ctx, OPC_ROTRV, rd, rt, rs);
+break;
+case NM_ADD:
+gen_arith(ctx, OPC_ADD, rd, rs, rt);
+break;
+case NM_ADDU:
+gen_arith(ctx, OPC_ADDU, rd, rs, rt);
+break;
+case NM_SUB:
+gen_arith(ctx, OPC_SUB, rd, rs, rt);
+break;
+case NM_SUBU:
+gen_arith(ctx, OPC_SUBU, rd, rs, rt);
+break;
+case NM_P_CMOVE:
+switch ((ctx->opcode >> 10) & 1) {
+case NM_MOVZ:
+gen_cond_move(ctx, OPC_MOVZ, rd, rs, rt);
+break;
+case NM_MOVN:
+gen_cond_move(ctx, OPC_MOVN, rd, rs, rt);
+break;
+}
+break;
+case NM_AND:
+gen_logic(ctx, OPC_AND, rd, rs, rt);
+break;
+case NM_OR:
+gen_logic(ctx, OPC_OR, rd, rs, rt);
+break;
+case NM_NOR:
+gen_logic(ctx, OPC_NOR, rd, rs, rt);
+break;
+case NM_XOR:
+gen_logic(ctx, OPC_XOR, rd, rs, rt);
+break;
+case NM_SLT:
+gen_slt(ctx, OPC_SLT, rd, rs, rt);
+break;
+case NM_P_SLTU:
+if (rd == 0) {
+/* P_DVP */
+#ifndef CONFIG_USER_ONLY
+TCGv t0 = tcg_temp_new();
+switch ((ctx->opcode >> 10) & 1) {
+case NM_DVP:
+if (ctx->vp) {
+check_cp0_enabled(ctx);
+gen_helper_dvp(t0, cpu_env);
+gen_store_gpr(t0, rt);
+}
+break;
+case NM_EVP:
+if (ctx->vp) {
+check_cp0_enabled(ctx);
+gen_helper_evp(t0, cpu_env);
+gen_store_gpr(t0, rt);
+}
+break;
+}
+tcg_temp_free(t0);
+#endif
+} else {
+gen_slt(ctx, OPC_SLTU, rd, rs, rt);
+}
+break;
+case NM_SOV:
+{
+TCGv t0 = tcg_temp_local_new();
+TCGv t1 = tcg_temp_new();
+TCGv t2 = tcg_temp_new();
+TCGLabel *l1 = gen_new_label();
+
+gen_load_gpr(t1, rs);
+gen_load_gpr(t2, rt);
+tcg_gen_add_tl(t0, t1, t2);
+tcg_gen_ext32s_tl(t0, t0);
+tcg_gen_xor_tl(t1, t1, t2);
+tcg_gen_xor_tl(t2, t0, t2);
+tcg_gen_andc_tl(t1, t2, t1);
+
+tcg_gen_movi_tl(t0, 0);
+tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
+/* operands of same sign, result different sign */
+
+tcg_gen_movi_tl(t0, 1);
+gen_set_label(l1);
+gen_store_gpr(t0, rd);
+
+tcg_temp_free(t0);
+tcg_temp_free(t1);
+tcg_temp_free(t2);
+}
+break;
+case NM_MUL:
+gen_r6_muldiv(ctx, R6_OPC_MUL, rd, rs, rt);
+break;
+case NM_MUH:
+gen_r6_muldiv(ctx, R6_OPC_MUH, rd, rs, rt);
+break;
+case NM_MULU:
+gen_r6_muldiv(ctx, R6_OPC_MULU, rd, rs, rt);
+break;
+case NM_MUHU:
+gen_r6_muldiv(ctx, R6_OPC_MUHU, rd, rs, rt);
+break;
+case NM_DIV:
+gen_r6_muldiv(ctx, R6_OPC_DIV, rd, rs, rt);
+break;
+case NM_MOD:
+gen_r6_muldiv(ctx, R6_OPC_MOD, rd, rs, rt);
+break;
+case NM_DIVU:
+gen_r6_muldiv(ctx, R6_OPC_DIVU, rd, rs, rt);
+brea
[Qemu-devel] [PATCH v3 15/40] target/mips: Add emulation of misc nanoMIPS instructions (pool p_lsx)
From: Yongbok Kim
Add emulation of nanoMIPS instructions situated in pool p_lsx, and
emulation of LSA instruction as well.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
Reviewed-by: Aleksandar Markovic
---
target/mips/translate.c | 139 +++-
1 file changed, 138 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index af7825a..f3753bb 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16855,6 +16855,132 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState
*env, DisasContext *ctx)
}
}
+
+static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)
+{
+TCGv t0, t1;
+t0 = tcg_temp_new();
+t1 = tcg_temp_new();
+tcg_gen_movi_tl(t1, 0);
+if (rs == 0) {
+tcg_gen_movi_tl(t0, 0);
+} else {
+gen_load_gpr(t0, rs);
+}
+if (rt == 0) {
+tcg_gen_movi_tl(t1, 0);
+} else {
+gen_load_gpr(t1, rt);
+}
+if (((ctx->opcode >> 6) & 1) == 1) {
+/* PP.LSXS instructions require shifting */
+switch ((ctx->opcode >> 7) & 0xf) {
+case NM_LHXS:
+case NM_SHXS:
+case NM_LHUXS:
+tcg_gen_shli_tl(t0, t0, 1);
+break;
+case NM_LWXS:
+case NM_SWXS:
+case NM_LWC1XS:
+case NM_SWC1XS:
+tcg_gen_shli_tl(t0, t0, 2);
+break;
+case NM_LDC1XS:
+case NM_SDC1XS:
+tcg_gen_shli_tl(t0, t0, 3);
+break;
+}
+}
+gen_op_addr_add(ctx, t0, t0, t1);
+
+switch ((ctx->opcode >> 7) & 0xf) {
+case NM_LBX:
+tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
+ MO_SB);
+gen_store_gpr(t0, rd);
+break;
+case NM_LHX:
+/*case NM_LHXS:*/
+tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
+ MO_TESW);
+gen_store_gpr(t0, rd);
+break;
+case NM_LWX:
+/*case NM_LWXS:*/
+tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
+ MO_TESL);
+gen_store_gpr(t0, rd);
+break;
+case NM_LBUX:
+tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
+ MO_UB);
+gen_store_gpr(t0, rd);
+break;
+case NM_LHUX:
+/*case NM_LHUXS:*/
+tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
+ MO_TEUW);
+gen_store_gpr(t0, rd);
+break;
+case NM_SBX:
+gen_load_gpr(t1, rd);
+tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
+ MO_8);
+break;
+case NM_SHX:
+/*case NM_SHXS:*/
+gen_load_gpr(t1, rd);
+tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
+ MO_TEUW);
+break;
+case NM_SWX:
+/*case NM_SWXS:*/
+gen_load_gpr(t1, rd);
+tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
+ MO_TEUL);
+break;
+case NM_LWC1X:
+/*case NM_LWC1XS:*/
+case NM_LDC1X:
+/*case NM_LDC1XS:*/
+case NM_SWC1X:
+/*case NM_SWC1XS:*/
+case NM_SDC1X:
+/*case NM_SDC1XS:*/
+if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
+check_cp1_enabled(ctx);
+switch ((ctx->opcode >> 7) & 0xf) {
+case NM_LWC1X:
+/*case NM_LWC1XS:*/
+gen_flt_ldst(ctx, OPC_LWC1, rd, t0);
+break;
+case NM_LDC1X:
+/*case NM_LDC1XS:*/
+gen_flt_ldst(ctx, OPC_LDC1, rd, t0);
+break;
+case NM_SWC1X:
+/*case NM_SWC1XS:*/
+gen_flt_ldst(ctx, OPC_SWC1, rd, t0);
+break;
+case NM_SDC1X:
+/*case NM_SDC1XS:*/
+gen_flt_ldst(ctx, OPC_SDC1, rd, t0);
+break;
+}
+} else {
+generate_exception_err(ctx, EXCP_CpU, 1);
+}
+break;
+default:
+generate_exception_end(ctx, EXCP_RI);
+break;
+}
+
+tcg_temp_free(t0);
+tcg_temp_free(t1);
+}
+
static void gen_pool32f_nanomips_insn(DisasContext *ctx)
{
int rt, rs, rd;
@@ -17157,7 +17283,7 @@ static void gen_pool32f_nanomips_insn(DisasContext *ctx)
static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
{
uint16_t insn;
-int rt, rs;
+int rt, rs, rd;
uint32_t op;
insn = cpu_lduw_code(env, ctx->base.pc_next + 2);
@@ -17165,6 +17291,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env,
DisasContext *ctx)
rt = (ctx->opcode >> 21) & 0x1f;
rs = (ctx->opcode >> 16) & 0x1f;
+rd = (ctx->opcode >> 11) & 0x1f;
op = (ctx->opcode >> 26) & 0x3f;
switch (op) {
@@ -17226,6 +17353,16 @@ static int decod
[Qemu-devel] [PATCH v3 07/40] target/mips: Add emulation of nanoMIPS 16-bit load and store instructions
From: Yongbok Kim
Add emulation of LWXS16, LB16, SB16, LBU16, LH16, SH16, LHU16, LW16, LWSP16,
LW4X4, SW4X4, LWGP16, SWSP16, SW16, and SWGP16 instructions.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/translate.c | 114
1 file changed, 114 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 798f977..1a839be 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16472,6 +16472,14 @@ static int decode_gpr_gpr3(int r)
return map[r & 0x7];
}
+/* Used for 16-bit store instructions. */
+static int decode_gpr_gpr3_src_store(int r)
+{
+static const int map[] = { 0, 17, 18, 19, 4, 5, 6, 7 };
+
+return map[r & 0x7];
+}
+
static int decode_gpr_gpr4(int r)
{
static const int map[] = { 8, 9, 10, 11, 4, 5, 6, 7,
@@ -16568,6 +16576,13 @@ static int decode_nanomips_opc(CPUMIPSState *env,
DisasContext *ctx)
}
break;
case NM_P16C:
+switch (ctx->opcode & 1) {
+case NM_POOL16C_0:
+break;
+case NM_LWXS16:
+gen_ldxs(ctx, rt, rs, rd);
+break;
+}
break;
case NM_P16_A1:
switch ((ctx->opcode >> 6) & 1) {
@@ -16651,24 +1,123 @@ static int decode_nanomips_opc(CPUMIPSState *env,
DisasContext *ctx)
}
break;
case NM_P16_LB:
+{
+uint32_t u = extract32(ctx->opcode, 0, 2);
+switch (((ctx->opcode) >> 2) & 0x03) {
+case NM_LB16:
+gen_ld(ctx, OPC_LB, rt, rs, u);
+break;
+case NM_SB16:
+{
+int rt = decode_gpr_gpr3_src_store(
+ NANOMIPS_EXTRACT_RD(ctx->opcode));
+gen_st(ctx, OPC_SB, rt, rs, u);
+}
+break;
+case NM_LBU16:
+gen_ld(ctx, OPC_LBU, rt, rs, u);
+break;
+default:
+generate_exception_end(ctx, EXCP_RI);
+break;
+}
+}
break;
case NM_P16_LH:
+{
+uint32_t u = extract32(ctx->opcode, 1, 2) << 1;
+switch ctx->opcode >> 3) & 1) << 1) | (ctx->opcode & 1)) {
+case NM_LH16:
+gen_ld(ctx, OPC_LH, rt, rs, u);
+break;
+case NM_SH16:
+{
+int rt = decode_gpr_gpr3_src_store(
+ NANOMIPS_EXTRACT_RD(ctx->opcode));
+gen_st(ctx, OPC_SH, rt, rs, u);
+}
+break;
+case NM_LHU16:
+gen_ld(ctx, OPC_LHU, rt, rs, u);
+break;
+default:
+generate_exception_end(ctx, EXCP_RI);
+break;
+}
+}
break;
case NM_LW16:
+{
+int u = extract32(ctx->opcode, 0, 4) << 2;
+gen_ld(ctx, OPC_LW, rt, rs, u);
+}
break;
case NM_LWSP16:
+{
+int rt = NANOMIPS_EXTRACT_RD5(ctx->opcode);
+int u = extract32(ctx->opcode, 0, 5) << 2;
+
+gen_ld(ctx, OPC_LW, rt, 29, u);
+}
break;
case NM_LW4X4:
+{
+int rt = (extract32(ctx->opcode, 9, 1) << 3) |
+ extract32(ctx->opcode, 5, 3);
+int rs = (extract32(ctx->opcode, 4, 1) << 3) |
+ extract32(ctx->opcode, 0, 3);
+int u = (extract32(ctx->opcode, 3, 1) << 3) |
+(extract32(ctx->opcode, 8, 1) << 2);
+rt = decode_gpr_gpr4(rt);
+rs = decode_gpr_gpr4(rs);
+gen_ld(ctx, OPC_LW, rt, rs, u);
+}
break;
case NM_SW4X4:
+{
+int rt = (extract32(ctx->opcode, 9, 1) << 3) |
+ extract32(ctx->opcode, 5, 3);
+int rs = (extract32(ctx->opcode, 4, 1) << 3) |
+ extract32(ctx->opcode, 0, 3);
+int u = (extract32(ctx->opcode, 3, 1) << 3) |
+(extract32(ctx->opcode, 8, 1) << 2);
+rt = decode_gpr_gpr4_zero(rt);
+rs = decode_gpr_gpr4(rs);
+gen_st(ctx, OPC_SW, rt, rs, u);
+}
break;
case NM_LWGP16:
+{
+int u = extract32(ctx->opcode, 0, 7) << 2;
+gen_ld(ctx, OPC_LW, rt, 28, u);
+}
break;
case NM_SWSP16:
+{
+int rt = NANOMIPS_EXTRACT_RD5(ctx->opcode);
+int u = extract32(ctx->opcode, 0, 5) << 2;
+
+gen_st(ctx, OPC_SW, rt, 29, u);
+}
break;
case NM_SW16:
+
[Qemu-devel] [PATCH v6 01/11] target/mips: Update maintainer's email addresses
From: Aleksandar Markovic Update email addresses of Aleksandar Markovic and Paul Burton in the MAINTAINERS file. Also, add corresponding items in the .mailmap file. Signed-off-by: Aleksandar Markovic Reviewed-by: Philippe Mathieu-Daudé --- .mailmap| 7 +-- MAINTAINERS | 9 + 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/.mailmap b/.mailmap index 778a4d4..2c2b9b1 100644 --- a/.mailmap +++ b/.mailmap @@ -12,8 +12,11 @@ Fabrice Bellard bellard Jocelyn Mayer j_mayer Paul Brook pbrook -Paul Burton -Paul Burton +Aleksandar Markovic +Aleksandar Markovic +Paul Burton +Paul Burton +Paul Burton Thiemo Seufer ths malc malc diff --git a/MAINTAINERS b/MAINTAINERS index 666e936..7130807 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -187,7 +187,7 @@ F: disas/microblaze.c MIPS M: Aurelien Jarno -M: Aleksandar Markovic +M: Aleksandar Markovic S: Maintained F: target/mips/ F: hw/mips/ @@ -718,7 +718,7 @@ S: Maintained F: hw/mips/mips_malta.c Mipssim -M: Aleksandar Markovic +M: Aleksandar Markovic S: Odd Fixes F: hw/mips/mips_mipssim.c F: hw/net/mipsnet.c @@ -729,14 +729,15 @@ S: Maintained F: hw/mips/mips_r4k.c Fulong 2E -M: Aleksandar Markovic +M: Aleksandar Markovic S: Odd Fixes F: hw/mips/mips_fulong2e.c F: hw/isa/vt82c686.c + F: include/hw/isa/vt82c686.h Boston -M: Paul Burton +M: Paul Burton S: Maintained F: hw/core/loader-fit.c F: hw/mips/boston.c -- 2.7.4
[Qemu-devel] [PATCH v6 07/11] target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0
From: Yongbok Kim
MFHC0 and MTHC0 used to handle EntryLo0 and EntryLo1 registers only,
and placing ELPA flag checks before switch statement were technically
correct. However, after adding handling more registers, these checks
should be moved to act only in cases of handling EntryLo0 and
EntryLo1.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Reviewed-by: Aleksandar Markovic
---
target/mips/translate.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 9871182..de0d55b 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -4884,12 +4884,11 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
{
const char *rn = "invalid";
-CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
-
switch (reg) {
case 2:
switch (sel) {
case 0:
+CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo0));
rn = "EntryLo0";
break;
@@ -4900,6 +4899,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
case 3:
switch (sel) {
case 0:
+CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1));
rn = "EntryLo1";
break;
@@ -4952,12 +4952,11 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
const char *rn = "invalid";
uint64_t mask = ctx->PAMask >> 36;
-CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
-
switch (reg) {
case 2:
switch (sel) {
case 0:
+CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
tcg_gen_andi_tl(arg, arg, mask);
gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo0));
rn = "EntryLo0";
@@ -4969,6 +4968,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
case 3:
switch (sel) {
case 0:
+CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
tcg_gen_andi_tl(arg, arg, mask);
gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1));
rn = "EntryLo1";
--
2.7.4
[Qemu-devel] [PATCH v6 11/11] linux-user: Add availability control to some syscalls
From: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/strace.c | 14 +-
linux-user/syscall.c | 25 +
2 files changed, 38 insertions(+), 1 deletion(-)
diff --git a/linux-user/strace.c b/linux-user/strace.c
index bd897a3..33f4a50 100644
--- a/linux-user/strace.c
+++ b/linux-user/strace.c
@@ -2304,7 +2304,19 @@ print_statfs(const struct syscallname *name,
print_pointer(arg1, 1);
print_syscall_epilogue(name);
}
-#define print_statfs64 print_statfs
+#endif
+
+#ifdef TARGET_NR_statfs64
+static void
+print_statfs64(const struct syscallname *name,
+abi_long arg0, abi_long arg1, abi_long arg2,
+abi_long arg3, abi_long arg4, abi_long arg5)
+{
+print_syscall_prologue(name);
+print_string(arg0, 0);
+print_pointer(arg1, 1);
+print_syscall_epilogue(name);
+}
#endif
#ifdef TARGET_NR_symlink
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 3df3bdf..851dd77 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -7996,8 +7996,15 @@ abi_long do_syscall(void *cpu_env, int num, abi_long
arg1,
{
CPUState *cpu = ENV_GET_CPU(cpu_env);
abi_long ret;
+#if defined(TARGET_NR_stat) || defined(TARGET_NR_stat64) \
+|| defined(TARGET_NR_lstat) || defined(TARGET_NR_lstat64) \
+|| defined(TARGET_NR_fstat) || defined(TARGET_NR_fstat64)
struct stat st;
+#endif
+#if defined(TARGET_NR_statfs) || defined(TARGET_NR_statfs64) \
+|| defined(TARGET_NR_fstatfs)
struct statfs stfs;
+#endif
void *p;
#if defined(DEBUG_ERESTARTSYS)
@@ -8365,9 +8372,11 @@ abi_long do_syscall(void *cpu_env, int num, abi_long
arg1,
case TARGET_NR_oldstat:
goto unimplemented;
#endif
+#ifdef TARGET_NR_lseek
case TARGET_NR_lseek:
ret = get_errno(lseek(arg1, arg2, arg3));
break;
+#endif
#if defined(TARGET_NR_getxpid) && defined(TARGET_ALPHA)
/* Alpha specific */
case TARGET_NR_getxpid:
@@ -9251,6 +9260,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
ret = get_errno(sethostname(p, arg2));
unlock_user(p, arg1, 0);
break;
+#ifdef TARGET_NR_setrlimit
case TARGET_NR_setrlimit:
{
int resource = target_to_host_resource(arg1);
@@ -9264,6 +9274,8 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
ret = get_errno(setrlimit(resource, &rlim));
}
break;
+#endif
+#ifdef TARGET_NR_getrlimit
case TARGET_NR_getrlimit:
{
int resource = target_to_host_resource(arg1);
@@ -9280,6 +9292,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
}
}
break;
+#endif
case TARGET_NR_getrusage:
{
struct rusage rusage;
@@ -9644,15 +9657,19 @@ abi_long do_syscall(void *cpu_env, int num, abi_long
arg1,
ret = get_errno(munlockall());
break;
#endif
+#ifdef TARGET_NR_truncate
case TARGET_NR_truncate:
if (!(p = lock_user_string(arg1)))
goto efault;
ret = get_errno(truncate(p, arg2));
unlock_user(p, arg1, 0);
break;
+#endif
+#ifdef TARGET_NR_ftruncate
case TARGET_NR_ftruncate:
ret = get_errno(ftruncate(arg1, arg2));
break;
+#endif
case TARGET_NR_fchmod:
ret = get_errno(fchmod(arg1, arg2));
break;
@@ -9688,6 +9705,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
case TARGET_NR_profil:
goto unimplemented;
#endif
+#ifdef TARGET_NR_statfs
case TARGET_NR_statfs:
if (!(p = lock_user_string(arg1)))
goto efault;
@@ -9719,9 +9737,12 @@ abi_long do_syscall(void *cpu_env, int num, abi_long
arg1,
unlock_user_struct(target_stfs, arg2, 1);
}
break;
+#endif
+#ifdef TARGET_NR_fstatfs
case TARGET_NR_fstatfs:
ret = get_errno(fstatfs(arg1, &stfs));
goto convert_statfs;
+#endif
#ifdef TARGET_NR_statfs64
case TARGET_NR_statfs64:
if (!(p = lock_user_string(arg1)))
@@ -9969,6 +9990,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
unlock_user(p, arg1, 0);
goto do_stat;
#endif
+#ifdef TARGET_NR_fstat
case TARGET_NR_fstat:
{
ret = get_errno(fstat(arg1, &st));
@@ -9998,6 +10020,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long
arg1,
}
}
break;
+#endif
#ifdef TARGET_NR_olduname
case TARGET_NR_olduname:
goto unimplemented;
@@ -10997,6 +11020,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long
arg1,
break;
#ifdef CONFIG_SENDFILE
+#ifdef TARGET_NR_sendfile
case TARGET_NR_sendfile:
{
off_t *offp = NULL;
@@ -11017,6 +11041,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long
arg1,
}
break;
}
+#endif
#ifdef TARGET_NR_sendfile64
case TARGET_NR_sendfile64:
{
--
2.7.4
[Qemu-devel] [PATCH v6 03/11] target/mips: Update some CP0 registers bit definitions
From: Aleksandar Markovic
Update CP0 registers Config0, Config1, Config2, Config3,
Config4, and Config5 bit definitions.
Some of these bits will be utilized by upcoming nanoMIPS changes.
Signed-off-by: Aleksandar Markovic
Reviewed-by: Philippe Mathieu-Daudé
---
target/mips/cpu.h | 157 ++
1 file changed, 88 insertions(+), 69 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index cfe1735..77c638c 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -388,26 +388,27 @@ struct CPUMIPSState {
target_ulong CP0_CMGCRBase;
int32_t CP0_Config0;
#define CP0C0_M31
-#define CP0C0_K23 28
-#define CP0C0_KU 25
+#define CP0C0_K23 28/* 30..28 */
+#define CP0C0_KU 25/* 27..25 */
#define CP0C0_MDU 20
#define CP0C0_MM 18
#define CP0C0_BM 16
+#define CP0C0_Impl 16/* 24..16 */
#define CP0C0_BE 15
-#define CP0C0_AT 13
-#define CP0C0_AR 10
-#define CP0C0_MT 7
+#define CP0C0_AT 13/* 14..13 */
+#define CP0C0_AR 10/* 12..10 */
+#define CP0C0_MT 7 /* 9..7 */
#define CP0C0_VI 3
-#define CP0C0_K0 0
+#define CP0C0_K0 0 /* 2..0 */
int32_t CP0_Config1;
#define CP0C1_M31
-#define CP0C1_MMU 25
-#define CP0C1_IS 22
-#define CP0C1_IL 19
-#define CP0C1_IA 16
-#define CP0C1_DS 13
-#define CP0C1_DL 10
-#define CP0C1_DA 7
+#define CP0C1_MMU 25/* 30..25 */
+#define CP0C1_IS 22/* 24..22 */
+#define CP0C1_IL 19/* 21..19 */
+#define CP0C1_IA 16/* 18..16 */
+#define CP0C1_DS 13/* 15..13 */
+#define CP0C1_DL 10/* 12..10 */
+#define CP0C1_DA 7 /* 9..7 */
#define CP0C1_C2 6
#define CP0C1_MD 5
#define CP0C1_PC 4
@@ -417,67 +418,85 @@ struct CPUMIPSState {
#define CP0C1_FP 0
int32_t CP0_Config2;
#define CP0C2_M31
-#define CP0C2_TU 28
-#define CP0C2_TS 24
-#define CP0C2_TL 20
-#define CP0C2_TA 16
-#define CP0C2_SU 12
-#define CP0C2_SS 8
-#define CP0C2_SL 4
-#define CP0C2_SA 0
+#define CP0C2_TU 28/* 30..28 */
+#define CP0C2_TS 24/* 27..24 */
+#define CP0C2_TL 20/* 23..20 */
+#define CP0C2_TA 16/* 19..16 */
+#define CP0C2_SU 12/* 15..12 */
+#define CP0C2_SS 8 /* 11..8 */
+#define CP0C2_SL 4 /* 7..4 */
+#define CP0C2_SA 0 /* 3..0 */
int32_t CP0_Config3;
-#define CP0C3_M31
-#define CP0C3_BPG 30
-#define CP0C3_CMGCR 29
-#define CP0C3_MSAP 28
-#define CP0C3_BP 27
-#define CP0C3_BI 26
-#define CP0C3_SC 25
-#define CP0C3_IPLW 21
-#define CP0C3_MMAR 18
-#define CP0C3_MCU 17
-#define CP0C3_ISA_ON_EXC 16
-#define CP0C3_ISA 14
-#define CP0C3_ULRI 13
-#define CP0C3_RXI 12
-#define CP0C3_DSP2P 11
-#define CP0C3_DSPP 10
-#define CP0C3_LPA 7
-#define CP0C3_VEIC 6
-#define CP0C3_VInt 5
-#define CP0C3_SP 4
-#define CP0C3_CDMM 3
-#define CP0C3_MT 2
-#define CP0C3_SM 1
-#define CP0C3_TL 0
+#define CP0C3_M31
+#define CP0C3_BPG 30
+#define CP0C3_CMGCR29
+#define CP0C3_MSAP 28
+#define CP0C3_BP 27
+#define CP0C3_BI 26
+#define CP0C3_SC 25
+#define CP0C3_PW 24
+#define CP0C3_VZ 23
+#define CP0C3_IPLV 21/* 22..21 */
+#define CP0C3_MMAR 18/* 20..18 */
+#define CP0C3_MCU 17
+#define CP0C3_ISA_ON_EXC 16
+#define CP0C3_ISA 14/* 15..14 */
+#define CP0C3_ULRI 13
+#define CP0C3_RXI 12
+#define CP0C3_DSP2P11
+#define CP0C3_DSPP 10
+#define CP0C3_CTXTC9
+#define CP0C3_ITL 8
+#define CP0C3_LPA 7
+#define CP0C3_VEIC 6
+#define CP0C3_VInt 5
+#define CP0C3_SP 4
+#define CP0C3_CDMM 3
+#define CP0C3_MT 2
+#define CP0C3_SM 1
+#define CP0C3_TL 0
int32_t CP0_Config4;
int32_t CP0_Config4_rw_bitmask;
-#define CP0C4_M31
-#define CP0C4_IE 29
-#define CP0C4_AE 28
-#define CP0C4_KScrExist 16
-#define CP0C4_MMUExtDef 14
-#define CP0C4_FTLBPageSize 8
-#define CP0C4_FTLBWays 4
-#define CP0C4_FTLBSets 0
-#define CP0C4_MMUSizeExt 0
+#define CP0C4_M31
+#define CP0C4_IE 29/* 30..29 */
+#define CP0C4_AE 28
+#define CP0C4_VTLBSizeExt 24/* 27..24 */
+#define CP0C4_KScrExist16
+#define CP0C4_MMUExtDef14
+#define CP0C4_FTLBPageSize 8 /* 12..8 */
+/* bit layout if MMUExtDef=1 */
+#define CP0C4_MMUSizeExt 0 /* 7..0 */
+/* bit layout if MMUExtDef=2 */
+#define CP0C4_FTLBWays 4 /* 7..4 */
+#define CP0C4_FTLBSets 0 /* 3..0 */
int32_t CP0_Config5;
int32_t CP0_Config5_rw_bitmask;
-#define CP0C5_M 31
-#define CP0C5_K 30
-#define CP0C5_CV 29
-#define CP0C5_EVA28
-#define CP0C5_MSAEn 27
-#define CP0C5_XNP13
-#define CP0C5_UFE9
-#define CP0C5_FRE8
-#define CP0C5_VP 7
-#define CP0C5_SBRI 6
-#define CP0C5_MVH5
-#define CP0C5_LLB4
-#define CP
[Qemu-devel] [PATCH v3 03/40] target/mips: Add nanoMIPS DSP ASE opcodes
From: Stefan Markovic
Add nanoMIPS opcodes for DSP ASE instruction pools and instructions.
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/translate.c | 144
1 file changed, 144 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 6a99a61..227b2c0 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16142,10 +16142,154 @@ enum {
/* POOL32Axf instruction pool */
enum {
+NM_POOL32AXF_1 = 0x01,
+NM_POOL32AXF_2 = 0x02,
NM_POOL32AXF_4 = 0x04,
NM_POOL32AXF_5 = 0x05,
+NM_POOL32AXF_7 = 0x07,
};
+/* POOL32Axf_1 instruction pool */
+enum {
+NM_POOL32AXF_1_0 = 0x00,
+NM_POOL32AXF_1_1 = 0x01,
+NM_POOL32AXF_1_3 = 0x03,
+NM_POOL32AXF_1_4 = 0x04,
+NM_POOL32AXF_1_5 = 0x05,
+NM_POOL32AXF_1_7 = 0x07,
+};
+
+/* POOL32Axf_2 instruction pool */
+enum {
+NM_POOL32AXF_2_0_7 = 0x00,
+NM_POOL32AXF_2_8_15= 0x01,
+NM_POOL32AXF_2_16_23 = 0x02,
+NM_POOL32AXF_2_24_31 = 0x03,
+};
+
+/* POOL32Axf_{4, 5} instruction pool */
+enum {
+/* nanoMIPS DSP instructions */
+NM_ABSQ_S_QB= 0x00,
+NM_ABSQ_S_PH= 0x08,
+NM_ABSQ_S_W = 0x10,
+NM_PRECEQ_W_PHL = 0x28,
+NM_PRECEQ_W_PHR = 0x30,
+NM_PRECEQU_PH_QBL = 0x38,
+NM_PRECEQU_PH_QBR = 0x48,
+NM_PRECEU_PH_QBL= 0x58,
+NM_PRECEU_PH_QBR= 0x68,
+NM_PRECEQU_PH_QBLA = 0x39,
+NM_PRECEQU_PH_QBRA = 0x49,
+NM_PRECEU_PH_QBLA = 0x59,
+NM_PRECEU_PH_QBRA = 0x69,
+NM_REPLV_PH = 0x01,
+NM_REPLV_QB = 0x09,
+NM_BITREV = 0x18,
+NM_INSV = 0x20,
+NM_RADDU_W_QB = 0x78,
+
+NM_BITSWAP = 0x05,
+NM_WSBH = 0x3d,
+};
+
+/* POOL32Axf_7 instruction pool */
+enum {
+NM_SHRA_R_QB= 0x0,
+NM_SHRL_PH = 0x1,
+NM_REPL_QB = 0x2,
+};
+
+/* POOL32Axf_1_0 instruction pool */
+enum {
+NM_MFHI = 0x0,
+NM_MFLO = 0x1,
+NM_MTHI = 0x2,
+NM_MTLO = 0x3,
+};
+
+/* POOL32Axf_1_1 instruction pool */
+enum {
+NM_MTHLIP = 0x0,
+NM_SHILOV = 0x1,
+};
+
+/* POOL32Axf_1_3 instruction pool */
+enum {
+NM_RDDSP= 0x0,
+NM_WRDSP= 0x1,
+NM_EXTP = 0x2,
+NM_EXTPDP = 0x3,
+};
+
+/* POOL32Axf_1_4 instruction pool */
+enum {
+NM_SHLL_QB = 0x0,
+NM_SHRL_QB = 0x1,
+};
+
+/* POOL32Axf_1_5 instruction pool */
+enum {
+NM_MAQ_S_W_PHR = 0x0,
+NM_MAQ_S_W_PHL = 0x1,
+NM_MAQ_SA_W_PHR = 0x2,
+NM_MAQ_SA_W_PHL = 0x3,
+};
+
+/* POOL32Axf_1_7 instruction pool */
+enum {
+NM_EXTR_W = 0x0,
+NM_EXTR_R_W = 0x1,
+NM_EXTR_RS_W= 0x2,
+NM_EXTR_S_H = 0x3,
+};
+
+/* POOL32Axf_2_0_7 instruction pool */
+enum {
+NM_DPA_W_PH = 0x0,
+NM_DPAQ_S_W_PH = 0x1,
+NM_DPS_W_PH = 0x2,
+NM_DPSQ_S_W_PH = 0x3,
+NM_BALIGN = 0x4,
+NM_MADD = 0x5,
+NM_MULT = 0x6,
+NM_EXTRV_W = 0x7,
+};
+
+/* POOL32Axf_2_8_15 instruction pool */
+enum {
+NM_DPAX_W_PH= 0x0,
+NM_DPAQ_SA_L_W = 0x1,
+NM_DPSX_W_PH= 0x2,
+NM_DPSQ_SA_L_W = 0x3,
+NM_MADDU= 0x5,
+NM_MULTU= 0x6,
+NM_EXTRV_R_W= 0x7,
+};
+
+/* POOL32Axf_2_16_23 instruction pool */
+enum {
+NM_DPAU_H_QBL = 0x0,
+NM_DPAQX_S_W_PH = 0x1,
+NM_DPSU_H_QBL = 0x2,
+NM_DPSQX_S_W_PH = 0x3,
+NM_EXTPV= 0x4,
+NM_MSUB = 0x5,
+NM_MULSA_W_PH = 0x6,
+NM_EXTRV_RS_W = 0x7,
+};
+
+/* POOL32Axf_2_24_31 instruction pool */
+enum {
+NM_DPAU_H_QBR = 0x0,
+NM_DPAQX_SA_W_PH= 0x1,
+NM_DPSU_H_QBR = 0x2,
+NM_DPSQX_SA_W_PH= 0x3,
+NM_EXTPDPV = 0x4,
+NM_MSUBU= 0x5,
+NM_MULSAQ_S_W_PH= 0x6,
+NM_EXTRV_S_H= 0x7,
+};
/* POOL32Axf_{4, 5} instruction pool */
enum {
NM_CLO = 0x25,
--
2.7.4
[Qemu-devel] [PATCH v3 00/40] Add nanoMIPS support to QEMU
From: Aleksandar Markovic v2->v3: - added support for nanoMIPS-specifics in ELF headers - added support for CP0 Config0.WR bit - updated I7200 definition - improved indentation of some switch statements - slight reorganization of patches (splitting, order) - rebased to the latest code v1->v2: - added DSP ASE support - added MT ASE support - added GDB XML support - order of patches changed - commit messages and patch title improved accross the board - obsolete email addresses for authors and cosigners replaced with the right ones - some functions renamed to reflect better the documentation - some macros renamed to reflect better their nanoMIPS nature - streamlined formatting - some of other reviewer's comments addressed, but the majority was not; this is because the focus of this version was on completing the functionality as much as possible; remaining comments will be addressed in the subsequent versions of this series This series of patches implements recently announced nanoMIPS on QEMU. nanoMIPS is a variable length ISA containing 16, 32 and 48-bit wide instructions. It is designed to be portable at assembly level with other MIPS and microMIPS code, but contains a number of changes that enhance code density and efficiency. The largest portion of patches is nanoMIPS decoding engine. For more information, please refer to the following link: https://www.mips.com/products/architectures/nanomips/ Aleksandar Markovic (4): target/mips: Add preprocessor constants for nanoMIPS elf: Add nanoMIPS specific variations in ELF header fields elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS too linux-user: Don't check FCR31_NAN2008 bit for nanoMIPS James Hogan (5): target/mips: Implement emulation of nanoMIPS EXTW instruction target/mips: Adjust exception_resume_pc() for nanoMIPS target/mips: Adjust set_hflags_for_handler() for nanoMIPS target/mips: Adjust set_pc() for nanoMIPS gdbstub: Disable handling of nanoMIPS ISA bit in the MIPS gdbstub Matthew Fortune (3): target/mips: Implement emulation of nanoMIPS ROTX instruction target/mips: Add handling of branch delay slots for nanoMIPS mips_malta: Add basic nanoMIPS boot code for MIPS' Malta Paul Burton (1): mips_malta: Setup GT64120 BARs in nanoMIPS bootloader Stefan Markovic (8): target/mips: Add nanoMIPS DSP ASE opcodes target/mips: Implement MT ASE support for nanoMIPS target/mips: Implement DSP ASE support for nanoMIPS target/mips: Add updating CP0 BadInstrX register for nanoMIPs only target/mips: Implement CP0 Config0.WR bit functionality mips_malta: Fix semihosting argument passing for nanoMIPS bare metal gdbstub: Add XML support for GDB for nanoMIPS target/mips: Add definition of nanoMIPS I7200 CPU Yongbok Kim (19): target/mips: Add nanoMIPS base instruction set opcodes target/mips: Add decode_nanomips_opc() function target/mips: Add nanoMIPS decoding and extraction utilities target/mips: Add emulation of misc nanoMIPS 16-bit instructions target/mips: Add emulation of nanoMIPS 16-bit load and store instructions target/mips: Add emulation of nanoMIPS 16-bit logic instructions target/mips: Add emulation of nanoMIPS 16-bit save and restore instructions target/mips: Add emulation of some common nanoMIPS 32-bit instructions target/mips: Add emulation of nanoMIPS 48-bit instructions target/mips: Add emulation of nanoMIPS FP instructions target/mips: Add emulation of misc nanoMIPS instructions (pool32a0) target/mips: Add emulation of misc nanoMIPS instructions (pool32axf) target/mips: Add emulation of misc nanoMIPS instructions (pool p_lsx) target/mips: Add emulation of nanoMIPS 32-bit load and store instructions target/mips: Add emulation of nanoMIPS branch instructions target/mips: Implement emulation of nanoMIPS LLWP/SCWP pair target/mips: Add updating BadInstr and BadInstrP registers for nanoMIPS target/mips: Adjust behavior of Config3's ISAOnExc bit for nanoMIPS target/mips: Fix ERET/ERETNC behavior related to ADEL exception MAINTAINERS |3 +- gdb-xml/nanomips-cp0.xml | 13 + gdb-xml/nanomips-cpu.xml | 44 + gdb-xml/nanomips-dsp.xml | 20 + gdb-xml/nanomips-fpu.xml | 45 + gdb-xml/nanomips-linux.xml | 20 + hw/mips/mips_malta.c | 153 +- include/elf.h| 20 + linux-user/elfload.c |2 + linux-user/mips/cpu_loop.c | 28 +- target/mips/cpu.h|2 + target/mips/gdbstub.c| 13 +- target/mips/helper.c | 47 +- target/mips/helper.h |4 + target/mips/mips-defs.h |4 + target/mips/op_helper.c | 147 +- target/mips/translate.c | 7305 ++ target/mips/translate_init.inc.c | 40 + 18 files changed, 6474 insertions(+),
[Qemu-devel] [PATCH v6 02/11] target/mips: Workaround for checkpatch.pl hanging on msa_helper.c
From: Aleksandar Markovic
If checkpatch.pl is applied (using switch "-f") on file
target/mips/msa_helper.c, it will hang.
This is a workaround by correcting the source file. The workaround is
found by partial deleting and undeleting of the code in msa_helper.c
in binary search fashion.
The bug (for checkpatch.pl) is already reported to the qemu-devel list.
Signed-off-by: Aleksandar Markovic
---
target/mips/msa_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index c74e3cd..1691b70 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -2750,8 +2750,8 @@ void helper_msa_ftq_df(CPUMIPSState *env, uint32_t df,
uint32_t wd,
#define FMAXMIN_A(F, G, X, _S, _T, BITS, STATUS)\
do {\
-uint## BITS ##_t S = _S, T = _T;\
-uint## BITS ##_t as, at, xs, xt, xd;\
+uint## BITS ## _t S = _S, T = _T; \
+uint## BITS ## _t as, at, xs, xt, xd; \
if (NUMBER_QNAN_PAIR(S, T, BITS, STATUS)) { \
T = S; \
} \
--
2.7.4
[Qemu-devel] [PATCH v3 06/40] target/mips: Add emulation of misc nanoMIPS 16-bit instructions
From: Yongbok Kim
Add emulation of misc nanoMIPS 16-bit instructions from instruction
pools P16, P16.BR, P16.BRI, P16.4X4 and other related pools.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/translate.c | 258
1 file changed, 258 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 4e6ae1f..798f977 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16502,6 +16502,264 @@ static int decode_gpr_gpr4_zero(int r)
static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
{
+uint32_t op;
+int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD(ctx->opcode));
+int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS(ctx->opcode));
+int rd = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS1(ctx->opcode));
+
+/* make sure instructions are on a halfword boundary */
+if (ctx->base.pc_next & 0x1) {
+env->CP0_BadVAddr = ctx->base.pc_next;
+generate_exception_end(ctx, EXCP_AdEL);
+return 2;
+}
+
+op = (ctx->opcode >> 10) & 0x3f;
+switch (op) {
+case NM_P16_MV:
+{
+int rt = NANOMIPS_EXTRACT_RD5(ctx->opcode);
+if (rt != 0) {
+/* MOVE */
+int rs = NANOMIPS_EXTRACT_RS5(ctx->opcode);
+gen_arith(ctx, OPC_ADDU, rt, rs, 0);
+} else {
+/* P16.RI */
+switch ((ctx->opcode >> 3) & 0x3) {
+case NM_P16_SYSCALL:
+generate_exception_end(ctx, EXCP_SYSCALL);
+break;
+case NM_BREAK16:
+generate_exception_end(ctx, EXCP_BREAK);
+break;
+case NM_SDBBP16:
+if (is_uhi(extract32(ctx->opcode, 0, 3))) {
+gen_helper_do_semihosting(cpu_env);
+} else {
+if (ctx->hflags & MIPS_HFLAG_SBRI) {
+generate_exception_end(ctx, EXCP_RI);
+} else {
+generate_exception_end(ctx, EXCP_DBp);
+}
+}
+break;
+default:
+generate_exception_end(ctx, EXCP_RI);
+break;
+}
+}
+}
+break;
+case NM_P16_SHIFT:
+{
+int shift = (ctx->opcode) & 0x7;
+uint32_t opc = 0;
+shift = (shift == 0) ? 8 : shift;
+
+switch ((ctx->opcode >> 3) & 1) {
+case NM_SLL16:
+opc = OPC_SLL;
+break;
+case NM_SRL16:
+opc = OPC_SRL;
+break;
+}
+gen_shift_imm(ctx, opc, rt, rs, shift);
+}
+break;
+case NM_P16C:
+break;
+case NM_P16_A1:
+switch ((ctx->opcode >> 6) & 1) {
+case NM_ADDIUR1SP:
+gen_arith_imm(ctx, OPC_ADDIU, rt, 29,
+ extract32(ctx->opcode, 0, 6) << 2);
+break;
+default:
+generate_exception_end(ctx, EXCP_RI);
+break;
+}
+break;
+case NM_P16_A2:
+switch ((ctx->opcode >> 3) & 1) {
+case NM_ADDIUR2:
+{
+uint8_t u = (uint8_t) extract32(ctx->opcode, 0, 3) << 2;
+gen_arith_imm(ctx, OPC_ADDIU, rt, rs, u);
+}
+break;
+case NM_P_ADDIURS5:
+{
+int rt = extract32(ctx->opcode, 5, 5);
+if (rt != 0) {
+int s = (sextract32(ctx->opcode, 4, 1) << 3) |
+extract32(ctx->opcode, 0, 3);
+/* s = sign_extend( s[3] . s[2:0] , from_nbits = 4)*/
+gen_arith_imm(ctx, OPC_ADDIU, rt, rt, s);
+}
+}
+break;
+}
+break;
+case NM_P16_ADDU:
+switch (ctx->opcode & 0x1) {
+case NM_ADDU16:
+gen_arith(ctx, OPC_ADDU, rd, rs, rt);
+break;
+case NM_SUBU16:
+gen_arith(ctx, OPC_SUBU, rd, rs, rt);
+break;
+}
+break;
+case NM_P16_4X4:
+{
+int rt = (extract32(ctx->opcode, 9, 1) << 3) |
+ extract32(ctx->opcode, 5, 3);
+int rs = (extract32(ctx->opcode, 4, 1) << 3) |
+ extract32(ctx->opcode, 0, 3);
+rt = decode_gpr_gpr4(rt);
+rs = decode_gpr_gpr4(rs);
+
+switch (((ctx->opcode >> 7) & 0x2) | ((ctx->opcode >> 3) & 0x1)) {
+case NM_ADDU4X4:
+gen_arith(ctx, OPC_ADDU, rt, rs, rt);
+
[Qemu-devel] [PATCH v3 18/40] target/mips: Add emulation of nanoMIPS 32-bit load and store instructions
From: Yongbok Kim
Add emulation of various nanoMIPS load and store instructions.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
Reviewed-by: Aleksandar Markovic
---
target/mips/translate.c | 271
1 file changed, 271 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 29d1f19..5dc6582 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -17668,10 +17668,281 @@ static int decode_nanomips_32_48_opc(CPUMIPSState
*env, DisasContext *ctx)
}
break;
case NM_P_GP_BH:
+{
+uint32_t u = extract32(ctx->opcode, 0, 18);
+switch ((ctx->opcode >> 18) & 0x7) {
+case NM_LBGP:
+gen_ld(ctx, OPC_LB, rt, 28, u);
+break;
+case NM_SBGP:
+gen_st(ctx, OPC_SB, rt, 28, u);
+break;
+case NM_LBUGP:
+gen_ld(ctx, OPC_LBU, rt, 28, u);
+break;
+case NM_ADDIUGP_B:
+gen_arith_imm(ctx, OPC_ADDIU, rt, 28, u);
+break;
+case NM_P_GP_LH:
+u &= ~1;
+switch (ctx->opcode & 1) {
+case NM_LHGP:
+gen_ld(ctx, OPC_LH, rt, 28, u);
+break;
+case NM_LHUGP:
+gen_ld(ctx, OPC_LHU, rt, 28, u);
+break;
+}
+break;
+case NM_P_GP_SH:
+u &= ~1;
+switch (ctx->opcode & 1) {
+case NM_SHGP:
+gen_st(ctx, OPC_SH, rt, 28, u);
+break;
+default:
+generate_exception_end(ctx, EXCP_RI);
+break;
+}
+break;
+case NM_P_GP_CP1:
+u &= ~0x3;
+switch ((ctx->opcode & 0x3)) {
+case NM_LWC1GP:
+gen_cop1_ldst(ctx, OPC_LWC1, rt, 28, u);
+break;
+case NM_LDC1GP:
+gen_cop1_ldst(ctx, OPC_LDC1, rt, 28, u);
+break;
+case NM_SWC1GP:
+gen_cop1_ldst(ctx, OPC_SWC1, rt, 28, u);
+break;
+case NM_SDC1GP:
+gen_cop1_ldst(ctx, OPC_SDC1, rt, 28, u);
+break;
+}
+break;
+default:
+generate_exception_end(ctx, EXCP_RI);
+break;
+}
+}
break;
case NM_P_LS_U12:
+{
+uint32_t u = extract32(ctx->opcode, 0, 12);
+switch ((ctx->opcode >> 12) & 0x0f) {
+case NM_P_PREFU12:
+if (rt == 31) {
+/* SYNCI */
+/* Break the TB to be able to sync copied instructions
+ immediately */
+ctx->base.is_jmp = DISAS_STOP;
+} else {
+/* PREF */
+/* Treat as NOP. */
+}
+break;
+case NM_LB:
+gen_ld(ctx, OPC_LB, rt, rs, u);
+break;
+case NM_LH:
+gen_ld(ctx, OPC_LH, rt, rs, u);
+break;
+case NM_LW:
+gen_ld(ctx, OPC_LW, rt, rs, u);
+break;
+case NM_LBU:
+gen_ld(ctx, OPC_LBU, rt, rs, u);
+break;
+case NM_LHU:
+gen_ld(ctx, OPC_LHU, rt, rs, u);
+break;
+case NM_SB:
+gen_st(ctx, OPC_SB, rt, rs, u);
+break;
+case NM_SH:
+gen_st(ctx, OPC_SH, rt, rs, u);
+break;
+case NM_SW:
+gen_st(ctx, OPC_SW, rt, rs, u);
+break;
+case NM_LWC1:
+gen_cop1_ldst(ctx, OPC_LWC1, rt, rs, u);
+break;
+case NM_LDC1:
+gen_cop1_ldst(ctx, OPC_LDC1, rt, rs, u);
+break;
+case NM_SWC1:
+gen_cop1_ldst(ctx, OPC_SWC1, rt, rs, u);
+break;
+case NM_SDC1:
+gen_cop1_ldst(ctx, OPC_SDC1, rt, rs, u);
+break;
+default:
+generate_exception_end(ctx, EXCP_RI);
+break;
+}
+}
break;
case NM_P_LS_S9:
+{
+int32_t s = (sextract32(ctx->opcode, 15, 1) << 8) |
+extract32(ctx->opcode, 0, 8);
+switch ((ctx->opcode >> 8) & 0x07) {
+case NM_P_LS_S0:
+switch ((ctx->opcode >> 11) & 0x0f) {
+case NM_LBS9:
+gen_ld(ctx, OPC_LB, rt, rs, s);
+break;
+case NM_LHS9:
+gen_ld(ctx, OPC_LH, rt, rs, s);
+break;
+case NM_LWS9:
+gen_ld(ctx, OPC_LW, rt, rs, s);
+break;
+case NM_LBUS9:
+gen_ld(ctx, OPC_LBU, rt, rs, s);
+break;
+case NM_LHUS9:
+gen_ld(ctx, OPC_LHU, rt,
[Qemu-devel] [PATCH v3 05/40] target/mips: Add nanoMIPS decoding and extraction utilities
From: Yongbok Kim
Add some basic utility functions and macros for nanoMIPS decoding
engine.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/translate.c | 35 +++
1 file changed, 35 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 67a0f70..4e6ae1f 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16465,6 +16465,41 @@ enum {
*
*/
+static int decode_gpr_gpr3(int r)
+{
+static const int map[] = { 16, 17, 18, 19, 4, 5, 6, 7 };
+
+return map[r & 0x7];
+}
+
+static int decode_gpr_gpr4(int r)
+{
+static const int map[] = { 8, 9, 10, 11, 4, 5, 6, 7,
+16, 17, 18, 19, 20, 21, 22, 23 };
+
+return map[r & 0xf];
+}
+
+/* Used for 16-bit store instructions. */
+static int decode_gpr_gpr4_zero(int r)
+{
+static const int map[] = { 8, 9, 10, 0, 4, 5, 6, 7,
+16, 17, 18, 19, 20, 21, 22, 23 };
+
+return map[r & 0xf];
+}
+
+
+/* extraction utilities */
+
+#define NANOMIPS_EXTRACT_RD(op) ((op >> 7) & 0x7)
+#define NANOMIPS_EXTRACT_RS(op) ((op >> 4) & 0x7)
+#define NANOMIPS_EXTRACT_RS2(op) uMIPS_RS(op)
+#define NANOMIPS_EXTRACT_RS1(op) ((op >> 1) & 0x7)
+#define NANOMIPS_EXTRACT_RD5(op) ((op >> 5) & 0x1f)
+#define NANOMIPS_EXTRACT_RS5(op) (op & 0x1f)
+
+
static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
{
return 2;
--
2.7.4
[Qemu-devel] [PATCH v3 04/40] target/mips: Add decode_nanomips_opc() function
From: Yongbok Kim
Add empty body and invocation of decode_nanomips_opc() if the bit
ISA_NANOMIPS32 is set in env->insn_flags.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/translate.c | 22 --
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 227b2c0..67a0f70 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16458,6 +16458,19 @@ enum {
NM_EVP = 0x01,
};
+
+/*
+ *
+ * nanoMIPS decoding engine
+ *
+ */
+
+static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
+{
+return 2;
+}
+
+
/* SmartMIPS extension to MIPS32 */
#if defined(TARGET_MIPS64)
@@ -21263,8 +21276,13 @@ static void mips_tr_translate_insn(DisasContextBase
*dcbase, CPUState *cs)
insn_bytes = 4;
decode_opc(env, ctx);
} else if (ctx->insn_flags & ASE_MICROMIPS) {
-ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next);
-insn_bytes = decode_micromips_opc(env, ctx);
+if (env->insn_flags & ISA_NANOMIPS32) {
+ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next);
+insn_bytes = decode_nanomips_opc(env, ctx);
+} else {
+ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next);
+insn_bytes = decode_micromips_opc(env, ctx);
+}
} else if (ctx->insn_flags & ASE_MIPS16) {
ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next);
insn_bytes = decode_mips16_opc(env, ctx);
--
2.7.4
[Qemu-devel] [PATCH v3 34/40] linux-user: Don't check FCR31_NAN2008 bit for nanoMIPS
From: Aleksandar Markovic
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
linux-user/mips/cpu_loop.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c
index 1d3dc9e..c9c20cf 100644
--- a/linux-user/mips/cpu_loop.c
+++ b/linux-user/mips/cpu_loop.c
@@ -747,6 +747,9 @@ void target_cpu_copy_regs(CPUArchState *env, struct
target_pt_regs *regs)
if (regs->cp0_epc & 1) {
env->hflags |= MIPS_HFLAG_M16;
}
+if (env->insn_flags & ISA_NANOMIPS32) {
+return;
+}
if (((info->elf_flags & EF_MIPS_NAN2008) != 0) !=
((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) != 0)) {
if ((env->active_fpu.fcr31_rw_bitmask &
--
2.7.4
[Qemu-devel] [PATCH v3 22/40] target/mips: Add handling of branch delay slots for nanoMIPS
From: Matthew Fortune
ISA mode bit (LSB of address) is no longer required but is also
masked to allow for tools transition. The flag has_isa_mode has the
key role in the implementation.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/translate.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index d7454a6..7fb2ff9 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1458,6 +1458,7 @@ typedef struct DisasContext {
bool mrp;
bool nan2008;
bool abs2008;
+bool has_isa_mode;
} DisasContext;
#define DISAS_STOP DISAS_TARGET_0
@@ -4538,7 +4539,7 @@ static void gen_compute_branch (DisasContext *ctx,
uint32_t opc,
if (blink > 0) {
int post_delay = insn_bytes + delayslot_size;
-int lowbit = !!(ctx->hflags & MIPS_HFLAG_M16);
+int lowbit = ctx->has_isa_mode && !!(ctx->hflags & MIPS_HFLAG_M16);
tcg_gen_movi_tl(cpu_gpr[blink],
ctx->base.pc_next + post_delay + lowbit);
@@ -10991,7 +10992,8 @@ static void gen_branch(DisasContext *ctx, int
insn_bytes)
break;
case MIPS_HFLAG_BR:
/* unconditional branch to register */
-if (ctx->insn_flags & (ASE_MIPS16 | ASE_MICROMIPS)) {
+if (ctx->has_isa_mode &&
+(ctx->insn_flags & (ASE_MIPS16 | ASE_MICROMIPS))) {
TCGv t0 = tcg_temp_new();
TCGv_i32 t1 = tcg_temp_new_i32();
@@ -11027,7 +11029,7 @@ static void gen_compute_compact_branch(DisasContext
*ctx, uint32_t opc,
int bcond_compute = 0;
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
-int m16_lowbit = (ctx->hflags & MIPS_HFLAG_M16) != 0;
+int m16_lowbit = ctx->has_isa_mode && ((ctx->hflags & MIPS_HFLAG_M16) !=
0);
if (ctx->hflags & MIPS_HFLAG_BMASK) {
#ifdef MIPS_DEBUG_DISAS
@@ -24747,6 +24749,7 @@ static void mips_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
ctx->mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1;
ctx->nan2008 = (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1;
ctx->abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1;
+ctx->has_isa_mode = ((env->CP0_Config3 >> CP0C3_MMAR) & 0x7) != 3;
restore_cpu_state(env, ctx);
#ifdef CONFIG_USER_ONLY
ctx->mem_idx = MIPS_HFLAG_UM;
--
2.7.4
[Qemu-devel] [PATCH v3 19/40] target/mips: Add emulation of nanoMIPS branch instructions
From: Yongbok Kim
Add emulation of various flavors of nanoMIPS branch instructions.
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
Reviewed-by: Aleksandar Markovic
---
target/mips/translate.c | 277
1 file changed, 277 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 5dc6582..50b31de 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16871,6 +16871,168 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState
*env, DisasContext *ctx)
}
}
+/* Immediate Value Compact Branches */
+static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc,
+ int rt, int32_t imm, int32_t offset)
+{
+int bcond_compute = 0;
+TCGv t0 = tcg_temp_new();
+TCGv t1 = tcg_temp_new();
+
+if (ctx->hflags & MIPS_HFLAG_BMASK) {
+#ifdef MIPS_DEBUG_DISAS
+LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx
+ "\n", ctx->base.pc_next);
+#endif
+generate_exception_end(ctx, EXCP_RI);
+goto out;
+}
+
+gen_load_gpr(t0, rt);
+tcg_gen_movi_tl(t1, imm);
+ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset);
+
+/* Load needed operands and calculate btarget */
+switch (opc) {
+case NM_BEQIC:
+if (rt == 0 && imm == 0) {
+/* Unconditional branch */
+} else if (rt == 0 && imm != 0) {
+/* Treat as NOP */
+goto out;
+} else {
+bcond_compute = 1;
+}
+break;
+case NM_BBEQZC:
+case NM_BBNEZC:
+if (imm >= 32 && !(ctx->hflags & MIPS_HFLAG_64)) {
+generate_exception_end(ctx, EXCP_RI);
+goto out;
+} else if (rt == 0 && opc == NM_BBEQZC) {
+/* Unconditional branch */
+} else if (rt == 0 && opc == NM_BBNEZC) {
+/* Treat as NOP */
+goto out;
+} else {
+tcg_gen_shri_tl(t0, t0, imm);
+tcg_gen_andi_tl(t0, t0, 1);
+tcg_gen_movi_tl(t1, 0);
+bcond_compute = 1;
+}
+break;
+case NM_BNEIC:
+if (rt == 0 && imm == 0) {
+/* Treat as NOP */
+goto out;
+} else if (rt == 0 && imm != 0) {
+/* Unconditional branch */
+} else {
+bcond_compute = 1;
+}
+break;
+case NM_BGEIC:
+if (rt == 0 && imm == 0) {
+/* Unconditional branch */
+} else {
+bcond_compute = 1;
+}
+break;
+case NM_BLTIC:
+bcond_compute = 1;
+break;
+case NM_BGEIUC:
+if (rt == 0 && imm == 0) {
+/* Unconditional branch */
+} else {
+bcond_compute = 1;
+}
+break;
+case NM_BLTIUC:
+bcond_compute = 1;
+break;
+default:
+MIPS_INVAL("Immediate Value Compact branch");
+generate_exception_end(ctx, EXCP_RI);
+goto out;
+}
+
+if (bcond_compute == 0) {
+/* Uncoditional compact branch */
+ctx->hflags |= MIPS_HFLAG_B;
+/* Generating branch here as compact branches don't have delay slot */
+gen_branch(ctx, 4);
+} else {
+/* Conditional compact branch */
+TCGLabel *fs = gen_new_label();
+save_cpu_state(ctx, 0);
+
+switch (opc) {
+case NM_BEQIC:
+tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_EQ), t0, t1, fs);
+break;
+case NM_BBEQZC:
+tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_EQ), t0, t1, fs);
+break;
+case NM_BNEIC:
+tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_NE), t0, t1, fs);
+break;
+case NM_BBNEZC:
+tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_NE), t0, t1, fs);
+break;
+case NM_BGEIC:
+tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_GE), t0, t1, fs);
+break;
+case NM_BLTIC:
+tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_LT), t0, t1, fs);
+break;
+case NM_BGEIUC:
+tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_GEU), t0, t1, fs);
+break;
+case NM_BLTIUC:
+tcg_gen_brcond_tl(tcg_invert_cond(TCG_COND_LTU), t0, t1, fs);
+break;
+}
+
+/* Generating branch here as compact branches don't have delay slot */
+gen_goto_tb(ctx, 1, ctx->btarget);
+gen_set_label(fs);
+
+ctx->hflags |= MIPS_HFLAG_FBNSLOT;
+}
+
+out:
+tcg_temp_free(t0);
+tcg_temp_free(t1);
+}
+
+/* P.BALRSC type nanoMIPS R6 branches: BALRSC and BRSC */
+static void gen_compute_nanomips_pbalrsc_branch(DisasContext *ctx, int rs,
+
[Qemu-devel] [PATCH v3 08/40] target/mips: Add emulation of nanoMIPS 16-bit logic instructions
From: Yongbok Kim
Add emulation of NOT16, AND16, XOR16, OR16 instructions.
Reviewed-by: Richard Henderson
Signed-off-by: Yongbok Kim
Signed-off-by: Aleksandar Markovic
Signed-off-by: Stefan Markovic
---
target/mips/translate.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 1a839be..12505a8 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16508,6 +16508,27 @@ static int decode_gpr_gpr4_zero(int r)
#define NANOMIPS_EXTRACT_RS5(op) (op & 0x1f)
+static void gen_pool16c_nanomips_insn(DisasContext *ctx)
+{
+int rt = decode_gpr_gpr3(NANOMIPS_EXTRACT_RD(ctx->opcode));
+int rs = decode_gpr_gpr3(NANOMIPS_EXTRACT_RS(ctx->opcode));
+
+switch ((ctx->opcode >> 2) & 0x3) {
+case NM_NOT16:
+gen_logic(ctx, OPC_NOR, rt, rs, 0);
+break;
+case NM_AND16:
+gen_logic(ctx, OPC_AND, rt, rt, rs);
+break;
+case NM_XOR16:
+gen_logic(ctx, OPC_XOR, rt, rt, rs);
+break;
+case NM_OR16:
+gen_logic(ctx, OPC_OR, rt, rt, rs);
+break;
+}
+}
+
static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
{
uint32_t op;
@@ -16578,6 +16599,7 @@ static int decode_nanomips_opc(CPUMIPSState *env,
DisasContext *ctx)
case NM_P16C:
switch (ctx->opcode & 1) {
case NM_POOL16C_0:
+gen_pool16c_nanomips_insn(ctx);
break;
case NM_LWXS16:
gen_ldxs(ctx, rt, rs, rd);
--
2.7.4
[Qemu-devel] [PATCH v3 32/40] elf: Add nanoMIPS specific variations in ELF header fields
From: Aleksandar Markovic Add nanoMIPS-related values in ELF header fields as specified in nanoMIPS' "ELF ABI Supplement". Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- include/elf.h | 20 1 file changed, 20 insertions(+) diff --git a/include/elf.h b/include/elf.h index 2c4fe7a..fff5967 100644 --- a/include/elf.h +++ b/include/elf.h @@ -62,6 +62,24 @@ typedef int64_t Elf64_Sxword; #define EF_MIPS_NAN2008 0x0400 #define EF_MIPS_ARCH 0xf000 +/* nanoMIPS architecture bits, EF_NANOMIPS_ARCH */ +#define EF_NANOMIPS_ARCH_32R6 0x /* 32-bit nanoMIPS Release 6 ISA */ +#define EF_NANOMIPS_ARCH_64R6 0x1000 /* 62-bit nanoMIPS Release 6 ISA */ + +/* nanoMIPS ABI bits, EF_NANOMIPS_ABI */ +#define EF_NANOMIPS_ABI_P32 0x1000 /* 32-bit nanoMIPS ABI */ +#define EF_NANOMIPS_ABI_P64 0x2000 /* 64-bit nanoMIPS ABI */ + +/* nanoMIPS processor specific flags, e_flags */ +#define EF_NANOMIPS_LINKRELAX 0x0001 /* Link-time relaxation*/ +#define EF_NANOMIPS_PIC 0x0002 /* Position independant code */ +#define EF_NANOMIPS_32BITMODE 0x0004 /* 32-bit object for 64-bit arch. */ +#define EF_NANOMIPS_PID 0x0008 /* Position independant data */ +#define EF_NANOMIPS_PCREL 0x0010 /* PC-relative mode*/ +#define EF_NANOMIPS_ABI 0xf000 /* nanoMIPS ABI*/ +#define EF_NANOMIPS_MACH 0x00ff /* Machine variant */ +#define EF_NANOMIPS_ARCH 0xf000 /* nanoMIPS architecture */ + /* MIPS machine variant */ #define EF_MIPS_MACH_NONE 0x /* A standard MIPS implementation */ #define EF_MIPS_MACH_3900 0x0081 /* Toshiba R3900 */ @@ -143,6 +161,8 @@ typedef int64_t Elf64_Sxword; #define EM_RISCV243 /* RISC-V */ +#define EM_NANOMIPS 249 /* Wave Computing nanoMIPS */ + /* * This is an interim value that we will use until the committee comes * up with a final number. -- 2.7.4
