Re: [PATCH v1 13/22] test/qtest: Introduce a new aspeed-hace-utils.c to place common testcases
On 3/21/25 10:26, Jamin Lin wrote:
The test cases for the ASPEED HACE model were originally placed in
aspeed_hace-test.c. However, this test file only supports ARM32. To enable
compatibility with all ASPEED SoCs, including the AST2700, which uses the
AArch64 architecture, this update introduces a new source file,
aspeed-hace-utils.c.
All common APIs and test cases have been moved from aspeed_hace-test.c to
aspeed-hace-utils.c to facilitate reuse across different ASPEED SoCs.
As a result, these test cases can now be reused for AST2700 and future ASPEED
SoC testing.
Signed-off-by: Jamin Lin
One comment, the digest reference arrays should have fixed sizes.
Looks ok :
00085fa0 l O .rodata0020
test_result_accum_sha256
00085fc0 l O .rodata0040
test_result_accum_sha512
000860c0 l O .rodata0020
test_result_sg_sha256
000860e0 l O .rodata0040
test_result_sg_sha512
00086130 l O .rodata0010
test_result_md5
00086140 l O .rodata0020
test_result_sha256
00086160 l O .rodata0040
test_result_sha512
but it would be safer add a size when the array is defined.
Anyhow, this is for another patch.
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
tests/qtest/aspeed-hace-utils.h | 71 +
tests/qtest/aspeed-hace-utils.c | 455
tests/qtest/aspeed_hace-test.c | 515 ++--
tests/qtest/meson.build | 1 +
4 files changed, 547 insertions(+), 495 deletions(-)
create mode 100644 tests/qtest/aspeed-hace-utils.h
create mode 100644 tests/qtest/aspeed-hace-utils.c
diff --git a/tests/qtest/aspeed-hace-utils.h b/tests/qtest/aspeed-hace-utils.h
new file mode 100644
index 00..598577c69b
--- /dev/null
+++ b/tests/qtest/aspeed-hace-utils.h
@@ -0,0 +1,71 @@
+/*
+ * QTest testcase for the ASPEED Hash and Crypto Engine
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ * Copyright 2021 IBM Corp.
+ */
+
+#ifndef TESTS_ASPEED_HACE_UTILS_H
+#define TESTS_ASPEED_HACE_UTILS_H
+
+#include "qemu/osdep.h"
+#include "libqtest.h"
+#include "qemu/bitops.h"
+
+#define HACE_CMD 0x10
+#define HACE_SHA_BE_EN BIT(3)
+#define HACE_MD5_LE_EN BIT(2)
+#define HACE_ALGO_MD5 0
+#define HACE_ALGO_SHA1 BIT(5)
+#define HACE_ALGO_SHA224BIT(6)
+#define HACE_ALGO_SHA256(BIT(4) | BIT(6))
+#define HACE_ALGO_SHA512(BIT(5) | BIT(6))
+#define HACE_ALGO_SHA384(BIT(5) | BIT(6) | BIT(10))
+#define HACE_SG_EN BIT(18)
+#define HACE_ACCUM_EN BIT(8)
+
+#define HACE_STS 0x1c
+#define HACE_RSA_ISRBIT(13)
+#define HACE_CRYPTO_ISR BIT(12)
+#define HACE_HASH_ISR BIT(9)
+#define HACE_RSA_BUSY BIT(2)
+#define HACE_CRYPTO_BUSYBIT(1)
+#define HACE_HASH_BUSY BIT(0)
+#define HACE_HASH_SRC0x20
+#define HACE_HASH_DIGEST 0x24
+#define HACE_HASH_KEY_BUFF 0x28
+#define HACE_HASH_DATA_LEN 0x2c
+#define HACE_HASH_CMD0x30
+
+/* Scatter-Gather Hash */
+#define SG_LIST_LEN_LAST BIT(31)
+struct AspeedSgList {
+uint32_t len;
+uint32_t addr;
+} __attribute__ ((__packed__));
+
+struct AspeedMasks {
+uint32_t src;
+uint32_t dest;
+uint32_t len;
+};
+
+void aspeed_test_md5(const char *machine, const uint32_t base,
+ const uint32_t src_addr);
+void aspeed_test_sha256(const char *machine, const uint32_t base,
+const uint32_t src_addr);
+void aspeed_test_sha512(const char *machine, const uint32_t base,
+const uint32_t src_addr);
+void aspeed_test_sha256_sg(const char *machine, const uint32_t base,
+ const uint32_t src_addr);
+void aspeed_test_sha512_sg(const char *machine, const uint32_t base,
+ const uint32_t src_addr);
+void aspeed_test_sha256_accum(const char *machine, const uint32_t base,
+ const uint32_t src_addr);
+void aspeed_test_sha512_accum(const char *machine, const uint32_t base,
+ const uint32_t src_addr);
+void aspeed_test_addresses(const char *machine, const uint32_t base,
+ const struct AspeedMasks *expected);
+
+#endif /* TESTS_ASPEED_HACE_UTILS_H */
+
diff --git a/tests/qtest/aspeed-hace-utils.c b/tests/qtest/aspeed-hace-utils.c
new file mode 100644
index 00..8582847945
--- /dev/null
+++ b/tests/qtest/aspeed-hace-utils.c
@@ -0,0 +1,455 @@
+/*
+ * QTest testcase for the ASPEED Hash and Crypto Engine
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ * Copyright 2021 IBM Corp.
+ */
+
+#include "qemu/osdep.
Re: [PATCH v5 4/4] virtio_net: Add third acceptable configuration for MAC setup.
On Thu, Apr 3, 2025 at 12:36 AM Michael S. Tsirkin wrote:
>
> On Wed, Mar 26, 2025 at 09:19:33PM +0800, Cindy Lu wrote:
> > For VDPA devices, Allow configurations where both the hardware MAC address
> > and QEMU command line MAC address are zero.
> >
> > Signed-off-by: Cindy Lu
> > ---
> > hw/net/virtio-net.c | 13 +
> > 1 file changed, 13 insertions(+)
> >
> > diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c
> > index 1fd0403d5d..d1f44850d5 100644
> > --- a/hw/net/virtio-net.c
> > +++ b/hw/net/virtio-net.c
> > @@ -3782,6 +3782,19 @@ static bool virtio_net_check_vdpa_mac(NetClientState
> > *nc, VirtIONet *n,
> > return true;
> > }
> > }
> > +/*
> > + * 3.The hardware MAC address is 0,
> > + * and the MAC address in the QEMU command line is also 0.
> > + * In this situation, qemu will generate a random mac address
> > + * QEMU will try to use CVQ/set_config to set this address to
> > + * device
>
> same comments. end sentences with a period.
>
sure. will fix this
Thanks
cindy
> > + */
> > +if ((memcmp(&hwcfg.mac, &zero, sizeof(MACAddr)) == 0) &&
> > +(memcmp(cmdline_mac, &zero, sizeof(MACAddr)) == 0)) {
> > +memcpy(&n->mac[0], &n->nic_conf.macaddr, sizeof(n->mac));
> > +
> > +return true;
> > +}
> >
> > error_setg(errp,
> > "vDPA device's mac %02x:%02x:%02x:%02x:%02x:%02x"
> > --
> > 2.45.0
>
[PATCH-for-10.1 12/43] target/loongarch: Restrict SoftMMU mmu_index() to TCG
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/loongarch/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index ea1665e2705..cb96b17911a 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -868,6 +868,7 @@ static const TCGCPUOps loongarch_tcg_ops = {
.translate_code = loongarch_translate_code,
.synchronize_from_tb = loongarch_cpu_synchronize_from_tb,
.restore_state_to_opc = loongarch_restore_state_to_opc,
+.mmu_index = loongarch_cpu_mmu_index,
#ifndef CONFIG_USER_ONLY
.tlb_fill = loongarch_cpu_tlb_fill,
@@ -919,7 +920,6 @@ static void loongarch_cpu_class_init(ObjectClass *c, void
*data)
&lacc->parent_phases);
cc->class_by_name = loongarch_cpu_class_by_name;
-cc->mmu_index = loongarch_cpu_mmu_index;
cc->dump_state = loongarch_cpu_dump_state;
cc->set_pc = loongarch_cpu_set_pc;
cc->get_pc = loongarch_cpu_get_pc;
--
2.47.1
[PATCH-for-10.1 12/13] hw/arm/realview: Replace arm_feature() -> arm_cpu_has_feature()
By using arm_cpu_has_feature() instead of arm_feature()
we don't need to include "cpu.h" anymore.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/realview.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/hw/arm/realview.c b/hw/arm/realview.c
index f81d084eb80..48cfe05add0 100644
--- a/hw/arm/realview.c
+++ b/hw/arm/realview.c
@@ -9,7 +9,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "cpu.h"
#include "hw/sysbus.h"
#include "hw/arm/boot.h"
#include "hw/arm/primecell.h"
@@ -31,6 +30,7 @@
#include "hw/sd/sd.h"
#include "audio/audio.h"
#include "target/arm/cpu-qom.h"
+#include "target/arm/cpu_has_feature.h"
#define SMP_BOOT_ADDR 0xe000
#define SMP_BOOTREG_ADDR 0x1030
@@ -77,7 +77,6 @@ static void realview_init(MachineState *machine,
enum realview_board_type board_type)
{
ARMCPU *cpu = NULL;
-CPUARMState *env;
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *ram_lo;
MemoryRegion *ram_hi = g_new(MemoryRegion, 1);
@@ -138,16 +137,15 @@ static void realview_init(MachineState *machine,
cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpuobj), ARM_CPU_IRQ);
}
cpu = ARM_CPU(first_cpu);
-env = &cpu->env;
-if (arm_feature(env, ARM_FEATURE_V7)) {
+if (arm_cpu_has_feature(cpu, ARM_FEATURE_V7)) {
if (is_mpcore) {
proc_id = 0x0c00;
} else {
proc_id = 0x0e00;
}
-} else if (arm_feature(env, ARM_FEATURE_V6K)) {
+} else if (arm_cpu_has_feature(cpu, ARM_FEATURE_V6K)) {
proc_id = 0x0600;
-} else if (arm_feature(env, ARM_FEATURE_V6)) {
+} else if (arm_cpu_has_feature(cpu, ARM_FEATURE_V6)) {
proc_id = 0x0400;
} else {
proc_id = 0x0200;
--
2.47.1
Re: [PATCH 1/3] ipmi/bmc-sim: implement watchdog dont log flag
On Mon, Mar 31, 2025 at 10:57:22PM +1000, Nicholas Piggin wrote:
> If the dont-log flag is set in the 'timer use' field for the
> 'set watchdog' command, a watchdog timeout will not get logged as
> a timer use expiration.
>
> Signed-off-by: Nicholas Piggin
> ---
> hw/ipmi/ipmi_bmc_sim.c | 7 ++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/hw/ipmi/ipmi_bmc_sim.c b/hw/ipmi/ipmi_bmc_sim.c
> index 6157ac71201..32161044c0b 100644
> --- a/hw/ipmi/ipmi_bmc_sim.c
> +++ b/hw/ipmi/ipmi_bmc_sim.c
> @@ -733,7 +733,12 @@ static void ipmi_sim_handle_timeout(IPMIBmcSim *ibs)
>
> do_full_expiry:
> ibs->watchdog_running = 0; /* Stop the watchdog on a timeout */
> -ibs->watchdog_expired |= (1 << IPMI_BMC_WATCHDOG_GET_USE(ibs));
> +
> +/* Log the expiry if the don't log bit is clear */
> +if (!IPMI_BMC_WATCHDOG_GET_DONT_LOG(ibs)) {
> +ibs->watchdog_expired |= (1 << IPMI_BMC_WATCHDOG_GET_USE(ibs));
> +}
> +
Are you sure this is correct? The spec doesn't say what this means, but
I would assume this means "Don't add a system log" not "Don't set the
expiry happened bit".
> switch (IPMI_BMC_WATCHDOG_GET_ACTION(ibs)) {
> case IPMI_BMC_WATCHDOG_ACTION_NONE:
> sensor_set_discrete_bit(ibs, IPMI_WATCHDOG_SENSOR, 0, 1,
> --
> 2.47.1
>
[PATCH-for-10.1 08/13] hw/arm: Include missing 'target/arm/gtimer.h' header
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/aspeed_ast27x0.c| 1 +
hw/arm/bcm2838.c | 1 +
hw/arm/exynos4210.c| 1 +
hw/arm/fsl-imx8mp.c| 1 +
hw/arm/mps3r.c | 1 +
hw/arm/npcm8xx.c | 1 +
hw/vmapple/vmapple.c | 1 +
target/arm/tcg/op_helper.c | 1 +
8 files changed, 8 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 37bfeef304d..5c2481225dd 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -22,6 +22,7 @@
#include "hw/intc/arm_gicv3.h"
#include "qobject/qlist.h"
#include "qemu/log.h"
+#include "target/arm/gtimer.h"
#include "target/arm/multiprocessing.h"
static const hwaddr aspeed_soc_ast2700_memmap[] = {
diff --git a/hw/arm/bcm2838.c b/hw/arm/bcm2838.c
index ddb7c5f757a..38d9b785a75 100644
--- a/hw/arm/bcm2838.c
+++ b/hw/arm/bcm2838.c
@@ -12,6 +12,7 @@
#include "hw/arm/raspi_platform.h"
#include "hw/sysbus.h"
#include "hw/arm/bcm2838.h"
+#include "target/arm/gtimer.h"
#include "trace.h"
#define GIC400_MAINTENANCE_IRQ 9
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index 01e6e2fb052..ca40df3db75 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -36,6 +36,7 @@
#include "hw/sd/sdhci.h"
#include "hw/usb/hcd-ehci.h"
#include "target/arm/cpu-qom.h"
+#include "target/arm/gtimer.h"
#include "target/arm/multiprocessing.h"
#define EXYNOS4210_CHIPID_ADDR 0x1000
diff --git a/hw/arm/fsl-imx8mp.c b/hw/arm/fsl-imx8mp.c
index 2cf5eeaf313..180feca9d80 100644
--- a/hw/arm/fsl-imx8mp.c
+++ b/hw/arm/fsl-imx8mp.c
@@ -17,6 +17,7 @@
#include "hw/boards.h"
#include "system/system.h"
#include "target/arm/cpu-qom.h"
+#include "target/arm/gtimer.h"
#include "qapi/error.h"
#include "qobject/qlist.h"
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
index 604f6845fde..37c0de28a92 100644
--- a/hw/arm/mps3r.c
+++ b/hw/arm/mps3r.c
@@ -47,6 +47,7 @@
#include "hw/ssi/pl022.h"
#include "hw/timer/cmsdk-apb-dualtimer.h"
#include "hw/watchdog/cmsdk-apb-watchdog.h"
+#include "target/arm/gtimer.h"
/* Define the layout of RAM and ROM in a board */
typedef struct RAMInfo {
diff --git a/hw/arm/npcm8xx.c b/hw/arm/npcm8xx.c
index 3987e55355b..2f11bc53a86 100644
--- a/hw/arm/npcm8xx.c
+++ b/hw/arm/npcm8xx.c
@@ -29,6 +29,7 @@
#include "qapi/error.h"
#include "qemu/units.h"
#include "system/system.h"
+#include "target/arm/gtimer.h"
#include "target/arm/multiprocessing.h"
/*
diff --git a/hw/vmapple/vmapple.c b/hw/vmapple/vmapple.c
index 9bb5b0553a2..25652b16f0c 100644
--- a/hw/vmapple/vmapple.c
+++ b/hw/vmapple/vmapple.c
@@ -51,6 +51,7 @@
#include "system/reset.h"
#include "system/runstate.h"
#include "system/system.h"
+#include "target/arm/gtimer.h"
#include "target/arm/multiprocessing.h"
struct VMAppleMachineState {
diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c
index 38d49cbb9d8..005f84082af 100644
--- a/target/arm/tcg/op_helper.c
+++ b/target/arm/tcg/op_helper.c
@@ -25,6 +25,7 @@
#include "cpu-features.h"
#include "exec/exec-all.h"
#include "accel/tcg/cpu-ldst.h"
+#include "target/arm/gtimer.h"
#include "cpregs.h"
#define SIGNBIT (uint32_t)0x8000
--
2.47.1
[PATCH-for-10.1 06/13] target/arm: Restrict inclusion of 'multiprocessing.h'
Only cpu.c requires "multiprocessing.h" definitions so far.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/cpu.h | 1 -
target/arm/cpu.c | 1 +
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 88ed06987f3..768e784c3e9 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -30,7 +30,6 @@
#include "exec/gdbstub.h"
#include "exec/page-protection.h"
#include "qapi/qapi-types-common.h"
-#include "target/arm/multiprocessing.h"
#include "target/arm/gtimer.h"
#define EXCP_UDEF1 /* undefined instruction */
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index b1aa482c726..6f62745d7f6 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -53,6 +53,7 @@
#include "qemu/target_info-qom.h"
#include "target/arm/cpu-qom.h"
#include "target/arm/gtimer.h"
+#include "target/arm/multiprocessing.h"
static void arm_cpu_set_pc(CPUState *cs, vaddr value)
{
--
2.47.1
[PATCH-for-10.1 11/13] target/arm: Add arm_cpu_has_feature() helper
arm_cpu_has_feature() is equivalent of arm_feature(), however
while the latter uses CPUARMState so is target-specific, the
former doesn't and can be called by target-agnostic code in hw/.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/cpu_has_feature.h | 2 ++
target/arm/cpu.c | 7 +++
2 files changed, 9 insertions(+)
diff --git a/target/arm/cpu_has_feature.h b/target/arm/cpu_has_feature.h
index 2adfccd9208..352f9d75bed 100644
--- a/target/arm/cpu_has_feature.h
+++ b/target/arm/cpu_has_feature.h
@@ -62,4 +62,6 @@ typedef enum arm_features {
ARM_FEATURE_BACKCOMPAT_CNTFRQ, /* 62.5MHz timer default */
} ArmCpuFeature;
+bool arm_cpu_has_feature(ARMCPU *cpu, ArmCpuFeature feature);
+
#endif
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 6f62745d7f6..66a58916fcc 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -55,6 +55,13 @@
#include "target/arm/gtimer.h"
#include "target/arm/multiprocessing.h"
+bool arm_cpu_has_feature(ARMCPU *cpu, ArmCpuFeature feature)
+{
+CPUARMState *env = &cpu->env;
+
+return arm_feature(env, feature);
+}
+
static void arm_cpu_set_pc(CPUState *cs, vaddr value)
{
ARMCPU *cpu = ARM_CPU(cs);
--
2.47.1
[PATCH-for-10.1 02/13] target/arm/qmp: Include missing 'cpu.h' header
arm-qmp-cmds.c uses ARM_MAX_VQ, which is defined in "cpu.h".
Include the latter to avoid when refactoring unrelated headers:
target/arm/arm-qmp-cmds.c:83:19: error: use of undeclared identifier
'ARM_MAX_VQ'
83 | QEMU_BUILD_BUG_ON(ARM_MAX_VQ > 16);
| ^
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/arm-qmp-cmds.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/arm-qmp-cmds.c b/target/arm/arm-qmp-cmds.c
index 883c0a0e8cc..d654be2a619 100644
--- a/target/arm/arm-qmp-cmds.c
+++ b/target/arm/arm-qmp-cmds.c
@@ -30,6 +30,7 @@
#include "qapi/qapi-commands-misc-target.h"
#include "qobject/qdict.h"
#include "qom/qom-qobject.h"
+#include "cpu.h"
static GICCapability *gic_cap_new(int version)
{
--
2.47.1
[PATCH-for-10.1 09/13] target/arm: Extract PSCI definitions to 'psci.h'
Extract PSCI definitions (which are not target specific)
to the new "target/arm/psci.h", so code from hw/arm/ can
use them without having to include the target specific
"cpu.h" header.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/arm/boot.h | 3 ++-
target/arm/cpu.h | 6 --
target/arm/psci.h | 18 ++
hw/arm/bananapi_m2u.c | 1 +
hw/arm/boot.c | 1 +
hw/arm/highbank.c | 1 +
hw/arm/imx8mp-evk.c| 1 +
hw/arm/mcimx6ul-evk.c | 1 +
hw/arm/mcimx7d-sabre.c | 1 +
hw/arm/orangepi.c | 1 +
hw/arm/sbsa-ref.c | 1 +
hw/arm/virt-acpi-build.c | 1 +
hw/arm/virt.c | 1 +
hw/arm/xlnx-versal-virt.c | 1 +
hw/arm/xlnx-zcu102.c | 1 +
hw/vmapple/vmapple.c | 1 +
target/arm/helper.c| 1 +
target/arm/hvf/hvf.c | 1 +
target/arm/tcg/op_helper.c | 1 +
target/arm/tcg/psci.c | 1 +
20 files changed, 37 insertions(+), 7 deletions(-)
create mode 100644 target/arm/psci.h
diff --git a/include/hw/arm/boot.h b/include/hw/arm/boot.h
index b12bf61ca81..648fdb88862 100644
--- a/include/hw/arm/boot.h
+++ b/include/hw/arm/boot.h
@@ -12,6 +12,7 @@
#define HW_ARM_BOOT_H
#include "target/arm/cpu-qom.h"
+//#include "target/arm/psci.h"
#include "qemu/notify.h"
typedef enum {
@@ -100,7 +101,7 @@ struct arm_boot_info {
* as the conduit specifies calls should go to (eg guest firmware booted
* to EL3) then PSCI will not be enabled.
*/
-int psci_conduit;
+int psci_conduit;//
/* Used internally by arm_boot.c */
int is_linux;
hwaddr initrd_start;
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 45a9551535e..e78a1668bba 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3104,12 +3104,6 @@ static inline bool bswap_code(bool sctlr_b)
void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc,
uint64_t *cs_base, uint32_t *flags);
-enum {
-QEMU_PSCI_CONDUIT_DISABLED = 0,
-QEMU_PSCI_CONDUIT_SMC = 1,
-QEMU_PSCI_CONDUIT_HVC = 2,
-};
-
#ifndef CONFIG_USER_ONLY
/* Return the address space index to use for a memory access */
static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
diff --git a/target/arm/psci.h b/target/arm/psci.h
new file mode 100644
index 000..8b868dfbb91
--- /dev/null
+++ b/target/arm/psci.h
@@ -0,0 +1,18 @@
+/*
+ * ARM Power State Coordination Interface (PSCI) definitions
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+
+#ifndef TARGET_ARM_PSCI_H
+#define TARGET_ARM_PSCI_H
+
+enum {
+QEMU_PSCI_CONDUIT_DISABLED = 0,
+QEMU_PSCI_CONDUIT_SMC = 1,
+QEMU_PSCI_CONDUIT_HVC = 2,
+};
+
+#endif
diff --git a/hw/arm/bananapi_m2u.c b/hw/arm/bananapi_m2u.c
index b750a575f72..61e01a38099 100644
--- a/hw/arm/bananapi_m2u.c
+++ b/hw/arm/bananapi_m2u.c
@@ -27,6 +27,7 @@
#include "hw/qdev-properties.h"
#include "hw/arm/allwinner-r40.h"
#include "hw/arm/boot.h"
+#include "target/arm/psci.h"
static struct arm_boot_info bpim2u_binfo;
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index 79afb51b8a5..b81a850819b 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -29,6 +29,7 @@
#include "qemu/config-file.h"
#include "qemu/option.h"
#include "qemu/units.h"
+#include "target/arm/psci.h"
/* Kernel boot protocol is specified in the kernel docs
* Documentation/arm/Booting and Documentation/arm64/booting.txt
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index 0caa08631ad..16fb2508d30 100644
--- a/hw/arm/highbank.c
+++ b/hw/arm/highbank.c
@@ -36,6 +36,7 @@
#include "qemu/log.h"
#include "qom/object.h"
#include "target/arm/cpu-qom.h"
+#include "target/arm/psci.h"
#define SMP_BOOT_ADDR 0x100
#define SMP_BOOT_REG0x40
diff --git a/hw/arm/imx8mp-evk.c b/hw/arm/imx8mp-evk.c
index 6e64ec4ea54..c8a99b2c49e 100644
--- a/hw/arm/imx8mp-evk.c
+++ b/hw/arm/imx8mp-evk.c
@@ -15,6 +15,7 @@
#include "system/qtest.h"
#include "qemu/error-report.h"
#include "qapi/error.h"
+#include "target/arm/psci.h"
static void imx8mp_evk_init(MachineState *machine)
{
diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c
index 86982cb0772..be5e50abf17 100644
--- a/hw/arm/mcimx6ul-evk.c
+++ b/hw/arm/mcimx6ul-evk.c
@@ -18,6 +18,7 @@
#include "hw/qdev-properties.h"
#include "qemu/error-report.h"
#include "system/qtest.h"
+#include "target/arm/psci.h"
static void mcimx6ul_evk_init(MachineState *machine)
{
diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c
index 33119610113..e0f25b92594 100644
--- a/hw/arm/mcimx7d-sabre.c
+++ b/hw/arm/mcimx7d-sabre.c
@@ -20,6 +20,7 @@
#include "hw/qdev-properties.h"
#include "qemu/error-report.h"
#include "system/qtest.h"
+#include "target/arm/psci.h"
static void mcimx7d_sabre_init(MachineState *machine)
{
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
index e0956880d11..99037a09a36 100644
--- a/hw/arm/orangepi.c
+++ b/hw/arm/or
[PATCH-for-10.1 03/13] target/arm/kvm: Include missing 'cpu-qom.h' header
ARMCPU typedef is declared in "cpu-qom.h". Include it in order to avoid when refactoring unrelated headers: target/arm/kvm_arm.h:54:29: error: unknown type name 'ARMCPU' 54 | bool write_list_to_kvmstate(ARMCPU *cpu, int level); | ^ Signed-off-by: Philippe Mathieu-Daudé --- target/arm/kvm_arm.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 05c3de8cd46..2db2f060e6a 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -12,6 +12,7 @@ #define QEMU_KVM_ARM_H #include "system/kvm.h" +#include "target/arm/cpu-qom.h" #define KVM_ARM_VGIC_V2 (1 << 0) #define KVM_ARM_VGIC_V3 (1 << 1) -- 2.47.1
[PATCH-for-10.1 10/13] target/arm: Extract feature definitions to 'cpu_has_feature.h' header
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/cpu.h | 54 +-
target/arm/cpu_has_feature.h | 65
2 files changed, 66 insertions(+), 53 deletions(-)
create mode 100644 target/arm/cpu_has_feature.h
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index e78a1668bba..a76874badc3 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -30,6 +30,7 @@
#include "exec/gdbstub.h"
#include "exec/page-protection.h"
#include "qapi/qapi-types-common.h"
+#include "target/arm/cpu_has_feature.h"
#include "target/arm/gtimer.h"
#define EXCP_UDEF1 /* undefined instruction */
@@ -2379,59 +2380,6 @@ FIELD(MFAR, NS, 63, 1)
QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <=
R_V7M_CSSELR_INDEX_MASK);
-/* If adding a feature bit which corresponds to a Linux ELF
- * HWCAP bit, remember to update the feature-bit-to-hwcap
- * mapping in linux-user/elfload.c:get_elf_hwcap().
- */
-enum arm_features {
-ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
-ARM_FEATURE_XSCALE, /* Intel XScale extensions. */
-ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */
-ARM_FEATURE_V6,
-ARM_FEATURE_V6K,
-ARM_FEATURE_V7,
-ARM_FEATURE_THUMB2,
-ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */
-ARM_FEATURE_NEON,
-ARM_FEATURE_M, /* Microcontroller profile. */
-ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */
-ARM_FEATURE_THUMB2EE,
-ARM_FEATURE_V7MP,/* v7 Multiprocessing Extensions */
-ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */
-ARM_FEATURE_V4T,
-ARM_FEATURE_V5,
-ARM_FEATURE_STRONGARM,
-ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
-ARM_FEATURE_GENERIC_TIMER,
-ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
-ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */
-ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */
-ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
-ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
-ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
-ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
-ARM_FEATURE_V8,
-ARM_FEATURE_AARCH64, /* supports 64 bit mode */
-ARM_FEATURE_CBAR, /* has cp15 CBAR */
-ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */
-ARM_FEATURE_EL2, /* has EL2 Virtualization support */
-ARM_FEATURE_EL3, /* has EL3 Secure monitor support */
-ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */
-ARM_FEATURE_PMU, /* has PMU support */
-ARM_FEATURE_VBAR, /* has cp15 VBAR */
-ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
-ARM_FEATURE_M_MAIN, /* M profile Main Extension */
-ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */
-/*
- * ARM_FEATURE_BACKCOMPAT_CNTFRQ makes the CPU default cntfrq be 62.5MHz
- * if the board doesn't set a value, instead of 1GHz. It is for backwards
- * compatibility and used only with CPU definitions that were already
- * in QEMU before we changed the default. It should not be set on any
- * CPU types added in future.
- */
-ARM_FEATURE_BACKCOMPAT_CNTFRQ, /* 62.5MHz timer default */
-};
-
static inline int arm_feature(CPUARMState *env, int feature)
{
return (env->features & (1ULL << feature)) != 0;
diff --git a/target/arm/cpu_has_feature.h b/target/arm/cpu_has_feature.h
new file mode 100644
index 000..2adfccd9208
--- /dev/null
+++ b/target/arm/cpu_has_feature.h
@@ -0,0 +1,65 @@
+/*
+ * Helper to check ARM CPU has features
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+#ifndef TARGET_ARM_CPU_HAS_FEATURE_H
+#define TARGET_ARM_CPU_HAS_FEATURE_H
+
+/*
+ * If adding a feature bit which corresponds to a Linux ELF
+ * HWCAP bit, remember to update the feature-bit-to-hwcap
+ * mapping in linux-user/elfload.c:get_elf_hwcap().
+ */
+typedef enum arm_features {
+ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
+ARM_FEATURE_XSCALE, /* Intel XScale extensions. */
+ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */
+ARM_FEATURE_V6,
+ARM_FEATURE_V6K,
+ARM_FEATURE_V7,
+ARM_FEATURE_THUMB2,
+ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */
+ARM_FEATURE_NEON,
+ARM_FEATURE_M, /* Microcontroller profile. */
+ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */
+ARM_FEATURE_THUMB2EE,
+ARM_FEATURE_V7MP,/* v7 Multiprocessing Extensions */
+ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */
+ARM_FEATURE_V4T,
+ARM_FEATURE_V5,
+ARM_FEATURE_STRONGARM,
+ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
+ARM_FEATURE_GENERIC_TIMER,
+ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
+ARM_FEATURE_DUMMY_C15_REG
Re: [PATCH 1/3] target/mips: Revert TARGET_PAGE_BITS_VARY
On Thu, Apr 3, 2025 at 2:11 AM Richard Henderson wrote: > > On 4/1/25 20:04, Huacai Chen wrote: > > Hi, Richard, > > > > On Tue, Apr 1, 2025 at 9:39 PM Richard Henderson > > wrote: > >> > >> On 3/31/25 20:15, Huacai Chen wrote: > # define TARGET_VIRT_ADDR_SPACE_BITS 32 > #endif > #endif > -#ifdef CONFIG_USER_ONLY > #define TARGET_PAGE_BITS 12 > -#else > -#define TARGET_PAGE_BITS_VARY > -#define TARGET_PAGE_BITS_MIN 12 > -#endif > >>> I'm a bit confused about TARGET_PAGE_BITS and other macros. > >>> > >>> In my opinion, if we define TARGET_PAGE_BITS as 12, that means we only > >>> support 4K pages. And if we define TARGET_PAGE_BITS_VARY and > >>> TARGET_PAGE_BITS_MIN as 12, that means we support the minimum page as > >>> 4K, but we also support larger pages. > >>> > >>> Am I wrong? > >> Yes. > >> > >> TARGET_PAGE_BITS is a minimum value that is used by the memory subsystem > >> for managing ram > >> and i/o. If variable, via TARGET_PAGE_BITS_VARY, this is set very early > >> in qemu startup > >> and cannot be changed. > >> > >> The page size for the mips cpu, like many others, may be changed at > >> runtime. The page > >> size used at that point is reported to softmmu during tlb_fill. > >> > >> The value of TARGET_PAGE_BITS must be the minimum supported by the cpu. > >> > >> For Arm, the minimum for armv6 was 1k, then armv7 dropped support for tiny > >> pages so the > >> minimum is 4k. At runtime, armv8 supports page sizes of 4k, 16k, and 64k. > >> > >> For MIPS, ignoring those cpus which support 1k pages, the minimum is 4k. > > If all types of cpus of the target arch has the same minimum supported > > page size, we only need to define TARGET_PAGE_BITS; otherwise we need > > to define TARGET_PAGE_BITS_VARY, and TARGET_PAGE_BITS_MIN means the > > minimum supported page size of the smallest supported page's cpu type. > > Here we remove TARGET_PAGE_BITS_VARY because we just ignore the 1K > > pages. > > > > Am I right now? > > Yes. OK, then it is fine to remove the TARGET_PAGE_BITS_VARY and TARGET_PAGE_BITS_MIN definition. But Loongson still prefers 16K pages (4K pages cause cache alias on Loongson), so I want to keep mc->minimum_page_bits = 14. Huacai > > > r~
Re: [PATCH v8 01/28] vfio/container: pass MemoryRegion to DMA operations
On 2/19/25 15:48, John Levon wrote:
From: Jagannathan Raman
Pass through the MemoryRegion to DMA operation handlers of vfio
containers. The vfio-user container will need this later.
Originally-by: John Johnson
Signed-off-by: Jagannathan Raman
Signed-off-by: Elena Ufimtseva
Signed-off-by: John Levon
FYI, in case you didn't see the discussion here :
https://lore.kernel.org/qemu-devel/1739542467-226739-29-git-send-email-steven.sist...@oracle.com/
Thanks,
C.
---
hw/vfio/common.c | 17 ++---
hw/vfio/container-base.c | 4 ++--
hw/vfio/container.c | 3 ++-
hw/vfio/iommufd.c | 3 ++-
hw/virtio/vhost-vdpa.c| 2 +-
include/exec/memory.h | 4 +++-
include/hw/vfio/vfio-container-base.h | 4 ++--
system/memory.c | 7 ++-
8 files changed, 28 insertions(+), 16 deletions(-)
diff --git a/hw/vfio/common.c b/hw/vfio/common.c
index abbdc56b6d..8d3d425c63 100644
--- a/hw/vfio/common.c
+++ b/hw/vfio/common.c
@@ -248,12 +248,12 @@ static bool
vfio_listener_skipped_section(MemoryRegionSection *section)
/* Called with rcu_read_lock held. */
static bool vfio_get_xlat_addr(IOMMUTLBEntry *iotlb, void **vaddr,
ram_addr_t *ram_addr, bool *read_only,
- Error **errp)
+ MemoryRegion **mrp, Error **errp)
{
bool ret, mr_has_discard_manager;
ret = memory_get_xlat_addr(iotlb, vaddr, ram_addr, read_only,
- &mr_has_discard_manager, errp);
+ &mr_has_discard_manager, mrp, errp);
if (ret && mr_has_discard_manager) {
/*
* Malicious VMs might trigger discarding of IOMMU-mapped memory. The
@@ -281,6 +281,7 @@ static void vfio_iommu_map_notify(IOMMUNotifier *n,
IOMMUTLBEntry *iotlb)
VFIOGuestIOMMU *giommu = container_of(n, VFIOGuestIOMMU, n);
VFIOContainerBase *bcontainer = giommu->bcontainer;
hwaddr iova = iotlb->iova + giommu->iommu_offset;
+MemoryRegion *mrp;
void *vaddr;
int ret;
Error *local_err = NULL;
@@ -300,7 +301,8 @@ static void vfio_iommu_map_notify(IOMMUNotifier *n,
IOMMUTLBEntry *iotlb)
if ((iotlb->perm & IOMMU_RW) != IOMMU_NONE) {
bool read_only;
-if (!vfio_get_xlat_addr(iotlb, &vaddr, NULL, &read_only, &local_err)) {
+if (!vfio_get_xlat_addr(iotlb, &vaddr, NULL, &read_only, &mrp,
+&local_err)) {
error_report_err(local_err);
goto out;
}
@@ -313,7 +315,7 @@ static void vfio_iommu_map_notify(IOMMUNotifier *n,
IOMMUTLBEntry *iotlb)
*/
ret = vfio_container_dma_map(bcontainer, iova,
iotlb->addr_mask + 1, vaddr,
- read_only);
+ read_only, mrp);
if (ret) {
error_report("vfio_container_dma_map(%p, 0x%"HWADDR_PRIx", "
"0x%"HWADDR_PRIx", %p) = %d (%s)",
@@ -378,7 +380,7 @@ static int
vfio_ram_discard_notify_populate(RamDiscardListener *rdl,
vaddr = memory_region_get_ram_ptr(section->mr) + start;
ret = vfio_container_dma_map(bcontainer, iova, next - start,
- vaddr, section->readonly);
+ vaddr, section->readonly, section->mr);
if (ret) {
/* Rollback */
vfio_ram_discard_notify_discard(rdl, section);
@@ -675,7 +677,7 @@ static void vfio_listener_region_add(MemoryListener
*listener,
}
ret = vfio_container_dma_map(bcontainer, iova, int128_get64(llsize),
- vaddr, section->readonly);
+ vaddr, section->readonly, section->mr);
if (ret) {
error_setg(&err, "vfio_container_dma_map(%p, 0x%"HWADDR_PRIx", "
"0x%"HWADDR_PRIx", %p) = %d (%s)",
@@ -1232,7 +1234,8 @@ static void vfio_iommu_map_dirty_notify(IOMMUNotifier *n,
IOMMUTLBEntry *iotlb)
}
rcu_read_lock();
-if (!vfio_get_xlat_addr(iotlb, NULL, &translated_addr, NULL, &local_err)) {
+if (!vfio_get_xlat_addr(iotlb, NULL, &translated_addr, NULL, NULL,
+&local_err)) {
error_report_err(local_err);
goto out_unlock;
}
diff --git a/hw/vfio/container-base.c b/hw/vfio/container-base.c
index 749a3fd29d..5e0c9700d9 100644
--- a/hw/vfio/container-base.c
+++ b/hw/vfio/container-base.c
@@ -17,12 +17,12 @@
int vfio_container_dma_map(VFIOContainerBase *bcontainer,
hwaddr iova, ram_addr_t size,
- void *vaddr, bool readonly)
+ void *vaddr, bool readonly, MemoryRegion *mrp)
{
VFIOIOMMUClass *vioc = VFIO_IOMM
Re: [RFC PATCH-for-10.1 v2 0/7] tcg: Move TCG_GUEST_DEFAULT_MO -> TCGCPUOps::guest_default_memory_order
On 2/4/25 22:27, Philippe Mathieu-Daudé wrote:
On 2/4/25 22:00, Richard Henderson wrote:
On 3/21/25 11:15, Philippe Mathieu-Daudé wrote:
Since v1:
- Do not use tcg_ctx in tcg_req_mo (rth)
Hi,
In this series we replace the TCG_GUEST_DEFAULT_MO definition
from "cpu-param.h" by a 'guest_default_memory_order' field in
TCGCPUOps.
Since tcg_req_mo() now accesses tcg_ctx, this impact the
cpu_req_mo() calls in accel/tcg/{cputlb,user-exec}.c.
The long term goal is to be able to use targets with distinct
guest memory order restrictions.
Philippe Mathieu-Daudé (7):
tcg: Always define TCG_GUEST_DEFAULT_MO
tcg: Simplify tcg_req_mo() macro
tcg: Define guest_default_memory_order in TCGCPUOps
tcg: Remove use of TCG_GUEST_DEFAULT_MO in tb_gen_code()
tcg: Propagate CPUState argument to cpu_req_mo()
tcg: Have tcg_req_mo() useTCGCPUOps::guest_default_memory_order
tcg: Remove the TCG_GUEST_DEFAULT_MO definition globally
Queued to tcg-next, thanks.
Thanks but I neglected to test on linux-user and found a pair of issues,
so I'll respin with them addressed.
Oops, wrong series (I meant the one about TCGCPUOps::mttcg_supported).
This one is OK.
[PATCH] ui/curses: Fix infinite loop on windows
>From a42046272f0544dd18ed58661e53ea17d1584c2c Mon Sep 17 00:00:00 2001
From: William Hu
Date: Wed, 2 Apr 2025 12:00:00 -0400
Subject: [PATCH] ui/curses: Fix infinite loop on windows
Replace -1 comparisons for wint_t with WEOF to fix infinite loop caused by a
65535 == -1 comparison.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2905
Signed-off-by: William Hu
---
ui/curses.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/ui/curses.c b/ui/curses.c
index a39aee8762..3f5c5adf78 100644
--- a/ui/curses.c
+++ b/ui/curses.c
@@ -265,7 +265,12 @@ static int curses2foo(const int _curses2foo[], const int
_curseskey2foo[],
static void curses_refresh(DisplayChangeListener *dcl)
{
-int chr, keysym, keycode, keycode_alt;
+/*
+ * DO NOT MAKE chr AN INT:
+ * Causes silent conversion errors on Windows where wint_t is unsigned
short.
+ */
+wint_t chr = 0;
+int keysym, keycode, keycode_alt;
enum maybe_keycode maybe_keycode = CURSES_KEYCODE;
curses_winch_check();
@@ -284,8 +289,9 @@ static void curses_refresh(DisplayChangeListener *dcl)
/* while there are any pending key strokes to process */
chr = console_getch(&maybe_keycode);
-if (chr == -1)
+if (chr == WEOF) {
break;
+}
#ifdef KEY_RESIZE
/* this shouldn't occur when we use a custom SIGWINCH handler */
--
2.47.0
[PATCH v2 1/2] target/hexagon: Replace `prepare` script with meson target
The purpose of the prepare script is to invoke `cpp` to preprocess input
to idef-parser by expanding a few select macros. On macOS `cpp`
expands into `clang ... -traditional-cpp` which breaks macro
concatenation. Replace `cpp` with `${compiler} -E`
and replace the script with a meson custom_target.
Signed-off-by: Anton Johansson
---
target/hexagon/idef-parser/prepare | 24
target/hexagon/meson.build | 3 ++-
2 files changed, 2 insertions(+), 25 deletions(-)
delete mode 100755 target/hexagon/idef-parser/prepare
diff --git a/target/hexagon/idef-parser/prepare
b/target/hexagon/idef-parser/prepare
deleted file mode 100755
index cb3622d4f8..00
--- a/target/hexagon/idef-parser/prepare
+++ /dev/null
@@ -1,24 +0,0 @@
-#!/usr/bin/env bash
-
-#
-# Copyright(c) 2019-2021 rev.ng Labs Srl. All Rights Reserved.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, see
Re: [PATCH v8 18/55] i386/tdx: Parse TDVF metadata for TDX VM
On Tue, Apr 01, 2025 at 09:01:28AM -0400, Xiaoyao Li wrote: > After TDVF is loaded to bios MemoryRegion, it needs parse TDVF metadata. > > Signed-off-by: Xiaoyao Li > Acked-by: Gerd Hoffmann > --- > hw/i386/pc_sysfw.c | 7 +++ > target/i386/kvm/tdx-stub.c | 5 + > target/i386/kvm/tdx.c | 5 + > target/i386/kvm/tdx.h | 3 +++ > 4 files changed, 20 insertions(+) Reviewed-by: Daniel P. Berrangé With regards, Daniel -- |: https://berrange.com -o-https://www.flickr.com/photos/dberrange :| |: https://libvirt.org -o-https://fstop138.berrange.com :| |: https://entangle-photo.org-o-https://www.instagram.com/dberrange :|
Re: [PATCH v9 4/7] qapi: add blockdev-replace command
On 18.10.24 16:59, Kevin Wolf wrote: If we want to get rid of the union, I think the best course of action would unifying the namespaces (so that nodes, exports and devices can't share the same ID) and then we could just accept a universal 'id' along with 'child'. Maybe we can go this way even without explicit restriction (which should some how go through deprecation period, etc), but simply look for the id among nodes, devices and exports and if found more than one parent - fail. And we document, that id should not be ambiguous, should not match more than one parent object. So, those who want to use new command will care to make unique ids. -- Best regards, Vladimir
Re: [PATCH v8 43/55] i386/cgs: Rename *mask_cpuid_features() to *adjust_cpuid_features()
On Tue, Apr 01, 2025 at 09:01:53AM -0400, Xiaoyao Li wrote: > Because for TDX case, there are also fixed-1 bits that enfored by TDX > module. > > Signed-off-by: Xiaoyao Li > --- > target/i386/confidential-guest.h | 20 ++-- > target/i386/kvm/kvm.c| 2 +- > target/i386/sev.c| 4 ++-- > 3 files changed, 13 insertions(+), 13 deletions(-) Reviewed-by: Daniel P. Berrangé With regards, Daniel -- |: https://berrange.com -o-https://www.flickr.com/photos/dberrange :| |: https://libvirt.org -o-https://fstop138.berrange.com :| |: https://entangle-photo.org-o-https://www.instagram.com/dberrange :|
Re: [PATCH v5 49/65] i386/tdx: handle TDG.VP.VMCALL
Sorry for the late response.
KVM part of TDX attestation support is submitting again. QEMU part will
follow and we need to settle dowm this topic before QEMU patches submission.
On 10/4/2024 2:08 AM, Daniel P. Berrangé wrote:
On Thu, Feb 29, 2024 at 01:37:10AM -0500, Xiaoyao Li wrote:
From: Isaku Yamahata
Add property "quote-generation-socket" to tdx-guest, which is a property
of type SocketAddress to specify Quote Generation Service(QGS).
On request of GetQuote, it connects to the QGS socket, read request
data from shared guest memory, send the request data to the QGS,
and store the response into shared guest memory, at last notify
TD guest by interrupt.
command line example:
qemu-system-x86_64 \
-object '{"qom-type":"tdx-guest","id":"tdx0","quote-generation-socket":{"type": "vsock",
"cid":"1","port":"1234"}}' \
-machine confidential-guest-support=tdx0
Note, above example uses vsock type socket because the QGS we used
implements the vsock socket. It can be other types, like UNIX socket,
which depends on the implementation of QGS.
To avoid no response from QGS server, setup a timer for the transaction.
If timeout, make it an error and interrupt guest. Define the threshold of
time to 30s at present, maybe change to other value if not appropriate.
Signed-off-by: Isaku Yamahata
Codeveloped-by: Chenyi Qiang
Signed-off-by: Chenyi Qiang
Codeveloped-by: Xiaoyao Li
Signed-off-by: Xiaoyao Li
diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c
index 49f94d9d46f4..7dfda507cc8c 100644
--- a/target/i386/kvm/tdx.c
+++ b/target/i386/kvm/tdx.c
+static int tdx_handle_get_quote(X86CPU *cpu, struct kvm_tdx_vmcall *vmcall)
+{
+struct tdx_generate_quote_task *task;
+struct tdx_get_quote_header hdr;
+hwaddr buf_gpa = vmcall->in_r12;
+uint64_t buf_len = vmcall->in_r13;
+
+QEMU_BUILD_BUG_ON(sizeof(struct tdx_get_quote_header) !=
TDX_GET_QUOTE_HDR_SIZE);
+
+vmcall->status_code = TDG_VP_VMCALL_INVALID_OPERAND;
+
+if (buf_len == 0) {
+return 0;
+}
+
+/* GPA must be shared. */
+if (!(buf_gpa & tdx_shared_bit(cpu))) {
+return 0;
+}
+buf_gpa &= ~tdx_shared_bit(cpu);
+
+if (!QEMU_IS_ALIGNED(buf_gpa, 4096) || !QEMU_IS_ALIGNED(buf_len, 4096)) {
+vmcall->status_code = TDG_VP_VMCALL_ALIGN_ERROR;
+return 0;
+}
+
+if (address_space_read(&address_space_memory, buf_gpa,
MEMTXATTRS_UNSPECIFIED,
+ &hdr, TDX_GET_QUOTE_HDR_SIZE) != MEMTX_OK) {
+error_report("TDX: get-quote: failed to read GetQuote header.\n");
+return -1;
+}
+
+if (le64_to_cpu(hdr.structure_version) != TDX_GET_QUOTE_STRUCTURE_VERSION)
{
+return 0;
+}
+
+/*
+ * Paranoid: Guest should clear error_code and out_len to avoid information
+ * leak. Enforce it. The initial value of them doesn't matter for qemu to
+ * process the request.
+ */
+if (le64_to_cpu(hdr.error_code) != TDX_VP_GET_QUOTE_SUCCESS ||
+le32_to_cpu(hdr.out_len) != 0) {
+return 0;
+}
+
+/* Only safe-guard check to avoid too large buffer size. */
+if (buf_len > TDX_GET_QUOTE_MAX_BUF_LEN ||
+le32_to_cpu(hdr.in_len) > buf_len - TDX_GET_QUOTE_HDR_SIZE) {
+return 0;
+}
+
+vmcall->status_code = TDG_VP_VMCALL_SUCCESS;
+if (!tdx_guest->quote_generator) {
+hdr.error_code = cpu_to_le64(TDX_VP_GET_QUOTE_QGS_UNAVAILABLE);
+if (address_space_write(&address_space_memory, buf_gpa,
+MEMTXATTRS_UNSPECIFIED,
+&hdr, TDX_GET_QUOTE_HDR_SIZE) != MEMTX_OK) {
+error_report("TDX: failed to update GetQuote header.\n");
+return -1;
+}
+return 0;
+}
+
+qemu_mutex_lock(&tdx_guest->quote_generator->lock);
+if (tdx_guest->quote_generator->num >= TDX_MAX_GET_QUOTE_REQUEST) {
+qemu_mutex_unlock(&tdx_guest->quote_generator->lock);
+vmcall->status_code = TDG_VP_VMCALL_RETRY;
+return 0;
+}
+tdx_guest->quote_generator->num++;
+qemu_mutex_unlock(&tdx_guest->quote_generator->lock);
+
+/* Mark the buffer in-flight. */
+hdr.error_code = cpu_to_le64(TDX_VP_GET_QUOTE_IN_FLIGHT);
+if (address_space_write(&address_space_memory, buf_gpa,
+MEMTXATTRS_UNSPECIFIED,
+&hdr, TDX_GET_QUOTE_HDR_SIZE) != MEMTX_OK) {
+error_report("TDX: failed to update GetQuote header.\n");
+return -1;
+}
+
+task = g_malloc(sizeof(*task));
+task->buf_gpa = buf_gpa;
+task->payload_gpa = buf_gpa + TDX_GET_QUOTE_HDR_SIZE;
+task->payload_len = buf_len - TDX_GET_QUOTE_HDR_SIZE;
+task->hdr = hdr;
+task->quote_gen = tdx_guest->quote_generator;
+task->completion = tdx_get_quote_completion;
+
+task->send_data_size = le32_to_cpu(hdr.in_len);
+task->send_data = g_malloc(task->send_data_size);
+task->send_data_sent = 0;
+
+if (a
Re: [PATCH 05/18] target/arm: Move CPU QOM type definitions to "hw/arm/cpu.h"
On 4/1/25 21:06, Philippe Mathieu-Daudé wrote: Cc'ing Pierrick On 12/1/23 08:17, Philippe Mathieu-Daudé wrote: On 11/1/23 21:02, Richard Henderson wrote: On 1/10/23 08:43, Philippe Mathieu-Daudé wrote: +++ b/target/arm/cpu.h @@ -26,6 +26,7 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" #include "qapi/qapi-types-common.h" +#include "hw/arm/cpu.h" I'm not a fan of this. If you want a smaller version of cpu-qom.h here in target/arm/, for use by hw/, that's one thing. But target/ should not be reaching back into hw/, IMO. I concur, but currently we have: $ git grep '#include "hw' target | wc -l 220 $ git grep -h '#include "hw' target | sort | uniq -c 1 #include "hw/acpi/acpi.h" 1 #include "hw/acpi/ghes.h" 1 #include "hw/arm/boot.h" 1 #include "hw/arm/virt.h" 19 #include "hw/boards.h" 2 #include "hw/clock.h" 3 #include "hw/core/accel-cpu.h" 24 #include "hw/core/cpu.h" 20 #include "hw/core/sysemu-cpu-ops.h" 24 #include "hw/core/tcg-cpu-ops.h" 1 #include "hw/hppa/hppa_hardware.h" 3 #include "hw/hw.h" 1 #include "hw/hyperv/hyperv-proto.h" 2 #include "hw/hyperv/hyperv.h" 2 #include "hw/i386/apic-msidef.h" 2 #include "hw/i386/apic.h" 8 #include "hw/i386/apic_internal.h" 1 #include "hw/i386/e820_memory_layout.h" 1 #include "hw/i386/intel_iommu.h" 1 #include "hw/i386/ioapic.h" 2 #include "hw/i386/pc.h" 1 #include "hw/i386/sgx-epc.h" 1 #include "hw/i386/topology.h" 1 #include "hw/i386/x86-iommu.h" 2 #include "hw/i386/x86.h" 1 #include "hw/intc/riscv_aclint.h" 8 #include "hw/irq.h" 1 #include "hw/isa/isa.h" 5 #include "hw/loader.h" 1 #include "hw/loongarch/virt.h" 2 #include "hw/mips/cpudevs.h" 2 #include "hw/pci/msi.h" 1 #include "hw/pci/msix.h" 3 #include "hw/pci/pci.h" 1 #include "hw/ppc/openpic_kvm.h" 5 #include "hw/ppc/ppc.h" 2 #include "hw/ppc/spapr.h" 1 #include "hw/ppc/spapr_cpu_core.h" 2 #include "hw/qdev-clock.h" 12 #include "hw/qdev-properties.h" 11 #include "hw/registerfields.h" 2 #include "hw/s390x/ebcdic.h" 5 #include "hw/s390x/ioinst.h" 2 #include "hw/s390x/ipl.h" 8 #include "hw/s390x/pv.h" 2 #include "hw/s390x/s390-pci-bus.h" 2 #include "hw/s390x/s390-pci-inst.h" 2 #include "hw/s390x/s390-virtio-ccw.h" 2 #include "hw/s390x/s390-virtio-hcall.h" 3 #include "hw/s390x/s390_flic.h" 1 #include "hw/s390x/sclp.h" 2 #include "hw/s390x/storage-keys.h" 1 #include "hw/s390x/tod.h" 1 #include "hw/sh4/sh_intc.h" 2 #include "hw/sysbus.h" 1 #include "hw/watchdog/wdt_diag288.h" 1 #include "hw/xtensa/xtensa-isa.h" Assuming we want to have a self-contained libtarget$arch, how can we deal with HW tied to the arch such CPU timers or NVIC? It's not what we'll achieve. Right now, what we call libX in meson.build is simply a selection of object files, without any guarantee that they don't have external dependency on symbols from other libraries. We use that to apply specific compilation flags to a set of files, and this is what we really achieve here. Yes, ideally, it would be better if hw was a leaf library in our dependency graph. However, it's not needed to solve this now, and it's not unblocking anything to be able to build a single binary, so I don't see it as a priority.
Re: [PATCH 1/2] vfio/migration: Add also max in-flight VFIO device state buffers size limit
On 4/2/25 14:40, Maciej S. Szmigiero wrote:
On 2.04.2025 11:51, Cédric Le Goater wrote:
Hello Maciej,
On 4/1/25 14:26, Maciej S. Szmigiero wrote:
On 11.03.2025 14:04, Cédric Le Goater wrote:
On 3/7/25 14:45, Maciej S. Szmigiero wrote:
On 7.03.2025 13:03, Cédric Le Goater wrote:
On 3/7/25 11:57, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
There's already a max in-flight VFIO device state buffers *count* limit,
no. there isn't. Do we need both ?
This is on a top of the remaining patches (x-migration-load-config-after-iter
and x-migration-max-queued-buffers) - I thought we were supposed to work
on these after the main series was merged as they are relatively non-critical.
yes. we don't need both count and size limits though, a size limit is enough.
I would also give x-migration-load-config-after-iter priority over
x-migration-max-queued-buffers{,-size} as the former is correctness fix
while the later are just additional functionalities.
ok. I have kept both patches in my tree with the doc updates.
I don't see the x-migration-load-config-after-iter patch in upstream QEMU
anywhere.
That's a bit concerning since it's a correctness fix - without it the
multifd VFIO migration on ARM64 can fail.
The existing patch still applies, but requires changing
"#if defined(TARGET_ARM)" to "strcmp(target_name(), "aarch64") == 0" due to
recent commit 5731baee6c3c ("hw/vfio: Compile some common objects once").
I can submit an updated patch if you like.
It is a bit early.
Let's wait for the spring cleanup to be applied first. I am waiting for
more feedback from Avihai and Joao. It should not be long.
I guess by "spring cleanup" you mean this patch set:
https://lore.kernel.org/qemu-devel/20250326075122.1299361-1-...@redhat.com/
It is marked "for-10.1" while I think we should not have this ARM64
regression in 10.0, which is due to be released in 2-3 weeks.
A regression would be mean the feature worked before which is not case,
it didn't exist.
As said before, I'd rather expose the initial "multifd support for VFIO
migration" feature first without workarounds in QEMU 10.0.
Support on ARM is broken not because we are missing support in VFIO
but because there is an issue in the ordering of device states on ARM.
IMO, this needs to be addressed with a larger crowd. Please include
migration maintainers, the virt ARM maintainers, GIC maintainers and
let's see what can be done to avoid a workaround during the QEMU 10.1
cycle.
VFIO migration is a recent feature. VFIO migration support on ARM
(for MLX5 VFs) is even newer (there were recently fixes in the
upstream kernel for it). If a distro needs support for it, your
patch is there and ready to be backported. So there is a plan B.
Let's not rush things please.
Thanks,
C.
Re: [PATCH 1/2] vfio/migration: Add also max in-flight VFIO device state buffers size limit
On 2.04.2025 11:51, Cédric Le Goater wrote:
Hello Maciej,
On 4/1/25 14:26, Maciej S. Szmigiero wrote:
On 11.03.2025 14:04, Cédric Le Goater wrote:
On 3/7/25 14:45, Maciej S. Szmigiero wrote:
On 7.03.2025 13:03, Cédric Le Goater wrote:
On 3/7/25 11:57, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
There's already a max in-flight VFIO device state buffers *count* limit,
no. there isn't. Do we need both ?
This is on a top of the remaining patches (x-migration-load-config-after-iter
and x-migration-max-queued-buffers) - I thought we were supposed to work
on these after the main series was merged as they are relatively non-critical.
yes. we don't need both count and size limits though, a size limit is enough.
I would also give x-migration-load-config-after-iter priority over
x-migration-max-queued-buffers{,-size} as the former is correctness fix
while the later are just additional functionalities.
ok. I have kept both patches in my tree with the doc updates.
I don't see the x-migration-load-config-after-iter patch in upstream QEMU
anywhere.
That's a bit concerning since it's a correctness fix - without it the
multifd VFIO migration on ARM64 can fail.
The existing patch still applies, but requires changing
"#if defined(TARGET_ARM)" to "strcmp(target_name(), "aarch64") == 0" due to
recent commit 5731baee6c3c ("hw/vfio: Compile some common objects once").
I can submit an updated patch if you like.
It is a bit early.
Let's wait for the spring cleanup to be applied first. I am waiting for
more feedback from Avihai and Joao. It should not be long.
I guess by "spring cleanup" you mean this patch set:
https://lore.kernel.org/qemu-devel/20250326075122.1299361-1-...@redhat.com/
It is marked "for-10.1" while I think we should not have this ARM64
regression in 10.0, which is due to be released in 2-3 weeks.
(The situation is different with the buffer queuing limits patches which
can wait since they are just additional functionalities rather than
correctness fixes).
Thanks,
C.
Thanks,
Maciej
Re: [PATCH 2/2] rust/hw/char/pl011/src/device: Implement logging
On Wed, Apr 02, 2025 at 09:33:16AM +, Bernhard Beschow wrote:
>
>
> Am 31. März 2025 09:18:05 UTC schrieb "Daniel P. Berrangé"
> :
> >On Sun, Mar 30, 2025 at 10:58:57PM +0200, Bernhard Beschow wrote:
> >> Now that there is logging support in Rust for QEMU, use it in the pl011
> >> device.
> >>
> >> Signed-off-by: Bernhard Beschow
> >> ---
> >> rust/hw/char/pl011/src/device.rs | 12
> >> 1 file changed, 8 insertions(+), 4 deletions(-)
> >>
> >> diff --git a/rust/hw/char/pl011/src/device.rs
> >> b/rust/hw/char/pl011/src/device.rs
> >> index bf88e0b00a..d5470fae11 100644
> >> --- a/rust/hw/char/pl011/src/device.rs
> >> +++ b/rust/hw/char/pl011/src/device.rs
> >> @@ -8,9 +8,11 @@
> >> chardev::{CharBackend, Chardev, Event},
> >> impl_vmstate_forward,
> >> irq::{IRQState, InterruptSource},
> >> +log::{LOG_GUEST_ERROR, LOG_UNIMP},
> >> memory::{hwaddr, MemoryRegion, MemoryRegionOps,
> >> MemoryRegionOpsBuilder},
> >> prelude::*,
> >> qdev::{Clock, ClockEvent, DeviceImpl, DeviceState, Property,
> >> ResetType, ResettablePhasesImpl},
> >> +qemu_log_mask,
> >> qom::{ObjectImpl, Owned, ParentField},
> >> static_assert,
> >> sysbus::{SysBusDevice, SysBusDeviceImpl},
> >> @@ -298,8 +300,7 @@ pub(self) fn write(
> >> DMACR => {
> >> self.dmacr = value;
> >> if value & 3 > 0 {
> >> -// qemu_log_mask(LOG_UNIMP, "pl011: DMA not
> >> implemented\n");
> >> -eprintln!("pl011: DMA not implemented");
> >> +qemu_log_mask!(LOG_UNIMP, "pl011: DMA not
> >> implemented\n");
> >> }
> >> }
> >> }
> >> @@ -535,7 +536,7 @@ fn read(&self, offset: hwaddr, _size: u32) -> u64 {
> >> u64::from(device_id[(offset - 0xfe0) >> 2])
> >> }
> >> Err(_) => {
> >> -// qemu_log_mask(LOG_GUEST_ERROR, "pl011_read: Bad offset
> >> 0x%x\n", (int)offset);
> >> +qemu_log_mask!(LOG_GUEST_ERROR, "pl011_read: Bad offset
> >> {offset}\n");
> >> 0
> >> }
> >> Ok(field) => {
> >> @@ -567,7 +568,10 @@ fn write(&self, offset: hwaddr, value: u64, _size:
> >> u32) {
> >> .borrow_mut()
> >> .write(field, value as u32, &self.char_backend);
> >> } else {
> >> -eprintln!("write bad offset {offset} value {value}");
> >> +qemu_log_mask!(
> >> +LOG_GUEST_ERROR,
> >> +"pl011_write: Bad offset {offset} value {value}\n"
> >> +);
> >> }
> >
> >General conceptual question . I've never understood what the dividing
> >line is between use of 'qemu_log_mask' and trace points.
>
> I *think* it's the perspective: If you want to see any issues, regardless
> of which device, use the -l option, i.e. qemu_log_mask(). If, however,
> you want to see what a particular device does, use tracepoints.
I guess I'd say that the latter ought to be capable of satisfying the
former use case too, given a suitable trace point selection. If it
can't, then perhaps that's telling us the way we select trace points
is insufficiently expressive ?
With regards,
Daniel
--
|: https://berrange.com -o-https://www.flickr.com/photos/dberrange :|
|: https://libvirt.org -o-https://fstop138.berrange.com :|
|: https://entangle-photo.org-o-https://www.instagram.com/dberrange :|
Re: [PATCH for-10.1 v2 26/37] vfio: Move dirty tracking related services into container-base.c
On 26/03/2025 07:51, Cédric Le Goater wrote:
> Routines of common.c :
>
> vfio_devices_all_dirty_tracking_started
> vfio_devices_all_device_dirty_tracking
> vfio_devices_query_dirty_bitmap
> vfio_get_dirty_bitmap
>
> are all related to dirty page tracking directly at the container level
> or at the container device level. Naming is a bit confusing. We will
> propose new names in the following changes.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Joao Martins
> ---
> include/hw/vfio/vfio-common.h | 9 --
> include/hw/vfio/vfio-container-base.h | 7 ++
> hw/vfio/common.c | 130
> hw/vfio/container-base.c | 138 ++
> hw/vfio/meson.build | 2 +-
> hw/vfio/trace-events | 4 +-
> 6 files changed, 149 insertions(+), 141 deletions(-)
>
> diff --git a/include/hw/vfio/vfio-common.h b/include/hw/vfio/vfio-common.h
> index
> 8b300e7768fb61af881f6a8b7eeb75dc84c98ac3..a804af9f651f0916ca06b3f4f009381eea385ba0
> 100644
> --- a/include/hw/vfio/vfio-common.h
> +++ b/include/hw/vfio/vfio-common.h
> @@ -141,15 +141,6 @@ int vfio_get_dev_region_info(VFIODevice *vbasedev,
> uint32_t type,
> bool vfio_has_region_cap(VFIODevice *vbasedev, int region, uint16_t
> cap_type);
> #endif
>
> -bool vfio_devices_all_dirty_tracking_started(
> -const VFIOContainerBase *bcontainer);
> -bool
> -vfio_devices_all_device_dirty_tracking(const VFIOContainerBase *bcontainer);
> -int vfio_devices_query_dirty_bitmap(const VFIOContainerBase *bcontainer,
> -VFIOBitmap *vbmap, hwaddr iova, hwaddr size, Error **errp);
> -int vfio_get_dirty_bitmap(const VFIOContainerBase *bcontainer, uint64_t iova,
> - uint64_t size, ram_addr_t ram_addr, Error **errp);
> -
> /* Returns 0 on success, or a negative errno. */
> bool vfio_device_get_name(VFIODevice *vbasedev, Error **errp);
> void vfio_device_set_fd(VFIODevice *vbasedev, const char *str, Error **errp);
> diff --git a/include/hw/vfio/vfio-container-base.h
> b/include/hw/vfio/vfio-container-base.h
> index
> b33231b94013e0b535b77887109a97f9128f1c15..8575cdcb587dfe803808d452c7dc6c81241a47cf
> 100644
> --- a/include/hw/vfio/vfio-container-base.h
> +++ b/include/hw/vfio/vfio-container-base.h
> @@ -91,6 +91,13 @@ int
> vfio_container_set_dirty_page_tracking(VFIOContainerBase *bcontainer,
> bool start, Error **errp);
> int vfio_container_query_dirty_bitmap(const VFIOContainerBase *bcontainer,
> VFIOBitmap *vbmap, hwaddr iova, hwaddr size, Error
> **errp);
> +bool vfio_devices_all_dirty_tracking_started(const VFIOContainerBase
> *bcontainer);
> +bool vfio_devices_all_device_dirty_tracking(const VFIOContainerBase
> *bcontainer);
> +int vfio_devices_query_dirty_bitmap(const VFIOContainerBase *bcontainer,
> +VFIOBitmap *vbmap, hwaddr iova, hwaddr
> size,
> +Error **errp);
> +int vfio_get_dirty_bitmap(const VFIOContainerBase *bcontainer, uint64_t iova,
> + uint64_t size, ram_addr_t ram_addr, Error **errp);
>
> GList *vfio_container_get_iova_ranges(const VFIOContainerBase *bcontainer);
>
> diff --git a/hw/vfio/common.c b/hw/vfio/common.c
> index
> e62bb3818c55a789e81fe50cebf7c6693228db31..85dedcbe5933c55c6fc25015d3701aba43b381a4
> 100644
> --- a/hw/vfio/common.c
> +++ b/hw/vfio/common.c
> @@ -52,27 +52,6 @@
> */
>
>
> -static bool vfio_devices_all_device_dirty_tracking_started(
> -const VFIOContainerBase *bcontainer)
> -{
> -VFIODevice *vbasedev;
> -
> -QLIST_FOREACH(vbasedev, &bcontainer->device_list, container_next) {
> -if (!vbasedev->dirty_tracking) {
> -return false;
> -}
> -}
> -
> -return true;
> -}
> -
> -bool vfio_devices_all_dirty_tracking_started(
> -const VFIOContainerBase *bcontainer)
> -{
> -return vfio_devices_all_device_dirty_tracking_started(bcontainer) ||
> - bcontainer->dirty_pages_started;
> -}
> -
> static bool vfio_log_sync_needed(const VFIOContainerBase *bcontainer)
> {
> VFIODevice *vbasedev;
> @@ -97,22 +76,6 @@ static bool vfio_log_sync_needed(const VFIOContainerBase
> *bcontainer)
> return true;
> }
>
> -bool vfio_devices_all_device_dirty_tracking(const VFIOContainerBase
> *bcontainer)
> -{
> -VFIODevice *vbasedev;
> -
> -QLIST_FOREACH(vbasedev, &bcontainer->device_list, container_next) {
> -if (vbasedev->device_dirty_page_tracking == ON_OFF_AUTO_OFF) {
> -return false;
> -}
> -if (!vbasedev->dirty_pages_supported) {
> -return false;
> -}
> -}
> -
> -return true;
> -}
> -
> static bool vfio_listener_skipped_section(MemoryRegionSection *section)
> {
> return (!memory_region_is_ram(section->mr) &&
> @@ -1010,99 +973,6 @@ static void
> vfio_listener_log_glo
Re: smbios entry point auto on pc-i440fx
On Wed, Apr 02, 2025 at 02:36:01PM +0200, Pierre-Samuel LE STANG wrote: > Hello team, > > I'm facing the issue of windows instances not beeing able of retrieving > the uuid because of smbios 3.0 (qemu 8.2 on debian openstack/libvirt). > The instances are of pc-i440fx-8.2 machine type. > > If I understand well since 8.1 qemu use a 64bit format for the smbios > v3 which is not handle by windows OS. > > I also found some commit about handling automatically the format by qemu > on q35 machine type to resolve this bug startting to 9.0.0 version > https://gitlab.com/qemu-project/qemu/-/issues/2008 > > It seems forced to 64 bit on pc-i440fx-8.1 and above while forced to 32 > under. > > Is there a reason to not handle it automatically on pc-i440fx machine > type? That is done since: commit 2c7c45b3d0ba097ac99bf4b9a13c6de1d7724032 Author: Igor Mammedov Date: Thu Mar 14 16:23:00 2024 +0100 pc/q35: set SMBIOS entry point type to 'auto' by default Use smbios-entry-point-type='auto' for newer machine types as a workaround for Windows not detecting SMBIOS tables. Which makes QEMU pick SMBIOS tables based on configuration (with 2.x preferred and fallback to 3.x if the former isn't compatible with configuration) Default compat setting of smbios-entry-point-type after series for pc/q35 machines: * 9.0-newer: 'auto' * 8.1-8.2: '64' * 8.0-older: '32' > Is it safe to keep it to 32 for machine type pc-i440fx-8.1 and above? Once QEMU ships a particular machine type version, it is fixed and we cannot change its defaults. Hence the "auto" choice of SMBIOS entrypoint is only done for 9.0 or newer machine types. With regards, Daniel -- |: https://berrange.com -o-https://www.flickr.com/photos/dberrange :| |: https://libvirt.org -o-https://fstop138.berrange.com :| |: https://entangle-photo.org-o-https://www.instagram.com/dberrange :|
Re: [PATCH for-10.1 v2 29/37] vfio: Rename vfio_devices_all_dirty_tracking_started()
On 26/03/2025 07:51, Cédric Le Goater wrote:
> Also rename vfio_devices_all_device_dirty_tracking_started() while at
> it and use the prefix 'vfio_container_devices_' for routines simply
> looping over the container's device list.
>
> Signed-off-by: Cédric Le Goater
Much better name indeed:
Reviewed-by: Joao Martins
> ---
> include/hw/vfio/vfio-container-base.h | 3 ++-
> hw/vfio/common.c | 2 +-
> hw/vfio/container-base.c | 6 +++---
> hw/vfio/container.c | 2 +-
> 4 files changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/include/hw/vfio/vfio-container-base.h
> b/include/hw/vfio/vfio-container-base.h
> index
> 04c87fe48bed75aa281a13f75a36e345036a9163..d00db365991aabf7fdee0c9306197920d9524ed8
> 100644
> --- a/include/hw/vfio/vfio-container-base.h
> +++ b/include/hw/vfio/vfio-container-base.h
> @@ -89,7 +89,8 @@ void vfio_container_del_section_window(VFIOContainerBase
> *bcontainer,
> MemoryRegionSection *section);
> int vfio_container_set_dirty_page_tracking(VFIOContainerBase *bcontainer,
> bool start, Error **errp);
> -bool vfio_devices_all_dirty_tracking_started(const VFIOContainerBase
> *bcontainer);
> +bool vfio_container_dirty_tracking_is_started(
> +const VFIOContainerBase *bcontainer);
> bool vfio_devices_all_device_dirty_tracking(const VFIOContainerBase
> *bcontainer);
> int vfio_get_dirty_bitmap(const VFIOContainerBase *bcontainer, uint64_t iova,
>uint64_t size, ram_addr_t ram_addr, Error **errp);
> diff --git a/hw/vfio/common.c b/hw/vfio/common.c
> index
> 85dedcbe5933c55c6fc25015d3701aba43b381a4..fae8756ade1f85c29a8567adef87135ee111baba
> 100644
> --- a/hw/vfio/common.c
> +++ b/hw/vfio/common.c
> @@ -56,7 +56,7 @@ static bool vfio_log_sync_needed(const VFIOContainerBase
> *bcontainer)
> {
> VFIODevice *vbasedev;
>
> -if (!vfio_devices_all_dirty_tracking_started(bcontainer)) {
> +if (!vfio_container_dirty_tracking_is_started(bcontainer)) {
> return false;
> }
>
> diff --git a/hw/vfio/container-base.c b/hw/vfio/container-base.c
> index
> 7f11aad339e713ea09123f361425370d87762950..7121f68464b144bc397a3bccc36743b65232273c
> 100644
> --- a/hw/vfio/container-base.c
> +++ b/hw/vfio/container-base.c
> @@ -141,7 +141,7 @@ int
> vfio_container_set_dirty_page_tracking(VFIOContainerBase *bcontainer,
> return ret;
> }
>
> -static bool vfio_devices_all_device_dirty_tracking_started(
> +static bool vfio_container_devices_dirty_tracking_is_started(
> const VFIOContainerBase *bcontainer)
> {
> VFIODevice *vbasedev;
> @@ -155,10 +155,10 @@ static bool
> vfio_devices_all_device_dirty_tracking_started(
> return true;
> }
>
> -bool vfio_devices_all_dirty_tracking_started(
> +bool vfio_container_dirty_tracking_is_started(
> const VFIOContainerBase *bcontainer)
> {
> -return vfio_devices_all_device_dirty_tracking_started(bcontainer) ||
> +return vfio_container_devices_dirty_tracking_is_started(bcontainer) ||
> bcontainer->dirty_pages_started;
> }
>
> diff --git a/hw/vfio/container.c b/hw/vfio/container.c
> index
> 7436388a73a424b11e6bad9ce80b86c3792242dd..e827ae9167b780ec9776ab98974245defb57590d
> 100644
> --- a/hw/vfio/container.c
> +++ b/hw/vfio/container.c
> @@ -137,7 +137,7 @@ static int vfio_legacy_dma_unmap(const VFIOContainerBase
> *bcontainer,
> int ret;
> Error *local_err = NULL;
>
> -if (iotlb && vfio_devices_all_dirty_tracking_started(bcontainer)) {
> +if (iotlb && vfio_container_dirty_tracking_is_started(bcontainer)) {
> if (!vfio_devices_all_device_dirty_tracking(bcontainer) &&
> bcontainer->dirty_pages_supported) {
> return vfio_dma_unmap_bitmap(container, iova, size, iotlb);
Re: [PATCH v2 20/30] target/arm/cpu: always define kvm related registers
On 25/3/25 02:24, Richard Henderson wrote:
On 3/24/25 14:11, Pierrick Bouvier wrote:
On 3/23/25 12:37, Richard Henderson wrote:
On 3/20/25 15:29, Pierrick Bouvier wrote:
This does not hurt, even if they are not used.
Signed-off-by: Pierrick Bouvier
---
target/arm/cpu.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index a8a1a8faf6b..ab7412772bc 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -971,7 +971,6 @@ struct ArchCPU {
*/
uint32_t kvm_target;
-#ifdef CONFIG_KVM
/* KVM init features for this CPU */
uint32_t kvm_init_features[7];
@@ -984,7 +983,6 @@ struct ArchCPU {
/* KVM steal time */
OnOffAuto kvm_steal_time;
-#endif /* CONFIG_KVM */
/* Uniprocessor system with MP extensions */
bool mp_is_up;
I'm not sure what this achieves? CONFIG_KVM is a configure-time
selection.
CONFIG_KVM is a poisoned identifier.
It's included via config-target.h, and not config-host.h.
Whoops, yes.
If we go this way, can we consistently allow CONFIG_${HW_ACCEL}
(read "remove poisoned defs in config-poison.h)?
[PATCH v3] hw/rtc: Add RTC PCF8563 module
Add PCF8563 a real-time clock with calendar and I2C interface.
This commit adds support for interfacing with it and implements
functionality of setting timer, alarm, reading and writing time.
Add a unit test for pcf8563_rtc module, that checks:
- default value after initialization
- set/get time
- minute alarm
- hour alarm
- day alarm
- wday alarm
- minute & hour alarm
- minute & day alarm
- day & wday alarm
- timer
Signed-off-by: Ilya Chichkov
---
v2->v3
Bernhard:
- Fix typo in test header comment section
- Move defines and pcf8563 struct to the header
- Merge test and production code patches
- Remove casting from void*
- Fix pcf8563 reset according datasheet
- Remove pcf8563_reset from pcf8563_init
- Inline pcf8563_reset inside pcf8563_reset_hold
---
hw/rtc/Kconfig | 5 +
hw/rtc/meson.build | 1 +
hw/rtc/pcf8563_rtc.c | 665 +++
hw/rtc/trace-events | 12 +
include/hw/rtc/pcf8563_rtc.h | 80 +
tests/qtest/meson.build | 1 +
tests/qtest/pcf8563-test.c | 466
7 files changed, 1230 insertions(+)
create mode 100644 hw/rtc/pcf8563_rtc.c
create mode 100644 include/hw/rtc/pcf8563_rtc.h
create mode 100644 tests/qtest/pcf8563-test.c
diff --git a/hw/rtc/Kconfig b/hw/rtc/Kconfig
index b90c2e510a..4e7a1f75ef 100644
--- a/hw/rtc/Kconfig
+++ b/hw/rtc/Kconfig
@@ -27,5 +27,10 @@ config GOLDFISH_RTC
config LS7A_RTC
bool
+config PCF8563_RTC
+bool
+depends on I2C
+default y if I2C_DEVICES
+
config STM32_RTC
bool
\ No newline at end of file
diff --git a/hw/rtc/meson.build b/hw/rtc/meson.build
index b6bb7436c7..6180ffc6d9 100644
--- a/hw/rtc/meson.build
+++ b/hw/rtc/meson.build
@@ -13,4 +13,5 @@ system_ss.add(when: 'CONFIG_GOLDFISH_RTC', if_true:
files('goldfish_rtc.c'))
system_ss.add(when: 'CONFIG_LS7A_RTC', if_true: files('ls7a_rtc.c'))
system_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-rtc.c'))
system_ss.add(when: 'CONFIG_MC146818RTC', if_true: files('mc146818rtc.c'))
+system_ss.add(when: 'CONFIG_PCF8563_RTC', if_true: files('pcf8563_rtc.c'))
system_ss.add(when: 'CONFIG_STM32_RTC', if_true: files('stm32-rtc.c'))
diff --git a/hw/rtc/pcf8563_rtc.c b/hw/rtc/pcf8563_rtc.c
new file mode 100644
index 00..5531328362
--- /dev/null
+++ b/hw/rtc/pcf8563_rtc.c
@@ -0,0 +1,665 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Real-time clock/calendar PCF8563 with I2C interface.
+ *
+ * Datasheet: https://www.nxp.com/docs/en/data-sheet/PCF8563.pdf
+ *
+ * Author (c) 2024 Ilya Chichkov
+ */
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "qemu/bitops.h"
+#include "hw/qdev-properties.h"
+#include "qemu/timer.h"
+#include "hw/i2c/i2c.h"
+#include "qemu/bcd.h"
+#include "qom/object.h"
+#include "sysemu/sysemu.h"
+#include "sysemu/rtc.h"
+#include "migration/vmstate.h"
+#include "qapi/visitor.h"
+#include "hw/register.h"
+#include "hw/registerfields.h"
+#include "hw/irq.h"
+#include "trace.h"
+
+#include "hw/rtc/pcf8563_rtc.h"
+
+#define MINUTES_IN_HOUR 60
+#define HOURS_IN_DAY 24
+#define DAYS_IN_MONTH 31
+#define DAYS_IN_WEEK 7
+
+REG8(PCF8563_CS1, 0x00)
+FIELD(PCF8563_CS1, RSVD0, 0, 3)
+FIELD(PCF8563_CS1, TESTC, 3, 1)
+FIELD(PCF8563_CS1, RSVD1, 4, 1)
+FIELD(PCF8563_CS1, STOP, 5, 1)
+FIELD(PCF8563_CS1, RSVD2, 6, 1)
+FIELD(PCF8563_CS1, TEST1, 7, 1)
+
+REG8(PCF8563_CS2, 0x01)
+FIELD(PCF8563_CS2, TIE, 0, 1)
+FIELD(PCF8563_CS2, AIE, 1, 1)
+FIELD(PCF8563_CS2, TF,2, 1)
+FIELD(PCF8563_CS2, AF,3, 1)
+FIELD(PCF8563_CS2, TI_TP, 4, 1)
+FIELD(PCF8563_CS2, RSVD, 5, 3)
+
+REG8(PCF8563_VLS, 0x02)
+FIELD(PCF8563_VLS, SECONDS, 0, 7)
+FIELD(PCF8563_VLS, VL, 7, 1)
+
+REG8(PCF8563_MINUTES, 0x03)
+FIELD(PCF8563_MINUTES, MINUTES, 0, 7)
+FIELD(PCF8563_MINUTES, RSVD,7, 1)
+
+REG8(PCF8563_HOURS, 0x04)
+FIELD(PCF8563_HOURS, HOURS, 0, 6)
+FIELD(PCF8563_HOURS, RSVD, 6, 2)
+
+REG8(PCF8563_DAYS, 0x05)
+FIELD(PCF8563_DAYS, DAYS, 0, 6)
+FIELD(PCF8563_DAYS, RSVD, 6, 2)
+
+REG8(PCF8563_WEEKDAYS, 0x06)
+FIELD(PCF8563_WEEKDAYS, WEEKDAYS, 0, 3)
+FIELD(PCF8563_WEEKDAYS, RSVD, 3, 5)
+
+REG8(PCF8563_CENTURY_MONTHS, 0x07)
+FIELD(PCF8563_CENTURY_MONTHS, MONTHS, 0, 5)
+FIELD(PCF8563_CENTURY_MONTHS, RSVD,5, 2)
+FIELD(PCF8563_CENTURY_MONTHS, CENTURY, 7, 1)
+
+REG8(PCF8563_YEARS, 0x08)
+FIELD(PCF8563_YEARS, YEARS, 0, 8)
+
+REG8(PCF8563_MINUTE_A, 0x09)
+FIELD(PCF8563_MINUTE_A, MINUTE_A, 0, 7)
+FIELD(PCF8563_MINUTE_A, AE_M, 7, 1)
+
+REG8(PCF8563_HOUR_A, 0x0A)
+FIELD(PCF8563_HOUR_A, HOUR_A, 0, 7)
+FIELD(PCF8563_HOUR_A, AE_H, 7, 1)
+
+REG8(PCF8563_DAY_A, 0x0B)
+FIELD(PCF8563_DAY_A, DAY_A, 0, 7)
+FIELD(PCF8563_DAY_A, AE_D, 7, 1)
+
+REG8(PCF8563_WEEKDAY_A, 0x0C)
+FIELD(PCF8563_WEEKDAY_A, WEEKDAY_A, 0, 3)
+FIELD(PCF8563_WEEKDAY_A, RSVD, 3, 4)
+FIELD(PCF8563_WEEKDAY_A
Re: [PATCH v8 03/28] vfio/container: support VFIO_DMA_UNMAP_FLAG_ALL
On 2/19/25 15:48, John Levon wrote:
Some containers can directly implement unmapping all regions;
add a new flag to support this.
Originally-by: John Johnson
Signed-off-by: Elena Ufimtseva
Signed-off-by: Jagannathan Raman
Signed-off-by: John Levon
---
hw/vfio/common.c | 24 +++--
hw/vfio/container-base.c | 4 +--
hw/vfio/container.c | 38 +--
hw/vfio/iommufd.c | 19 +-
include/hw/vfio/vfio-common.h | 1 +
include/hw/vfio/vfio-container-base.h | 4 +--
6 files changed, 68 insertions(+), 22 deletions(-)
This is difficult to understand. There are no functional changes right ?
I think it should be broken down further to clarify the changes.
Thanks,
C.
diff --git a/hw/vfio/common.c b/hw/vfio/common.c
index 6f106167fd..b49aafc40c 100644
--- a/hw/vfio/common.c
+++ b/hw/vfio/common.c
@@ -324,7 +324,7 @@ static void vfio_iommu_map_notify(IOMMUNotifier *n,
IOMMUTLBEntry *iotlb)
}
} else {
ret = vfio_container_dma_unmap(bcontainer, iova,
- iotlb->addr_mask + 1, iotlb);
+ iotlb->addr_mask + 1, iotlb, 0);
if (ret) {
error_report("vfio_container_dma_unmap(%p, 0x%"HWADDR_PRIx", "
"0x%"HWADDR_PRIx") = %d (%s)",
@@ -348,7 +348,7 @@ static void
vfio_ram_discard_notify_discard(RamDiscardListener *rdl,
int ret;
/* Unmap with a single call. */
-ret = vfio_container_dma_unmap(bcontainer, iova, size , NULL);
+ret = vfio_container_dma_unmap(bcontainer, iova, size, NULL, 0);
if (ret) {
error_report("%s: vfio_container_dma_unmap() failed: %s", __func__,
strerror(-ret));
@@ -806,21 +806,15 @@ static void vfio_listener_region_del(MemoryListener
*listener,
}
if (try_unmap) {
+int flags = 0;
+
if (int128_eq(llsize, int128_2_64())) {
-/* The unmap ioctl doesn't accept a full 64-bit span. */
-llsize = int128_rshift(llsize, 1);
-ret = vfio_container_dma_unmap(bcontainer, iova,
- int128_get64(llsize), NULL);
-if (ret) {
-error_report("vfio_container_dma_unmap(%p, 0x%"HWADDR_PRIx", "
- "0x%"HWADDR_PRIx") = %d (%s)",
- bcontainer, iova, int128_get64(llsize), ret,
- strerror(-ret));
-}
-iova += int128_get64(llsize);
+flags = VFIO_DMA_UNMAP_FLAG_ALL;
}
-ret = vfio_container_dma_unmap(bcontainer, iova,
- int128_get64(llsize), NULL);
+
+ret = vfio_container_dma_unmap(bcontainer, iova, int128_get64(llsize),
+ NULL, flags);
+
if (ret) {
error_report("vfio_container_dma_unmap(%p, 0x%"HWADDR_PRIx", "
"0x%"HWADDR_PRIx") = %d (%s)",
diff --git a/hw/vfio/container-base.c b/hw/vfio/container-base.c
index 5e0c9700d9..db27e9c31d 100644
--- a/hw/vfio/container-base.c
+++ b/hw/vfio/container-base.c
@@ -27,12 +27,12 @@ int vfio_container_dma_map(VFIOContainerBase *bcontainer,
int vfio_container_dma_unmap(VFIOContainerBase *bcontainer,
hwaddr iova, ram_addr_t size,
- IOMMUTLBEntry *iotlb)
+ IOMMUTLBEntry *iotlb, int flags)
{
VFIOIOMMUClass *vioc = VFIO_IOMMU_GET_CLASS(bcontainer);
g_assert(vioc->dma_unmap);
-return vioc->dma_unmap(bcontainer, iova, size, iotlb);
+return vioc->dma_unmap(bcontainer, iova, size, iotlb, flags);
}
bool vfio_container_add_section_window(VFIOContainerBase *bcontainer,
diff --git a/hw/vfio/container.c b/hw/vfio/container.c
index 0db0055f39..82987063e5 100644
--- a/hw/vfio/container.c
+++ b/hw/vfio/container.c
@@ -117,7 +117,7 @@ unmap_exit:
*/
static int vfio_legacy_dma_unmap(const VFIOContainerBase *bcontainer,
hwaddr iova, ram_addr_t size,
- IOMMUTLBEntry *iotlb)
+ IOMMUTLBEntry *iotlb, int flags)
{
const VFIOContainer *container = container_of(bcontainer, VFIOContainer,
bcontainer);
@@ -140,6 +140,34 @@ static int vfio_legacy_dma_unmap(const VFIOContainerBase
*bcontainer,
need_dirty_sync = true;
}
+/* use unmap all if supported */
+if (flags & VFIO_DMA_UNMAP_FLAG_ALL) {
+unmap.iova = 0;
+unmap.size = 0;
+if (container->unmap_all_supported) {
+ret = ioctl(container->fd, VFIO_IOMMU_UNMAP_DMA, unmap);
+} else {
+/* unmap in halves */
+Int128 llsize = int128_rshift(int128_2_64(),
Re: [PATCH v8 04/28] vfio: add vfio_attach_device_by_iommu_type()
On 2/19/25 15:48, John Levon wrote:
Allow attachment by explicitly passing a TYPE_VFIO_IOMMU_* string;
vfio-user will use this later.
Signed-off-by: John Levon
---
hw/vfio/common.c | 30 +++---
include/hw/vfio/vfio-common.h | 3 +++
2 files changed, 22 insertions(+), 11 deletions(-)
diff --git a/hw/vfio/common.c b/hw/vfio/common.c
index b49aafc40c..eefd735bc6 100644
--- a/hw/vfio/common.c
+++ b/hw/vfio/common.c
@@ -1569,25 +1569,20 @@ retry:
return info;
}
-bool vfio_attach_device(char *name, VFIODevice *vbasedev,
-AddressSpace *as, Error **errp)
+bool vfio_attach_device_by_iommu_type(const char *iommu_type, char *name,
+ VFIODevice *vbasedev, AddressSpace *as,
+ Error **errp)
{
-const VFIOIOMMUClass *ops =
-VFIO_IOMMU_CLASS(object_class_by_name(TYPE_VFIO_IOMMU_LEGACY));
HostIOMMUDevice *hiod = NULL;
-
-if (vbasedev->iommufd) {
-ops = VFIO_IOMMU_CLASS(object_class_by_name(TYPE_VFIO_IOMMU_IOMMUFD));
-}
-
-assert(ops);
-
+const VFIOIOMMUClass *ops =
+VFIO_IOMMU_CLASS(object_class_by_name(iommu_type));
if (!vbasedev->mdev) {
hiod = HOST_IOMMU_DEVICE(object_new(ops->hiod_typename));
vbasedev->hiod = hiod;
}
+
please drop the extra line.
if (!ops->attach_device(name, vbasedev, as, errp)) {
object_unref(hiod);
vbasedev->hiod = NULL;
@@ -1597,6 +1592,19 @@ bool vfio_attach_device(char *name, VFIODevice *vbasedev,
return true;
}
+bool vfio_attach_device(char *name, VFIODevice *vbasedev,
+ AddressSpace *as, Error **errp)
+{
+const char *iommu_type = TYPE_VFIO_IOMMU_LEGACY;
+
+if (vbasedev->iommufd) {
+iommu_type = TYPE_VFIO_IOMMU_IOMMUFD;
+}
May be use a ternary operator.
+return vfio_attach_device_by_iommu_type(iommu_type, name, vbasedev,
+as, errp);
+}
+
void vfio_detach_device(VFIODevice *vbasedev)
{
if (!vbasedev->bcontainer) {
diff --git a/include/hw/vfio/vfio-common.h b/include/hw/vfio/vfio-common.h
index f4f08eb8a6..c40f8de6bc 100644
--- a/include/hw/vfio/vfio-common.h
+++ b/include/hw/vfio/vfio-common.h
@@ -252,6 +252,9 @@ bool vfio_device_is_mdev(VFIODevice *vbasedev);
bool vfio_device_hiod_realize(VFIODevice *vbasedev, Error **errp);
bool vfio_attach_device(char *name, VFIODevice *vbasedev,
AddressSpace *as, Error **errp);
+bool vfio_attach_device_by_iommu_type(const char *iommu_type, char *name,
+ VFIODevice *vbasedev, AddressSpace *as,
+ Error **errp);
void vfio_detach_device(VFIODevice *vbasedev);
VFIODevice *vfio_get_vfio_device(Object *obj);
Looks OK. It will need a refresh because of the spring cleanup.
Thanks,
C.
[PATCH-for-10.1 v2 38/43] tcg: Move cpu_req_mo() macro to target-agnostic 'backend-ldst.h'
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/backend-ldst.h| 41 +
accel/tcg/internal-common.h | 27
accel/tcg/internal-target.h | 28 -
accel/tcg/cputlb.c | 1 +
accel/tcg/user-exec.c | 1 +
5 files changed, 70 insertions(+), 28 deletions(-)
create mode 100644 accel/tcg/backend-ldst.h
diff --git a/accel/tcg/backend-ldst.h b/accel/tcg/backend-ldst.h
new file mode 100644
index 000..9c3a407a5af
--- /dev/null
+++ b/accel/tcg/backend-ldst.h
@@ -0,0 +1,41 @@
+/*
+ * Internal memory barrier helpers for QEMU (target agnostic)
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+
+#ifndef ACCEL_TCG_BACKEND_LDST_H
+#define ACCEL_TCG_BACKEND_LDST_H
+
+#include "tcg-target-mo.h"
+
+/**
+ * tcg_req_mo:
+ * @guest_mo: Guest default memory order
+ * @type: TCGBar
+ *
+ * Filter @type to the barrier that is required for the guest
+ * memory ordering vs the host memory ordering. A non-zero
+ * result indicates that some barrier is required.
+ */
+#define tcg_req_mo(guest_mo, type) \
+((type) & guest_mo & ~TCG_TARGET_DEFAULT_MO)
+
+/**
+ * cpu_req_mo:
+ * @cpu: CPUState
+ * @type: TCGBar
+ *
+ * If tcg_req_mo indicates a barrier for @type is required
+ * for the guest memory model, issue a host memory barrier.
+ */
+#define cpu_req_mo(cpu, type) \
+do { \
+if (tcg_req_mo(cpu->cc->tcg_ops->guest_default_memory_order, type)) { \
+smp_mb(); \
+} \
+} while (0)
+
+#endif
diff --git a/accel/tcg/internal-common.h b/accel/tcg/internal-common.h
index 2f00560d102..829ae9389d2 100644
--- a/accel/tcg/internal-common.h
+++ b/accel/tcg/internal-common.h
@@ -108,4 +108,31 @@ static inline tb_page_addr_t
get_page_addr_code(CPUArchState *env,
return get_page_addr_code_hostp(env, addr, NULL);
}
+/**
+ * tcg_req_mo:
+ * @guest_mo: Guest default memory order
+ * @type: TCGBar
+ *
+ * Filter @type to the barrier that is required for the guest
+ * memory ordering vs the host memory ordering. A non-zero
+ * result indicates that some barrier is required.
+ */
+#define tcg_req_mo(guest_mo, type) \
+((type) & guest_mo & ~TCG_TARGET_DEFAULT_MO)
+
+/**
+ * cpu_req_mo:
+ * @cpu: CPUState
+ * @type: TCGBar
+ *
+ * If tcg_req_mo indicates a barrier for @type is required
+ * for the guest memory model, issue a host memory barrier.
+ */
+#define cpu_req_mo(cpu, type) \
+do { \
+if (tcg_req_mo(cpu->cc->tcg_ops->guest_default_memory_order, type)) { \
+smp_mb(); \
+} \
+} while (0)
+
#endif
diff --git a/accel/tcg/internal-target.h b/accel/tcg/internal-target.h
index f5a3fd7e402..9a9cef31406 100644
--- a/accel/tcg/internal-target.h
+++ b/accel/tcg/internal-target.h
@@ -13,7 +13,6 @@
#include "exec/exec-all.h"
#include "exec/translation-block.h"
#include "tb-internal.h"
-#include "tcg-target-mo.h"
#include "exec/mmap-lock.h"
/*
@@ -44,31 +43,4 @@ void page_table_config_init(void);
G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
#endif /* CONFIG_USER_ONLY */
-/**
- * tcg_req_mo:
- * @guest_mo: Guest default memory order
- * @type: TCGBar
- *
- * Filter @type to the barrier that is required for the guest
- * memory ordering vs the host memory ordering. A non-zero
- * result indicates that some barrier is required.
- */
-#define tcg_req_mo(guest_mo, type) \
-((type) & guest_mo & ~TCG_TARGET_DEFAULT_MO)
-
-/**
- * cpu_req_mo:
- * @cpu: CPUState
- * @type: TCGBar
- *
- * If tcg_req_mo indicates a barrier for @type is required
- * for the guest memory model, issue a host memory barrier.
- */
-#define cpu_req_mo(cpu, type) \
-do { \
-if (tcg_req_mo(cpu->cc->tcg_ops->guest_default_memory_order, type)) { \
-smp_mb(); \
-} \
-} while (0)
-
#endif /* ACCEL_TCG_INTERNAL_H */
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 35b1ff03a51..d9fb68d7198 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -48,6 +48,7 @@
#include "qemu/plugin-memory.h"
#endif
#include "tcg/tcg-ldst.h"
+#include "backend-ldst.h"
/* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 3f4d6824460..5eef8e7f186 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -37,6 +37,7 @@
#include "qemu/int128.h"
#include "trace.h"
#include "tcg/tcg-ldst.h"
+#include "backend-ldst.h"
#include "internal-common.h"
#include "internal-target.h"
#include "tb-internal.h"
--
2.47.1
Re: [PATCH] Rust: Add tracing and logging support for Rust code
Il mar 1 apr 2025, 10:27 Daniel P. Berrangé ha scritto: > This is a non-trivial degradation for the tracing code. The code is > generated in an inline function in the header so that when a probe > point is not active, it has as little overhead as possible - with > some backends it will just a 'nop' instruction. With this change > every probe is turned into a function call with no possiblity to > optimize away this overhead. > > IMHO tracing in Rust needs to be done by generating native Rust > code for the (sub)set of trace backends that we care about, and > not attempt to wrap the C trace code from Rust. > A little bit of both. Moving the body of the tracing to a C out-of-line function is okay: easier than converting printf strings to Rust format strings and possibly *more* efficient. The condition must remain inline though. Also, the focus should be on what the Rust API should look like, not on throwing some code on the other side of the fence. Introducing a second language has the risk of introducing massive technical debt, and therefore requires some design work. Tracing and logging is certainly not a one-patch task. Paolo With regards, > Daniel > -- > |: https://berrange.com -o- > https://www.flickr.com/photos/dberrange :| > |: https://libvirt.org -o- > https://fstop138.berrange.com :| > |: https://entangle-photo.org-o- > https://www.instagram.com/dberrange :| > > >
[PATCH-for-10.1 01/13] target/arm/cpu-features: Include missing 'cpu.h' header
"target/arm/cpu-features.h" dereferences the ARMISARegisters structure, which is defined in "cpu.h". Include the latter to avoid when refactoring unrelated headers: In file included from target/arm/internals.h:33: target/arm/cpu-features.h:45:54: error: unknown type name 'ARMISARegisters' 45 | static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id) | ^ target/arm/cpu-features.h:47:12: error: use of undeclared identifier 'R_ID_ISAR0_DIVIDE_SHIFT' 47 | return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; |^ Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu-features.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 525e4cee12f..4452e7c21e3 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -22,6 +22,7 @@ #include "hw/registerfields.h" #include "qemu/host-utils.h" +#include "cpu.h" /* * Naming convention for isar_feature functions: -- 2.47.1
[PATCH-for-10.1 13/13] hw/arm/virt-acpi: Replace arm_feature() -> arm_cpu_has_feature()
Using arm_cpu_has_feature() instead of arm_feature() remove
a dependency on (the indirectly included) "cpu.h" header.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/virt-acpi-build.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index da61af1d359..ae28d958895 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -58,6 +58,7 @@
#include "hw/acpi/ghes.h"
#include "hw/acpi/viot.h"
#include "hw/virtio/virtio-acpi.h"
+#include "target/arm/cpu_has_feature.h"
#include "target/arm/multiprocessing.h"
#include "target/arm/psci.h"
@@ -697,7 +698,7 @@ build_madt(GArray *table_data, BIOSLinker *linker,
VirtMachineState *vms)
ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));
uint64_t physical_base_address = 0, gich = 0, gicv = 0;
uint32_t vgic_interrupt = vms->virt ? ARCH_GIC_MAINT_IRQ : 0;
-uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ?
+uint32_t pmu_interrupt = arm_cpu_has_feature(armcpu, ARM_FEATURE_PMU) ?
VIRTUAL_PMU_IRQ : 0;
if (vms->gic_version == VIRT_GIC_VERSION_2) {
--
2.47.1
[PATCH-for-10.1 00/13] arm: Spring header cleanups
This series is more useful for heterogeneous emulation preparation than single binary, because it allows non-ARM hw/ code to configure ARM cores, so not using target-specific APIs. I figured some patches could be useful to Pierrick "build hw/arm once" series (in particular arm_cpu_has_feature). Philippe Mathieu-Daudé (13): target/arm/cpu-features: Include missing 'cpu.h' header target/arm/qmp: Include missing 'cpu.h' header target/arm/kvm: Include missing 'cpu-qom.h' header target/arm/hvf: Include missing 'cpu-qom.h' header hw/arm: Remove unnecessary 'cpu.h' header target/arm: Restrict inclusion of 'multiprocessing.h' target/arm: Move some definitions from 'cpu.h' to 'multiprocessing.h' hw/arm: Include missing 'target/arm/gtimer.h' header target/arm: Extract PSCI definitions to 'psci.h' target/arm: Extract feature definitions to 'cpu_has_feature.h' header target/arm: Add arm_cpu_has_feature() helper hw/arm/realview: Replace arm_feature() -> arm_cpu_has_feature() hw/arm/virt-acpi: Replace arm_feature() -> arm_cpu_has_feature() include/hw/arm/boot.h| 3 +- target/arm/cpu-features.h| 1 + target/arm/cpu.h | 78 +--- target/arm/cpu_has_feature.h | 67 +++ target/arm/hvf_arm.h | 2 +- target/arm/kvm_arm.h | 1 + target/arm/multiprocessing.h | 18 + target/arm/psci.h| 18 + hw/arm/aspeed_ast2600.c | 1 + hw/arm/aspeed_ast27x0.c | 2 + hw/arm/bananapi_m2u.c| 1 + hw/arm/bcm2838.c | 1 + hw/arm/boot.c| 1 + hw/arm/exynos4210.c | 3 +- hw/arm/fsl-imx8mp.c | 1 + hw/arm/highbank.c| 2 +- hw/arm/imx8mp-evk.c | 1 + hw/arm/mcimx6ul-evk.c| 1 + hw/arm/mcimx7d-sabre.c | 1 + hw/arm/mps3r.c | 2 +- hw/arm/npcm8xx.c | 2 + hw/arm/orangepi.c| 1 + hw/arm/realview.c| 10 ++--- hw/arm/sbsa-ref.c| 2 + hw/arm/smmuv3.c | 1 - hw/arm/virt-acpi-build.c | 4 +- hw/arm/virt.c| 1 + hw/arm/xlnx-versal-virt.c| 1 + hw/arm/xlnx-zcu102.c | 1 + hw/vmapple/vmapple.c | 3 ++ target/arm/arm-qmp-cmds.c| 1 + target/arm/cpu.c | 8 target/arm/helper.c | 1 + target/arm/hvf/hvf.c | 1 + target/arm/kvm.c | 1 + target/arm/tcg/op_helper.c | 2 + target/arm/tcg/psci.c| 1 + 37 files changed, 156 insertions(+), 90 deletions(-) create mode 100644 target/arm/cpu_has_feature.h create mode 100644 target/arm/psci.h -- 2.47.1
[PATCH-for-10.1 04/13] target/arm/hvf: Include missing 'cpu-qom.h' header
ARMCPU typedef is declared in "cpu-qom.h". Include it in order to avoid when refactoring unrelated headers: target/arm/hvf_arm.h:23:41: error: unknown type name 'ARMCPU' 23 | void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu); | ^ Signed-off-by: Philippe Mathieu-Daudé --- target/arm/hvf_arm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/hvf_arm.h b/target/arm/hvf_arm.h index 26c717b3826..ee5545f2d10 100644 --- a/target/arm/hvf_arm.h +++ b/target/arm/hvf_arm.h @@ -11,7 +11,7 @@ #ifndef QEMU_HVF_ARM_H #define QEMU_HVF_ARM_H -#include "cpu.h" +#include "target/arm/cpu-qom.h" /** * hvf_arm_init_debug() - initialize guest debug capabilities -- 2.47.1
Re: [PATCH] hw/arm/virt.c: Fix wrong default cpu type in AARCH64
On Thu, Apr 3, 2025 at 2:43 AM Richard Henderson
wrote:
>
> On 4/2/25 06:54, Zhang Chen wrote:
> > Because of the CONFIG_TCG auto enabled, the cpu type "cortex-a15"
> > is mistakenly set to the default AARCH64 target.
>
> This is the correct backward compatible setting.
> In essence, it means that you *must* supply a -cpu argument.
>
>
If the "-cpu" is required, the VM should not be started without this argument.
If yes, I will skip this patch and submit another one to make QEMU
refuse to start without this parameter.
Thanks
Chen
> r~
>
> >
> > Signed-off-by: Zhang Chen
> > ---
> > hw/arm/virt.c | 5 +++--
> > 1 file changed, 3 insertions(+), 2 deletions(-)
> >
> > diff --git a/hw/arm/virt.c b/hw/arm/virt.c
> > index a96452f17a..63649e9543 100644
> > --- a/hw/arm/virt.c
> > +++ b/hw/arm/virt.c
> > @@ -3178,9 +3178,10 @@ static void virt_machine_class_init(ObjectClass *oc,
> > void *data)
> > mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
> > #ifdef CONFIG_TCG
> > mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
> > -#else
> > +#ifdef TARGET_AARCH64
> > mc->default_cpu_type = ARM_CPU_TYPE_NAME("max");
> > -#endif
> > +#endif /* TARGET_AARCH64 */
> > +#endif /* CONFIG_TCG */
> > mc->valid_cpu_types = valid_cpu_types;
> > mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
> > mc->kvm_type = virt_kvm_type;
>
>
Re: [PATCH-for-10.1 21/43] target/s390x: Restrict SoftMMU mmu_index() to TCG
On 2/4/25 23:03, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/s390x/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 1f75629ddc2..320ace67198 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -348,6 +348,7 @@ static const TCGCPUOps s390_tcg_ops = {
.initialize = s390x_translate_init,
.translate_code = s390x_translate_code,
.restore_state_to_opc = s390x_restore_state_to_opc,
+.mmu_index = s390x_cpu_mmu_index,
#ifdef CONFIG_USER_ONLY
.record_sigsegv = s390_cpu_record_sigsegv,
@@ -378,7 +379,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
&scc->parent_phases);
cc->class_by_name = s390_cpu_class_by_name;
-cc->mmu_index = s390x_cpu_mmu_index;
cc->dump_state = s390_cpu_dump_state;
cc->query_cpu_fast = s390_query_cpu_fast;
cc->set_pc = s390_cpu_set_pc;
Missing:
-- >8 --
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 9efa4ef735..43fc3194bc 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -128,7 +128,2 @@ static vaddr s390_cpu_get_pc(CPUState *cs)
-static int s390x_cpu_mmu_index(CPUState *cs, bool ifetch)
-{
-return s390x_env_mmu_index(cpu_env(cs), ifetch);
-}
-
static void s390_query_cpu_fast(CPUState *cpu, CpuInfoFast *value)
@@ -310,2 +305,7 @@ static const Property s390x_cpu_properties[] = {
+static int s390x_cpu_mmu_index(CPUState *cs, bool ifetch)
+{
+return s390x_env_mmu_index(cpu_env(cs), ifetch);
+}
+
void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc,
---
With following description:
---
Convert CPUClass::mmu_index() to TCGCPUOps::mmu_index(),
restricting s390x_cpu_mmu_index() to TCG #ifdef.
---
Re: [PATCH-for-10.0 1/5] qtest/bios-tables-test: Add test for -M virt,its=off
Hi Phil,
On 4/2/25 07:30, Philippe Mathieu-Daudé wrote:
On 2/4/25 08:41, Gustavo Romero wrote:
Hi Phil,
On 3/31/25 19:12, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
Please, put commit message (body) into the commits.
For example, the commit message here could quickly explain that the FACP table
changed because virtualization=on (due to PSCI conduit). I'm assuming
virtualization is set to on because gic-version=max and so GICv4 is selected for
testing. It also could be that we want to exercise its=off when Arm
Virtualization
Extensions are enabled, which is the common use case (I understand that ITS
can be used also with virtualization=off).
Finally, the commit message could mention at the end which struct
vanishes in APIC table and why IO remapping table is affected by
ITS on/off.
A good commit message always help in code spelunking :)
I simply copied the reproducer from the issue, so I'll mention that.
(https://gitlab.com/qemu-project/qemu/-/issues/2886)
---
tests/qtest/bios-tables-test.c | 22 ++
tests/data/acpi/aarch64/virt/APIC.its_off | Bin 0 -> 184 bytes
tests/data/acpi/aarch64/virt/FACP.its_off | Bin 0 -> 276 bytes
tests/data/acpi/aarch64/virt/IORT.its_off | Bin 0 -> 236 bytes
4 files changed, 22 insertions(+)
create mode 100644 tests/data/acpi/aarch64/virt/APIC.its_off
create mode 100644 tests/data/acpi/aarch64/virt/FACP.its_off
create mode 100644 tests/data/acpi/aarch64/virt/IORT.its_off
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables- test.c
index 0a333ec4353..55366bf4956 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -2146,6 +2146,26 @@ static void test_acpi_aarch64_virt_tcg_topology(void)
free_test_data(&data);
}
+static void test_acpi_aarch64_virt_tcg_its_off(void)
+{
+ test_data data = {
+ .machine = "virt",
+ .arch = "aarch64",
+ .variant = ".its_off",
+ .tcg_only = true,
+ .uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
+ .uefi_fl2 = "pc-bios/edk2-arm-vars.fd",
+ .cd = "tests/data/uefi-boot-images/bios-tables-
test.aarch64.iso.qcow2",
+ .ram_start = 0x4000ULL,
+ .scan_len = 128ULL * 1024 * 1024,
+ };
+
+ test_acpi_one("-cpu cortex-a57 "
+ "-M virtualization=on,secure=off "
+ "-M gic-version=max,its=off,iommu=smmuv3", &data);
+ free_test_data(&data);
+}
+
static void test_acpi_q35_viot(void)
{
test_data data = {
@@ -2577,6 +2597,8 @@ int main(int argc, char *argv[])
test_acpi_aarch64_virt_tcg_acpi_hmat);
qtest_add_func("acpi/virt/topology",
test_acpi_aarch64_virt_tcg_topology);
+ qtest_add_func("acpi/virt/its_off",
+ test_acpi_aarch64_virt_tcg_its_off);
qtest_add_func("acpi/virt/numamem",
test_acpi_aarch64_virt_tcg_numamem);
qtest_add_func("acpi/virt/memhp",
test_acpi_aarch64_virt_tcg_memhp);
diff --git a/tests/data/acpi/aarch64/virt/APIC.its_off b/tests/data/
acpi/aarch64/virt/APIC.its_off
new file mode 100644
index
..c37d05d6e05805304f10afe73eb7cb9100fcccfa
GIT binary patch
literal 184
zcmZ<^@O0k6z`($=+{xeBBUr&HBEVSz2pEB4AU24G0Uik$i-7~iVgWL^17JJ`2AFzr
bgb+@aBn}xq0gwb2)Q)cq{30-g9B_L93G4|0
literal 0
HcmV?d1
diff --git a/tests/data/acpi/aarch64/virt/FACP.its_off b/tests/data/
acpi/aarch64/virt/FACP.its_off
new file mode 100644
index
..606dac3fe4b55c31fd68b25d3a4127eeef227434
GIT binary patch
literal 276
zcmZ>BbPf
Re: [PATCH-for-10.0 3/5] hw/arm/virt-acpi: Factor its_enabled() helper out
Hi Phil,
On 4/2/25 07:27, Philippe Mathieu-Daudé wrote:
On 2/4/25 08:43, Gustavo Romero wrote:
Hi Phil,
On 3/31/25 19:12, Philippe Mathieu-Daudé wrote:
GIC ITS is checked for the MADT and IORT tables.
Factor the checks out to the its_enabled() helper.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/virt-acpi-build.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 3ac8f8e1786..fdc08b40883 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -208,6 +208,13 @@ static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineState
*vms)
#define ROOT_COMPLEX_ENTRY_SIZE 36
#define IORT_NODE_OFFSET 48
+static bool its_enabled(VirtMachineState *vms)
+{
+ VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
+
+ return its_class_name() && !vmc->no_its;
+}
+
Isn't its_class_name() always "true"?
The method signature is described as:
/**
* its_class_name:
*
* Return the ITS class name to use depending on whether
* KVM acceleration and KVM CAP_SIGNAL_MSI are supported
*
* Returns: class name to use or NULL
*/
const char *its_class_name(void);
So I'd say no.
Indeed since commit cc5e719e2c8 ("kvm: require KVM_CAP_SIGNAL_MSI")
the single implementation doesn't return NULL anymore.
Paolo, can we update the signature and clean code path?
Updating the signature won't solve the redundancy here. Using its_class_name()
for gating the generation of GIC ITS-related ACPI data is still moot.
Anyhow Gustavo, while well noticed, this is pre-exising and unrelated
to the code movement in this patch.
hmm I think the fix is kind simple: just remove its_class_name() from
the predicate in its_enabled(). Is that what you meant by "clean code path"
above?
This seems correct to me because we always have ITS present if
(vmc->no_its == false and vms->its == true). If TCG is used and option
its=on is given ITS is created in create_its(). If KVM accel is used
it's as in the commit message from Paolo you pointed out:
ARM uses it to detect the presence of the ITS emulation in the kernel,
introduced in Linux 4.8. **Assume that it's there and possibly fail when
realizing the arm-its-kvm device.**
So if kernel does not support in-kernel ITS kvm_arm_its_realize() will
bail out with "error creating in-kernel ITS".
It's up to you if you want to fix it in this series or not :)
/*
* Append an ID mapping entry as described by "Table 4 ID mapping format" in
* "IO Remapping Table System Software on ARM Platforms", Chapter 3.
@@ -670,7 +677,6 @@ static void
build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
{
int i;
- VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
const MemMapEntry *memmap = vms->memmap;
AcpiTable table = { .sig = "APIC", .rev = 4, .oem_id = vms->oem_id,
.oem_table_id = vms->oem_table_id };
@@ -741,7 +747,7 @@ build_madt(GArray *table_data, BIOSLinker *linker,
VirtMachineState *vms)
memmap[VIRT_HIGH_GIC_REDIST2].size);
}
- if (its_class_name() && !vmc->no_its) {
+ if (its_enabled(vms)) {
/*
* ACPI spec, Revision 6.0 Errata A
* (original 6.0 definition has invalid Length)
@@ -973,7 +979,7 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables
*tables)
vms->oem_table_id);
}
- if (its_class_name() && !vmc->no_its) {
+ if (its_enabled(vms)) {
acpi_add_table(table_offsets, tables_blob);
build_iort(tables_blob, tables->linker, vms);
}
I can't see how that's right. Gating IORT table generation entirely based
on the presence of ITS looks wrong because IORT table has data beyond GIC ITS,
like for SMMUv3 etc.. Maybe open an issue to investigate it later?
FWIW,
Reviewed-by: Gustavo Romero
Cheers,
Gustavo
Re: [PATCH-for-10.0 5/5] qtest/bios-tables-test: Update aarch64/virt/APIC.its_off blob
Hi Phil, On 4/2/25 07:34, Philippe Mathieu-Daudé wrote: On 2/4/25 08:45, Gustavo Romero wrote: Hi Phil, On 3/31/25 19:12, Philippe Mathieu-Daudé wrote: Changes in the tables: @@ -1,32 +1,32 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20240927 (64-bit version) * Copyright (c) 2000 - 2023 Intel Corporation * * Disassembly of tests/data/acpi/aarch64/virt/APIC.its_off * * ACPI Data Table [APIC] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue (in hex) */ [000h 004h] Signature : "APIC" [Multiple APIC Description Table (MADT)] -[004h 0004 004h] Table Length : 00B8 +[004h 0004 004h] Table Length : 00A4 [008h 0008 001h] Revision : 04 -[009h 0009 001h] Checksum : A7 +[009h 0009 001h] Checksum : EE [00Ah 0010 006h] Oem ID : "BOCHS " [010h 0016 008h] Oem Table ID : "BXPC " [018h 0024 004h] Oem Revision : 0001 [01Ch 0028 004h] Asl Compiler ID : "BXPC" [020h 0032 004h] Asl Compiler Revision : 0001 [024h 0036 004h] Local Apic Address : [028h 0040 004h] Flags (decoded below) : PC-AT Compatibility : 0 [02Ch 0044 001h] Subtable Type : 0C [Generic Interrupt Distributor] [02Dh 0045 001h] Length : 18 [02Eh 0046 002h] Reserved : [030h 0048 004h] Local GIC Hardware ID : [034h 0052 008h] Base Address : 0800 [03Ch 0060 004h] Interrupt Base : @@ -49,37 +49,29 @@ [06Ch 0108 008h] Virtual GIC Base Address : [074h 0116 008h] Hypervisor GIC Base Address : [07Ch 0124 004h] Virtual GIC Interrupt : 0019 [080h 0128 008h] Redistributor Base Address : [088h 0136 008h] ARM MPIDR : [090h 0144 001h] Efficiency Class : 00 [091h 0145 001h] Reserved : 00 [092h 0146 002h] SPE Overflow Interrupt : [094h 0148 002h] TRBE Interrupt : 100E [094h 0148 001h] Subtable Type : 0E [Generic Interrupt Redistributor] [095h 0149 001h] Length : 10 [097h 0151 002h] Reserved : [098h 0152 008h] Base Address : 080A [0A0h 0160 004h] Length : 00F6 -[0A4h 0164 001h] Subtable Type : 0F [Generic Interrupt Translator] -[0A5h 0165 001h] Length : 14 -[0A7h 0167 002h] Reserved : -[0A8h 0168 004h] Translation ID : -[0ACh 0172 008h] Base Address : 0808 -[0B4h 0180 004h] Reserved : +Raw Table Data: Length 164 (0xA4) -Raw Table Data: Length 184 (0xB8) - - : 41 50 49 43 B8 00 00 00 04 A7 42 4F 43 48 53 20 // APIC..BOCHS + : 41 50 49 43 A4 00 00 00 04 EE 42 4F 43 48 53 20 // APIC..BOCHS 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC BXPC 0020: 01 00 00 00 00 00 00 00 00 00 00 00 0C 18 00 00 // 0030: 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 // 0040: 04 00 00 00 0B 50 00 00 00 00 00 00 00 00 00 00 // .P.. 0050: 01 00 00 00 00 00 00 00 17 00 00 00 00 00 00 00 // 0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // 0070: 00 00 00 00 00 00 00 00 00 00 00 00 19 00 00 00 // 0080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // 0090: 00 00 00 00 0E 10 00 00 00 00 0A 08 00 00 00 00 // - 00A0: 00 00 F6 00 0F 14 00 00 00 00 00 00 00 00 08 08 // - 00B0: 00 00 00 00 00 00 00 00 // + 00A0: 00 00 F6 00 // Signed-off-by: Philippe Mathieu-Daudé --- tests/qtest/bios-tables-test-allowed-diff.h | 1 - tests/data/acpi/aarch64/virt/APIC.its_off | Bin 184 -> 164 bytes 2 files changed, 1 deletion(-) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/ qtest/bios-tables-test-allowed-diff.h index bfc4d601243..dfb8523c8bf 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,2 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/aarch64/virt/APIC.its_off", diff --git a/tests/data/acpi/aarch64/virt/APIC.its_off b/tests/data/ acpi/aarch64/virt/APIC.
Re: [PATCH-for-10.0 2/5] qtest/bios-tables-test: Whitelist aarch64/virt/APIC.its_off blob
Hi Phil, On 4/2/25 07:31, Philippe Mathieu-Daudé wrote: On 2/4/25 08:43, Gustavo Romero wrote: Hi Phil, On 3/31/25 19:12, Philippe Mathieu-Daudé wrote: Prepare for ACPI table change in aarch64/virt/APIC.its_off. The comment could be smth like: Ignore APIC.its_off expected table (blob) for now until we update it later, after fixing the code that generates this table correctly. ? Signed-off-by: Philippe Mathieu-Daudé --- tests/qtest/bios-tables-test-allowed-diff.h | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/ qtest/bios-tables-test-allowed-diff.h index dfb8523c8bf..bfc4d601243 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,2 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/aarch64/virt/APIC.its_off", I think this patch should be merged into 1/2, accordingly to my comment in 1/5. FACP and IORT .its_off files should be added to the list as well. No, otherwise the test added in previous patch fails. I can't see how adding the tests to the list in tests/qtest/bios-tables-test-allowed-diff.h can cause any failure. The list in this header file works as a "ignore list", so even if the .its_off blobs in 1/5 were empty (for instance) the test would pass if they are in this list. That said, as per my comments in 1/5, this preparation is correct to me: the fix will cause changes to APIC table so the current expected blob (committed) needs to be ignored until it gets updated later, in 5/5. Reviewed-by: Gustavo Romero Cheers, Gustavo
Re: [PATCH-for-10.0 1/5] qtest/bios-tables-test: Add test for -M virt,its=off
On 2/4/25 08:41, Gustavo Romero wrote:
Hi Phil,
On 3/31/25 19:12, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
Please, put commit message (body) into the commits.
For example, the commit message here could quickly explain that the FACP
table
changed because virtualization=on (due to PSCI conduit). I'm assuming
virtualization is set to on because gic-version=max and so GICv4 is
selected for
testing. It also could be that we want to exercise its=off when Arm
Virtualization
Extensions are enabled, which is the common use case (I understand that ITS
can be used also with virtualization=off).
Finally, the commit message could mention at the end which struct
vanishes in APIC table and why IO remapping table is affected by
ITS on/off.
A good commit message always help in code spelunking :)
I simply copied the reproducer from the issue, so I'll mention that.
(https://gitlab.com/qemu-project/qemu/-/issues/2886)
---
tests/qtest/bios-tables-test.c | 22 ++
tests/data/acpi/aarch64/virt/APIC.its_off | Bin 0 -> 184 bytes
tests/data/acpi/aarch64/virt/FACP.its_off | Bin 0 -> 276 bytes
tests/data/acpi/aarch64/virt/IORT.its_off | Bin 0 -> 236 bytes
4 files changed, 22 insertions(+)
create mode 100644 tests/data/acpi/aarch64/virt/APIC.its_off
create mode 100644 tests/data/acpi/aarch64/virt/FACP.its_off
create mode 100644 tests/data/acpi/aarch64/virt/IORT.its_off
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-
test.c
index 0a333ec4353..55366bf4956 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -2146,6 +2146,26 @@ static void
test_acpi_aarch64_virt_tcg_topology(void)
free_test_data(&data);
}
+static void test_acpi_aarch64_virt_tcg_its_off(void)
+{
+ test_data data = {
+ .machine = "virt",
+ .arch = "aarch64",
+ .variant = ".its_off",
+ .tcg_only = true,
+ .uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
+ .uefi_fl2 = "pc-bios/edk2-arm-vars.fd",
+ .cd = "tests/data/uefi-boot-images/bios-tables-
test.aarch64.iso.qcow2",
+ .ram_start = 0x4000ULL,
+ .scan_len = 128ULL * 1024 * 1024,
+ };
+
+ test_acpi_one("-cpu cortex-a57 "
+ "-M virtualization=on,secure=off "
+ "-M gic-version=max,its=off,iommu=smmuv3", &data);
+ free_test_data(&data);
+}
+
static void test_acpi_q35_viot(void)
{
test_data data = {
@@ -2577,6 +2597,8 @@ int main(int argc, char *argv[])
test_acpi_aarch64_virt_tcg_acpi_hmat);
qtest_add_func("acpi/virt/topology",
test_acpi_aarch64_virt_tcg_topology);
+ qtest_add_func("acpi/virt/its_off",
+ test_acpi_aarch64_virt_tcg_its_off);
qtest_add_func("acpi/virt/numamem",
test_acpi_aarch64_virt_tcg_numamem);
qtest_add_func("acpi/virt/memhp",
test_acpi_aarch64_virt_tcg_memhp);
diff --git a/tests/data/acpi/aarch64/virt/APIC.its_off b/tests/data/
acpi/aarch64/virt/APIC.its_off
new file mode 100644
index
..c37d05d6e05805304f10afe73eb7cb9100fcccfa
GIT binary patch
literal 184
zcmZ<^@O0k6z`($=+{xeBBUr&HBEVSz2pEB4AU24G0Uik$i-7~iVgWL^17JJ`2AFzr
bgb+@aBn}xq0gwb2)Q)cq{30-g9B_L93G4|0
literal 0
HcmV?d1
diff --git a/tests/data/acpi/aarch64/virt/FACP.its_off b/tests/data/
acpi/aarch64/virt/FACP.its_off
new file mode 100644
index
..606dac3fe4b55c31fd68b25d3a4127eeef227434
GIT binary patch
literal 276
zcmZ>BbPf
Re: [PATCH-for-10.0 2/5] qtest/bios-tables-test: Whitelist aarch64/virt/APIC.its_off blob
On 2/4/25 08:43, Gustavo Romero wrote: Hi Phil, On 3/31/25 19:12, Philippe Mathieu-Daudé wrote: Prepare for ACPI table change in aarch64/virt/APIC.its_off. The comment could be smth like: Ignore APIC.its_off expected table (blob) for now until we update it later, after fixing the code that generates this table correctly. ? Signed-off-by: Philippe Mathieu-Daudé --- tests/qtest/bios-tables-test-allowed-diff.h | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/ qtest/bios-tables-test-allowed-diff.h index dfb8523c8bf..bfc4d601243 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,2 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/aarch64/virt/APIC.its_off", I think this patch should be merged into 1/2, accordingly to my comment in 1/5. FACP and IORT .its_off files should be added to the list as well. No, otherwise the test added in previous patch fails. Btw, IMHO the name of this header is a tad misleading, because actually "allowed-diff" means that "we allow the machine's table to be different from the tables listed in this header", so it doesn't look like an allowlist (whitelist), it works more like an ignore list? Cheers, Gustavo
Re: [PATCH-for-10.0 5/5] qtest/bios-tables-test: Update aarch64/virt/APIC.its_off blob
On 2/4/25 08:45, Gustavo Romero wrote: Hi Phil, On 3/31/25 19:12, Philippe Mathieu-Daudé wrote: Changes in the tables: @@ -1,32 +1,32 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20240927 (64-bit version) * Copyright (c) 2000 - 2023 Intel Corporation * * Disassembly of tests/data/acpi/aarch64/virt/APIC.its_off * * ACPI Data Table [APIC] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue (in hex) */ [000h 004h] Signature : "APIC" [Multiple APIC Description Table (MADT)] -[004h 0004 004h] Table Length : 00B8 +[004h 0004 004h] Table Length : 00A4 [008h 0008 001h] Revision : 04 -[009h 0009 001h] Checksum : A7 +[009h 0009 001h] Checksum : EE [00Ah 0010 006h] Oem ID : "BOCHS " [010h 0016 008h] Oem Table ID : "BXPC " [018h 0024 004h] Oem Revision : 0001 [01Ch 0028 004h] Asl Compiler ID : "BXPC" [020h 0032 004h] Asl Compiler Revision : 0001 [024h 0036 004h] Local Apic Address : [028h 0040 004h] Flags (decoded below) : PC-AT Compatibility : 0 [02Ch 0044 001h] Subtable Type : 0C [Generic Interrupt Distributor] [02Dh 0045 001h] Length : 18 [02Eh 0046 002h] Reserved : [030h 0048 004h] Local GIC Hardware ID : [034h 0052 008h] Base Address : 0800 [03Ch 0060 004h] Interrupt Base : @@ -49,37 +49,29 @@ [06Ch 0108 008h] Virtual GIC Base Address : [074h 0116 008h] Hypervisor GIC Base Address : [07Ch 0124 004h] Virtual GIC Interrupt : 0019 [080h 0128 008h] Redistributor Base Address : [088h 0136 008h] ARM MPIDR : [090h 0144 001h] Efficiency Class : 00 [091h 0145 001h] Reserved : 00 [092h 0146 002h] SPE Overflow Interrupt : [094h 0148 002h] TRBE Interrupt : 100E [094h 0148 001h] Subtable Type : 0E [Generic Interrupt Redistributor] [095h 0149 001h] Length : 10 [097h 0151 002h] Reserved : [098h 0152 008h] Base Address : 080A [0A0h 0160 004h] Length : 00F6 -[0A4h 0164 001h] Subtable Type : 0F [Generic Interrupt Translator] -[0A5h 0165 001h] Length : 14 -[0A7h 0167 002h] Reserved : -[0A8h 0168 004h] Translation ID : -[0ACh 0172 008h] Base Address : 0808 -[0B4h 0180 004h] Reserved : +Raw Table Data: Length 164 (0xA4) -Raw Table Data: Length 184 (0xB8) - - : 41 50 49 43 B8 00 00 00 04 A7 42 4F 43 48 53 20 // APIC..BOCHS + : 41 50 49 43 A4 00 00 00 04 EE 42 4F 43 48 53 20 // APIC..BOCHS 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC BXPC 0020: 01 00 00 00 00 00 00 00 00 00 00 00 0C 18 00 00 // 0030: 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 // 0040: 04 00 00 00 0B 50 00 00 00 00 00 00 00 00 00 00 // .P.. 0050: 01 00 00 00 00 00 00 00 17 00 00 00 00 00 00 00 // 0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // 0070: 00 00 00 00 00 00 00 00 00 00 00 00 19 00 00 00 // 0080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // 0090: 00 00 00 00 0E 10 00 00 00 00 0A 08 00 00 00 00 // - 00A0: 00 00 F6 00 0F 14 00 00 00 00 00 00 00 00 08 08 // - 00B0: 00 00 00 00 00 00 00 00 // + 00A0: 00 00 F6 00 // Signed-off-by: Philippe Mathieu-Daudé --- tests/qtest/bios-tables-test-allowed-diff.h | 1 - tests/data/acpi/aarch64/virt/APIC.its_off | Bin 184 -> 164 bytes 2 files changed, 1 deletion(-) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/ qtest/bios-tables-test-allowed-diff.h index bfc4d601243..dfb8523c8bf 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,2 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/aarch64/virt/APIC.its_off", diff --git a/tests/data/acpi/aarch64/virt/APIC.its_off b/tests/data/ acpi/aarch64/virt/APIC.its_off index c37d05d6e05805304f10afe73eb7cb9100f
Re: [PATCH v8 38/55] i386/tdx: Set and check kernel_irqchip mode for TDX
On Tue, Apr 01, 2025 at 09:01:48AM -0400, Xiaoyao Li wrote:
> KVM mandates kernel_irqchip to be split mode.
>
> Set it to split mode automatically when users don't provide an explicit
> value, otherwise check it to be the split mode.
>
> Suggested-by: Daniel P. Berrangé
> Signed-off-by: Xiaoyao Li
> ---
> target/i386/kvm/tdx.c | 8
> 1 file changed, 8 insertions(+)
Reviewed-by: Daniel P. Berrangé
> diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c
> index 0d30506c2021..4128f27d6b64 100644
> --- a/target/i386/kvm/tdx.c
> +++ b/target/i386/kvm/tdx.c
> @@ -16,6 +16,7 @@
> #include "qapi/error.h"
> #include "qom/object_interfaces.h"
> #include "crypto/hash.h"
> +#include "system/kvm_int.h"
> #include "system/runstate.h"
> #include "system/system.h"
> #include "exec/ramblock.h"
> @@ -390,6 +391,13 @@ static int tdx_kvm_init(ConfidentialGuestSupport *cgs,
> Error **errp)
> return -EINVAL;
> }
>
> +if (kvm_state->kernel_irqchip_split == ON_OFF_AUTO_AUTO ) {
Nitpick, no need for a space before the ')' ...
> +kvm_state->kernel_irqchip_split = ON_OFF_AUTO_ON;
> +} else if(kvm_state->kernel_irqchip_split != ON_OFF_AUTO_ON) {
..and need a space between 'if' and '('
> +error_setg(errp, "TDX VM requires kernel_irqchip to be split");
> +return -EINVAL;
> +}
> +
Note for self - 'tdx_kvm_init' is called by 'confidential_guest_kvm_init',
which is called by 'kvm_arch_init', which is called by 'kvm_init' *before*
it processes "kvm_state->kernel_irqchip_split == ON_OFF_AUTO_AUTO" to set
the default. So this change is correctly taking priority over the default
behaviour.
> if (!tdx_caps) {
> r = get_tdx_capabilities(errp);
> if (r) {
> --
> 2.34.1
>
With regards,
Daniel
--
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Re: [PATCH v8 55/55] docs: Add TDX documentation
CC libvirt / Jiri, for confirmation about whether the CPUID restrictions listed below will have any possible impact on libvirt CPUID handling... On Tue, Apr 01, 2025 at 09:02:05AM -0400, Xiaoyao Li wrote: > Add docs/system/i386/tdx.rst for TDX support, and add tdx in > confidential-guest-support.rst > > Signed-off-by: Xiaoyao Li > --- > Changes in v6: > - Add more information of "Feature configuration" > - Mark TD Attestation as future work because KVM now drops the support >of it. > > Changes in v5: > - Add TD attestation section and update the QEMU parameter; > > Changes since v1: > - Add prerequisite of private gmem; > - update example command to launch TD; > > Changes since RFC v4: > - add the restriction that kernel-irqchip must be split > --- > docs/system/confidential-guest-support.rst | 1 + > docs/system/i386/tdx.rst | 156 + > docs/system/target-i386.rst| 1 + > 3 files changed, 158 insertions(+) > create mode 100644 docs/system/i386/tdx.rst > +Feature Configuration > +- > + > +Unlike non-TDX VM, the CPU features (enumerated by CPU or MSR) of a TD are > not > +under full control of VMM. VMM can only configure part of features of a TD on > +``KVM_TDX_INIT_VM`` command of VM scope ``MEMORY_ENCRYPT_OP`` ioctl. > + > +The configurable features have three types: > + > +- Attributes: > + - PKS (bit 30) controls whether Supervisor Protection Keys is exposed to > TD, > + which determines related CPUID bit and CR4 bit; > + - PERFMON (bit 63) controls whether PMU is exposed to TD. > + > +- XSAVE related features (XFAM): > + XFAM is a 64b mask, which has the same format as XCR0 or IA32_XSS MSR. It > + determines the set of extended features available for use by the guest TD. > + > +- CPUID features: > + Only some bits of some CPUID leaves are directly configurable by VMM. > + > +What features can be configured is reported via TDX capabilities. > + > +TDX capabilities > + > + > +The VM scope ``MEMORY_ENCRYPT_OP`` ioctl provides command > ``KVM_TDX_CAPABILITIES`` > +to get the TDX capabilities from KVM. It returns a data structure of > +``struct kvm_tdx_capabilities``, which tells the supported configuration of > +attributes, XFAM and CPUIDs. > + > +TD attributes > +~ > + > +QEMU supports configuring raw 64-bit TD attributes directly via "attributes" > +property of "tdx-guest" object. Note, it's users' responsibility to provide a > +valid value because some bits may not supported by current QEMU or KVM yet. > + > +QEMU also supports the configuration of individual attribute bits that are > +supported by it, via properties of "tdx-guest" object. > +E.g., "sept-ve-disable" (bit 28). > + > +MSR based features > +~~ > + > +Current KVM doesn't support MSR based feature (e.g., > MSR_IA32_ARCH_CAPABILITIES) > +configuration for TDX, and it's a future work to enable it in QEMU when KVM > adds > +support of it. > + > +Feature check > +~ > + > +QEMU checks if the final (CPU) features, determined by given cpu model and > +explicit feature adjustment of "+featureA/-featureB", can be supported or > not. > +It can produce feature not supported warning like > + > + "warning: host doesn't support requested feature: CPUID.07H:EBX.intel-pt > [bit 25]" > + > +It can also produce warning like > + > + "warning: TDX forcibly sets the feature: CPUID.8007H:EDX.invtsc [bit > 8]" > + > +if the fixed-1 feature is requested to be disabled explicitly. This is newly > +added to QEMU for TDX because TDX has fixed-1 features that are forcibly > enabled > +by TDX module and VMM cannot disable them. This is where I'm wondering if libvirt has anything to be concerned about. Possibly when libvirt queries the actual CPUID after launching the guest it will just "do the right thing" ? Wondering if there's any need for libvirt to be aware of CPUID restrictions before that point though ? > + > +Launching a TD (TDX VM) > +--- > + > +To launch a TD, the necessary command line options are tdx-guest object and > +split kernel-irqchip, as below: > + > +.. parsed-literal:: > + > +|qemu_system_x86| \\ > +-object tdx-guest,id=tdx0 \\ > +-machine ...,kernel-irqchip=split,confidential-guest-support=tdx0 \\ > +-bios OVMF.fd \\ I don't think we need to show 'kernel-irqchip=split' now that we "do the right thing" by default This surely also ought to include '-accel kvm', as IIUC there's no TCG support for TDX. And presumably '-cpu host', since QEMU's default 'qemu64' CPU model is likely a terrible match for what TDX will force set. > + > +Restrictions > + > + > + - kernel-irqchip must be split; Can append "This is set by default for TDX guests if kernel-irqchip is left on its default 'auto' setting." > + > + - No readonly support for private memory; > + > + - No SMM support: SMM support requires manipulating the g
Re: [PATCH-for-10.0 3/5] hw/arm/virt-acpi: Factor its_enabled() helper out
Hi Phil,
On 3/31/25 19:12, Philippe Mathieu-Daudé wrote:
GIC ITS is checked for the MADT and IORT tables.
Factor the checks out to the its_enabled() helper.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/virt-acpi-build.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 3ac8f8e1786..fdc08b40883 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -208,6 +208,13 @@ static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineState
*vms)
#define ROOT_COMPLEX_ENTRY_SIZE 36
#define IORT_NODE_OFFSET 48
+static bool its_enabled(VirtMachineState *vms)
+{
+VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
+
+return its_class_name() && !vmc->no_its;
+}
+
Isn't its_class_name() always "true"?
Cheers,
Gustavo
/*
* Append an ID mapping entry as described by "Table 4 ID mapping format" in
* "IO Remapping Table System Software on ARM Platforms", Chapter 3.
@@ -670,7 +677,6 @@ static void
build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
{
int i;
-VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
const MemMapEntry *memmap = vms->memmap;
AcpiTable table = { .sig = "APIC", .rev = 4, .oem_id = vms->oem_id,
.oem_table_id = vms->oem_table_id };
@@ -741,7 +747,7 @@ build_madt(GArray *table_data, BIOSLinker *linker,
VirtMachineState *vms)
memmap[VIRT_HIGH_GIC_REDIST2].size);
}
-if (its_class_name() && !vmc->no_its) {
+if (its_enabled(vms)) {
/*
* ACPI spec, Revision 6.0 Errata A
* (original 6.0 definition has invalid Length)
@@ -973,7 +979,7 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables
*tables)
vms->oem_table_id);
}
-if (its_class_name() && !vmc->no_its) {
+if (its_enabled(vms)) {
acpi_add_table(table_offsets, tables_blob);
build_iort(tables_blob, tables->linker, vms);
}
Re: [PATCH v8 15/55] i386/tdx: Implement user specified tsc frequency
On Tue, Apr 01, 2025 at 09:01:25AM -0400, Xiaoyao Li wrote: > Reuse "-cpu,tsc-frequency=" to get user wanted tsc frequency and call VM > scope VM_SET_TSC_KHZ to set the tsc frequency of TD before KVM_TDX_INIT_VM. > > Besides, sanity check the tsc frequency to be in the legal range and > legal granularity (required by TDX module). > > Signed-off-by: Xiaoyao Li > Acked-by: Gerd Hoffmann > --- > Changes in v3: > - use @errp to report error info; (Daniel) > > Changes in v1: > - Use VM scope VM_SET_TSC_KHZ to set the TSC frequency of TD since KVM > side drop the @tsc_khz field in struct kvm_tdx_init_vm > --- > target/i386/kvm/kvm.c | 9 + > target/i386/kvm/tdx.c | 25 + > 2 files changed, 34 insertions(+) Reviewed-by: Daniel P. Berrangé With regards, Daniel -- |: https://berrange.com -o-https://www.flickr.com/photos/dberrange :| |: https://libvirt.org -o-https://fstop138.berrange.com :| |: https://entangle-photo.org-o-https://www.instagram.com/dberrange :|
Re: [PATCH for-10.1 v2 31/37] vfio: Rename vfio_get_dirty_bitmap()
On 26/03/2025 07:51, Cédric Le Goater wrote:
> vfio_container_query_dirty_bitmap() is consistent the VFIO container
> routine naming scheme and is now free to use.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Joao Martins
> ---
> include/hw/vfio/vfio-container-base.h | 4 ++--
> hw/vfio/common.c | 6 +++---
> hw/vfio/container-base.c | 5 +++--
> hw/vfio/container.c | 2 +-
> hw/vfio/trace-events | 2 +-
> 5 files changed, 10 insertions(+), 9 deletions(-)
>
> diff --git a/include/hw/vfio/vfio-container-base.h
> b/include/hw/vfio/vfio-container-base.h
> index
> 163d9b3c30b3093d2f40bb3d3ffc0314519ac285..a441932be779e5c6740da78f005ed2c8320e7cb2
> 100644
> --- a/include/hw/vfio/vfio-container-base.h
> +++ b/include/hw/vfio/vfio-container-base.h
> @@ -93,8 +93,8 @@ bool vfio_container_dirty_tracking_is_started(
> const VFIOContainerBase *bcontainer);
> bool vfio_container_devices_dirty_tracking_is_supported(
> const VFIOContainerBase *bcontainer);
> -int vfio_get_dirty_bitmap(const VFIOContainerBase *bcontainer, uint64_t iova,
> - uint64_t size, ram_addr_t ram_addr, Error **errp);
> +int vfio_container_query_dirty_bitmap(const VFIOContainerBase *bcontainer,
> +uint64_t iova, uint64_t size, ram_addr_t ram_addr, Error **errp);
>
> GList *vfio_container_get_iova_ranges(const VFIOContainerBase *bcontainer);
>
> diff --git a/hw/vfio/common.c b/hw/vfio/common.c
> index
> d063ea03c1cb4f475d421e626c703875fecd97a8..26ced6d4fb04b0dedf399686db40acaca5d85552
> 100644
> --- a/hw/vfio/common.c
> +++ b/hw/vfio/common.c
> @@ -1003,7 +1003,7 @@ static void vfio_iommu_map_dirty_notify(IOMMUNotifier
> *n, IOMMUTLBEntry *iotlb)
> goto out_unlock;
> }
>
> -ret = vfio_get_dirty_bitmap(bcontainer, iova, iotlb->addr_mask + 1,
> +ret = vfio_container_query_dirty_bitmap(bcontainer, iova,
> iotlb->addr_mask + 1,
> translated_addr, &local_err);
> if (ret) {
> error_prepend(&local_err,
> @@ -1040,7 +1040,7 @@ static int
> vfio_ram_discard_get_dirty_bitmap(MemoryRegionSection *section,
> * Sync the whole mapped region (spanning multiple individual mappings)
> * in one go.
> */
> -ret = vfio_get_dirty_bitmap(vrdl->bcontainer, iova, size, ram_addr,
> +ret = vfio_container_query_dirty_bitmap(vrdl->bcontainer, iova, size,
> ram_addr,
> &local_err);
> if (ret) {
> error_report_err(local_err);
> @@ -1134,7 +1134,7 @@ static int vfio_sync_dirty_bitmap(VFIOContainerBase
> *bcontainer,
> ram_addr = memory_region_get_ram_addr(section->mr) +
> section->offset_within_region;
>
> -return vfio_get_dirty_bitmap(bcontainer,
> +return vfio_container_query_dirty_bitmap(bcontainer,
>
> REAL_HOST_PAGE_ALIGN(section->offset_within_address_space),
> int128_get64(section->size), ram_addr,
> errp);
> }
> diff --git a/hw/vfio/container-base.c b/hw/vfio/container-base.c
> index
> 648dd25676e5b25a7c414109888b2796f890deac..a2e7a3b2e747d422f7a681fb09b1182e119c6d20
> 100644
> --- a/hw/vfio/container-base.c
> +++ b/hw/vfio/container-base.c
> @@ -237,7 +237,7 @@ static int
> vfio_container_devices_query_dirty_bitmap(const VFIOContainerBase *bc
> return 0;
> }
>
> -int vfio_get_dirty_bitmap(const VFIOContainerBase *bcontainer, uint64_t iova,
> +int vfio_container_query_dirty_bitmap(const VFIOContainerBase *bcontainer,
> uint64_t iova,
>uint64_t size, ram_addr_t ram_addr, Error **errp)
> {
> bool all_device_dirty_tracking =
> @@ -275,7 +275,8 @@ int vfio_get_dirty_bitmap(const VFIOContainerBase
> *bcontainer, uint64_t iova,
> dirty_pages = cpu_physical_memory_set_dirty_lebitmap(vbmap.bitmap,
> ram_addr,
> vbmap.pages);
>
> -trace_vfio_get_dirty_bitmap(iova, size, vbmap.size, ram_addr,
> dirty_pages);
> +trace_vfio_container_query_dirty_bitmap(iova, size, vbmap.size, ram_addr,
> +dirty_pages);
> out:
> g_free(vbmap.bitmap);
>
> diff --git a/hw/vfio/container.c b/hw/vfio/container.c
> index
> 9ea03ed618f6aefe35f966c644cbbc127ce7bf06..c74e08e531a501313cab27c57728a8c940d975be
> 100644
> --- a/hw/vfio/container.c
> +++ b/hw/vfio/container.c
> @@ -169,7 +169,7 @@ static int vfio_legacy_dma_unmap(const VFIOContainerBase
> *bcontainer,
> }
>
> if (need_dirty_sync) {
> -ret = vfio_get_dirty_bitmap(bcontainer, iova, size,
> +ret = vfio_container_query_dirty_bitmap(bcontainer, iova, size,
> iotlb->translated_addr, &local_err);
> if (ret) {
> error_report_err(local_err);
> diff --git a/hw/vfio/trace-events b/hw/vfio/trace-events
> index
> d4cd09cb0f93485fe06984346f6
Re: [PATCH for-10.1 v2 27/37] vfio: Make vfio_devices_query_dirty_bitmap() static
On 26/03/2025 07:51, Cédric Le Goater wrote:
> vfio_devices_query_dirty_bitmap() is only used in "container-base.c".
> Also, rename to vfio_container_devices_query_dirty_bitmap() to reflect
> with the prefix 'vfio_container_devices_' that it simply loops over
> the container's device list.
>
> This rename also frees the vfio_devices_query_dirty_bitmap() name
> which we will reuse in the next changes.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Joao Martins
> ---
> include/hw/vfio/vfio-container-base.h | 3 ---
> hw/vfio/container-base.c | 6 +++---
> 2 files changed, 3 insertions(+), 6 deletions(-)
>
> diff --git a/include/hw/vfio/vfio-container-base.h
> b/include/hw/vfio/vfio-container-base.h
> index
> 8575cdcb587dfe803808d452c7dc6c81241a47cf..1227771dd896b5917366ef578109b0ad92da2375
> 100644
> --- a/include/hw/vfio/vfio-container-base.h
> +++ b/include/hw/vfio/vfio-container-base.h
> @@ -93,9 +93,6 @@ int vfio_container_query_dirty_bitmap(const
> VFIOContainerBase *bcontainer,
> VFIOBitmap *vbmap, hwaddr iova, hwaddr size, Error
> **errp);
> bool vfio_devices_all_dirty_tracking_started(const VFIOContainerBase
> *bcontainer);
> bool vfio_devices_all_device_dirty_tracking(const VFIOContainerBase
> *bcontainer);
> -int vfio_devices_query_dirty_bitmap(const VFIOContainerBase *bcontainer,
> -VFIOBitmap *vbmap, hwaddr iova, hwaddr
> size,
> -Error **errp);
> int vfio_get_dirty_bitmap(const VFIOContainerBase *bcontainer, uint64_t iova,
>uint64_t size, ram_addr_t ram_addr, Error **errp);
>
> diff --git a/hw/vfio/container-base.c b/hw/vfio/container-base.c
> index
> 2844c5325efffade43022bfb517a43ac372c4125..4edbd39185375dee42ee6e6410da7b94635b5ab8
> 100644
> --- a/hw/vfio/container-base.c
> +++ b/hw/vfio/container-base.c
> @@ -214,7 +214,7 @@ static int vfio_device_dma_logging_report(VFIODevice
> *vbasedev, hwaddr iova,
> return 0;
> }
>
> -int vfio_devices_query_dirty_bitmap(const VFIOContainerBase *bcontainer,
> +static int vfio_container_devices_query_dirty_bitmap(const VFIOContainerBase
> *bcontainer,
> VFIOBitmap *vbmap, hwaddr iova, hwaddr size, Error **errp)
> {
> VFIODevice *vbasedev;
> @@ -260,8 +260,8 @@ int vfio_get_dirty_bitmap(const VFIOContainerBase
> *bcontainer, uint64_t iova,
> }
>
> if (all_device_dirty_tracking) {
> -ret = vfio_devices_query_dirty_bitmap(bcontainer, &vbmap, iova, size,
> - errp);
> +ret = vfio_container_devices_query_dirty_bitmap(bcontainer, &vbmap,
> iova, size,
> +errp);
> } else {
> ret = vfio_container_query_dirty_bitmap(bcontainer, &vbmap, iova,
> size,
> errp);
Re: [PATCH v1 21/22] test/qtest/hace: Support to validate 64-bit hmac key buffer addresses
On 3/21/25 10:26, Jamin Lin wrote:
Added "key" and "key_hi" fields to "AspeedMasks" for 64-bit addresses test.
Updated "aspeed_test_addresses" to validate "HACE_HASH_KEY_BUFF" and
"HACE_HASH_KEY_BUFF_HI".
Ensured correct masking of 64-bit addresses by checking both lower and upper
32-bit registers.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
tests/qtest/aspeed-hace-utils.h | 2 ++
tests/qtest/aspeed-hace-utils.c | 14 ++
tests/qtest/aspeed_hace-test.c | 4
3 files changed, 20 insertions(+)
diff --git a/tests/qtest/aspeed-hace-utils.h b/tests/qtest/aspeed-hace-utils.h
index de8055a1db..c8b2ec45af 100644
--- a/tests/qtest/aspeed-hace-utils.h
+++ b/tests/qtest/aspeed-hace-utils.h
@@ -50,9 +50,11 @@ struct AspeedSgList {
struct AspeedMasks {
uint32_t src;
uint32_t dest;
+uint32_t key;
uint32_t len;
uint32_t src_hi;
uint32_t dest_hi;
+uint32_t key_hi;
};
void aspeed_test_md5(const char *machine, const uint32_t base,
diff --git a/tests/qtest/aspeed-hace-utils.c b/tests/qtest/aspeed-hace-utils.c
index fc209353f3..a5ece614ed 100644
--- a/tests/qtest/aspeed-hace-utils.c
+++ b/tests/qtest/aspeed-hace-utils.c
@@ -591,6 +591,8 @@ void aspeed_test_addresses(const char *machine, const
uint32_t base,
g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC_HI), ==, 0);
g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), ==, 0);
g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST_HI), ==, 0);
+g_assert_cmphex(qtest_readl(s, base + HACE_HASH_KEY_BUFF), ==, 0);
+g_assert_cmphex(qtest_readl(s, base + HACE_HASH_KEY_BUFF_HI), ==, 0);
g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), ==, 0);
/* Check that the address masking is correct */
@@ -609,6 +611,14 @@ void aspeed_test_addresses(const char *machine, const
uint32_t base,
g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST_HI), ==,
expected->dest_hi);
+qtest_writel(s, base + HACE_HASH_KEY_BUFF, 0x);
+g_assert_cmphex(qtest_readl(s, base + HACE_HASH_KEY_BUFF), ==,
+expected->key);
+
+qtest_writel(s, base + HACE_HASH_KEY_BUFF_HI, 0x);
+g_assert_cmphex(qtest_readl(s, base + HACE_HASH_KEY_BUFF_HI), ==,
+expected->key_hi);
+
qtest_writel(s, base + HACE_HASH_DATA_LEN, 0x);
g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), ==,
expected->len);
@@ -618,6 +628,8 @@ void aspeed_test_addresses(const char *machine, const
uint32_t base,
qtest_writel(s, base + HACE_HASH_SRC_HI, 0);
qtest_writel(s, base + HACE_HASH_DIGEST, 0);
qtest_writel(s, base + HACE_HASH_DIGEST_HI, 0);
+qtest_writel(s, base + HACE_HASH_KEY_BUFF, 0);
+qtest_writel(s, base + HACE_HASH_KEY_BUFF_HI, 0);
qtest_writel(s, base + HACE_HASH_DATA_LEN, 0);
/* Check that all bits are now zero */
@@ -625,6 +637,8 @@ void aspeed_test_addresses(const char *machine, const
uint32_t base,
g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC_HI), ==, 0);
g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), ==, 0);
g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST_HI), ==, 0);
+g_assert_cmphex(qtest_readl(s, base + HACE_HASH_KEY_BUFF), ==, 0);
+g_assert_cmphex(qtest_readl(s, base + HACE_HASH_KEY_BUFF_HI), ==, 0);
g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), ==, 0);
qtest_quit(s);
diff --git a/tests/qtest/aspeed_hace-test.c b/tests/qtest/aspeed_hace-test.c
index 31890d574e..38777020ca 100644
--- a/tests/qtest/aspeed_hace-test.c
+++ b/tests/qtest/aspeed_hace-test.c
@@ -13,24 +13,28 @@
static const struct AspeedMasks ast1030_masks = {
.src = 0x7fff,
.dest = 0x7ff8,
+.key = 0x7ff8,
.len = 0x0fff,
};
static const struct AspeedMasks ast2600_masks = {
.src = 0x7fff,
.dest = 0x7ff8,
+.key = 0x7ff8,
.len = 0x0fff,
};
static const struct AspeedMasks ast2500_masks = {
.src = 0x3fff,
.dest = 0x3ff8,
+.key = 0x3fc0,
.len = 0x0fff,
};
static const struct AspeedMasks ast2400_masks = {
.src = 0x0fff,
.dest = 0x0ff8,
+.key = 0x0fc0,
.len = 0x0fff,
};
Re: [PATCH v8 17/55] i386/tdvf: Introduce function to parse TDVF metadata
On Tue, Apr 01, 2025 at 09:01:27AM -0400, Xiaoyao Li wrote:
> From: Isaku Yamahata
>
> TDX VM needs to boot with its specialized firmware, Trusted Domain
> Virtual Firmware (TDVF). QEMU needs to parse TDVF and map it in TD
> guest memory prior to running the TDX VM.
>
> A TDVF Metadata in TDVF image describes the structure of firmware.
> QEMU refers to it to setup memory for TDVF. Introduce function
> tdvf_parse_metadata() to parse the metadata from TDVF image and store
> the info of each TDVF section.
>
> TDX metadata is located by a TDX metadata offset block, which is a
> GUID-ed structure. The data portion of the GUID structure contains
> only an 4-byte field that is the offset of TDX metadata to the end
> of firmware file.
>
> Select X86_FW_OVMF when TDX is enable to leverage existing functions
> to parse and search OVMF's GUID-ed structures.
>
> Signed-off-by: Isaku Yamahata
> Co-developed-by: Xiaoyao Li
> Signed-off-by: Xiaoyao Li
> Acked-by: Gerd Hoffmann
> ---
> Changes in v8:
> - Drop the failure handling of memcpy() since it cannot fail;
>
> Changes in v7:
> - Update license info to only use SPDX tag;
> - use g_autofree to avoid manually free;
>
> Changes in v6:
> - Drop the the data endianness change for metadata->Length;
>
> Changes in v1:
> - rename tdvf_parse_section_entry() to
>tdvf_parse_and_check_section_entry()
>
> Changes in RFC v4:
> - rename TDX_METADATA_GUID to TDX_METADATA_OFFSET_GUID
> ---
> hw/i386/Kconfig| 1 +
> hw/i386/meson.build| 1 +
> hw/i386/tdvf.c | 183 +
> include/hw/i386/tdvf.h | 38 +
> 4 files changed, 223 insertions(+)
> create mode 100644 hw/i386/tdvf.c
> create mode 100644 include/hw/i386/tdvf.h
>
> diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig
> index cce9521ba934..eb65bda6e071 100644
> --- a/hw/i386/Kconfig
> +++ b/hw/i386/Kconfig
> @@ -12,6 +12,7 @@ config SGX
>
> config TDX
> bool
> +select X86_FW_OVMF
> depends on KVM
>
> config PC
> diff --git a/hw/i386/meson.build b/hw/i386/meson.build
> index 10bdfde27c69..3bc1da2b6eb4 100644
> --- a/hw/i386/meson.build
> +++ b/hw/i386/meson.build
> @@ -32,6 +32,7 @@ i386_ss.add(when: 'CONFIG_PC', if_true: files(
>'port92.c'))
> i386_ss.add(when: 'CONFIG_X86_FW_OVMF', if_true: files('pc_sysfw_ovmf.c'),
> if_false:
> files('pc_sysfw_ovmf-stubs.c'))
> +i386_ss.add(when: 'CONFIG_TDX', if_true: files('tdvf.c'))
>
> subdir('kvm')
> subdir('xen')
> diff --git a/hw/i386/tdvf.c b/hw/i386/tdvf.c
> new file mode 100644
> index ..328d1b7ffdf8
> --- /dev/null
> +++ b/hw/i386/tdvf.c
> @@ -0,0 +1,183 @@
> +/*
> + * Copyright (c) 2025 Intel Corporation
> + * Author: Isaku Yamahata
> + *
> + * Xiaoyao Li
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/error-report.h"
> +
> +#include "hw/i386/pc.h"
> +#include "hw/i386/tdvf.h"
> +#include "system/kvm.h"
> +
> +#define TDX_METADATA_OFFSET_GUID"e47a6535-984a-4798-865e-4685a7bf8ec2"
> +#define TDX_METADATA_VERSION1
> +#define TDVF_SIGNATURE 0x46564454 /* TDVF as little endian */
> +
> +typedef struct {
> +uint32_t DataOffset;
> +uint32_t RawDataSize;
> +uint64_t MemoryAddress;
> +uint64_t MemoryDataSize;
> +uint32_t Type;
> +uint32_t Attributes;
> +} TdvfSectionEntry;
> +
> +typedef struct {
> +uint32_t Signature;
> +uint32_t Length;
> +uint32_t Version;
> +uint32_t NumberOfSectionEntries;
> +TdvfSectionEntry SectionEntries[];
> +} TdvfMetadata;
struct field names starting with an initial capital is
not the usual QEMU code style. Can this be all initial
lowercase, with capital just for word separation.
> +
> +struct tdx_metadata_offset {
> +uint32_t offset;
> +};
> +
With regards,
Daniel
--
|: https://berrange.com -o-https://www.flickr.com/photos/dberrange :|
|: https://libvirt.org -o-https://fstop138.berrange.com :|
|: https://entangle-photo.org-o-https://www.instagram.com/dberrange :|
Re: [PATCH v8 36/55] i386/tdx: Disable SMM for TDX VMs
On Tue, Apr 01, 2025 at 09:01:46AM -0400, Xiaoyao Li wrote: > TDX doesn't support SMM and VMM cannot emulate SMM for TDX VMs because > VMM cannot manipulate TDX VM's memory. > > Disable SMM for TDX VMs and error out if user requests to enable SMM. > > Signed-off-by: Xiaoyao Li > Acked-by: Gerd Hoffmann > --- > target/i386/kvm/tdx.c | 9 + > 1 file changed, 9 insertions(+) Reviewed-by: Daniel P. Berrangé With regards, Daniel -- |: https://berrange.com -o-https://www.flickr.com/photos/dberrange :| |: https://libvirt.org -o-https://fstop138.berrange.com :| |: https://entangle-photo.org-o-https://www.instagram.com/dberrange :|
Re: [PATCH v8 37/55] i386/tdx: Disable PIC for TDX VMs
On Tue, Apr 01, 2025 at 09:01:47AM -0400, Xiaoyao Li wrote: > Legacy PIC (8259) cannot be supported for TDX VMs since TDX module > doesn't allow directly interrupt injection. Using posted interrupts > for the PIC is not a viable option as the guest BIOS/kernel will not > do EOI for PIC IRQs, i.e. will leave the vIRR bit set. > > Hence disable PIC for TDX VMs and error out if user wants PIC. > > Signed-off-by: Xiaoyao Li > Acked-by: Gerd Hoffmann > --- > target/i386/kvm/tdx.c | 7 +++ > 1 file changed, 7 insertions(+) Reviewed-by: Daniel P. Berrangé With regards, Daniel -- |: https://berrange.com -o-https://www.flickr.com/photos/dberrange :| |: https://libvirt.org -o-https://fstop138.berrange.com :| |: https://entangle-photo.org-o-https://www.instagram.com/dberrange :|
Re: [PATCH v2 20/30] target/arm/cpu: always define kvm related registers
On 4/2/25 06:36, Philippe Mathieu-Daudé wrote:
On 25/3/25 02:24, Richard Henderson wrote:
On 3/24/25 14:11, Pierrick Bouvier wrote:
On 3/23/25 12:37, Richard Henderson wrote:
On 3/20/25 15:29, Pierrick Bouvier wrote:
This does not hurt, even if they are not used.
Signed-off-by: Pierrick Bouvier
---
target/arm/cpu.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index a8a1a8faf6b..ab7412772bc 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -971,7 +971,6 @@ struct ArchCPU {
*/
uint32_t kvm_target;
-#ifdef CONFIG_KVM
/* KVM init features for this CPU */
uint32_t kvm_init_features[7];
@@ -984,7 +983,6 @@ struct ArchCPU {
/* KVM steal time */
OnOffAuto kvm_steal_time;
-#endif /* CONFIG_KVM */
/* Uniprocessor system with MP extensions */
bool mp_is_up;
I'm not sure what this achieves? CONFIG_KVM is a configure-time
selection.
CONFIG_KVM is a poisoned identifier.
It's included via config-target.h, and not config-host.h.
Whoops, yes.
If we go this way, can we consistently allow CONFIG_${HW_ACCEL}
(read "remove poisoned defs in config-poison.h)?
It would be safe to do this for CONFIG_TCG, which is applied to all
compilation units (through config_host). And we'll do it when we meet a
case that really needs it, not before. As long as the code can be
cleaned up from those ifdefs, it's better.
However, it's not safe for all other CONFIG_${HW_ACCEL}, which are
applied selectively on some targets (basically, for the pair {host ==
target}, when host supports this acceleration).
For them, the right fix is to make sure we call "{accel}_enabled()",
expose the associated code, and eventually deal with missing symbols at
link.
Re: [PULL 04/23] include/exec: Split out exec/cpu-interrupt.h
Hi Richard, On 8/3/25 23:58, Richard Henderson wrote: Some of these bits are actually common to all cpus; while the reset have common reservations for target-specific usage. While generic code cannot know what the target-specific usage is, common code can know what to do with the bits, e.g. single-step. Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 53 +-- include/exec/cpu-interrupt.h | 70 include/exec/poison.h| 13 --- 3 files changed, 71 insertions(+), 65 deletions(-) create mode 100644 include/exec/cpu-interrupt.h diff --git a/include/exec/poison.h b/include/exec/poison.h index 35721366d7..8ed04b3108 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -46,19 +46,6 @@ #pragma GCC poison TARGET_PHYS_ADDR_SPACE_BITS -#pragma GCC poison CPU_INTERRUPT_HARD -#pragma GCC poison CPU_INTERRUPT_EXITTB -#pragma GCC poison CPU_INTERRUPT_HALT -#pragma GCC poison CPU_INTERRUPT_DEBUG -#pragma GCC poison CPU_INTERRUPT_TGT_EXT_0 -#pragma GCC poison CPU_INTERRUPT_TGT_EXT_1 -#pragma GCC poison CPU_INTERRUPT_TGT_EXT_2 -#pragma GCC poison CPU_INTERRUPT_TGT_EXT_3 -#pragma GCC poison CPU_INTERRUPT_TGT_EXT_4 -#pragma GCC poison CPU_INTERRUPT_TGT_INT_0 -#pragma GCC poison CPU_INTERRUPT_TGT_INT_1 -#pragma GCC poison CPU_INTERRUPT_TGT_INT_2 If I understood correctly yesterday's discussion, these definitions are internal to target/ and shouldn't be used by hw/ at all. If this is right, then we need to keep them poisoned for hw/ code.
Re: [PATCH v8 05/55] i386/tdx: Get tdx_capabilities via KVM_TDX_CAPABILITIES
On Tue, Apr 01, 2025 at 09:01:15AM -0400, Xiaoyao Li wrote:
> KVM provides TDX capabilities via sub command KVM_TDX_CAPABILITIES of
> IOCTL(KVM_MEMORY_ENCRYPT_OP). Get the capabilities when initializing
> TDX context. It will be used to validate user's setting later.
>
> Since there is no interface reporting how many cpuid configs contains in
> KVM_TDX_CAPABILITIES, QEMU chooses to try starting with a known number
> and abort when it exceeds KVM_MAX_CPUID_ENTRIES.
>
> Besides, introduce the interfaces to invoke TDX "ioctls" at VCPU scope
> in preparation.
>
> Signed-off-by: Xiaoyao Li
> ---
> Changes in v7:
> - refine and unifiy the error handling; (Daniel)
>
> Changes in v6:
> - Pass CPUState * to tdx_vcpu_ioctl();
> - update commit message to remove platform scope thing;
> - dump hw_error when it's non-zero to help debug;
>
> Changes in v4:
> - use {} to initialize struct kvm_tdx_cmd, to avoid memset();
> - remove tdx_platform_ioctl() because no user;
>
> Changes in v3:
> - rename __tdx_ioctl() to tdx_ioctl_internal()
> - Pass errp in get_tdx_capabilities();
>
> changes in v2:
> - Make the error message more clear;
>
> changes in v1:
> - start from nr_cpuid_configs = 6 for the loop;
> - stop the loop when nr_cpuid_configs exceeds KVM_MAX_CPUID_ENTRIES;
> ---
> target/i386/kvm/kvm.c | 2 -
> target/i386/kvm/kvm_i386.h | 2 +
> target/i386/kvm/tdx.c | 107 -
> 3 files changed, 108 insertions(+), 3 deletions(-)
>
> diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
> index 1af4710556ad..b4fa35405fe1 100644
> --- a/target/i386/kvm/kvm.c
> +++ b/target/i386/kvm/kvm.c
> @@ -1779,8 +1779,6 @@ static int hyperv_init_vcpu(X86CPU *cpu)
>
> static Error *invtsc_mig_blocker;
>
> -#define KVM_MAX_CPUID_ENTRIES 100
> -
> static void kvm_init_xsave(CPUX86State *env)
> {
> if (has_xsave2) {
> diff --git a/target/i386/kvm/kvm_i386.h b/target/i386/kvm/kvm_i386.h
> index 88565e8dbac1..ed1e61fb8ba9 100644
> --- a/target/i386/kvm/kvm_i386.h
> +++ b/target/i386/kvm/kvm_i386.h
> @@ -13,6 +13,8 @@
>
> #include "system/kvm.h"
>
> +#define KVM_MAX_CPUID_ENTRIES 100
> +
> /* always false if !CONFIG_KVM */
> #define kvm_pit_in_kernel() \
> (kvm_irqchip_in_kernel() && !kvm_irqchip_is_split())
> diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c
> index 4ff94860815d..c67be5e618e2 100644
> --- a/target/i386/kvm/tdx.c
> +++ b/target/i386/kvm/tdx.c
> @@ -10,17 +10,122 @@
> */
>
> #include "qemu/osdep.h"
> +#include "qemu/error-report.h"
> +#include "qapi/error.h"
> #include "qom/object_interfaces.h"
>
> #include "hw/i386/x86.h"
> #include "kvm_i386.h"
> #include "tdx.h"
>
> +static struct kvm_tdx_capabilities *tdx_caps;
> +
> +enum tdx_ioctl_level {
> +TDX_VM_IOCTL,
> +TDX_VCPU_IOCTL,
> +};
> +
> +static int tdx_ioctl_internal(enum tdx_ioctl_level level, void *state,
> + int cmd_id, __u32 flags, void *data,
> + Error **errp)
> +{
> +struct kvm_tdx_cmd tdx_cmd = {};
> +int r;
> +
> +const char *tdx_ioctl_name[] = {
> +[KVM_TDX_CAPABILITIES] = "KVM_TDX_CAPABILITIES",
> +[KVM_TDX_INIT_VM] = "KVM_TDX_INIT_VM",
> +[KVM_TDX_INIT_VCPU] = "KVM_TDX_INIT_VCPU",
> +[KVM_TDX_INIT_MEM_REGION] = "KVM_TDX_INIT_MEM_REGION",
> +[KVM_TDX_FINALIZE_VM] = "KVM_TDX_FINALIZE_VM",
> +[KVM_TDX_GET_CPUID] = "KVM_TDX_GET_CPUID",
> +};
> +
> +tdx_cmd.id = cmd_id;
> +tdx_cmd.flags = flags;
> +tdx_cmd.data = (__u64)(unsigned long)data;
> +
> +switch (level) {
> +case TDX_VM_IOCTL:
> +r = kvm_vm_ioctl(kvm_state, KVM_MEMORY_ENCRYPT_OP, &tdx_cmd);
> +break;
> +case TDX_VCPU_IOCTL:
> +r = kvm_vcpu_ioctl(state, KVM_MEMORY_ENCRYPT_OP, &tdx_cmd);
> +break;
> +default:
> +error_setg(errp, "Invalid tdx_ioctl_level %d", level);
> +return -EINVAL;
> +}
> +
> +if (r < 0) {
> +error_setg_errno(errp, -r, "TDX ioctl %s failed, hw_errors: 0x%llx",
> + tdx_ioctl_name[cmd_id], tdx_cmd.hw_error);
> +}
> +return r;
> +}
> +
> +static inline int tdx_vm_ioctl(int cmd_id, __u32 flags, void *data,
> + Error **errp)
> +{
> +return tdx_ioctl_internal(TDX_VM_IOCTL, NULL, cmd_id, flags, data, errp);
> +}
> +
> +static inline int tdx_vcpu_ioctl(CPUState *cpu, int cmd_id, __u32 flags,
> + void *data, Error **errp)
> +{
> +return tdx_ioctl_internal(TDX_VCPU_IOCTL, cpu, cmd_id, flags, data,
> errp);
> +}
> +
> +static int get_tdx_capabilities(Error **errp)
> +{
> +struct kvm_tdx_capabilities *caps;
> +/* 1st generation of TDX reports 6 cpuid configs */
> +int nr_cpuid_configs = 6;
> +size_t size;
> +int r;
> +
> +do {
> +Error *local_err = NULL;
> +size = sizeof(struct kvm_tdx_capabilities) +
> + n
Re: [PATCH v3 2/3] include: Add a header to define host PCI MMIO functions
On Tue, Apr 01, 2025 at 10:22:45AM -0700, Farhan Ali wrote: > Add a generic API for host PCI MMIO reads/writes > (e.g. Linux VFIO BAR accesses). The functions access > little endian memory and returns the result in > host cpu endianness. > > Reviewed-by: Philippe Mathieu-Daudé > Signed-off-by: Farhan Ali > --- > include/qemu/host-pci-mmio.h | 116 +++ > 1 file changed, 116 insertions(+) > create mode 100644 include/qemu/host-pci-mmio.h Reviewed-by: Stefan Hajnoczi signature.asc Description: PGP signature
Re: [PATCH v8 05/55] i386/tdx: Get tdx_capabilities via KVM_TDX_CAPABILITIES
On 4/2/2025 7:00 PM, Daniel P. Berrangé wrote:
On Tue, Apr 01, 2025 at 09:01:15AM -0400, Xiaoyao Li wrote:
KVM provides TDX capabilities via sub command KVM_TDX_CAPABILITIES of
IOCTL(KVM_MEMORY_ENCRYPT_OP). Get the capabilities when initializing
TDX context. It will be used to validate user's setting later.
Since there is no interface reporting how many cpuid configs contains in
KVM_TDX_CAPABILITIES, QEMU chooses to try starting with a known number
and abort when it exceeds KVM_MAX_CPUID_ENTRIES.
Besides, introduce the interfaces to invoke TDX "ioctls" at VCPU scope
in preparation.
Signed-off-by: Xiaoyao Li
---
Changes in v7:
- refine and unifiy the error handling; (Daniel)
Changes in v6:
- Pass CPUState * to tdx_vcpu_ioctl();
- update commit message to remove platform scope thing;
- dump hw_error when it's non-zero to help debug;
Changes in v4:
- use {} to initialize struct kvm_tdx_cmd, to avoid memset();
- remove tdx_platform_ioctl() because no user;
Changes in v3:
- rename __tdx_ioctl() to tdx_ioctl_internal()
- Pass errp in get_tdx_capabilities();
changes in v2:
- Make the error message more clear;
changes in v1:
- start from nr_cpuid_configs = 6 for the loop;
- stop the loop when nr_cpuid_configs exceeds KVM_MAX_CPUID_ENTRIES;
---
target/i386/kvm/kvm.c | 2 -
target/i386/kvm/kvm_i386.h | 2 +
target/i386/kvm/tdx.c | 107 -
3 files changed, 108 insertions(+), 3 deletions(-)
diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
index 1af4710556ad..b4fa35405fe1 100644
--- a/target/i386/kvm/kvm.c
+++ b/target/i386/kvm/kvm.c
@@ -1779,8 +1779,6 @@ static int hyperv_init_vcpu(X86CPU *cpu)
static Error *invtsc_mig_blocker;
-#define KVM_MAX_CPUID_ENTRIES 100
-
static void kvm_init_xsave(CPUX86State *env)
{
if (has_xsave2) {
diff --git a/target/i386/kvm/kvm_i386.h b/target/i386/kvm/kvm_i386.h
index 88565e8dbac1..ed1e61fb8ba9 100644
--- a/target/i386/kvm/kvm_i386.h
+++ b/target/i386/kvm/kvm_i386.h
@@ -13,6 +13,8 @@
#include "system/kvm.h"
+#define KVM_MAX_CPUID_ENTRIES 100
+
/* always false if !CONFIG_KVM */
#define kvm_pit_in_kernel() \
(kvm_irqchip_in_kernel() && !kvm_irqchip_is_split())
diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c
index 4ff94860815d..c67be5e618e2 100644
--- a/target/i386/kvm/tdx.c
+++ b/target/i386/kvm/tdx.c
@@ -10,17 +10,122 @@
*/
#include "qemu/osdep.h"
+#include "qemu/error-report.h"
+#include "qapi/error.h"
#include "qom/object_interfaces.h"
#include "hw/i386/x86.h"
#include "kvm_i386.h"
#include "tdx.h"
+static struct kvm_tdx_capabilities *tdx_caps;
+
+enum tdx_ioctl_level {
+TDX_VM_IOCTL,
+TDX_VCPU_IOCTL,
+};
+
+static int tdx_ioctl_internal(enum tdx_ioctl_level level, void *state,
+ int cmd_id, __u32 flags, void *data,
+ Error **errp)
+{
+struct kvm_tdx_cmd tdx_cmd = {};
+int r;
+
+const char *tdx_ioctl_name[] = {
+[KVM_TDX_CAPABILITIES] = "KVM_TDX_CAPABILITIES",
+[KVM_TDX_INIT_VM] = "KVM_TDX_INIT_VM",
+[KVM_TDX_INIT_VCPU] = "KVM_TDX_INIT_VCPU",
+[KVM_TDX_INIT_MEM_REGION] = "KVM_TDX_INIT_MEM_REGION",
+[KVM_TDX_FINALIZE_VM] = "KVM_TDX_FINALIZE_VM",
+[KVM_TDX_GET_CPUID] = "KVM_TDX_GET_CPUID",
+};
+
+tdx_cmd.id = cmd_id;
+tdx_cmd.flags = flags;
+tdx_cmd.data = (__u64)(unsigned long)data;
+
+switch (level) {
+case TDX_VM_IOCTL:
+r = kvm_vm_ioctl(kvm_state, KVM_MEMORY_ENCRYPT_OP, &tdx_cmd);
+break;
+case TDX_VCPU_IOCTL:
+r = kvm_vcpu_ioctl(state, KVM_MEMORY_ENCRYPT_OP, &tdx_cmd);
+break;
+default:
+error_setg(errp, "Invalid tdx_ioctl_level %d", level);
+return -EINVAL;
+}
+
+if (r < 0) {
+error_setg_errno(errp, -r, "TDX ioctl %s failed, hw_errors: 0x%llx",
+ tdx_ioctl_name[cmd_id], tdx_cmd.hw_error);
+}
+return r;
+}
+
+static inline int tdx_vm_ioctl(int cmd_id, __u32 flags, void *data,
+ Error **errp)
+{
+return tdx_ioctl_internal(TDX_VM_IOCTL, NULL, cmd_id, flags, data, errp);
+}
+
+static inline int tdx_vcpu_ioctl(CPUState *cpu, int cmd_id, __u32 flags,
+ void *data, Error **errp)
+{
+return tdx_ioctl_internal(TDX_VCPU_IOCTL, cpu, cmd_id, flags, data, errp);
+}
+
+static int get_tdx_capabilities(Error **errp)
+{
+struct kvm_tdx_capabilities *caps;
+/* 1st generation of TDX reports 6 cpuid configs */
+int nr_cpuid_configs = 6;
+size_t size;
+int r;
+
+do {
+Error *local_err = NULL;
+size = sizeof(struct kvm_tdx_capabilities) +
+ nr_cpuid_configs * sizeof(struct kvm_cpuid_entry2);
+caps = g_malloc0(size);
+caps->cpuid.nent = nr_cpuid_configs;
+
+r = tdx_vm_ioctl(KVM_TDX_CAPABILITIES, 0, caps, &local_err);
+if (r == -E2BIG
[PATCH v1 0/1] hw/misc/aspeed_sbc: Implement OTP memory and controller
This patch introduces part of the Secure Boot Controller device, which consists of several sub-components, including an OTP memory, OTP controller, cryptographic engine, and boot controller. In this version, the implementation includes the OTP memory and its controller. The OTP memory can be programmed from within the guest OS via a software utility. Kane-Chen-AS (1): hw/misc/aspeed_sbc: Implement OTP memory and controller hw/misc/aspeed_sbc.c | 304 +++ include/hw/misc/aspeed_sbc.h | 14 ++ 2 files changed, 318 insertions(+) -- 2.43.0
Re: [PATCH v8 13/55] i386/tdx: Support user configurable mrconfigid/mrowner/mrownerconfig
On Tue, Apr 01, 2025 at 09:01:23AM -0400, Xiaoyao Li wrote:
> From: Isaku Yamahata
>
> Three sha384 hash values, mrconfigid, mrowner and mrownerconfig, of a TD
> can be provided for TDX attestation. Detailed meaning of them can be
> found:
> https://lore.kernel.org/qemu-devel/31d6dbc1-f453-4cef-ab08-4813f4e0f...@intel.com/
>
> Allow user to specify those values via property mrconfigid, mrowner and
> mrownerconfig. They are all in base64 format.
>
> example
> -object tdx-guest, \
>
> mrconfigid=ASNFZ4mrze8BI0VniavN7wEjRWeJq83vASNFZ4mrze8BI0VniavN7wEjRWeJq83v,\
> mrowner=ASNFZ4mrze8BI0VniavN7wEjRWeJq83vASNFZ4mrze8BI0VniavN7wEjRWeJq83v,\
>
> mrownerconfig=ASNFZ4mrze8BI0VniavN7wEjRWeJq83vASNFZ4mrze8BI0VniavN7wEjRWeJq83v
>
> Signed-off-by: Isaku Yamahata
> Co-developed-by: Xiaoyao Li
> Signed-off-by: Xiaoyao Li
> ---
> Changes in v8:
> - it gets squashed into previous patch in v7. So split it out in v8;
>
> Changes in v6:
> - refine the doc comment of QAPI properties;
>
> Changes in v5:
> - refine the description of QAPI properties and add description of
>default value when not specified;
>
> Changes in v4:
> - describe more of there fields in qom.json
> - free the old value before set new value to avoid memory leak in
>_setter(); (Daniel)
>
> Changes in v3:
> - use base64 encoding instread of hex-string;
> ---
> qapi/qom.json | 16 +++-
> target/i386/kvm/tdx.c | 86 +++
> target/i386/kvm/tdx.h | 3 ++
> 3 files changed, 104 insertions(+), 1 deletion(-)
> diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c
> index aa043acb1a88..77ddb2655c53 100644
> --- a/target/i386/kvm/tdx.c
> +++ b/target/i386/kvm/tdx.c
> @@ -11,8 +11,10 @@
>
> #include "qemu/osdep.h"
> #include "qemu/error-report.h"
> +#include "qemu/base64.h"
> #include "qapi/error.h"
> #include "qom/object_interfaces.h"
> +#include "crypto/hash.h"
>
> #include "hw/i386/x86.h"
> #include "kvm_i386.h"
> @@ -239,6 +241,7 @@ int tdx_pre_create_vcpu(CPUState *cpu, Error **errp)
> CPUX86State *env = &x86cpu->env;
> g_autofree struct kvm_tdx_init_vm *init_vm = NULL;
> Error *local_err = NULL;
> +size_t data_len;
> int retry = 1;
> int r = 0;
>
> @@ -250,6 +253,36 @@ int tdx_pre_create_vcpu(CPUState *cpu, Error **errp)
> init_vm = g_malloc0(sizeof(struct kvm_tdx_init_vm) +
> sizeof(struct kvm_cpuid_entry2) *
> KVM_MAX_CPUID_ENTRIES);
>
> +if (tdx_guest->mrconfigid) {
> +g_autofree uint8_t *data = qbase64_decode(tdx_guest->mrconfigid,
> + strlen(tdx_guest->mrconfigid), &data_len,
> errp);
> +if (!data || data_len != QCRYPTO_HASH_DIGEST_LEN_SHA384) {
> +error_setg(errp, "TDX: failed to decode mrconfigid");
> +return -1;
> +}
When '!data', qbase64_decode will have already filled 'errp' with
details, so we must immediately 'return -1', as a repeated error_setg
call is an programming error.
The error_setg call should only be done in response to failing
the 'data_len' check and the message should specify the lengths
eg more like this
if (!data) {
return -1;
}
if (data_len != QCRYPTO_HASH_DIGEST_LEN_SHA384) {
error_setg(errp, "TDX mrconfigid len %d must match SHA384 digest len %d",
data_len, QCRYPTO_HASH_DIGEST_LEN_SHA384)
return -1;
}
> +memcpy(init_vm->mrconfigid, data, data_len);
> +}
> +
> +if (tdx_guest->mrowner) {
> +g_autofree uint8_t *data = qbase64_decode(tdx_guest->mrowner,
> + strlen(tdx_guest->mrowner), &data_len, errp);
> +if (!data || data_len != QCRYPTO_HASH_DIGEST_LEN_SHA384) {
> +error_setg(errp, "TDX: failed to decode mrowner");
> +return -1;
> +}
> +memcpy(init_vm->mrowner, data, data_len);
> +}
> +
> +if (tdx_guest->mrownerconfig) {
> +g_autofree uint8_t *data = qbase64_decode(tdx_guest->mrownerconfig,
> +strlen(tdx_guest->mrownerconfig), &data_len,
> errp);
> +if (!data || data_len != QCRYPTO_HASH_DIGEST_LEN_SHA384) {
> +error_setg(errp, "TDX: failed to decode mrownerconfig");
> +return -1;
> +}
> +memcpy(init_vm->mrownerconfig, data, data_len);
> +}
> +
> r = setup_td_guest_attributes(x86cpu, errp);
> if (r) {
> return r;
With regards,
Daniel
--
|: https://berrange.com -o-https://www.flickr.com/photos/dberrange :|
|: https://libvirt.org -o-https://fstop138.berrange.com :|
|: https://entangle-photo.org-o-https://www.instagram.com/dberrange :|
Re: [PATCH for-10.1 v2 32/37] vfio: Introduce new files for VFIO MemoryListener
On 26/03/2025 07:51, Cédric Le Goater wrote:
> File "common.c" has been emptied of most of its definitions by the
> previous changes and the only definitions left are related to the VFIO
> MemoryListener handlers. Rename it to "listener.c" and introduce its
> associated "vfio-listener.h" header file for the declarations.
>
> Cleanup a little the includes while at it.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: Joao Martins
> ---
> hw/vfio/vfio-listener.h | 14 ++
> include/hw/vfio/vfio-common.h| 1 -
> hw/vfio/container.c | 1 +
> hw/vfio/iommufd.c| 1 +
> hw/vfio/{common.c => listener.c} | 0
> hw/vfio/meson.build | 2 +-
> hw/vfio/trace-events | 2 +-
> 7 files changed, 18 insertions(+), 3 deletions(-)
> create mode 100644 hw/vfio/vfio-listener.h
> rename hw/vfio/{common.c => listener.c} (100%)
>
> diff --git a/hw/vfio/vfio-listener.h b/hw/vfio/vfio-listener.h
> new file mode 100644
> index
> ..93af6747b28955f038454a335b361787f8364a3a
> --- /dev/null
> +++ b/hw/vfio/vfio-listener.h
> @@ -0,0 +1,14 @@
> +/*
> + * VFIO MemoryListener services
> + *
> + * Copyright Red Hat, Inc. 2025
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
> +#ifndef HW_VFIO_VFIO_LISTENER_H
> +#define HW_VFIO_VFIO_LISTENER_H
> +
> +extern const MemoryListener vfio_memory_listener;
> +
> +#endif /* HW_VFIO_VFIO_LISTENER_H */
> diff --git a/include/hw/vfio/vfio-common.h b/include/hw/vfio/vfio-common.h
> index
> a804af9f651f0916ca06b3f4f009381eea385ba0..4ab6e18d3c798ab379b98a0a16504814ec0556b1
> 100644
> --- a/include/hw/vfio/vfio-common.h
> +++ b/include/hw/vfio/vfio-common.h
> @@ -131,7 +131,6 @@ VFIODevice *vfio_get_vfio_device(Object *obj);
>
> typedef QLIST_HEAD(VFIODeviceList, VFIODevice) VFIODeviceList;
> extern VFIODeviceList vfio_device_list;
> -extern const MemoryListener vfio_memory_listener;
>
> #ifdef CONFIG_LINUX
> int vfio_get_region_info(VFIODevice *vbasedev, int index,
> diff --git a/hw/vfio/container.c b/hw/vfio/container.c
> index
> c74e08e531a501313cab27c57728a8c940d975be..acebb53dcb1b829d31cc31d9f7f2cc9599f952eb
> 100644
> --- a/hw/vfio/container.c
> +++ b/hw/vfio/container.c
> @@ -35,6 +35,7 @@
> #include "hw/vfio/vfio-container.h"
> #include "vfio-helpers.h"
> #include "vfio-cpr.h"
> +#include "vfio-listener.h"
>
> #define TYPE_HOST_IOMMU_DEVICE_LEGACY_VFIO TYPE_HOST_IOMMU_DEVICE
> "-legacy-vfio"
>
> diff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c
> index
> a5bd189a86d70bd11ecb80384ac145a51979322b..7488d21215b6eee78c9c51cfb227d9c8c59c4978
> 100644
> --- a/hw/vfio/iommufd.c
> +++ b/hw/vfio/iommufd.c
> @@ -28,6 +28,7 @@
> #include "vfio-iommufd.h"
> #include "vfio-helpers.h"
> #include "vfio-cpr.h"
> +#include "vfio-listener.h"
>
> #define TYPE_HOST_IOMMU_DEVICE_IOMMUFD_VFIO \
> TYPE_HOST_IOMMU_DEVICE_IOMMUFD "-vfio"
> diff --git a/hw/vfio/common.c b/hw/vfio/listener.c
> similarity index 100%
> rename from hw/vfio/common.c
> rename to hw/vfio/listener.c
> diff --git a/hw/vfio/meson.build b/hw/vfio/meson.build
> index
> 9c8a989db2d4578e97d864c5fd8bcba125eab66a..bccb05098ce18968caaa4d5d8dec3df0852d0398
> 100644
> --- a/hw/vfio/meson.build
> +++ b/hw/vfio/meson.build
> @@ -1,6 +1,6 @@
> vfio_ss = ss.source_set()
> vfio_ss.add(files(
> - 'common.c',
> + 'listener.c',
>'container-base.c',
>'container.c',
>'helpers.c',
> diff --git a/hw/vfio/trace-events b/hw/vfio/trace-events
> index
> aa0ba695fa38f7767bf506ec604046101186e7d4..ddb1bcc24a9cdc405713ca04d4ecc3d4a923ec42
> 100644
> --- a/hw/vfio/trace-events
> +++ b/hw/vfio/trace-events
> @@ -89,7 +89,7 @@ vfio_pci_igd_bdsm_enabled(const char *name, int size) "%s
> %dMB"
> vfio_pci_igd_host_bridge_enabled(const char *name) "%s"
> vfio_pci_igd_lpc_bridge_enabled(const char *name) "%s"
>
> -# common.c
> +# listener.c
> vfio_iommu_map_notify(const char *op, uint64_t iova_start, uint64_t
> iova_end) "iommu %s @ 0x%"PRIx64" - 0x%"PRIx64
> vfio_listener_region_skip(const char *name, uint64_t start, uint64_t end)
> "SKIPPING %s 0x%"PRIx64" - 0x%"PRIx64
> vfio_spapr_group_attach(int groupfd, int tablefd) "Attached groupfd %d to
> liobn fd %d"
Re: [PATCH for-10.1 v2 10/37] vfio: Introduce a new header file for VFIOIOMMUFD declarations
On 26/03/2025 07:50, Cédric Le Goater wrote:
> Gather all VFIOIOMMUFD related declarations introduced by commits
> 5ee3dc7af785 ("vfio/iommufd: Implement the iommufd backend") and
> 5b1e96e65403 ("vfio/iommufd: Introduce auto domain creation") into
> "vfio-iommufd.h". This to reduce exposure of VFIO internals in
> "hw/vfio/vfio-common.h".
>
> Cc: Joao Martins
> Cc: Yi Liu
> Reviewed-by: John Levon
> Link:
> https://lore.kernel.org/qemu-devel/20250318095415.670319-10-...@redhat.com
> Signed-off-by: Cédric Le Goater
Reviewed-by: Joao Martins
> ---
> hw/vfio/vfio-iommufd.h| 34 ++
> include/hw/vfio/vfio-common.h | 21 +++--
> hw/vfio/iommufd.c | 1 +
> 3 files changed, 38 insertions(+), 18 deletions(-)
> create mode 100644 hw/vfio/vfio-iommufd.h
>
> diff --git a/hw/vfio/vfio-iommufd.h b/hw/vfio/vfio-iommufd.h
> new file mode 100644
> index
> ..07ea0f43049645a5f3782048117fd9bf22083053
> --- /dev/null
> +++ b/hw/vfio/vfio-iommufd.h
> @@ -0,0 +1,34 @@
> +/*
> + * VFIO iommufd
> + *
> + * Copyright Red Hat, Inc. 2025
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
> +#ifndef HW_VFIO_VFIO_IOMMUFD_H
> +#define HW_VFIO_VFIO_IOMMUFD_H
> +
> +#include "hw/vfio/vfio-container-base.h"
> +
> +typedef struct VFIODevice VFIODevice;
> +
> +typedef struct VFIOIOASHwpt {
> +uint32_t hwpt_id;
> +uint32_t hwpt_flags;
> +QLIST_HEAD(, VFIODevice) device_list;
> +QLIST_ENTRY(VFIOIOASHwpt) next;
> +} VFIOIOASHwpt;
> +
> +typedef struct IOMMUFDBackend IOMMUFDBackend;
> +
> +typedef struct VFIOIOMMUFDContainer {
> +VFIOContainerBase bcontainer;
> +IOMMUFDBackend *be;
> +uint32_t ioas_id;
> +QLIST_HEAD(, VFIOIOASHwpt) hwpt_list;
> +} VFIOIOMMUFDContainer;
> +
> +OBJECT_DECLARE_SIMPLE_TYPE(VFIOIOMMUFDContainer, VFIO_IOMMU_IOMMUFD);
> +
> +#endif /* HW_VFIO_VFIO_IOMMUFD_H */
> diff --git a/include/hw/vfio/vfio-common.h b/include/hw/vfio/vfio-common.h
> index
> 3355c2d4e57569d7bb01b4d9378fb49a807335e8..8d48f5300a791d8858fe29d1bb905f814ef11990
> 100644
> --- a/include/hw/vfio/vfio-common.h
> +++ b/include/hw/vfio/vfio-common.h
> @@ -69,27 +69,12 @@ typedef struct VFIOContainer {
>
> OBJECT_DECLARE_SIMPLE_TYPE(VFIOContainer, VFIO_IOMMU_LEGACY);
>
> -typedef struct IOMMUFDBackend IOMMUFDBackend;
> -
> -typedef struct VFIOIOASHwpt {
> -uint32_t hwpt_id;
> -uint32_t hwpt_flags;
> -QLIST_HEAD(, VFIODevice) device_list;
> -QLIST_ENTRY(VFIOIOASHwpt) next;
> -} VFIOIOASHwpt;
> -
> -typedef struct VFIOIOMMUFDContainer {
> -VFIOContainerBase bcontainer;
> -IOMMUFDBackend *be;
> -uint32_t ioas_id;
> -QLIST_HEAD(, VFIOIOASHwpt) hwpt_list;
> -} VFIOIOMMUFDContainer;
> -
> -OBJECT_DECLARE_SIMPLE_TYPE(VFIOIOMMUFDContainer, VFIO_IOMMU_IOMMUFD);
> -
> typedef struct VFIODeviceOps VFIODeviceOps;
> typedef struct VFIOMigration VFIOMigration;
>
> +typedef struct IOMMUFDBackend IOMMUFDBackend;
> +typedef struct VFIOIOASHwpt VFIOIOASHwpt;
> +
> typedef struct VFIODevice {
> QLIST_ENTRY(VFIODevice) next;
> QLIST_ENTRY(VFIODevice) container_next;
> diff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c
> index
> 42c8412bbf50724dddb43f9b19a3aa40c8bc311d..7196c4080125674ec58b1ebf02dad84b4387c355
> 100644
> --- a/hw/vfio/iommufd.c
> +++ b/hw/vfio/iommufd.c
> @@ -25,6 +25,7 @@
> #include "qemu/cutils.h"
> #include "qemu/chardev_open.h"
> #include "pci.h"
> +#include "vfio-iommufd.h"
>
> static int iommufd_cdev_map(const VFIOContainerBase *bcontainer, hwaddr iova,
> ram_addr_t size, void *vaddr, bool readonly)
[PATCH] hw/arm/virt.c: Fix wrong default cpu type in AARCH64
Because of the CONFIG_TCG auto enabled, the cpu type "cortex-a15"
is mistakenly set to the default AARCH64 target.
Signed-off-by: Zhang Chen
---
hw/arm/virt.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index a96452f17a..63649e9543 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -3178,9 +3178,10 @@ static void virt_machine_class_init(ObjectClass *oc,
void *data)
mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
#ifdef CONFIG_TCG
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
-#else
+#ifdef TARGET_AARCH64
mc->default_cpu_type = ARM_CPU_TYPE_NAME("max");
-#endif
+#endif /* TARGET_AARCH64 */
+#endif /* CONFIG_TCG */
mc->valid_cpu_types = valid_cpu_types;
mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
mc->kvm_type = virt_kvm_type;
--
2.49.0
[PATCH 1/2] hvf: avoid repeatedly setting trap debug for each cpu
From: Mads Ynddal
hvf_arch_set_traps is already called from a context of a specific
CPUState, so we don't need to do a nested CPU_FOREACH.
It also results in an error from hv_vcpu_set_sys_reg, as it may only be
called from the thread owning the vCPU.
Tested-by: Daniel Gomez
Signed-off-by: Mads Ynddal
---
target/arm/hvf/hvf.c | 27 +++
1 file changed, 11 insertions(+), 16 deletions(-)
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index 2439af63a0..48e4b12725 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -2277,28 +2277,23 @@ static inline bool hvf_arm_hw_debug_active(CPUState
*cpu)
return ((cur_hw_wps > 0) || (cur_hw_bps > 0));
}
-static void hvf_arch_set_traps(void)
+static void hvf_arch_set_traps(CPUState *cpu)
{
-CPUState *cpu;
bool should_enable_traps = false;
hv_return_t r = HV_SUCCESS;
/* Check whether guest debugging is enabled for at least one vCPU; if it
* is, enable exiting the guest on all vCPUs */
-CPU_FOREACH(cpu) {
-should_enable_traps |= cpu->accel->guest_debug_enabled;
-}
-CPU_FOREACH(cpu) {
-/* Set whether debug exceptions exit the guest */
-r = hv_vcpu_set_trap_debug_exceptions(cpu->accel->fd,
- should_enable_traps);
-assert_hvf_ok(r);
+should_enable_traps |= cpu->accel->guest_debug_enabled;
+/* Set whether debug exceptions exit the guest */
+r = hv_vcpu_set_trap_debug_exceptions(cpu->accel->fd,
+should_enable_traps);
+assert_hvf_ok(r);
-/* Set whether accesses to debug registers exit the guest */
-r = hv_vcpu_set_trap_debug_reg_accesses(cpu->accel->fd,
-should_enable_traps);
-assert_hvf_ok(r);
-}
+/* Set whether accesses to debug registers exit the guest */
+r = hv_vcpu_set_trap_debug_reg_accesses(cpu->accel->fd,
+should_enable_traps);
+assert_hvf_ok(r);
}
void hvf_arch_update_guest_debug(CPUState *cpu)
@@ -2339,7 +2334,7 @@ void hvf_arch_update_guest_debug(CPUState *cpu)
deposit64(env->cp15.mdscr_el1, MDSCR_EL1_MDE_SHIFT, 1, 0);
}
-hvf_arch_set_traps();
+hvf_arch_set_traps(cpu);
}
bool hvf_arch_supports_guest_debug(void)
--
2.48.1
Re: [PATCH v5 2/4] virtio_net: Add the check for vdpa's mac address
On Wed, Mar 26, 2025 at 09:19:31PM +0800, Cindy Lu wrote:
> When using a VDPA device, it is important to ensure that the MAC
> address is correctly set. The MAC address in the hardware should
> match the MAC address from the QEMU command line. This is a recommended
> configuration and will allow the system to boot.
>
> Signed-off-by: Cindy Lu
> ---
> hw/net/virtio-net.c | 40 +++-
> 1 file changed, 39 insertions(+), 1 deletion(-)
>
> diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c
> index de87cfadff..a3b431e000 100644
> --- a/hw/net/virtio-net.c
> +++ b/hw/net/virtio-net.c
> @@ -3749,12 +3749,43 @@ static bool
> failover_hide_primary_device(DeviceListener *listener,
> /* failover_primary_hidden is set during feature negotiation */
> return qatomic_read(&n->failover_primary_hidden);
> }
> +static bool virtio_net_check_vdpa_mac(NetClientState *nc, VirtIONet *n,
> + MACAddr *cmdline_mac, Error **errp)
> +{
> +struct virtio_net_config hwcfg = {};
> +static const MACAddr zero = { .a = { 0, 0, 0, 0, 0, 0 } };
> +
> +vhost_net_get_config(get_vhost_net(nc->peer), (uint8_t *)&hwcfg,
> ETH_ALEN);
> +
> +/*For VDPA device following situations are acceptable:*/
/* This is how you format comments in QEMU */
/*Never like this*/
> +if (memcmp(&hwcfg.mac, &zero, sizeof(MACAddr)) != 0) {
> +/*
> + * 1.The hardware MAC address is the same as the QEMU command line
> MAC
space after .
> + * address, and both of them are not 0.
> + */
> +if ((memcmp(&hwcfg.mac, cmdline_mac, sizeof(MACAddr)) == 0)) {
> +return true;
> +}
> +}
>
> +error_setg(errp,
> + "vDPA device's mac %02x:%02x:%02x:%02x:%02x:%02x"
> + "not same with the cmdline's mac
> %02x:%02x:%02x:%02x:%02x:%02x,"
the same with the command line mac (avoid abbreviation)
> + "Please check.",
space after , and no uppercase
> + hwcfg.mac[0], hwcfg.mac[1], hwcfg.mac[2], hwcfg.mac[3],
> + hwcfg.mac[4], hwcfg.mac[5], cmdline_mac->a[0],
> cmdline_mac->a[1],
> + cmdline_mac->a[2], cmdline_mac->a[3], cmdline_mac->a[4],
> + cmdline_mac->a[5]);
check what? maybe "initialization failed"?
> +
> +return false;
> +}
> static void virtio_net_device_realize(DeviceState *dev, Error **errp)
> {
> VirtIODevice *vdev = VIRTIO_DEVICE(dev);
> VirtIONet *n = VIRTIO_NET(dev);
> NetClientState *nc;
> +MACAddr macaddr_cmdline;
> int i;
>
> if (n->net_conf.mtu) {
> @@ -3862,6 +3893,7 @@ static void virtio_net_device_realize(DeviceState *dev,
> Error **errp)
> virtio_net_add_queue(n, 0);
>
> n->ctrl_vq = virtio_add_queue(vdev, 64, virtio_net_handle_ctrl);
> +memcpy(&macaddr_cmdline, &n->nic_conf.macaddr, sizeof(n->mac));
> qemu_macaddr_default_if_unset(&n->nic_conf.macaddr);
> memcpy(&n->mac[0], &n->nic_conf.macaddr, sizeof(n->mac));
> n->status = VIRTIO_NET_S_LINK_UP;
> @@ -3908,7 +3940,13 @@ static void virtio_net_device_realize(DeviceState
> *dev, Error **errp)
> nc = qemu_get_queue(n->nic);
> nc->rxfilter_notify_enabled = 1;
>
> - if (nc->peer && nc->peer->info->type == NET_CLIENT_DRIVER_VHOST_VDPA) {
> +if (nc->peer && (nc->peer->info->type == NET_CLIENT_DRIVER_VHOST_VDPA)) {
> +if (nc->peer->check_mac) {
> +if (!virtio_net_check_vdpa_mac(nc, n, &macaddr_cmdline, errp)) {
> +virtio_cleanup(vdev);
> +return;
> +}
> +}
> struct virtio_net_config netcfg = {};
> memcpy(&netcfg.mac, &n->nic_conf.macaddr, ETH_ALEN);
> vhost_net_set_config(get_vhost_net(nc->peer),
> --
> 2.45.0
Re: [PATCH v5 3/4] virtio_net: Add second acceptable configuration for MAC setup
On Wed, Mar 26, 2025 at 09:19:32PM +0800, Cindy Lu wrote:
> For VDPA devices, Allow configurations where the hardware MAC address
> is non-zero while the MAC address in the QEMU command line is zero.
>
> Signed-off-by: Cindy Lu
> ---
> hw/net/virtio-net.c | 14 ++
> 1 file changed, 14 insertions(+)
>
> diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c
> index a3b431e000..1fd0403d5d 100644
> --- a/hw/net/virtio-net.c
> +++ b/hw/net/virtio-net.c
> @@ -3767,6 +3767,20 @@ static bool virtio_net_check_vdpa_mac(NetClientState
> *nc, VirtIONet *n,
> if ((memcmp(&hwcfg.mac, cmdline_mac, sizeof(MACAddr)) == 0)) {
> return true;
> }
> +/*
> + * 2.The hardware MAC address is NOT 0,
space after .
> + * and the MAC address in the QEMU command line is 0.
> + * In this situation, Here we use the hardware MAC address overwrite
> + * the QEMU command line address(is 0) in VirtIONet->mac[0].
drop "here" and add punctiation. period before overwrite maybe?
what is (is 0)?
> + * in the follwoing process, QEMU will use this mac in VirtIONet and
> + * finish the bring up
> + */
> +if (memcmp(cmdline_mac, &zero, sizeof(MACAddr)) == 0) {
> +/* overwrite the mac address with hardware address*/
> +memcpy(&n->mac[0], &hwcfg.mac, sizeof(n->mac));
> +memcpy(&n->nic_conf.macaddr, &hwcfg.mac, sizeof(n->mac));
> +return true;
> +}
> }
>
> error_setg(errp,
> --
> 2.45.0
Re: [PATCH v5 4/4] virtio_net: Add third acceptable configuration for MAC setup.
On Wed, Mar 26, 2025 at 09:19:33PM +0800, Cindy Lu wrote:
> For VDPA devices, Allow configurations where both the hardware MAC address
> and QEMU command line MAC address are zero.
>
> Signed-off-by: Cindy Lu
> ---
> hw/net/virtio-net.c | 13 +
> 1 file changed, 13 insertions(+)
>
> diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c
> index 1fd0403d5d..d1f44850d5 100644
> --- a/hw/net/virtio-net.c
> +++ b/hw/net/virtio-net.c
> @@ -3782,6 +3782,19 @@ static bool virtio_net_check_vdpa_mac(NetClientState
> *nc, VirtIONet *n,
> return true;
> }
> }
> +/*
> + * 3.The hardware MAC address is 0,
> + * and the MAC address in the QEMU command line is also 0.
> + * In this situation, qemu will generate a random mac address
> + * QEMU will try to use CVQ/set_config to set this address to
> + * device
same comments. end sentences with a period.
> + */
> +if ((memcmp(&hwcfg.mac, &zero, sizeof(MACAddr)) == 0) &&
> +(memcmp(cmdline_mac, &zero, sizeof(MACAddr)) == 0)) {
> +memcpy(&n->mac[0], &n->nic_conf.macaddr, sizeof(n->mac));
> +
> +return true;
> +}
>
> error_setg(errp,
> "vDPA device's mac %02x:%02x:%02x:%02x:%02x:%02x"
> --
> 2.45.0
Re: [PATCH v8 07/55] kvm: Introduce kvm_arch_pre_create_vcpu()
On Tue, Apr 01, 2025 at 09:01:17AM -0400, Xiaoyao Li wrote: > Introduce kvm_arch_pre_create_vcpu(), to perform arch-dependent > work prior to create any vcpu. This is for i386 TDX because it needs > call TDX_INIT_VM before creating any vcpu. > > The specific implemnet of i386 will be added in the future patch. s/implemnet of/implementation for' > > Signed-off-by: Xiaoyao Li > Acked-by: Gerd Hoffmann > --- > Changes in v7: > - Implement stub for all the ARCHes instead of defining it with weak > attribute; (Philippe) > > Changes in v3: > - pass @errp to kvm_arch_pre_create_vcpu(); (Per Daniel) > --- > accel/kvm/kvm-all.c| 5 + > include/system/kvm.h | 1 + > target/arm/kvm.c | 5 + > target/i386/kvm/kvm.c | 5 + > target/loongarch/kvm/kvm.c | 4 > target/mips/kvm.c | 5 + > target/ppc/kvm.c | 5 + > target/riscv/kvm/kvm-cpu.c | 5 + > target/s390x/kvm/kvm.c | 5 + > 9 files changed, 40 insertions(+) Reviewed-by: Daniel P. Berrangé With regards, Daniel -- |: https://berrange.com -o-https://www.flickr.com/photos/dberrange :| |: https://libvirt.org -o-https://fstop138.berrange.com :| |: https://entangle-photo.org-o-https://www.instagram.com/dberrange :|
[PATCH v2 2/2] target/hexagon: Only indent on linux
indent on macOS, installed via homebrew, doesn't support -linux. Only
run indent on linux hosts.
Signed-off-by: Anton Johansson
---
target/hexagon/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/hexagon/meson.build b/target/hexagon/meson.build
index abcf00ca1f..d26787a9b9 100644
--- a/target/hexagon/meson.build
+++ b/target/hexagon/meson.build
@@ -324,7 +324,7 @@ if idef_parser_enabled and 'hexagon-linux-user' in
target_dirs
)
indent = find_program('indent', required: false)
-if indent.found()
+if indent.found() and host_os == 'linux'
idef_generated_tcg_c = custom_target(
'indent',
input: idef_generated_tcg[0],
--
2.47.1
[PATCH v2 0/2] target/hexagon: Fix macOS build
A default macOS build with xcode cli tools installed lacks the `indent`
program needed by the idef-parser postprocess step. If `indent` is
installed through homebrew it doesn't support the `-linux` flag.
Conditionally run `indent` only on linux hosts.
Additionally `cpp` used by the idef-parser preprocess step expands into
`clang ... -traditional-cpp` and doesn't support macro concatenation
among other things, replace it with a meson custom_target running
`${compiler} -E`.
fixes:
https://lore.kernel.org/qemu-devel/d95ebf5d-c1f6-42c5-8aeb-65764fa87...@linaro.org/
Note: default bison on macOS is still too old (v2.3 vs v3.0) and a newer
version needs to be installed via homebrew. I'll take a look at
supporting v2.3.
Changes in v2:
* Don't remove the indent step but only run on linux hosts.
Anton Johansson (2):
target/hexagon: Replace `prepare` script with meson target
target/hexagon: Only indent on linux
target/hexagon/idef-parser/prepare | 24
target/hexagon/meson.build | 5 +++--
2 files changed, 3 insertions(+), 26 deletions(-)
delete mode 100755 target/hexagon/idef-parser/prepare
--
2.47.1
Re: [PATCH v8 10/55] i386/tdx: Make sept_ve_disable set by default
On Tue, Apr 01, 2025 at 09:01:20AM -0400, Xiaoyao Li wrote: > From: Isaku Yamahata > > For TDX KVM use case, Linux guest is the most major one. It requires > sept_ve_disable set. Make it default for the main use case. For other use > case, it can be enabled/disabled via qemu command line. > > Signed-off-by: Isaku Yamahata > Signed-off-by: Xiaoyao Li > --- > target/i386/kvm/tdx.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Daniel P. Berrangé With regards, Daniel -- |: https://berrange.com -o-https://www.flickr.com/photos/dberrange :| |: https://libvirt.org -o-https://fstop138.berrange.com :| |: https://entangle-photo.org-o-https://www.instagram.com/dberrange :|
Re: [PATCH v8 12/55] i386/tdx: Validate TD attributes
On Tue, Apr 01, 2025 at 09:01:22AM -0400, Xiaoyao Li wrote:
> Validate TD attributes with tdx_caps that only supported bits are
> allowed by KVM.
>
> Besides, sanity check the attribute bits that have not been supported by
> QEMU yet. e.g., debug bit, it will be allowed in the future when debug
> TD support lands in QEMU.
>
> Signed-off-by: Xiaoyao Li
> Acked-by: Gerd Hoffmann
> ---
> Changes in v8:
> - Split the mrconfigid/mrowner/mrownerconfig part into a seperate next
> patch;
>
> Changes in v7:
> - Define TDX_SUPPORTED_TD_ATTRS as QEMU supported mask, to validates
> user's request. (Rick)
>
> Changes in v3:
> - using error_setg() for error report; (Daniel)
> ---
> target/i386/kvm/tdx.c | 32 ++--
> 1 file changed, 30 insertions(+), 2 deletions(-)
>
> diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c
> index 1202b2111ba8..aa043acb1a88 100644
> --- a/target/i386/kvm/tdx.c
> +++ b/target/i386/kvm/tdx.c
> @@ -18,10 +18,15 @@
> #include "kvm_i386.h"
> #include "tdx.h"
>
> +#define TDX_TD_ATTRIBUTES_DEBUG BIT_ULL(0)
> #define TDX_TD_ATTRIBUTES_SEPT_VE_DISABLE BIT_ULL(28)
> #define TDX_TD_ATTRIBUTES_PKS BIT_ULL(30)
> #define TDX_TD_ATTRIBUTES_PERFMON BIT_ULL(63)
>
> +#define TDX_SUPPORTED_TD_ATTRS (TDX_TD_ATTRIBUTES_SEPT_VE_DISABLE |\
> + TDX_TD_ATTRIBUTES_PKS | \
> + TDX_TD_ATTRIBUTES_PERFMON)
> +
> static TdxGuest *tdx_guest;
>
> static struct kvm_tdx_capabilities *tdx_caps;
> @@ -153,13 +158,33 @@ static int tdx_kvm_type(X86ConfidentialGuest *cg)
> return KVM_X86_TDX_VM;
> }
>
> -static void setup_td_guest_attributes(X86CPU *x86cpu)
> +static int tdx_validate_attributes(TdxGuest *tdx, Error **errp)
> +{
> +if ((tdx->attributes & ~tdx_caps->supported_attrs)) {
> +error_setg(errp, "Invalid attributes 0x%lx for TDX VM "
> + "(KVM supported: 0x%llx)", tdx->attributes,
> + tdx_caps->supported_attrs);
> +return -1;
> +}
> +
> +if (tdx->attributes & ~TDX_SUPPORTED_TD_ATTRS) {
> +warn_report("Some QEMU unsupported TD attribute bits being
> requested:"
> +"requested: 0x%lx QEMU supported: 0x%llx",
> +tdx->attributes, TDX_SUPPORTED_TD_ATTRS);
IIUC, this is an explicit user mis-configuration, and so we
ought to use error_setg & return -1, not merely a warning.
> +}
> +
> +return 0;
> +}
> +
> +static int setup_td_guest_attributes(X86CPU *x86cpu, Error **errp)
> {
> CPUX86State *env = &x86cpu->env;
>
> tdx_guest->attributes |= (env->features[FEAT_7_0_ECX] &
> CPUID_7_0_ECX_PKS) ?
> TDX_TD_ATTRIBUTES_PKS : 0;
> tdx_guest->attributes |= x86cpu->enable_pmu ? TDX_TD_ATTRIBUTES_PERFMON
> : 0;
> +
> +return tdx_validate_attributes(tdx_guest, errp);
> }
>
> static int setup_td_xfam(X86CPU *x86cpu, Error **errp)
> @@ -225,7 +250,10 @@ int tdx_pre_create_vcpu(CPUState *cpu, Error **errp)
> init_vm = g_malloc0(sizeof(struct kvm_tdx_init_vm) +
> sizeof(struct kvm_cpuid_entry2) *
> KVM_MAX_CPUID_ENTRIES);
>
> -setup_td_guest_attributes(x86cpu);
> +r = setup_td_guest_attributes(x86cpu, errp);
> +if (r) {
> +return r;
> +}
>
> r = setup_td_xfam(x86cpu, errp);
> if (r) {
> --
> 2.34.1
>
With regards,
Daniel
--
|: https://berrange.com -o-https://www.flickr.com/photos/dberrange :|
|: https://libvirt.org -o-https://fstop138.berrange.com :|
|: https://entangle-photo.org-o-https://www.instagram.com/dberrange :|
Re: [PATCH 1/2] vfio/migration: Add also max in-flight VFIO device state buffers size limit
Hello Maciej,
On 4/1/25 14:26, Maciej S. Szmigiero wrote:
On 11.03.2025 14:04, Cédric Le Goater wrote:
On 3/7/25 14:45, Maciej S. Szmigiero wrote:
On 7.03.2025 13:03, Cédric Le Goater wrote:
On 3/7/25 11:57, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
There's already a max in-flight VFIO device state buffers *count* limit,
no. there isn't. Do we need both ?
This is on a top of the remaining patches (x-migration-load-config-after-iter
and x-migration-max-queued-buffers) - I thought we were supposed to work
on these after the main series was merged as they are relatively non-critical.
yes. we don't need both count and size limits though, a size limit is enough.
I would also give x-migration-load-config-after-iter priority over
x-migration-max-queued-buffers{,-size} as the former is correctness fix
while the later are just additional functionalities.
ok. I have kept both patches in my tree with the doc updates.
I don't see the x-migration-load-config-after-iter patch in upstream QEMU
anywhere.
That's a bit concerning since it's a correctness fix - without it the
multifd VFIO migration on ARM64 can fail.
The existing patch still applies, but requires changing
"#if defined(TARGET_ARM)" to "strcmp(target_name(), "aarch64") == 0" due to
recent commit 5731baee6c3c ("hw/vfio: Compile some common objects once").
I can submit an updated patch if you like.
It is a bit early.
Let's wait for the spring cleanup to be applied first. I am waiting for
more feedback from Avihai and Joao. It should not be long.
Thanks,
C.
Re: [PATCH v8 03/55] i386/tdx: Implement tdx_kvm_type() for TDX
On Tue, Apr 01, 2025 at 09:01:13AM -0400, Xiaoyao Li wrote: > TDX VM requires VM type to be KVM_X86_TDX_VM. Implement tdx_kvm_type() > as X86ConfidentialGuestClass->kvm_type. > > Signed-off-by: Xiaoyao Li > --- > Changes in v6: > - new added patch; > --- > target/i386/kvm/kvm.c | 1 + > target/i386/kvm/tdx.c | 12 > 2 files changed, 13 insertions(+) Reviewed-by: Daniel P. Berrangé With regards, Daniel -- |: https://berrange.com -o-https://www.flickr.com/photos/dberrange :| |: https://libvirt.org -o-https://fstop138.berrange.com :| |: https://entangle-photo.org-o-https://www.instagram.com/dberrange :|
[PATCH] Add annotations in QemuEvent functions
This patch adds missing annotations for qemu_event_set, qemu_event_reset,
and qemu_event_wait to prevent TSAN from reporting false alarms caused by
the use of barriers and futex_wait.
Fixes: c7c4d063f5 ("qemu-thread: add QemuEvent")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2904
Signed-off-by: Vitalii Mordan
---
util/qemu-thread-posix.c | 4
util/qemu-thread-win32.c | 4
2 files changed, 8 insertions(+)
diff --git a/util/qemu-thread-posix.c b/util/qemu-thread-posix.c
index b2e26e2120..2f6b4834e9 100644
--- a/util/qemu-thread-posix.c
+++ b/util/qemu-thread-posix.c
@@ -403,6 +403,7 @@ void qemu_event_set(QemuEvent *ev)
qemu_futex_wake(ev, INT_MAX);
}
}
+QEMU_TSAN_ANNOTATE_HAPPENS_BEFORE(ev);
}
void qemu_event_reset(QemuEvent *ev)
@@ -420,6 +421,7 @@ void qemu_event_reset(QemuEvent *ev)
* Pairs with the first memory barrier in qemu_event_set().
*/
smp_mb__after_rmw();
+QEMU_TSAN_ANNOTATE_HAPPENS_BEFORE(ev);
}
void qemu_event_wait(QemuEvent *ev)
@@ -452,6 +454,7 @@ void qemu_event_wait(QemuEvent *ev)
* like the load above.
*/
if (qatomic_cmpxchg(&ev->value, EV_FREE, EV_BUSY) == EV_SET) {
+QEMU_TSAN_ANNOTATE_HAPPENS_AFTER(ev);
return;
}
}
@@ -463,6 +466,7 @@ void qemu_event_wait(QemuEvent *ev)
*/
qemu_futex_wait(ev, EV_BUSY);
}
+QEMU_TSAN_ANNOTATE_HAPPENS_AFTER(ev);
}
static __thread NotifierList thread_exit;
diff --git a/util/qemu-thread-win32.c b/util/qemu-thread-win32.c
index a7fe3cc345..b08aed9b6f 100644
--- a/util/qemu-thread-win32.c
+++ b/util/qemu-thread-win32.c
@@ -290,6 +290,7 @@ void qemu_event_set(QemuEvent *ev)
SetEvent(ev->event);
}
}
+QEMU_TSAN_ANNOTATE_HAPPENS_BEFORE(ev);
}
void qemu_event_reset(QemuEvent *ev)
@@ -307,6 +308,7 @@ void qemu_event_reset(QemuEvent *ev)
* Pairs with the first memory barrier in qemu_event_set().
*/
smp_mb__after_rmw();
+QEMU_TSAN_ANNOTATE_HAPPENS_BEFORE(ev);
}
void qemu_event_wait(QemuEvent *ev)
@@ -348,6 +350,7 @@ void qemu_event_wait(QemuEvent *ev)
* set or busy.
*/
if (qatomic_cmpxchg(&ev->value, EV_FREE, EV_BUSY) == EV_SET) {
+QEMU_TSAN_ANNOTATE_HAPPENS_AFTER(ev);
return;
}
}
@@ -358,6 +361,7 @@ void qemu_event_wait(QemuEvent *ev)
*/
WaitForSingleObject(ev->event, INFINITE);
}
+QEMU_TSAN_ANNOTATE_HAPPENS_AFTER(ev);
}
struct QemuThreadData {
--
2.34.1
Re: [PATCH v8 08/55] i386/tdx: Initialize TDX before creating TD vcpus
On Tue, Apr 01, 2025 at 09:01:18AM -0400, Xiaoyao Li wrote:
> Invoke KVM_TDX_INIT_VM in kvm_arch_pre_create_vcpu() that
> KVM_TDX_INIT_VM configures global TD configurations, e.g. the canonical
> CPUID config, and must be executed prior to creating vCPUs.
>
> Use kvm_x86_arch_cpuid() to setup the CPUID settings for TDX VM.
>
> Note, this doesn't address the fact that QEMU may change the CPUID
> configuration when creating vCPUs, i.e. punts on refactoring QEMU to
> provide a stable CPUID config prior to kvm_arch_init().
>
> Signed-off-by: Xiaoyao Li
> Acked-by: Gerd Hoffmann
> Acked-by: Markus Armbruster
> ---
> Changes in v8:
> - Drop the code that initializes cpu->kvm_state before
> kvm_arch_pre_create_vcpu() because it's not needed anymore.
>
> Changes in v7:
> - Add comments to explain why KVM_TDX_INIT_VM should retry on -EAGAIN;
> - Add retry limit of 1 times for -EAGAIN on KVM_TDX_INIT_VM;
>
> Changes in v6:
> - setup xfam explicitly to fit with new uapi;
> - use tdx_caps->cpuid to filter the input of cpuids because now KVM only
> allows the leafs that reported via KVM_TDX_GET_CAPABILITIES;
>
> Changes in v4:
> - mark init_vm with g_autofree() and use QEMU_LOCK_GUARD() to eliminate
> the goto labels; (Daniel)
> Changes in v3:
> - Pass @errp in tdx_pre_create_vcpu() and pass error info to it. (Daniel)
> ---
> target/i386/kvm/kvm.c | 16 +++---
> target/i386/kvm/kvm_i386.h | 5 ++
> target/i386/kvm/meson.build | 2 +-
> target/i386/kvm/tdx-stub.c | 10
> target/i386/kvm/tdx.c | 105
> target/i386/kvm/tdx.h | 6 +++
> 6 files changed, 137 insertions(+), 7 deletions(-)
> create mode 100644 target/i386/kvm/tdx-stub.c
> diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c
> index 16f67e18ae78..0afaf739c09f 100644
> --- a/target/i386/kvm/tdx.c
> +++ b/target/i386/kvm/tdx.c
> +int tdx_pre_create_vcpu(CPUState *cpu, Error **errp)
> +{
> +X86CPU *x86cpu = X86_CPU(cpu);
> +CPUX86State *env = &x86cpu->env;
> +g_autofree struct kvm_tdx_init_vm *init_vm = NULL;
> +Error *local_err = NULL;
> +int retry = 1;
> +int r = 0;
> +
> +QEMU_LOCK_GUARD(&tdx_guest->lock);
> +if (tdx_guest->initialized) {
> +return r;
> +}
> +
> +init_vm = g_malloc0(sizeof(struct kvm_tdx_init_vm) +
> +sizeof(struct kvm_cpuid_entry2) *
> KVM_MAX_CPUID_ENTRIES);
> +
> +r = setup_td_xfam(x86cpu, errp);
> +if (r) {
> +return r;
> +}
> +
> +init_vm->cpuid.nent = kvm_x86_build_cpuid(env, init_vm->cpuid.entries,
> 0);
> +tdx_filter_cpuid(&init_vm->cpuid);
> +
> +init_vm->attributes = tdx_guest->attributes;
> +init_vm->xfam = tdx_guest->xfam;
> +
> +/*
> + * KVM_TDX_INIT_VM gets -EAGAIN when KVM side SEAMCALL(TDH_MNG_CREATE)
> + * gets TDX_RND_NO_ENTROPY due to Random number generation (e.g., RDRAND
> or
> + * RDSEED) is busy.
> + *
> + * Retry for the case.
> + */
> +do {
> +error_free(local_err);
> +local_err = NULL;
> +r = tdx_vm_ioctl(KVM_TDX_INIT_VM, 0, init_vm, &local_err);
> +} while (r == -EAGAIN && --retry);
> +
> +if (r < 0) {
> +if (!retry) {
> +error_report("Hardware RNG (Random Number Generator) is busy "
> + "occupied by someone (via RDRAND/RDSEED)
> maliciously, "
> + "which leads to KVM_TDX_INIT_VM keeping failure "
> + "due to lack of entropy.");
This needs to be
error_append_hint(local_err, );
so that this message gets associated with the error object that
is propagated, and the top level will print it all at once.
> +}
> +error_propagate(errp, local_err);
> +return r;
> +}
> +
> +tdx_guest->initialized = true;
> +
> +return 0;
> +}
With regards,
Daniel
--
|: https://berrange.com -o-https://www.flickr.com/photos/dberrange :|
|: https://libvirt.org -o-https://fstop138.berrange.com :|
|: https://entangle-photo.org-o-https://www.instagram.com/dberrange :|
Re: [PATCH v2 2/2] target/hexagon: Only indent on linux
On 4/2/2025 6:42 AM, Anton Johansson wrote:
indent on macOS, installed via homebrew, doesn't support -linux. Only
run indent on linux hosts.
Signed-off-by: Anton Johansson
---
Reviewed-by: Brian Cain
target/hexagon/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/hexagon/meson.build b/target/hexagon/meson.build
index abcf00ca1f..d26787a9b9 100644
--- a/target/hexagon/meson.build
+++ b/target/hexagon/meson.build
@@ -324,7 +324,7 @@ if idef_parser_enabled and 'hexagon-linux-user' in
target_dirs
)
indent = find_program('indent', required: false)
-if indent.found()
+if indent.found() and host_os == 'linux'
idef_generated_tcg_c = custom_target(
'indent',
input: idef_generated_tcg[0],
Re: [PATCH v2 1/2] target/hexagon: Replace `prepare` script with meson target
On 4/2/2025 6:42 AM, Anton Johansson wrote:
The purpose of the prepare script is to invoke `cpp` to preprocess input
to idef-parser by expanding a few select macros. On macOS `cpp`
expands into `clang ... -traditional-cpp` which breaks macro
concatenation. Replace `cpp` with `${compiler} -E`
and replace the script with a meson custom_target.
Signed-off-by: Anton Johansson
---
Reviewed-by: Brian Cain
target/hexagon/idef-parser/prepare | 24
target/hexagon/meson.build | 3 ++-
2 files changed, 2 insertions(+), 25 deletions(-)
delete mode 100755 target/hexagon/idef-parser/prepare
diff --git a/target/hexagon/idef-parser/prepare
b/target/hexagon/idef-parser/prepare
deleted file mode 100755
index cb3622d4f8..00
--- a/target/hexagon/idef-parser/prepare
+++ /dev/null
@@ -1,24 +0,0 @@
-#!/usr/bin/env bash
-
-#
-# Copyright(c) 2019-2021 rev.ng Labs Srl. All Rights Reserved.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, see
Re: [PATCH v2 06/42] include/exec: Split out cpu-mmu-index.h
On 2/4/25 20:33, Richard Henderson wrote: On 4/2/25 04:26, Philippe Mathieu-Daudé wrote: Hi Richard, On 18/3/25 22:31, Richard Henderson wrote: The implementation of cpu_mmu_index was split between cpu-common.h and cpu-all.h, depending on CONFIG_USER_ONLY. We already have the plumbing common to user and system mode. Using MMU_USER_IDX requires the cpu.h for a specific target, and so is restricted to when we're compiling per-target. Include the new header only where needed. Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 6 -- include/exec/cpu-common.h | 20 -- include/exec/cpu-mmu-index.h | 39 +++ include/exec/cpu_ldst.h | 1 + semihosting/uaccess.c | 1 + target/arm/gdbstub64.c | 3 +++ target/hppa/mem_helper.c | 1 + target/i386/tcg/translate.c | 1 + target/loongarch/cpu_helper.c | 1 + target/microblaze/helper.c | 1 + target/microblaze/mmu.c | 1 + target/openrisc/translate.c | 1 + target/sparc/cpu.c | 1 + target/sparc/mmu_helper.c | 1 + target/tricore/helper.c | 1 + target/xtensa/mmu_helper.c | 1 + 16 files changed, 54 insertions(+), 26 deletions(-) create mode 100644 include/exec/cpu-mmu-index.h diff --git a/include/exec/cpu-mmu-index.h b/include/exec/cpu-mmu-index.h new file mode 100644 index 00..b46e622048 --- /dev/null +++ b/include/exec/cpu-mmu-index.h @@ -0,0 +1,39 @@ +/* + * cpu_mmu_index() + * + * Copyright (c) 2003 Fabrice Bellard + * + * SPDX-License-Identifier: LGPL-2.1+ + */ + +#ifndef EXEC_CPU_MMU_INDEX_H +#define EXEC_CPU_MMU_INDEX_H + +#include "hw/core/cpu.h" +#include "tcg/debug-assert.h" +#ifdef COMPILING_PER_TARGET +#include "cpu.h" IIUC we only need "cpu.h" on user emulation. Maybe use: #if defined(COMPILING_PER_TARGET) && defined(CONFIG_USER_ONLY) Can't. +#ifdef COMPILING_PER_TARGET +# ifdef CONFIG_USER_ONLY It would have to be this nesting, for the poisoning. Fine then, so we avoid including the huge "cpu.h" when not necessary.
[PATCH-for-10.0?] target/riscv: Do not expose rv128 CPU on user mode emulation
As Richard mentioned:
We should allow RV128 in user-mode at all until there's a
kernel abi for it.
Remove the experimental 'x-rv128' CPU on user emulation
(since it is experimental, no deprecation period is required).
Reported-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/riscv/cpu.c | 10 --
target/riscv/tcg/tcg-cpu.c | 5 +++--
2 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 430b02d2a58..ad534cee51f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -697,7 +697,7 @@ static void rv64_xiangshan_nanhu_cpu_init(Object *obj)
#endif
}
-#ifdef CONFIG_TCG
+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
static void rv128_base_cpu_init(Object *obj)
{
RISCVCPU *cpu = RISCV_CPU(obj);
@@ -708,11 +708,9 @@ static void rv128_base_cpu_init(Object *obj)
/* Set latest version of privileged specification */
env->priv_ver = PRIV_VERSION_LATEST;
-#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
-#endif
}
-#endif /* CONFIG_TCG */
+#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
static void rv64i_bare_cpu_init(Object *obj)
{
@@ -3255,9 +3253,9 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64,
rv64_veyron_v1_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU,
MXL_RV64,
rv64_xiangshan_nanhu_cpu_init),
-#ifdef CONFIG_TCG
+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, MXL_RV128,
rv128_base_cpu_init),
-#endif /* CONFIG_TCG */
+#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I,MXL_RV64,
rv64i_bare_cpu_init),
DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64E,MXL_RV64,
rv64e_bare_cpu_init),
DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, MXL_RV64,
rva22u64_profile_cpu_init),
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 19ab324cb2a..50e81b2e521 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -1048,7 +1048,6 @@ static bool riscv_cpu_is_generic(Object *cpu_obj)
static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp)
{
RISCVCPU *cpu = RISCV_CPU(cs);
-RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
if (!riscv_cpu_tcg_compatible(cpu)) {
g_autofree char *name = riscv_cpu_get_name(cpu);
@@ -1057,6 +1056,9 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error
**errp)
return false;
}
+#ifndef CONFIG_USER_ONLY
+RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
+
if (mcc->misa_mxl_max >= MXL_RV128 && qemu_tcg_mttcg_enabled()) {
/* Missing 128-bit aligned atomics */
error_setg(errp,
@@ -1065,7 +1067,6 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error
**errp)
return false;
}
-#ifndef CONFIG_USER_ONLY
CPURISCVState *env = &cpu->env;
tcg_cflags_set(CPU(cs), CF_PCREL);
--
2.47.1
[PATCH-for-10.1 04/43] accel/tcg: Introduce TCGCPUOps::mmu_index() callback
We'll move CPUClass::mmu_index() to TCGCPUOps::mmu_index().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
include/accel/tcg/cpu-ops.h | 3 +++
include/exec/cpu-mmu-index.h | 5 -
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/include/accel/tcg/cpu-ops.h b/include/accel/tcg/cpu-ops.h
index f60e5303f21..106a0688da8 100644
--- a/include/accel/tcg/cpu-ops.h
+++ b/include/accel/tcg/cpu-ops.h
@@ -67,6 +67,9 @@ struct TCGCPUOps {
/** @debug_excp_handler: Callback for handling debug exceptions */
void (*debug_excp_handler)(CPUState *cpu);
+/** @mmu_index: Callback for choosing softmmu mmu index */
+int (*mmu_index)(CPUState *cpu, bool ifetch);
+
#ifdef CONFIG_USER_ONLY
/**
* @fake_user_interrupt: Callback for 'fake exception' handling.
diff --git a/include/exec/cpu-mmu-index.h b/include/exec/cpu-mmu-index.h
index cfc13d46bea..651526e9f97 100644
--- a/include/exec/cpu-mmu-index.h
+++ b/include/exec/cpu-mmu-index.h
@@ -10,6 +10,7 @@
#define EXEC_CPU_MMU_INDEX_H
#include "hw/core/cpu.h"
+#include "accel/tcg/cpu-ops.h"
#include "tcg/debug-assert.h"
#ifdef COMPILING_PER_TARGET
#include "cpu.h"
@@ -31,7 +32,9 @@ static inline int cpu_mmu_index(CPUState *cs, bool ifetch)
# endif
#endif
-int ret = cs->cc->mmu_index(cs, ifetch);
+const TCGCPUOps *tcg_ops = cs->cc->tcg_ops;
+int ret = tcg_ops->mmu_index ? tcg_ops->mmu_index(cs, ifetch)
+ : cs->cc->mmu_index(cs, ifetch);
tcg_debug_assert(ret >= 0 && ret < NB_MMU_MODES);
return ret;
}
--
2.47.1
[PATCH-for-10.1 00/43] tcg: philmd's queue
Hi Richard,
Here is my patch queue based on your tcg-next tree.
Missing review: 38, 41, 43 (all news)
Thanks,
Phil.
Philippe Mathieu-Daudé (43):
tcg: Declare TARGET_INSN_START_EXTRA_WORDS in 'cpu-param.h'
tcg: Always define TARGET_INSN_START_EXTRA_WORDS
hw/core/cpu: Update CPUClass::mmu_index docstring
accel/tcg: Introduce TCGCPUOps::mmu_index() callback
target/alpha: Restrict SoftMMU mmu_index() to TCG
target/arm: Restrict SoftMMU mmu_index() to TCG
target/avr: Restrict SoftMMU mmu_index() to TCG
target/hppa: Restrict SoftMMU mmu_index() to TCG
target/i386: Remove unused cpu_(ldub,stb)_kernel macros
target/i386: Restrict cpu_mmu_index_kernel() to TCG
target/i386: Restrict SoftMMU mmu_index() to TCG
target/loongarch: Restrict SoftMMU mmu_index() to TCG
target/m68k: Restrict SoftMMU mmu_index() to TCG
target/microblaze: Restrict SoftMMU mmu_index() to TCG
target/mips: Restrict SoftMMU mmu_index() to TCG
target/openrisc: Restrict SoftMMU mmu_index() to TCG
target/ppc: Restrict SoftMMU mmu_index() to TCG
target/riscv: Restrict SoftMMU mmu_index() to TCG
target/rx: Fix copy/paste typo (riscv -> rx)
target/rx: Restrict SoftMMU mmu_index() to TCG
target/s390x: Restrict SoftMMU mmu_index() to TCG
target/sh4: Restrict SoftMMU mmu_index() to TCG
target/sparc: Restrict SoftMMU mmu_index() to TCG
target/tricore: Restrict SoftMMU mmu_index() to TCG
target/xtensa: Restrict SoftMMU mmu_index() to TCG
hw/core/cpu: Remove CPUClass::mmu_index()
exec: Restrict cpu-mmu-index.h to accel/tcg/
exec: Restrict 'cpu-ldst-common.h' to accel/tcg/
exec: Restrict 'cpu_ldst.h' to accel/tcg/
exec: Do not include 'accel/tcg/cpu-ldst.h' in 'exec-all.h'
tcg: Always define TCG_GUEST_DEFAULT_MO
tcg: Simplify tcg_req_mo() macro
tcg: Define guest_default_memory_order in TCGCPUOps
tcg: Remove use of TCG_GUEST_DEFAULT_MO in tb_gen_code()
tcg: Propagate CPUState argument to cpu_req_mo()
tcg: Have tcg_req_mo() use TCGCPUOps::guest_default_memory_order
tcg: Remove the TCG_GUEST_DEFAULT_MO definition globally
tcg: Move cpu_req_mo() macro to target-agnostic 'backend-ldst.h'
tcg: Move qemu_tcg_mttcg_enabled() to 'system/tcg.h'
tcg: Convert TCGState::mttcg_enabled to TriState
tcg: Factor mttcg_init() out
tcg: Convert TARGET_SUPPORTS_MTTCG to TCGCPUOps::mttcg_supported field
target/arm: Update comment around cpu_untagged_addr()
docs/devel/multi-thread-tcg.rst | 6 +-
configs/targets/aarch64-softmmu.mak | 1 -
configs/targets/alpha-softmmu.mak | 1 -
configs/targets/arm-softmmu.mak | 1 -
configs/targets/hppa-softmmu.mak | 1 -
configs/targets/i386-softmmu.mak | 1 -
configs/targets/loongarch64-softmmu.mak | 1 -
configs/targets/microblaze-softmmu.mak| 1 -
configs/targets/microblazeel-softmmu.mak | 1 -
configs/targets/mips-softmmu.mak | 1 -
configs/targets/mipsel-softmmu.mak| 1 -
configs/targets/or1k-softmmu.mak | 1 -
configs/targets/ppc64-softmmu.mak | 1 -
configs/targets/riscv32-softmmu.mak | 1 -
configs/targets/riscv64-softmmu.mak | 1 -
configs/targets/s390x-softmmu.mak | 1 -
configs/targets/sparc-softmmu.mak | 1 -
configs/targets/sparc64-softmmu.mak | 1 -
configs/targets/x86_64-softmmu.mak| 1 -
configs/targets/xtensa-softmmu.mak| 1 -
configs/targets/xtensaeb-softmmu.mak | 1 -
accel/tcg/backend-ldst.h | 41 +
accel/tcg/internal-common.h | 27 ++
accel/tcg/internal-target.h | 35
bsd-user/qemu.h | 2 +-
include/{exec => accel/tcg}/cpu-ldst-common.h | 6 +-
.../{exec/cpu_ldst.h => accel/tcg/cpu-ldst.h} | 10 +--
include/{exec => accel/tcg}/cpu-mmu-index.h | 9 +-
include/accel/tcg/cpu-ops.h | 19 +
include/exec/exec-all.h | 3 -
include/exec/poison.h | 1 -
include/hw/core/cpu.h | 12 ---
include/system/tcg.h | 8 ++
include/tcg/insn-start-words.h| 4 -
include/tcg/tcg-op.h | 2 +-
linux-user/qemu.h | 2 +-
target/alpha/cpu-param.h | 3 +-
target/arm/cpu-param.h| 8 +-
target/arm/cpu.h | 8 +-
target/arm/internals.h| 1 +
target/arm/tcg/sve_ldst_internal.h| 2 +-
target/avr/cpu-param.h| 2 +-
target/hexagon/cpu-param.h| 2 +
target/hppa/cpu-param.h | 8 +-
target/hppa/cpu.h | 2 -
target/i386/cpu-param.h | 3 +-
target/i386/cpu.h | 5 --
tar
[PATCH-for-10.1 14/43] target/microblaze: Restrict SoftMMU mmu_index() to TCG
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/microblaze/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index f3bebea856e..88baeb6807a 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -431,6 +431,7 @@ static const TCGCPUOps mb_tcg_ops = {
.translate_code = mb_translate_code,
.synchronize_from_tb = mb_cpu_synchronize_from_tb,
.restore_state_to_opc = mb_restore_state_to_opc,
+.mmu_index = mb_cpu_mmu_index,
#ifndef CONFIG_USER_ONLY
.tlb_fill = mb_cpu_tlb_fill,
@@ -455,7 +456,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
&mcc->parent_phases);
cc->class_by_name = mb_cpu_class_by_name;
-cc->mmu_index = mb_cpu_mmu_index;
cc->dump_state = mb_cpu_dump_state;
cc->set_pc = mb_cpu_set_pc;
cc->get_pc = mb_cpu_get_pc;
--
2.47.1
[PATCH-for-10.1 06/43] target/arm: Restrict SoftMMU mmu_index() to TCG
Move arm_cpu_mmu_index() within CONFIG_TCG #ifdef'ry
and expose its prototype in "target/arm/internals.h".
Convert CPUClass::mmu_index() to TCGCPUOps::mmu_index().
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/internals.h | 1 +
target/arm/cpu.c | 13 +++--
target/arm/tcg/cpu-v7m.c | 1 +
3 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 895d60218e3..01408e40a34 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -374,6 +374,7 @@ void arm_cpu_synchronize_from_tb(CPUState *cs, const
TranslationBlock *tb);
/* Our implementation of TCGCPUOps::cpu_exec_halt */
bool arm_cpu_exec_halt(CPUState *cs);
+int arm_cpu_mmu_index(CPUState *cs, bool ifetch);
#endif /* CONFIG_TCG */
typedef enum ARMFPRounding {
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index f29661938c4..c9e043bc9b5 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -122,6 +122,12 @@ void arm_restore_state_to_opc(CPUState *cs,
env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT;
}
}
+
+int arm_cpu_mmu_index(CPUState *cs, bool ifetch)
+{
+return arm_env_mmu_index(cpu_env(cs));
+}
+
#endif /* CONFIG_TCG */
#ifndef CONFIG_USER_ONLY
@@ -145,11 +151,6 @@ static bool arm_cpu_has_work(CPUState *cs)
}
#endif /* !CONFIG_USER_ONLY */
-static int arm_cpu_mmu_index(CPUState *cs, bool ifetch)
-{
-return arm_env_mmu_index(cpu_env(cs));
-}
-
void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
void *opaque)
{
@@ -2675,6 +2676,7 @@ static const TCGCPUOps arm_tcg_ops = {
.synchronize_from_tb = arm_cpu_synchronize_from_tb,
.debug_excp_handler = arm_debug_excp_handler,
.restore_state_to_opc = arm_restore_state_to_opc,
+.mmu_index = arm_cpu_mmu_index,
#ifdef CONFIG_USER_ONLY
.record_sigsegv = arm_cpu_record_sigsegv,
@@ -2709,7 +2711,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void
*data)
&acc->parent_phases);
cc->class_by_name = arm_cpu_class_by_name;
-cc->mmu_index = arm_cpu_mmu_index;
cc->dump_state = arm_cpu_dump_state;
cc->set_pc = arm_cpu_set_pc;
cc->get_pc = arm_cpu_get_pc;
diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c
index c4dd3092726..1a913faa50f 100644
--- a/target/arm/tcg/cpu-v7m.c
+++ b/target/arm/tcg/cpu-v7m.c
@@ -237,6 +237,7 @@ static const TCGCPUOps arm_v7m_tcg_ops = {
.synchronize_from_tb = arm_cpu_synchronize_from_tb,
.debug_excp_handler = arm_debug_excp_handler,
.restore_state_to_opc = arm_restore_state_to_opc,
+.mmu_index = arm_cpu_mmu_index,
#ifdef CONFIG_USER_ONLY
.record_sigsegv = arm_cpu_record_sigsegv,
--
2.47.1
[PATCH-for-10.1 13/43] target/m68k: Restrict SoftMMU mmu_index() to TCG
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/m68k/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 0065e1c1ca5..4409d8941ce 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -592,6 +592,7 @@ static const TCGCPUOps m68k_tcg_ops = {
.initialize = m68k_tcg_init,
.translate_code = m68k_translate_code,
.restore_state_to_opc = m68k_restore_state_to_opc,
+.mmu_index = m68k_cpu_mmu_index,
#ifndef CONFIG_USER_ONLY
.tlb_fill = m68k_cpu_tlb_fill,
@@ -615,7 +616,6 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
&mcc->parent_phases);
cc->class_by_name = m68k_cpu_class_by_name;
-cc->mmu_index = m68k_cpu_mmu_index;
cc->dump_state = m68k_cpu_dump_state;
cc->set_pc = m68k_cpu_set_pc;
cc->get_pc = m68k_cpu_get_pc;
--
2.47.1
[PATCH-for-10.1 37/43] tcg: Remove the TCG_GUEST_DEFAULT_MO definition globally
By directly using TCGCPUOps::guest_default_memory_order, we don't need the TCG_GUEST_DEFAULT_MO definition anymore. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- docs/devel/multi-thread-tcg.rst | 4 ++-- target/alpha/cpu-param.h| 3 --- target/arm/cpu-param.h | 3 --- target/avr/cpu-param.h | 2 -- target/hexagon/cpu-param.h | 3 --- target/hppa/cpu-param.h | 8 target/i386/cpu-param.h | 3 --- target/loongarch/cpu-param.h| 2 -- target/m68k/cpu-param.h | 3 --- target/microblaze/cpu-param.h | 3 --- target/mips/cpu-param.h | 2 -- target/openrisc/cpu-param.h | 2 -- target/ppc/cpu-param.h | 2 -- target/riscv/cpu-param.h| 2 -- target/rx/cpu-param.h | 3 --- target/s390x/cpu-param.h| 6 -- target/sh4/cpu-param.h | 3 --- target/sparc/cpu-param.h| 23 --- target/tricore/cpu-param.h | 3 --- target/xtensa/cpu-param.h | 3 --- target/alpha/cpu.c | 3 ++- target/arm/cpu.c| 3 ++- target/arm/tcg/cpu-v7m.c| 3 ++- target/avr/cpu.c| 2 +- target/hexagon/cpu.c| 3 ++- target/hppa/cpu.c | 8 +++- target/i386/tcg/tcg-cpu.c | 5 - target/loongarch/cpu.c | 2 +- target/m68k/cpu.c | 3 ++- target/microblaze/cpu.c | 3 ++- target/mips/cpu.c | 2 +- target/openrisc/cpu.c | 2 +- target/ppc/cpu_init.c | 2 +- target/riscv/tcg/tcg-cpu.c | 2 +- target/rx/cpu.c | 3 ++- target/s390x/cpu.c | 6 +- target/sh4/cpu.c| 3 ++- target/sparc/cpu.c | 23 ++- target/tricore/cpu.c| 3 ++- target/xtensa/cpu.c | 3 ++- 40 files changed, 66 insertions(+), 101 deletions(-) diff --git a/docs/devel/multi-thread-tcg.rst b/docs/devel/multi-thread-tcg.rst index b0f473961dd..14a2a9dc7b5 100644 --- a/docs/devel/multi-thread-tcg.rst +++ b/docs/devel/multi-thread-tcg.rst @@ -28,8 +28,8 @@ vCPU Scheduling We introduce a new running mode where each vCPU will run on its own user-space thread. This is enabled by default for all FE/BE combinations where the host memory model is able to accommodate the -guest (TCG_GUEST_DEFAULT_MO & ~TCG_TARGET_DEFAULT_MO is zero) and the -guest has had the required work done to support this safely +guest (TCGCPUOps::guest_default_memory_order & ~TCG_TARGET_DEFAULT_MO is zero) +and the guest has had the required work done to support this safely (TARGET_SUPPORTS_MTTCG). System emulation will fall back to the original round robin approach diff --git a/target/alpha/cpu-param.h b/target/alpha/cpu-param.h index dd44feb1793..a799f42db31 100644 --- a/target/alpha/cpu-param.h +++ b/target/alpha/cpu-param.h @@ -26,7 +26,4 @@ #define TARGET_INSN_START_EXTRA_WORDS 0 -/* Alpha processors have a weak memory model */ -#define TCG_GUEST_DEFAULT_MO (0) - #endif diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 2cee4be6938..5c5bc8a009e 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -44,7 +44,4 @@ */ #define TARGET_INSN_START_EXTRA_WORDS 2 -/* ARM processors have a weak memory model */ -#define TCG_GUEST_DEFAULT_MO (0) - #endif diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h index 9d37848d97d..f74bfc25804 100644 --- a/target/avr/cpu-param.h +++ b/target/avr/cpu-param.h @@ -27,6 +27,4 @@ #define TARGET_INSN_START_EXTRA_WORDS 0 -#define TCG_GUEST_DEFAULT_MO 0 - #endif diff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h index 7cc63a01d4b..635d509e743 100644 --- a/target/hexagon/cpu-param.h +++ b/target/hexagon/cpu-param.h @@ -25,7 +25,4 @@ #define TARGET_INSN_START_EXTRA_WORDS 0 -/* MTTCG not yet supported: require strict ordering */ -#define TCG_GUEST_DEFAULT_MOTCG_MO_ALL - #endif diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h index 68ed84e84af..9bf7ac76d0c 100644 --- a/target/hppa/cpu-param.h +++ b/target/hppa/cpu-param.h @@ -21,12 +21,4 @@ #define TARGET_INSN_START_EXTRA_WORDS 2 -/* PA-RISC 1.x processors have a strong memory model. */ -/* - * ??? While we do not yet implement PA-RISC 2.0, those processors have - * a weak memory model, but with TLB bits that force ordering on a per-page - * basis. It's probably easier to fall back to a strong memory model. - */ -#define TCG_GUEST_DEFAULT_MOTCG_MO_ALL - #endif diff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.h index 0c8efce8619..ebb844bcc83 100644 --- a/target/i386/cpu-param.h +++ b/target/i386/cpu-param.h @@ -24,7 +24,4 @@ #define TARGET_INSN_START_EXTRA_WORDS 1 -/* The x86 has a strong memory model with some store-after-load re-ordering */ -#define TCG_GUEST_DEFAUL
[PATCH-for-10.1 38/43] tcg: Move cpu_req_mo() macro to target-agnostic 'backend-ldst.h'
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/backend-ldst.h| 41 +
accel/tcg/internal-common.h | 27
accel/tcg/internal-target.h | 28 -
accel/tcg/cputlb.c | 1 +
accel/tcg/user-exec.c | 1 +
5 files changed, 70 insertions(+), 28 deletions(-)
create mode 100644 accel/tcg/backend-ldst.h
diff --git a/accel/tcg/backend-ldst.h b/accel/tcg/backend-ldst.h
new file mode 100644
index 000..9c3a407a5af
--- /dev/null
+++ b/accel/tcg/backend-ldst.h
@@ -0,0 +1,41 @@
+/*
+ * Internal memory barrier helpers for QEMU (target agnostic)
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+
+#ifndef ACCEL_TCG_BACKEND_LDST_H
+#define ACCEL_TCG_BACKEND_LDST_H
+
+#include "tcg-target-mo.h"
+
+/**
+ * tcg_req_mo:
+ * @guest_mo: Guest default memory order
+ * @type: TCGBar
+ *
+ * Filter @type to the barrier that is required for the guest
+ * memory ordering vs the host memory ordering. A non-zero
+ * result indicates that some barrier is required.
+ */
+#define tcg_req_mo(guest_mo, type) \
+((type) & guest_mo & ~TCG_TARGET_DEFAULT_MO)
+
+/**
+ * cpu_req_mo:
+ * @cpu: CPUState
+ * @type: TCGBar
+ *
+ * If tcg_req_mo indicates a barrier for @type is required
+ * for the guest memory model, issue a host memory barrier.
+ */
+#define cpu_req_mo(cpu, type) \
+do { \
+if (tcg_req_mo(cpu->cc->tcg_ops->guest_default_memory_order, type)) { \
+smp_mb(); \
+} \
+} while (0)
+
+#endif
diff --git a/accel/tcg/internal-common.h b/accel/tcg/internal-common.h
index 2f00560d102..829ae9389d2 100644
--- a/accel/tcg/internal-common.h
+++ b/accel/tcg/internal-common.h
@@ -108,4 +108,31 @@ static inline tb_page_addr_t
get_page_addr_code(CPUArchState *env,
return get_page_addr_code_hostp(env, addr, NULL);
}
+/**
+ * tcg_req_mo:
+ * @guest_mo: Guest default memory order
+ * @type: TCGBar
+ *
+ * Filter @type to the barrier that is required for the guest
+ * memory ordering vs the host memory ordering. A non-zero
+ * result indicates that some barrier is required.
+ */
+#define tcg_req_mo(guest_mo, type) \
+((type) & guest_mo & ~TCG_TARGET_DEFAULT_MO)
+
+/**
+ * cpu_req_mo:
+ * @cpu: CPUState
+ * @type: TCGBar
+ *
+ * If tcg_req_mo indicates a barrier for @type is required
+ * for the guest memory model, issue a host memory barrier.
+ */
+#define cpu_req_mo(cpu, type) \
+do { \
+if (tcg_req_mo(cpu->cc->tcg_ops->guest_default_memory_order, type)) { \
+smp_mb(); \
+} \
+} while (0)
+
#endif
diff --git a/accel/tcg/internal-target.h b/accel/tcg/internal-target.h
index f5a3fd7e402..9a9cef31406 100644
--- a/accel/tcg/internal-target.h
+++ b/accel/tcg/internal-target.h
@@ -13,7 +13,6 @@
#include "exec/exec-all.h"
#include "exec/translation-block.h"
#include "tb-internal.h"
-#include "tcg-target-mo.h"
#include "exec/mmap-lock.h"
/*
@@ -44,31 +43,4 @@ void page_table_config_init(void);
G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
#endif /* CONFIG_USER_ONLY */
-/**
- * tcg_req_mo:
- * @guest_mo: Guest default memory order
- * @type: TCGBar
- *
- * Filter @type to the barrier that is required for the guest
- * memory ordering vs the host memory ordering. A non-zero
- * result indicates that some barrier is required.
- */
-#define tcg_req_mo(guest_mo, type) \
-((type) & guest_mo & ~TCG_TARGET_DEFAULT_MO)
-
-/**
- * cpu_req_mo:
- * @cpu: CPUState
- * @type: TCGBar
- *
- * If tcg_req_mo indicates a barrier for @type is required
- * for the guest memory model, issue a host memory barrier.
- */
-#define cpu_req_mo(cpu, type) \
-do { \
-if (tcg_req_mo(cpu->cc->tcg_ops->guest_default_memory_order, type)) { \
-smp_mb(); \
-} \
-} while (0)
-
#endif /* ACCEL_TCG_INTERNAL_H */
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 35b1ff03a51..d9fb68d7198 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -48,6 +48,7 @@
#include "qemu/plugin-memory.h"
#endif
#include "tcg/tcg-ldst.h"
+#include "backend-ldst.h"
/* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 3f4d6824460..5eef8e7f186 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -37,6 +37,7 @@
#include "qemu/int128.h"
#include "trace.h"
#include "tcg/tcg-ldst.h"
+#include "backend-ldst.h"
#include "internal-common.h"
#include "internal-target.h"
#include "tb-internal.h"
--
2.47.1
[PATCH-for-10.1 40/43] tcg: Convert TCGState::mttcg_enabled to TriState
Use the OnOffAuto type as 3-state.
Since the TCGState instance is zero-initialized, the
mttcg_enabled is initialzed as AUTO (ON_OFF_AUTO_AUTO).
In tcg_init_machine(), if mttcg_enabled is still AUTO,
set a default value (effectively inlining the
default_mttcg_enabled() method content).
Instead of emiting a warning when the 'thread' property
is set in tcg_set_thread(), emit it in tcg_init_machine()
where it is consumed. This is in preparation of the
next commit where we replace the TARGET_SUPPORTS_MTTCG
definition by getting the value at runtime via
CPUState -> CPUClass -> TCGCPUOps -> mttcg_supported,
so we need an initialized CPUState -- which is not
possible at instance_init time).
In the tcg_get_thread() getter, consider AUTO / OFF states
as "single", otherwise ON is "multi".
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Anton Johansson
---
accel/tcg/tcg-all.c | 68 ++---
1 file changed, 33 insertions(+), 35 deletions(-)
diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c
index b8874430d30..ae3a137e87f 100644
--- a/accel/tcg/tcg-all.c
+++ b/accel/tcg/tcg-all.c
@@ -32,6 +32,7 @@
#include "qemu/error-report.h"
#include "qemu/accel.h"
#include "qemu/atomic.h"
+#include "qapi/qapi-types-common.h"
#include "qapi/qapi-builtin-visit.h"
#include "qemu/units.h"
#if defined(CONFIG_USER_ONLY)
@@ -47,7 +48,7 @@
struct TCGState {
AccelState parent_obj;
-bool mttcg_enabled;
+OnOffAuto mttcg_enabled;
bool one_insn_per_tb;
int splitwx_enabled;
unsigned long tb_size;
@@ -70,37 +71,10 @@ bool qemu_tcg_mttcg_enabled(void)
#endif /* !CONFIG_USER_ONLY */
-/*
- * We default to false if we know other options have been enabled
- * which are currently incompatible with MTTCG. Otherwise when each
- * guest (target) has been updated to support:
- * - atomic instructions
- * - memory ordering primitives (barriers)
- * they can set the appropriate CONFIG flags in ${target}-softmmu.mak
- *
- * Once a guest architecture has been converted to the new primitives
- * there is one remaining limitation to check:
- * - The guest can't be oversized (e.g. 64 bit guest on 32 bit host)
- */
-
-static bool default_mttcg_enabled(void)
-{
-if (icount_enabled()) {
-return false;
-}
-#ifdef TARGET_SUPPORTS_MTTCG
-return true;
-#else
-return false;
-#endif
-}
-
static void tcg_accel_instance_init(Object *obj)
{
TCGState *s = TCG_STATE(obj);
-s->mttcg_enabled = default_mttcg_enabled();
-
/* If debugging enabled, default "auto on", otherwise off. */
#if defined(CONFIG_DEBUG_TCG) && !defined(CONFIG_USER_ONLY)
s->splitwx_enabled = -1;
@@ -118,7 +92,35 @@ static int tcg_init_machine(MachineState *ms)
unsigned max_cpus = 1;
#else
unsigned max_cpus = ms->smp.max_cpus;
+#ifdef TARGET_SUPPORTS_MTTCG
+bool mttcg_supported = true;
+#else
+bool mttcg_supported = false;
+#endif
+if (s->mttcg_enabled == ON_OFF_AUTO_AUTO) {
+/*
+ * We default to false if we know other options have been enabled
+ * which are currently incompatible with MTTCG. Otherwise when each
+ * guest (target) has been updated to support:
+ * - atomic instructions
+ * - memory ordering primitives (barriers)
+ * they can set the appropriate CONFIG flags in ${target}-softmmu.mak
+ *
+ * Once a guest architecture has been converted to the new primitives
+ * there is one remaining limitation to check:
+ * - The guest can't be oversized (e.g. 64 bit guest on 32 bit host)
+ */
+if (icount_enabled()) {
+s->mttcg_enabled = ON_OFF_AUTO_OFF;
+} else {
+s->mttcg_enabled = mttcg_supported;
+}
+}
+if (s->mttcg_enabled == ON_OFF_AUTO_ON && !mttcg_supported) {
+warn_report("Guest not yet converted to MTTCG - "
+"you may get unexpected results");
+}
mttcg_enabled = s->mttcg_enabled;
#endif
@@ -147,7 +149,7 @@ static char *tcg_get_thread(Object *obj, Error **errp)
{
TCGState *s = TCG_STATE(obj);
-return g_strdup(s->mttcg_enabled ? "multi" : "single");
+return g_strdup(s->mttcg_enabled == ON_OFF_AUTO_ON ? "multi" : "single");
}
static void tcg_set_thread(Object *obj, const char *value, Error **errp)
@@ -158,14 +160,10 @@ static void tcg_set_thread(Object *obj, const char
*value, Error **errp)
if (icount_enabled()) {
error_setg(errp, "No MTTCG when icount is enabled");
} else {
-#ifndef TARGET_SUPPORTS_MTTCG
-warn_report("Guest not yet converted to MTTCG - "
-"you may get unexpected results");
-#endif
-s->mttcg_enabled = true;
+s->mttcg_enabled = ON_OFF_AUTO_ON;
}
} else if (strcmp(value, "single") == 0) {
-s->mttcg_enabled = false;
+s->mttcg_enabled = ON_OFF_AUTO_OFF;
} else {
error_setg(err
[PATCH-for-10.1 24/43] target/tricore: Restrict SoftMMU mmu_index() to TCG
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/tricore/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 16acc4ecb92..833a93d37af 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -176,6 +176,7 @@ static const TCGCPUOps tricore_tcg_ops = {
.translate_code = tricore_translate_code,
.synchronize_from_tb = tricore_cpu_synchronize_from_tb,
.restore_state_to_opc = tricore_restore_state_to_opc,
+.mmu_index = tricore_cpu_mmu_index,
.tlb_fill = tricore_cpu_tlb_fill,
.cpu_exec_interrupt = tricore_cpu_exec_interrupt,
.cpu_exec_halt = tricore_cpu_has_work,
@@ -194,7 +195,6 @@ static void tricore_cpu_class_init(ObjectClass *c, void
*data)
resettable_class_set_parent_phases(rc, NULL, tricore_cpu_reset_hold, NULL,
&mcc->parent_phases);
cc->class_by_name = tricore_cpu_class_by_name;
-cc->mmu_index = tricore_cpu_mmu_index;
cc->gdb_read_register = tricore_cpu_gdb_read_register;
cc->gdb_write_register = tricore_cpu_gdb_write_register;
--
2.47.1
[PATCH-for-10.1 34/43] tcg: Remove use of TCG_GUEST_DEFAULT_MO in tb_gen_code()
Use TCGCPUOps::guest_default_memory_order to set TCGContext::guest_mo. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- accel/tcg/translate-all.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index cb1cf270888..9a9ee0502ea 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -352,7 +352,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tcg_ctx->tlb_dyn_max_bits = CPU_TLB_DYN_MAX_BITS; #endif tcg_ctx->insn_start_words = TARGET_INSN_START_WORDS; -tcg_ctx->guest_mo = TCG_GUEST_DEFAULT_MO; +tcg_ctx->guest_mo = cpu->cc->tcg_ops->guest_default_memory_order; restart_translate: trace_translate_block(tb, pc, tb->tc.ptr); -- 2.47.1
[PATCH-for-10.1 09/43] target/i386: Remove unused cpu_(ldub, stb)_kernel macros
Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/i386/tcg/seg_helper.h | 6 -- 1 file changed, 6 deletions(-) diff --git a/target/i386/tcg/seg_helper.h b/target/i386/tcg/seg_helper.h index ebf10352778..6b8606cd6d8 100644 --- a/target/i386/tcg/seg_helper.h +++ b/target/i386/tcg/seg_helper.h @@ -35,8 +35,6 @@ * TODO: Convert callers to compute cpu_mmu_index_kernel once * and use *_mmuidx_ra directly. */ -#define cpu_ldub_kernel_ra(e, p, r) \ -cpu_ldub_mmuidx_ra(e, p, cpu_mmu_index_kernel(e), r) #define cpu_lduw_kernel_ra(e, p, r) \ cpu_lduw_mmuidx_ra(e, p, cpu_mmu_index_kernel(e), r) #define cpu_ldl_kernel_ra(e, p, r) \ @@ -44,8 +42,6 @@ #define cpu_ldq_kernel_ra(e, p, r) \ cpu_ldq_mmuidx_ra(e, p, cpu_mmu_index_kernel(e), r) -#define cpu_stb_kernel_ra(e, p, v, r) \ -cpu_stb_mmuidx_ra(e, p, v, cpu_mmu_index_kernel(e), r) #define cpu_stw_kernel_ra(e, p, v, r) \ cpu_stw_mmuidx_ra(e, p, v, cpu_mmu_index_kernel(e), r) #define cpu_stl_kernel_ra(e, p, v, r) \ @@ -53,12 +49,10 @@ #define cpu_stq_kernel_ra(e, p, v, r) \ cpu_stq_mmuidx_ra(e, p, v, cpu_mmu_index_kernel(e), r) -#define cpu_ldub_kernel(e, p)cpu_ldub_kernel_ra(e, p, 0) #define cpu_lduw_kernel(e, p)cpu_lduw_kernel_ra(e, p, 0) #define cpu_ldl_kernel(e, p) cpu_ldl_kernel_ra(e, p, 0) #define cpu_ldq_kernel(e, p) cpu_ldq_kernel_ra(e, p, 0) -#define cpu_stb_kernel(e, p, v) cpu_stb_kernel_ra(e, p, v, 0) #define cpu_stw_kernel(e, p, v) cpu_stw_kernel_ra(e, p, v, 0) #define cpu_stl_kernel(e, p, v) cpu_stl_kernel_ra(e, p, v, 0) #define cpu_stq_kernel(e, p, v) cpu_stq_kernel_ra(e, p, v, 0) -- 2.47.1
[PATCH-for-10.1 35/43] tcg: Propagate CPUState argument to cpu_req_mo()
In preparation of having tcg_req_mo() access CPUState in
the next commit, pass it to cpu_req_mo(), its single caller.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
accel/tcg/internal-target.h | 3 ++-
accel/tcg/cputlb.c | 20 ++--
accel/tcg/user-exec.c | 20 ++--
3 files changed, 22 insertions(+), 21 deletions(-)
diff --git a/accel/tcg/internal-target.h b/accel/tcg/internal-target.h
index 1a46a7c87dc..23aac39b572 100644
--- a/accel/tcg/internal-target.h
+++ b/accel/tcg/internal-target.h
@@ -59,12 +59,13 @@ G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr_t
retaddr);
/**
* cpu_req_mo:
+ * @cpu: CPUState
* @type: TCGBar
*
* If tcg_req_mo indicates a barrier for @type is required
* for the guest memory model, issue a host memory barrier.
*/
-#define cpu_req_mo(type) \
+#define cpu_req_mo(cpu, type) \
do { \
if (tcg_req_mo(type)) { \
smp_mb(); \
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 2cafd38d2af..35b1ff03a51 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -2324,7 +2324,7 @@ static uint8_t do_ld1_mmu(CPUState *cpu, vaddr addr,
MemOpIdx oi,
MMULookupLocals l;
bool crosspage;
-cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
+cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD);
crosspage = mmu_lookup(cpu, addr, oi, ra, access_type, &l);
tcg_debug_assert(!crosspage);
@@ -2339,7 +2339,7 @@ static uint16_t do_ld2_mmu(CPUState *cpu, vaddr addr,
MemOpIdx oi,
uint16_t ret;
uint8_t a, b;
-cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
+cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD);
crosspage = mmu_lookup(cpu, addr, oi, ra, access_type, &l);
if (likely(!crosspage)) {
return do_ld_2(cpu, &l.page[0], l.mmu_idx, access_type, l.memop, ra);
@@ -2363,7 +2363,7 @@ static uint32_t do_ld4_mmu(CPUState *cpu, vaddr addr,
MemOpIdx oi,
bool crosspage;
uint32_t ret;
-cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
+cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD);
crosspage = mmu_lookup(cpu, addr, oi, ra, access_type, &l);
if (likely(!crosspage)) {
return do_ld_4(cpu, &l.page[0], l.mmu_idx, access_type, l.memop, ra);
@@ -2384,7 +2384,7 @@ static uint64_t do_ld8_mmu(CPUState *cpu, vaddr addr,
MemOpIdx oi,
bool crosspage;
uint64_t ret;
-cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
+cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD);
crosspage = mmu_lookup(cpu, addr, oi, ra, access_type, &l);
if (likely(!crosspage)) {
return do_ld_8(cpu, &l.page[0], l.mmu_idx, access_type, l.memop, ra);
@@ -2407,7 +2407,7 @@ static Int128 do_ld16_mmu(CPUState *cpu, vaddr addr,
Int128 ret;
int first;
-cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD);
+cpu_req_mo(cpu, TCG_MO_LD_LD | TCG_MO_ST_LD);
crosspage = mmu_lookup(cpu, addr, oi, ra, MMU_DATA_LOAD, &l);
if (likely(!crosspage)) {
if (unlikely(l.page[0].flags & TLB_MMIO)) {
@@ -2735,7 +2735,7 @@ static void do_st1_mmu(CPUState *cpu, vaddr addr, uint8_t
val,
MMULookupLocals l;
bool crosspage;
-cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
+cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST);
crosspage = mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l);
tcg_debug_assert(!crosspage);
@@ -2749,7 +2749,7 @@ static void do_st2_mmu(CPUState *cpu, vaddr addr,
uint16_t val,
bool crosspage;
uint8_t a, b;
-cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
+cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST);
crosspage = mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l);
if (likely(!crosspage)) {
do_st_2(cpu, &l.page[0], val, l.mmu_idx, l.memop, ra);
@@ -2771,7 +2771,7 @@ static void do_st4_mmu(CPUState *cpu, vaddr addr,
uint32_t val,
MMULookupLocals l;
bool crosspage;
-cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
+cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST);
crosspage = mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l);
if (likely(!crosspage)) {
do_st_4(cpu, &l.page[0], val, l.mmu_idx, l.memop, ra);
@@ -2792,7 +2792,7 @@ static void do_st8_mmu(CPUState *cpu, vaddr addr,
uint64_t val,
MMULookupLocals l;
bool crosspage;
-cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
+cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST);
crosspage = mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l);
if (likely(!crosspage)) {
do_st_8(cpu, &l.page[0], val, l.mmu_idx, l.memop, ra);
@@ -2815,7 +2815,7 @@ static void do_st16_mmu(CPUState *cpu, vaddr addr, Int128
val,
uint64_t a, b;
int first;
-cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
+cpu_req_mo(cpu, TCG_MO_LD_ST | TCG_MO_ST_ST);
crosspage = mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l);
if (likely(!crosspage)) {
if (unlikely(l.page[0].flags & TLB_MMIO)) {
diff --git a/accel/tcg/user-exec.c
[PATCH-for-10.1 16/43] target/openrisc: Restrict SoftMMU mmu_index() to TCG
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/openrisc/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index e8abf1f8b5c..dc55594a7de 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -247,6 +247,7 @@ static const TCGCPUOps openrisc_tcg_ops = {
.translate_code = openrisc_translate_code,
.synchronize_from_tb = openrisc_cpu_synchronize_from_tb,
.restore_state_to_opc = openrisc_restore_state_to_opc,
+.mmu_index = openrisc_cpu_mmu_index,
#ifndef CONFIG_USER_ONLY
.tlb_fill = openrisc_cpu_tlb_fill,
@@ -269,7 +270,6 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void
*data)
&occ->parent_phases);
cc->class_by_name = openrisc_cpu_class_by_name;
-cc->mmu_index = openrisc_cpu_mmu_index;
cc->dump_state = openrisc_cpu_dump_state;
cc->set_pc = openrisc_cpu_set_pc;
cc->get_pc = openrisc_cpu_get_pc;
--
2.47.1
[PATCH-for-10.1 27/43] exec: Restrict cpu-mmu-index.h to accel/tcg/
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
include/{exec => accel/tcg}/cpu-mmu-index.h | 6 +++---
include/exec/cpu_ldst.h | 2 +-
accel/tcg/translator.c | 2 +-
semihosting/uaccess.c | 2 +-
target/arm/gdbstub64.c | 2 +-
target/hppa/mem_helper.c| 2 +-
target/i386/tcg/translate.c | 2 +-
target/loongarch/cpu_helper.c | 2 +-
target/microblaze/helper.c | 2 +-
target/microblaze/mmu.c | 2 +-
target/openrisc/translate.c | 2 +-
target/sparc/cpu.c | 2 +-
target/sparc/mmu_helper.c | 2 +-
target/tricore/helper.c | 2 +-
target/xtensa/mmu_helper.c | 2 +-
15 files changed, 17 insertions(+), 17 deletions(-)
rename include/{exec => accel/tcg}/cpu-mmu-index.h (87%)
diff --git a/include/exec/cpu-mmu-index.h b/include/accel/tcg/cpu-mmu-index.h
similarity index 87%
rename from include/exec/cpu-mmu-index.h
rename to include/accel/tcg/cpu-mmu-index.h
index a87b6f7c4b7..3699c18b4cb 100644
--- a/include/exec/cpu-mmu-index.h
+++ b/include/accel/tcg/cpu-mmu-index.h
@@ -6,8 +6,8 @@
* SPDX-License-Identifier: LGPL-2.1-or-later
*/
-#ifndef EXEC_CPU_MMU_INDEX_H
-#define EXEC_CPU_MMU_INDEX_H
+#ifndef ACCEL_TCG_CPU_MMU_INDEX_H
+#define ACCEL_TCG_CPU_MMU_INDEX_H
#include "hw/core/cpu.h"
#include "accel/tcg/cpu-ops.h"
@@ -37,4 +37,4 @@ static inline int cpu_mmu_index(CPUState *cs, bool ifetch)
return ret;
}
-#endif /* EXEC_CPU_MMU_INDEX_H */
+#endif /* ACCEL_TCG_CPU_MMU_INDEX_H */
diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
index 313100fcda1..63847f6e618 100644
--- a/include/exec/cpu_ldst.h
+++ b/include/exec/cpu_ldst.h
@@ -68,7 +68,7 @@
#include "exec/cpu-common.h"
#include "exec/cpu-ldst-common.h"
-#include "exec/cpu-mmu-index.h"
+#include "accel/tcg/cpu-mmu-index.h"
#include "exec/abi_ptr.h"
#if defined(CONFIG_USER_ONLY)
diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c
index 36a6a9e0408..c53bbdef99f 100644
--- a/accel/tcg/translator.c
+++ b/accel/tcg/translator.c
@@ -12,7 +12,7 @@
#include "qemu/log.h"
#include "qemu/error-report.h"
#include "exec/cpu-ldst-common.h"
-#include "exec/cpu-mmu-index.h"
+#include "accel/tcg/cpu-mmu-index.h"
#include "exec/target_page.h"
#include "exec/translator.h"
#include "exec/plugin-gen.h"
diff --git a/semihosting/uaccess.c b/semihosting/uaccess.c
index 92b2421dce5..81ffecaaba4 100644
--- a/semihosting/uaccess.c
+++ b/semihosting/uaccess.c
@@ -8,7 +8,7 @@
*/
#include "qemu/osdep.h"
-#include "exec/cpu-mmu-index.h"
+#include "accel/tcg/cpu-mmu-index.h"
#include "exec/exec-all.h"
#include "exec/target_page.h"
#include "exec/tlb-flags.h"
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
index 3bbca4cbb98..64ee9b3b567 100644
--- a/target/arm/gdbstub64.c
+++ b/target/arm/gdbstub64.c
@@ -28,7 +28,7 @@
#include "mte_user_helper.h"
#endif
#ifdef CONFIG_TCG
-#include "exec/cpu-mmu-index.h"
+#include "accel/tcg/cpu-mmu-index.h"
#include "exec/target_page.h"
#endif
diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c
index df4e35f4de6..554d7bf4d14 100644
--- a/target/hppa/mem_helper.c
+++ b/target/hppa/mem_helper.c
@@ -22,7 +22,7 @@
#include "cpu.h"
#include "exec/exec-all.h"
#include "exec/cputlb.h"
-#include "exec/cpu-mmu-index.h"
+#include "accel/tcg/cpu-mmu-index.h"
#include "exec/page-protection.h"
#include "exec/target_page.h"
#include "exec/helper-proto.h"
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 7e6d1ef9379..ca49f8d6dcb 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -20,7 +20,7 @@
#include "qemu/host-utils.h"
#include "cpu.h"
-#include "exec/cpu-mmu-index.h"
+#include "accel/tcg/cpu-mmu-index.h"
#include "exec/exec-all.h"
#include "exec/translation-block.h"
#include "tcg/tcg-op.h"
diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c
index 4597e29b153..bb343078bf7 100644
--- a/target/loongarch/cpu_helper.c
+++ b/target/loongarch/cpu_helper.c
@@ -8,7 +8,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
-#include "exec/cpu-mmu-index.h"
+#include "accel/tcg/cpu-mmu-index.h"
#include "exec/target_page.h"
#include "internals.h"
#include "cpu-csr.h"
diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
index 9e6969ccc9a..92031924830 100644
--- a/target/microblaze/helper.c
+++ b/target/microblaze/helper.c
@@ -21,7 +21,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/cputlb.h"
-#include "exec/cpu-mmu-index.h"
+#include "accel/tcg/cpu-mmu-index.h"
#include "exec/page-protection.h"
#include "exec/target_page.h"
#include "qemu/host-utils.h"
diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c
index 7f20c4e4c69..95a12e16f8e 100644
--- a/target/microblaze/mmu.c
+++ b/t
[PATCH-for-10.1 11/43] target/i386: Restrict SoftMMU mmu_index() to TCG
Move x86_cpu_mmu_index() to tcg-cpu.c, convert
CPUClass::mmu_index() to TCGCPUOps::mmu_index().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
target/i386/cpu.h| 2 --
target/i386/tcg/tcg-cpu.h| 2 ++
target/i386/cpu.c| 18 --
target/i386/tcg/seg_helper.c | 1 +
target/i386/tcg/tcg-cpu.c| 18 ++
5 files changed, 21 insertions(+), 20 deletions(-)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index a557dccf3e2..16d76df34b2 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -2595,8 +2595,6 @@ static inline bool is_mmu_index_32(int mmu_index)
return mmu_index & 1;
}
-int x86_mmu_index_pl(CPUX86State *env, unsigned pl);
-
#define CC_DST (env->cc_dst)
#define CC_SRC (env->cc_src)
#define CC_SRC2 (env->cc_src2)
diff --git a/target/i386/tcg/tcg-cpu.h b/target/i386/tcg/tcg-cpu.h
index 53a84944551..7580f8afb4f 100644
--- a/target/i386/tcg/tcg-cpu.h
+++ b/target/i386/tcg/tcg-cpu.h
@@ -78,4 +78,6 @@ QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) !=
XSAVE_PKRU_OFFSET);
bool tcg_cpu_realizefn(CPUState *cs, Error **errp);
+int x86_mmu_index_pl(CPUX86State *env, unsigned pl);
+
#endif /* TCG_CPU_H */
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 0b74b9a3754..d930ebd262e 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -8652,23 +8652,6 @@ static bool x86_cpu_has_work(CPUState *cs)
}
#endif /* !CONFIG_USER_ONLY */
-int x86_mmu_index_pl(CPUX86State *env, unsigned pl)
-{
-int mmu_index_32 = (env->hflags & HF_CS64_MASK) ? 0 : 1;
-int mmu_index_base =
-pl == 3 ? MMU_USER64_IDX :
-!(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX :
-(env->eflags & AC_MASK) ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX;
-
-return mmu_index_base + mmu_index_32;
-}
-
-static int x86_cpu_mmu_index(CPUState *cs, bool ifetch)
-{
-CPUX86State *env = cpu_env(cs);
-return x86_mmu_index_pl(env, env->hflags & HF_CPL_MASK);
-}
-
static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
{
X86CPU *cpu = X86_CPU(cs);
@@ -8910,7 +8893,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc,
void *data)
cc->class_by_name = x86_cpu_class_by_name;
cc->parse_features = x86_cpu_parse_featurestr;
-cc->mmu_index = x86_cpu_mmu_index;
cc->dump_state = x86_cpu_dump_state;
cc->set_pc = x86_cpu_set_pc;
cc->get_pc = x86_cpu_get_pc;
diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c
index f4370202fed..9dfbc4208cd 100644
--- a/target/i386/tcg/seg_helper.c
+++ b/target/i386/tcg/seg_helper.c
@@ -28,6 +28,7 @@
#include "helper-tcg.h"
#include "seg_helper.h"
#include "access.h"
+#include "tcg-cpu.h"
#ifdef TARGET_X86_64
#define SET_ESP(val, sp_mask) \
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
index 36b8dc78a3e..35b17f2b183 100644
--- a/target/i386/tcg/tcg-cpu.c
+++ b/target/i386/tcg/tcg-cpu.c
@@ -94,6 +94,23 @@ static void x86_restore_state_to_opc(CPUState *cs,
}
}
+int x86_mmu_index_pl(CPUX86State *env, unsigned pl)
+{
+int mmu_index_32 = (env->hflags & HF_CS64_MASK) ? 0 : 1;
+int mmu_index_base =
+pl == 3 ? MMU_USER64_IDX :
+!(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP64_IDX :
+(env->eflags & AC_MASK) ? MMU_KNOSMAP64_IDX : MMU_KSMAP64_IDX;
+
+return mmu_index_base + mmu_index_32;
+}
+
+static int x86_cpu_mmu_index(CPUState *cs, bool ifetch)
+{
+CPUX86State *env = cpu_env(cs);
+return x86_mmu_index_pl(env, env->hflags & HF_CPL_MASK);
+}
+
#ifndef CONFIG_USER_ONLY
static bool x86_debug_check_breakpoint(CPUState *cs)
{
@@ -112,6 +129,7 @@ static const TCGCPUOps x86_tcg_ops = {
.translate_code = x86_translate_code,
.synchronize_from_tb = x86_cpu_synchronize_from_tb,
.restore_state_to_opc = x86_restore_state_to_opc,
+.mmu_index = x86_cpu_mmu_index,
.cpu_exec_enter = x86_cpu_exec_enter,
.cpu_exec_exit = x86_cpu_exec_exit,
#ifdef CONFIG_USER_ONLY
--
2.47.1
[PATCH-for-10.1 03/43] hw/core/cpu: Update CPUClass::mmu_index docstring
Since commits 32a8ea12fab..90b7022e698 (target: "Split out TARGET_env_mmu_index"), target's memory_rw_debug() callbacks use the target's TARGET_env_mmu_index(), not the generic CPUClass::mmu_index() callback. Update the documentation. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/hw/core/cpu.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 84a71d8cf17..60b7abaf49b 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -104,8 +104,7 @@ struct SysemuCPUOps; * instantiatable CPU type. * @parse_features: Callback to parse command line arguments. * @reset_dump_flags: #CPUDumpFlags to use for reset logging. - * @mmu_index: Callback for choosing softmmu mmu index; - * may be used internally by memory_rw_debug without TCG. + * @mmu_index: Callback for choosing softmmu mmu index. * @memory_rw_debug: Callback for GDB memory access. * @dump_state: Callback for dumping state. * @query_cpu_fast: -- 2.47.1
