[PATCH 0/8] ACPI: X86 AML generation and GPE tracing cleanup

[Bernhard Beschow]

This series contains changes from my effort to bring the VIA south bridges to
the PC machine [1]. The first part of the series resolves the
AcpiCpuAmlIfClass::madt_cpu virtual method which frees ACPI controllers from
worrying about CPU AML generation. The second part minimizes an Intel-specific
assumption in AML generation to just one place. The third part contains two
ACPI tracing patches which have been reviewed a long time ago but weren't merged
yet.

The removal of AcpiCpuAmlIfClass::madt_cpu is essentially a respin of [2] with
a different approach. Igor wasn't generally against it but wasn't convinced
either [3]. The new approach causes much less churn and instead allows to
remove code. So I think it's worth to be reconsidered.

The motivation for removing this virtual method didn't change: It frees the ACPI
controllers in general and PIIX4 PM in particular from generating X86 CPU AML.
The latter is also used in MPIS context where X86 CPU AML generation is
stubbed out. This indicates a design issue where a problem was solved at the
wrong place. Moreover, it turned out that TYPE_ACPI_GED_X86 could be removed as
well, further supporting this claim.

The second part of this series limits SMI command port determination during AML
generation to just one place. Currently the ACPI_PORT_SMI_CMD constant is used
multiple times which has an Intel-specific value. In order to make the code a
microscopic bit more compatible with our VIA south bridge models its usage gets
limited to one place, allowing the constant to be turned into a device model
property in the future.

The third part improves the tracing experience for ACPI general purpose events.
It originates from an old series: [4].

Testing done:
* `make check`
* `make check-avocado`
* `qemu-system-ppc -machine pegasos2 -rtc base=localtime \
   -device ati-vga,guest_hwcursor=true,romfile=""
   -cdrom morphos-3.18.iso -bios pegasos2.rom`

[1] https://github.com/shentok/qemu/tree/pc-via
[2] https://lore.kernel.org/qemu-devel/20230121151941.24120-1-shen...@gmail.com/
[3] 
https://lore.kernel.org/qemu-devel/20230125174842.395fd...@imammedo.users.ipa.redhat.com/
[4] https://patchew.org/QEMU/20230122170724.21868-1-shen...@gmail.com/

Bernhard Beschow (8):
  hw/i386/acpi-build: Use pc_madt_cpu_entry() directly
  hw/acpi/cpu: Have build_cpus_aml() take a build_madt_cpu_fn callback
  hw/acpi/acpi_dev_interface: Remove now unused madt_cpu virtual method
  hw/acpi/acpi_dev_interface: Remove now unused #include "hw/boards.h"
  hw/i386: Remove now redundant TYPE_ACPI_GED_X86
  hw/i386/acpi-build: Determine SMI command port just once
  hw/acpi: Trace GPE access in all device models, not just PIIX4
  hw/acpi/core: Trace enable and status registers of GPE separately

 hw/acpi/hmat.h |  3 ++-
 hw/i386/acpi-common.h  |  3 +--
 include/hw/acpi/acpi_dev_interface.h   |  3 ---
 include/hw/acpi/cpu.h  |  6 -
 include/hw/acpi/generic_event_device.h |  2 --
 hw/acpi/acpi-x86-stub.c|  6 -
 hw/acpi/core.c |  9 +++
 hw/acpi/cpu.c  |  9 +++
 hw/acpi/hmat.c |  1 +
 hw/acpi/memory_hotplug.c   |  1 +
 hw/acpi/piix4.c|  5 
 hw/i386/acpi-build.c   | 13 +-
 hw/i386/acpi-common.c  |  5 ++--
 hw/i386/acpi-microvm.c |  3 +--
 hw/i386/generic_event_device_x86.c | 36 --
 hw/i386/microvm.c  |  2 +-
 hw/isa/lpc_ich9.c  |  1 -
 hw/acpi/trace-events   | 10 ---
 hw/i386/meson.build|  1 -
 19 files changed, 38 insertions(+), 81 deletions(-)
 delete mode 100644 hw/i386/generic_event_device_x86.c

-- 
2.42.0

[PATCH 3/8] hw/acpi/acpi_dev_interface: Remove now unused madt_cpu virtual method

[Bernhard Beschow]

This virtual method was always set to the x86-specific pc_madt_cpu_entry(),
even in piix4 which is also used in MIPS. The previous changes use
pc_madt_cpu_entry() otherwise, so madt_cpu can be dropped.

Since pc_madt_cpu_entry() is now only used in x86-specific code, the stub
in hw/acpi/acpi-x86-stub can be removed as well.

Signed-off-by: Bernhard Beschow 
---
 include/hw/acpi/acpi_dev_interface.h | 2 --
 hw/acpi/acpi-x86-stub.c  | 6 --
 hw/acpi/piix4.c  | 2 --
 hw/i386/generic_event_device_x86.c   | 9 -
 hw/isa/lpc_ich9.c| 1 -
 5 files changed, 20 deletions(-)

diff --git a/include/hw/acpi/acpi_dev_interface.h 
b/include/hw/acpi/acpi_dev_interface.h
index a1648220ff..ca92928124 100644
--- a/include/hw/acpi/acpi_dev_interface.h
+++ b/include/hw/acpi/acpi_dev_interface.h
@@ -52,7 +52,5 @@ struct AcpiDeviceIfClass {
 /*  */
 void (*ospm_status)(AcpiDeviceIf *adev, ACPIOSTInfoList ***list);
 void (*send_event)(AcpiDeviceIf *adev, AcpiEventStatusBits ev);
-void (*madt_cpu)(int uid, const CPUArchIdList *apic_ids, GArray *entry,
- bool force_enabled);
 };
 #endif
diff --git a/hw/acpi/acpi-x86-stub.c b/hw/acpi/acpi-x86-stub.c
index d0d399d26b..9662a594ad 100644
--- a/hw/acpi/acpi-x86-stub.c
+++ b/hw/acpi/acpi-x86-stub.c
@@ -1,12 +1,6 @@
 #include "qemu/osdep.h"
-#include "hw/i386/pc.h"
 #include "hw/i386/acpi-build.h"
 
-void pc_madt_cpu_entry(int uid, const CPUArchIdList *apic_ids,
-   GArray *entry, bool force_enabled)
-{
-}
-
 Object *acpi_get_i386_pci_host(void)
 {
return NULL;
diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
index 63d2113b86..a7892c444c 100644
--- a/hw/acpi/piix4.c
+++ b/hw/acpi/piix4.c
@@ -20,7 +20,6 @@
  */
 
 #include "qemu/osdep.h"
-#include "hw/i386/pc.h"
 #include "hw/irq.h"
 #include "hw/isa/apm.h"
 #include "hw/i2c/pm_smbus.h"
@@ -654,7 +653,6 @@ static void piix4_pm_class_init(ObjectClass *klass, void 
*data)
 hc->is_hotpluggable_bus = piix4_is_hotpluggable_bus;
 adevc->ospm_status = piix4_ospm_status;
 adevc->send_event = piix4_send_gpe;
-adevc->madt_cpu = pc_madt_cpu_entry;
 }
 
 static const TypeInfo piix4_pm_info = {
diff --git a/hw/i386/generic_event_device_x86.c 
b/hw/i386/generic_event_device_x86.c
index e26fb02a2e..8fc233e1f1 100644
--- a/hw/i386/generic_event_device_x86.c
+++ b/hw/i386/generic_event_device_x86.c
@@ -8,19 +8,10 @@
 
 #include "qemu/osdep.h"
 #include "hw/acpi/generic_event_device.h"
-#include "hw/i386/pc.h"
-
-static void acpi_ged_x86_class_init(ObjectClass *class, void *data)
-{
-AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(class);
-
-adevc->madt_cpu = pc_madt_cpu_entry;
-}
 
 static const TypeInfo acpi_ged_x86_info = {
 .name  = TYPE_ACPI_GED_X86,
 .parent= TYPE_ACPI_GED,
-.class_init= acpi_ged_x86_class_init,
 .interfaces = (InterfaceInfo[]) {
 { TYPE_HOTPLUG_HANDLER },
 { TYPE_ACPI_DEVICE_IF },
diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c
index 9c47a2f6c7..92527f3c75 100644
--- a/hw/isa/lpc_ich9.c
+++ b/hw/isa/lpc_ich9.c
@@ -876,7 +876,6 @@ static void ich9_lpc_class_init(ObjectClass *klass, void 
*data)
 hc->is_hotpluggable_bus = ich9_pm_is_hotpluggable_bus;
 adevc->ospm_status = ich9_pm_ospm_status;
 adevc->send_event = ich9_send_gpe;
-adevc->madt_cpu = pc_madt_cpu_entry;
 amldevc->build_dev_aml = build_ich9_isa_aml;
 }
 
-- 
2.42.0

[PATCH 1/8] hw/i386/acpi-build: Use pc_madt_cpu_entry() directly

[Bernhard Beschow]

This is x86-specific code, so there is no advantage in using
pc_madt_cpu_entry() behind an architecture-agnostic interface.

Signed-off-by: Bernhard Beschow 
---
 hw/i386/acpi-common.h  | 3 +--
 hw/i386/acpi-build.c   | 3 +--
 hw/i386/acpi-common.c  | 5 ++---
 hw/i386/acpi-microvm.c | 3 +--
 4 files changed, 5 insertions(+), 9 deletions(-)

diff --git a/hw/i386/acpi-common.h b/hw/i386/acpi-common.h
index a68825acf5..b3c56ee014 100644
--- a/hw/i386/acpi-common.h
+++ b/hw/i386/acpi-common.h
@@ -1,7 +1,6 @@
 #ifndef HW_I386_ACPI_COMMON_H
 #define HW_I386_ACPI_COMMON_H
 
-#include "hw/acpi/acpi_dev_interface.h"
 #include "hw/acpi/bios-linker-loader.h"
 #include "hw/i386/x86.h"
 
@@ -9,7 +8,7 @@
 #define ACPI_BUILD_IOAPIC_ID 0x0
 
 void acpi_build_madt(GArray *table_data, BIOSLinker *linker,
- X86MachineState *x86ms, AcpiDeviceIf *adev,
+ X86MachineState *x86ms,
  const char *oem_id, const char *oem_table_id);
 
 #endif
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index bb12b0ad43..09586b8d9b 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -2547,8 +2547,7 @@ void acpi_build(AcpiBuildTables *tables, MachineState 
*machine)
 
 acpi_add_table(table_offsets, tables_blob);
 acpi_build_madt(tables_blob, tables->linker, x86ms,
-ACPI_DEVICE_IF(x86ms->acpi_dev), x86ms->oem_id,
-x86ms->oem_table_id);
+x86ms->oem_id, x86ms->oem_table_id);
 
 #ifdef CONFIG_ACPI_ERST
 {
diff --git a/hw/i386/acpi-common.c b/hw/i386/acpi-common.c
index 8a0932fe84..43dc23f7e0 100644
--- a/hw/i386/acpi-common.c
+++ b/hw/i386/acpi-common.c
@@ -94,14 +94,13 @@ build_xrupt_override(GArray *entry, uint8_t src, uint32_t 
gsi, uint16_t flags)
  * 5.2.8 Multiple APIC Description Table
  */
 void acpi_build_madt(GArray *table_data, BIOSLinker *linker,
- X86MachineState *x86ms, AcpiDeviceIf *adev,
+ X86MachineState *x86ms,
  const char *oem_id, const char *oem_table_id)
 {
 int i;
 bool x2apic_mode = false;
 MachineClass *mc = MACHINE_GET_CLASS(x86ms);
 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(MACHINE(x86ms));
-AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_GET_CLASS(adev);
 AcpiTable table = { .sig = "APIC", .rev = 3, .oem_id = oem_id,
 .oem_table_id = oem_table_id };
 
@@ -111,7 +110,7 @@ void acpi_build_madt(GArray *table_data, BIOSLinker *linker,
 build_append_int_noprefix(table_data, 1 /* PCAT_COMPAT */, 4); /* Flags */
 
 for (i = 0; i < apic_ids->len; i++) {
-adevc->madt_cpu(i, apic_ids, table_data, false);
+pc_madt_cpu_entry(i, apic_ids, table_data, false);
 if (apic_ids->cpus[i].arch_id > 254) {
 x2apic_mode = true;
 }
diff --git a/hw/i386/acpi-microvm.c b/hw/i386/acpi-microvm.c
index a075360d85..fec22d85c1 100644
--- a/hw/i386/acpi-microvm.c
+++ b/hw/i386/acpi-microvm.c
@@ -214,8 +214,7 @@ static void acpi_build_microvm(AcpiBuildTables *tables,
 
 acpi_add_table(table_offsets, tables_blob);
 acpi_build_madt(tables_blob, tables->linker, X86_MACHINE(machine),
-ACPI_DEVICE_IF(x86ms->acpi_dev), x86ms->oem_id,
-x86ms->oem_table_id);
+x86ms->oem_id, x86ms->oem_table_id);
 
 #ifdef CONFIG_ACPI_ERST
 {
-- 
2.42.0

[PATCH 5/8] hw/i386: Remove now redundant TYPE_ACPI_GED_X86

[Bernhard Beschow]

Now that TYPE_ACPI_GED_X86 doesn't assign AcpiDeviceIfClass::madt_cpu any more
it is the same as TYPE_ACPI_GED.

Signed-off-by: Bernhard Beschow 
---
 include/hw/acpi/generic_event_device.h |  2 --
 hw/i386/generic_event_device_x86.c | 27 --
 hw/i386/microvm.c  |  2 +-
 hw/i386/meson.build|  1 -
 4 files changed, 1 insertion(+), 31 deletions(-)
 delete mode 100644 hw/i386/generic_event_device_x86.c

diff --git a/include/hw/acpi/generic_event_device.h 
b/include/hw/acpi/generic_event_device.h
index d831bbd889..ba84ce0214 100644
--- a/include/hw/acpi/generic_event_device.h
+++ b/include/hw/acpi/generic_event_device.h
@@ -69,8 +69,6 @@
 #define TYPE_ACPI_GED "acpi-ged"
 OBJECT_DECLARE_SIMPLE_TYPE(AcpiGedState, ACPI_GED)
 
-#define TYPE_ACPI_GED_X86 "acpi-ged-x86"
-
 #define ACPI_GED_EVT_SEL_OFFSET0x0
 #define ACPI_GED_EVT_SEL_LEN   0x4
 
diff --git a/hw/i386/generic_event_device_x86.c 
b/hw/i386/generic_event_device_x86.c
deleted file mode 100644
index 8fc233e1f1..00
--- a/hw/i386/generic_event_device_x86.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * x86 variant of the generic event device for hw reduced acpi
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2 or later, as published by the Free Software Foundation.
- */
-
-#include "qemu/osdep.h"
-#include "hw/acpi/generic_event_device.h"
-
-static const TypeInfo acpi_ged_x86_info = {
-.name  = TYPE_ACPI_GED_X86,
-.parent= TYPE_ACPI_GED,
-.interfaces = (InterfaceInfo[]) {
-{ TYPE_HOTPLUG_HANDLER },
-{ TYPE_ACPI_DEVICE_IF },
-{ }
-}
-};
-
-static void acpi_ged_x86_register_types(void)
-{
-type_register_static(&acpi_ged_x86_info);
-}
-
-type_init(acpi_ged_x86_register_types)
diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c
index 7227a2156c..d5cde2f075 100644
--- a/hw/i386/microvm.c
+++ b/hw/i386/microvm.c
@@ -202,7 +202,7 @@ static void microvm_devices_init(MicrovmMachineState *mms)
 
 /* Optional and legacy devices */
 if (x86_machine_is_acpi_enabled(x86ms)) {
-DeviceState *dev = qdev_new(TYPE_ACPI_GED_X86);
+DeviceState *dev = qdev_new(TYPE_ACPI_GED);
 qdev_prop_set_uint32(dev, "ged-event", ACPI_GED_PWR_DOWN_EVT);
 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, GED_MMIO_BASE);
 /* sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, GED_MMIO_BASE_MEMHP); */
diff --git a/hw/i386/meson.build b/hw/i386/meson.build
index cfdbfdcbcb..ff879069c9 100644
--- a/hw/i386/meson.build
+++ b/hw/i386/meson.build
@@ -20,7 +20,6 @@ i386_ss.add(when: 'CONFIG_SGX', if_true: 
files('sgx-epc.c','sgx.c'),
 if_false: files('sgx-stub.c'))
 
 i386_ss.add(when: 'CONFIG_ACPI', if_true: files('acpi-common.c'))
-i386_ss.add(when: 'CONFIG_ACPI_HW_REDUCED', if_true: 
files('generic_event_device_x86.c'))
 i386_ss.add(when: 'CONFIG_PC', if_true: files(
   'pc.c',
   'pc_sysfw.c',
-- 
2.42.0

[PATCH 6/8] hw/i386/acpi-build: Determine SMI command port just once

[Bernhard Beschow]

The SMI command port is currently hardcoded by means of the ACPI_PORT_SMI_CMD
macro. This hardcoding is Intel specific and doesn't match VIA, for example.
There is already the AcpiFadtData::smi_cmd attribute which is used when building
the FADT. Let's also use it when building the DSDT which confines SMI command
port determination to just one place. This allows it to become a property later,
thus resolving the Intel assumption.

Signed-off-by: Bernhard Beschow 
---
 hw/i386/acpi-build.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index c8ac665d36..f9e7291150 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1495,14 +1495,14 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
 aml_append(crs,
 aml_io(
AML_DECODE16,
-   ACPI_PORT_SMI_CMD,
-   ACPI_PORT_SMI_CMD,
+   pm->fadt.smi_cmd,
+   pm->fadt.smi_cmd,
1,
2)
 );
 aml_append(dev, aml_name_decl("_CRS", crs));
 aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO,
-aml_int(ACPI_PORT_SMI_CMD), 2));
+aml_int(pm->fadt.smi_cmd), 2));
 field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK,
   AML_WRITE_AS_ZEROS);
 aml_append(field, aml_named_field("SMIC", 8));
-- 
2.42.0

Re: [PATCH for-8.2 v3 5/6] vfio/migration: Add P2P support for VFIO migration

[YangHang Liu]

Test result of multiple Mellanox CX-7 VFs migration:  PASS
[1] create two VFs and bind them to mlx5_vfio_pci driver
[2] start a VM with two VFs
[3] migrate the VM
[4] check if the VM works well

Tested-by: YangHang Liu 

Best Regards,
YangHang Liu


On Wed, Aug 2, 2023 at 4:43 PM Cédric Le Goater  wrote:
>
> On 8/2/23 10:14, Avihai Horon wrote:
> > VFIO migration uAPI defines an optional intermediate P2P quiescent
> > state. While in the P2P quiescent state, P2P DMA transactions cannot be
> > initiated by the device, but the device can respond to incoming ones.
> > Additionally, all outstanding P2P transactions are guaranteed to have
> > been completed by the time the device enters this state.
> >
> > The purpose of this state is to support migration of multiple devices
> > that might do P2P transactions between themselves.
> >
> > Add support for P2P migration by transitioning all the devices to the
> > P2P quiescent state before stopping or starting the devices. Use the new
> > VMChangeStateHandler prepare_cb to achieve that behavior.
> >
> > This will allow migration of multiple VFIO devices if all of them
> > support P2P migration.
> >
> > Signed-off-by: Avihai Horon 
>
>
> Reviewed-by: Cédric Le Goater 
>
> Thanks,
>
> C.
>
>
> > ---
> >   docs/devel/vfio-migration.rst | 93 +--
> >   hw/vfio/common.c  |  6 ++-
> >   hw/vfio/migration.c   | 46 +++--
> >   hw/vfio/trace-events  |  1 +
> >   4 files changed, 105 insertions(+), 41 deletions(-)
> >
> > diff --git a/docs/devel/vfio-migration.rst b/docs/devel/vfio-migration.rst
> > index b433cb5bb2..605fe60e96 100644
> > --- a/docs/devel/vfio-migration.rst
> > +++ b/docs/devel/vfio-migration.rst
> > @@ -23,9 +23,21 @@ and recommends that the initial bytes are sent and 
> > loaded in the destination
> >   before stopping the source VM. Enabling this migration capability will
> >   guarantee that and thus, can potentially reduce downtime even further.
> >
> > -Note that currently VFIO migration is supported only for a single device. 
> > This
> > -is due to VFIO migration's lack of P2P support. However, P2P support is 
> > planned
> > -to be added later on.
> > +To support migration of multiple devices that might do P2P transactions 
> > between
> > +themselves, VFIO migration uAPI defines an intermediate P2P quiescent 
> > state.
> > +While in the P2P quiescent state, P2P DMA transactions cannot be initiated 
> > by
> > +the device, but the device can respond to incoming ones. Additionally, all
> > +outstanding P2P transactions are guaranteed to have been completed by the 
> > time
> > +the device enters this state.
> > +
> > +All the devices that support P2P migration are first transitioned to the 
> > P2P
> > +quiescent state and only then are they stopped or started. This makes 
> > migration
> > +safe P2P-wise, since starting and stopping the devices is not done 
> > atomically
> > +for all the devices together.
> > +
> > +Thus, multiple VFIO devices migration is allowed only if all the devices
> > +support P2P migration. Single VFIO device migration is allowed regardless 
> > of
> > +P2P migration support.
> >
> >   A detailed description of the UAPI for VFIO device migration can be found 
> > in
> >   the comment for the ``vfio_device_mig_state`` structure in the header file
> > @@ -132,54 +144,63 @@ will be blocked.
> >   Flow of state changes during Live migration
> >   ===
> >
> > -Below is the flow of state change during live migration.
> > +Below is the state change flow during live migration for a VFIO device that
> > +supports both precopy and P2P migration. The flow for devices that don't
> > +support it is similar, except that the relevant states for precopy and P2P 
> > are
> > +skipped.
> >   The values in the parentheses represent the VM state, the migration 
> > state, and
> >   the VFIO device state, respectively.
> > -The text in the square brackets represents the flow if the VFIO device 
> > supports
> > -pre-copy.
> >
> >   Live migration save path
> >   
> >
> >   ::
> >
> > -QEMU normal running state
> > -(RUNNING, _NONE, _RUNNING)
> > -  |
> > +   QEMU normal running state
> > +   (RUNNING, _NONE, _RUNNING)
> > +  |
> >migrate_init spawns migration_thread
> > -Migration thread then calls each device's .save_setup()
> > -  (RUNNING, _SETUP, _RUNNING [_PRE_COPY])
> > -  |
> > -  (RUNNING, _ACTIVE, _RUNNING [_PRE_COPY])
> > -  If device is active, get pending_bytes by 
> > .state_pending_{estimate,exact}()
> > -  If total pending_bytes >= threshold_size, call 
> > .save_live_iterate()
> > -  [Data of VFIO device 

[PATCH 4/8] hw/acpi/acpi_dev_interface: Remove now unused #include "hw/boards.h"

[Bernhard Beschow]

The "hw/boards.h" is unused since the previous commit. Since its removal
requires include fixes in various unrelated files to keep the code compiling it
has been split in a dedicated commit.

Signed-off-by: Bernhard Beschow 
---
 hw/acpi/hmat.h   | 3 ++-
 include/hw/acpi/acpi_dev_interface.h | 1 -
 hw/acpi/cpu.c| 1 +
 hw/acpi/hmat.c   | 1 +
 hw/acpi/memory_hotplug.c | 1 +
 5 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/hw/acpi/hmat.h b/hw/acpi/hmat.h
index b57f0e7e80..fd989cb661 100644
--- a/hw/acpi/hmat.h
+++ b/hw/acpi/hmat.h
@@ -27,7 +27,8 @@
 #ifndef HMAT_H
 #define HMAT_H
 
-#include "hw/acpi/aml-build.h"
+#include "hw/acpi/bios-linker-loader.h"
+#include "sysemu/numa.h"
 
 /*
  * ACPI 6.3: 5.2.27.3 Memory Proximity Domain Attributes Structure,
diff --git a/include/hw/acpi/acpi_dev_interface.h 
b/include/hw/acpi/acpi_dev_interface.h
index ca92928124..68d9d15f50 100644
--- a/include/hw/acpi/acpi_dev_interface.h
+++ b/include/hw/acpi/acpi_dev_interface.h
@@ -3,7 +3,6 @@
 
 #include "qapi/qapi-types-acpi.h"
 #include "qom/object.h"
-#include "hw/boards.h"
 #include "hw/qdev-core.h"
 
 /* These values are part of guest ABI, and can not be changed */
diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c
index 65a3202d3f..011d2c6c2d 100644
--- a/hw/acpi/cpu.c
+++ b/hw/acpi/cpu.c
@@ -1,6 +1,7 @@
 #include "qemu/osdep.h"
 #include "migration/vmstate.h"
 #include "hw/acpi/cpu.h"
+#include "hw/core/cpu.h"
 #include "qapi/error.h"
 #include "qapi/qapi-events-acpi.h"
 #include "trace.h"
diff --git a/hw/acpi/hmat.c b/hw/acpi/hmat.c
index 3a6d51282a..d9de0daf89 100644
--- a/hw/acpi/hmat.c
+++ b/hw/acpi/hmat.c
@@ -27,6 +27,7 @@
 #include "qemu/osdep.h"
 #include "qemu/units.h"
 #include "sysemu/numa.h"
+#include "hw/acpi/aml-build.h"
 #include "hw/acpi/hmat.h"
 
 /*
diff --git a/hw/acpi/memory_hotplug.c b/hw/acpi/memory_hotplug.c
index d926f4f77d..0b883df813 100644
--- a/hw/acpi/memory_hotplug.c
+++ b/hw/acpi/memory_hotplug.c
@@ -1,6 +1,7 @@
 #include "qemu/osdep.h"
 #include "hw/acpi/memory_hotplug.h"
 #include "hw/mem/pc-dimm.h"
+#include "hw/boards.h"
 #include "hw/qdev-core.h"
 #include "migration/vmstate.h"
 #include "trace.h"
-- 
2.42.0

[PATCH 7/8] hw/acpi: Trace GPE access in all device models, not just PIIX4

[Bernhard Beschow]

Signed-off-by: Bernhard Beschow 
Reviewed-by: Igor Mammedov 
Reviewed-by: Philippe Mathieu-Daudé 
---
 hw/acpi/core.c   | 5 +
 hw/acpi/piix4.c  | 3 ---
 hw/acpi/trace-events | 8 
 3 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/hw/acpi/core.c b/hw/acpi/core.c
index 00b1e79a30..c561845a4a 100644
--- a/hw/acpi/core.c
+++ b/hw/acpi/core.c
@@ -32,6 +32,7 @@
 #include "qemu/module.h"
 #include "qemu/option.h"
 #include "sysemu/runstate.h"
+#include "trace.h"
 
 struct acpi_table_header {
 uint16_t _length; /* our length, not actual part of the hdr */
@@ -686,6 +687,8 @@ void acpi_gpe_ioport_writeb(ACPIREGS *ar, uint32_t addr, 
uint32_t val)
 {
 uint8_t *cur;
 
+trace_acpi_gpe_ioport_writeb(addr, val);
+
 cur = acpi_gpe_ioport_get_ptr(ar, addr);
 if (addr < ar->gpe.len / 2) {
 /* GPE_STS */
@@ -709,6 +712,8 @@ uint32_t acpi_gpe_ioport_readb(ACPIREGS *ar, uint32_t addr)
 val = *cur;
 }
 
+trace_acpi_gpe_ioport_readb(addr, val);
+
 return val;
 }
 
diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
index a7892c444c..dd523d2e4c 100644
--- a/hw/acpi/piix4.c
+++ b/hw/acpi/piix4.c
@@ -42,7 +42,6 @@
 #include "hw/acpi/acpi_dev_interface.h"
 #include "migration/vmstate.h"
 #include "hw/core/cpu.h"
-#include "trace.h"
 #include "qom/object.h"
 
 #define GPE_BASE 0xafe0
@@ -517,7 +516,6 @@ static uint64_t gpe_readb(void *opaque, hwaddr addr, 
unsigned width)
 PIIX4PMState *s = opaque;
 uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr);
 
-trace_piix4_gpe_readb(addr, width, val);
 return val;
 }
 
@@ -526,7 +524,6 @@ static void gpe_writeb(void *opaque, hwaddr addr, uint64_t 
val,
 {
 PIIX4PMState *s = opaque;
 
-trace_piix4_gpe_writeb(addr, width, val);
 acpi_gpe_ioport_writeb(&s->ar, addr, val);
 acpi_update_sci(&s->ar, s->irq);
 }
diff --git a/hw/acpi/trace-events b/hw/acpi/trace-events
index 78e0a8670e..159937ddb9 100644
--- a/hw/acpi/trace-events
+++ b/hw/acpi/trace-events
@@ -17,6 +17,10 @@ mhp_acpi_clear_remove_evt(uint32_t slot) "slot[0x%"PRIx32"] 
clear remove event"
 mhp_acpi_pc_dimm_deleted(uint32_t slot) "slot[0x%"PRIx32"] pc-dimm deleted"
 mhp_acpi_pc_dimm_delete_failed(uint32_t slot) "slot[0x%"PRIx32"] pc-dimm 
delete failed"
 
+# core.c
+acpi_gpe_ioport_readb(uint32_t addr, uint8_t val) "addr: 0x%" PRIx32 " ==> 
0x%" PRIx8
+acpi_gpe_ioport_writeb(uint32_t addr, uint8_t val) "addr: 0x%" PRIx32 " <== 
0x%" PRIx8
+
 # cpu.c
 cpuhp_acpi_invalid_idx_selected(uint32_t idx) "0x%"PRIx32
 cpuhp_acpi_read_flags(uint32_t idx, uint8_t flags) "idx[0x%"PRIx32"] flags: 
0x%"PRIx8
@@ -48,10 +52,6 @@ acpi_pci_sel_read(uint32_t val) "%" PRIu32
 acpi_pci_ej_write(uint64_t addr, uint64_t data) "0x%" PRIx64 " <== %" PRIu64
 acpi_pci_sel_write(uint64_t addr, uint64_t data) "0x%" PRIx64 " <== %" PRIu64
 
-# piix4.c
-piix4_gpe_readb(uint64_t addr, unsigned width, uint64_t val) "addr: 0x%" 
PRIx64 " width: %d ==> 0x%" PRIx64
-piix4_gpe_writeb(uint64_t addr, unsigned width, uint64_t val) "addr: 0x%" 
PRIx64 " width: %d <== 0x%" PRIx64
-
 # tco.c
 tco_timer_reload(int ticks, int msec) "ticks=%d (%d ms)"
 tco_timer_expired(int timeouts_no, bool strap, bool no_reboot) "timeouts_no=%d 
no_reboot=%d/%d"
-- 
2.42.0

[PATCH 8/8] hw/acpi/core: Trace enable and status registers of GPE separately

[Bernhard Beschow]

The bit positions of both registers are related. Tracing the registers
independently results in the same offsets across these registers which
eases debugging.

Signed-off-by: Bernhard Beschow 
Acked-by: Igor Mammedov 
---
 hw/acpi/core.c   | 10 +++---
 hw/acpi/trace-events |  6 --
 2 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/hw/acpi/core.c b/hw/acpi/core.c
index c561845a4a..ec5e127d17 100644
--- a/hw/acpi/core.c
+++ b/hw/acpi/core.c
@@ -687,13 +687,13 @@ void acpi_gpe_ioport_writeb(ACPIREGS *ar, uint32_t addr, 
uint32_t val)
 {
 uint8_t *cur;
 
-trace_acpi_gpe_ioport_writeb(addr, val);
-
 cur = acpi_gpe_ioport_get_ptr(ar, addr);
 if (addr < ar->gpe.len / 2) {
+trace_acpi_gpe_sts_ioport_writeb(addr, val);
 /* GPE_STS */
 *cur = (*cur) & ~val;
 } else if (addr < ar->gpe.len) {
+trace_acpi_gpe_en_ioport_writeb(addr - (ar->gpe.len / 2), val);
 /* GPE_EN */
 *cur = val;
 } else {
@@ -712,7 +712,11 @@ uint32_t acpi_gpe_ioport_readb(ACPIREGS *ar, uint32_t addr)
 val = *cur;
 }
 
-trace_acpi_gpe_ioport_readb(addr, val);
+if (addr < ar->gpe.len / 2) {
+trace_acpi_gpe_sts_ioport_readb(addr, val);
+} else {
+trace_acpi_gpe_en_ioport_readb(addr - (ar->gpe.len / 2), val);
+}
 
 return val;
 }
diff --git a/hw/acpi/trace-events b/hw/acpi/trace-events
index 159937ddb9..d387adfb0b 100644
--- a/hw/acpi/trace-events
+++ b/hw/acpi/trace-events
@@ -18,8 +18,10 @@ mhp_acpi_pc_dimm_deleted(uint32_t slot) "slot[0x%"PRIx32"] 
pc-dimm deleted"
 mhp_acpi_pc_dimm_delete_failed(uint32_t slot) "slot[0x%"PRIx32"] pc-dimm 
delete failed"
 
 # core.c
-acpi_gpe_ioport_readb(uint32_t addr, uint8_t val) "addr: 0x%" PRIx32 " ==> 
0x%" PRIx8
-acpi_gpe_ioport_writeb(uint32_t addr, uint8_t val) "addr: 0x%" PRIx32 " <== 
0x%" PRIx8
+acpi_gpe_sts_ioport_readb(uint32_t addr, uint8_t val) "addr: 0x%" PRIx32 " ==> 
0x%" PRIx8
+acpi_gpe_en_ioport_readb(uint32_t addr, uint8_t val) "addr: 0x%" PRIx32 " ==> 
0x%" PRIx8
+acpi_gpe_sts_ioport_writeb(uint32_t addr, uint8_t val) "addr: 0x%" PRIx32 " 
<== 0x%" PRIx8
+acpi_gpe_en_ioport_writeb(uint32_t addr, uint8_t val) "addr: 0x%" PRIx32 " <== 
0x%" PRIx8
 
 # cpu.c
 cpuhp_acpi_invalid_idx_selected(uint32_t idx) "0x%"PRIx32
-- 
2.42.0

[PATCH 2/8] hw/acpi/cpu: Have build_cpus_aml() take a build_madt_cpu_fn callback

[Bernhard Beschow]

build_cpus_aml() is architecture independent but needs to create architecture-
specific CPU AML. So far this was achieved by using a virtual method from
TYPE_ACPI_DEVICE_IF. However, build_cpus_aml() would resolve this interface from
global (!) state. This makes it quite incomprehensible where this interface
comes from (TYPE_PIIX4_PM?, TYPE_ICH9_LPC_DEVICE?, TYPE_ACPI_GED_X86?) an can
lead to crashes when the generic code is ported to new architectures.

So far, build_cpus_aml() is only called in architecture-specific code -- and
only in x86. We can therefore simply pass pc_madt_cpu_entry() as callback to
build_cpus_aml(). This is the same callback that would be used through
TYPE_ACPI_DEVICE_IF.

Signed-off-by: Bernhard Beschow 
---
 include/hw/acpi/cpu.h | 6 +-
 hw/acpi/cpu.c | 8 ++--
 hw/i386/acpi-build.c  | 4 ++--
 3 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/include/hw/acpi/cpu.h b/include/hw/acpi/cpu.h
index 999caaf510..bc901660fb 100644
--- a/include/hw/acpi/cpu.h
+++ b/include/hw/acpi/cpu.h
@@ -15,6 +15,7 @@
 #include "hw/qdev-core.h"
 #include "hw/acpi/acpi.h"
 #include "hw/acpi/aml-build.h"
+#include "hw/boards.h"
 #include "hw/hotplug.h"
 
 typedef struct AcpiCpuStatus {
@@ -55,8 +56,11 @@ typedef struct CPUHotplugFeatures {
 const char *smi_path;
 } CPUHotplugFeatures;
 
+typedef void (*build_madt_cpu_fn)(int uid, const CPUArchIdList *apic_ids,
+  GArray *entry, bool force_enabled);
+
 void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures opts,
-hwaddr io_base,
+build_madt_cpu_fn build_madt_cpu, hwaddr io_base,
 const char *res_root,
 const char *event_handler_method);
 
diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c
index 19c154d78f..65a3202d3f 100644
--- a/hw/acpi/cpu.c
+++ b/hw/acpi/cpu.c
@@ -338,7 +338,7 @@ const VMStateDescription vmstate_cpu_hotplug = {
 #define CPU_FW_EJECT_EVENT "CEJF"
 
 void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures opts,
-hwaddr io_base,
+build_madt_cpu_fn build_madt_cpu, hwaddr io_base,
 const char *res_root,
 const char *event_handler_method)
 {
@@ -353,8 +353,6 @@ void build_cpus_aml(Aml *table, MachineState *machine, 
CPUHotplugFeatures opts,
 MachineClass *mc = MACHINE_GET_CLASS(machine);
 const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(machine);
 char *cphp_res_path = g_strdup_printf("%s." CPUHP_RES_DEVICE, res_root);
-Object *obj = object_resolve_path_type("", TYPE_ACPI_DEVICE_IF, NULL);
-AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_GET_CLASS(obj);
 
 cpu_ctrl_dev = aml_device("%s", cphp_res_path);
 {
@@ -664,9 +662,7 @@ void build_cpus_aml(Aml *table, MachineState *machine, 
CPUHotplugFeatures opts,
 aml_append(dev, method);
 
 /* build _MAT object */
-assert(adevc && adevc->madt_cpu);
-adevc->madt_cpu(i, arch_ids, madt_buf,
-true); /* set enabled flag */
+build_madt_cpu(i, arch_ids, madt_buf, true); /* set enabled flag */
 aml_append(dev, aml_name_decl("_MAT",
 aml_buffer(madt_buf->len, (uint8_t *)madt_buf->data)));
 g_array_free(madt_buf, true);
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 09586b8d9b..c8ac665d36 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1549,8 +1549,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
 .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL,
 .fw_unplugs_cpu = pm->smi_on_cpu_unplug,
 };
-build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base,
-   "\\_SB.PCI0", "\\_GPE._E02");
+build_cpus_aml(dsdt, machine, opts, pc_madt_cpu_entry,
+   pm->cpu_hp_io_base, "\\_SB.PCI0", "\\_GPE._E02");
 }
 
 if (pcms->memhp_io_base && nr_mem) {
-- 
2.42.0

Re: [PATCH for-8.2 v3 0/6] vfio/migration: Add P2P support for VFIO migration

[YangHang Liu]

Test result of multiple Mellanox CX-7 VFs migration:  PASS

[1] create two VFs and bind them to mlx5_vfio_pci driver
[2] start a VM with two VFs
[3] migrate the VM
[4] check if the VM works well

Tested-by: YangHang Liu 

Best Regards,
YangHang Liu
On Wed, Aug 2, 2023 at 4:16 PM Avihai Horon  wrote:
>
> Hi all,
>
> The first patch in this series adds a small optimization to VFIO
> migration by moving the STOP_COPY->STOP transition to
> vfio_save_cleanup(). Testing with a ConnectX-7 VFIO device showed that
> this can reduce downtime by up to 6%.
>
> The rest of the series adds P2P support for VFIO migration.
>
> VFIO migration uAPI defines an optional intermediate P2P quiescent
> state. While in the P2P quiescent state, P2P DMA transactions cannot be
> initiated by the device, but the device can respond to incoming ones.
> Additionally, all outstanding P2P transactions are guaranteed to have
> been completed by the time the device enters this state.
>
> The purpose of this state is to support migration of multiple devices
> that might do P2P transactions between themselves.
>
> To implement P2P migration support, all the devices must be transitioned
> to the P2P quiescent state before being stopped or started.
>
> This behavior is achieved by adding an optional prepare callback to
> VMChangeStateEntry. These callbacks are invoked before the main VM state
> change callbacks, transitioning all the VFIO devices to the P2P state,
> and only then are the main callbacks invoked, which stop or start the
> devices.
>
> This will allow migration of multiple VFIO devices if all of them
> support P2P migration.
>
> Thanks.
>
> Changes from v2 [2]:
> * Registered VFIO prepare callback only if P2P migration is supported by
>   the device. (Cedric)
> * Added Cedric R-b tags to patches 2,3 and 6.
>
> Changes from v1 [1]:
> * Rebased on latest master branch.
> * Renamed pre_change_cb to prepare_cb and adjusted relevant code
>   accordingly. (Cedric)
> * Split VFIO vmstate change handler to two separate handlers, one for
>   prepare callback and another for main callback. (Cedric)
> * Renamed vfio_should_block_multiple_devices_migration() to
>   vfio_multiple_devices_migration_is_supported() and reverted its logic
>   accordingly. (Cedric)
> * Rephrased "that are doing P2P" to "that might do P2P" in docs and
>   commit message. (Jason)
> * Added Cedric R-b tag to patch #4.
>
> [1]
> https://lore.kernel.org/qemu-devel/20230716081541.27900-1-avih...@nvidia.com/
>
> [2]
> https://lore.kernel.org/qemu-devel/20230731102521.15335-1-avih...@nvidia.com/
>
> Avihai Horon (5):
>   vfio/migration: Move from STOP_COPY to STOP in vfio_save_cleanup()
>   sysemu: Add prepare callback to struct VMChangeStateEntry
>   qdev: Add qdev_add_vm_change_state_handler_full()
>   vfio/migration: Add P2P support for VFIO migration
>   vfio/migration: Allow migration of multiple P2P supporting devices
>
> Joao Martins (1):
>   vfio/migration: Refactor PRE_COPY and RUNNING state checks
>
>  docs/devel/vfio-migration.rst | 93 +++
>  include/hw/vfio/vfio-common.h |  2 +
>  include/sysemu/runstate.h |  7 +++
>  hw/core/vm-change-state-handler.c | 14 -
>  hw/vfio/common.c  | 50 +
>  hw/vfio/migration.c   | 75 -
>  softmmu/runstate.c| 40 +
>  hw/vfio/trace-events  |  1 +
>  8 files changed, 218 insertions(+), 64 deletions(-)
>
> --
> 2.26.3
>
>

Re: [PATCH v1 0/7] Introduce model for IBM's FSP

[Joel Stanley]

Hi Ninad,

On Fri, 25 Aug 2023 at 20:51, Ninad Palsule  wrote:
>
> Hello,
>
> Please review the patch-set.
>
> This is a first step towards introducing model for IBM's Flexible
> Service Interface. The full functionality will be implemented over the
> time.

You have a typo in the subject, I think you meant to write FSI instead of FSP.

[PATCH] accel/kvm: Fix dirty reaper thread crash

[alloc . young]

From: alloc 

kvm_dirty_ring_reaper_init is called much early than vcpu creation,
so it's possibe the reaper get a crash before vcpu mmap kvm_dirty_gfns.
Add a machine done notifier to ensure dirty reaper get run after vcpu
inited.

Signed-off-by: alloc 
---
 accel/kvm/kvm-all.c | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c
index d07f1ecbd3..5ae7e27a72 100644
--- a/accel/kvm/kvm-all.c
+++ b/accel/kvm/kvm-all.c
@@ -51,6 +51,7 @@
 
 #include "hw/boards.h"
 #include "sysemu/stats.h"
+#include "sysemu/sysemu.h"
 
 /* This check must be after config-host.h is included */
 #ifdef CONFIG_EVENTFD
@@ -133,6 +134,8 @@ static QLIST_HEAD(, KVMResampleFd) kvm_resample_fd_list =
 
 static QemuMutex kml_slots_lock;
 
+static Notifier dirty_ring_reaper_machine_done;
+
 #define kvm_slots_lock()qemu_mutex_lock(&kml_slots_lock)
 #define kvm_slots_unlock()  qemu_mutex_unlock(&kml_slots_lock)
 
@@ -1454,8 +1457,9 @@ static void *kvm_dirty_ring_reaper_thread(void *data)
 return NULL;
 }
 
-static void kvm_dirty_ring_reaper_init(KVMState *s)
+static void kvm_dirty_ring_reaper_init(Notifier *n, void *unused)
 {
+KVMState *s = kvm_state;
 struct KVMDirtyRingReaper *r = &s->reaper;
 
 qemu_thread_create(&r->reaper_thr, "kvm-reaper",
@@ -2742,7 +2746,8 @@ static int kvm_init(MachineState *ms)
 }
 
 if (s->kvm_dirty_ring_size) {
-kvm_dirty_ring_reaper_init(s);
+dirty_ring_reaper_machine_done.notify = kvm_dirty_ring_reaper_init;
+qemu_add_machine_init_done_notifier(&dirty_ring_reaper_machine_done);
 }
 
 if (kvm_check_extension(kvm_state, KVM_CAP_BINARY_STATS_FD)) {
-- 
2.39.3

Re: [PATCH v1 1/7] hw/fsi: Introduce IBM's Local bus

[Joel Stanley]

On Fri, 25 Aug 2023 at 20:31, Ninad Palsule  wrote:
>
> This is a part of patchset where IBM's Flexible Service Interface is
> introduced.
>
> The LBUS is modelled to maintain the qdev bus hierarchy and to take
> advantage of the object model to automatically generate the CFAM
> configuration block. The configuration block presents engines in the
> order they are attached to the CFAM's LBUS. Engine implementations
> should subclass the LBusDevice and set the 'config' member of
> LBusDeviceClass to match the engine's type.
>
> Signed-off-by: Andrew Jeffery 
> Signed-off-by: Cédric Le Goater 
> Signed-off-by: Ninad Palsule 
> ---
>  hw/Kconfig|  1 +
>  hw/fsi/Kconfig|  2 +
>  hw/fsi/lbus.c | 94 +++
>  hw/fsi/meson.build|  1 +
>  hw/meson.build|  1 +
>  include/hw/fsi/bits.h | 15 +++
>  include/hw/fsi/lbus.h | 57 ++
>  7 files changed, 171 insertions(+)
>  create mode 100644 hw/fsi/Kconfig
>  create mode 100644 hw/fsi/lbus.c
>  create mode 100644 hw/fsi/meson.build
>  create mode 100644 include/hw/fsi/bits.h
>  create mode 100644 include/hw/fsi/lbus.h
>
> diff --git a/hw/Kconfig b/hw/Kconfig
> index ba62ff6417..2ccb73add5 100644
> --- a/hw/Kconfig
> +++ b/hw/Kconfig
> @@ -9,6 +9,7 @@ source core/Kconfig
>  source cxl/Kconfig
>  source display/Kconfig
>  source dma/Kconfig
> +source fsi/Kconfig
>  source gpio/Kconfig
>  source hyperv/Kconfig
>  source i2c/Kconfig
> diff --git a/hw/fsi/Kconfig b/hw/fsi/Kconfig
> new file mode 100644
> index 00..687449e14e
> --- /dev/null
> +++ b/hw/fsi/Kconfig
> @@ -0,0 +1,2 @@
> +config LBUS
> +bool
> diff --git a/hw/fsi/lbus.c b/hw/fsi/lbus.c
> new file mode 100644
> index 00..afb26ef7ea
> --- /dev/null
> +++ b/hw/fsi/lbus.c
> @@ -0,0 +1,94 @@
> +/*
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + * Copyright (C) 2023 IBM Corp.
> + *
> + * IBM Local bus where FSI slaves are connected
> + */
> +
> +#include "qemu/osdep.h"
> +
> +#include "qapi/error.h"
> +#include "qemu/log.h"
> +
> +#include "hw/fsi/lbus.h"
> +
> +#include "hw/qdev-properties.h"
> +
> +static void lbus_realize(BusState *bus, Error **errp)
> +{
> +LBusNode *node;
> +LBus *lbus = LBUS(bus);
> +
> +memory_region_init(&lbus->mr, OBJECT(lbus), TYPE_LBUS,
> +   (2 * 1024 * 1024) - 0x400);
> +
> +QLIST_FOREACH(node, &lbus->devices, next) {
> +memory_region_add_subregion(&lbus->mr, node->ldev->address,
> +&node->ldev->iomem);
> +}
> +}
> +
> +static void lbus_init(Object *o)
> +{
> +}
> +
> +static void lbus_class_init(ObjectClass *klass, void *data)
> +{
> +BusClass *k = BUS_CLASS(klass);
> +k->realize = lbus_realize;
> +}
> +
> +static const TypeInfo lbus_info = {
> +.name = TYPE_LBUS,
> +.parent = TYPE_BUS,
> +.instance_init = lbus_init,
> +.instance_size = sizeof(LBus),
> +.class_init = lbus_class_init,
> +};
> +
> +static Property lbus_device_props[] = {
> +DEFINE_PROP_UINT32("address", LBusDevice, address, 0),
> +DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +DeviceState *lbus_create_device(LBus *bus, const char *type, uint32_t addr)
> +{
> +DeviceState *dev;
> +LBusNode *node;
> +
> +dev = qdev_new(type);
> +qdev_prop_set_uint8(dev, "address", addr);
> +qdev_realize_and_unref(dev, &bus->bus, &error_fatal);
> +
> +/* Move to post_load */
> +node = g_malloc(sizeof(struct LBusNode));
> +node->ldev = LBUS_DEVICE(dev);
> +QLIST_INSERT_HEAD(&bus->devices, node, next);
> +
> +return dev;
> +}
> +
> +static void lbus_device_class_init(ObjectClass *klass, void *data)
> +{
> +DeviceClass *dc = DEVICE_CLASS(klass);
> +
> +dc->bus_type = TYPE_LBUS;
> +device_class_set_props(dc, lbus_device_props);
> +}
> +
> +static const TypeInfo lbus_device_type_info = {
> +.name = TYPE_LBUS_DEVICE,
> +.parent = TYPE_DEVICE,
> +.instance_size = sizeof(LBusDevice),
> +.abstract = true,
> +.class_init = lbus_device_class_init,
> +.class_size = sizeof(LBusDeviceClass),
> +};
> +
> +static void lbus_register_types(void)
> +{
> +type_register_static(&lbus_info);
> +type_register_static(&lbus_device_type_info);
> +}
> +
> +type_init(lbus_register_types);
> diff --git a/hw/fsi/meson.build b/hw/fsi/meson.build
> new file mode 100644
> index 00..e1007d5fea
> --- /dev/null
> +++ b/hw/fsi/meson.build
> @@ -0,0 +1 @@
> +system_ss.add(when: 'CONFIG_LBUS', if_true: files('lbus.c'))
> diff --git a/hw/meson.build b/hw/meson.build
> index c7ac7d3d75..6c71ee9cfa 100644
> --- a/hw/meson.build
> +++ b/hw/meson.build
> @@ -43,6 +43,7 @@ subdir('virtio')
>  subdir('watchdog')
>  subdir('xen')
>  subdir('xenpv')
> +subdir('fsi')
>
>  subdir('alpha')
>  subdir('arm')
> diff --git a/include/hw/fsi/bits.h b/include/hw/fsi/bits.h
> new file mode 100644
> index 00..338ae483cf
> --- /dev/null
> +++ b/include/hw/fsi/bits.h
> @@ 

[RFC PATCH v2 1/6] cpu: Add new API cpu_type_by_name

[LIU Zhiwei]

cpu_type_by_name is used to get the cpu type name from the command
line -cpu.

Currently it is only used by parse_cpu_option. In the next patch, it
will be used by other cpu query functions.

Signed-off-by: LIU Zhiwei 
---
 cpu.c | 31 +++
 1 file changed, 19 insertions(+), 12 deletions(-)

diff --git a/cpu.c b/cpu.c
index 1c948d1161..e1a9239d0f 100644
--- a/cpu.c
+++ b/cpu.c
@@ -257,28 +257,35 @@ void cpu_exec_initfn(CPUState *cpu)
 #endif
 }
 
-const char *parse_cpu_option(const char *cpu_option)
+static const char *cpu_type_by_name(const char *cpu_model)
 {
 ObjectClass *oc;
-CPUClass *cc;
-gchar **model_pieces;
 const char *cpu_type;
 
-model_pieces = g_strsplit(cpu_option, ",", 2);
-if (!model_pieces[0]) {
-error_report("-cpu option cannot be empty");
-exit(1);
-}
 
-oc = cpu_class_by_name(CPU_RESOLVING_TYPE, model_pieces[0]);
+oc = cpu_class_by_name(CPU_RESOLVING_TYPE, cpu_model);
 if (oc == NULL) {
-error_report("unable to find CPU model '%s'", model_pieces[0]);
-g_strfreev(model_pieces);
+error_report("unable to find CPU model '%s'", cpu_model);
 exit(EXIT_FAILURE);
 }
 
 cpu_type = object_class_get_name(oc);
-cc = CPU_CLASS(oc);
+return cpu_type;
+}
+
+const char *parse_cpu_option(const char *cpu_option)
+{
+const char *cpu_type;
+CPUClass *cc;
+gchar **model_pieces;
+
+model_pieces = g_strsplit(cpu_option, ",", 2);
+if (!model_pieces[0]) {
+error_report("-cpu option cannot be empty");
+exit(1);
+}
+cpu_type = cpu_type_by_name(model_pieces[0]);
+cc = CPU_CLASS(object_class_by_name(cpu_type));
 cc->parse_features(cpu_type, model_pieces[1], &error_fatal);
 g_strfreev(model_pieces);
 return cpu_type;
-- 
2.17.1

[RFC PATCH v2 0/6] Add API for list cpu extensions

[LIU Zhiwei]

Some times we want to know what is the really mean of one cpu option.
For example, in RISC-V, we usually specify a cpu in this way:
-cpu rv64,v=on

If we don't look into the source code, we can't get the ISA extensions
of this -cpu command line.

In this patch set, we add one list_cpu_props API for common cores. It
will output the enabled ISA extensions.

In the near future, I will also list all possible user configurable
options and all possible extensions for this cpu.

In order to reuse the options parse code, I also add a QemuOptsList
for cpu.

After this patch, we can output the extensions for cpu,
"""
./qemu-system-riscv64 -cpu rv64,help
Enabled extensions:

rv64imafdch_zicbom_zicboz_zicsr_zifencei_zihintpause_zawrs_zfa_zba_zbb_zbc_zbs_sstc_svadu
To get all configuable options for this cpu, use -device rv64-riscv-cpu,help
"""


v1->v2:

1) Give a hint to use -device cpu,help for configualbe options on cpu
2) Support list_cpu_props for linux user mode
3) Add default to some properties to make -device cpu,help output better


Todo:
1) Fix Daniel comments on KVM and cpu option check
2) Add support for other archs
3) Move qdev help function from qdev-monitor to qdev-property

LIU Zhiwei (6):
  cpu: Add new API cpu_type_by_name
  target/riscv: Add API list_cpu_props
  softmmu/vl: Add qemu_cpu_opts QemuOptsList
  target/riscv: Add default value for misa property
  target/riscv: Add defalut value for string property
  linux-user: Move qemu_cpu_opts to cpu.c

 cpu.c| 63 +---
 hw/core/qdev-prop-internal.h |  2 ++
 hw/core/qdev-properties.c|  7 
 include/exec/cpu-common.h|  3 ++
 include/hw/core/cpu.h| 11 +++
 include/hw/qdev-properties.h |  8 +
 linux-user/main.c| 10 ++
 softmmu/vl.c | 11 +++
 target/riscv/cpu.c   | 30 +
 target/riscv/cpu.h   |  2 ++
 10 files changed, 128 insertions(+), 19 deletions(-)

-- 
2.17.1

[RFC PATCH v2 2/6] target/riscv: Add API list_cpu_props

[LIU Zhiwei]

This API used for output current configuration for one specified CPU.
Currently only RISC-V frontend implements this API.

Signed-off-by: LIU Zhiwei 
---
 cpu.c |  8 
 include/exec/cpu-common.h |  1 +
 target/riscv/cpu.c| 14 ++
 target/riscv/cpu.h|  2 ++
 4 files changed, 25 insertions(+)

diff --git a/cpu.c b/cpu.c
index e1a9239d0f..03a313cd72 100644
--- a/cpu.c
+++ b/cpu.c
@@ -299,6 +299,14 @@ void list_cpus(void)
 #endif
 }
 
+void list_cpu_props(CPUState *cs)
+{
+/* XXX: implement xxx_cpu_list_props for targets that still miss it */
+#if defined(cpu_list_props)
+cpu_list_props(cs);
+#endif
+}
+
 #if defined(CONFIG_USER_ONLY)
 void tb_invalidate_phys_addr(hwaddr addr)
 {
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index 87dc9a752c..b3160d9218 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -166,5 +166,6 @@ int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
 
 /* vl.c */
 void list_cpus(void);
+void list_cpu_props(CPUState *);
 
 #endif /* CPU_COMMON_H */
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6b93b04453..c2f102fae1 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2226,6 +2226,20 @@ void riscv_cpu_list(void)
 g_slist_free(list);
 }
 
+void riscv_cpu_list_props(CPUState *cs)
+{
+char *enabled_isa;
+RISCVCPU *cpu = RISCV_CPU(cs);
+RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
+ObjectClass *oc = OBJECT_CLASS(mcc);
+
+enabled_isa = riscv_isa_string(RISCV_CPU(cs));
+qemu_printf("Enabled extensions:\n");
+qemu_printf("\t%s\n", enabled_isa);
+qemu_printf("To get all configuable options for this cpu, use"
+" -device %s,help\n", object_class_get_name(oc));
+}
+
 #define DEFINE_CPU(type_name, initfn)  \
 {  \
 .name = type_name, \
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 6ea22e0eea..af1d47605b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -443,9 +443,11 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int 
size,
 bool probe, uintptr_t retaddr);
 char *riscv_isa_string(RISCVCPU *cpu);
 void riscv_cpu_list(void);
+void riscv_cpu_list_props(CPUState *cs);
 void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
 
 #define cpu_list riscv_cpu_list
+#define cpu_list_props riscv_cpu_list_props
 #define cpu_mmu_index riscv_cpu_mmu_index
 
 #ifndef CONFIG_USER_ONLY
-- 
2.17.1

Re: [RFC PATCH 2/3] target/riscv: Add API list_cpu_props

[LIU Zhiwei]

On 2023/8/25 21:46, Daniel Henrique Barboza wrote:



On 8/25/23 09:16, LIU Zhiwei wrote:

This API used for output current configuration for one specified CPU.
Currently only RISC-V frontend implements this API.

Signed-off-by: LIU Zhiwei 
---
  cpu.c |  8 
  include/exec/cpu-common.h |  1 +
  target/riscv/cpu.c    | 10 ++
  target/riscv/cpu.h    |  2 ++
  4 files changed, 21 insertions(+)

diff --git a/cpu.c b/cpu.c
index e1a9239d0f..03a313cd72 100644
--- a/cpu.c
+++ b/cpu.c
@@ -299,6 +299,14 @@ void list_cpus(void)
  #endif
  }
  +void list_cpu_props(CPUState *cs)
+{
+    /* XXX: implement xxx_cpu_list_props for targets that still miss 
it */

+#if defined(cpu_list_props)
+    cpu_list_props(cs);
+#endif
+}
+
  #if defined(CONFIG_USER_ONLY)
  void tb_invalidate_phys_addr(hwaddr addr)
  {
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index 87dc9a752c..b3160d9218 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -166,5 +166,6 @@ int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
    /* vl.c */
  void list_cpus(void);
+void list_cpu_props(CPUState *);
    #endif /* CPU_COMMON_H */
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6b93b04453..3ea18de06f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2226,6 +2226,16 @@ void riscv_cpu_list(void)
  g_slist_free(list);
  }
  +void riscv_cpu_list_props(CPUState *cs)
+{
+    char *enabled_isa;
+
+    enabled_isa = riscv_isa_string(RISCV_CPU(cs));
+    qemu_printf("Enable extension:\n");


I suggest "Enabled extensions". LGTM otherwise.


Fixed, thanks.

Zhiwei



Daniel


+    qemu_printf("\t%s\n", enabled_isa);
+    /* TODO: output all user configurable options and all possible 
extensions */

+}
+
  #define DEFINE_CPU(type_name, initfn)  \
  {  \
  .name = type_name, \
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 6ea22e0eea..af1d47605b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -443,9 +443,11 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr 
address, int size,

  bool probe, uintptr_t retaddr);
  char *riscv_isa_string(RISCVCPU *cpu);
  void riscv_cpu_list(void);
+void riscv_cpu_list_props(CPUState *cs);
  void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
    #define cpu_list riscv_cpu_list
+#define cpu_list_props riscv_cpu_list_props
  #define cpu_mmu_index riscv_cpu_mmu_index
    #ifndef CONFIG_USER_ONLY

[RFC PATCH v2 3/6] softmmu/vl: Add qemu_cpu_opts QemuOptsList

[LIU Zhiwei]

This make the cpu works the similar way like the -device option.

For device option,
"""
./qemu-system-riscv64 -device e1000,help
e1000 options:
  acpi-index=-  (default: 0)
  addr=   - Slot and optional function number, example: 06.0 or 
06 (default: -1)
  autonegotiation= - on/off (default: true)
  bootindex=
  extra_mac_registers= - on/off (default: true)
  failover_pair_id=
"""

After this patch, the cpu can output its configurations,
"""
./qemu-system-riscv64 -cpu rv64,help
Enable extension:

rv64imafdch_zicbom_zicboz_zicsr_zifencei_zihintpause_zawrs_zfa_zba_zbb_zbc_zbs_sstc_svadu
"""

Signed-off-by: LIU Zhiwei 
---
 cpu.c |  2 +-
 include/hw/core/cpu.h | 11 +++
 softmmu/vl.c  | 35 +++
 3 files changed, 47 insertions(+), 1 deletion(-)

diff --git a/cpu.c b/cpu.c
index 03a313cd72..712bd02684 100644
--- a/cpu.c
+++ b/cpu.c
@@ -257,7 +257,7 @@ void cpu_exec_initfn(CPUState *cpu)
 #endif
 }
 
-static const char *cpu_type_by_name(const char *cpu_model)
+const char *cpu_type_by_name(const char *cpu_model)
 {
 ObjectClass *oc;
 const char *cpu_type;
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index fdcbe87352..49d41afdfa 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -657,6 +657,17 @@ CPUState *cpu_create(const char *typename);
  */
 const char *parse_cpu_option(const char *cpu_option);
 
+/**
+ * cpu_type_by_name:
+ * @cpu_model: The -cpu command line model name.
+ *
+ * Looks up type name by the -cpu command line model name
+ *
+ * Returns: type name of CPU or prints error and terminates process
+ *  if an error occurred.
+ */
+const char *cpu_type_by_name(const char *cpu_model);
+
 /**
  * cpu_has_work:
  * @cpu: The vCPU to check.
diff --git a/softmmu/vl.c b/softmmu/vl.c
index b0b96f67fa..bc30f3954d 100644
--- a/softmmu/vl.c
+++ b/softmmu/vl.c
@@ -218,6 +218,15 @@ static struct {
 { .driver = "virtio-vga-gl",.flag = &default_vga   },
 };
 
+static QemuOptsList qemu_cpu_opts = {
+.name = "cpu",
+.implied_opt_name = "cpu_model",
+.head = QTAILQ_HEAD_INITIALIZER(qemu_cpu_opts.head),
+.desc = {
+{ /* end of list */ }
+},
+};
+
 static QemuOptsList qemu_rtc_opts = {
 .name = "rtc",
 .head = QTAILQ_HEAD_INITIALIZER(qemu_rtc_opts.head),
@@ -1140,6 +1149,21 @@ static int parse_fw_cfg(void *opaque, QemuOpts *opts, 
Error **errp)
 return 0;
 }
 
+static int cpu_help_func(void *opaque, QemuOpts *opts, Error **errp)
+{
+const char *cpu_model, *cpu_type;
+cpu_model = qemu_opt_get(opts, "cpu_model");
+if (!cpu_model) {
+return 1;
+}
+if (!qemu_opt_has_help_opt(opts)) {
+return 0;
+}
+cpu_type = cpu_type_by_name(cpu_model);
+list_cpu_props((CPUState *)object_new(cpu_type));
+return 1;
+}
+
 static int device_help_func(void *opaque, QemuOpts *opts, Error **errp)
 {
 return qdev_device_help(opts);
@@ -2467,6 +2491,11 @@ static void qemu_process_help_options(void)
 exit(0);
 }
 
+if (qemu_opts_foreach(qemu_find_opts("cpu"),
+  cpu_help_func, NULL, NULL)) {
+exit(0);
+}
+
 if (qemu_opts_foreach(qemu_find_opts("device"),
   device_help_func, NULL, NULL)) {
 exit(0);
@@ -2680,6 +2709,7 @@ void qemu_init(int argc, char **argv)
 qemu_add_drive_opts(&bdrv_runtime_opts);
 qemu_add_opts(&qemu_chardev_opts);
 qemu_add_opts(&qemu_device_opts);
+qemu_add_opts(&qemu_cpu_opts);
 qemu_add_opts(&qemu_netdev_opts);
 qemu_add_opts(&qemu_nic_opts);
 qemu_add_opts(&qemu_net_opts);
@@ -2756,6 +2786,11 @@ void qemu_init(int argc, char **argv)
 case QEMU_OPTION_cpu:
 /* hw initialization will check this */
 cpu_option = optarg;
+opts = qemu_opts_parse_noisily(qemu_find_opts("cpu"),
+   optarg, true);
+if (!opts) {
+exit(1);
+}
 break;
 case QEMU_OPTION_hda:
 case QEMU_OPTION_hdb:
-- 
2.17.1

[RFC PATCH v2 4/6] target/riscv: Add default value for misa property

[LIU Zhiwei]

Before this patch,
"
qemu-system-riscv64 -device rv64-riscv-cpu,v=true,help

...
v=   - Vector operations
...

"

After this patch,
"
v=   - Vector operations (default: false)
"

Signed-off-by: LIU Zhiwei 
---
 target/riscv/cpu.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c2f102fae1..38838cd2c0 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1728,6 +1728,7 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
 int i;
 
 for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) {
+ObjectProperty *op;
 RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i];
 int bit = misa_cfg->misa_bit;
 
@@ -1739,14 +1740,13 @@ static void riscv_cpu_add_misa_properties(Object 
*cpu_obj)
 continue;
 }
 
-object_property_add(cpu_obj, misa_cfg->name, "bool",
-cpu_get_misa_ext_cfg,
-cpu_set_misa_ext_cfg,
-NULL, (void *)misa_cfg);
+op = object_property_add(cpu_obj, misa_cfg->name, "bool",
+ cpu_get_misa_ext_cfg,
+ cpu_set_misa_ext_cfg,
+ NULL, (void *)misa_cfg);
 object_property_set_description(cpu_obj, misa_cfg->name,
 misa_cfg->description);
-object_property_set_bool(cpu_obj, misa_cfg->name,
- misa_cfg->enabled, NULL);
+object_property_set_default_bool(op, misa_cfg->enabled);
 }
 }
 
-- 
2.17.1

[RFC PATCH v2 5/6] target/riscv: Add defalut value for string property

[LIU Zhiwei]

Before this patch,
"""
qemu-system-riscv64 -device rv64-riscv-cpu,v=true,help

...
vext_spec=
...

"""

After this patch,
"""
vext_spec=-  (default: "v1.0")
"""

Signed-off-by: LIU Zhiwei 
---
 hw/core/qdev-prop-internal.h | 2 ++
 hw/core/qdev-properties.c| 7 +++
 include/hw/qdev-properties.h | 8 
 target/riscv/cpu.c   | 2 +-
 4 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/hw/core/qdev-prop-internal.h b/hw/core/qdev-prop-internal.h
index d7b77844fe..f0613b9757 100644
--- a/hw/core/qdev-prop-internal.h
+++ b/hw/core/qdev-prop-internal.h
@@ -13,6 +13,8 @@ void qdev_propinfo_get_enum(Object *obj, Visitor *v, const 
char *name,
 void qdev_propinfo_set_enum(Object *obj, Visitor *v, const char *name,
 void *opaque, Error **errp);
 
+void qdev_propinfo_set_default_value_string(ObjectProperty *op,
+const Property *prop);
 void qdev_propinfo_set_default_value_enum(ObjectProperty *op,
   const Property *prop);
 void qdev_propinfo_set_default_value_int(ObjectProperty *op,
diff --git a/hw/core/qdev-properties.c b/hw/core/qdev-properties.c
index 357b8761b5..64f70a7292 100644
--- a/hw/core/qdev-properties.c
+++ b/hw/core/qdev-properties.c
@@ -96,6 +96,12 @@ static ObjectPropertyAccessor *field_prop_setter(const 
PropertyInfo *info)
 return info->set ? field_prop_set : NULL;
 }
 
+void qdev_propinfo_set_default_value_string(ObjectProperty *op,
+const Property *prop)
+{
+object_property_set_default_str(op, prop->defval.p);
+}
+
 void qdev_propinfo_get_enum(Object *obj, Visitor *v, const char *name,
 void *opaque, Error **errp)
 {
@@ -488,6 +494,7 @@ const PropertyInfo qdev_prop_string = {
 .release = release_string,
 .get   = get_string,
 .set   = set_string,
+.set_default_value = qdev_propinfo_set_default_value_string,
 };
 
 /* --- on/off/auto --- */
diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h
index e1df08876c..8e5651724a 100644
--- a/include/hw/qdev-properties.h
+++ b/include/hw/qdev-properties.h
@@ -22,6 +22,7 @@ struct Property {
 union {
 int64_t i;
 uint64_t u;
+void *p;
 } defval;
 int  arrayoffset;
 const PropertyInfo *arrayinfo;
@@ -91,6 +92,11 @@ extern const PropertyInfo qdev_prop_link;
 .set_default = true,   \
 .defval.u  = (_type)_defval)
 
+#define DEFINE_PROP_STR(_name, _state, _field, _defval, _prop, _type)  \
+DEFINE_PROP(_name, _state, _field, _prop, _type,   \
+.set_default = true,   \
+.defval.p  = (_type)_defval)
+
 #define DEFINE_PROP_UNSIGNED_NODEFAULT(_name, _state, _field, _prop, _type) \
 DEFINE_PROP(_name, _state, _field, _prop, _type)
 
@@ -171,6 +177,8 @@ extern const PropertyInfo qdev_prop_link;
 DEFINE_PROP_UNSIGNED(_n, _s, _f, _d, qdev_prop_size, uint64_t)
 #define DEFINE_PROP_STRING(_n, _s, _f) \
 DEFINE_PROP(_n, _s, _f, qdev_prop_string, char*)
+#define DEFINE_PROP_STRING_DEF(_n, _s, _f, _d) \
+DEFINE_PROP_STR(_n, _s, _f, _d, qdev_prop_string, char*)
 #define DEFINE_PROP_ON_OFF_AUTO(_n, _s, _f, _d) \
 DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_on_off_auto, OnOffAuto)
 #define DEFINE_PROP_SIZE32(_n, _s, _f, _d)   \
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 38838cd2c0..edcd34e62b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1769,7 +1769,7 @@ static Property riscv_cpu_extensions[] = {
 DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true),
 
 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
-DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
+DEFINE_PROP_STRING_DEF("vext_spec", RISCVCPU, cfg.vext_spec, "v1.0"),
 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
 
-- 
2.17.1

Re: [PATCH v1 7/7] hw/arm: Hook up FSI module in AST2600

[Joel Stanley]

On Fri, 25 Aug 2023 at 20:35, Ninad Palsule  wrote:
>
> This patchset introduces IBM's Flexible Service Interface(FSI).
>
> Time for some fun with inter-processor buses. FSI allows a service
> processor access to the internal buses of a host POWER processor to
> perform configuration or debugging.
>
> FSI has long existed in POWER processes and so comes with some baggage,
> including how it has been integrated into the ASPEED SoC.
>
> Working backwards from the POWER processor, the fundamental pieces of
> interest for the implementation are:
>
> 1. The Common FRU Access Macro (CFAM), an address space containing
>various "engines" that drive accesses on buses internal and external
>to the POWER chip. Examples include the SBEFIFO and I2C masters. The
>engines hang off of an internal Local Bus (LBUS) which is described
>by the CFAM configuration block.
>
> 2. The FSI slave: The slave is the terminal point of the FSI bus for
>FSI symbols addressed to it. Slaves can be cascaded off of one
>another. The slave's configuration registers appear in address space
>of the CFAM to which it is attached.
>
> 3. The FSI master: A controller in the platform service processor (e.g.
>BMC) driving CFAM engine accesses into the POWER chip. At the
>hardware level FSI is a bit-based protocol supporting synchronous and
>DMA-driven accesses of engines in a CFAM.
>
> 4. The On-Chip Peripheral Bus (OPB): A low-speed bus typically found in
>POWER processors. This now makes an appearance in the ASPEED SoC due
>to tight integration of the FSI master IP with the OPB, mainly the
>existence of an MMIO-mapping of the CFAM address straight onto a
>sub-region of the OPB address space.
>
> 5. An APB-to-OPB bridge enabling access to the OPB from the ARM core in
>the AST2600. Hardware limitations prevent the OPB from being directly
>mapped into APB, so all accesses are indirect through the bridge.
>
> The implementation appears as following in the qemu device tree:
>
> (qemu) info qtree
> bus: main-system-bus
>   type System
>   ...
>   dev: aspeed.apb2opb, id ""
> gpio-out "sysbus-irq" 1
> mmio 1e79b000/1000
> bus: opb.1
>   type opb
>   dev: fsi.master, id ""
> bus: fsi.bus.1
>   type fsi.bus
>   dev: cfam.config, id ""
>   dev: cfam, id ""
> bus: lbus.1
>   type lbus
>   dev: scratchpad, id ""
> address = 0 (0x0)
> bus: opb.0
>   type opb
>   dev: fsi.master, id ""
> bus: fsi.bus.0
>   type fsi.bus
>   dev: cfam.config, id ""
>   dev: cfam, id ""
> bus: lbus.0
>   type lbus
>   dev: scratchpad, id ""
> address = 0 (0x0)
>
> The LBUS is modelled to maintain the qdev bus hierarchy and to take
> advantage of the object model to automatically generate the CFAM
> configuration block. The configuration block presents engines in the
> order they are attached to the CFAM's LBUS. Engine implementations
> should subclass the LBusDevice and set the 'config' member of
> LBusDeviceClass to match the engine's type.
>
> CFAM designs offer a lot of flexibility, for instance it is possible for
> a CFAM to be simultaneously driven from multiple FSI links. The modeling
> is not so complete; it's assumed that each CFAM is attached to a single
> FSI slave (as a consequence the CFAM subclasses the FSI slave).
>
> As for FSI, its symbols and wire-protocol are not modelled at all. This
> is not necessary to get FSI off the ground thanks to the mapping of the
> CFAM address space onto the OPB address space - the models follow this
> directly and map the CFAM memory region into the OPB's memory region.
> Future work includes supporting more advanced accesses that drive the
> FSI master directly rather than indirectly via the CFAM mapping, which
> will require implementing the FSI state machine and methods for each of
> the FSI symbols on the slave. Further down the track we can also look at
> supporting the bitbanged SoftFSI drivers in Linux by extending the FSI
> slave model to resolve sequences of GPIO IRQs into FSI symbols, and
> calling the associated symbol method on the slave to map the access onto
> the CFAM.
>
> Testing:
> Tested by reading cfam config address 0 on rainier machine. We can
> ignore the error line as it is not related.
> root@p10bmc:~# pdbg -a getcfam 0x0
> Unable to open dtb file '/var/lib/phosphor-software-manager/pnor/rw/DEVTREE'

Delete this line (and the explanation). It's something to follow up
with the version of pdbg that openbmc has, but unrelated to this
patch.

> p0: 0x0 = 0xc0022d15
>
> Signed-off-by: Andrew Jeffery 
> Signed-off-by: Cédric Le Goater 
> Signed-off-by: Ninad Palsule 
> ---
>  hw/arm/aspeed_ast2600.c | 15 +++

[RFC PATCH v2 6/6] linux-user: Move qemu_cpu_opts to cpu.c

[LIU Zhiwei]

Make qemu_cpu_opts also works for linux user mode. Notice, currently
qdev monitor is not included in linux user mode. We just output
current enabled extentions for RISC-V(without the hint to print all
properties with -device).

With this patch,
"""
qemu-riscv64 -cpu rv64,help
Enabled extensions:

rv64_zicbom_zicboz_zicsr_zifencei_zihintpause_zawrs_zfa_zba_zbb_zbc_zbs_sstc_svadu
"""

Signed-off-by: LIU Zhiwei 
---
 cpu.c | 24 
 include/exec/cpu-common.h |  2 ++
 linux-user/main.c | 10 ++
 softmmu/vl.c  | 24 
 target/riscv/cpu.c|  8 +---
 5 files changed, 41 insertions(+), 27 deletions(-)

diff --git a/cpu.c b/cpu.c
index 712bd02684..590d75def0 100644
--- a/cpu.c
+++ b/cpu.c
@@ -47,6 +47,30 @@
 uintptr_t qemu_host_page_size;
 intptr_t qemu_host_page_mask;
 
+QemuOptsList qemu_cpu_opts = {
+.name = "cpu",
+.implied_opt_name = "cpu_model",
+.head = QTAILQ_HEAD_INITIALIZER(qemu_cpu_opts.head),
+.desc = {
+{ /* end of list */ }
+},
+};
+
+int cpu_help_func(void *opaque, QemuOpts *opts, Error **errp)
+{
+const char *cpu_model, *cpu_type;
+cpu_model = qemu_opt_get(opts, "cpu_model");
+if (!cpu_model) {
+return 1;
+}
+if (!qemu_opt_has_help_opt(opts)) {
+return 0;
+}
+cpu_type = cpu_type_by_name(cpu_model);
+list_cpu_props((CPUState *)object_new(cpu_type));
+return 1;
+}
+
 #ifndef CONFIG_USER_ONLY
 static int cpu_common_post_load(void *opaque, int version_id)
 {
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index b3160d9218..4d385436a5 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -168,4 +168,6 @@ int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
 void list_cpus(void);
 void list_cpu_props(CPUState *);
 
+int cpu_help_func(void *opaque, QemuOpts *opts, Error **errp);
+extern QemuOptsList qemu_cpu_opts;
 #endif /* CPU_COMMON_H */
diff --git a/linux-user/main.c b/linux-user/main.c
index 96be354897..c3ef84b1a7 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -362,6 +362,15 @@ static void handle_arg_cpu(const char *arg)
 list_cpus();
 exit(EXIT_FAILURE);
 }
+QemuOpts *opts = qemu_opts_parse_noisily(qemu_find_opts("cpu"),
+ arg, true);
+if (!opts) {
+exit(1);
+}
+if (qemu_opts_foreach(qemu_find_opts("cpu"),
+  cpu_help_func, NULL, NULL)) {
+exit(0);
+}
 }
 
 static void handle_arg_guest_base(const char *arg)
@@ -720,6 +729,7 @@ int main(int argc, char **argv, char **envp)
 cpu_model = NULL;
 
 qemu_add_opts(&qemu_trace_opts);
+qemu_add_opts(&qemu_cpu_opts);
 qemu_plugin_add_opts();
 
 optind = parse_args(argc, argv);
diff --git a/softmmu/vl.c b/softmmu/vl.c
index bc30f3954d..d6a395454a 100644
--- a/softmmu/vl.c
+++ b/softmmu/vl.c
@@ -218,15 +218,6 @@ static struct {
 { .driver = "virtio-vga-gl",.flag = &default_vga   },
 };
 
-static QemuOptsList qemu_cpu_opts = {
-.name = "cpu",
-.implied_opt_name = "cpu_model",
-.head = QTAILQ_HEAD_INITIALIZER(qemu_cpu_opts.head),
-.desc = {
-{ /* end of list */ }
-},
-};
-
 static QemuOptsList qemu_rtc_opts = {
 .name = "rtc",
 .head = QTAILQ_HEAD_INITIALIZER(qemu_rtc_opts.head),
@@ -1149,21 +1140,6 @@ static int parse_fw_cfg(void *opaque, QemuOpts *opts, 
Error **errp)
 return 0;
 }
 
-static int cpu_help_func(void *opaque, QemuOpts *opts, Error **errp)
-{
-const char *cpu_model, *cpu_type;
-cpu_model = qemu_opt_get(opts, "cpu_model");
-if (!cpu_model) {
-return 1;
-}
-if (!qemu_opt_has_help_opt(opts)) {
-return 0;
-}
-cpu_type = cpu_type_by_name(cpu_model);
-list_cpu_props((CPUState *)object_new(cpu_type));
-return 1;
-}
-
 static int device_help_func(void *opaque, QemuOpts *opts, Error **errp)
 {
 return qdev_device_help(opts);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index edcd34e62b..e4318fcc46 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2229,15 +2229,17 @@ void riscv_cpu_list(void)
 void riscv_cpu_list_props(CPUState *cs)
 {
 char *enabled_isa;
-RISCVCPU *cpu = RISCV_CPU(cs);
-RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
-ObjectClass *oc = OBJECT_CLASS(mcc);
 
 enabled_isa = riscv_isa_string(RISCV_CPU(cs));
 qemu_printf("Enabled extensions:\n");
 qemu_printf("\t%s\n", enabled_isa);
+#ifndef CONFIG_USER_ONLY
+RISCVCPU *cpu = RISCV_CPU(cs);
+RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
+ObjectClass *oc = OBJECT_CLASS(mcc);
 qemu_printf("To get all configuable options for this cpu, use"
 " -device %s,help\n", object_class_get_name(oc));
+#endif
 }
 
 #define DEFINE_CPU(type_name, initfn)  \
-- 
2.17.1

Re: [PATCH v1 0/7] Introduce model for IBM's FSP

[Cédric Le Goater]

Hello Ninad,

On 8/25/23 22:30, Ninad Palsule wrote:

Hello,

Please review the patch-set.

This is a first step towards introducing model for IBM's Flexible
Service Interface. The full functionality will be implemented over the
time.

Ninad Palsule (7):
   hw/fsi: Introduce IBM's Local bus
   hw/fsi: Introduce IBM's scratchpad
   hw/fsi: Introduce IBM's cfam,fsi-slave
   hw/fsi: Introduce IBM's FSI
   hw/fsi: IBM's On-chip Peripheral Bus
   hw/fsi: Aspeed APB2OPB interface
   hw/arm: Hook up FSI module in AST2600

  hw/Kconfig |   1 +
  hw/arm/Kconfig |   1 +
  hw/arm/aspeed_ast2600.c|  15 ++
  hw/fsi/Kconfig |  23 ++
  hw/fsi/aspeed-apb2opb.c| 346 +
  hw/fsi/cfam.c  | 236 
  hw/fsi/engine-scratchpad.c | 100 +
  hw/fsi/fsi-master.c| 202 +
  hw/fsi/fsi-slave.c | 109 +
  hw/fsi/fsi.c   |  54 +
  hw/fsi/lbus.c  |  94 
  hw/fsi/meson.build |   6 +
  hw/fsi/opb.c   | 194 
  hw/fsi/trace-events|   2 +
  hw/fsi/trace.h |   1 +
  hw/meson.build |   1 +
  include/hw/arm/aspeed_soc.h|   4 +
  include/hw/fsi/aspeed-apb2opb.h|  32 +++
  include/hw/fsi/bits.h  |  15 ++
  include/hw/fsi/cfam.h  |  59 +
  include/hw/fsi/engine-scratchpad.h |  32 +++
  include/hw/fsi/fsi-master.h|  30 +++
  include/hw/fsi/fsi-slave.h |  29 +++
  include/hw/fsi/fsi.h   |  35 +++
  include/hw/fsi/lbus.h  |  57 +
  include/hw/fsi/opb.h   |  45 
  meson.build|   1 +


Thanks for creating a series for these models.

I think the commit logs have a lot of useful information which would
be good for some docs/specs/ file. Please add a need a entry in
MAINTAINERS for this new bus model.
 
Tests are *very* much welcome also. Ideally we should have a couple

in qtest. A minimum would be an avocado test running pdbg.

Thanks,

C.




  27 files changed, 1724 insertions(+)
  create mode 100644 hw/fsi/Kconfig
  create mode 100644 hw/fsi/aspeed-apb2opb.c
  create mode 100644 hw/fsi/cfam.c
  create mode 100644 hw/fsi/engine-scratchpad.c
  create mode 100644 hw/fsi/fsi-master.c
  create mode 100644 hw/fsi/fsi-slave.c
  create mode 100644 hw/fsi/fsi.c
  create mode 100644 hw/fsi/lbus.c
  create mode 100644 hw/fsi/meson.build
  create mode 100644 hw/fsi/opb.c
  create mode 100644 hw/fsi/trace-events
  create mode 100644 hw/fsi/trace.h
  create mode 100644 include/hw/fsi/aspeed-apb2opb.h
  create mode 100644 include/hw/fsi/bits.h
  create mode 100644 include/hw/fsi/cfam.h
  create mode 100644 include/hw/fsi/engine-scratchpad.h
  create mode 100644 include/hw/fsi/fsi-master.h
  create mode 100644 include/hw/fsi/fsi-slave.h
  create mode 100644 include/hw/fsi/fsi.h
  create mode 100644 include/hw/fsi/lbus.h
  create mode 100644 include/hw/fsi/opb.h

Re: [PATCH v3 1/3] hw/i2c/aspeed: Fix Tx count and Rx size error in buffer pool mode

[Cédric Le Goater]

On 8/16/23 11:44, Hang Yu wrote:

Hello! Thank you for your review!Sorry I forgot to cc other maintainers so I 
resend this mail.

From: "Cédric Le Goater" 
Date: 2023-08-16 16:32:58
To:  Hang Yu ,qemu-devel@nongnu.org
Cc:  koml...@google.com,pe...@pjd.dev,Peter Maydell ,Andrew Jeffery 
,Joel Stanley ,"open list:ASPEED BMCs" 
,qemu-sta...@nongnu.org
Subject: Re: [PATCH v3 1/3] hw/i2c/aspeed: Fix Tx count and Rx size error in 
buffer pool mode>On 8/12/23 08:52, Hang Yu wrote:

Fixed inconsistency between the regisiter bit field definition header file
and the ast2600 datasheet. The reg name is I2CD1C:Pool Buffer Control
Register in old register mode and  I2CC0C: Master/Slave Pool Buffer Control
Register in new register mode. They share bit field
[12:8]:Transmit Data Byte Count and bit field
[29:24]:Actual Received Pool Buffer Size according to the datasheet.
According to the ast2600 datasheet,the actual Tx count is
Transmit Data Byte Count plus 1, and the max Rx size is
Receive Pool Buffer Size plus 1, both in Pool Buffer Control Register.
The version before forgot to plus 1, and mistake Rx count for Rx size.

Signed-off-by: Hang Yu 
Fixes: 3be3d6ccf2ad ("aspeed: i2c: Migrate to registerfields API")


This is -stable material with the following patch. It fixes support for

 >the v08.06 SDK.
Should I add this line into the commit in next version?



 >Reviewed-by: Cédric Le Goater 
Should I add your Reviewed-by tag and send v4 now?Or just wait for
other maintainers to reply?


No need for a v4. The tags are pulled automatically with the tooling
we use, b4, pwclient, etc.

I will prepare an aspeed PR for QEMU 8.1 with these patches. Then,
the first two could be backported to -stable.

Thanks,

C.



Thanks,
Hang.


Thanks,

C.



---
v2-->v3:
1. Merged patch1 and patch2 in v2
2. added fixes tag
3. Fixed typos

  hw/i2c/aspeed_i2c.c | 8 
  include/hw/i2c/aspeed_i2c.h | 4 ++--
  2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
index 1f071a3811..e485d8bfb8 100644
--- a/hw/i2c/aspeed_i2c.c
+++ b/hw/i2c/aspeed_i2c.c
@@ -236,7 +236,7 @@ static int aspeed_i2c_bus_send(AspeedI2CBus *bus, uint8_t 
pool_start)
  uint32_t reg_byte_buf = aspeed_i2c_bus_byte_buf_offset(bus);
  uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus);
  int pool_tx_count = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl,
-TX_COUNT);
+TX_COUNT) + 1;
  
  if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_BUFF_EN)) {

  for (i = pool_start; i < pool_tx_count; i++) {
@@ -293,7 +293,7 @@ static void aspeed_i2c_bus_recv(AspeedI2CBus *bus)
  uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus);
  uint32_t reg_dma_addr = aspeed_i2c_bus_dma_addr_offset(bus);
  int pool_rx_count = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl,
-RX_COUNT);
+RX_SIZE) + 1;
  
  if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_BUFF_EN)) {

  uint8_t *pool_base = aic->bus_pool_base(bus);
@@ -418,7 +418,7 @@ static void aspeed_i2c_bus_cmd_dump(AspeedI2CBus *bus)
  uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus);
  uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus);
  if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_BUFF_EN)) {
-count = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl, TX_COUNT);
+count = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl, TX_COUNT) + 
1;
  } else if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_DMA_EN)) {
  count = bus->regs[reg_dma_len];
  } else { /* BYTE mode */
@@ -490,7 +490,7 @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, 
uint64_t value)
   */
  if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_BUFF_EN)) {
  if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl, TX_COUNT)
-== 1) {
+== 0) {
  SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_TX_CMD, 0);
  } else {
  /*
diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h
index 51c944efea..2e1e15aaf0 100644
--- a/include/hw/i2c/aspeed_i2c.h
+++ b/include/hw/i2c/aspeed_i2c.h
@@ -139,9 +139,9 @@ REG32(I2CD_CMD, 0x14) /* I2CD Command/Status */
  REG32(I2CD_DEV_ADDR, 0x18) /* Slave Device Address */
  SHARED_FIELD(SLAVE_DEV_ADDR1, 0, 7)
  REG32(I2CD_POOL_CTRL, 0x1C) /* Pool Buffer Control */
-SHARED_FIELD(RX_COUNT, 24, 5)
+SHARED_FIELD(RX_COUNT, 24, 6)
  SHARED_FIELD(RX_SIZE, 16, 5)
-SHARED_FIELD(TX_COUNT, 9, 5)
+SHARED_FIELD(TX_COUNT, 8, 5)
  FIELD(I2CD_POOL_CTRL, OFFSET, 2, 6) /* AST2400 */
  REG32(I2CD_BYTE_BUF, 0x20) /* Transmit/Receive Byte Buffer */
  SHARED_FIELD(RX_BUF, 8, 8)

Re: [PATCH v1 6/7] hw/fsi: Aspeed APB2OPB interface

[Joel Stanley]

On Fri, 25 Aug 2023 at 20:31, Ninad Palsule  wrote:
>
> This is a part of patchset where IBM's Flexible Service Interface is
> introduced.
>
> An APB-to-OPB bridge enabling access to the OPB from the ARM core in
> the AST2600. Hardware limitations prevent the OPB from being directly
> mapped into APB, so all accesses are indirect through the bridge.
>
> Signed-off-by: Andrew Jeffery 
> Signed-off-by: Cédric Le Goater 
> Signed-off-by: Ninad Palsule 
> ---
>  hw/arm/Kconfig  |   1 +
>  hw/fsi/Kconfig  |   4 +
>  hw/fsi/aspeed-apb2opb.c | 346 
>  hw/fsi/meson.build  |   1 +
>  hw/fsi/trace-events |   2 +
>  hw/fsi/trace.h  |   1 +
>  include/hw/fsi/aspeed-apb2opb.h |  32 +++
>  meson.build |   1 +
>  8 files changed, 388 insertions(+)
>  create mode 100644 hw/fsi/aspeed-apb2opb.c
>  create mode 100644 hw/fsi/trace-events
>  create mode 100644 hw/fsi/trace.h
>  create mode 100644 include/hw/fsi/aspeed-apb2opb.h
>
> diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
> index 7e68348440..a6994cd9d7 100644
> --- a/hw/arm/Kconfig
> +++ b/hw/arm/Kconfig
> @@ -589,6 +589,7 @@ config FSL_IMX7
>  select PCI_EXPRESS_DESIGNWARE
>  select SDHCI
>  select UNIMP
> +select APB2OPB_ASPEED
>
>  config ARM_SMMUV3
>  bool
> diff --git a/hw/fsi/Kconfig b/hw/fsi/Kconfig
> index 560ce536db..fbb021658d 100644
> --- a/hw/fsi/Kconfig
> +++ b/hw/fsi/Kconfig
> @@ -1,3 +1,7 @@
> +config APB2OPB_ASPEED
> +bool
> +select OPB
> +
>  config OPB
>  bool
>  select CFAM
> diff --git a/hw/fsi/aspeed-apb2opb.c b/hw/fsi/aspeed-apb2opb.c
> new file mode 100644
> index 00..bbc63f2eb3
> --- /dev/null
> +++ b/hw/fsi/aspeed-apb2opb.c
> @@ -0,0 +1,346 @@
> +/*
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + * Copyright (C) 2023 IBM Corp.
> + *
> + * ASPEED APB-OPB FSI interface
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/log.h"
> +#include "qom/object.h"
> +#include "qapi/error.h"
> +#include "trace.h"
> +
> +#include "hw/fsi/aspeed-apb2opb.h"
> +#include "hw/qdev-core.h"
> +
> +#define TO_REG(x) (x >> 2)
> +#define GENMASK(t, b) (((1ULL << ((t) + 1)) - 1) & ~((1ULL << (b)) - 1))

We should put this in a common header.

> +
> +#define APB2OPB_VERSIONTO_REG(0x00)
> +#define   APB2OPB_VERSION_VER  GENMASK(7, 0)
> +
> +#define APB2OPB_TRIGGERTO_REG(0x04)
> +#define   APB2OPB_TRIGGER_EN   BIT(0)
> +
> +#define APB2OPB_CONTROLTO_REG(0x08)
> +#define   APB2OPB_CONTROL_OFF  GENMASK(31, 13)
> +
> +#define APB2OPB_OPB2FSITO_REG(0x0c)
> +#define   APB2OPB_OPB2FSI_OFF  GENMASK(31, 22)
> +
> +#define APB2OPB_OPB0_SEL   TO_REG(0x10)
> +#define APB2OPB_OPB1_SEL   TO_REG(0x28)
> +#define   APB2OPB_OPB_SEL_EN   BIT(0)
> +
> +#define APB2OPB_OPB0_MODE  TO_REG(0x14)
> +#define APB2OPB_OPB1_MODE  TO_REG(0x2c)
> +#define   APB2OPB_OPB_MODE_RD  BIT(0)
> +
> +#define APB2OPB_OPB0_XFER  TO_REG(0x18)
> +#define APB2OPB_OPB1_XFER  TO_REG(0x30)
> +#define   APB2OPB_OPB_XFER_FULLBIT(1)
> +#define   APB2OPB_OPB_XFER_HALFBIT(0)
> +
> +#define APB2OPB_OPB0_ADDR  TO_REG(0x1c)
> +#define APB2OPB_OPB0_WRITE_DATATO_REG(0x20)
> +
> +#define APB2OPB_OPB1_DMA_ENTO_REG(0x24)
> +#define APB2OPB_OPB1_DMA_EN_3  BIT(3)
> +#define APB2OPB_OPB1_DMA_EN_2  BIT(2)
> +#define APB2OPB_OPB1_DMA_EN_1  BIT(1)
> +#define APB2OPB_OPB1_DMA_EN_0  BIT(0)
> +
> +#define APB2OPB_OPB1_ADDR  TO_REG(0x34)
> +#define APB2OPB_OPB1_WRITE_DATA  TO_REG(0x38)
> +
> +#define APB2OPB_OPB_CLKTO_REG(0x3c)
> +#define   APB2OPB_OPB_CLK_SYNC BIT(0)
> +
> +#define APB2OPB_IRQ_CLEAR  TO_REG(0x40)
> +#define   APB2OPB_IRQ_CLEAR_EN BIT(0)
> +
> +#define APB2OPB_IRQ_MASK   TO_REG(0x44)
> +#define   APB2OPB_IRQ_MASK_OPB1_TX_ACK BIT(17)
> +#define   APB2OPB_IRQ_MASK_OPB0_TX_ACK BIT(16)
> +#define   APB2OPB_IRQ_MASK_CH3_TCONT   BIT(15)
> +#define   APB2OPB_IRQ_MASK_CH2_TCONT   BIT(14)
> +#define   APB2OPB_IRQ_MASK_CH1_TCONT   BIT(13)
> +#define   APB2OPB_IRQ_MASK_CH0_TCONT   BIT(12)
> +#define   APB2OPB_IRQ_MASK_CH3_FIFO_EMPTY  BIT(11)
> +#define   APB2OPB_IRQ_MASK_CH2_FIFO_EMPTY  BIT(10)
> +#define   APB2OPB_IRQ_MASK_CH1_FIFO_EMPTY  BIT(9)
> +#define   APB2OPB_IRQ_MASK_CH0_FIFO_EMPTY  BIT(8)
> +#define   APB2OPB_IRQ_MASK_CH3_FIFO_FULL   BIT(7)
> +#define   APB2OPB_IRQ_MASK_CH2_FIFO_FULL   BIT(6)
> +#define   APB2OPB_IRQ_MASK_CH1_FIFO_FULL   BIT(5)
> +#define   APB2OPB_IRQ_MASK_CH0_FIFO_FULL   BIT(4)
> +#define   APB2OPB_IRQ_MASK_CH3_DMA_EOT BIT(3)
> +#define  

Re: [PATCH v1 4/7] hw/fsi: Introduce IBM's FSI

[Joel Stanley]

On Fri, 25 Aug 2023 at 20:44, Ninad Palsule  wrote:
>
> This is a part of patchset where IBM's Flexible Service Interface is
> introduced.
>
> This commit models the FSI bus. CFAM is hanging out of FSI bus. The bus
> is model such a way that it is embeded inside the FSI master which is a
> bus controller.
>
> The FSI master: A controller in the platform service processor (e.g.
> BMC) driving CFAM engine accesses into the POWER chip. At the
> hardware level FSI is a bit-based protocol supporting synchronous and
> DMA-driven accesses of engines in a CFAM.
>
> Signed-off-by: Andrew Jeffery 
> Signed-off-by: Cédric Le Goater 
> Signed-off-by: Ninad Palsule 

Reviewed-by: Joel Stanley 

> ---
>  hw/fsi/cfam.c   |   1 +
>  hw/fsi/fsi-master.c | 203 
>  hw/fsi/fsi.c|  54 ++
>  hw/fsi/meson.build  |   2 +-
>  include/hw/fsi/cfam.h   |   2 -
>  include/hw/fsi/fsi-master.h |  30 ++
>  include/hw/fsi/fsi.h|  35 +++
>  7 files changed, 324 insertions(+), 3 deletions(-)
>  create mode 100644 hw/fsi/fsi-master.c
>  create mode 100644 hw/fsi/fsi.c
>  create mode 100644 include/hw/fsi/fsi-master.h
>  create mode 100644 include/hw/fsi/fsi.h
>
> diff --git a/hw/fsi/cfam.c b/hw/fsi/cfam.c
> index 19256050bd..12ce31cac4 100644
> --- a/hw/fsi/cfam.c
> +++ b/hw/fsi/cfam.c
> @@ -12,6 +12,7 @@
>
>  #include "hw/fsi/bits.h"
>  #include "hw/fsi/cfam.h"
> +#include "hw/fsi/fsi.h"
>  #include "hw/fsi/engine-scratchpad.h"
>
>  #include "hw/qdev-properties.h"
> diff --git a/hw/fsi/fsi-master.c b/hw/fsi/fsi-master.c
> new file mode 100644
> index 00..fe1693539a
> --- /dev/null
> +++ b/hw/fsi/fsi-master.c
> @@ -0,0 +1,203 @@
> +/*
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + * Copyright (C) 2023 IBM Corp.
> + *
> + * IBM Flexible Service Interface master
> + */
> +
> +#include "qemu/osdep.h"
> +
> +#include "qapi/error.h"
> +
> +#include "qemu/log.h"
> +
> +#include "hw/fsi/bits.h"
> +#include "hw/fsi/fsi-master.h"
> +
> +#define TYPE_OP_BUS "opb"
> +
> +#define TO_REG(x)   ((x) >> 2)
> +
> +#define FSI_MMODE   TO_REG(0x000)
> +#define   FSI_MMODE_IPOLL_DMA_ENBE_BIT(0)
> +#define   FSI_MMODE_HW_ERROR_RECOVERY_ENBE_BIT(1)
> +#define   FSI_MMODE_RELATIVE_ADDRESS_EN BE_BIT(2)
> +#define   FSI_MMODE_PARITY_CHECK_EN BE_BIT(3)
> +#define   FSI_MMODE_CLOCK_DIVIDER_0 BE_GENMASK(4, 13)
> +#define   FSI_MMODE_CLOCK_DIVIDER_1 BE_GENMASK(14, 23)
> +#define   FSI_MMODE_DEBUG_ENBE_BIT(24)
> +
> +#define FSI_MDELAY  TO_REG(0x004)
> +#define   FSI_MDELAY_ECHO_0 BE_GENMASK(0, 3)
> +#define   FSI_MDELAY_SEND_0 BE_GENMASK(4, 7)
> +#define   FSI_MDELAY_ECHO_1 BE_GENMASK(8, 11)
> +#define   FSI_MDELAY_SEND_1 BE_GENMASK(12, 15)
> +
> +#define FSI_MENP0   TO_REG(0x010)
> +#define FSI_MENP32  TO_REG(0x014)
> +#define FSI_MSENP0  TO_REG(0x018)
> +#define FSI_MLEVP0  TO_REG(0x018)
> +#define FSI_MSENP32 TO_REG(0x01c)
> +#define FSI_MLEVP32 TO_REG(0x01c)
> +#define FSI_MCENP0  TO_REG(0x020)
> +#define FSI_MREFP0  TO_REG(0x020)
> +#define FSI_MCENP32 TO_REG(0x024)
> +#define FSI_MREFP32 TO_REG(0x024)
> +
> +#define FSI_MAEBTO_REG(0x070)
> +#define   FSI_MAEB_ANY_CPU_ERRORBE_BIT(0)
> +#define   FSI_MAEB_ANY_DMA_ERRORBE_GENMASK(1, 16)
> +#define   FSI_MAEB_ANY_PARITY_ERROR BE_BIT(17)
> +
> +#define FSI_MVERTO_REG(0x074)
> +#define   FSI_MVER_VERSION  BE_GENMASK(0, 7)
> +#define   FSI_MVER_BRIDGES  BE_GENMASK(8, 15)
> +#define   FSI_MVER_PORTSBE_GENMASK(16, 23)
> +
> +#define FSI_MRESP0  TO_REG(0x0d0)
> +#define   FSI_MRESP0_RESET_PORT_GENERAL BE_BIT(0)
> +#define   FSI_MRESP0_RESET_PORT_ERROR   BE_BIT(1)
> +#define   FSI_MRESP0_RESET_ALL_BRIDGES_GENERAL  BE_BIT(2)
> +#define   FSI_MRESP0_RESET_ALL_PORTS_GENERALBE_BIT(3)
> +#define   FSI_MRESP0_RESET_MASTER   BE_BIT(4)
> +#define   FSI_MRESP0_RESET_PARITY_ERROR_LATCH   BE_BIT(5)
> +
> +#define FSI_MRESB0  TO_REG(0x1d0)
> +#define   FSI_MRESB0_RESET_GENERAL  BE_BIT(0)
> +#define   FSI_MRESB0_RESET_ERRORBE_BIT(1)
> +#define   FSI_MRESB0_SET_DMA_SUSPENDBE_BIT(5)
> +#define   FSI_MRESB0_CLEAR_DMA_SUSPEND  BE_BIT(6)
> +#define   FSI_MRESB0_SET_DELAY_MEASURE  BE_BIT(7)
> 

Re: [PATCH v1 5/7] hw/fsi: IBM's On-chip Peripheral Bus

[Joel Stanley]

On Fri, 25 Aug 2023 at 20:35, Ninad Palsule  wrote:
>
> This is a part of patchset where IBM's Flexible Service Interface is
> introduced.
>
> The On-Chip Peripheral Bus (OPB): A low-speed bus typically found in
> POWER processors. This now makes an appearance in the ASPEED SoC due
> to tight integration of the FSI master IP with the OPB, mainly the
> existence of an MMIO-mapping of the CFAM address straight onto a
> sub-region of the OPB address space.
>
> Signed-off-by: Andrew Jeffery 
> Signed-off-by: Cédric Le Goater 
> Signed-off-by: Ninad Palsule 

Reviewed-by: Joel Stanley 

> ---
>  hw/fsi/Kconfig   |   4 +
>  hw/fsi/fsi-master.c  |   3 +-
>  hw/fsi/meson.build   |   1 +
>  hw/fsi/opb.c | 194 +++
>  include/hw/fsi/opb.h |  45 ++
>  5 files changed, 245 insertions(+), 2 deletions(-)
>  create mode 100644 hw/fsi/opb.c
>  create mode 100644 include/hw/fsi/opb.h
>
> diff --git a/hw/fsi/Kconfig b/hw/fsi/Kconfig
> index 087980be22..560ce536db 100644
> --- a/hw/fsi/Kconfig
> +++ b/hw/fsi/Kconfig
> @@ -1,3 +1,7 @@
> +config OPB
> +bool
> +select CFAM
> +
>  config CFAM
>  bool
>  select FSI
> diff --git a/hw/fsi/fsi-master.c b/hw/fsi/fsi-master.c
> index fe1693539a..ba00e2bb7d 100644
> --- a/hw/fsi/fsi-master.c
> +++ b/hw/fsi/fsi-master.c
> @@ -13,8 +13,7 @@
>
>  #include "hw/fsi/bits.h"
>  #include "hw/fsi/fsi-master.h"
> -
> -#define TYPE_OP_BUS "opb"
> +#include "hw/fsi/opb.h"
>
>  #define TO_REG(x)   ((x) >> 2)
>
> diff --git a/hw/fsi/meson.build b/hw/fsi/meson.build
> index ca80d11cb9..cab645f4ea 100644
> --- a/hw/fsi/meson.build
> +++ b/hw/fsi/meson.build
> @@ -2,3 +2,4 @@ system_ss.add(when: 'CONFIG_LBUS', if_true: files('lbus.c'))
>  system_ss.add(when: 'CONFIG_SCRATCHPAD', if_true: 
> files('engine-scratchpad.c'))
>  system_ss.add(when: 'CONFIG_CFAM', if_true: files('cfam.c'))
>  system_ss.add(when: 'CONFIG_FSI', if_true: 
> files('fsi.c','fsi-master.c','fsi-slave.c'))
> +system_ss.add(when: 'CONFIG_OPB', if_true: files('opb.c'))
> diff --git a/hw/fsi/opb.c b/hw/fsi/opb.c
> new file mode 100644
> index 00..ac7693c001
> --- /dev/null
> +++ b/hw/fsi/opb.c
> @@ -0,0 +1,194 @@
> +/*
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + * Copyright (C) 2023 IBM Corp.
> + *
> + * IBM On-chip Peripheral Bus
> + */
> +
> +#include "qemu/osdep.h"
> +
> +#include "qapi/error.h"
> +#include "qemu/log.h"
> +
> +#include "hw/fsi/opb.h"
> +
> +static MemTxResult opb_read(OPBus *opb, hwaddr addr, void *data, size_t len)
> +{
> +return address_space_read(&opb->as, addr, MEMTXATTRS_UNSPECIFIED, data,
> +  len);
> +}
> +
> +uint8_t opb_read8(OPBus *opb, hwaddr addr)
> +{
> +MemTxResult tx;
> +uint8_t data;
> +
> +tx = opb_read(opb, addr, &data, sizeof(data));
> +/* FIXME: improve error handling */
> +assert(!tx);
> +
> +return data;
> +}
> +
> +uint16_t opb_read16(OPBus *opb, hwaddr addr)
> +{
> +MemTxResult tx;
> +uint16_t data;
> +
> +tx = opb_read(opb, addr, &data, sizeof(data));
> +/* FIXME: improve error handling */
> +assert(!tx);
> +
> +return data;
> +}
> +
> +uint32_t opb_read32(OPBus *opb, hwaddr addr)
> +{
> +MemTxResult tx;
> +uint32_t data;
> +
> +tx = opb_read(opb, addr, &data, sizeof(data));
> +/* FIXME: improve error handling */
> +assert(!tx);
> +
> +return data;
> +}
> +
> +static MemTxResult opb_write(OPBus *opb, hwaddr addr, void *data, size_t len)
> +{
> +return address_space_write(&opb->as, addr, MEMTXATTRS_UNSPECIFIED, data,
> +   len);
> +}
> +
> +void opb_write8(OPBus *opb, hwaddr addr, uint8_t data)
> +{
> +MemTxResult tx;
> +
> +tx = opb_write(opb, addr, &data, sizeof(data));
> +/* FIXME: improve error handling */
> +assert(!tx);
> +}
> +
> +void opb_write16(OPBus *opb, hwaddr addr, uint16_t data)
> +{
> +MemTxResult tx;
> +
> +tx = opb_write(opb, addr, &data, sizeof(data));
> +/* FIXME: improve error handling */
> +assert(!tx);
> +}
> +
> +void opb_write32(OPBus *opb, hwaddr addr, uint32_t data)
> +{
> +MemTxResult tx;
> +
> +tx = opb_write(opb, addr, &data, sizeof(data));
> +/* FIXME: improve error handling */
> +assert(!tx);
> +}
> +
> +void opb_fsi_master_address(OPBus *opb, hwaddr addr)
> +{
> +memory_region_transaction_begin();
> +memory_region_set_address(&opb->fsi.iomem, addr);
> +memory_region_transaction_commit();
> +}
> +
> +void opb_opb2fsi_address(OPBus *opb, hwaddr addr)
> +{
> +memory_region_transaction_begin();
> +memory_region_set_address(&opb->fsi.opb2fsi, addr);
> +memory_region_transaction_commit();
> +}
> +
> +static uint64_t opb_unimplemented_read(void *opaque, hwaddr addr, unsigned 
> size)
> +{
> +qemu_log_mask(LOG_UNIMP, "%s: read @0x%" HWADDR_PRIx " size=%d\n",
> +  __func__, addr, size);
> +
> +return 0;
> +}
> +
> +static voi

[PATCH] tests/avocado/machine_aspeed.py: Update SDK images

[Cédric Le Goater]

Switch to the latest v8.06 release which introduces interesting
changes for the AST2600 I2C and I3C models. Also take the AST2600 A2
images instead of the default since QEMU tries to model The AST2600 A3
SoC.

Signed-off-by: Cédric Le Goater 
---

  Requires patches from Hang Yu [1]
  
  [1] 
https://lore.kernel.org/qemu-devel/20230812065230.8839-1-francis_...@stu.pku.edu.cn/


 tests/avocado/machine_aspeed.py | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/tests/avocado/machine_aspeed.py b/tests/avocado/machine_aspeed.py
index 724ee72c0208..90f1b7cb77a1 100644
--- a/tests/avocado/machine_aspeed.py
+++ b/tests/avocado/machine_aspeed.py
@@ -316,8 +316,8 @@ def test_arm_ast2500_evb_sdk(self):
 """
 
 image_url = ('https://github.com/AspeedTech-BMC/openbmc/releases/'
- 'download/v08.01/ast2500-default-obmc.tar.gz')
-image_hash = 
('5375f82b4c43a79427909342a1e18b4e48bd663e38466862145d27bb358796fd')
+ 'download/v08.06/ast2500-default-obmc.tar.gz')
+image_hash = 
('e1755f3cadff69190438c688d52dd0f0d399b70a1e14b1d3d5540fc4851d38ca')
 image_path = self.fetch_asset(image_url, asset_hash=image_hash,
   algorithm='sha256')
 archive.extract(image_path, self.workdir)
@@ -334,8 +334,8 @@ def test_arm_ast2600_evb_sdk(self):
 """
 
 image_url = ('https://github.com/AspeedTech-BMC/openbmc/releases/'
- 'download/v08.01/ast2600-default-obmc.tar.gz')
-image_hash = 
('f12ef15e8c1f03a214df3b91c814515c5e2b2f56119021398c1dbdd626817d15')
+ 'download/v08.06/ast2600-a2-obmc.tar.gz')
+image_hash = 
('9083506135f622d5e7351fcf7d4e1c7125cee5ba16141220c0ba88931f3681a4')
 image_path = self.fetch_asset(image_url, asset_hash=image_hash,
   algorithm='sha256')
 archive.extract(image_path, self.workdir)
@@ -345,8 +345,8 @@ def test_arm_ast2600_evb_sdk(self):
 self.vm.add_args('-device',
  'ds1338,bus=aspeed.i2c.bus.5,address=0x32');
 self.do_test_arm_aspeed_sdk_start(
-self.workdir + '/ast2600-default/image-bmc')
-self.wait_for_console_pattern('nodistro.0 ast2600-default ttyS4')
+self.workdir + '/ast2600-a2/image-bmc')
+self.wait_for_console_pattern('nodistro.0 ast2600-a2 ttyS4')
 
 self.ssh_connect('root', '0penBmc', False)
 self.ssh_command('dmesg -c > /dev/null')
-- 
2.41.0

[RESEND PATCH] target/ppc: Fix the order of kvm_enable judgment about kvmppc_set_interrupt()

[jianchunfu]

It's unnecessary for non-KVM accelerators(TCG, for example),
to call this function, so change the order of kvm_enable() judgment.

The static inline function that returns -1 directly does not work
 in TCG's situation.

Signed-off-by: jianchunfu 
---
 hw/ppc/ppc.c | 8 ++--
 target/ppc/kvm.c | 2 +-
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index 0e0a3d93c3..3e96b24487 100644
--- a/hw/ppc/ppc.c
+++ b/hw/ppc/ppc.c
@@ -58,7 +58,9 @@ void ppc_set_irq(PowerPCCPU *cpu, int irq, int level)
 
 if (old_pending != env->pending_interrupts) {
 ppc_maybe_interrupt(env);
-kvmppc_set_interrupt(cpu, irq, level);
+if (kvm_enabled()) {
+kvmppc_set_interrupt(cpu, irq, level);
+}
 }
 
 trace_ppc_irq_set_exit(env, irq, level, env->pending_interrupts,
@@ -1465,5 +1467,7 @@ void ppc_irq_reset(PowerPCCPU *cpu)
 CPUPPCState *env = &cpu->env;
 
 env->irq_input_state = 0;
-kvmppc_set_interrupt(cpu, PPC_INTERRUPT_EXT, 0);
+if (kvm_enabled()) {
+kvmppc_set_interrupt(cpu, PPC_INTERRUPT_EXT, 0);
+}
 }
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index a8a935e267..11a1fbc244 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -1315,7 +1315,7 @@ int kvmppc_set_interrupt(PowerPCCPU *cpu, int irq, int 
level)
 return 0;
 }
 
-if (!kvm_enabled() || !cap_interrupt_unset) {
+if (!cap_interrupt_unset) {
 return 0;
 }
 
-- 
2.27.0

Re: [PATCH v2 2/4] qcow2: add configurations for zoned format extension

[Sam Li]

Markus Armbruster  于2023年8月21日周一 21:13写道：
>
> Sam Li  writes:
>
> > To configure the zoned format feature on the qcow2 driver, it
> > requires following arguments: the device size, zoned profile,
> > zoned model, zone size, zone capacity, number of conventional
> > zones, limits on zone resources (max append sectors, max open
> > zones, and max_active_zones). The zoned profile option is set
> > to zns when using the qcow2 file as a ZNS drive.
> >
> > To create a qcow2 file with zoned format, use command like this:
> > $ qemu-img create -f qcow2 test.qcow2 -o size=768M -o
> > zone_size=64M -o zone_capacity=64M -o zone_nr_conv=0 -o
> > max_append_sectors=512 -o max_open_zones=0 -o max_active_zones=0
> >  -o zoned_profile=zbc/zns
> >
> > Signed-off-by: Sam Li 
>
> [...]
>
> > diff --git a/qapi/block-core.json b/qapi/block-core.json
> > index 2b1d493d6e..0c97ae678b 100644
> > --- a/qapi/block-core.json
> > +++ b/qapi/block-core.json
> > @@ -5020,24 +5020,42 @@
> >  #
> >  # @compression-type: The image cluster compression method
> >  # (default: zlib, since 5.1)
> > +# @zoned-profile: Two zoned device protocol options, zbc or zns
> > +# (default: off, since 8.0)
>
> When a 'str' thing accepts a fixed set of (string) values, it most
> likely should be an enum instead.  Have you considered making
> @zoned-profile one?
>
> > +# @zone-size: The size of a zone of the zoned device (since 8.0)
> > +# @zone-capacity: The capacity of a zone of the zoned device (since 8.0)
>
> In bytes, I presume?

Yes.

>
> What's the difference between size and capacity?
>

Zone size is the total number of logical blocks within zones in bytes.
Zone capacity is the number of usable logical blocks within zones in
bytes. A zone capacity is always smaller or equal to than zone size.
According to ZBC/ZAC standards, a zone capacity is equal to the zone
size. While in ZNS spec, it can be smaller. I will add the
documentation and below in the next patches.

> > +# @zone-nr-conv: The number of conventional zones of the zoned device
> > +#(since 8.0)
> > +# @max-open-zones: The maximal allowed open zones (since 8.0)
> > +# @max-active-zones: The limit of the zones that have the implicit open,
> > +#explicit open or closed state (since 8.0)
>
> Naming...  if I understand the comment correctly, then @zone-nr-conv,
> @max-open-zones, and @max-active-zones are all counting zones.  Rename
> @zone-nr-conv to @conventional-zones?
>
> > +# @max-append-sectors: The maximal sectors that is allowed to append write
>
> I'm not sure I understand the explanation.  Elaborate for me?

The max_append_sector is the maximum data size (in sectors) of a zone
append request that can be successfully issued to the device.  It is a
constraint on the maximum amount of data that can be appended to a
zone in a single request.

>
> > +#  (since 8.0)
>
> Please format like
>
>#
># @zoned-profile: Two zoned device protocol options, zbc or zns
># (default: off, since 8.0)
>#
># @zone-size: The size of a zone of the zoned device (since 8.0)
>#
># @zone-capacity: The capacity of a zone of the zoned device
># (since 8.0)
>#
># @zone-nr-conv: The number of conventional zones of the zoned device
># (since 8.0)
>#
># @max-open-zones: The maximal allowed open zones (since 8.0)
>#
># @max-active-zones: The limit of the zones that have the implicit
># open, explicit open or closed state (since 8.0)
>#
># @max-append-sectors: The maximal sectors that is allowed to append
># write (since 8.0)
>
> to blend in with recent commit a937b6aa739 (qapi: Reformat doc comments
> to conform to current conventions).
>
> >  #
> >  # Since: 2.12
> >  ##
> >  { 'struct': 'BlockdevCreateOptionsQcow2',
> > -  'data': { 'file': 'BlockdevRef',
> > -'*data-file':   'BlockdevRef',
> > -'*data-file-raw':   'bool',
> > -'*extended-l2': 'bool',
> > -'size': 'size',
> > -'*version': 'BlockdevQcow2Version',
> > -'*backing-file':'str',
> > -'*backing-fmt': 'BlockdevDriver',
> > -'*encrypt': 'QCryptoBlockCreateOptions',
> > -'*cluster-size':'size',
> > -'*preallocation':   'PreallocMode',
> > -'*lazy-refcounts':  'bool',
> > -'*refcount-bits':   'int',
> > -'*compression-type':'Qcow2CompressionType' } }
> > +  'data': { 'file':'BlockdevRef',
> > +'*data-file':  'BlockdevRef',
> > +'*data-file-raw':  'bool',
> > +'*extended-l2':'bool',
> > +'size':'size',
> > +'*version':'BlockdevQcow2Version',
> > +'*backing-file':   'str',
> > +'*backing-fmt':'BlockdevDriver',
> > +  

Re: [PATCH v2 2/4] qcow2: add configurations for zoned format extension

[Sam Li]

Stefan Hajnoczi  于2023年8月21日周一 21:31写道：
>
> On Mon, Aug 14, 2023 at 04:58:00PM +0800, Sam Li wrote:
> > diff --git a/block/qcow2.h b/block/qcow2.h
> > index f789ce3ae0..3694c8d217 100644
> > --- a/block/qcow2.h
> > +++ b/block/qcow2.h
> > @@ -236,6 +236,20 @@ typedef struct Qcow2CryptoHeaderExtension {
> >  uint64_t length;
> >  } QEMU_PACKED Qcow2CryptoHeaderExtension;
> >
> > +typedef struct Qcow2ZonedHeaderExtension {
> > +/* Zoned device attributes */
> > +uint8_t zoned_profile;
> > +uint8_t zoned;
> > +uint16_t reserved16;
> > +uint32_t zone_size;
> > +uint32_t zone_capacity;
>
> Should zone capacity be stored individually for each zone (alongside the
> write pointer and other per zone metadata) instead of as a global value
> for all zones? My understanding is that NVMe ZNS does not have a global
> value and each zone could have a different zone capacity value.

Though zone capacity is per-zone attribute, it remains same for all
zones in most cases. Referring to the NVMe ZNS spec, zone capacity
changes associate to RESET_ZONE op when the variable zone capacity bit
is '1'. It hasn't specifically tell what it is changed to. Current ZNS
emulation doesn't change zone capacity as well.

If the Variable Zone Capacity bit is cleared to ‘0’ in the Zone
Operation Characteristics field in the Zoned
Namespace Command Set specific Identify Namespace data structure, then
this field does not change without a change to the format of the zoned
namespace.

If the Variable Zone Capacity bit is set to ‘1’ in the Zone Operation
Characteristics field in the Zoned
Namespace Command Set specific Identify Namespace data structure, then
the zone capacity may
change upon successful completion of a Zone Management Send command
specifying the Zone Send
Action of Reset Zone.

>
> > +uint32_t nr_zones;
>
> Is this field necessary since it can be derived from other image
> options: nr_zones = DIV_ROUND_UP(total_length, zone_capacity)?

It can be dropped. I added this for reducing duplication. Thanks!

Re: [PATCH v2 2/4] qcow2: add configurations for zoned format extension

[Damien Le Moal]

On 8/28/23 18:22, Sam Li wrote:
> Stefan Hajnoczi  于2023年8月21日周一 21:31写道：
>>
>> On Mon, Aug 14, 2023 at 04:58:00PM +0800, Sam Li wrote:
>>> diff --git a/block/qcow2.h b/block/qcow2.h
>>> index f789ce3ae0..3694c8d217 100644
>>> --- a/block/qcow2.h
>>> +++ b/block/qcow2.h
>>> @@ -236,6 +236,20 @@ typedef struct Qcow2CryptoHeaderExtension {
>>>  uint64_t length;
>>>  } QEMU_PACKED Qcow2CryptoHeaderExtension;
>>>
>>> +typedef struct Qcow2ZonedHeaderExtension {
>>> +/* Zoned device attributes */
>>> +uint8_t zoned_profile;
>>> +uint8_t zoned;
>>> +uint16_t reserved16;
>>> +uint32_t zone_size;
>>> +uint32_t zone_capacity;
>>
>> Should zone capacity be stored individually for each zone (alongside the
>> write pointer and other per zone metadata) instead of as a global value
>> for all zones? My understanding is that NVMe ZNS does not have a global
>> value and each zone could have a different zone capacity value.
> 
> Though zone capacity is per-zone attribute, it remains same for all
> zones in most cases. Referring to the NVMe ZNS spec, zone capacity
> changes associate to RESET_ZONE op when the variable zone capacity bit
> is '1'. It hasn't specifically tell what it is changed to. Current ZNS
> emulation doesn't change zone capacity as well.
> 
> If the Variable Zone Capacity bit is cleared to ‘0’ in the Zone
> Operation Characteristics field in the Zoned
> Namespace Command Set specific Identify Namespace data structure, then
> this field does not change without a change to the format of the zoned
> namespace.
> 
> If the Variable Zone Capacity bit is set to ‘1’ in the Zone Operation
> Characteristics field in the Zoned
> Namespace Command Set specific Identify Namespace data structure, then
> the zone capacity may
> change upon successful completion of a Zone Management Send command
> specifying the Zone Send
> Action of Reset Zone.

Regardless of the variable zone capacity feature, zone capacity is per zone and
may be different between zones. That is why it is reported per zone in zone
report. The IO path code should not assume that the zone capacity is the same
for all zones.

For this particular case though, given that this is QCow2 emulation, limiting
ourselves to the same zone capacity for all zones is I think fine. But that
should be clearly stated somewhere may be...

> 
>>
>>> +uint32_t nr_zones;
>>
>> Is this field necessary since it can be derived from other image
>> options: nr_zones = DIV_ROUND_UP(total_length, zone_capacity)?
> 
> It can be dropped. I added this for reducing duplication. Thanks!

-- 
Damien Le Moal
Western Digital Research

Re: [PATCH v2 2/4] qcow2: add configurations for zoned format extension

[Sam Li]

Damien Le Moal  于2023年8月28日周一 18:13写道：
>
> On 8/28/23 18:22, Sam Li wrote:
> > Stefan Hajnoczi  于2023年8月21日周一 21:31写道：
> >>
> >> On Mon, Aug 14, 2023 at 04:58:00PM +0800, Sam Li wrote:
> >>> diff --git a/block/qcow2.h b/block/qcow2.h
> >>> index f789ce3ae0..3694c8d217 100644
> >>> --- a/block/qcow2.h
> >>> +++ b/block/qcow2.h
> >>> @@ -236,6 +236,20 @@ typedef struct Qcow2CryptoHeaderExtension {
> >>>  uint64_t length;
> >>>  } QEMU_PACKED Qcow2CryptoHeaderExtension;
> >>>
> >>> +typedef struct Qcow2ZonedHeaderExtension {
> >>> +/* Zoned device attributes */
> >>> +uint8_t zoned_profile;
> >>> +uint8_t zoned;
> >>> +uint16_t reserved16;
> >>> +uint32_t zone_size;
> >>> +uint32_t zone_capacity;
> >>
> >> Should zone capacity be stored individually for each zone (alongside the
> >> write pointer and other per zone metadata) instead of as a global value
> >> for all zones? My understanding is that NVMe ZNS does not have a global
> >> value and each zone could have a different zone capacity value.
> >
> > Though zone capacity is per-zone attribute, it remains same for all
> > zones in most cases. Referring to the NVMe ZNS spec, zone capacity
> > changes associate to RESET_ZONE op when the variable zone capacity bit
> > is '1'. It hasn't specifically tell what it is changed to. Current ZNS
> > emulation doesn't change zone capacity as well.
> >
> > If the Variable Zone Capacity bit is cleared to ‘0’ in the Zone
> > Operation Characteristics field in the Zoned
> > Namespace Command Set specific Identify Namespace data structure, then
> > this field does not change without a change to the format of the zoned
> > namespace.
> >
> > If the Variable Zone Capacity bit is set to ‘1’ in the Zone Operation
> > Characteristics field in the Zoned
> > Namespace Command Set specific Identify Namespace data structure, then
> > the zone capacity may
> > change upon successful completion of a Zone Management Send command
> > specifying the Zone Send
> > Action of Reset Zone.
>
> Regardless of the variable zone capacity feature, zone capacity is per zone 
> and
> may be different between zones. That is why it is reported per zone in zone
> report. The IO path code should not assume that the zone capacity is the same
> for all zones.

How is zone capacity changed, by devices or commands? Can you give
some example please?

>
> For this particular case though, given that this is QCow2 emulation, limiting
> ourselves to the same zone capacity for all zones is I think fine. But that
> should be clearly stated somewhere may be...

I see. The qcow2 documentaion can add that.

>
> >
> >>
> >>> +uint32_t nr_zones;
> >>
> >> Is this field necessary since it can be derived from other image
> >> options: nr_zones = DIV_ROUND_UP(total_length, zone_capacity)?
> >
> > It can be dropped. I added this for reducing duplication. Thanks!
>
> --
> Damien Le Moal
> Western Digital Research
>

Re: [PATCH v2 2/4] qcow2: add configurations for zoned format extension

[Damien Le Moal]

On 8/28/23 19:18, Sam Li wrote:
> Damien Le Moal  于2023年8月28日周一 18:13写道：
>>
>> On 8/28/23 18:22, Sam Li wrote:
>>> Stefan Hajnoczi  于2023年8月21日周一 21:31写道：

 On Mon, Aug 14, 2023 at 04:58:00PM +0800, Sam Li wrote:
> diff --git a/block/qcow2.h b/block/qcow2.h
> index f789ce3ae0..3694c8d217 100644
> --- a/block/qcow2.h
> +++ b/block/qcow2.h
> @@ -236,6 +236,20 @@ typedef struct Qcow2CryptoHeaderExtension {
>  uint64_t length;
>  } QEMU_PACKED Qcow2CryptoHeaderExtension;
>
> +typedef struct Qcow2ZonedHeaderExtension {
> +/* Zoned device attributes */
> +uint8_t zoned_profile;
> +uint8_t zoned;
> +uint16_t reserved16;
> +uint32_t zone_size;
> +uint32_t zone_capacity;

 Should zone capacity be stored individually for each zone (alongside the
 write pointer and other per zone metadata) instead of as a global value
 for all zones? My understanding is that NVMe ZNS does not have a global
 value and each zone could have a different zone capacity value.
>>>
>>> Though zone capacity is per-zone attribute, it remains same for all
>>> zones in most cases. Referring to the NVMe ZNS spec, zone capacity
>>> changes associate to RESET_ZONE op when the variable zone capacity bit
>>> is '1'. It hasn't specifically tell what it is changed to. Current ZNS
>>> emulation doesn't change zone capacity as well.
>>>
>>> If the Variable Zone Capacity bit is cleared to ‘0’ in the Zone
>>> Operation Characteristics field in the Zoned
>>> Namespace Command Set specific Identify Namespace data structure, then
>>> this field does not change without a change to the format of the zoned
>>> namespace.
>>>
>>> If the Variable Zone Capacity bit is set to ‘1’ in the Zone Operation
>>> Characteristics field in the Zoned
>>> Namespace Command Set specific Identify Namespace data structure, then
>>> the zone capacity may
>>> change upon successful completion of a Zone Management Send command
>>> specifying the Zone Send
>>> Action of Reset Zone.
>>
>> Regardless of the variable zone capacity feature, zone capacity is per zone 
>> and
>> may be different between zones. That is why it is reported per zone in zone
>> report. The IO path code should not assume that the zone capacity is the same
>> for all zones.
> 
> How is zone capacity changed, by devices or commands? Can you give
> some example please?

If the device does not support variable zone capacity, the zone capacity is
fixed at device manufacturing time and never changes. It is reported per zone
and you have to make things work with whatever value you see. The user cannot
change device zone capacity.

For you qcow2 zoned image, the equivalent is to fix the zone capacity when the
image is created and not allowing to change it. And for simplicity, the same
zone capacity value can be used for all zones, so having the zone capacity
value in the header is OK.

> 
>>
>> For this particular case though, given that this is QCow2 emulation, limiting
>> ourselves to the same zone capacity for all zones is I think fine. But that
>> should be clearly stated somewhere may be...
> 
> I see. The qcow2 documentaion can add that.
> 
>>
>>>

> +uint32_t nr_zones;

 Is this field necessary since it can be derived from other image
 options: nr_zones = DIV_ROUND_UP(total_length, zone_capacity)?
>>>
>>> It can be dropped. I added this for reducing duplication. Thanks!
>>
>> --
>> Damien Le Moal
>> Western Digital Research
>>

-- 
Damien Le Moal
Western Digital Research

[PULL 03/14] python: mkvenv: tweak the matching of --diagnose to depspecs

[Paolo Bonzini]

Move the matching between the "absent" array and dep_specs[0] inside
the loop, preparing for the possibility of having multiple canaries
among the installed packages.

Signed-off-by: Paolo Bonzini 
---
 python/scripts/mkvenv.py | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/python/scripts/mkvenv.py b/python/scripts/mkvenv.py
index a47f1eaf5d6..399659b22f1 100644
--- a/python/scripts/mkvenv.py
+++ b/python/scripts/mkvenv.py
@@ -806,6 +806,7 @@ def _do_ensure(
 """
 absent = []
 present = []
+canary = None
 for spec in dep_specs:
 matcher = distlib.version.LegacyMatcher(spec)
 ver = _get_version(matcher.name)
@@ -817,6 +818,8 @@ def _do_ensure(
 or not matcher.match(distlib.version.LegacyVersion(ver))
 ):
 absent.append(spec)
+if spec == dep_specs[0]:
+canary = prog
 else:
 logger.info("found %s %s", matcher.name, ver)
 present.append(matcher.name)
@@ -839,7 +842,7 @@ def _do_ensure(
 absent[0],
 online,
 wheels_dir,
-prog if absent[0] == dep_specs[0] else None,
+canary,
 )
 
 return None
-- 
2.41.0

[PULL 13/14] configure: fix container_hosts misspellings and duplications

[Paolo Bonzini]

container_hosts is matched against $cpu, so it must contain QEMU
canonical architecture names, not Debian architecture names.
Also do not set $container_hosts inside the loop, since it is
already set before.

Reviewed-by: Richard Henderson 
Signed-off-by: Paolo Bonzini 
---
 configure | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/configure b/configure
index e4d42d640e4..08bf24b689c 100755
--- a/configure
+++ b/configure
@@ -1352,7 +1352,7 @@ probe_target_compiler() {
 sh4) container_hosts=x86_64 ;;
 sparc64) container_hosts=x86_64 ;;
 tricore) container_hosts=x86_64 ;;
-x86_64) container_hosts="aarch64 ppc64el x86_64" ;;
+x86_64) container_hosts="aarch64 ppc64le x86_64" ;;
 xtensa*) container_hosts=x86_64 ;;
   esac
 
@@ -1459,7 +1459,6 @@ probe_target_compiler() {
 container_cross_prefix=x86_64-linux-gnu-
 ;;
   xtensa*)
-container_hosts=x86_64
 container_image=debian-xtensa-cross
 
 # default to the dc232b cpu
-- 
2.41.0

[PULL 11/14] tests/docker: add python3-tomli dependency to containers

[Paolo Bonzini]

Instead of having CI pick tomli from the vendored wheel at configure
time, place it in the containers.

Signed-off-by: Paolo Bonzini 
---
 .gitlab-ci.d/cirrus/freebsd-13.vars  |  2 +-
 .gitlab-ci.d/cirrus/macos-12.vars|  2 +-
 tests/docker/dockerfiles/centos8.docker  |  3 ++-
 .../dockerfiles/debian-all-test-cross.docker |  7 ++-
 .../docker/dockerfiles/debian-amd64-cross.docker |  4 
 tests/docker/dockerfiles/debian-amd64.docker |  4 
 .../docker/dockerfiles/debian-arm64-cross.docker |  4 
 .../docker/dockerfiles/debian-armel-cross.docker |  4 
 .../docker/dockerfiles/debian-armhf-cross.docker |  4 
 .../dockerfiles/debian-hexagon-cross.docker  |  6 +-
 .../dockerfiles/debian-mips64el-cross.docker |  4 
 .../dockerfiles/debian-mipsel-cross.docker   |  4 
 .../dockerfiles/debian-ppc64el-cross.docker  |  4 
 .../docker/dockerfiles/debian-s390x-cross.docker |  4 
 .../dockerfiles/debian-tricore-cross.docker  |  2 ++
 .../docker/dockerfiles/fedora-i386-cross.docker  |  1 +
 tests/docker/dockerfiles/ubuntu2004.docker   |  4 +++-
 tests/docker/dockerfiles/ubuntu2204.docker   |  1 +
 tests/lcitool/mappings.yml   | 16 
 tests/lcitool/projects/qemu.yml  |  1 +
 tests/vm/generated/freebsd.json  |  1 +
 21 files changed, 76 insertions(+), 6 deletions(-)

diff --git a/.gitlab-ci.d/cirrus/freebsd-13.vars 
b/.gitlab-ci.d/cirrus/freebsd-13.vars
index facb649f5bd..3785afca36d 100644
--- a/.gitlab-ci.d/cirrus/freebsd-13.vars
+++ b/.gitlab-ci.d/cirrus/freebsd-13.vars
@@ -11,6 +11,6 @@ MAKE='/usr/local/bin/gmake'
 NINJA='/usr/local/bin/ninja'
 PACKAGING_COMMAND='pkg'
 PIP3='/usr/local/bin/pip-3.8'
-PKGS='alsa-lib bash bison bzip2 ca_root_nss capstone4 ccache cmocka ctags curl 
cyrus-sasl dbus diffutils dtc flex fusefs-libs3 gettext git glib gmake gnutls 
gsed gtk3 json-c libepoxy libffi libgcrypt libjpeg-turbo libnfs libslirp 
libspice-server libssh libtasn1 llvm lzo2 meson mtools ncurses nettle ninja 
opencv pixman pkgconf png py39-numpy py39-pillow py39-pip py39-sphinx 
py39-sphinx_rtd_theme py39-yaml python3 rpm2cpio sdl2 sdl2_image snappy sndio 
socat spice-protocol tesseract usbredir virglrenderer vte3 xorriso zstd'
+PKGS='alsa-lib bash bison bzip2 ca_root_nss capstone4 ccache cmocka ctags curl 
cyrus-sasl dbus diffutils dtc flex fusefs-libs3 gettext git glib gmake gnutls 
gsed gtk3 json-c libepoxy libffi libgcrypt libjpeg-turbo libnfs libslirp 
libspice-server libssh libtasn1 llvm lzo2 meson mtools ncurses nettle ninja 
opencv pixman pkgconf png py39-numpy py39-pillow py39-pip py39-sphinx 
py39-sphinx_rtd_theme py39-tomli py39-yaml python3 rpm2cpio sdl2 sdl2_image 
snappy sndio socat spice-protocol tesseract usbredir virglrenderer vte3 xorriso 
zstd'
 PYPI_PKGS=''
 PYTHON='/usr/local/bin/python3'
diff --git a/.gitlab-ci.d/cirrus/macos-12.vars 
b/.gitlab-ci.d/cirrus/macos-12.vars
index ceb294e1539..80eadaab296 100644
--- a/.gitlab-ci.d/cirrus/macos-12.vars
+++ b/.gitlab-ci.d/cirrus/macos-12.vars
@@ -12,5 +12,5 @@ NINJA='/opt/homebrew/bin/ninja'
 PACKAGING_COMMAND='brew'
 PIP3='/opt/homebrew/bin/pip3'
 PKGS='bash bc bison bzip2 capstone ccache cmocka ctags curl dbus diffutils dtc 
flex gcovr gettext git glib gnu-sed gnutls gtk+3 jemalloc jpeg-turbo json-c 
libepoxy libffi libgcrypt libiscsi libnfs libpng libslirp libssh libtasn1 
libusb llvm lzo make meson mtools ncurses nettle ninja pixman pkg-config 
python3 rpm2cpio sdl2 sdl2_image snappy socat sparse spice-protocol tesseract 
usbredir vde vte3 xorriso zlib zstd'
-PYPI_PKGS='PyYAML numpy pillow sphinx sphinx-rtd-theme'
+PYPI_PKGS='PyYAML numpy pillow sphinx sphinx-rtd-theme tomli'
 PYTHON='/opt/homebrew/bin/python3'
diff --git a/tests/docker/dockerfiles/centos8.docker 
b/tests/docker/dockerfiles/centos8.docker
index da7dc818fb6..fc1830966f4 100644
--- a/tests/docker/dockerfiles/centos8.docker
+++ b/tests/docker/dockerfiles/centos8.docker
@@ -133,7 +133,8 @@ RUN /usr/bin/pip3.8 install \
 meson==0.63.2 \
 pillow \
 sphinx \
-sphinx-rtd-theme
+sphinx-rtd-theme \
+tomli
 
 ENV CCACHE_WRAPPERSDIR "/usr/libexec/ccache-wrappers"
 ENV LANG "en_US.UTF-8"
diff --git a/tests/docker/dockerfiles/debian-all-test-cross.docker 
b/tests/docker/dockerfiles/debian-all-test-cross.docker
index f9f401544a0..54e957d5e74 100644
--- a/tests/docker/dockerfiles/debian-all-test-cross.docker
+++ b/tests/docker/dockerfiles/debian-all-test-cross.docker
@@ -58,7 +58,12 @@ RUN DEBIAN_FRONTEND=noninteractive eatmydata \
 libc6-dev-sh4-cross \
 gcc-sparc64-linux-gnu \
 libc6-dev-sparc64-cross \
-python3-venv
+python3-pip \
+python3-setuptools \
+python3-venv \
+python3-wheel
+
+RUN /usr/bin/pip3 install tomli
 
 ENV QEMU_CONFIGURE_OPTS --d

[PULL 04/14] python: mkvenv: introduce TOML-like representation of dependencies

[Paolo Bonzini]

We would like to place all Python dependencies in the same file, so that
we can add more information without having long and complex command lines.
The plan is to have a TOML file with one entry per package, for example

  [avocado]
  avocado-framework = {
accepted = "(>=88.1, <93.0)",
installed = "88.1",
canary = "avocado"
  }

Each TOML section will thus be a dictionary of dictionaries.  Modify
mkvenv.py's workhorse function, _do_ensure, to already operate on such
a data structure.  The "ensure" subcommand is modified to separate the
depspec into a name and a version part, and use the result (plus the
--diagnose argument) to build a dictionary for each command line argument.

Signed-off-by: Paolo Bonzini 
---
 python/scripts/mkvenv.py | 77 +++-
 1 file changed, 61 insertions(+), 16 deletions(-)

diff --git a/python/scripts/mkvenv.py b/python/scripts/mkvenv.py
index 399659b22f1..96f506d7e22 100644
--- a/python/scripts/mkvenv.py
+++ b/python/scripts/mkvenv.py
@@ -46,6 +46,9 @@
 
 """
 
+# The duplication between importlib and pkg_resources does not help
+# pylint: disable=too-many-lines
+
 # Copyright (C) 2022-2023 Red Hat, Inc.
 #
 # Authors:
@@ -69,6 +72,7 @@
 from types import SimpleNamespace
 from typing import (
 Any,
+Dict,
 Iterator,
 Optional,
 Sequence,
@@ -786,43 +790,67 @@ def pip_install(
 )
 
 
+def _make_version_constraint(info: Dict[str, str], install: bool) -> str:
+"""
+Construct the version constraint part of a PEP 508 dependency
+specification (for example '>=0.61.5') from the accepted and
+installed keys of the provided dictionary.
+
+:param info: A dictionary corresponding to a TOML key-value list.
+:param install: True generates install constraints, False generates
+presence constraints
+"""
+if install and "installed" in info:
+return "==" + info["installed"]
+
+dep_spec = info.get("accepted", "")
+dep_spec = dep_spec.strip()
+# Double check that they didn't just use a version number
+if dep_spec and dep_spec[0] not in "!~><=(":
+raise Ouch(
+"invalid dependency specifier " + dep_spec + " in dependency file"
+)
+
+return dep_spec
+
+
 def _do_ensure(
-dep_specs: Sequence[str],
+group: Dict[str, Dict[str, str]],
 online: bool = False,
 wheels_dir: Optional[Union[str, Path]] = None,
-prog: Optional[str] = None,
 ) -> Optional[Tuple[str, bool]]:
 """
-Use pip to ensure we have the package specified by @dep_specs.
+Use pip to ensure we have the packages specified in @group.
 
-If the package is already installed, do nothing. If online and
+If the packages are already installed, do nothing. If online and
 wheels_dir are both provided, prefer packages found in wheels_dir
 first before connecting to PyPI.
 
-:param dep_specs:
-PEP 508 dependency specifications. e.g. ['meson>=0.61.5'].
+:param group: A dictionary of dictionaries, corresponding to a
+section in a pythondeps.toml file.
 :param online: If True, fall back to PyPI.
 :param wheels_dir: If specified, search this path for packages.
 """
 absent = []
 present = []
 canary = None
-for spec in dep_specs:
-matcher = distlib.version.LegacyMatcher(spec)
-ver = _get_version(matcher.name)
+for name, info in group.items():
+constraint = _make_version_constraint(info, False)
+matcher = distlib.version.LegacyMatcher(name + constraint)
+ver = _get_version(name)
 if (
 ver is None
 # Always pass installed package to pip, so that they can be
 # updated if the requested version changes
-or not _is_system_package(matcher.name)
+or not _is_system_package(name)
 or not matcher.match(distlib.version.LegacyVersion(ver))
 ):
-absent.append(spec)
-if spec == dep_specs[0]:
-canary = prog
+absent.append(name + _make_version_constraint(info, True))
+if len(absent) == 1:
+canary = info.get("canary", None)
 else:
-logger.info("found %s %s", matcher.name, ver)
-present.append(matcher.name)
+logger.info("found %s %s", name, ver)
+present.append(name)
 
 if present:
 generate_console_scripts(present)
@@ -875,7 +903,24 @@ def ensure(
 if not HAVE_DISTLIB:
 raise Ouch("a usable distlib could not be found, please install it")
 
-result = _do_ensure(dep_specs, online, wheels_dir, prog)
+# Convert the depspecs to a dictionary, as if they came
+# from a section in a pythondeps.toml file
+group: Dict[str, Dict[str, str]] = {}
+for spec in dep_specs:
+name = distlib.version.LegacyMatcher(spec).name
+group[name] = {}
+
+spec = spec.strip()
+pos = len(name)
+ver =

[PULL 05/14] python: mkvenv: add ensuregroup command

[Paolo Bonzini]

Introduce a new subcommand that retrieves the packages to be installed
from a TOML file. This allows being more flexible in using the system
version of a package, while at the same time using a known-good version
when installing the package.  This is important for packages that
sometimes have backwards-incompatible changes or that depend on
specific versions of their dependencies.

Compared to JSON, TOML is more human readable and easier to edit.  A
parser is available in 3.11 but also available as a small (12k) package
for older versions, tomli.  While tomli is bundled with pip, this is only
true of recent versions of pip.  Of all the supported OSes pretty much
only FreeBSD has a recent enough version of pip while staying on Python
<3.11.  So we cannot use the same trick that is in place for distlib.

Signed-off-by: Paolo Bonzini 
---
 python/scripts/mkvenv.py | 126 ++-
 python/setup.cfg |   6 ++
 pythondeps.toml  |  17 ++
 3 files changed, 148 insertions(+), 1 deletion(-)
 create mode 100644 pythondeps.toml

diff --git a/python/scripts/mkvenv.py b/python/scripts/mkvenv.py
index 96f506d7e22..02bcd9a8c92 100644
--- a/python/scripts/mkvenv.py
+++ b/python/scripts/mkvenv.py
@@ -14,6 +14,8 @@
 post_init
   post-venv initialization
 ensureEnsure that the specified package is installed.
+ensuregroup
+  Ensure that the specified package group is installed.
 
 --
 
@@ -44,6 +46,19 @@
   --onlineInstall packages from PyPI, if necessary.
   --dir DIR   Path to vendored packages where we may install from.
 
+--
+
+usage: mkvenv ensuregroup [-h] [--online] [--dir DIR] file group...
+
+positional arguments:
+  filepointer to a TOML file
+  group   section name in the TOML file
+
+options:
+  -h, --help  show this help message and exit
+  --onlineInstall packages from PyPI, if necessary.
+  --dir DIR   Path to vendored packages where we may install from.
+
 """
 
 # The duplication between importlib and pkg_resources does not help
@@ -99,6 +114,18 @@
 except ImportError:
 HAVE_DISTLIB = False
 
+# Try to load tomllib, with a fallback to tomli.
+# HAVE_TOMLLIB is checked below, just-in-time, so that mkvenv does not fail
+# outside the venv or before a potential call to ensurepip in checkpip().
+HAVE_TOMLLIB = True
+try:
+import tomllib
+except ImportError:
+try:
+import tomli as tomllib
+except ImportError:
+HAVE_TOMLLIB = False
+
 # Do not add any mandatory dependencies from outside the stdlib:
 # This script *must* be usable standalone!
 
@@ -837,6 +864,7 @@ def _do_ensure(
 for name, info in group.items():
 constraint = _make_version_constraint(info, False)
 matcher = distlib.version.LegacyMatcher(name + constraint)
+print(f"mkvenv: checking for {matcher}", file=sys.stderr)
 ver = _get_version(name)
 if (
 ver is None
@@ -898,7 +926,6 @@ def ensure(
 be presented to the user. e.g., 'sphinx-build' can be used as a
 bellwether for the presence of 'sphinx'.
 """
-print(f"mkvenv: checking for {', '.join(dep_specs)}", file=sys.stderr)
 
 if not HAVE_DISTLIB:
 raise Ouch("a usable distlib could not be found, please install it")
@@ -928,6 +955,64 @@ def ensure(
 raise SystemExit(f"\n{result[0]}\n\n")
 
 
+def _parse_groups(file: str) -> Dict[str, Dict[str, Any]]:
+if not HAVE_TOMLLIB:
+if sys.version_info < (3, 11):
+raise Ouch("found no usable tomli, please install it")
+
+raise Ouch(
+"Python >=3.11 does not have tomllib... what have you done!?"
+)
+
+try:
+# Use loads() to support both tomli v1.2.x (Ubuntu 22.04,
+# Debian bullseye-backports) and v2.0.x
+with open(file, "r", encoding="ascii") as depfile:
+contents = depfile.read()
+return tomllib.loads(contents)  # type: ignore
+except tomllib.TOMLDecodeError as exc:
+raise Ouch(f"parsing {file} failed: {exc}") from exc
+
+
+def ensure_group(
+file: str,
+groups: Sequence[str],
+online: bool = False,
+wheels_dir: Optional[Union[str, Path]] = None,
+) -> None:
+"""
+Use pip to ensure we have the package specified by @dep_specs.
+
+If the package is already installed, do nothing. If online and
+wheels_dir are both provided, prefer packages found in wheels_dir
+first before connecting to PyPI.
+
+:param dep_specs:
+PEP 508 dependency specifications. e.g. ['meson>=0.61.5'].
+:param online: If True, fall back to PyPI.
+:param wheels_dir: If specified, search this path for packages.
+"""
+
+if not HAVE_DISTLIB:
+raise Ouch("found no usable distlib, please install it")
+
+parsed_deps = _parse_groups(file)
+
+to_install: Dict[str, Dict[str, 

[PULL 14/14] configure: remove unnecessary mkdir -p

[Paolo Bonzini]

It is already included in the symlink shell function.

Signed-off-by: Paolo Bonzini 
---
 configure | 1 -
 1 file changed, 1 deletion(-)

diff --git a/configure b/configure
index 08bf24b689c..b9bd008592a 100755
--- a/configure
+++ b/configure
@@ -1775,7 +1775,6 @@ fi
 for target in $target_list; do
 target_dir="$target"
 target_name=$(echo $target | cut -d '-' -f 1)$EXESUF
-mkdir -p "$target_dir"
 case $target in
 *-user) symlink "../qemu-$target_name" "$target_dir/qemu-$target_name" 
;;
 *) symlink "../qemu-system-$target_name" 
"$target_dir/qemu-system-$target_name" ;;
-- 
2.41.0

[PULL 00/14] Python, i386 changes for 2023-08-28

[Paolo Bonzini]

The following changes since commit 50e7a40af372ee5931c99ef7390f5d3d6fbf6ec4:

  Merge tag 'pull-target-arm-20230824' of 
https://git.linaro.org/people/pmaydell/qemu-arm into staging (2023-08-24 
10:08:33 -0400)

are available in the Git repository at:

  https://gitlab.com/bonzini/qemu.git tags/for-upstream

for you to fetch changes up to 29a8238510df27080b0ffa92c58400412ce19daa:

  configure: remove unnecessary mkdir -p (2023-08-28 10:01:44 +0200)


* separate accepted and auto-installed versions of Python dependencies
* bump tricore container to Debian 11
* small configure cleanups


Ake Koomsin (1):
  target/i386: add support for VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE

Paolo Bonzini (13):
  configure: fix and complete detection of tricore tools
  dockerfiles: bump tricore cross compiler container to Debian 11
  python: mkvenv: tweak the matching of --diagnose to depspecs
  python: mkvenv: introduce TOML-like representation of dependencies
  python: mkvenv: add ensuregroup command
  lcitool: bump libvirt-ci submodule and regenerate
  configure: never use PyPI for Meson
  python: use vendored tomli
  configure: switch to ensuregroup
  Revert "tests: Use separate virtual environment for avocado"
  tests/docker: add python3-tomli dependency to containers
  configure: fix container_hosts misspellings and duplications
  configure: remove unnecessary mkdir -p

 .gitlab-ci.d/buildtest.yml |   6 +-
 .gitlab-ci.d/cirrus/freebsd-13.vars|   2 +-
 .gitlab-ci.d/cirrus/macos-12.vars  |   2 +-
 configure  |  31 +---
 docs/devel/acpi-bits.rst   |   6 +-
 docs/devel/testing.rst |  14 +-
 python/scripts/mkvenv.py   | 201 +++--
 python/scripts/vendor.py   |   5 +-
 python/setup.cfg   |   6 +
 python/wheels/tomli-2.0.1-py3-none-any.whl | Bin 0 -> 12757 bytes
 pythondeps.toml|  32 
 scripts/ci/org.centos/stream/8/x86_64/test-avocado |   4 +-
 scripts/device-crash-test  |   2 +-
 target/i386/cpu.c  |   6 +-
 target/i386/cpu.h  |   1 +
 tests/Makefile.include |  19 +-
 tests/docker/dockerfiles/centos8.docker|   3 +-
 .../dockerfiles/debian-all-test-cross.docker   |   7 +-
 tests/docker/dockerfiles/debian-amd64-cross.docker |   6 +-
 tests/docker/dockerfiles/debian-amd64.docker   |   4 +
 tests/docker/dockerfiles/debian-arm64-cross.docker |   6 +-
 tests/docker/dockerfiles/debian-armel-cross.docker |   6 +-
 tests/docker/dockerfiles/debian-armhf-cross.docker |   6 +-
 .../docker/dockerfiles/debian-hexagon-cross.docker |   6 +-
 .../dockerfiles/debian-mips64el-cross.docker   |   6 +-
 .../docker/dockerfiles/debian-mipsel-cross.docker  |   6 +-
 .../docker/dockerfiles/debian-ppc64el-cross.docker |   6 +-
 .../docker/dockerfiles/debian-riscv64-cross.docker |   2 +-
 tests/docker/dockerfiles/debian-s390x-cross.docker |   6 +-
 .../docker/dockerfiles/debian-tricore-cross.docker |   4 +-
 tests/docker/dockerfiles/fedora-i386-cross.docker  |   1 +
 tests/docker/dockerfiles/fedora-win32-cross.docker |   2 +-
 tests/docker/dockerfiles/fedora-win64-cross.docker |   2 +-
 tests/docker/dockerfiles/opensuse-leap.docker  |  22 +--
 tests/docker/dockerfiles/ubuntu2004.docker |   4 +-
 tests/docker/dockerfiles/ubuntu2204.docker |   1 +
 tests/lcitool/libvirt-ci   |   2 +-
 tests/lcitool/mappings.yml |  28 ++-
 tests/lcitool/projects/qemu.yml|   3 +-
 tests/lcitool/targets/opensuse-leap-15.yml |   4 +-
 tests/requirements.txt |   6 -
 tests/vm/Makefile.include  |   2 +-
 tests/vm/generated/freebsd.json|   1 +
 43 files changed, 377 insertions(+), 112 deletions(-)
 create mode 100644 python/wheels/tomli-2.0.1-py3-none-any.whl
 create mode 100644 pythondeps.toml
 delete mode 100644 tests/requirements.txt
-- 
2.41.0

[PULL 02/14] dockerfiles: bump tricore cross compiler container to Debian 11

[Paolo Bonzini]

With the release of version 12 on June 10, 2023, Debian 10 is
not supported anymore.  Modify the cross compiler container to
build on a newer version.

Signed-off-by: Paolo Bonzini 
---
 tests/docker/dockerfiles/debian-tricore-cross.docker | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/docker/dockerfiles/debian-tricore-cross.docker 
b/tests/docker/dockerfiles/debian-tricore-cross.docker
index 269bfa8d423..5bd1963fb55 100644
--- a/tests/docker/dockerfiles/debian-tricore-cross.docker
+++ b/tests/docker/dockerfiles/debian-tricore-cross.docker
@@ -9,7 +9,7 @@
 #
 # SPDX-License-Identifier: GPL-2.0-or-later
 #
-FROM docker.io/library/debian:buster-slim
+FROM docker.io/library/debian:11-slim
 
 MAINTAINER Philippe Mathieu-Daudé 
 
-- 
2.41.0

[PULL 12/14] target/i386: add support for VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE

[Paolo Bonzini]

From: Ake Koomsin 

Current QEMU can expose waitpkg to guests when it is available. However,
VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE is still not recognized and
masked by QEMU. This can lead to an unexpected situation when a L1
hypervisor wants to expose waitpkg to a L2 guest. The L1 hypervisor can
assume that VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE exists as waitpkg is
available. The L1 hypervisor then can accidentally expose waitpkg to the
L2 guest. This will cause invalid opcode exception in the L2 guest when
it executes waitpkg related instructions.

This patch adds VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE support, and
sets up dependency between the bit and CPUID_7_0_ECX_WAITPKG. QEMU should
not expose waitpkg feature if VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE is
not available to avoid unexpected invalid opcode exception in L2 guests.

Signed-off-by: Ake Koomsin 
Message-ID: <20230807093339.32091-2-...@igel.co.jp>
Signed-off-by: Paolo Bonzini 
---
 target/i386/cpu.c | 6 +-
 target/i386/cpu.h | 1 +
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 97ad229d8ba..00f913b6382 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1228,7 +1228,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", 
"vmx-encls-exit",
 "vmx-rdseed-exit", "vmx-pml", NULL, NULL,
 "vmx-xsaves", NULL, NULL, NULL,
-NULL, "vmx-tsc-scaling", NULL, NULL,
+NULL, "vmx-tsc-scaling", "vmx-enable-user-wait-pause", NULL,
 NULL, NULL, NULL, NULL,
 },
 .msr = {
@@ -1545,6 +1545,10 @@ static FeatureDep feature_dependencies[] = {
 .from = { FEAT_8000_0001_ECX,   CPUID_EXT3_SVM },
 .to = { FEAT_SVM,   ~0ull },
 },
+{
+.from = { FEAT_VMX_SECONDARY_CTLS,  
VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE },
+.to = { FEAT_7_0_ECX,   CPUID_7_0_ECX_WAITPKG },
+},
 };
 
 typedef struct X86RegisterInfo32 {
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index e0771a10433..a6000e93bd8 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -,6 +,7 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
 #define VMX_SECONDARY_EXEC_ENABLE_PML   0x0002
 #define VMX_SECONDARY_EXEC_XSAVES   0x0010
 #define VMX_SECONDARY_EXEC_TSC_SCALING  0x0200
+#define VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE   0x0400
 
 #define VMX_PIN_BASED_EXT_INTR_MASK 0x0001
 #define VMX_PIN_BASED_NMI_EXITING   0x0008
-- 
2.41.0

[PULL 01/14] configure: fix and complete detection of tricore tools

[Paolo Bonzini]

The tricore tools are not detected when they are installed in
the host system, only if they are taken from an external
container.  For this reason the build-tricore-softmmu job
was not running the TCG tests.

In addition the container provides all tools, not just as/ld/gcc,
so there is no need to special case tricore.

Signed-off-by: Paolo Bonzini 
---
 configure | 5 +
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/configure b/configure
index 133f4e32351..f2bd8858d6c 100755
--- a/configure
+++ b/configure
@@ -1271,6 +1271,7 @@ fi
 : ${cross_prefix_sh4="sh4-linux-gnu-"}
 : ${cross_prefix_sparc64="sparc64-linux-gnu-"}
 : ${cross_prefix_sparc="$cross_prefix_sparc64"}
+: ${cross_prefix_tricore="tricore-"}
 : ${cross_prefix_x86_64="x86_64-linux-gnu-"}
 
 : ${cross_cc_aarch64_be="$cross_cc_aarch64"}
@@ -1458,10 +1459,6 @@ probe_target_compiler() {
   tricore)
 container_image=debian-tricore-cross
 container_cross_prefix=tricore-
-container_cross_as=tricore-as
-container_cross_ld=tricore-ld
-container_cross_cc=tricore-gcc
-break
 ;;
   x86_64)
 container_image=debian-amd64-cross
-- 
2.41.0

[PULL 06/14] lcitool: bump libvirt-ci submodule and regenerate

[Paolo Bonzini]

This brings in a newer version of the pipewire mapping, so rename it.

Python 3.9 and 3.10 do not seem to work in OpenSUSE LEAP 15.5 (weird,
because 3.9 persisted from 15.3 to 15.4) so bump the Python runtime
version to 3.11.

Signed-off-by: Paolo Bonzini 
---
 .../dockerfiles/debian-amd64-cross.docker |  2 +-
 .../dockerfiles/debian-arm64-cross.docker |  2 +-
 .../dockerfiles/debian-armel-cross.docker |  2 +-
 .../dockerfiles/debian-armhf-cross.docker |  2 +-
 .../dockerfiles/debian-mips64el-cross.docker  |  2 +-
 .../dockerfiles/debian-mipsel-cross.docker|  2 +-
 .../dockerfiles/debian-ppc64el-cross.docker   |  2 +-
 .../dockerfiles/debian-riscv64-cross.docker   |  2 +-
 .../dockerfiles/debian-s390x-cross.docker |  2 +-
 .../dockerfiles/fedora-win32-cross.docker |  2 +-
 .../dockerfiles/fedora-win64-cross.docker |  2 +-
 tests/docker/dockerfiles/opensuse-leap.docker | 22 +--
 tests/lcitool/libvirt-ci  |  2 +-
 tests/lcitool/mappings.yml| 12 +-
 tests/lcitool/projects/qemu.yml   |  2 +-
 tests/lcitool/targets/opensuse-leap-15.yml|  4 ++--
 16 files changed, 32 insertions(+), 32 deletions(-)

diff --git a/tests/docker/dockerfiles/debian-amd64-cross.docker 
b/tests/docker/dockerfiles/debian-amd64-cross.docker
index b7bdc012431..b9871f9c8c7 100644
--- a/tests/docker/dockerfiles/debian-amd64-cross.docker
+++ b/tests/docker/dockerfiles/debian-amd64-cross.docker
@@ -1,6 +1,6 @@
 # THIS FILE WAS AUTO-GENERATED
 #
-#  $ lcitool dockerfile --layers all --cross x86_64 debian-11 qemu
+#  $ lcitool dockerfile --layers all --cross-arch x86_64 debian-11 qemu
 #
 # https://gitlab.com/libvirt/libvirt-ci
 
diff --git a/tests/docker/dockerfiles/debian-arm64-cross.docker 
b/tests/docker/dockerfiles/debian-arm64-cross.docker
index 68165c2f23e..3504c771a76 100644
--- a/tests/docker/dockerfiles/debian-arm64-cross.docker
+++ b/tests/docker/dockerfiles/debian-arm64-cross.docker
@@ -1,6 +1,6 @@
 # THIS FILE WAS AUTO-GENERATED
 #
-#  $ lcitool dockerfile --layers all --cross aarch64 debian-11 qemu
+#  $ lcitool dockerfile --layers all --cross-arch aarch64 debian-11 qemu
 #
 # https://gitlab.com/libvirt/libvirt-ci
 
diff --git a/tests/docker/dockerfiles/debian-armel-cross.docker 
b/tests/docker/dockerfiles/debian-armel-cross.docker
index 2fb65308c7a..6d11c9510fd 100644
--- a/tests/docker/dockerfiles/debian-armel-cross.docker
+++ b/tests/docker/dockerfiles/debian-armel-cross.docker
@@ -1,6 +1,6 @@
 # THIS FILE WAS AUTO-GENERATED
 #
-#  $ lcitool dockerfile --layers all --cross armv6l debian-11 qemu
+#  $ lcitool dockerfile --layers all --cross-arch armv6l debian-11 qemu
 #
 # https://gitlab.com/libvirt/libvirt-ci
 
diff --git a/tests/docker/dockerfiles/debian-armhf-cross.docker 
b/tests/docker/dockerfiles/debian-armhf-cross.docker
index df77ccb57bd..37ae575cf7e 100644
--- a/tests/docker/dockerfiles/debian-armhf-cross.docker
+++ b/tests/docker/dockerfiles/debian-armhf-cross.docker
@@ -1,6 +1,6 @@
 # THIS FILE WAS AUTO-GENERATED
 #
-#  $ lcitool dockerfile --layers all --cross armv7l debian-11 qemu
+#  $ lcitool dockerfile --layers all --cross-arch armv7l debian-11 qemu
 #
 # https://gitlab.com/libvirt/libvirt-ci
 
diff --git a/tests/docker/dockerfiles/debian-mips64el-cross.docker 
b/tests/docker/dockerfiles/debian-mips64el-cross.docker
index 63a3d7aa3b9..26ed730165a 100644
--- a/tests/docker/dockerfiles/debian-mips64el-cross.docker
+++ b/tests/docker/dockerfiles/debian-mips64el-cross.docker
@@ -1,6 +1,6 @@
 # THIS FILE WAS AUTO-GENERATED
 #
-#  $ lcitool dockerfile --layers all --cross mips64el debian-11 qemu
+#  $ lcitool dockerfile --layers all --cross-arch mips64el debian-11 qemu
 #
 # https://gitlab.com/libvirt/libvirt-ci
 
diff --git a/tests/docker/dockerfiles/debian-mipsel-cross.docker 
b/tests/docker/dockerfiles/debian-mipsel-cross.docker
index ac87bbb0956..ade2f37ed1d 100644
--- a/tests/docker/dockerfiles/debian-mipsel-cross.docker
+++ b/tests/docker/dockerfiles/debian-mipsel-cross.docker
@@ -1,6 +1,6 @@
 # THIS FILE WAS AUTO-GENERATED
 #
-#  $ lcitool dockerfile --layers all --cross mipsel debian-11 qemu
+#  $ lcitool dockerfile --layers all --cross-arch mipsel debian-11 qemu
 #
 # https://gitlab.com/libvirt/libvirt-ci
 
diff --git a/tests/docker/dockerfiles/debian-ppc64el-cross.docker 
b/tests/docker/dockerfiles/debian-ppc64el-cross.docker
index def11f16933..08dcffa0a85 100644
--- a/tests/docker/dockerfiles/debian-ppc64el-cross.docker
+++ b/tests/docker/dockerfiles/debian-ppc64el-cross.docker
@@ -1,6 +1,6 @@
 # THIS FILE WAS AUTO-GENERATED
 #
-#  $ lcitool dockerfile --layers all --cross ppc64le debian-11 qemu
+#  $ lcitool dockerfile --layers all --cross-arch ppc64le debian-11 qemu
 #
 # https://gitlab.com/libvirt/libvirt-ci
 
diff --git a/tests/docker/dockerfiles/debian-riscv64-cross.docker 
b/tests/docker/dockerfiles/debian-riscv64-cross.docker
index a2d879ee1fd..a26637ec4fb 100644
--- a/tests/docker/dockerfile

[PULL 10/14] Revert "tests: Use separate virtual environment for avocado"

[Paolo Bonzini]

This reverts commit e8e4298feadae7924cf7600bb3bcc5b0a8d7cbe9.

ensuregroup allows to specify both the acceptable versions of avocado,
and a locked version to be used when avocado is not installed as a system
pacakge.  This lets us install avocado in pyvenv/ using "mkvenv.py" and
reuse the distro package on Fedora and CentOS Stream (the only distros
where it's available).

ensuregroup's usage of "(>=..., <=...)" constraints when evaluating
the distro package, and "==" constraints when installing it from PyPI,
makes it possible to avoid conflicts between the known-good version and
a package plugins included in the distro.

This is because package plugins have "==" constraints on the version
that is included in the distro, and, using "pip install avocado==88.1"
on a venv that includes system packages will result in an error:

   avocado-framework-plugin-varianter-yaml-to-mux 98.0 requires 
avocado-framework==98.0, but you have avocado-framework 88.1 which is 
incompatible.
   avocado-framework-plugin-result-html 98.0 requires avocado-framework==98.0, 
but you have avocado-framework 88.1 which is incompatible.

But at the same time, if the venv does not include a system distribution
of avocado then we can install a known-good version and stick to LTS
releases.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1663
Signed-off-by: Paolo Bonzini 
---
 .gitlab-ci.d/buildtest.yml|  6 +++---
 docs/devel/acpi-bits.rst  |  6 +++---
 docs/devel/testing.rst| 14 +++---
 python/scripts/mkvenv.py  | 13 +
 pythondeps.toml   |  7 +++
 .../org.centos/stream/8/x86_64/test-avocado   |  4 ++--
 scripts/device-crash-test |  2 +-
 tests/Makefile.include| 19 ---
 tests/requirements.txt|  6 --
 tests/vm/Makefile.include |  2 +-
 10 files changed, 37 insertions(+), 42 deletions(-)
 delete mode 100644 tests/requirements.txt

diff --git a/.gitlab-ci.d/buildtest.yml b/.gitlab-ci.d/buildtest.yml
index 77dc83a6be0..aee91015077 100644
--- a/.gitlab-ci.d/buildtest.yml
+++ b/.gitlab-ci.d/buildtest.yml
@@ -103,7 +103,7 @@ crash-test-debian:
   script:
 - cd build
 - make NINJA=":" check-venv
-- tests/venv/bin/python3 scripts/device-crash-test -q --tcg-only 
./qemu-system-i386
+- pyvenv/bin/python3 scripts/device-crash-test -q --tcg-only 
./qemu-system-i386
 
 build-system-fedora:
   extends:
@@ -146,8 +146,8 @@ crash-test-fedora:
   script:
 - cd build
 - make NINJA=":" check-venv
-- tests/venv/bin/python3 scripts/device-crash-test -q ./qemu-system-ppc
-- tests/venv/bin/python3 scripts/device-crash-test -q ./qemu-system-riscv32
+- pyvenv/bin/python3 scripts/device-crash-test -q ./qemu-system-ppc
+- pyvenv/bin/python3 scripts/device-crash-test -q ./qemu-system-riscv32
 
 build-system-centos:
   extends:
diff --git a/docs/devel/acpi-bits.rst b/docs/devel/acpi-bits.rst
index 22e2580200c..9677b0098f4 100644
--- a/docs/devel/acpi-bits.rst
+++ b/docs/devel/acpi-bits.rst
@@ -61,19 +61,19 @@ Under ``tests/avocado/`` as the root we have:
::
 
  $ make check-venv (needed only the first time to create the venv)
- $ ./tests/venv/bin/avocado run -t acpi tests/avocado
+ $ ./pyvenv/bin/avocado run -t acpi tests/avocado
 
The above will run all acpi avocado tests including this one.
In order to run the individual tests, perform the following:
::
 
- $ ./tests/venv/bin/avocado run tests/avocado/acpi-bits.py --tap -
+ $ ./pyvenv/bin/avocado run tests/avocado/acpi-bits.py --tap -
 
The above will produce output in tap format. You can omit "--tap -" in the
end and it will produce output like the following:
::
 
-  $ ./tests/venv/bin/avocado run tests/avocado/acpi-bits.py
+  $ ./pyvenv/bin/avocado run tests/avocado/acpi-bits.py
   Fetching asset from 
tests/avocado/acpi-bits.py:AcpiBitsTest.test_acpi_smbios_bits
   JOB ID : eab225724da7b64c012c65705dc2fa14ab1defef
   JOB LOG: 
/home/anisinha/avocado/job-results/job-2022-10-10T17.58-eab2257/job.log
diff --git a/docs/devel/testing.rst b/docs/devel/testing.rst
index b6ad21bed1c..5d1fc0aa95f 100644
--- a/docs/devel/testing.rst
+++ b/docs/devel/testing.rst
@@ -894,9 +894,9 @@ You can run the avocado tests simply by executing:
 
   make check-avocado
 
-This involves the automatic creation of Python virtual environment
-within the build tree (at ``tests/venv``) which will have all the
-right dependencies, and will save tests results also within the
+This involves the automatic installation, from PyPI, of all the
+necessary avocado-framework dependencies into the QEMU venv within the
+build tree (at ``./pyvenv``). Test results are also saved within the
 build tree (at ``tests/results``).
 
 Note: the build environment must be using a Python 3 stack, and have
@

[PULL 09/14] configure: switch to ensuregroup

[Paolo Bonzini]

Using the new ensuregroup command, the desired versions of meson and
sphinx can be placed in pythondeps.toml rather than configure.

The meson.install entry in pythondeps.toml matches the version that is
found in python/wheels.  This ensures that mkvenv.py uses the bundled
wheel even if PyPI is enabled; thus not introducing warnings or errors
from versions that are more recent than the one used in CI.

The sphinx entries match what is shipped in Fedora 38.  It's the
last release that has support for older versions of Python (sphinx 6.0
requires Python 3.8) and especially docutils (of which sphinx 6.0 requires
version 0.18).  This is important because Ubuntu 20.04 has docutils 0.14
and Debian 11 has docutils 0.16.

"mkvenv.py ensure" is only used to bootstrap tomli.

Signed-off-by: Paolo Bonzini 
---
 configure   | 14 --
 pythondeps.toml |  8 
 2 files changed, 12 insertions(+), 10 deletions(-)

diff --git a/configure b/configure
index 347153702c1..e4d42d640e4 100755
--- a/configure
+++ b/configure
@@ -1024,13 +1024,8 @@ if $python -c 'import sys; sys.exit(sys.version_info >= 
(3,11))'; then
 $mkvenv ensure --dir "${source_path}/python/wheels" \
 'tomli>=1.2.0' || exit 1
 fi
-if ! $mkvenv ensure \
- --dir "${source_path}/python/wheels" \
- --diagnose "meson" \
- "meson>=0.63.0" ;
-then
-exit 1
-fi
+$mkvenv ensuregroup --dir "${source_path}/python/wheels" \
+ ${source_path}/pythondeps.toml meson || exit 1
 
 # At this point, we expect Meson to be installed and available.
 # We expect mkvenv or pip to have created pyvenv/bin/meson for us.
@@ -1047,10 +1042,9 @@ if test "$download" = "enabled" -a "$docs" = "enabled" ; 
then
 fi
 
 if test "$docs" != "disabled" ; then
-if ! $mkvenv ensure \
+if ! $mkvenv ensuregroup \
  $mkvenv_flags \
- --diagnose "sphinx-build" \
- "sphinx>=1.6.0" "sphinx-rtd-theme>=0.5.0";
+ ${source_path}/pythondeps.toml docs;
 then
 if test "$docs" = "enabled" ; then
 exit 1
diff --git a/pythondeps.toml b/pythondeps.toml
index 362f63ff2c9..6be31dba301 100644
--- a/pythondeps.toml
+++ b/pythondeps.toml
@@ -15,3 +15,11 @@
 #   precise error diagnostics to the user.  For example,
 #   'sphinx-build' can be used as a bellwether for the
 #   presence of 'sphinx' in the system.
+
+[meson]
+# The install key should match the version in python/wheels/
+meson = { accepted = ">=0.63.0", installed = "0.63.3", canary = "meson" }
+
+[docs]
+sphinx = { accepted = ">=1.6", installed = "5.3.0", canary = "sphinx-build" }
+sphinx_rtd_theme = { accepted = ">=0.5", installed = "1.1.1" }
-- 
2.41.0

[PULL 07/14] configure: never use PyPI for Meson

[Paolo Bonzini]

Since there is a vendored copy, there is no point in choosing online
operation.

Signed-off-by: Paolo Bonzini 
---
 configure | 6 --
 1 file changed, 6 deletions(-)

diff --git a/configure b/configure
index f2bd8858d6c..f13f0662b98 100755
--- a/configure
+++ b/configure
@@ -1018,13 +1018,7 @@ fi
 python="$python -B"
 mkvenv="$python ${source_path}/python/scripts/mkvenv.py"
 
-mkvenv_flags=""
-if test "$download" = "enabled" ; then
-mkvenv_flags="--online"
-fi
-
 if ! $mkvenv ensure \
- $mkvenv_flags \
  --dir "${source_path}/python/wheels" \
  --diagnose "meson" \
  "meson>=0.63.0" ;
-- 
2.41.0

[PULL 08/14] python: use vendored tomli

[Paolo Bonzini]

Debian only introduced tomli in the bookworm release.  Use a
vendored wheel to avoid requiring a package that is only in
bullseye-backports and is also absent in Ubuntu 20.04.

While at it, fix an issue in the vendor.py scripts which does
not add a newline after each package and hash.

Signed-off-by: Paolo Bonzini 
---
 configure  |   6 ++
 python/scripts/vendor.py   |   5 -
 python/wheels/tomli-2.0.1-py3-none-any.whl | Bin 0 -> 12757 bytes
 3 files changed, 10 insertions(+), 1 deletion(-)
 create mode 100644 python/wheels/tomli-2.0.1-py3-none-any.whl

diff --git a/configure b/configure
index f13f0662b98..347153702c1 100755
--- a/configure
+++ b/configure
@@ -1018,6 +1018,12 @@ fi
 python="$python -B"
 mkvenv="$python ${source_path}/python/scripts/mkvenv.py"
 
+# Finish preparing the virtual environment using vendored .whl files
+
+if $python -c 'import sys; sys.exit(sys.version_info >= (3,11))'; then
+$mkvenv ensure --dir "${source_path}/python/wheels" \
+'tomli>=1.2.0' || exit 1
+fi
 if ! $mkvenv ensure \
  --dir "${source_path}/python/wheels" \
  --diagnose "meson" \
diff --git a/python/scripts/vendor.py b/python/scripts/vendor.py
index 34486a51f44..76274871170 100755
--- a/python/scripts/vendor.py
+++ b/python/scripts/vendor.py
@@ -43,13 +43,16 @@ def main() -> int:
 packages = {
 "meson==0.63.3":
 "d677b809c4895dcbaac9bf6c43703fcb3609a4b24c6057c78f828590049cf43a",
+
+"tomli==2.0.1":
+"939de3e7a6161af0c887ef91b7d41a53e7c5a1ca976325f429cb46ea9bc30ecc",
 }
 
 vendor_dir = Path(__file__, "..", "..", "wheels").resolve()
 
 with tempfile.NamedTemporaryFile(mode="w", encoding="utf-8") as file:
 for dep_spec, checksum in packages.items():
-file.write(f"{dep_spec} --hash=sha256:{checksum}")
+print(f"{dep_spec} --hash=sha256:{checksum}", file=file)
 file.flush()
 
 cli_args = [
diff --git a/python/wheels/tomli-2.0.1-py3-none-any.whl 
b/python/wheels/tomli-2.0.1-py3-none-any.whl
new file mode 100644
index 
..29670b98d16e2bc770d4fea718582e1dc0dd8aca
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Re: [PATCH v2 2/4] qcow2: add configurations for zoned format extension

[Sam Li]

Damien Le Moal  于2023年8月28日周一 18:22写道：
>
> On 8/28/23 19:18, Sam Li wrote:
> > Damien Le Moal  于2023年8月28日周一 18:13写道：
> >>
> >> On 8/28/23 18:22, Sam Li wrote:
> >>> Stefan Hajnoczi  于2023年8月21日周一 21:31写道：
> 
>  On Mon, Aug 14, 2023 at 04:58:00PM +0800, Sam Li wrote:
> > diff --git a/block/qcow2.h b/block/qcow2.h
> > index f789ce3ae0..3694c8d217 100644
> > --- a/block/qcow2.h
> > +++ b/block/qcow2.h
> > @@ -236,6 +236,20 @@ typedef struct Qcow2CryptoHeaderExtension {
> >  uint64_t length;
> >  } QEMU_PACKED Qcow2CryptoHeaderExtension;
> >
> > +typedef struct Qcow2ZonedHeaderExtension {
> > +/* Zoned device attributes */
> > +uint8_t zoned_profile;
> > +uint8_t zoned;
> > +uint16_t reserved16;
> > +uint32_t zone_size;
> > +uint32_t zone_capacity;
> 
>  Should zone capacity be stored individually for each zone (alongside the
>  write pointer and other per zone metadata) instead of as a global value
>  for all zones? My understanding is that NVMe ZNS does not have a global
>  value and each zone could have a different zone capacity value.
> >>>
> >>> Though zone capacity is per-zone attribute, it remains same for all
> >>> zones in most cases. Referring to the NVMe ZNS spec, zone capacity
> >>> changes associate to RESET_ZONE op when the variable zone capacity bit
> >>> is '1'. It hasn't specifically tell what it is changed to. Current ZNS
> >>> emulation doesn't change zone capacity as well.
> >>>
> >>> If the Variable Zone Capacity bit is cleared to ‘0’ in the Zone
> >>> Operation Characteristics field in the Zoned
> >>> Namespace Command Set specific Identify Namespace data structure, then
> >>> this field does not change without a change to the format of the zoned
> >>> namespace.
> >>>
> >>> If the Variable Zone Capacity bit is set to ‘1’ in the Zone Operation
> >>> Characteristics field in the Zoned
> >>> Namespace Command Set specific Identify Namespace data structure, then
> >>> the zone capacity may
> >>> change upon successful completion of a Zone Management Send command
> >>> specifying the Zone Send
> >>> Action of Reset Zone.
> >>
> >> Regardless of the variable zone capacity feature, zone capacity is per 
> >> zone and
> >> may be different between zones. That is why it is reported per zone in zone
> >> report. The IO path code should not assume that the zone capacity is the 
> >> same
> >> for all zones.
> >
> > How is zone capacity changed, by devices or commands? Can you give
> > some example please?
>
> If the device does not support variable zone capacity, the zone capacity is
> fixed at device manufacturing time and never changes. It is reported per zone
> and you have to make things work with whatever value you see. The user cannot
> change device zone capacity.
>
> For you qcow2 zoned image, the equivalent is to fix the zone capacity when the
> image is created and not allowing to change it. And for simplicity, the same
> zone capacity value can be used for all zones, so having the zone capacity
> value in the header is OK.

Thanks!

>
> >
> >>
> >> For this particular case though, given that this is QCow2 emulation, 
> >> limiting
> >> ourselves to the same zone capacity for all zones is I think fine. But that
> >> should be clearly stated somewhere may be...
> >
> > I see. The qcow2 documentaion can add that.
> >
> >>
> >>>
> 
> > +uint32_t nr_zones;
> 
>  Is this field necessary since it can be derived from other image
>  options: nr_zones = DIV_ROUND_UP(total_length, zone_capacity)?
> >>>
> >>> It can be dropped. I added this for reducing duplication. Thanks!
> >>
> >> --
> >> Damien Le Moal
> >> Western Digital Research
> >>
>
> --
> Damien Le Moal
> Western Digital Research
>

[PATCH v2 04/11] target/tricore: Implement FTOU insn

[Bastian Koppelmann]

Signed-off-by: Bastian Koppelmann 
---
v1 -> v2:
- Remove special case for NAN input
- Clarified, why we need arg < 0.0 special case

 target/tricore/fpu_helper.c   | 32 +++
 target/tricore/helper.h   |  1 +
 target/tricore/translate.c|  3 +++
 tests/tcg/tricore/Makefile.softmmu-target |  1 +
 tests/tcg/tricore/asm/test_ftou.S | 12 +
 5 files changed, 49 insertions(+)
 create mode 100644 tests/tcg/tricore/asm/test_ftou.S

diff --git a/target/tricore/fpu_helper.c b/target/tricore/fpu_helper.c
index cb7ee7dd35..3aefeb776e 100644
--- a/target/tricore/fpu_helper.c
+++ b/target/tricore/fpu_helper.c
@@ -429,6 +429,38 @@ uint32_t helper_ftoiz(CPUTriCoreState *env, uint32_t arg)
 return result;
 }
 
+uint32_t helper_ftou(CPUTriCoreState *env, uint32_t arg)
+{
+float32 f_arg = make_float32(arg);
+uint32_t result;
+int32_t flags = 0;
+
+result = float32_to_uint32(f_arg, &env->fp_status);
+
+flags = f_get_excp_flags(env);
+if (flags & float_flag_invalid) {
+flags &= ~float_flag_inexact;
+if (float32_is_any_nan(f_arg)) {
+result = 0;
+}
+/*
+ * we need to check arg < 0.0 before rounding as TriCore needs to raise
+ * float_flag_invalid as well. For instance, when we have a negative
+ * exponent and sign, softfloat would only raise float_flat_inexact.
+ */
+} else if (float32_lt_quiet(f_arg, 0, &env->fp_status)) {
+flags = float_flag_invalid;
+result = 0;
+}
+
+if (flags) {
+f_update_psw_flags(env, flags);
+} else {
+env->FPU_FS = 0;
+}
+return result;
+}
+
 uint32_t helper_ftouz(CPUTriCoreState *env, uint32_t arg)
 {
 float32 f_arg = make_float32(arg);
diff --git a/target/tricore/helper.h b/target/tricore/helper.h
index 190645413a..827fbaa692 100644
--- a/target/tricore/helper.h
+++ b/target/tricore/helper.h
@@ -114,6 +114,7 @@ DEF_HELPER_2(ftoi, i32, env, i32)
 DEF_HELPER_2(itof, i32, env, i32)
 DEF_HELPER_2(utof, i32, env, i32)
 DEF_HELPER_2(ftoiz, i32, env, i32)
+DEF_HELPER_2(ftou, i32, env, i32)
 DEF_HELPER_2(ftouz, i32, env, i32)
 DEF_HELPER_2(updfl, void, env, i32)
 /* dvinit */
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index c2ef84af08..165297376a 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -6273,6 +6273,9 @@ static void decode_rr_divide(DisasContext *ctx)
 case OPC2_32_RR_ITOF:
 gen_helper_itof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
 break;
+case OPC2_32_RR_FTOU:
+gen_helper_ftou(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
+break;
 case OPC2_32_RR_FTOUZ:
 gen_helper_ftouz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
 break;
diff --git a/tests/tcg/tricore/Makefile.softmmu-target 
b/tests/tcg/tricore/Makefile.softmmu-target
index 7a7d73a60c..e6ed5c56f2 100644
--- a/tests/tcg/tricore/Makefile.softmmu-target
+++ b/tests/tcg/tricore/Makefile.softmmu-target
@@ -15,6 +15,7 @@ TESTS += test_dvstep.asm.tst
 TESTS += test_fadd.asm.tst
 TESTS += test_fmul.asm.tst
 TESTS += test_ftoi.asm.tst
+TESTS += test_ftou.asm.tst
 TESTS += test_imask.asm.tst
 TESTS += test_insert.asm.tst
 TESTS += test_ld_bu.asm.tst
diff --git a/tests/tcg/tricore/asm/test_ftou.S 
b/tests/tcg/tricore/asm/test_ftou.S
new file mode 100644
index 00..10f106ad62
--- /dev/null
+++ b/tests/tcg/tricore/asm/test_ftou.S
@@ -0,0 +1,12 @@
+#include "macros.h"
+.text
+.global _start
+_start:
+TEST_D_D(ftou, 1, 0x, 0x1733f6c2)
+TEST_D_D(ftou, 2, 0x, 0x2c9d9cdc)
+TEST_D_D(ftou, 3, 0x, 0x56eb7395)
+TEST_D_D(ftou, 4, 0x79900800, 0x4ef32010)
+TEST_D_D(ftou, 5, 0x0353f510, 0x4c54fd44)
+
+TEST_PASSFAIL
+
-- 
2.41.0

[PATCH v2 02/11] target/tricore: Implement CRCN insn

[Bastian Koppelmann]

reported in https://gitlab.com/qemu-project/qemu/-/issues/1667

Signed-off-by: Bastian Koppelmann 
---
v1 -> v2:
- Removed useless deposits in crc_div()
- Replaced final deposit() with extract() in helper_crcn()
- Add trap for CRCN insn if not feature_162

 target/tricore/helper.h   |  1 +
 target/tricore/op_helper.c| 63 +++
 target/tricore/translate.c|  8 +++
 target/tricore/tricore-opcodes.h  |  1 +
 tests/tcg/tricore/Makefile.softmmu-target |  1 +
 tests/tcg/tricore/asm/test_crcn.S |  9 
 6 files changed, 83 insertions(+)
 create mode 100644 tests/tcg/tricore/asm/test_crcn.S

diff --git a/target/tricore/helper.h b/target/tricore/helper.h
index 31d71eac7a..190645413a 100644
--- a/target/tricore/helper.h
+++ b/target/tricore/helper.h
@@ -134,6 +134,7 @@ DEF_HELPER_FLAGS_5(mulr_h, TCG_CALL_NO_RWG_SE, i32, i32, 
i32, i32, i32, i32)
 DEF_HELPER_FLAGS_2(crc32b, TCG_CALL_NO_RWG_SE, i32, i32, i32)
 DEF_HELPER_FLAGS_2(crc32_be, TCG_CALL_NO_RWG_SE, i32, i32, i32)
 DEF_HELPER_FLAGS_2(crc32_le, TCG_CALL_NO_RWG_SE, i32, i32, i32)
+DEF_HELPER_FLAGS_3(crcn, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32)
 DEF_HELPER_FLAGS_2(shuffle, TCG_CALL_NO_RWG_SE, i32, i32, i32)
 /* CSA */
 DEF_HELPER_2(call, void, env, i32)
diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c
index 89be1ed648..0cf8eb50bd 100644
--- a/target/tricore/op_helper.c
+++ b/target/tricore/op_helper.c
@@ -2308,6 +2308,69 @@ uint32_t helper_crc32_le(uint32_t arg0, uint32_t arg1)
 return crc32(arg1, buf, 4);
 }
 
+static uint32_t crc_div(uint32_t crc_in, uint32_t data, uint32_t gen,
+uint32_t n, uint32_t m)
+{
+uint32_t i;
+
+data = data << n;
+for (i = 0; i < m; i++) {
+if (crc_in & (1u << (n - 1))) {
+crc_in <<= 1;
+if (data & (1u << (m - 1))) {
+crc_in++;
+}
+crc_in ^= gen;
+} else {
+crc_in <<= 1;
+if (data & (1u << (m - 1))) {
+crc_in++;
+}
+}
+data <<= 1;
+}
+
+return crc_in;
+}
+
+uint32_t helper_crcn(uint32_t arg0, uint32_t arg1, uint32_t arg2)
+{
+uint32_t crc_out, crc_in;
+uint32_t n = extract32(arg0, 12, 4) + 1;
+uint32_t gen = extract32(arg0, 16, n);
+uint32_t inv = extract32(arg0, 9, 1);
+uint32_t le = extract32(arg0, 8, 1);
+uint32_t m = extract32(arg0, 0, 3) + 1;
+uint32_t data = extract32(arg1, 0, m);
+uint32_t seed = extract32(arg2, 0, n);
+
+if (le == 1) {
+if (m == 0) {
+data = 0;
+} else {
+data = revbit32(data) >> (32 - m);
+}
+}
+
+if (inv == 1) {
+seed = ~seed;
+}
+
+if (m > n) {
+crc_in = (data >> (m - n)) ^ seed;
+} else {
+crc_in = (data << (n - m)) ^ seed;
+}
+
+crc_out = crc_div(crc_in, data, gen, n, m);
+
+if (inv) {
+crc_out = ~crc_out;
+}
+
+return extract32(crc_out, 0, n);
+}
+
 uint32_t helper_shuffle(uint32_t arg0, uint32_t arg1)
 {
 uint32_t resb;
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 1947733870..c2ef84af08 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -6673,6 +6673,14 @@ static void decode_rrr_divide(DisasContext *ctx)
 gen_helper_pack(cpu_gpr_d[r4], cpu_PSW_C, cpu_gpr_d[r3],
 cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
 break;
+case OPC2_32_RRR_CRCN:
+if (has_feature(ctx, TRICORE_FEATURE_162)) {
+gen_helper_crcn(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2],
+cpu_gpr_d[r3]);
+} else {
+generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+}
+break;
 case OPC2_32_RRR_ADD_F:
 gen_helper_fadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]);
 break;
diff --git a/target/tricore/tricore-opcodes.h b/target/tricore/tricore-opcodes.h
index bc62b73173..f070571665 100644
--- a/target/tricore/tricore-opcodes.h
+++ b/target/tricore/tricore-opcodes.h
@@ -1247,6 +1247,7 @@ enum {
 OPC2_32_RRR_SUB_F= 0x03,
 OPC2_32_RRR_MADD_F   = 0x06,
 OPC2_32_RRR_MSUB_F   = 0x07,
+OPC2_32_RRR_CRCN = 0x01, /* 1.6.2 up */
 };
 /*
  * RRR1 Format
diff --git a/tests/tcg/tricore/Makefile.softmmu-target 
b/tests/tcg/tricore/Makefile.softmmu-target
index f8fd207921..7a7d73a60c 100644
--- a/tests/tcg/tricore/Makefile.softmmu-target
+++ b/tests/tcg/tricore/Makefile.softmmu-target
@@ -9,6 +9,7 @@ CFLAGS = -mtc162 -c -I$(TESTS_PATH)
 TESTS += test_abs.asm.tst
 TESTS += test_bmerge.asm.tst
 TESTS += test_clz.asm.tst
+TESTS += test_crcn.asm.tst
 TESTS += test_dextr.asm.tst
 TESTS += test_dvstep.asm.tst
 TESTS += test_fadd.asm.tst
diff --git a/tests/tcg/tricore/asm/test_crcn.S 
b/tests/tcg/tri

[PATCH v2 11/11] target/tricore: Fix FTOUZ being ISA v1.3.1 up

[Bastian Koppelmann]

Reviewed-by: Richard Henderson 
Signed-off-by: Bastian Koppelmann 
---
 target/tricore/translate.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index cc2030be14..9770839749 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -6294,7 +6294,11 @@ static void decode_rr_divide(DisasContext *ctx)
 gen_helper_ftou(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
 break;
 case OPC2_32_RR_FTOUZ:
-gen_helper_ftouz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
+if (has_feature(ctx, TRICORE_FEATURE_131)) {
+gen_helper_ftouz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
+} else {
+generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+}
 break;
 case OPC2_32_RR_UPDFL:
 gen_helper_updfl(cpu_env, cpu_gpr_d[r1]);
-- 
2.41.0

[PATCH v2 03/11] target/tricore: Correctly handle FPU RM from PSW

[Bastian Koppelmann]

when we reconstructed PSW using psw_read(), we were trying to clear the
cached USB bits out of env->PSW. The mask was wrong and we would clear
PSW.RM as well.

when we write the PSW using psw_write() we update the rounding modes in
env->fp_status for softfloat. The order of bits used by TriCore is not
the one used by softfloat.

Reviewed-by: Richard Henderson 
Signed-off-by: Bastian Koppelmann 
---
 target/tricore/helper.c | 18 --
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/target/tricore/helper.c b/target/tricore/helper.c
index 6d076ac36f..e615c3d6d4 100644
--- a/target/tricore/helper.c
+++ b/target/tricore/helper.c
@@ -120,7 +120,21 @@ void tricore_cpu_list(void)
 
 void fpu_set_state(CPUTriCoreState *env)
 {
-set_float_rounding_mode(env->PSW & MASK_PSW_FPU_RM, &env->fp_status);
+switch (extract32(env->PSW, 24, 2)) {
+case 0:
+set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
+break;
+case 1:
+set_float_rounding_mode(float_round_up, &env->fp_status);
+break;
+case 2:
+set_float_rounding_mode(float_round_down, &env->fp_status);
+break;
+case 3:
+set_float_rounding_mode(float_round_to_zero, &env->fp_status);
+break;
+}
+
 set_flush_inputs_to_zero(1, &env->fp_status);
 set_flush_to_zero(1, &env->fp_status);
 set_default_nan_mode(1, &env->fp_status);
@@ -129,7 +143,7 @@ void fpu_set_state(CPUTriCoreState *env)
 uint32_t psw_read(CPUTriCoreState *env)
 {
 /* clear all USB bits */
-env->PSW &= 0x6ff;
+env->PSW &= 0x7ff;
 /* now set them from the cache */
 env->PSW |= ((env->PSW_USB_C != 0) << 31);
 env->PSW |= ((env->PSW_USB_V   & (1 << 31))  >> 1);
-- 
2.41.0

[PATCH v2 01/11] tests/tcg/tricore: Bump cpu to tc37x

[Bastian Koppelmann]

we don't want to exclude ISA v1.6.2 insns from our tests.

Acked-by: Richard Henderson 
Signed-off-by: Bastian Koppelmann 
---
 tests/tcg/tricore/Makefile.softmmu-target | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/tcg/tricore/Makefile.softmmu-target 
b/tests/tcg/tricore/Makefile.softmmu-target
index aff7c1b580..f8fd207921 100644
--- a/tests/tcg/tricore/Makefile.softmmu-target
+++ b/tests/tcg/tricore/Makefile.softmmu-target
@@ -25,7 +25,7 @@ TESTS += test_muls.asm.tst
 TESTS += test_boot_to_main.c.tst
 TESTS += test_context_save_areas.c.tst
 
-QEMU_OPTS += -M tricore_testboard -cpu tc27x -nographic -kernel
+QEMU_OPTS += -M tricore_testboard -cpu tc37x -nographic -kernel
 
 %.pS: $(ASM_TESTS_PATH)/%.S
$(HOST_CC) -E -o $@ $<
-- 
2.41.0

[PATCH v2 00/11] TriCore 1.6.2 insn and bugfixes

[Bastian Koppelmann]

Hi,

this series implements the insns reported in [1], as well as ftou. Also I fixed
two bugs in the insert insn which I came across during testing.

Cheers,
Bastian

[1] https://gitlab.com/qemu-project/qemu/-/issues/1667

v1 -> v2:
- Removed useless deposits in crc_div()
- Replaced final deposit() with extract() in helper_crcn()
- Add trap if not feature_162 (CRCN)
- Removed special case for NAN input (FTOU)
- Clarified why we need arg < 0.0 special case (FTOU, FTOUZ)
- Removed special case for f_arg being infinity (ftohp, hptof)
- Clarified, why we need a special case for arg being NAN (ftohp, hptof)


Bastian Koppelmann (11):
  tests/tcg/tricore: Bump cpu to tc37x
  target/tricore: Implement CRCN insn
  target/tricore: Correctly handle FPU RM from PSW
  target/tricore: Implement FTOU insn
  target/tricore: Clarify special case for FTOUZ insn
  target/tricore: Implement ftohp insn
  target/tricore: Implement hptof insn
  target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0
  target/tricore: Swap src and dst reg for RCRR_INSERT
  target/tricore: Replace cpu_*_code with translator_*
  target/tricore: Fix FTOUZ being ISA v1.3.1 up

 target/tricore/fpu_helper.c   | 111 ++
 target/tricore/helper.c   |  19 +++-
 target/tricore/helper.h   |   4 +
 target/tricore/op_helper.c|  63 
 target/tricore/translate.c|  56 +--
 target/tricore/tricore-opcodes.h  |   3 +
 tests/tcg/tricore/Makefile.softmmu-target |   6 +-
 tests/tcg/tricore/asm/macros.h|  24 +
 tests/tcg/tricore/asm/test_crcn.S |   9 ++
 tests/tcg/tricore/asm/test_ftohp.S|  14 +++
 tests/tcg/tricore/asm/test_ftou.S |  12 +++
 tests/tcg/tricore/asm/test_hptof.S|  12 +++
 tests/tcg/tricore/asm/test_insert.S   |  14 +++
 13 files changed, 334 insertions(+), 13 deletions(-)
 create mode 100644 tests/tcg/tricore/asm/test_crcn.S
 create mode 100644 tests/tcg/tricore/asm/test_ftohp.S
 create mode 100644 tests/tcg/tricore/asm/test_ftou.S
 create mode 100644 tests/tcg/tricore/asm/test_hptof.S

-- 
2.41.0

[PATCH v2 07/11] target/tricore: Implement hptof insn

[Bastian Koppelmann]

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1667
Signed-off-by: Bastian Koppelmann 
---
v1 -> v2:
- Removed special case for f_arg being infinity
- Clarified, why we need a special case for arg being NAN

 target/tricore/fpu_helper.c   | 36 +++
 target/tricore/helper.h   |  1 +
 target/tricore/translate.c|  7 +
 target/tricore/tricore-opcodes.h  |  1 +
 tests/tcg/tricore/Makefile.softmmu-target |  1 +
 tests/tcg/tricore/asm/test_hptof.S| 12 
 6 files changed, 58 insertions(+)
 create mode 100644 tests/tcg/tricore/asm/test_hptof.S

diff --git a/target/tricore/fpu_helper.c b/target/tricore/fpu_helper.c
index 848c4a40a0..5d38aea143 100644
--- a/target/tricore/fpu_helper.c
+++ b/target/tricore/fpu_helper.c
@@ -373,6 +373,42 @@ uint32_t helper_ftoi(CPUTriCoreState *env, uint32_t arg)
 return (uint32_t)result;
 }
 
+uint32_t helper_hptof(CPUTriCoreState *env, uint32_t arg)
+{
+float16 f_arg = make_float16(arg);
+uint32_t result = 0;
+int32_t flags = 0;
+
+/*
+ * if we have any NAN we need to move the top 2 and lower 8 input mantissa
+ * bits to the top 2 and lower 8 output mantissa bits respectively.
+ * Softfloat on the other hand uses the top 10 mantissa bits.
+ */
+if (float16_is_any_nan(f_arg)) {
+if (float16_is_signaling_nan(f_arg, &env->fp_status)) {
+flags |= float_flag_invalid;
+}
+result = 0;
+result = float32_set_sign(result, f_arg >> 15);
+result = deposit32(result, 23, 8, 0xff);
+result = deposit32(result, 21, 2, extract32(f_arg, 8, 2));
+result = deposit32(result, 0, 8, extract32(f_arg, 0, 8));
+} else {
+set_flush_inputs_to_zero(0, &env->fp_status);
+result = float16_to_float32(f_arg, true, &env->fp_status);
+set_flush_inputs_to_zero(1, &env->fp_status);
+flags = f_get_excp_flags(env);
+}
+
+if (flags) {
+f_update_psw_flags(env, flags);
+} else {
+env->FPU_FS = 0;
+}
+
+return result;
+}
+
 uint32_t helper_ftohp(CPUTriCoreState *env, uint32_t arg)
 {
 float32 f_arg = make_float32(arg);
diff --git a/target/tricore/helper.h b/target/tricore/helper.h
index dcc5a492b3..1d97d078b0 100644
--- a/target/tricore/helper.h
+++ b/target/tricore/helper.h
@@ -112,6 +112,7 @@ DEF_HELPER_3(fcmp, i32, env, i32, i32)
 DEF_HELPER_2(qseed, i32, env, i32)
 DEF_HELPER_2(ftoi, i32, env, i32)
 DEF_HELPER_2(ftohp, i32, env, i32)
+DEF_HELPER_2(hptof, i32, env, i32)
 DEF_HELPER_2(itof, i32, env, i32)
 DEF_HELPER_2(utof, i32, env, i32)
 DEF_HELPER_2(ftoiz, i32, env, i32)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 947e83b492..c2bac05de1 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -6271,6 +6271,13 @@ static void decode_rr_divide(DisasContext *ctx)
 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
 }
 break;
+   case OPC2_32_RR_HPTOF:
+if (has_feature(ctx, TRICORE_FEATURE_162)) {
+gen_helper_hptof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
+} else {
+generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+}
+break;
 case OPC2_32_RR_CMP_F:
 gen_helper_fcmp(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
 break;
diff --git a/target/tricore/tricore-opcodes.h b/target/tricore/tricore-opcodes.h
index 29e655a667..60d2402b6e 100644
--- a/target/tricore/tricore-opcodes.h
+++ b/target/tricore/tricore-opcodes.h
@@ -1153,6 +1153,7 @@ enum {
 OPC2_32_RR_CMP_F = 0x00,
 OPC2_32_RR_FTOIZ = 0x13,
 OPC2_32_RR_FTOHP = 0x25, /* 1.6.2 only */
+OPC2_32_RR_HPTOF = 0x24, /* 1.6.2 only */
 OPC2_32_RR_FTOQ31= 0x11,
 OPC2_32_RR_FTOQ31Z   = 0x18,
 OPC2_32_RR_FTOU  = 0x12,
diff --git a/tests/tcg/tricore/Makefile.softmmu-target 
b/tests/tcg/tricore/Makefile.softmmu-target
index f4a27a83e4..afcf41a977 100644
--- a/tests/tcg/tricore/Makefile.softmmu-target
+++ b/tests/tcg/tricore/Makefile.softmmu-target
@@ -17,6 +17,7 @@ TESTS += test_fmul.asm.tst
 TESTS += test_ftohp.asm.tst
 TESTS += test_ftoi.asm.tst
 TESTS += test_ftou.asm.tst
+TESTS += test_hptof.asm.tst
 TESTS += test_imask.asm.tst
 TESTS += test_insert.asm.tst
 TESTS += test_ld_bu.asm.tst
diff --git a/tests/tcg/tricore/asm/test_hptof.S 
b/tests/tcg/tricore/asm/test_hptof.S
new file mode 100644
index 00..8adc5e5273
--- /dev/null
+++ b/tests/tcg/tricore/asm/test_hptof.S
@@ -0,0 +1,12 @@
+#include "macros.h"
+.text
+.global _start
+_start:
+TEST_D_D(hptof, 1, 0xba19, 0xcc0e90c8)
+TEST_D_D(hptof, 2, 0x3eaea000, 0x8be23575)
+TEST_D_D(hptof, 3, 0xc33b8000, 0xcc48d9dc)
+TEST_D_D(hptof, 4, 0x43e2a000, 0xaef95f15)
+   

[PATCH v2 06/11] target/tricore: Implement ftohp insn

[Bastian Koppelmann]

reported in https://gitlab.com/qemu-project/qemu/-/issues/1667

Signed-off-by: Bastian Koppelmann 
---
v1 -> v2:
- Removed special case for f_arg being infinity
- Clarified, why we need a special case for arg being NAN

 target/tricore/fpu_helper.c   | 38 +++
 target/tricore/helper.c   |  1 +
 target/tricore/helper.h   |  1 +
 target/tricore/translate.c|  7 +
 target/tricore/tricore-opcodes.h  |  1 +
 tests/tcg/tricore/Makefile.softmmu-target |  1 +
 tests/tcg/tricore/asm/test_ftohp.S| 14 +
 7 files changed, 63 insertions(+)
 create mode 100644 tests/tcg/tricore/asm/test_ftohp.S

diff --git a/target/tricore/fpu_helper.c b/target/tricore/fpu_helper.c
index d0c474c5f3..848c4a40a0 100644
--- a/target/tricore/fpu_helper.c
+++ b/target/tricore/fpu_helper.c
@@ -373,6 +373,44 @@ uint32_t helper_ftoi(CPUTriCoreState *env, uint32_t arg)
 return (uint32_t)result;
 }
 
+uint32_t helper_ftohp(CPUTriCoreState *env, uint32_t arg)
+{
+float32 f_arg = make_float32(arg);
+uint32_t result = 0;
+int32_t flags = 0;
+
+/*
+ * if we have any NAN we need to move the top 2 and lower 8 input mantissa
+ * bits to the top 2 and lower 8 output mantissa bits respectively.
+ * Softfloat on the other hand uses the top 10 mantissa bits.
+ */
+if (float32_is_any_nan(f_arg)) {
+if (float32_is_signaling_nan(f_arg, &env->fp_status)) {
+flags |= float_flag_invalid;
+}
+result = float16_set_sign(result, arg >> 31);
+result = deposit32(result, 10, 5, 0x1f);
+result = deposit32(result, 8, 2, extract32(arg, 21, 2));
+result = deposit32(result, 0, 8, extract32(arg, 0, 8));
+if (extract32(result, 0, 10) == 0) {
+result |= (1 << 8);
+}
+} else {
+set_flush_to_zero(0, &env->fp_status);
+result = float32_to_float16(f_arg, true, &env->fp_status);
+set_flush_to_zero(1, &env->fp_status);
+flags = f_get_excp_flags(env);
+}
+
+if (flags) {
+f_update_psw_flags(env, flags);
+} else {
+env->FPU_FS = 0;
+}
+
+return result;
+}
+
 uint32_t helper_itof(CPUTriCoreState *env, uint32_t arg)
 {
 float32 f_result;
diff --git a/target/tricore/helper.c b/target/tricore/helper.c
index e615c3d6d4..7e5da3cb23 100644
--- a/target/tricore/helper.c
+++ b/target/tricore/helper.c
@@ -137,6 +137,7 @@ void fpu_set_state(CPUTriCoreState *env)
 
 set_flush_inputs_to_zero(1, &env->fp_status);
 set_flush_to_zero(1, &env->fp_status);
+set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status);
 set_default_nan_mode(1, &env->fp_status);
 }
 
diff --git a/target/tricore/helper.h b/target/tricore/helper.h
index 827fbaa692..dcc5a492b3 100644
--- a/target/tricore/helper.h
+++ b/target/tricore/helper.h
@@ -111,6 +111,7 @@ DEF_HELPER_4(fmsub, i32, env, i32, i32, i32)
 DEF_HELPER_3(fcmp, i32, env, i32, i32)
 DEF_HELPER_2(qseed, i32, env, i32)
 DEF_HELPER_2(ftoi, i32, env, i32)
+DEF_HELPER_2(ftohp, i32, env, i32)
 DEF_HELPER_2(itof, i32, env, i32)
 DEF_HELPER_2(utof, i32, env, i32)
 DEF_HELPER_2(ftoiz, i32, env, i32)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 165297376a..947e83b492 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -6264,6 +6264,13 @@ static void decode_rr_divide(DisasContext *ctx)
 case OPC2_32_RR_DIV_F:
 gen_helper_fdiv(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
 break;
+case OPC2_32_RR_FTOHP:
+if (has_feature(ctx, TRICORE_FEATURE_162)) {
+gen_helper_ftohp(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
+} else {
+generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+}
+break;
 case OPC2_32_RR_CMP_F:
 gen_helper_fcmp(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
 break;
diff --git a/target/tricore/tricore-opcodes.h b/target/tricore/tricore-opcodes.h
index f070571665..29e655a667 100644
--- a/target/tricore/tricore-opcodes.h
+++ b/target/tricore/tricore-opcodes.h
@@ -1152,6 +1152,7 @@ enum {
 OPC2_32_RR_ITOF  = 0x14,
 OPC2_32_RR_CMP_F = 0x00,
 OPC2_32_RR_FTOIZ = 0x13,
+OPC2_32_RR_FTOHP = 0x25, /* 1.6.2 only */
 OPC2_32_RR_FTOQ31= 0x11,
 OPC2_32_RR_FTOQ31Z   = 0x18,
 OPC2_32_RR_FTOU  = 0x12,
diff --git a/tests/tcg/tricore/Makefile.softmmu-target 
b/tests/tcg/tricore/Makefile.softmmu-target
index e6ed5c56f2..f4a27a83e4 100644
--- a/tests/tcg/tricore/Makefile.softmmu-target
+++ b/tests/tcg/tricore/Makefile.softmmu-target
@@ -14,6 +14,7 @@ TESTS += test_dextr.asm.tst
 TESTS += test_dvstep.asm.tst
 TESTS += test_fadd.asm.tst
 TESTS += test_fmul.asm.tst
+TESTS

[PATCH v2 10/11] target/tricore: Replace cpu_*_code with translator_*

[Bastian Koppelmann]

Reviewed-by: Richard Henderson 
Signed-off-by: Bastian Koppelmann 
---
 target/tricore/translate.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 403533c564..cc2030be14 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -8402,7 +8402,7 @@ static bool insn_crosses_page(CPUTriCoreState *env, 
DisasContext *ctx)
  * 4 bytes from the page boundary, so we cross the page if the first
  * 16 bits indicate that this is a 32 bit insn.
  */
-uint16_t insn = cpu_lduw_code(env, ctx->base.pc_next);
+uint16_t insn = translator_lduw(env, &ctx->base, ctx->base.pc_next);
 
 return !tricore_insn_is_16bit(insn);
 }
@@ -8415,14 +8415,15 @@ static void tricore_tr_translate_insn(DisasContextBase 
*dcbase, CPUState *cpu)
 uint16_t insn_lo;
 bool is_16bit;
 
-insn_lo = cpu_lduw_code(env, ctx->base.pc_next);
+insn_lo = translator_lduw(env, &ctx->base, ctx->base.pc_next);
 is_16bit = tricore_insn_is_16bit(insn_lo);
 if (is_16bit) {
 ctx->opcode = insn_lo;
 ctx->pc_succ_insn = ctx->base.pc_next + 2;
 decode_16Bit_opc(ctx);
 } else {
-uint32_t insn_hi = cpu_lduw_code(env, ctx->base.pc_next + 2);
+uint32_t insn_hi = translator_lduw(env, &ctx->base,
+   ctx->base.pc_next + 2);
 ctx->opcode = insn_hi << 16 | insn_lo;
 ctx->pc_succ_insn = ctx->base.pc_next + 4;
 decode_32Bit_opc(ctx);
-- 
2.41.0

[PATCH v2 09/11] target/tricore: Swap src and dst reg for RCRR_INSERT

[Bastian Koppelmann]

Signed-off-by: Bastian Koppelmann 
---
 target/tricore/translate.c  | 8 
 tests/tcg/tricore/asm/macros.h  | 9 +
 tests/tcg/tricore/asm/test_insert.S | 5 +
 3 files changed, 18 insertions(+), 4 deletions(-)

diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index ee04434f26..403533c564 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -8227,12 +8227,12 @@ static void decode_32Bit_opc(DisasContext *ctx)
 temp2 = tcg_temp_new(); /* width*/
 temp3 = tcg_temp_new(); /* pos */
 
-CHECK_REG_PAIR(r3);
+CHECK_REG_PAIR(r2);
 
-tcg_gen_andi_tl(temp2, cpu_gpr_d[r3+1], 0x1f);
-tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f);
+tcg_gen_andi_tl(temp2, cpu_gpr_d[r2 + 1], 0x1f);
+tcg_gen_andi_tl(temp3, cpu_gpr_d[r2], 0x1f);
 
-gen_insert(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, temp2, temp3);
+gen_insert(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, temp2, temp3);
 break;
 /* RCRW Format */
 case OPCM_32_RCRW_MASK_INSERT:
diff --git a/tests/tcg/tricore/asm/macros.h b/tests/tcg/tricore/asm/macros.h
index 51f6191ef2..17e696bef5 100644
--- a/tests/tcg/tricore/asm/macros.h
+++ b/tests/tcg/tricore/asm/macros.h
@@ -169,6 +169,15 @@ test_ ## num:  
  \
 insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, imm1, imm2;   \
 )
 
+#define TEST_D_DIE(insn, num, result, rs1, imm1, rs2_lo, rs2_hi)\
+TEST_CASE(num, DREG_CALC_RESULT, result,\
+LI(DREG_RS1, rs1);  \
+LI(EREG_RS2_LO, rs2_lo);\
+LI(EREG_RS2_HI, rs2_hi);\
+rstv;   \
+insn DREG_CALC_RESULT, DREG_RS1, imm1, EREG_RS2;\
+)
+
 #define TEST_D_DIII(insn, num, result, rs1, imm1, imm2, imm3)\
 TEST_CASE(num, DREG_CALC_RESULT, result, \
 LI(DREG_RS1, rs1);   \
diff --git a/tests/tcg/tricore/asm/test_insert.S 
b/tests/tcg/tricore/asm/test_insert.S
index 3978810121..223d7ce796 100644
--- a/tests/tcg/tricore/asm/test_insert.S
+++ b/tests/tcg/tricore/asm/test_insert.S
@@ -15,4 +15,9 @@ _start:
 # | |  |   |   |||
 TEST_D_DDII(insert, 4, 0x03c1e53c, 0x03c1e53c, 0x45821385, 0x7 ,0x0)
 
+#insn num   result   rs1 imm1  rs2_h   rs2_l
+# ||  |   || |   |
+TEST_D_DIE(insert, 5, 0xe30c308d, 0xe30c308d ,0x3 , 0x ,0x)
+TEST_D_DIE(insert, 6, 0x669b0120, 0x669b2820 ,0x2 , 0x5530a1c7 ,0x3a2b0f67)
+
 TEST_PASSFAIL
-- 
2.41.0

[PATCH v2 08/11] target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0

[Bastian Koppelmann]

we would crash if width was 0 for these insns, as tcg_gen_deposit() is
undefined for that case. For TriCore, width = 0 is a mov from the src reg
to the dst reg, so we special case this here.

Reviewed-by: Richard Henderson 
Signed-off-by: Bastian Koppelmann 
---
 target/tricore/translate.c  | 10 --
 tests/tcg/tricore/asm/macros.h  | 15 +++
 tests/tcg/tricore/asm/test_insert.S |  9 +
 3 files changed, 32 insertions(+), 2 deletions(-)

diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index c2bac05de1..ee04434f26 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -5317,8 +5317,11 @@ static void decode_rcpw_insert(DisasContext *ctx)
 }
 break;
 case OPC2_32_RCPW_INSERT:
+/* tcg_gen_deposit_tl() does not handle the case of width = 0 */
+if (width == 0) {
+tcg_gen_mov_tl(cpu_gpr_d[r2], cpu_gpr_d[r1]);
 /* if pos + width > 32 undefined result */
-if (pos + width <= 32) {
+} else if (pos + width <= 32) {
 temp = tcg_constant_i32(const4);
 tcg_gen_deposit_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, pos, width);
 }
@@ -6575,7 +6578,10 @@ static void decode_rrpw_extract_insert(DisasContext *ctx)
 
 break;
 case OPC2_32_RRPW_INSERT:
-if (pos + width <= 32) {
+/* tcg_gen_deposit_tl() does not handle the case of width = 0 */
+if (width == 0) {
+tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
+} else if (pos + width <= 32) {
 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
pos, width);
 }
diff --git a/tests/tcg/tricore/asm/macros.h b/tests/tcg/tricore/asm/macros.h
index b5087b5c97..51f6191ef2 100644
--- a/tests/tcg/tricore/asm/macros.h
+++ b/tests/tcg/tricore/asm/macros.h
@@ -161,6 +161,21 @@ test_ ## num:  
  \
 insn DREG_CALC_RESULT, DREG_RS1, imm1, DREG_RS2, imm2;   \
 )
 
+#define TEST_D_DDII(insn, num, result, rs1, rs2, imm1, imm2) \
+TEST_CASE(num, DREG_CALC_RESULT, result, \
+LI(DREG_RS1, rs1);   \
+LI(DREG_RS2, rs2);   \
+rstv;\
+insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, imm1, imm2;   \
+)
+
+#define TEST_D_DIII(insn, num, result, rs1, imm1, imm2, imm3)\
+TEST_CASE(num, DREG_CALC_RESULT, result, \
+LI(DREG_RS1, rs1);   \
+rstv;\
+insn DREG_CALC_RESULT, DREG_RS1, imm1, imm2, imm3;   \
+)
+
 #define TEST_E_ED(insn, num, res_hi, res_lo, rs1_hi, rs1_lo, rs2) \
 TEST_CASE_E(num, res_lo, res_hi,  \
 LI(EREG_RS1_LO, rs1_lo);  \
diff --git a/tests/tcg/tricore/asm/test_insert.S 
b/tests/tcg/tricore/asm/test_insert.S
index d5fd2237e1..3978810121 100644
--- a/tests/tcg/tricore/asm/test_insert.S
+++ b/tests/tcg/tricore/asm/test_insert.S
@@ -6,4 +6,13 @@ _start:
 # | |  ||   | ||
 TEST_D_DIDI(insert, 1, 0x7fff, 0x, 0xa, 0x10, 0x8)
 
+#insn numresultrs1imm1   imm2 imm3
+# | |  ||   | ||
+TEST_D_DIII(insert, 2, 0xd38fe370, 0xd38fe370, 0x4, 0x4 , 0x0)
+TEST_D_DIII(insert, 3, 0xd38fe374, 0xd38fe370, 0x4, 0x0 , 0x4)
+
+#insn  num   result   rs1 rs2  pos  width
+# | |  |   |   |||
+TEST_D_DDII(insert, 4, 0x03c1e53c, 0x03c1e53c, 0x45821385, 0x7 ,0x0)
+
 TEST_PASSFAIL
-- 
2.41.0

[PATCH v2 05/11] target/tricore: Clarify special case for FTOUZ insn

[Bastian Koppelmann]

this is not something other ISAs do, so clarify it with a comment.

Signed-off-by: Bastian Koppelmann 
---
 target/tricore/fpu_helper.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/target/tricore/fpu_helper.c b/target/tricore/fpu_helper.c
index 3aefeb776e..d0c474c5f3 100644
--- a/target/tricore/fpu_helper.c
+++ b/target/tricore/fpu_helper.c
@@ -475,6 +475,11 @@ uint32_t helper_ftouz(CPUTriCoreState *env, uint32_t arg)
 if (float32_is_any_nan(f_arg)) {
 result = 0;
 }
+/*
+ * we need to check arg < 0.0 before rounding as TriCore needs to raise
+ * float_flag_invalid as well. For instance, when we have a negative
+ * exponent and sign, softfloat would only raise float_flat_inexact.
+ */
 } else if (float32_lt_quiet(f_arg, 0, &env->fp_status)) {
 flags = float_flag_invalid;
 result = 0;
-- 
2.41.0

Re: [PATCH v2 3/4] qcow2: add zoned emulation capability

[Sam Li]

Stefan Hajnoczi  于2023年8月23日周三 03:48写道：
>
> On Mon, Aug 14, 2023 at 04:58:01PM +0800, Sam Li wrote:
> > By adding zone operations and zoned metadata, the zoned emulation
> > capability enables full emulation support of zoned device using
> > a qcow2 file. The zoned device metadata includes zone type,
> > zoned device state and write pointer of each zone, which is stored
> > to an array of unsigned integers.
> >
> > Each zone of a zoned device makes state transitions following
> > the zone state machine. The zone state machine mainly describes
> > five states, IMPLICIT OPEN, EXPLICIT OPEN, FULL, EMPTY and CLOSED.
> > READ ONLY and OFFLINE states will generally be affected by device
> > internal events. The operations on zones cause corresponding state
> > changing.
> >
> > Zoned devices have a limit on zone resources, which puts constraints on
> > write operations into zones.
> >
> > Signed-off-by: Sam Li 
> > ---
> >  block/qcow2.c  | 676 -
> >  block/qcow2.h  |   2 +
> >  docs/interop/qcow2.txt |   2 +
> >  3 files changed, 678 insertions(+), 2 deletions(-)
> >
> > diff --git a/block/qcow2.c b/block/qcow2.c
> > index c1077c4a4a..5ccf79cbe7 100644
> > --- a/block/qcow2.c
> > +++ b/block/qcow2.c
> > @@ -194,6 +194,164 @@ qcow2_extract_crypto_opts(QemuOpts *opts, const char 
> > *fmt, Error **errp)
> >  return cryptoopts_qdict;
> >  }
> >
> > +#define QCOW2_ZT_IS_CONV(wp)(wp & 1ULL << 59)
> > +
> > +static inline int qcow2_get_wp(uint64_t wp)
> > +{
> > +/* clear state and type information */
> > +return ((wp << 5) >> 5);
> > +}
> > +
> > +static inline int qcow2_get_zs(uint64_t wp)
> > +{
> > +return (wp >> 60);
> > +}
> > +
> > +static inline void qcow2_set_wp(uint64_t *wp, BlockZoneState zs)
> > +{
> > +uint64_t addr = qcow2_get_wp(*wp);
> > +addr |= ((uint64_t)zs << 60);
> > +*wp = addr;
> > +}
> > +
> > +/*
> > + * File wp tracking: reset zone, finish zone and append zone can
> > + * change the value of write pointer. All zone operations will change
> > + * the state of that/those zone.
> > + * */
> > +static inline void qcow2_wp_tracking_helper(int index, uint64_t wp) {
> > +/* format: operations, the wp. */
> > +printf("wps[%d]: 0x%x\n", index, qcow2_get_wp(wp)>>BDRV_SECTOR_BITS);
> > +}
> > +
> > +/*
> > + * Perform a state assignment and a flush operation that writes the new wp
> > + * value to the dedicated location of the disk file.
> > + */
> > +static int qcow2_write_wp_at(BlockDriverState *bs, uint64_t *wp,
> > + uint32_t index, BlockZoneState zs) {
> > +BDRVQcow2State *s = bs->opaque;
> > +int ret;
> > +
> > +qcow2_set_wp(wp, zs);
> > +ret = bdrv_pwrite(bs->file, s->zoned_header.zonedmeta_offset
> > ++ sizeof(uint64_t) * index, sizeof(uint64_t), wp, 0);
> > +
> > +if (ret < 0) {
> > +goto exit;
>
> Should *wp be restored to its original value to undo the effect of
> qcow2_set_wp()?
>
> > +}
> > +qcow2_wp_tracking_helper(index, *wp);
> > +return ret;
> > +
> > +exit:
> > +error_report("Failed to write metadata with file");
> > +return ret;
> > +}
> > +
> > +static int qcow2_check_active(BlockDriverState *bs)
>
> Please rename this to qcow2_check_active_zones() to avoid confusion with
> other uses "active" in qcow2.
>
> > +{
> > +BDRVQcow2State *s = bs->opaque;
> > +
> > +if (!s->zoned_header.max_active_zones) {
> > +return 0;
> > +}
> > +
> > +if (s->nr_zones_exp_open + s->nr_zones_imp_open + s->nr_zones_closed
> > +< s->zoned_header.max_active_zones) {
> > +return 0;
> > +}
> > +
> > +return -1;
> > +}
>
> (This function could return a bool instead of 0/-1 since it doesn't
> really need an int.)
>
> > +
> > +static int qcow2_check_open(BlockDriverState *bs)
>
> qcow2_check_open_zones() or, even better, qcow2_can_open_zone().
>
> > +{
> > +BDRVQcow2State *s = bs->opaque;
> > +int ret;
> > +
> > +if (!s->zoned_header.max_open_zones) {
> > +return 0;
> > +}
> > +
> > +if (s->nr_zones_exp_open + s->nr_zones_imp_open
> > +< s->zoned_header.max_open_zones) {
> > +return 0;
> > +}
> > +
> > +if(s->nr_zones_imp_open) {
> > +ret = qcow2_check_active(bs);
> > +if (ret == 0) {
> > +/* TODO: it takes O(n) time complexity (n = nr_zones).
> > + * Optimizations required. */
>
> One solution is to keep an implicitly open list. Then this operation is
> O(1).

Yes, I'll add this maybe in the v4.

>
> > +/* close one implicitly open zones to make it available */
> > +for (int i = s->zoned_header.zone_nr_conv;
> > +i < bs->bl.nr_zones; ++i) {
> > +uint64_t *wp = &s->wps->wp[i];
> > +if (qcow2_get_zs(*wp) == BLK_ZS_IOPEN) {
> > +ret = qcow2_write_wp_at(bs, wp, i, BLK_ZS_CLOSED);
>
> I'm wondering if it's correct t

Re: [PATCH 2/8] hw/acpi/cpu: Have build_cpus_aml() take a build_madt_cpu_fn callback

[Philippe Mathieu-Daudé]

On 28/8/23 09:36, Bernhard Beschow wrote:

build_cpus_aml() is architecture independent but needs to create architecture-
specific CPU AML. So far this was achieved by using a virtual method from
TYPE_ACPI_DEVICE_IF. However, build_cpus_aml() would resolve this interface from
global (!) state. This makes it quite incomprehensible where this interface
comes from (TYPE_PIIX4_PM?, TYPE_ICH9_LPC_DEVICE?, TYPE_ACPI_GED_X86?) an can
lead to crashes when the generic code is ported to new architectures.

So far, build_cpus_aml() is only called in architecture-specific code -- and
only in x86. We can therefore simply pass pc_madt_cpu_entry() as callback to
build_cpus_aml(). This is the same callback that would be used through
TYPE_ACPI_DEVICE_IF.

Signed-off-by: Bernhard Beschow 
---
  include/hw/acpi/cpu.h | 6 +-
  hw/acpi/cpu.c | 8 ++--
  hw/i386/acpi-build.c  | 4 ++--
  3 files changed, 9 insertions(+), 9 deletions(-)


Nice cleanup.

Reviewed-by: Philippe Mathieu-Daudé 

Re: [PATCH 3/8] hw/acpi/acpi_dev_interface: Remove now unused madt_cpu virtual method

[Philippe Mathieu-Daudé]

On 28/8/23 09:36, Bernhard Beschow wrote:

This virtual method was always set to the x86-specific pc_madt_cpu_entry(),
even in piix4 which is also used in MIPS. The previous changes use
pc_madt_cpu_entry() otherwise, so madt_cpu can be dropped.

Since pc_madt_cpu_entry() is now only used in x86-specific code, the stub
in hw/acpi/acpi-x86-stub can be removed as well.

Signed-off-by: Bernhard Beschow 
---
  include/hw/acpi/acpi_dev_interface.h | 2 --
  hw/acpi/acpi-x86-stub.c  | 6 --
  hw/acpi/piix4.c  | 2 --
  hw/i386/generic_event_device_x86.c   | 9 -
  hw/isa/lpc_ich9.c| 1 -
  5 files changed, 20 deletions(-)


Reviewed-by: Philippe Mathieu-Daudé 

Re: [PATCH 4/8] hw/acpi/acpi_dev_interface: Remove now unused #include "hw/boards.h"

[Philippe Mathieu-Daudé]

On 28/8/23 09:36, Bernhard Beschow wrote:

The "hw/boards.h" is unused since the previous commit. Since its removal
requires include fixes in various unrelated files to keep the code compiling it
has been split in a dedicated commit.

Signed-off-by: Bernhard Beschow 
---
  hw/acpi/hmat.h   | 3 ++-
  include/hw/acpi/acpi_dev_interface.h | 1 -
  hw/acpi/cpu.c| 1 +
  hw/acpi/hmat.c   | 1 +
  hw/acpi/memory_hotplug.c | 1 +
  5 files changed, 5 insertions(+), 2 deletions(-)


Reviewed-by: Philippe Mathieu-Daudé 

Re: [PATCH 5/8] hw/i386: Remove now redundant TYPE_ACPI_GED_X86

[Philippe Mathieu-Daudé]

On 28/8/23 09:36, Bernhard Beschow wrote:

Now that TYPE_ACPI_GED_X86 doesn't assign AcpiDeviceIfClass::madt_cpu any more
it is the same as TYPE_ACPI_GED.

Signed-off-by: Bernhard Beschow 
---
  include/hw/acpi/generic_event_device.h |  2 --
  hw/i386/generic_event_device_x86.c | 27 --
  hw/i386/microvm.c  |  2 +-
  hw/i386/meson.build|  1 -
  4 files changed, 1 insertion(+), 31 deletions(-)
  delete mode 100644 hw/i386/generic_event_device_x86.c


Reviewed-by: Philippe Mathieu-Daudé 

Re: [PATCH 8/8] hw/acpi/core: Trace enable and status registers of GPE separately

[Philippe Mathieu-Daudé]

On 28/8/23 09:36, Bernhard Beschow wrote:

The bit positions of both registers are related. Tracing the registers
independently results in the same offsets across these registers which
eases debugging.

Signed-off-by: Bernhard Beschow 
Acked-by: Igor Mammedov 
---
  hw/acpi/core.c   | 10 +++---
  hw/acpi/trace-events |  6 --
  2 files changed, 11 insertions(+), 5 deletions(-)




diff --git a/hw/acpi/trace-events b/hw/acpi/trace-events
index 159937ddb9..d387adfb0b 100644
--- a/hw/acpi/trace-events
+++ b/hw/acpi/trace-events
@@ -18,8 +18,10 @@ mhp_acpi_pc_dimm_deleted(uint32_t slot) "slot[0x%"PRIx32"] 
pc-dimm deleted"
  mhp_acpi_pc_dimm_delete_failed(uint32_t slot) "slot[0x%"PRIx32"] pc-dimm delete 
failed"
  
  # core.c

-acpi_gpe_ioport_readb(uint32_t addr, uint8_t val) "addr: 0x%" PRIx32 " ==> 
0x%" PRIx8
-acpi_gpe_ioport_writeb(uint32_t addr, uint8_t val) "addr: 0x%" PRIx32 " <== 
0x%" PRIx8
+acpi_gpe_sts_ioport_readb(uint32_t addr, uint8_t val) "addr: 0x%" PRIx32 " ==> 
0x%" PRIx8
+acpi_gpe_en_ioport_readb(uint32_t addr, uint8_t val) "addr: 0x%" PRIx32 " ==> 
0x%" PRIx8
+acpi_gpe_sts_ioport_writeb(uint32_t addr, uint8_t val) "addr: 0x%" PRIx32 " <== 
0x%" PRIx8
+acpi_gpe_en_ioport_writeb(uint32_t addr, uint8_t val) "addr: 0x%" PRIx32 " <== 
0x%" PRIx8


0x%02 for val? Otherwise:

Reviewed-by: Philippe Mathieu-Daudé 

Re: [PATCH 6/8] hw/i386/acpi-build: Determine SMI command port just once

[Philippe Mathieu-Daudé]

On 28/8/23 09:36, Bernhard Beschow wrote:

The SMI command port is currently hardcoded by means of the ACPI_PORT_SMI_CMD
macro. This hardcoding is Intel specific and doesn't match VIA, for example.
There is already the AcpiFadtData::smi_cmd attribute which is used when building
the FADT. Let's also use it when building the DSDT which confines SMI command
port determination to just one place. This allows it to become a property later,
thus resolving the Intel assumption.

Signed-off-by: Bernhard Beschow 
---
  hw/i386/acpi-build.c | 6 +++---
  1 file changed, 3 insertions(+), 3 deletions(-)


Reviewed-by: Philippe Mathieu-Daudé 

Re: [PATCH 1/8] hw/i386/acpi-build: Use pc_madt_cpu_entry() directly

[Philippe Mathieu-Daudé]

On 28/8/23 09:36, Bernhard Beschow wrote:

This is x86-specific code, so there is no advantage in using
pc_madt_cpu_entry() behind an architecture-agnostic interface.

Signed-off-by: Bernhard Beschow 
---
  hw/i386/acpi-common.h  | 3 +--
  hw/i386/acpi-build.c   | 3 +--
  hw/i386/acpi-common.c  | 5 ++---
  hw/i386/acpi-microvm.c | 3 +--
  4 files changed, 5 insertions(+), 9 deletions(-)


Reviewed-by: Philippe Mathieu-Daudé 

Re: [PATCH 1/3] hw/mips/jazz: Remove the big_endian variable

[Philippe Mathieu-Daudé]

Hi Thomas,

On 25/8/23 19:51, Thomas Huth wrote:

There is an easier way to get a value that can be used to decide
whether the target is big endian or not: Simply use the
target_words_bigendian() function instead.

Signed-off-by: Thomas Huth 
---
  hw/mips/jazz.c | 10 ++
  1 file changed, 2 insertions(+), 8 deletions(-)




@@ -157,12 +157,6 @@ static void mips_jazz_init(MachineState *machine,
  [JAZZ_PICA61] = {, 4},
  };
  
-#if TARGET_BIG_ENDIAN

-big_endian = 1;
-#else
-big_endian = 0;
-#endif
-
  if (machine->ram_size > 256 * MiB) {
  error_report("RAM size more than 256Mb is not supported");
  exit(EXIT_FAILURE);
@@ -301,7 +295,7 @@ static void mips_jazz_init(MachineState *machine,
  dev = qdev_new("dp8393x");
  qdev_set_nic_properties(dev, nd);
  qdev_prop_set_uint8(dev, "it_shift", 2);
-qdev_prop_set_bit(dev, "big_endian", big_endian > 0);
+qdev_prop_set_bit(dev, "big_endian", target_words_bigendian());


IIRC last time I tried that Peter pointed me at the documentation:

/**
 * target_words_bigendian:
 * Returns true if the (default) endianness of the target is big endian,
 * false otherwise. Note that in target-specific code, you can use
 * TARGET_BIG_ENDIAN directly instead. On the other hand, common
 * code should normally never need to know about the endianness of the
 * target, so please do *not* use this function unless you know very
 * well what you are doing!
 */

(Commit c95ac10340 "cpu: Provide a proper prototype for
 target_words_bigendian() in a header")

Should we update the comment?

Re: [PATCH] chardev/char-pty: Avoid losing bytes when the other side just (re-)connected

[Thomas Huth]

On 17/08/2023 19.09, Thomas Huth wrote:

On 17/08/2023 15.47, Marc-André Lureau wrote:

Hi

On Thu, Aug 17, 2023 at 5:06 PM Daniel P. Berrangé  
wrote:


On Thu, Aug 17, 2023 at 02:00:26PM +0200, Thomas Huth wrote:

On 17/08/2023 12.32, Daniel P. Berrangé wrote:

On Wed, Aug 16, 2023 at 11:07:43PM +0200, Thomas Huth wrote:

When starting a guest via libvirt with "virsh start --console ...",
the first second of the console output is missing. This is especially
annoying on s390x that only has a text console by default and no 
graphical

output - if the bios fails to boot here, the information about what went
wrong is completely lost.

One part of the problem (there is also some things to be done on the
libvirt side) is that QEMU only checks with a 1 second timer whether
the other side of the pty is already connected, so the first second of
the console output is always lost.

This likely used to work better in the past, since the code once checked
for a re-connection during write, but this has been removed in commit
f8278c7d74 ("char-pty: remove the check for connection on write") to 
avoid

some locking.

To ease the situation here at least a little bit, let's check with 
g_poll()

whether we could send out the data anyway, even if the connection has not
been marked as "connected" yet. The file descriptor is marked as 
non-blocking
anyway since commit fac6688a18 ("Do not hang on full PTY"), so this 
should

not cause any trouble if the other side is not ready for receiving yet.

With this patch applied, I can now successfully see the bios output of
a s390x guest when running it with "virsh start --console" (with a 
patched

version of virsh that fixes the remaining issues there, too).

Reported-by: Marc Hartmayer 
Signed-off-by: Thomas Huth 
---
   chardev/char-pty.c | 22 +++---
   1 file changed, 19 insertions(+), 3 deletions(-)

diff --git a/chardev/char-pty.c b/chardev/char-pty.c
index 4e5deac18a..fad12dfef3 100644
--- a/chardev/char-pty.c
+++ b/chardev/char-pty.c
@@ -106,11 +106,27 @@ static void pty_chr_update_read_handler(Chardev 
*chr)
   static int char_pty_chr_write(Chardev *chr, const uint8_t *buf, int 
len)

   {
   PtyChardev *s = PTY_CHARDEV(chr);
+    GPollFD pfd;
+    int rc;
-    if (!s->connected) {
-    return len;
+    if (s->connected) {
+    return io_channel_send(s->ioc, buf, len);
   }
-    return io_channel_send(s->ioc, buf, len);
+
+    /*
+ * The other side might already be re-connected, but the timer might
+ * not have fired yet. So let's check here whether we can write 
again:

+ */
+    pfd.fd = QIO_CHANNEL_FILE(s->ioc)->fd;
+    pfd.events = G_IO_OUT;
+    pfd.revents = 0;
+    rc = RETRY_ON_EINTR(g_poll(&pfd, 1, 0));
+    g_assert(rc >= 0);
+    if (!(pfd.revents & G_IO_HUP) && (pfd.revents & G_IO_OUT)) {


Should (can?) we call

 pty_chr_state(chr, 1);

here ?


As far as I understood commit f8278c7d74c6 and f7ea2038bea04628, this is 
not

possible anymore since the lock has been removed.


+    io_channel_send(s->ioc, buf, len);


As it feels a little dirty to be sending data before setting the
'connected == 1' and thus issuing the 'CHR_EVENT_OPENED' event


I didn't find a really better solution so far. We could maybe introduce a
buffer in the char-pty code and store the last second of guest output, but
IMHO that's way more complex and thus somewhat ugly, too?


The orignal commit f8278c7d74c6 said

[quote]
 char-pty: remove the check for connection on write

 This doesn't help much compared to the 1 second poll PTY
 timer. I can't think of a use case where this would help.
[/quote]

We've now identified a use case where it is actually important.

IOW, there's a justification to revert both f7ea2038bea04628 and
f8278c7d74c6, re-adding the locking and write update logic.


Indeed. But isn't it possible to watch for IO_OUT and get rid of the timer?


It might be possible - Marc Hartmayer just sent me a draft patch today that 
uses qio_channel_add_watch() and gets rid of the timer ... I'll do some 
experiments with that and send it out if it works reliably.


I did quite a bunch of experiments with the code, but as far as I can see, 
it's not so straight forward: IO_OUT keeps being enabled once IO_HUP occurs 
since the kernel can still buffer some output before it de-asserts IO_OUT. 
So there is no easy way to check for a re-connection without some kind of 
regular polling, as far as I can see...


Well, maybe something like this might be possible: Add a watch for IO_HUP. 
Once HUP occurs, don't signal CHR_EVENT_CLOSED yet, but set a flag variable 
and in case the guest still writes something to the chardev and the flag is 
true, we write the bytes to the pty one by one (to avoid locking in case the 
buffer gets full) and check for IO_OUT via g_poll() after each write. Once 
we see IO_OUT being gone, we can signal CHR_EVENT_CLOSED and add a watch for 
IO_OUT being enabled again. Once that watch triggers, we know t

Re: [RFC PATCH 1/3] cpu: Add new API cpu_type_by_name

[Philippe Mathieu-Daudé]

On 25/8/23 14:16, LIU Zhiwei wrote:

cpu_type_by_name is used to get the cpu type name from the command
line -cpu.

Currently it is only used by parse_cpu_option. In the next patch, it
will be used by other cpu query functions.

Signed-off-by: LIU Zhiwei 
---
  cpu.c | 31 +++
  1 file changed, 19 insertions(+), 12 deletions(-)


Alternative patch subject:
"cpu: Extract cpu_type_by_name() from parse_cpu_option()"

Otherwise,

Reviewed-by: Philippe Mathieu-Daudé 

Re: [RFC PATCH v2 4/6] target/riscv: Add default value for misa property

[Daniel Henrique Barboza]

On 8/28/23 05:45, LIU Zhiwei wrote:

Before this patch,
"
qemu-system-riscv64 -device rv64-riscv-cpu,v=true,help

...
v=   - Vector operations
...

"

After this patch,
"
v=   - Vector operations (default: false)
"

Signed-off-by: LIU Zhiwei 
---


Reviewed-by: Daniel Henrique Barboza 


  target/riscv/cpu.c | 12 ++--
  1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c2f102fae1..38838cd2c0 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1728,6 +1728,7 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
  int i;
  
  for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) {

+ObjectProperty *op;
  RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i];
  int bit = misa_cfg->misa_bit;
  
@@ -1739,14 +1740,13 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)

  continue;
  }
  
-object_property_add(cpu_obj, misa_cfg->name, "bool",

-cpu_get_misa_ext_cfg,
-cpu_set_misa_ext_cfg,
-NULL, (void *)misa_cfg);
+op = object_property_add(cpu_obj, misa_cfg->name, "bool",
+ cpu_get_misa_ext_cfg,
+ cpu_set_misa_ext_cfg,
+ NULL, (void *)misa_cfg);
  object_property_set_description(cpu_obj, misa_cfg->name,
  misa_cfg->description);
-object_property_set_bool(cpu_obj, misa_cfg->name,
- misa_cfg->enabled, NULL);
+object_property_set_default_bool(op, misa_cfg->enabled);
  }
  }
  

Re: [PATCH v2 08/11] target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0

[Philippe Mathieu-Daudé]

On 28/8/23 13:26, Bastian Koppelmann wrote:

we would crash if width was 0 for these insns, as tcg_gen_deposit() is
undefined for that case. For TriCore, width = 0 is a mov from the src reg
to the dst reg, so we special case this here.

Reviewed-by: Richard Henderson 
Signed-off-by: Bastian Koppelmann 
---
  target/tricore/translate.c  | 10 --
  tests/tcg/tricore/asm/macros.h  | 15 +++
  tests/tcg/tricore/asm/test_insert.S |  9 +
  3 files changed, 32 insertions(+), 2 deletions(-)


Reviewed-by: Philippe Mathieu-Daudé 

Re: [RFC PATCH v2 5/6] target/riscv: Add defalut value for string property

[Daniel Henrique Barboza]

On 8/28/23 05:45, LIU Zhiwei wrote:

Before this patch,
"""
qemu-system-riscv64 -device rv64-riscv-cpu,v=true,help

...
vext_spec=
...

"""

After this patch,
"""
vext_spec=-  (default: "v1.0")
"""

Signed-off-by: LIU Zhiwei 
---


Code LGTM.

Assuming that we'll need a new API to set default strings in 
hw/core/qdev-properties.c
(seems likely but we'll need more opinions on that) we'll need to split this 
patch in
two:

- one patch to add the new qdev_propinfo_set_default_value_string() into
hw/core/qdev-properties.c

- one to change target/riscv to use the newly created API


Thanks,


Daniel




  hw/core/qdev-prop-internal.h | 2 ++
  hw/core/qdev-properties.c| 7 +++
  include/hw/qdev-properties.h | 8 
  target/riscv/cpu.c   | 2 +-
  4 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/hw/core/qdev-prop-internal.h b/hw/core/qdev-prop-internal.h
index d7b77844fe..f0613b9757 100644
--- a/hw/core/qdev-prop-internal.h
+++ b/hw/core/qdev-prop-internal.h
@@ -13,6 +13,8 @@ void qdev_propinfo_get_enum(Object *obj, Visitor *v, const 
char *name,
  void qdev_propinfo_set_enum(Object *obj, Visitor *v, const char *name,
  void *opaque, Error **errp);
  
+void qdev_propinfo_set_default_value_string(ObjectProperty *op,

+const Property *prop);
  void qdev_propinfo_set_default_value_enum(ObjectProperty *op,
const Property *prop);
  void qdev_propinfo_set_default_value_int(ObjectProperty *op,
diff --git a/hw/core/qdev-properties.c b/hw/core/qdev-properties.c
index 357b8761b5..64f70a7292 100644
--- a/hw/core/qdev-properties.c
+++ b/hw/core/qdev-properties.c
@@ -96,6 +96,12 @@ static ObjectPropertyAccessor *field_prop_setter(const 
PropertyInfo *info)
  return info->set ? field_prop_set : NULL;
  }
  
+void qdev_propinfo_set_default_value_string(ObjectProperty *op,

+const Property *prop)
+{
+object_property_set_default_str(op, prop->defval.p);
+}
+
  void qdev_propinfo_get_enum(Object *obj, Visitor *v, const char *name,
  void *opaque, Error **errp)
  {
@@ -488,6 +494,7 @@ const PropertyInfo qdev_prop_string = {
  .release = release_string,
  .get   = get_string,
  .set   = set_string,
+.set_default_value = qdev_propinfo_set_default_value_string,
  };
  
  /* --- on/off/auto --- */

diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h
index e1df08876c..8e5651724a 100644
--- a/include/hw/qdev-properties.h
+++ b/include/hw/qdev-properties.h
@@ -22,6 +22,7 @@ struct Property {
  union {
  int64_t i;
  uint64_t u;
+void *p;
  } defval;
  int  arrayoffset;
  const PropertyInfo *arrayinfo;
@@ -91,6 +92,11 @@ extern const PropertyInfo qdev_prop_link;
  .set_default = true,   \
  .defval.u  = (_type)_defval)
  
+#define DEFINE_PROP_STR(_name, _state, _field, _defval, _prop, _type)  \

+DEFINE_PROP(_name, _state, _field, _prop, _type,   \
+.set_default = true,   \
+.defval.p  = (_type)_defval)
+
  #define DEFINE_PROP_UNSIGNED_NODEFAULT(_name, _state, _field, _prop, _type) \
  DEFINE_PROP(_name, _state, _field, _prop, _type)
  
@@ -171,6 +177,8 @@ extern const PropertyInfo qdev_prop_link;

  DEFINE_PROP_UNSIGNED(_n, _s, _f, _d, qdev_prop_size, uint64_t)
  #define DEFINE_PROP_STRING(_n, _s, _f) \
  DEFINE_PROP(_n, _s, _f, qdev_prop_string, char*)
+#define DEFINE_PROP_STRING_DEF(_n, _s, _f, _d) \
+DEFINE_PROP_STR(_n, _s, _f, _d, qdev_prop_string, char*)
  #define DEFINE_PROP_ON_OFF_AUTO(_n, _s, _f, _d) \
  DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_on_off_auto, OnOffAuto)
  #define DEFINE_PROP_SIZE32(_n, _s, _f, _d)   \
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 38838cd2c0..edcd34e62b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1769,7 +1769,7 @@ static Property riscv_cpu_extensions[] = {
  DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true),
  
  DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),

-DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
+DEFINE_PROP_STRING_DEF("vext_spec", RISCVCPU, cfg.vext_spec, "v1.0"),
  DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
  DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
  

Re: [RFC PATCH v2 6/6] linux-user: Move qemu_cpu_opts to cpu.c

[Daniel Henrique Barboza]

On 8/28/23 05:45, LIU Zhiwei wrote:

Make qemu_cpu_opts also works for linux user mode. Notice, currently
qdev monitor is not included in linux user mode. We just output
current enabled extentions for RISC-V(without the hint to print all
properties with -device).

With this patch,
"""
qemu-riscv64 -cpu rv64,help
Enabled extensions:

rv64_zicbom_zicboz_zicsr_zifencei_zihintpause_zawrs_zfa_zba_zbb_zbc_zbs_sstc_svadu
"""

Signed-off-by: LIU Zhiwei 
---



This is a similar to patch 5. Code LGTM but it's better to split the changes 
made in
the common code from the changes in a specific target.

What I suggest here is add a patch with the linux-user changes alone, then a 
second
patch with the target/riscv changes. Thanks,


Daniel



  cpu.c | 24 
  include/exec/cpu-common.h |  2 ++
  linux-user/main.c | 10 ++
  softmmu/vl.c  | 24 
  target/riscv/cpu.c|  8 +---
  5 files changed, 41 insertions(+), 27 deletions(-)

diff --git a/cpu.c b/cpu.c
index 712bd02684..590d75def0 100644
--- a/cpu.c
+++ b/cpu.c
@@ -47,6 +47,30 @@
  uintptr_t qemu_host_page_size;
  intptr_t qemu_host_page_mask;
  
+QemuOptsList qemu_cpu_opts = {

+.name = "cpu",
+.implied_opt_name = "cpu_model",
+.head = QTAILQ_HEAD_INITIALIZER(qemu_cpu_opts.head),
+.desc = {
+{ /* end of list */ }
+},
+};
+
+int cpu_help_func(void *opaque, QemuOpts *opts, Error **errp)
+{
+const char *cpu_model, *cpu_type;
+cpu_model = qemu_opt_get(opts, "cpu_model");
+if (!cpu_model) {
+return 1;
+}
+if (!qemu_opt_has_help_opt(opts)) {
+return 0;
+}
+cpu_type = cpu_type_by_name(cpu_model);
+list_cpu_props((CPUState *)object_new(cpu_type));
+return 1;
+}
+
  #ifndef CONFIG_USER_ONLY
  static int cpu_common_post_load(void *opaque, int version_id)
  {
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index b3160d9218..4d385436a5 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -168,4 +168,6 @@ int cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
  void list_cpus(void);
  void list_cpu_props(CPUState *);
  
+int cpu_help_func(void *opaque, QemuOpts *opts, Error **errp);

+extern QemuOptsList qemu_cpu_opts;
  #endif /* CPU_COMMON_H */
diff --git a/linux-user/main.c b/linux-user/main.c
index 96be354897..c3ef84b1a7 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -362,6 +362,15 @@ static void handle_arg_cpu(const char *arg)
  list_cpus();
  exit(EXIT_FAILURE);
  }
+QemuOpts *opts = qemu_opts_parse_noisily(qemu_find_opts("cpu"),
+ arg, true);
+if (!opts) {
+exit(1);
+}
+if (qemu_opts_foreach(qemu_find_opts("cpu"),
+  cpu_help_func, NULL, NULL)) {
+exit(0);
+}
  }
  
  static void handle_arg_guest_base(const char *arg)

@@ -720,6 +729,7 @@ int main(int argc, char **argv, char **envp)
  cpu_model = NULL;
  
  qemu_add_opts(&qemu_trace_opts);

+qemu_add_opts(&qemu_cpu_opts);
  qemu_plugin_add_opts();
  
  optind = parse_args(argc, argv);

diff --git a/softmmu/vl.c b/softmmu/vl.c
index bc30f3954d..d6a395454a 100644
--- a/softmmu/vl.c
+++ b/softmmu/vl.c
@@ -218,15 +218,6 @@ static struct {
  { .driver = "virtio-vga-gl",.flag = &default_vga   },
  };
  
-static QemuOptsList qemu_cpu_opts = {

-.name = "cpu",
-.implied_opt_name = "cpu_model",
-.head = QTAILQ_HEAD_INITIALIZER(qemu_cpu_opts.head),
-.desc = {
-{ /* end of list */ }
-},
-};
-
  static QemuOptsList qemu_rtc_opts = {
  .name = "rtc",
  .head = QTAILQ_HEAD_INITIALIZER(qemu_rtc_opts.head),
@@ -1149,21 +1140,6 @@ static int parse_fw_cfg(void *opaque, QemuOpts *opts, 
Error **errp)
  return 0;
  }
  
-static int cpu_help_func(void *opaque, QemuOpts *opts, Error **errp)

-{
-const char *cpu_model, *cpu_type;
-cpu_model = qemu_opt_get(opts, "cpu_model");
-if (!cpu_model) {
-return 1;
-}
-if (!qemu_opt_has_help_opt(opts)) {
-return 0;
-}
-cpu_type = cpu_type_by_name(cpu_model);
-list_cpu_props((CPUState *)object_new(cpu_type));
-return 1;
-}
-
  static int device_help_func(void *opaque, QemuOpts *opts, Error **errp)
  {
  return qdev_device_help(opts);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index edcd34e62b..e4318fcc46 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2229,15 +2229,17 @@ void riscv_cpu_list(void)
  void riscv_cpu_list_props(CPUState *cs)
  {
  char *enabled_isa;
-RISCVCPU *cpu = RISCV_CPU(cs);
-RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
-ObjectClass *oc = OBJECT_CLASS(mcc);
  
  enabled_isa = riscv_isa_string(RISCV_CPU(cs));

  qemu_printf("Enabled extensions:\n");
  qemu_printf("\t%s\n", enabled_isa);
+#ifndef CONFIG_USER_ONLY
+RISCVCPU *cpu = RISCV_CPU(cs);

Re: [PATCH 1/3] hw/mips/jazz: Remove the big_endian variable

[Thomas Huth]

On 28/08/2023 14.19, Philippe Mathieu-Daudé wrote:

Hi Thomas,

On 25/8/23 19:51, Thomas Huth wrote:

There is an easier way to get a value that can be used to decide
whether the target is big endian or not: Simply use the
target_words_bigendian() function instead.

Signed-off-by: Thomas Huth 
---
  hw/mips/jazz.c | 10 ++
  1 file changed, 2 insertions(+), 8 deletions(-)




@@ -157,12 +157,6 @@ static void mips_jazz_init(MachineState *machine,
  [JAZZ_PICA61] = {, 4},
  };
-#if TARGET_BIG_ENDIAN
-    big_endian = 1;
-#else
-    big_endian = 0;
-#endif
-
  if (machine->ram_size > 256 * MiB) {
  error_report("RAM size more than 256Mb is not supported");
  exit(EXIT_FAILURE);
@@ -301,7 +295,7 @@ static void mips_jazz_init(MachineState *machine,
  dev = qdev_new("dp8393x");
  qdev_set_nic_properties(dev, nd);
  qdev_prop_set_uint8(dev, "it_shift", 2);
-    qdev_prop_set_bit(dev, "big_endian", big_endian > 0);
+    qdev_prop_set_bit(dev, "big_endian", target_words_bigendian());


IIRC last time I tried that Peter pointed me at the documentation:

/**
  * target_words_bigendian:
  * Returns true if the (default) endianness of the target is big endian,
  * false otherwise. Note that in target-specific code, you can use
  * TARGET_BIG_ENDIAN directly instead. On the other hand, common
  * code should normally never need to know about the endianness of the
  * target, so please do *not* use this function unless you know very
  * well what you are doing!
  */

(Commit c95ac10340 "cpu: Provide a proper prototype for
  target_words_bigendian() in a header")

Should we update the comment?


What would you change? My motivation here was mainly to decrease the size of 
the code - I think it's way more complicated via the #if + extra variable 
compared to simply calling target_words_bigendian(), isn't it? I think the 
diffstat says it all...


 Thomas

Help with QEMU DBUS display

[Elijah R]

Hi!

I'm currently attempting to use qemu's DBUS display from within a go 
application, using the godbus 
 library. However, I'm 
hitting some roadblocks, and this is probably because I'm a bit confused 
about how qemu's peer-to-peer dbus connection works, and it's not 
explained in the documentation.



I invoke QEMU with the following argument

-display dbus,p2p=yes

and then connect to QMP through a separate UNIX socket. From my 
understanding, I need to listen on the socket separately in the program, 
and then pass qemu the file descriptor over QMP and run add_client.


In the same program I listen to the socket, and start waiting for a 
connection. Then, on another thread, get a file descriptor for the 
socket by first dialing it. Here's my code for that


sock, err := net.Dial("unix", "/tmp/qemudbus.sock")
if err != nil {
return err
}
uc, ok := sock.(*net.UnixConn)
if !ok {
	return fmt.Errorf("Could not cast 
Conn to UnixConn")

}
file, err := uc.File()

I then pass this file descriptor to QEMU using QMP (I'm using 
DigitalOcean's qmp library)


res, err := mon.RunWithFile([]byte(`{"execute": "getfd", "arguments": {"fdname": 
"dbusmon"}}`), file)

And add the dbus client:

res, err = mon.Run([]byte(`{"execute": "add_client", "arguments": {"protocol": "@dbus-display", 
"fdname": "dbusmon"}}`))

This seems to work fine, as I'm then (apparently) able to make a DBUS 
connection with that socket without any error.


However, when I then try to do anything with that connection (In this 
case I'm attempting to introspect /org/qemu/Display1/VM), the call hangs 
and never returns.


node, err := introspect.Call(session.Object("org.qemu.Display1.VM", 
"/org/qemu/Display1/VM"))

I'm not sure what's going wrong here, but I suspect I'm obtaining the 
file descriptor wrong (am I supposed to dial the socket?) or I'm doing 
things in the wrong order.


Thanks in advance for any help.



Regards,

Elijah R


publickey - elijah@elijahr.dev - a0a86704.asc
Description: application/pgp-keys


signature.asc
Description: OpenPGP digital signature

Re: [PATCH v2 47/58] i386/tdx: Wire REPORT_FATAL_ERROR with GuestPanic facility

[Xiaoyao Li]

On 8/21/2023 5:58 PM, Daniel P. Berrangé wrote:

On Fri, Aug 18, 2023 at 05:50:30AM -0400, Xiaoyao Li wrote:

Originated-from: Isaku Yamahata 
Signed-off-by: Xiaoyao Li 
---
  qapi/run-state.json   | 17 +--
  softmmu/runstate.c| 49 +++
  target/i386/kvm/tdx.c | 24 -
  3 files changed, 87 insertions(+), 3 deletions(-)

diff --git a/qapi/run-state.json b/qapi/run-state.json
index f216ba54ec4c..506bbe31541f 100644
--- a/qapi/run-state.json
+++ b/qapi/run-state.json
@@ -499,7 +499,7 @@
  # Since: 2.9
  ##
  { 'enum': 'GuestPanicInformationType',
-  'data': [ 'hyper-v', 's390' ] }
+  'data': [ 'hyper-v', 's390', 'tdx' ] }


Missing documentation for the 'tdx' value

  
  ##

  # @GuestPanicInformation:
@@ -514,7 +514,8 @@
   'base': {'type': 'GuestPanicInformationType'},
   'discriminator': 'type',
   'data': {'hyper-v': 'GuestPanicInformationHyperV',
-  's390': 'GuestPanicInformationS390'}}
+  's390': 'GuestPanicInformationS390',
+  'tdx' : 'GuestPanicInformationTdx'}}
  
  ##

  # @GuestPanicInformationHyperV:
@@ -577,6 +578,18 @@
'psw-addr': 'uint64',
'reason': 'S390CrashReason'}}
  
+##

+# @GuestPanicInformationTdx:
+#
+# TDX GHCI TDG.VP.VMCALL specific guest panic information


Not documented any of the struct members. Especially please include
the warning that 'message' comes from the guest and so must not be
trusted, not assumed to be well formed.


Will do it in next version.

thanks!



+#
+# Since: 8.2
+##
+{'struct': 'GuestPanicInformationTdx',
+ 'data': {'error-code': 'uint64',
+  'gpa': 'uint64',
+  'message': 'str'}}
+
  ##
  # @MEMORY_FAILURE:
  #
diff --git a/softmmu/runstate.c b/softmmu/runstate.c
index f3bd86281813..cab11484ed7e 100644
--- a/softmmu/runstate.c
+++ b/softmmu/runstate.c
@@ -518,7 +518,56 @@ void qemu_system_guest_panicked(GuestPanicInformation 
*info)
S390CrashReason_str(info->u.s390.reason),
info->u.s390.psw_mask,
info->u.s390.psw_addr);
+} else if (info->type == GUEST_PANIC_INFORMATION_TYPE_TDX) {
+char *buf = NULL;
+bool printable = false;
+
+/*
+ * Although message is defined as a json string, we shouldn't
+ * unconditionally treat it as is because the guest generated it 
and
+ * it's not necessarily trustable.
+ */
+if (info->u.tdx.message) {
+/* The caller guarantees the NUL-terminated string. */
+int len = strlen(info->u.tdx.message);
+int i;
+
+printable = len > 0;
+for (i = 0; i < len; i++) {
+if (!(0x20 <= info->u.tdx.message[i] &&
+  info->u.tdx.message[i] <= 0x7e)) {
+printable = false;
+break;
+}
+}
+
+/* 3 = length of "%02x " */
+buf = g_malloc(len * 3);
+for (i = 0; i < len; i++) {
+if (info->u.tdx.message[i] == '\0') {
+break;
+} else {
+sprintf(buf + 3 * i, "%02x ", info->u.tdx.message[i]);
+}
+}
+if (i > 0)
+/* replace the last ' '(space) to NUL */
+buf[i * 3 - 1] = '\0';
+else
+buf[0] = '\0';


You're building this escaped buffer but...


+}
+
+qemu_log_mask(LOG_GUEST_ERROR,
+  //" TDX report fatal error:\"%s\" %s",
+  " TDX report fatal error:\"%s\""
+  "error: 0x%016" PRIx64 " gpa page: 0x%016" PRIx64 
"\n",
+  printable ? info->u.tdx.message : "",
+  //buf ? buf : "",


...then not actually using it

Either delete the 'buf' code, or use it.


Sorry for posting some internal testing version.
Does below look good to you?

@@ -518,7 +518,56 @@ void 
qemu_system_guest_panicked(GuestPanicInformation *info)

   S390CrashReason_str(info->u.s390.reason),
   info->u.s390.psw_mask,
   info->u.s390.psw_addr);
+} else if (info->type == GUEST_PANIC_INFORMATION_TYPE_TDX) {
+bool printable = false;
+char *buf = NULL;
+int len = 0, i;
+
+/*
+ * Although message is defined as a json string, we shouldn't
+ * unconditionally treat it as is because the guest 
generated it and

+ * it's not necessarily trustable.
+ */
+if (info->u.tdx.message) {
+/* The caller guarantees the NUL-terminated string. */
+len = strlen(info->u.tdx.message)

Re: [PATCH] tests/avocado/machine_aspeed.py: Update SDK images

[Joel Stanley]

On Mon, 28 Aug 2023 at 09:01, Cédric Le Goater  wrote:
>
> Switch to the latest v8.06 release which introduces interesting
> changes for the AST2600 I2C and I3C models. Also take the AST2600 A2
> images instead of the default since QEMU tries to model The AST2600 A3
> SoC.

Is there any value in testing both the old and the new images?

Reviewed-by: Joel Stanley 

>
> Signed-off-by: Cédric Le Goater 
> ---
>
>   Requires patches from Hang Yu [1]
>
>   [1] 
> https://lore.kernel.org/qemu-devel/20230812065230.8839-1-francis_...@stu.pku.edu.cn/
>
>
>  tests/avocado/machine_aspeed.py | 12 ++--
>  1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/tests/avocado/machine_aspeed.py b/tests/avocado/machine_aspeed.py
> index 724ee72c0208..90f1b7cb77a1 100644
> --- a/tests/avocado/machine_aspeed.py
> +++ b/tests/avocado/machine_aspeed.py
> @@ -316,8 +316,8 @@ def test_arm_ast2500_evb_sdk(self):
>  """
>
>  image_url = ('https://github.com/AspeedTech-BMC/openbmc/releases/'
> - 'download/v08.01/ast2500-default-obmc.tar.gz')
> -image_hash = 
> ('5375f82b4c43a79427909342a1e18b4e48bd663e38466862145d27bb358796fd')
> + 'download/v08.06/ast2500-default-obmc.tar.gz')
> +image_hash = 
> ('e1755f3cadff69190438c688d52dd0f0d399b70a1e14b1d3d5540fc4851d38ca')
>  image_path = self.fetch_asset(image_url, asset_hash=image_hash,
>algorithm='sha256')
>  archive.extract(image_path, self.workdir)
> @@ -334,8 +334,8 @@ def test_arm_ast2600_evb_sdk(self):
>  """
>
>  image_url = ('https://github.com/AspeedTech-BMC/openbmc/releases/'
> - 'download/v08.01/ast2600-default-obmc.tar.gz')
> -image_hash = 
> ('f12ef15e8c1f03a214df3b91c814515c5e2b2f56119021398c1dbdd626817d15')
> + 'download/v08.06/ast2600-a2-obmc.tar.gz')
> +image_hash = 
> ('9083506135f622d5e7351fcf7d4e1c7125cee5ba16141220c0ba88931f3681a4')
>  image_path = self.fetch_asset(image_url, asset_hash=image_hash,
>algorithm='sha256')
>  archive.extract(image_path, self.workdir)
> @@ -345,8 +345,8 @@ def test_arm_ast2600_evb_sdk(self):
>  self.vm.add_args('-device',
>   'ds1338,bus=aspeed.i2c.bus.5,address=0x32');
>  self.do_test_arm_aspeed_sdk_start(
> -self.workdir + '/ast2600-default/image-bmc')
> -self.wait_for_console_pattern('nodistro.0 ast2600-default ttyS4')
> +self.workdir + '/ast2600-a2/image-bmc')
> +self.wait_for_console_pattern('nodistro.0 ast2600-a2 ttyS4')
>
>  self.ssh_connect('root', '0penBmc', False)
>  self.ssh_command('dmesg -c > /dev/null')
> --
> 2.41.0
>

Re: [RFC PATCH v2 0/6] Add API for list cpu extensions

[Igor Mammedov]

On Mon, 28 Aug 2023 16:45:30 +0800
LIU Zhiwei  wrote:

> Some times we want to know what is the really mean of one cpu option.
> For example, in RISC-V, we usually specify a cpu in this way:
> -cpu rv64,v=on
> 
> If we don't look into the source code, we can't get the ISA extensions
> of this -cpu command line.
> 
> In this patch set, we add one list_cpu_props API for common cores. It
> will output the enabled ISA extensions.
> 
> In the near future, I will also list all possible user configurable
> options and all possible extensions for this cpu.
> 
> In order to reuse the options parse code, I also add a QemuOptsList
> for cpu.
> 
> After this patch, we can output the extensions for cpu,
> """
> ./qemu-system-riscv64 -cpu rv64,help
> Enabled extensions:
> 
> rv64imafdch_zicbom_zicboz_zicsr_zifencei_zihintpause_zawrs_zfa_zba_zbb_zbc_zbs_sstc_svadu

It's not that easy to get features with values in general.
(many factors influence defaults, which may include:
 * properties set and/or added at realize time
 * defaults amended by machine type version
 * defaults amended by -global CLI options
)

To do that consensus was to query features after CPU object is realized.
Typically that implies starting dummy QEMU with needed CPU model and
then using query-cpu-model-expansion command to get actual property values.
 
The task is solved by implementing query-cpu-model-expansion
command so that user (mainly management layer) could get defaults via QMP.
So if your goal is to get the given cpu defaults to mgmt layer
it is sufficient to implement query-cpu-model-expansion command for riscv.
(CC-ing libvirt folks to see if it picks up the command
automatically for every target or some more work would be needed
on their side as well)

PS:
no one cared about making -cpu name,help working till this moment
and certainly not for linux-user part.

To make this option work reliably it's would be necessary to make sure
that query-cpu-model-expansion work in user mode as well.

Also the timing when 'help' is processed should ensure that
machine is available/initialized (i.e. compat properties are in effect) 

Once you have working query-cpu-model-expansion, your new -cpu foo,help handler
can translate json to human readable format that everyone would agree upon.

> To get all configuable options for this cpu, use -device rv64-riscv-cpu,help
> """
> 
> 
> v1->v2:
> 
> 1) Give a hint to use -device cpu,help for configualbe options on cpu
> 2) Support list_cpu_props for linux user mode
> 3) Add default to some properties to make -device cpu,help output better
> 
> 
> Todo:
> 1) Fix Daniel comments on KVM and cpu option check
> 2) Add support for other archs
> 3) Move qdev help function from qdev-monitor to qdev-property
> 
> LIU Zhiwei (6):
>   cpu: Add new API cpu_type_by_name
>   target/riscv: Add API list_cpu_props
>   softmmu/vl: Add qemu_cpu_opts QemuOptsList
>   target/riscv: Add default value for misa property
>   target/riscv: Add defalut value for string property
>   linux-user: Move qemu_cpu_opts to cpu.c
> 
>  cpu.c| 63 +---
>  hw/core/qdev-prop-internal.h |  2 ++
>  hw/core/qdev-properties.c|  7 
>  include/exec/cpu-common.h|  3 ++
>  include/hw/core/cpu.h| 11 +++
>  include/hw/qdev-properties.h |  8 +
>  linux-user/main.c| 10 ++
>  softmmu/vl.c | 11 +++
>  target/riscv/cpu.c   | 30 +
>  target/riscv/cpu.h   |  2 ++
>  10 files changed, 128 insertions(+), 19 deletions(-)
> 

Re: [PATCH v3] migration: hold the BQL during setup

[Fiona Ebner]

Ping

Am 14.07.23 um 10:20 schrieb Fiona Ebner:
> Ping
> 
> Am 30.06.23 um 16:18 schrieb Fiona Ebner:
>> This is intended to be a semantic revert of commit 9b09503752
>> ("migration: run setup callbacks out of big lock"). There have been so
>> many changes since that commit (e.g. a new setup callback
>> dirty_bitmap_save_setup() that also needs to be adapted now), it's
>> easier to do the revert manually.
>>
>> For snapshots, the bdrv_writev_vmstate() function is used during setup
>> (in QIOChannelBlock backing the QEMUFile), but not holding the BQL
>> while calling it could lead to an assertion failure. To understand
>> how, first note the following:
>>
>> 1. Generated coroutine wrappers for block layer functions spawn the
>> coroutine and use AIO_WAIT_WHILE()/aio_poll() to wait for it.
>> 2. If the host OS switches threads at an inconvenient time, it can
>> happen that a bottom half scheduled for the main thread's AioContext
>> is executed as part of a vCPU thread's aio_poll().
>>
>> An example leading to the assertion failure is as follows:
>>
>> main thread:
>> 1. A snapshot-save QMP command gets issued.
>> 2. snapshot_save_job_bh() is scheduled.
>>
>> vCPU thread:
>> 3. aio_poll() for the main thread's AioContext is called (e.g. when
>> the guest writes to a pflash device, as part of blk_pwrite which is a
>> generated coroutine wrapper).
>> 4. snapshot_save_job_bh() is executed as part of aio_poll().
>> 3. qemu_savevm_state() is called.
>> 4. qemu_mutex_unlock_iothread() is called. Now
>> qemu_get_current_aio_context() returns 0x0.
>> 5. bdrv_writev_vmstate() is executed during the usual savevm setup
>> via qemu_fflush(). But this function is a generated coroutine wrapper,
>> so it uses AIO_WAIT_WHILE. There, the assertion
>> assert(qemu_get_current_aio_context() == qemu_get_aio_context());
>> will fail.
>>
>> To fix it, ensure that the BQL is held during setup. While it would
>> only be needed for snapshots, adapting migration too avoids additional
>> logic for conditional locking/unlocking in the setup callbacks.
>> Writing the header could (in theory) also trigger qemu_fflush() and
>> thus bdrv_writev_vmstate(), so the locked section also covers the
>> qemu_savevm_state_header() call, even for migration for consistentcy.
>>
>> The section around multifd_send_sync_main() needs to be unlocked to
>> avoid a deadlock. In particular, the function calls
>> socket_send_channel_create() using multifd_new_send_channel_async() as
>> a callback and then waits for the callback to signal via the
>> channels_ready semaphore. The connection happens via
>> qio_task_run_in_thread(), but the callback is only executed via
>> qio_task_thread_result() which is scheduled for the main event loop.
>> Without unlocking the section, the main thread would never get to
>> process the task result and the callback meaning there would be no
>> signal via the channels_ready semaphore.
>>
>> The comment in ram_init_bitmaps() was introduced by 4987783400
>> ("migration: fix incorrect memory_global_dirty_log_start outside BQL")
>> and is removed, because it referred to the qemu_mutex_lock_iothread()
>> call.
>>
>> Signed-off-by: Fiona Ebner 
> 
> 
> 

Re: [PATCH] tests/avocado/machine_aspeed.py: Update SDK images

[Cédric Le Goater]

On 8/28/23 15:54, Joel Stanley wrote:

On Mon, 28 Aug 2023 at 09:01, Cédric Le Goater  wrote:


Switch to the latest v8.06 release which introduces interesting
changes for the AST2600 I2C and I3C models. Also take the AST2600 A2
images instead of the default since QEMU tries to model The AST2600 A3
SoC.


Is there any value in testing both the old and the new images?


For QEMU default tests, I think using the latest version of a test image
is just fine, or we will end up with a very long avocado test run. That
said we could make an exception when a HW feature is only activated in a
specific version.

I run pre-PR tests with more images (buildroot, mainline, sdk, openbmc,
provided by other vendors) but only the SDK v08.X images have decent
results. v07.02 and v04.05 have issues. It could be a software issue.

C.




Reviewed-by: Joel Stanley 



Signed-off-by: Cédric Le Goater 
---

   Requires patches from Hang Yu [1]

   [1] 
https://lore.kernel.org/qemu-devel/20230812065230.8839-1-francis_...@stu.pku.edu.cn/


  tests/avocado/machine_aspeed.py | 12 ++--
  1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/tests/avocado/machine_aspeed.py b/tests/avocado/machine_aspeed.py
index 724ee72c0208..90f1b7cb77a1 100644
--- a/tests/avocado/machine_aspeed.py
+++ b/tests/avocado/machine_aspeed.py
@@ -316,8 +316,8 @@ def test_arm_ast2500_evb_sdk(self):
  """

  image_url = ('https://github.com/AspeedTech-BMC/openbmc/releases/'
- 'download/v08.01/ast2500-default-obmc.tar.gz')
-image_hash = 
('5375f82b4c43a79427909342a1e18b4e48bd663e38466862145d27bb358796fd')
+ 'download/v08.06/ast2500-default-obmc.tar.gz')
+image_hash = 
('e1755f3cadff69190438c688d52dd0f0d399b70a1e14b1d3d5540fc4851d38ca')
  image_path = self.fetch_asset(image_url, asset_hash=image_hash,
algorithm='sha256')
  archive.extract(image_path, self.workdir)
@@ -334,8 +334,8 @@ def test_arm_ast2600_evb_sdk(self):
  """

  image_url = ('https://github.com/AspeedTech-BMC/openbmc/releases/'
- 'download/v08.01/ast2600-default-obmc.tar.gz')
-image_hash = 
('f12ef15e8c1f03a214df3b91c814515c5e2b2f56119021398c1dbdd626817d15')
+ 'download/v08.06/ast2600-a2-obmc.tar.gz')
+image_hash = 
('9083506135f622d5e7351fcf7d4e1c7125cee5ba16141220c0ba88931f3681a4')
  image_path = self.fetch_asset(image_url, asset_hash=image_hash,
algorithm='sha256')
  archive.extract(image_path, self.workdir)
@@ -345,8 +345,8 @@ def test_arm_ast2600_evb_sdk(self):
  self.vm.add_args('-device',
   'ds1338,bus=aspeed.i2c.bus.5,address=0x32');
  self.do_test_arm_aspeed_sdk_start(
-self.workdir + '/ast2600-default/image-bmc')
-self.wait_for_console_pattern('nodistro.0 ast2600-default ttyS4')
+self.workdir + '/ast2600-a2/image-bmc')
+self.wait_for_console_pattern('nodistro.0 ast2600-a2 ttyS4')

  self.ssh_connect('root', '0penBmc', False)
  self.ssh_command('dmesg -c > /dev/null')
--
2.41.0

[PULL 0/3] Dirty page rate and dirty page limit 20230828 patches

[Hyman Huang]

From: Hyman 

The following changes since commit 50e7a40af372ee5931c99ef7390f5d3d6fbf6ec4:

  Merge tag 'pull-target-arm-20230824' of 
https://git.linaro.org/people/pmaydell/qemu-arm into staging (2023-08-24 
10:08:33 -0400)

are available in the git repository at:

  https://github.com/newfriday/qemu.git 
tags/dirtylimit-dirtyrate-fixes-pull-request

for you to fetch changes up to e424d9f7e749c84de4a6ce532981271db1c14b23:

  migration/dirtyrate: Fix precision losses and g_usleep overshoot (2023-08-28 
21:03:58 +0800)


Dirty page limit and dirty page rate PULL request

Hi, this is the fix for dirty page limit and dirty page rate.

Please apply.

Thanks, Yong.

Andrei Gudkov (1):
  migration/dirtyrate: Fix precision losses and g_usleep overshoot

alloc.young (2):
  softmmu: Fix dirtylimit memory leak
  softmmu/dirtylimit: Convert free to g_free

 migration/dirtyrate.c | 10 --
 softmmu/dirtylimit.c  | 26 --
 2 files changed, 20 insertions(+), 16 deletions(-)

-- 
1.8.3.1

Re: [PATCH v2 2/4] qcow2: add configurations for zoned format extension

[Sam Li]

Stefan Hajnoczi  于2023年8月21日周一 21:31写道：
>
> On Mon, Aug 14, 2023 at 04:58:00PM +0800, Sam Li wrote:
> > diff --git a/block/qcow2.h b/block/qcow2.h
> > index f789ce3ae0..3694c8d217 100644
> > --- a/block/qcow2.h
> > +++ b/block/qcow2.h
> > @@ -236,6 +236,20 @@ typedef struct Qcow2CryptoHeaderExtension {
> >  uint64_t length;
> >  } QEMU_PACKED Qcow2CryptoHeaderExtension;
> >
> > +typedef struct Qcow2ZonedHeaderExtension {
> > +/* Zoned device attributes */
> > +uint8_t zoned_profile;
> > +uint8_t zoned;
> > +uint16_t reserved16;
> > +uint32_t zone_size;
> > +uint32_t zone_capacity;
>
> Should zone capacity be stored individually for each zone (alongside the
> write pointer and other per zone metadata) instead of as a global value
> for all zones? My understanding is that NVMe ZNS does not have a global
> value and each zone could have a different zone capacity value.
>
> > +uint32_t nr_zones;
>
> Is this field necessary since it can be derived from other image
> options: nr_zones = DIV_ROUND_UP(total_length, zone_capacity)?

Yes. The bs->total_sectors in refresh_limits is zero. Keeping a
persistent nr_zones helps assigning right value instead of zero.

The process is roughly like this:
*_qcow2_create: calculate nr_zones and write it to zoned_header
->  *_qcow2_update_header: update nr_zones
->  *_qcow2_read_extensions: read nr_zones in zoned_header to
Qcow2State and check if right (valid total size here)
  -> *_refresh_limits(): set bl.nr_zones to zoned_header.nr_zones

Sam

Re: [PATCH v2 3/8] machine: Print supported CPU models instead of typenames

[Igor Mammedov]

On Mon, 31 Jul 2023 15:07:30 +1000
Gavin Shan  wrote:

> On 7/27/23 19:00, Igor Mammedov wrote:
> > On Thu, 27 Jul 2023 15:16:18 +1000
> > Gavin Shan  wrote:
> >   
> >> On 7/27/23 09:08, Richard Henderson wrote:  
> >>> On 7/25/23 17:32, Gavin Shan wrote:  
>  -static const char *q800_machine_valid_cpu_types[] = {
>  +static const char * const q800_machine_valid_cpu_types[] = {
>     M68K_CPU_TYPE_NAME("m68040"),
>     NULL
>     };
>  +static const char * const q800_machine_valid_cpu_models[] = {
>  +    "m68040",
>  +    NULL
>  +};  
> >>>
> >>> I really don't like this replication.
> >>>  
> >>
> >> Right, it's going to be lots of replications, but gives much flexibility.
> >> There are 21 targets and we don't have fixed pattern for the mapping 
> >> between
> >> CPU model name and CPU typename. I'm summarizing the used patterns like 
> >> below.
> >>
> >> 1 All CPU model names are mappinged to fixed CPU typename;  
> > 
> >  plainly spelled it would be: cpu_model name ignored and
> >  a cpu type is returned anyways.
> > 
> > I'd make this hard error right away, as "junk in => error out"
> > it's clearly user error. I think we don't even have to follow
> > deprecation process for that.
> >   
> 
> Right, It's not expected behavior to map ambiguous CPU model names to
> the fixed CPU typename.

to be nice we can deprecate those and then later remove.
(while deprecating make those targets accept typenames)

> 
> >> 2 CPU model name is same to CPU typename;
> >> 3 CPU model name is alias to CPU typename;
> >> 4 CPU model name is prefix of CPU typename;  
> > 
> > and some more:
> >  5. cpu model names aren't names at all sometimes, and some other
> > CPU property is used. (ppc)
> > This one I'd prefer to get rid of and ppc handling more consistent
> > with other targets, which would need PPC folks to persuaded to drop
> > PVR lookup.
> >   
> 
> I put this into class 3, meaning the PVRs are regarded as aliases to CPU
> typenames.

with PPC using 'true' aliases, -cpu input is lost after it's translated into 
typename.
(same for alpha)

it also adds an extra fun with 'max' cpu model but that boils down to above 
statement.
(same for
  * sh4
  * cris(in user mode only, but you are making sysemu extension, so it doesn't 
count)
)
For this class of aliases reverse translation won't yield the same
result as used -cpu. The only option you have is to store -cpu cpu_model
somewhere (use qemu_opts??, and then fetch it later to print in error message)

x86 has 'aliases' as well, but in reality it creates distinct cpu types
for each 'alias', so it's possible to do reverse translation.

> >>
> >> Target Categoriessuffix-of-CPU-typename
> >> ---
> >> alpha  -234  -alpha-cpu
> >> arm---4  -arm-cpu
> >> avr-2--
> >> cris   --34  -cris-cpu
> >> hexagon---4  -hexagon-cpu
> >> hppa   1---
> >> i386   ---4  -i386-cpu
> >> loongarch  -2-4  -loongarch-cpu
> >> m68k   ---4  -m68k-cpu
> >> microblaze 1---
> >> mips   ---4  -mips64-cpu  -mips-cpu
> >> nios2  1---
> >> openrisc   ---4  -or1k-cpu
> >> ppc--34  -powerpc64-cpu  -powerpc-cpu
> >> riscv  ---4  -riscv-cpu
> >> rx -2-4  -rx-cpu
> >> s390x  ---4  -s390x-cpu
> >> sh4--34  -superh-cpu
> >> sparc  -2--

it's case 4

> >> tricore---4  -tricore-cpu
> >> xtensa ---4  -xtensa-cpu
> >>
> >> There are several options as below. Please let me know which one or 
> >> something
> >> else is the best.
> >>
> >> (a) Keep what we have and use mc->valid_{cpu_types, cpu_models}[] to track
> >> the valid CPU typenames and CPU model names.
> >>
> >> (b) Introduce CPUClass::model_name_by_typename(). Every target has their 
> >> own
> >> implementation to convert CPU typename to CPU model name. The CPU model 
> >> name
> >> is parsed from mc->valid_cpu_types[i].
> >>
> >>   char *CPUClass::model_by_typename(const char *typename);
> >>
> >> (c) As we discussed before, use mc->valid_cpu_type_suffix and 
> >> mc->valid_cpu_models
> >> because the CPU type check is currently needed by target arm/m68k/riscv 
> >> where we
> >> do have fixed pattern to convert CPU model names to CPU typenames. The CPU 
> >> typename
> >> is comprised of CPU model name and suffix. However, it won't be working 
> >> when the CPU
> >> type check is required by other target where we have patterns other than 
> >> this.  
> > 
> > none of above is really good, that's why I was objecting to introducing
> > reverse type->name mapping. That ends up with increased amount junk,
> 

[PATCH 5/8] target/translate: Restrict 'exec/cpu_ldst.h' to user emulation

[Philippe Mathieu-Daudé]

Only handle_sigsegv_accerr_write(), declared with user
emulation, requires "exec/cpu_ldst.h" (for the abi_ptr
typedef).

Signed-off-by: Philippe Mathieu-Daudé 
---
 include/exec/exec-all.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index d02517e95f..b2f5cd4c2a 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -21,7 +21,7 @@
 #define EXEC_ALL_H
 
 #include "cpu.h"
-#ifdef CONFIG_TCG
+#if defined(CONFIG_USER_ONLY)
 #include "exec/cpu_ldst.h"
 #endif
 #include "exec/translation-block.h"
-- 
2.41.0

[PATCH 7/8] target/helper: Remove unnecessary 'qemu/main-loop.h' header

[Philippe Mathieu-Daudé]

"qemu/main-loop.h" declares functions related to QEMU's
main loop mutex, which these files don't access. Remove
the unused "qemu/main-loop.h" header.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/riscv/pmu.h   | 2 --
 target/arm/ptw.c | 1 -
 target/loongarch/iocsr_helper.c  | 1 -
 target/loongarch/op_helper.c | 1 -
 target/mips/tcg/sysemu/lcsr_helper.c | 1 -
 target/nios2/op_helper.c | 1 -
 target/ppc/int_helper.c  | 1 -
 target/ppc/machine.c | 1 -
 target/ppc/mem_helper.c  | 1 -
 target/ppc/mmu_common.c  | 1 -
 target/ppc/mmu_helper.c  | 1 -
 target/ppc/power8-pmu.c  | 1 -
 target/ppc/translate.c   | 1 -
 target/riscv/csr.c   | 1 -
 target/riscv/m128_helper.c   | 1 -
 target/riscv/op_helper.c | 1 -
 target/s390x/tcg/crypto_helper.c | 1 -
 target/s390x/tcg/misc_helper.c   | 1 -
 target/xtensa/dbg_helper.c   | 1 -
 target/xtensa/fpu_helper.c   | 1 -
 target/xtensa/mmu_helper.c   | 2 --
 target/xtensa/op_helper.c| 2 --
 target/xtensa/win_helper.c   | 1 -
 23 files changed, 26 deletions(-)

diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h
index d2be06a133..2bfb71ba87 100644
--- a/target/riscv/pmu.h
+++ b/target/riscv/pmu.h
@@ -17,8 +17,6 @@
  */
 
 #include "cpu.h"
-#include "qemu/main-loop.h"
-#include "exec/exec-all.h"
 
 bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env,
 uint32_t target_ctr);
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index bfbab26b9b..a4b0172df3 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -9,7 +9,6 @@
 #include "qemu/osdep.h"
 #include "qemu/log.h"
 #include "qemu/range.h"
-#include "qemu/main-loop.h"
 #include "exec/exec-all.h"
 #include "cpu.h"
 #include "internals.h"
diff --git a/target/loongarch/iocsr_helper.c b/target/loongarch/iocsr_helper.c
index dda9845d6c..6cd01d5f09 100644
--- a/target/loongarch/iocsr_helper.c
+++ b/target/loongarch/iocsr_helper.c
@@ -6,7 +6,6 @@
  */
 
 #include "qemu/osdep.h"
-#include "qemu/main-loop.h"
 #include "cpu.h"
 #include "qemu/host-utils.h"
 #include "exec/helper-proto.h"
diff --git a/target/loongarch/op_helper.c b/target/loongarch/op_helper.c
index cf84f20aba..fe79c62fa4 100644
--- a/target/loongarch/op_helper.c
+++ b/target/loongarch/op_helper.c
@@ -7,7 +7,6 @@
 
 #include "qemu/osdep.h"
 #include "qemu/log.h"
-#include "qemu/main-loop.h"
 #include "cpu.h"
 #include "qemu/host-utils.h"
 #include "exec/helper-proto.h"
diff --git a/target/mips/tcg/sysemu/lcsr_helper.c 
b/target/mips/tcg/sysemu/lcsr_helper.c
index 8f97d04313..fb57bcbb78 100644
--- a/target/mips/tcg/sysemu/lcsr_helper.c
+++ b/target/mips/tcg/sysemu/lcsr_helper.c
@@ -7,7 +7,6 @@
  */
 
 #include "qemu/osdep.h"
-#include "qemu/main-loop.h"
 #include "cpu.h"
 #include "internal.h"
 #include "qemu/host-utils.h"
diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c
index 0aaf33ffc2..5017457c5e 100644
--- a/target/nios2/op_helper.c
+++ b/target/nios2/op_helper.c
@@ -22,7 +22,6 @@
 #include "cpu.h"
 #include "exec/helper-proto.h"
 #include "exec/exec-all.h"
-#include "qemu/main-loop.h"
 
 void helper_raise_exception(CPUNios2State *env, uint32_t index)
 {
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 834da80fe3..96cdb3c7e3 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -21,7 +21,6 @@
 #include "cpu.h"
 #include "internal.h"
 #include "qemu/host-utils.h"
-#include "qemu/main-loop.h"
 #include "qemu/log.h"
 #include "exec/helper-proto.h"
 #include "crypto/aes.h"
diff --git a/target/ppc/machine.c b/target/ppc/machine.c
index 134b16c625..1270a1f7fc 100644
--- a/target/ppc/machine.c
+++ b/target/ppc/machine.c
@@ -7,7 +7,6 @@
 #include "mmu-hash64.h"
 #include "migration/cpu.h"
 #include "qapi/error.h"
-#include "qemu/main-loop.h"
 #include "kvm_ppc.h"
 #include "power8-pmu.h"
 
diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c
index 46eae65819..c7535481d6 100644
--- a/target/ppc/mem_helper.c
+++ b/target/ppc/mem_helper.c
@@ -21,7 +21,6 @@
 #include "cpu.h"
 #include "exec/exec-all.h"
 #include "qemu/host-utils.h"
-#include "qemu/main-loop.h"
 #include "exec/helper-proto.h"
 #include "helper_regs.h"
 #include "exec/cpu_ldst.h"
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index 8c000e250d..6ca5d12207 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -28,7 +28,6 @@
 #include "exec/log.h"
 #include "helper_regs.h"
 #include "qemu/error-report.h"
-#include "qemu/main-loop.h"
 #include "qemu/qemu-print.h"
 #include "internal.h"
 #include "mmu-book3s-v3.h"
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index d3ea7588f9..f87d35379a 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -28,7 +28,6 @@
 #include "exec/log.h"
 #include "helper_regs.h"
 #include "q

[PATCH 3/8] target/translate: Include missing 'exec/cpu_ldst.h' header

[Philippe Mathieu-Daudé]

All these files access the CPU LD/ST API declared in "exec/cpu_ldst.h".

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/avr/helper.c  | 1 +
 target/i386/tcg/fpu_helper.c | 1 +
 target/i386/tcg/sysemu/excp_helper.c | 1 +
 target/loongarch/cpu.c   | 1 +
 target/mips/tcg/ldst_helper.c| 1 +
 target/mips/tcg/msa_helper.c | 1 +
 target/riscv/op_helper.c | 1 +
 target/riscv/vector_helper.c | 1 +
 8 files changed, 8 insertions(+)

diff --git a/target/avr/helper.c b/target/avr/helper.c
index e6e7d51487..fdc9884ea0 100644
--- a/target/avr/helper.c
+++ b/target/avr/helper.c
@@ -24,6 +24,7 @@
 #include "cpu.h"
 #include "hw/core/tcg-cpu-ops.h"
 #include "exec/exec-all.h"
+#include "exec/cpu_ldst.h"
 #include "exec/address-spaces.h"
 #include "exec/helper-proto.h"
 
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
index 6f3741b635..4430d3d380 100644
--- a/target/i386/tcg/fpu_helper.c
+++ b/target/i386/tcg/fpu_helper.c
@@ -21,6 +21,7 @@
 #include 
 #include "cpu.h"
 #include "tcg-cpu.h"
+#include "exec/cpu_ldst.h"
 #include "exec/helper-proto.h"
 #include "fpu/softfloat.h"
 #include "fpu/softfloat-macros.h"
diff --git a/target/i386/tcg/sysemu/excp_helper.c 
b/target/i386/tcg/sysemu/excp_helper.c
index b5f0abffa3..226689a4f2 100644
--- a/target/i386/tcg/sysemu/excp_helper.c
+++ b/target/i386/tcg/sysemu/excp_helper.c
@@ -19,6 +19,7 @@
 
 #include "qemu/osdep.h"
 #include "cpu.h"
+#include "exec/cpu_ldst.h"
 #include "exec/exec-all.h"
 #include "tcg/helper-tcg.h"
 
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 27fc6e1f33..65f9320e34 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -11,6 +11,7 @@
 #include "qapi/error.h"
 #include "qemu/module.h"
 #include "sysemu/qtest.h"
+#include "exec/cpu_ldst.h"
 #include "exec/exec-all.h"
 #include "cpu.h"
 #include "internals.h"
diff --git a/target/mips/tcg/ldst_helper.c b/target/mips/tcg/ldst_helper.c
index c1a8380e34..97056d00a2 100644
--- a/target/mips/tcg/ldst_helper.c
+++ b/target/mips/tcg/ldst_helper.c
@@ -24,6 +24,7 @@
 #include "cpu.h"
 #include "exec/helper-proto.h"
 #include "exec/exec-all.h"
+#include "exec/cpu_ldst.h"
 #include "exec/memop.h"
 #include "internal.h"
 
diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c
index 29b31d70fe..c8597b9e30 100644
--- a/target/mips/tcg/msa_helper.c
+++ b/target/mips/tcg/msa_helper.c
@@ -22,6 +22,7 @@
 #include "internal.h"
 #include "tcg/tcg.h"
 #include "exec/exec-all.h"
+#include "exec/cpu_ldst.h"
 #include "exec/helper-proto.h"
 #include "exec/memop.h"
 #include "fpu/softfloat.h"
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 9cdb9cdd06..7e2f1908ee 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -23,6 +23,7 @@
 #include "internals.h"
 #include "qemu/main-loop.h"
 #include "exec/exec-all.h"
+#include "exec/cpu_ldst.h"
 #include "exec/helper-proto.h"
 
 /* Exceptions processing helpers */
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 4d06754826..e3ef2113d6 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -22,6 +22,7 @@
 #include "cpu.h"
 #include "exec/memop.h"
 #include "exec/exec-all.h"
+#include "exec/cpu_ldst.h"
 #include "exec/helper-proto.h"
 #include "fpu/softfloat.h"
 #include "tcg/tcg-gvec-desc.h"
-- 
2.41.0

[PATCH 1/8] target/ppc/pmu: Include missing 'qemu/timer.h' header

[Philippe Mathieu-Daudé]

Since commit c2eff582a3 ("target/ppc: PMU basic cycle count for
pseries TCG") pmu_update_cycles() uses QEMU_CLOCK_VIRTUAL and
calls qemu_clock_get_ns(), both defined in "qemu/timer.h".

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/ppc/power8-pmu.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c
index 7bb4bf81f7..2537cded83 100644
--- a/target/ppc/power8-pmu.c
+++ b/target/ppc/power8-pmu.c
@@ -16,6 +16,7 @@
 #include "exec/exec-all.h"
 #include "exec/helper-proto.h"
 #include "qemu/error-report.h"
+#include "qemu/timer.h"
 #include "qemu/main-loop.h"
 #include "hw/ppc/ppc.h"
 #include "power8-pmu.h"
-- 
2.41.0

[PATCH 8/8] target/mips: Remove unused headers in lcsr_helper.c

[Philippe Mathieu-Daudé]

This files only access the address_space_ld/st API, declared
in "exec/cpu-all.h", already included by "cpu.h".

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/mips/tcg/sysemu/lcsr_helper.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/target/mips/tcg/sysemu/lcsr_helper.c 
b/target/mips/tcg/sysemu/lcsr_helper.c
index fb57bcbb78..25e03572fe 100644
--- a/target/mips/tcg/sysemu/lcsr_helper.c
+++ b/target/mips/tcg/sysemu/lcsr_helper.c
@@ -8,10 +8,7 @@
 
 #include "qemu/osdep.h"
 #include "cpu.h"
-#include "internal.h"
-#include "qemu/host-utils.h"
 #include "exec/helper-proto.h"
-#include "exec/exec-all.h"
 
 #define GET_MEMTXATTRS(cas) \
 ((MemTxAttrs){.requester_id = env_cpu(cas)->cpu_index})
-- 
2.41.0

[PATCH 0/8] target/translate: Remove unused "exec/cpu_ldst.h" / "qemu/main-loop.h"

[Philippe Mathieu-Daudé]

Yet another boring 'header cleanups' series :/

Philippe Mathieu-Daudé (8):
  target/ppc/pmu: Include missing 'qemu/timer.h' header
  target/riscv/pmu: Restrict 'qemu/log.h' include to source
  target/translate: Include missing 'exec/cpu_ldst.h' header
  target/translate: Remove unnecessary 'exec/cpu_ldst.h' header
  target/translate: Restrict 'exec/cpu_ldst.h' to user emulation
  target/helpers: Remove unnecessary 'exec/cpu_ldst.h' header
  target/helper: Remove unnecessary 'qemu/main-loop.h' header
  target/mips: Remove unused headers in lcsr_helper.c

 include/exec/exec-all.h  | 2 +-
 target/riscv/pmu.h   | 3 ---
 target/alpha/translate.c | 1 -
 target/arm/ptw.c | 1 -
 target/avr/helper.c  | 1 +
 target/cris/op_helper.c  | 1 -
 target/hexagon/translate.c   | 1 -
 target/hppa/translate.c  | 1 -
 target/i386/tcg/fpu_helper.c | 1 +
 target/i386/tcg/sysemu/excp_helper.c | 1 +
 target/loongarch/cpu.c   | 1 +
 target/loongarch/iocsr_helper.c  | 1 -
 target/loongarch/op_helper.c | 1 -
 target/m68k/translate.c  | 1 -
 target/microblaze/translate.c| 1 -
 target/mips/tcg/fpu_helper.c | 1 -
 target/mips/tcg/ldst_helper.c| 1 +
 target/mips/tcg/msa_helper.c | 1 +
 target/mips/tcg/sysemu/lcsr_helper.c | 5 -
 target/nios2/op_helper.c | 1 -
 target/nios2/translate.c | 1 -
 target/openrisc/translate.c  | 1 -
 target/ppc/int_helper.c  | 1 -
 target/ppc/machine.c | 1 -
 target/ppc/mem_helper.c  | 1 -
 target/ppc/mmu_common.c  | 1 -
 target/ppc/mmu_helper.c  | 1 -
 target/ppc/power8-pmu.c  | 2 +-
 target/ppc/translate.c   | 2 --
 target/riscv/csr.c   | 1 -
 target/riscv/m128_helper.c   | 1 -
 target/riscv/op_helper.c | 2 +-
 target/riscv/pmu.c   | 1 +
 target/riscv/vector_helper.c | 1 +
 target/s390x/tcg/crypto_helper.c | 1 -
 target/s390x/tcg/excp_helper.c   | 1 -
 target/s390x/tcg/fpu_helper.c| 1 -
 target/s390x/tcg/misc_helper.c   | 1 -
 target/sh4/translate.c   | 1 -
 target/sparc/translate.c | 1 -
 target/xtensa/dbg_helper.c   | 1 -
 target/xtensa/fpu_helper.c   | 1 -
 target/xtensa/mmu_helper.c   | 2 --
 target/xtensa/op_helper.c| 2 --
 target/xtensa/win_helper.c   | 1 -
 45 files changed, 11 insertions(+), 46 deletions(-)

-- 
2.41.0

[PATCH 2/8] target/riscv/pmu: Restrict 'qemu/log.h' include to source

[Philippe Mathieu-Daudé]

Declarations from "riscv/pmu.h" don't need anything from "qemu/log.h",
reduce it's inclusion to the source.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/riscv/pmu.h | 1 -
 target/riscv/pmu.c | 1 +
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h
index 0c819ca983..d2be06a133 100644
--- a/target/riscv/pmu.h
+++ b/target/riscv/pmu.h
@@ -16,7 +16,6 @@
  * this program.  If not, see .
  */
 
-#include "qemu/log.h"
 #include "cpu.h"
 #include "qemu/main-loop.h"
 #include "exec/exec-all.h"
diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
index db06b3882f..36f6307d28 100644
--- a/target/riscv/pmu.c
+++ b/target/riscv/pmu.c
@@ -17,6 +17,7 @@
  */
 
 #include "qemu/osdep.h"
+#include "qemu/log.h"
 #include "cpu.h"
 #include "pmu.h"
 #include "sysemu/cpu-timers.h"
-- 
2.41.0

[PATCH 4/8] target/translate: Remove unnecessary 'exec/cpu_ldst.h' header

[Philippe Mathieu-Daudé]

All these files only access the translator_ld/st API declared
in "exec/translator.h". The CPU ld/st API from declared in
"exec/cpu_ldst.h" is not used, remove it.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/alpha/translate.c  | 1 -
 target/hexagon/translate.c| 1 -
 target/hppa/translate.c   | 1 -
 target/m68k/translate.c   | 1 -
 target/microblaze/translate.c | 1 -
 target/nios2/translate.c  | 1 -
 target/openrisc/translate.c   | 1 -
 target/ppc/translate.c| 1 -
 target/sh4/translate.c| 1 -
 target/sparc/translate.c  | 1 -
 10 files changed, 10 deletions(-)

diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index 846f3d8091..d73ed28da0 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -24,7 +24,6 @@
 #include "qemu/host-utils.h"
 #include "exec/exec-all.h"
 #include "tcg/tcg-op.h"
-#include "exec/cpu_ldst.h"
 #include "exec/helper-proto.h"
 #include "exec/helper-gen.h"
 #include "exec/translator.h"
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index 708339198e..c00254e4d5 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -23,7 +23,6 @@
 #include "exec/helper-gen.h"
 #include "exec/helper-proto.h"
 #include "exec/translation-block.h"
-#include "exec/cpu_ldst.h"
 #include "exec/log.h"
 #include "internal.h"
 #include "attribs.h"
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index d66fcb3e6a..e57ac57338 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -23,7 +23,6 @@
 #include "qemu/host-utils.h"
 #include "exec/exec-all.h"
 #include "tcg/tcg-op.h"
-#include "exec/cpu_ldst.h"
 #include "exec/helper-proto.h"
 #include "exec/helper-gen.h"
 #include "exec/translator.h"
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index e07161d76f..5e68159634 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -25,7 +25,6 @@
 #include "tcg/tcg-op.h"
 #include "qemu/log.h"
 #include "qemu/qemu-print.h"
-#include "exec/cpu_ldst.h"
 #include "exec/translator.h"
 
 #include "exec/helper-proto.h"
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 7e7f837c63..d02c16296a 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -24,7 +24,6 @@
 #include "exec/exec-all.h"
 #include "tcg/tcg-op.h"
 #include "exec/helper-proto.h"
-#include "exec/cpu_ldst.h"
 #include "exec/helper-gen.h"
 #include "exec/translator.h"
 #include "qemu/qemu-print.h"
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index 4264c7ec6b..dfc546d3bb 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -29,7 +29,6 @@
 #include "exec/helper-proto.h"
 #include "exec/helper-gen.h"
 #include "exec/log.h"
-#include "exec/cpu_ldst.h"
 #include "exec/translator.h"
 #include "qemu/qemu-print.h"
 #include "semihosting/semihost.h"
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index a86360d4f5..30ff63ac0b 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -26,7 +26,6 @@
 #include "qemu/log.h"
 #include "qemu/bitops.h"
 #include "qemu/qemu-print.h"
-#include "exec/cpu_ldst.h"
 #include "exec/translator.h"
 
 #include "exec/helper-proto.h"
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 74796ec7ba..49b6a757b7 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -27,7 +27,6 @@
 #include "tcg/tcg-op-gvec.h"
 #include "qemu/host-utils.h"
 #include "qemu/main-loop.h"
-#include "exec/cpu_ldst.h"
 
 #include "exec/helper-proto.h"
 #include "exec/helper-gen.h"
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 49c87d7a01..c1e590feb3 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -22,7 +22,6 @@
 #include "disas/disas.h"
 #include "exec/exec-all.h"
 #include "tcg/tcg-op.h"
-#include "exec/cpu_ldst.h"
 #include "exec/helper-proto.h"
 #include "exec/helper-gen.h"
 #include "exec/translator.h"
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index bd877a5e4a..3e108fb19a 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -25,7 +25,6 @@
 #include "exec/helper-proto.h"
 #include "exec/exec-all.h"
 #include "tcg/tcg-op.h"
-#include "exec/cpu_ldst.h"
 
 #include "exec/helper-gen.h"
 
-- 
2.41.0

[PATCH] linux-user/riscv: Add new extensions to hwprobe

[Robbin Ehn]

This patch adds the new extensions in
linux 6.5 to the hwprobe syscall.

And fixes RVC check to OR with correct value.
The previous variable contains 0 therefore it
did work.

Signed-off-by: Robbin Ehn 
---
 linux-user/syscall.c | 14 +-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 9353268cc1..c46a0b1493 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -9049,6 +9049,10 @@ static int do_getdents64(abi_long dirfd, abi_long arg2, 
abi_long count)
 #define RISCV_HWPROBE_KEY_IMA_EXT_0 4
 #define RISCV_HWPROBE_IMA_FD   (1 << 0)
 #define RISCV_HWPROBE_IMA_C(1 << 1)
+#define RISCV_HWPROBE_IMA_V(1 << 2)
+#define RISCV_HWPROBE_EXT_ZBA  (1 << 3)
+#define RISCV_HWPROBE_EXT_ZBB  (1 << 4)
+#define RISCV_HWPROBE_EXT_ZBS  (1 << 5)
 
 #define RISCV_HWPROBE_KEY_CPUPERF_0 5
 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
@@ -9096,7 +9100,15 @@ static void risc_hwprobe_fill_pairs(CPURISCVState *env,
 riscv_has_ext(env, RVD) ?
 RISCV_HWPROBE_IMA_FD : 0;
 value |= riscv_has_ext(env, RVC) ?
- RISCV_HWPROBE_IMA_C : pair->value;
+ RISCV_HWPROBE_IMA_C : 0;
+value |= riscv_has_ext(env, RVV) ?
+ RISCV_HWPROBE_IMA_V : 0;
+value |= cfg->ext_zba ?
+ RISCV_HWPROBE_EXT_ZBA : 0;
+value |= cfg->ext_zbb ?
+ RISCV_HWPROBE_EXT_ZBB : 0;
+value |= cfg->ext_zbs ?
+ RISCV_HWPROBE_EXT_ZBS : 0;
 __put_user(value, &pair->value);
 break;
 case RISCV_HWPROBE_KEY_CPUPERF_0:
-- 
2.39.2

[PATCH 6/8] target/helpers: Remove unnecessary 'exec/cpu_ldst.h' header

[Philippe Mathieu-Daudé]

These files don't use the CPU ld/st API, remove the unnecessary
"exec/cpu_ldst.h" header.

Signed-off-by: Philippe Mathieu-Daudé 
---
 target/cris/op_helper.c  | 1 -
 target/mips/tcg/fpu_helper.c | 1 -
 target/mips/tcg/sysemu/lcsr_helper.c | 1 -
 target/s390x/tcg/excp_helper.c   | 1 -
 target/s390x/tcg/fpu_helper.c| 1 -
 5 files changed, 5 deletions(-)

diff --git a/target/cris/op_helper.c b/target/cris/op_helper.c
index 40cb74ce73..98a9aaf504 100644
--- a/target/cris/op_helper.c
+++ b/target/cris/op_helper.c
@@ -24,7 +24,6 @@
 #include "exec/helper-proto.h"
 #include "qemu/host-utils.h"
 #include "exec/exec-all.h"
-#include "exec/cpu_ldst.h"
 
 //#define CRIS_OP_HELPER_DEBUG
 
diff --git a/target/mips/tcg/fpu_helper.c b/target/mips/tcg/fpu_helper.c
index 8ce56ed7c8..45d593de48 100644
--- a/target/mips/tcg/fpu_helper.c
+++ b/target/mips/tcg/fpu_helper.c
@@ -25,7 +25,6 @@
 #include "internal.h"
 #include "exec/helper-proto.h"
 #include "exec/exec-all.h"
-#include "exec/cpu_ldst.h"
 #include "fpu/softfloat.h"
 #include "fpu_helper.h"
 
diff --git a/target/mips/tcg/sysemu/lcsr_helper.c 
b/target/mips/tcg/sysemu/lcsr_helper.c
index 942143d209..8f97d04313 100644
--- a/target/mips/tcg/sysemu/lcsr_helper.c
+++ b/target/mips/tcg/sysemu/lcsr_helper.c
@@ -13,7 +13,6 @@
 #include "qemu/host-utils.h"
 #include "exec/helper-proto.h"
 #include "exec/exec-all.h"
-#include "exec/cpu_ldst.h"
 
 #define GET_MEMTXATTRS(cas) \
 ((MemTxAttrs){.requester_id = env_cpu(cas)->cpu_index})
diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c
index b7116d0577..b875bf14e5 100644
--- a/target/s390x/tcg/excp_helper.c
+++ b/target/s390x/tcg/excp_helper.c
@@ -23,7 +23,6 @@
 #include "cpu.h"
 #include "exec/helper-proto.h"
 #include "exec/exec-all.h"
-#include "exec/cpu_ldst.h"
 #include "s390x-internal.h"
 #include "tcg_s390x.h"
 #ifndef CONFIG_USER_ONLY
diff --git a/target/s390x/tcg/fpu_helper.c b/target/s390x/tcg/fpu_helper.c
index c329b31261..d8bd5748fa 100644
--- a/target/s390x/tcg/fpu_helper.c
+++ b/target/s390x/tcg/fpu_helper.c
@@ -23,7 +23,6 @@
 #include "s390x-internal.h"
 #include "tcg_s390x.h"
 #include "exec/exec-all.h"
-#include "exec/cpu_ldst.h"
 #include "exec/helper-proto.h"
 #include "fpu/softfloat.h"
 
-- 
2.41.0

[PATCH] kconfig: Add NVME to s390x machines

[Cédric Le Goater]

From: Cédric Le Goater 

We recently had issues with nvme devices on big endian platforms.
Include their compilation on s390x to ease tests.

Signed-off-by: Cédric Le Goater 
---
 hw/nvme/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/nvme/Kconfig b/hw/nvme/Kconfig
index 8ac90942e55e..cfa2ab0f9d5a 100644
--- a/hw/nvme/Kconfig
+++ b/hw/nvme/Kconfig
@@ -1,4 +1,4 @@
 config NVME_PCI
 bool
-default y if PCI_DEVICES
+default y if PCI_DEVICES || PCIE_DEVICES
 depends on PCI
-- 
2.41.0

[PATCH v3 1/4] docs/qcow2: add the zoned format feature

[Sam Li]

Add the specs for the zoned format feature of the qcow2 driver.
The qcow2 file can be taken as zoned device and passed through by
virtio-blk device or NVMe ZNS device to the guest given zoned
information.

Signed-off-by: Sam Li 
---
 docs/system/qemu-block-drivers.rst.inc | 39 ++
 1 file changed, 39 insertions(+)

diff --git a/docs/system/qemu-block-drivers.rst.inc 
b/docs/system/qemu-block-drivers.rst.inc
index 105cb9679c..640ab151a7 100644
--- a/docs/system/qemu-block-drivers.rst.inc
+++ b/docs/system/qemu-block-drivers.rst.inc
@@ -172,6 +172,45 @@ This section describes each format and the options that 
are supported for it.
 filename`` to check if the NOCOW flag is set or not (Capital 'C' is
 NOCOW flag).
 
+  .. option:: zoned
+The zoned interface of zoned storage divices can different forms which
+is referred to as models. This option uses number to represent, 1 for
+host-managed and 0 for non-zoned.
+
+  .. option:: zone_size
+
+The size of a zone of the zoned device in bytes. The device is divided
+into zones of this size with the exception of the last zone, which may
+be smaller.
+
+  .. option:: zone_capacity
+
+The initial capacity value for all zones. The capacity must be less than
+or equal to zone size. If the last zone is smaller, then its capacity is
+capped. The device follows the ZBC protocol tends to have the same size
+as its zone.
+
+The zone capacity is per zone and may be different between zones in real
+devices. For simplicity, limits QCow2 emulation to the same zone capacity
+for all zones.
+
+  .. option:: zone_nr_conv
+
+The number of conventional zones of the zoned device.
+
+  .. option:: max_open_zones
+
+The maximal allowed open zones.
+
+  .. option:: max_active_zones
+
+The limit of the zones with implicit open, explicit open or closed state.
+
+  .. option:: max_append_sectors
+
+The maximal sectors in 512B blocks that is allowed to append to zones
+while writing.
+
 .. program:: image-formats
 .. option:: qed
 
-- 
2.40.1