Re: [PATCH] ppc/pnv: Add QME region for P10
On Fri, 7 Jul 2023 at 05:04, Cédric Le Goater wrote:
> pnv_quad_realize realizes power9 and power10 quad objects but ...
>
> > }
> >
> > static Property pnv_quad_properties[] = {
> > @@ -528,6 +581,9 @@ static void pnv_quad_power10_class_init(ObjectClass
> > *oc, void *data)
> >
> > pqc->xscom_ops = &pnv_quad_power10_xscom_ops;
> > pqc->xscom_size = PNV10_XSCOM_EQ_SIZE;
> > +
> > +pqc->xscom_qme_ops = &pnv_qme_power10_xscom_ops;
> > +pqc->xscom_qme_size = PNV10_XSCOM_QME_SIZE;
>
> xscom_qme_size is only defined on power10 and it is 0 on power9. The region
> is nevertheless initialized on power9 and never mapped.
>
> I think we should introduce a specific realize routine for each proc now.
I overlooked the P9 behaviour, thanks for pointing that out. I'll make
the realise proc specific.
Cheers,
Joel
[PATCH v2] ppc/pnv: Add QME region for P10
The Quad Management Engine (QME) manages power related settings for its
quad. The xscom region is separate from the quad xscoms, therefore a new
region is added. The xscoms in a QME select a given core by selecting
the forth nibble.
Implement dummy reads for the stop state history (SSH) and special
wakeup (SPWU) registers. This quietens some sxcom errors when skiboot
boots on p10.
Power9 does not have a QME.
Signed-off-by: Joel Stanley
---
v2:
Clean up extra whitespace
Make realize quad specific so power9 doesn't end up with the qme region
---
include/hw/ppc/pnv_core.h | 4 ++
include/hw/ppc/pnv_xscom.h | 11 ++
hw/ppc/pnv.c | 3 ++
hw/ppc/pnv_core.c | 78 +-
4 files changed, 94 insertions(+), 2 deletions(-)
diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h
index 77ef00f47a72..c829a18aa9c6 100644
--- a/include/hw/ppc/pnv_core.h
+++ b/include/hw/ppc/pnv_core.h
@@ -65,6 +65,9 @@ struct PnvQuadClass {
const MemoryRegionOps *xscom_ops;
uint64_t xscom_size;
+
+const MemoryRegionOps *xscom_qme_ops;
+uint64_t xscom_qme_size;
};
#define TYPE_PNV_QUAD "powernv-cpu-quad"
@@ -79,5 +82,6 @@ struct PnvQuad {
uint32_t quad_id;
MemoryRegion xscom_regs;
+MemoryRegion xscom_qme_regs;
};
#endif /* PPC_PNV_CORE_H */
diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h
index a4c9d95dc5d3..9bc64635471e 100644
--- a/include/hw/ppc/pnv_xscom.h
+++ b/include/hw/ppc/pnv_xscom.h
@@ -127,6 +127,17 @@ struct PnvXScomInterfaceClass {
#define PNV10_XSCOM_EC(proc)\
((0x2 << 16) | ((1 << (3 - (proc))) << 12))
+#define PNV10_XSCOM_QME(chiplet) \
+(PNV10_XSCOM_EQ(chiplet) | (0xE << 16))
+
+/*
+ * Make the region larger by 0x1000 (instead of starting at an offset) so the
+ * modelled addresses start from 0
+ */
+#define PNV10_XSCOM_QME_BASE(core) \
+((uint64_t) PNV10_XSCOM_QME(PNV10_XSCOM_EQ_CHIPLET(core)))
+#define PNV10_XSCOM_QME_SIZE(0x8000 + 0x1000)
+
#define PNV10_XSCOM_EQ_BASE(core) \
((uint64_t) PNV10_XSCOM_EQ(PNV10_XSCOM_EQ_CHIPLET(core)))
#define PNV10_XSCOM_EQ_SIZE0x2
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 23740f9d0733..eb54f93986df 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1685,6 +1685,9 @@ static void pnv_chip_power10_quad_realize(Pnv10Chip
*chip10, Error **errp)
pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id),
&eq->xscom_regs);
+
+pnv_xscom_add_subregion(chip, PNV10_XSCOM_QME_BASE(eq->quad_id),
+&eq->xscom_qme_regs);
}
}
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index 1f244ed181d0..09eb2bf94b9e 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -493,7 +493,67 @@ static const MemoryRegionOps pnv_quad_power10_xscom_ops = {
.endianness = DEVICE_BIG_ENDIAN,
};
-static void pnv_quad_realize(DeviceState *dev, Error **errp)
+#define P10_QME_SPWU_HYP 0x83c
+#define P10_QME_SSH_HYP 0x82c
+
+static uint64_t pnv_qme_power10_xscom_read(void *opaque, hwaddr addr,
+unsigned int width)
+{
+uint32_t offset = addr >> 3;
+uint64_t val = -1;
+
+/*
+ * Forth nibble selects the core within a quad, mask it to process read
+ * for any core.
+ */
+switch (offset & ~0xf000) {
+case P10_QME_SPWU_HYP:
+case P10_QME_SSH_HYP:
+return 0;
+default:
+qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__,
+ offset);
+}
+
+return val;
+}
+
+static void pnv_qme_power10_xscom_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned int width)
+{
+uint32_t offset = addr >> 3;
+
+switch (offset) {
+default:
+qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__,
+ offset);
+}
+}
+
+static const MemoryRegionOps pnv_qme_power10_xscom_ops = {
+.read = pnv_qme_power10_xscom_read,
+.write = pnv_qme_power10_xscom_write,
+.valid.min_access_size = 8,
+.valid.max_access_size = 8,
+.impl.min_access_size = 8,
+.impl.max_access_size = 8,
+.endianness = DEVICE_BIG_ENDIAN,
+};
+
+static void pnv_quad_power9_realize(DeviceState *dev, Error **errp)
+{
+PnvQuad *eq = PNV_QUAD(dev);
+PnvQuadClass *pqc = PNV_QUAD_GET_CLASS(eq);
+char name[32];
+
+snprintf(name, sizeof(name), "xscom-quad.%d", eq->quad_id);
+pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev),
+ pqc->xscom_ops,
+ eq, name,
+ pqc->xscom_size);
+}
+
+static void pnv_quad_power10_realize(DeviceState *dev, Error **errp)
{
PnvQuad *eq = PNV_QUAD(dev);
PnvQuadClass *pqc = PNV_QUAD_GET_CLASS(eq);
@@ -504,6 +564,12 @@ static void pnv_quad_realize(DeviceState *dev, Error
**errp)
Re: [PATCH] target/riscv KVM_RISCV_SET_TIMER macro is not configured correctly
On 7/7/23 00:23, yang.zhang wrote:
From: "yang.zhang"
Should set/get riscv all reg timer,i.e, time/compare/frequency/state.
Nice catch.
The reason why this went under the radar for 18 months is because kvm.c is using
an external 'time' variable.
Signed-off-by:Yang Zhang
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1688
---
Reviewed-by: Daniel Henrique Barboza
target/riscv/kvm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index 30f21453d6..0c567f668c 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -99,7 +99,7 @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t
type,
#define KVM_RISCV_SET_TIMER(cs, env, name, reg) \
do { \
-int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(env, time), ®); \
+int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(env, name), ®); \
if (ret) { \
abort(); \
} \
Re: [PATCH] ppc/pnv: Log all unimp warnings with similar message
Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks,
Daniel
On 7/5/23 23:45, Joel Stanley wrote:
Add the function name so there's an indication as to where the message
is coming from. Change all prints to use the offset instead of the
address.
Signed-off-by: Joel Stanley
---
Happy to use the address instead of the offset (or print both), but I
like the idea of being consistent.
---
hw/ppc/pnv_core.c | 34 ++
1 file changed, 18 insertions(+), 16 deletions(-)
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index ffbc29cbf4f9..3eb95670d6a3 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -85,8 +85,8 @@ static uint64_t pnv_core_power8_xscom_read(void *opaque,
hwaddr addr,
val = 0x24full;
break;
default:
-qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
- addr);
+qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__,
+ offset);
}
return val;
@@ -95,8 +95,10 @@ static uint64_t pnv_core_power8_xscom_read(void *opaque,
hwaddr addr,
static void pnv_core_power8_xscom_write(void *opaque, hwaddr addr, uint64_t
val,
unsigned int width)
{
-qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n",
- addr);
+uint32_t offset = addr >> 3;
+
+qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__,
+ offset);
}
static const MemoryRegionOps pnv_core_power8_xscom_ops = {
@@ -140,8 +142,8 @@ static uint64_t pnv_core_power9_xscom_read(void *opaque,
hwaddr addr,
val = 0;
break;
default:
-qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
- addr);
+qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__,
+ offset);
}
return val;
@@ -157,8 +159,8 @@ static void pnv_core_power9_xscom_write(void *opaque,
hwaddr addr, uint64_t val,
case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR:
break;
default:
-qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx
"\n",
- addr);
+qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__,
+ offset);
}
}
@@ -189,8 +191,8 @@ static uint64_t pnv_core_power10_xscom_read(void *opaque, hwaddr addr,
val = 0;
break;
default:
-qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
- addr);
+qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__,
+ offset);
}
return val;
@@ -203,8 +205,8 @@ static void pnv_core_power10_xscom_write(void *opaque,
hwaddr addr,
switch (offset) {
default:
-qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx
"\n",
- addr);
+qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__,
+ offset);
}
}
@@ -421,7 +423,7 @@ static uint64_t pnv_quad_power9_xscom_read(void *opaque, hwaddr addr,
val = 0;
break;
default:
-qemu_log_mask(LOG_UNIMP, "%s: reading @0x%08x\n", __func__,
+qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__,
offset);
}
@@ -438,7 +440,7 @@ static void pnv_quad_power9_xscom_write(void *opaque, hwaddr addr, uint64_t val,
case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */
break;
default:
-qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
+qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__,
offset);
}
}
@@ -465,7 +467,7 @@ static uint64_t pnv_quad_power10_xscom_read(void *opaque,
hwaddr addr,
switch (offset) {
default:
-qemu_log_mask(LOG_UNIMP, "%s: reading @0x%08x\n", __func__,
+qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__,
offset);
}
@@ -479,7 +481,7 @@ static void pnv_quad_power10_xscom_write(void *opaque, hwaddr addr,
switch (offset) {
default:
-qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
+qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__,
offset);
}
}
Re: [RESEND PATCH v3 0/4] PPC440 devices misc clean up
Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks, Daniel On 7/6/23 08:16, BALATON Zoltan wrote: These are some small misc clean ups to PPC440 related device models which is all I have ready for now. v3: - rebased on ppc-next moving already reviewed patch to front v2: - Added R-b tags from Philippe - Addressed review comments - Added new patch to rename parent field of PPC460EXPCIEState to parent_obj BALATON Zoltan (4): ppc440_pcix: Stop using system io region for PCI bus ppc4xx_pci: Rename QOM type name define ppc4xx_pci: Add define for ppc4xx-host-bridge type name ppc440_pcix: Rename QOM type define abd move it to common header hw/ppc/ppc440_bamboo.c | 3 +-- hw/ppc/ppc440_pcix.c| 21 - hw/ppc/ppc4xx_pci.c | 10 +- hw/ppc/sam460ex.c | 8 ++-- include/hw/ppc/ppc4xx.h | 4 +++- 5 files changed, 23 insertions(+), 23 deletions(-)
Re: [PATCH v2 0/2] ppc/pnv: Set P10 core xscom region size to match hardware
Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks, Daniel On 7/6/23 02:39, Nicholas Piggin wrote: Sorry about the paper bag bug in the first version of the patch - I broke powernv8 and 9. This adds a xsom_size core class field to change the P10 size without changing the others. Also added a P10 xscom test, and passes make check. Thanks, Nick Nicholas Piggin (2): ppc/pnv: Set P10 core xscom region size to match hardware tests/qtest: Add xscom tests for powernv10 machine hw/ppc/pnv_core.c| 6 +++-- include/hw/ppc/pnv_core.h| 1 + include/hw/ppc/pnv_xscom.h | 2 +- tests/qtest/pnv-xscom-test.c | 44 4 files changed, 41 insertions(+), 12 deletions(-)
Re: [PATCH v3] target/ppc: Machine check on invalid real address access on POWER9/10
Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks,
Daniel
On 7/3/23 09:03, Nicholas Piggin wrote:
ppc currently silently accepts invalid real address access. Catch
these and turn them into machine checks on POWER9/10 machines.
Signed-off-by: Nicholas Piggin
---
Since v1:
- Only implement this for POWER9/10. Seems like previous IBM processors
may not catch this, trying to get info.
Since v2:
- Split out from larger series since it is independent.
target/ppc/cpu_init.c| 1 +
target/ppc/excp_helper.c | 49
target/ppc/internal.h| 5
3 files changed, 55 insertions(+)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 720aad9e05..6ac1765a8d 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -7335,6 +7335,7 @@ static const struct TCGCPUOps ppc_tcg_ops = {
.cpu_exec_enter = ppc_cpu_exec_enter,
.cpu_exec_exit = ppc_cpu_exec_exit,
.do_unaligned_access = ppc_cpu_do_unaligned_access,
+ .do_transaction_failed = ppc_cpu_do_transaction_failed,
#endif /* !CONFIG_USER_ONLY */
};
#endif /* CONFIG_TCG */
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 354392668e..e49e13a30d 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -1428,7 +1428,9 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
/* machine check exceptions don't have ME set */
new_msr &= ~((target_ulong)1 << MSR_ME);
+msr |= env->error_code;
break;
+
case POWERPC_EXCP_DSI: /* Data storage exception
*/
trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
break;
@@ -3184,5 +3186,52 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr
vaddr,
env->error_code = insn & 0x03FF;
cpu_loop_exit(cs);
}
+
+void ppc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
+ vaddr vaddr, unsigned size,
+ MMUAccessType access_type,
+ int mmu_idx, MemTxAttrs attrs,
+ MemTxResult response, uintptr_t retaddr)
+{
+CPUPPCState *env = cs->env_ptr;
+
+switch (env->excp_model) {
+#if defined(TARGET_PPC64)
+case POWERPC_EXCP_POWER9:
+case POWERPC_EXCP_POWER10:
+/*
+ * Machine check codes can be found in processor User Manual or
+ * Linux or skiboot source.
+ */
+if (access_type == MMU_DATA_LOAD) {
+env->spr[SPR_DAR] = vaddr;
+env->spr[SPR_DSISR] = PPC_BIT(57);
+env->error_code = PPC_BIT(42);
+
+} else if (access_type == MMU_DATA_STORE) {
+/*
+ * MCE for stores in POWER is asynchronous so hardware does
+ * not set DAR, but QEMU can do better.
+ */
+env->spr[SPR_DAR] = vaddr;
+env->error_code = PPC_BIT(36) | PPC_BIT(43) | PPC_BIT(45);
+env->error_code |= PPC_BIT(42);
+
+} else { /* Fetch */
+env->error_code = PPC_BIT(36) | PPC_BIT(44) | PPC_BIT(45);
+}
+break;
+#endif
+default:
+/*
+ * TODO: Check behaviour for other CPUs, for now do nothing.
+ * Could add a basic MCE even if real hardware ignores.
+ */
+return;
+}
+
+cs->exception_index = POWERPC_EXCP_MCHECK;
+cpu_loop_exit_restore(cs, retaddr);
+}
#endif /* CONFIG_TCG */
#endif /* !CONFIG_USER_ONLY */
diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index 901bae6d39..57acb3212c 100644
--- a/target/ppc/internal.h
+++ b/target/ppc/internal.h
@@ -296,6 +296,11 @@ bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int
size,
G_NORETURN void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
MMUAccessType access_type, int
mmu_idx,
uintptr_t retaddr);
+void ppc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
+ vaddr addr, unsigned size,
+ MMUAccessType access_type,
+ int mmu_idx, MemTxAttrs attrs,
+ MemTxResult response, uintptr_t retaddr);
#endif
FIELD(GER_MSK, XMSK, 0, 4)
Re: [PATCH v3 0/6] target/ppc: Few cleanups in kvm_ppc.h
Phil, I queued all patches to ppc-next. I fixed up patch 3 to not move the cpu_list macro as Greg suggested. If you're strongly attached to it let me know and I'll remove it from the queue. Greg, feel free to send your R-b in patch 3 if patch 3 with this change pleases you. Daniel On 6/27/23 08:51, Philippe Mathieu-Daudé wrote: PPC specific changes of a bigger KVM cleanup, remove "kvm_ppc.h" from user emulation. Mostly trivial IMO. Philippe Mathieu-Daudé (6): target/ppc: Have 'kvm_ppc.h' include 'sysemu/kvm.h' target/ppc: Reorder #ifdef'ry in kvm_ppc.h target/ppc: Move CPU QOM definitions to cpu-qom.h target/ppc: Define TYPE_HOST_POWERPC_CPU in cpu-qom.h target/ppc: Restrict 'kvm_ppc.h' to sysemu in cpu_init.c target/ppc: Remove pointless checks of CONFIG_USER_ONLY in 'kvm_ppc.h' target/ppc/cpu-qom.h | 7 + target/ppc/cpu.h | 6 target/ppc/kvm_ppc.h | 70 ++- target/ppc/cpu_init.c | 2 +- 4 files changed, 37 insertions(+), 48 deletions(-)
Re: [PATCH v2] ppc/pnv: Add QME region for P10
On 7/7/23 09:12, Joel Stanley wrote:
The Quad Management Engine (QME) manages power related settings for its
quad. The xscom region is separate from the quad xscoms, therefore a new
region is added. The xscoms in a QME select a given core by selecting
the forth nibble.
Implement dummy reads for the stop state history (SSH) and special
wakeup (SPWU) registers. This quietens some sxcom errors when skiboot
boots on p10.
Power9 does not have a QME.
Signed-off-by: Joel Stanley
Nice, how about these now :
[ 24.482066616,3] Could not set special wakeup on 0:0: operation timeout.
[ 25.022003091,3] Could not set special wakeup on 0:0: operation timeout.
[ 25.073902795,3] Could not set special wakeup on 0:0: operation timeout.
[ 1593.383133413,3] Could not set special wakeup on 0:0: timeout waiting for
SPECIAL_WKUP_DONE.
[ 1593.435173594,3] Could not set special wakeup on 0:0: timeout waiting for
SPECIAL_WKUP_DONE.
:)
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
v2:
Clean up extra whitespace
Make realize quad specific so power9 doesn't end up with the qme region
---
include/hw/ppc/pnv_core.h | 4 ++
include/hw/ppc/pnv_xscom.h | 11 ++
hw/ppc/pnv.c | 3 ++
hw/ppc/pnv_core.c | 78 +-
4 files changed, 94 insertions(+), 2 deletions(-)
diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h
index 77ef00f47a72..c829a18aa9c6 100644
--- a/include/hw/ppc/pnv_core.h
+++ b/include/hw/ppc/pnv_core.h
@@ -65,6 +65,9 @@ struct PnvQuadClass {
const MemoryRegionOps *xscom_ops;
uint64_t xscom_size;
+
+const MemoryRegionOps *xscom_qme_ops;
+uint64_t xscom_qme_size;
};
#define TYPE_PNV_QUAD "powernv-cpu-quad"
@@ -79,5 +82,6 @@ struct PnvQuad {
uint32_t quad_id;
MemoryRegion xscom_regs;
+MemoryRegion xscom_qme_regs;
};
#endif /* PPC_PNV_CORE_H */
diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h
index a4c9d95dc5d3..9bc64635471e 100644
--- a/include/hw/ppc/pnv_xscom.h
+++ b/include/hw/ppc/pnv_xscom.h
@@ -127,6 +127,17 @@ struct PnvXScomInterfaceClass {
#define PNV10_XSCOM_EC(proc)\
((0x2 << 16) | ((1 << (3 - (proc))) << 12))
+#define PNV10_XSCOM_QME(chiplet) \
+(PNV10_XSCOM_EQ(chiplet) | (0xE << 16))
+
+/*
+ * Make the region larger by 0x1000 (instead of starting at an offset) so the
+ * modelled addresses start from 0
+ */
+#define PNV10_XSCOM_QME_BASE(core) \
+((uint64_t) PNV10_XSCOM_QME(PNV10_XSCOM_EQ_CHIPLET(core)))
+#define PNV10_XSCOM_QME_SIZE(0x8000 + 0x1000)
+
#define PNV10_XSCOM_EQ_BASE(core) \
((uint64_t) PNV10_XSCOM_EQ(PNV10_XSCOM_EQ_CHIPLET(core)))
#define PNV10_XSCOM_EQ_SIZE0x2
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 23740f9d0733..eb54f93986df 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1685,6 +1685,9 @@ static void pnv_chip_power10_quad_realize(Pnv10Chip
*chip10, Error **errp)
pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id),
&eq->xscom_regs);
+
+pnv_xscom_add_subregion(chip, PNV10_XSCOM_QME_BASE(eq->quad_id),
+&eq->xscom_qme_regs);
}
}
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index 1f244ed181d0..09eb2bf94b9e 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -493,7 +493,67 @@ static const MemoryRegionOps pnv_quad_power10_xscom_ops = {
.endianness = DEVICE_BIG_ENDIAN,
};
-static void pnv_quad_realize(DeviceState *dev, Error **errp)
+#define P10_QME_SPWU_HYP 0x83c
+#define P10_QME_SSH_HYP 0x82c
+
+static uint64_t pnv_qme_power10_xscom_read(void *opaque, hwaddr addr,
+unsigned int width)
+{
+uint32_t offset = addr >> 3;
+uint64_t val = -1;
+
+/*
+ * Forth nibble selects the core within a quad, mask it to process read
+ * for any core.
+ */
+switch (offset & ~0xf000) {
+case P10_QME_SPWU_HYP:
+case P10_QME_SSH_HYP:
+return 0;
+default:
+qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__,
+ offset);
+}
+
+return val;
+}
+
+static void pnv_qme_power10_xscom_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned int width)
+{
+uint32_t offset = addr >> 3;
+
+switch (offset) {
+default:
+qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__,
+ offset);
+}
+}
+
+static const MemoryRegionOps pnv_qme_power10_xscom_ops = {
+.read = pnv_qme_power10_xscom_read,
+.write = pnv_qme_power10_xscom_write,
+.valid.min_access_size = 8,
+.valid.max_access_size = 8,
+.impl.min_access_size = 8,
+.impl.max_access_size = 8,
+.endianness = DEVICE_BIG_ENDIAN,
+};
+
+static void pnv_quad_power9_realize(DeviceState *dev, Error **errp)
+{
+PnvQuad *eq = PNV_QUAD(dev);
+
Re: [PATCH v2 0/5] Migration deprecated parts
Doesn't apply to master, and has no Based-on: tags telling me what to apply first. Please advise :)
Re: [PULL 07/11] tests/tcg/aarch64: Add testcases for IC IVAU and dual-mapped code
Alright, thanks. Where should I go from here? Should I send in another patch that tries to debug this? /John -Original Message- From: Peter Maydell To: John Högberg Cc: phi...@linaro.org , richard.hender...@linaro.org , qemu-devel@nongnu.org Subject: Re: [PULL 07/11] tests/tcg/aarch64: Add testcases for IC IVAU and dual-mapped code Date: Thu, 06 Jul 2023 13:54:35 +0100 On Thu, 6 Jul 2023 at 13:45, John Högberg wrote: > > > That is enough to get it to build, but then in the CI the test > > consistently fails: > > > > https://gitlab.com/pm215/qemu/-/jobs/4606447875 > > > > TEST icivau on aarch64 > > make[1]: *** [Makefile:178: run-icivau] Error 1 > > > > I'm going to drop this patch from the pullreq until we > > can figure out what's going on... > > Oops, -pthread wasn't required on my machine. > > I'm unable to reproduce the failure locally. Is it possible to strace > it > and see whether it was caused by failing to set up dual-mapped code? On the CI machines all you get is what the test case (and whatever the makefile chooses to wrap it in) writes to stdout/stderr. thanks -- PMM
Re: [PATCH v2] ppc/pnv: Add QME region for P10
On Fri, 7 Jul 2023 at 07:30, Cédric Le Goater wrote:
>
> On 7/7/23 09:12, Joel Stanley wrote:
> > The Quad Management Engine (QME) manages power related settings for its
> > quad. The xscom region is separate from the quad xscoms, therefore a new
> > region is added. The xscoms in a QME select a given core by selecting
> > the forth nibble.
> >
> > Implement dummy reads for the stop state history (SSH) and special
> > wakeup (SPWU) registers. This quietens some sxcom errors when skiboot
> > boots on p10.
> >
> > Power9 does not have a QME.
> >
> > Signed-off-by: Joel Stanley
>
> Nice, how about these now :
>
>
> [ 24.482066616,3] Could not set special wakeup on 0:0: operation timeout.
> [ 25.022003091,3] Could not set special wakeup on 0:0: operation timeout.
> [ 25.073902795,3] Could not set special wakeup on 0:0: operation timeout.
>
> [ 1593.383133413,3] Could not set special wakeup on 0:0: timeout waiting for
> SPECIAL_WKUP_DONE.
> [ 1593.435173594,3] Could not set special wakeup on 0:0: timeout waiting for
> SPECIAL_WKUP_DONE.
Yes, something like below, except hard coding is not sufficient. We
need to pass the core state into the quad model so the qme callbacks
can keep track of the wakeup state.
From: Joel Stanley
Date: Fri, 7 Jul 2023 13:37:17 +0930
Subject: [PATCH] ppc/pnv: Implement more sleep related registers
We need to get the core object into the quad callback so we can update
the sleep state.
Signed-off-by: Joel Stanley
---
hw/ppc/pnv_core.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index 09eb2bf94b9e..359b341c748f 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -179,6 +179,7 @@ static const MemoryRegionOps pnv_core_power9_xscom_ops = {
*/
#define PNV10_XSCOM_EC_CORE_THREAD_STATE0x412
+#define PNV10_XSCOM_EC_RAS_STATUS 0x454
static uint64_t pnv_core_power10_xscom_read(void *opaque, hwaddr addr,
unsigned int width)
@@ -190,6 +191,9 @@ static uint64_t pnv_core_power10_xscom_read(void
*opaque, hwaddr addr,
case PNV10_XSCOM_EC_CORE_THREAD_STATE:
val = 0;
break;
+case PNV10_XSCOM_EC_RAS_STATUS:
+val = -1;
+break;
default:
qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__,
offset);
@@ -494,7 +498,12 @@ static const MemoryRegionOps pnv_quad_power10_xscom_ops = {
};
#define P10_QME_SPWU_HYP 0x83c
+#define P10_SPWU_REQ PPC_BIT(0)
+#define P10_SPWU_DONE PPC_BIT(4)
+
#define P10_QME_SSH_HYP 0x82c
+#define P10_SSH_CORE_GATED PPC_BIT(0)
+#define P10_SSH_SPWU_DONE PPC_BIT(1)
static uint64_t pnv_qme_power10_xscom_read(void *opaque, hwaddr addr,
unsigned int width)
@@ -508,8 +517,11 @@ static uint64_t pnv_qme_power10_xscom_read(void
*opaque, hwaddr addr,
*/
switch (offset & ~0xf000) {
case P10_QME_SPWU_HYP:
+val = 0;
+break;
case P10_QME_SSH_HYP:
-return 0;
+val = P10_SSH_SPWU_DONE;
+break;
default:
qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__,
offset);
@@ -524,6 +536,8 @@ static void pnv_qme_power10_xscom_write(void
*opaque, hwaddr addr,
uint32_t offset = addr >> 3;
switch (offset) {
+case P10_QME_SSH_HYP:
+case P10_QME_SPWU_HYP:
default:
qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__,
offset);
--
2.40.1
Re: Addition of qtest_irq_intercept_out_named, or modify qtest_irq_interrupt_out?
Hi Chris,
On 7/7/23 00:10, Chris Laplante wrote:
Hello all,
I have a test case that needs to intercept a named GPIO out interrupt.
qtest_irq_intercept_out doesn't support this currently. I would like to
send a patch to add this functionality. Does anyone have a preference if
I implement it is a new function (qtest_irq_intercept_out_named), vs add
the functionality to qtest_irq_intercept_out in the form of an optional
additional parameter?
qtest_irq_intercept_out() takes a QOM path argument. Whether it is
a named IRQ or not should be irrelevant at this layer.
IMO qtest_process_command() need to be improved to handle named IRQs,
see the "/* We don't support intercept of named GPIOs yet */" comment
from commit a5f54290ce ("qdev: Implement named GPIOs"). Few days later
commit 60a79016ae ("qtest/irq: Rework IRQ interception") improved the
support. Few is missing IMO.
Regards,
Phil.
Re: [PATCH 2/2] accel/tcg: Always lock pages before translation
On 7/6/23 18:05, Richard Henderson wrote:
+++ b/accel/tcg/cpu-exec.c
@@ -531,6 +531,10 @@ static void cpu_exec_longjmp_cleanup(CPUState *cpu)
/* Non-buggy compilers preserve this; assert the correct value. */
g_assert(cpu == current_cpu);
+if (tcg_ctx->gen_tb) {
+tb_unlock_pages(tcg_ctx->gen_tb);
+tcg_ctx->gen_tb = NULL;
+}
Ho hum, fails for user-only, since there is one tcg_ctx and this cpu didn't necessarily
own it. Just a slight tweak needed, I'm sure.
r~
Re: [PATCH 1/2] accel/tcg: Split out cpu_exec_longjmp_cleanup
On 6/7/23 19:05, Richard Henderson wrote: Share the setjmp cleanup between cpu_exec_step_atomic and cpu_exec_setjmp. Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 43 +++ 1 file changed, 19 insertions(+), 24 deletions(-) Reviewed-by: Philippe Mathieu-Daudé
Re: [RFC PATCH] docs/interop: define STANDALONE protocol feature for vhost-user
"Michael S. Tsirkin" writes:
> On Tue, Jul 04, 2023 at 01:36:00PM +0100, Alex Bennée wrote:
>> Currently QEMU has to know some details about the back-end to be able
>> to setup the guest. While various parts of the setup can be delegated
>> to the backend (for example config handling) this is a very piecemeal
>> approach.
>
>> This patch suggests a new feature flag (VHOST_USER_PROTOCOL_F_STANDALONE)
>> which the back-end can advertise which allows a probe message to be
>> sent to get all the details QEMU needs to know in one message.
>
> The reason we do piecemeal is that these existing pieces can be reused
> as others evolve or fall by wayside.
Sure I have no objection in principle but we then turn code like:
if (dev->protocol_features & (1ULL <<
VHOST_USER_PROTOCOL_F_STANDALONE)) {
err = vhost_user_get_backend_specs(dev, errp);
if (err < 0) {
error_setg_errno(errp, EPROTO, "vhost_get_backend_specs
failed");
return -EPROTO;
}
}
to
if (dev->protocol_features & (1ULL << VHOST_USER_PROTOCOL_F_ID) &&
dev->protocol_features & (1ULL << VHOST_USER_PROTOCOL_F_CFGSZ) &&
dev->protocol_features & (1ULL << VHOST_USER_PROTOCOL_F_MINVQ) &&
dev->protocol_features & (1ULL << VHOST_USER_PROTOCOL_F_MAXVQ)
) {
err = vhost_user_get_virtio_id(dev, errp);
if (err < 0) {
error_setg_errno(errp, EPROTO, "vhost_get_backend_id failed");
return -EPROTO;
}
err = vhost_user_get_virtio_cfgsz(dev, errp);
if (err < 0) {
error_setg_errno(errp, EPROTO, "vhost_get_backend_cfgsz
failed");
return -EPROTO;
}
err = vhost_user_get_virtio_minvq(dev, errp);
if (err < 0) {
error_setg_errno(errp, EPROTO, "vhost_get_backend_minvq
failed");
return -EPROTO;
}
err = vhost_user_get_virtio_maxvq(dev, errp);
if (err < 0) {
error_setg_errno(errp, EPROTO, "vhost_get_backend_maxvq
failed");
return -EPROTO;
}
dev->specs.valid = true;
}
for little gain IMHO.
> For example, I can think of instances where you want to connect
> specifically to e.g. networking backend, and specify it
> on command line. Reasons could be many, e.g. for debugging,
> or to prevent connecting to wrong device on wrong channel
> (kind of like type safety).
I don't quite follow what you are trying to say here.
> What is the reason to have 1 message? startup latency?
> How about we allow pipelining several messages then?
> Will be easier.
I'm not overly worried about performance because this is all at
start-up. I am worried about excessive complexity though. We already
have quite a lot of interacting protocol messages.
>
>
>>
>> Signed-off-by: Alex Bennée
>>
>> ---
>> Initial RFC for discussion. I intend to prototype this work with QEMU
>> and one of the rust-vmm vhost-user daemons.
>> ---
>> docs/interop/vhost-user.rst | 37 +
>> hw/virtio/vhost-user.c | 8
>> 2 files changed, 45 insertions(+)
>>
>> diff --git a/docs/interop/vhost-user.rst b/docs/interop/vhost-user.rst
>> index 5a070adbc1..85b1b1583a 100644
>> --- a/docs/interop/vhost-user.rst
>> +++ b/docs/interop/vhost-user.rst
>> @@ -275,6 +275,21 @@ Inflight description
>>
>> :queue size: a 16-bit size of virtqueues
>>
>> +Backend specifications
>> +^^
>> +
>> ++---+-+++
>> +| device id | config size | min_vqs | max_vqs |
>> ++---+-+++
>> +
>> +:device id: a 32-bit value holding the VirtIO device ID
>> +
>> +:config size: a 32-bit value holding the config size (see
>> ``VHOST_USER_GET_CONFIG``)
>> +
>> +:min_vqs: a 32-bit value holding the minimum number of vqs supported
>> +
>> +:max_vqs: a 32-bit value holding the maximum number of vqs supported, must
>> be >= min_vqs
>> +
>
> looks like a weird set of info.
It's basically the information you need for -device vhost-user-device to
start-up (and what is essentially the information set by the stubs as
they start-up).
> why would we want # of vqs and not their sizes?
I thought the vring's themselves where allocated by the driver. We only
need to the number of vqs so we can allocate the tracking structures.
> why config size but not config itself?
We already have GET_CONFIG and SET_CONFIG but without knowing the size
of the config space we can't properly set it up.
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
Re: [PATCH v3 0/6] target/ppc: Few cleanups in kvm_ppc.h
On 7/7/23 09:24, Daniel Henrique Barboza wrote: Phil, I queued all patches to ppc-next. I fixed up patch 3 to not move the cpu_list macro as Greg suggested. If you're strongly attached to it let me know and I'll remove it from the queue. Sorry for missing that earlier, sure, no problem! Greg, feel free to send your R-b in patch 3 if patch 3 with this change pleases you. Daniel
Re: [PATCH 02/21] q800: add djMEMC memory controller
On 2/7/23 17:48, Mark Cave-Ayland wrote: The djMEMC controller is used to store information related to the physical memory configuration. Co-developed-by: Laurent Vivier Signed-off-by: Mark Cave-Ayland --- MAINTAINERS | 2 + hw/m68k/Kconfig | 1 + hw/m68k/q800.c | 10 +++ hw/misc/Kconfig | 3 + hw/misc/djmemc.c | 135 +++ hw/misc/meson.build | 1 + hw/misc/trace-events | 4 ++ include/hw/m68k/q800.h | 2 + include/hw/misc/djmemc.h | 30 + 9 files changed, 188 insertions(+) create mode 100644 hw/misc/djmemc.c create mode 100644 include/hw/misc/djmemc.h diff --git a/include/hw/misc/djmemc.h b/include/hw/misc/djmemc.h new file mode 100644 index 00..82d4e4a2fe --- /dev/null +++ b/include/hw/misc/djmemc.h @@ -0,0 +1,30 @@ +/* + * djMEMC, macintosh memory and interrupt controller + * (Quadra 610/650/800 & Centris 610/650) + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_MISC_DJMEMC_H +#define HW_MISC_DJMEMC_H + +#include "hw/sysbus.h" + +#define DJMEMC_SIZE0x2000 +#define DJMEMC_NUM_REGS(0x38 / sizeof(uint32_t)) + +#define DJMEMC_MAXBANKS10 MAXBANKS doesn't seem used, but not a problem. Reviewed-by: Philippe Mathieu-Daudé
Re: [PATCH 04/21] q800: implement additional machine id bits on VIA1 port A
On 2/7/23 17:48, Mark Cave-Ayland wrote: Co-developed-by: Laurent Vivier Signed-off-by: Mark Cave-Ayland --- hw/misc/mac_via.c | 14 +- 1 file changed, 13 insertions(+), 1 deletion(-) Reviewed-by: Philippe Mathieu-Daudé
Re: [PATCH 05/21] q800: add IOSB subsystem
On 2/7/23 17:48, Mark Cave-Ayland wrote:
It is needed because it defines the BIOSConfig area.
Co-developed-by: Laurent Vivier
Signed-off-by: Mark Cave-Ayland
---
MAINTAINERS| 2 +
hw/m68k/Kconfig| 1 +
hw/m68k/q800.c | 9 +++
hw/misc/Kconfig| 3 +
hw/misc/iosb.c | 137 +
hw/misc/meson.build| 1 +
hw/misc/trace-events | 4 ++
include/hw/m68k/q800.h | 2 +
include/hw/misc/iosb.h | 25
9 files changed, 184 insertions(+)
create mode 100644 hw/misc/iosb.c
create mode 100644 include/hw/misc/iosb.h
diff --git a/hw/misc/iosb.c b/hw/misc/iosb.c
new file mode 100644
index 00..4fc10bcf9f
--- /dev/null
+++ b/hw/misc/iosb.c
@@ -0,0 +1,137 @@
+/*
+ * QEMU IOSB emulation
+ *
+ * Copyright (c) 2019 Laurent Vivier
+ * Copyright (c) 2022 Mark Cave-Ayland
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "migration/vmstate.h"
+#include "hw/sysbus.h"
+#include "hw/misc/iosb.h"
+#include "trace.h"
+
+#define IOSB_SIZE 0x2000
+
+#define IOSB_CONFIG0x0
+#define IOSB_CONFIG2 0x100
+#define IOSB_SONIC_SCSI0x200
+#define IOSB_REVISION 0x300
+#define IOSB_SCSI_RESID0x400
+#define IOSB_BRIGHTNESS0x500
+#define IOSB_TIMEOUT 0x600
+
+
+static uint64_t iosb_read(void *opaque, hwaddr addr,
+ unsigned size)
+{
+IOSBState *s = IOSB(opaque);
+uint64_t val = 0;
+
+switch (addr) {
+case IOSB_CONFIG:
+case IOSB_CONFIG2:
+case IOSB_SONIC_SCSI:
+case IOSB_REVISION:
+case IOSB_SCSI_RESID:
+case IOSB_BRIGHTNESS:
+case IOSB_TIMEOUT:
+val = s->regs[addr >> 8];
+break;
+default:
+qemu_log_mask(LOG_UNIMP, "IOSB: unimplemented read addr=0x%"PRIx64
+ " val=0x%"PRIx64 " size=%d\n",
+ addr, val, size);
+}
+
+trace_iosb_read(addr, val, size);
+return val;
+}
+
+static void iosb_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned size)
+{
+IOSBState *s = IOSB(opaque);
+
+switch (addr) {
+case IOSB_CONFIG:
+case IOSB_CONFIG2:
+case IOSB_SONIC_SCSI:
+case IOSB_REVISION:
+case IOSB_SCSI_RESID:
+case IOSB_BRIGHTNESS:
+case IOSB_TIMEOUT:
+s->regs[addr >> 8] = val;
+break;
+default:
+qemu_log_mask(LOG_UNIMP, "IOSB: unimplemented write addr=0x%"PRIx64
+ " val=0x%"PRIx64 " size=%d\n",
+ addr, val, size);
+}
+
+trace_iosb_write(addr, val, size);
+}
+
+static const MemoryRegionOps iosb_mmio_ops = {
+.read = iosb_read,
+.write = iosb_write,
+.endianness = DEVICE_BIG_ENDIAN,
+.impl = {
+.min_access_size = 1,
IIUC .impl.min_access_size = 4.
Do you mean .valid.min_access_size = 1?
Otherwise,
Reviewed-by: Philippe Mathieu-Daudé
+.max_access_size = 4,
+},
+};
Re: [PATCH 10/21] q800: add easc bool machine class property to switch between ASC and EASC
On 2/7/23 17:48, Mark Cave-Ayland wrote:
This determines whether the Apple Sound Chip (ASC) is set to enhanced mode
(default) or to original mode. The real Q800 hardware used an EASC chip however
a lot of older software only works with the older ASC chip.
Adding this as a machine parameter allows QEMU to be used as an developer aid
for testing and migrating code from ASC to EASC.
Signed-off-by: Mark Cave-Ayland
---
hw/m68k/q800.c | 30 +-
include/hw/m68k/q800.h | 1 +
2 files changed, 30 insertions(+), 1 deletion(-)
+static bool q800_get_easc(Object *obj, Error **errp)
+{
+Q800MachineState *ms = Q800_MACHINE(obj);
+
+return ms->easc;
+}
Is the getter useful? Otherwise:
Reviewed-by: Philippe Mathieu-Daudé
[PATCH v2 0/4] QGA VSS Logging
Print all VSS error and trace to debugger and stderr. Konstantin Kostiuk (4): QGA VSS: Add wrapper to send log to debugger and stderr QGA VSS: Replace 'fprintf(stderr' with PRINT_DEBUG QGA VSS: Print error in err_set QGA VSS: Add log in functions begin/end qga/vss-win32/install.cpp | 46 - qga/vss-win32/meson.build | 2 +- qga/vss-win32/provider.cpp | 3 +++ qga/vss-win32/requester.cpp | 51 - qga/vss-win32/vss-debug.cpp | 31 ++ qga/vss-win32/vss-debug.h | 24 + 6 files changed, 143 insertions(+), 14 deletions(-) create mode 100644 qga/vss-win32/vss-debug.cpp create mode 100644 qga/vss-win32/vss-debug.h -- 2.34.1
[PATCH v2 2/4] QGA VSS: Replace 'fprintf(stderr' with PRINT_DEBUG
Signed-off-by: Konstantin Kostiuk
---
qga/vss-win32/install.cpp | 13 +++--
qga/vss-win32/requester.cpp | 9 +
2 files changed, 12 insertions(+), 10 deletions(-)
diff --git a/qga/vss-win32/install.cpp b/qga/vss-win32/install.cpp
index ff93b08a9e..c84c40106e 100644
--- a/qga/vss-win32/install.cpp
+++ b/qga/vss-win32/install.cpp
@@ -13,6 +13,7 @@
#include "qemu/osdep.h"
#include "vss-common.h"
+#include "vss-debug.h"
#ifdef HAVE_VSS_SDK
#include
#else
@@ -54,7 +55,7 @@ void errmsg(DWORD err, const char *text)
FORMAT_MESSAGE_FROM_SYSTEM | FORMAT_MESSAGE_IGNORE_INSERTS,
NULL, err, MAKELANGID(LANG_NEUTRAL, SUBLANG_DEFAULT),
(char *)&msg, 0, NULL);
-fprintf(stderr, "%.*s. (Error: %lx) %s\n", len, text, err, msg);
+qga_debug("%.*s. (Error: %lx) %s\n", len, text, err, msg);
LocalFree(msg);
}
@@ -219,7 +220,7 @@ static HRESULT QGAProviderRemove(ICatalogCollection *coll,
int i, void *arg)
{
HRESULT hr;
-fprintf(stderr, "Removing COM+ Application: %s\n", QGA_PROVIDER_NAME);
+qga_debug("Removing COM+ Application: %s", QGA_PROVIDER_NAME);
chk(coll->Remove(i));
out:
return hr;
@@ -304,9 +305,9 @@ STDAPI COMRegister(void)
}
strcpy(tlbPath, dllPath);
strcpy(tlbPath+n-3, "tlb");
-fprintf(stderr, "Registering " QGA_PROVIDER_NAME ":\n");
-fprintf(stderr, " %s\n", dllPath);
-fprintf(stderr, " %s\n", tlbPath);
+qga_debug("Registering " QGA_PROVIDER_NAME ":");
+qga_debug(" %s", dllPath);
+qga_debug(" %s", tlbPath);
if (!PathFileExists(tlbPath)) {
hr = HRESULT_FROM_WIN32(ERROR_FILE_NOT_FOUND);
errmsg(hr, "Failed to lookup tlb");
@@ -517,7 +518,7 @@ namespace _com_util
}
if (mbstowcs(bstr, ascii, len) == (size_t)-1) {
-fprintf(stderr, "Failed to convert string '%s' into BSTR", ascii);
+qga_debug("Failed to convert string '%s' into BSTR", ascii);
bstr[0] = 0;
}
return bstr;
diff --git a/qga/vss-win32/requester.cpp b/qga/vss-win32/requester.cpp
index 3e998af4a8..e85b9bc633 100644
--- a/qga/vss-win32/requester.cpp
+++ b/qga/vss-win32/requester.cpp
@@ -12,6 +12,7 @@
#include "qemu/osdep.h"
#include "vss-common.h"
+#include "vss-debug.h"
#include "requester.h"
#include "install.h"
#include
@@ -59,13 +60,13 @@ STDAPI requester_init(void)
NULL, -1, NULL, NULL, RPC_C_AUTHN_LEVEL_PKT_PRIVACY,
RPC_C_IMP_LEVEL_IDENTIFY, NULL, EOAC_NONE, NULL);
if (FAILED(hr)) {
-fprintf(stderr, "failed to CoInitializeSecurity (error %lx)\n", hr);
+qga_debug("failed to CoInitializeSecurity (error %lx)", hr);
return hr;
}
hLib = LoadLibraryA("VSSAPI.DLL");
if (!hLib) {
-fprintf(stderr, "failed to load VSSAPI.DLL\n");
+qga_debug("failed to load VSSAPI.DLL");
return HRESULT_FROM_WIN32(GetLastError());
}
@@ -78,14 +79,14 @@ STDAPI requester_init(void)
#endif
);
if (!pCreateVssBackupComponents) {
-fprintf(stderr, "failed to get proc address from VSSAPI.DLL\n");
+qga_debug("failed to get proc address from VSSAPI.DLL");
return HRESULT_FROM_WIN32(GetLastError());
}
pVssFreeSnapshotProperties = (t_VssFreeSnapshotProperties)
GetProcAddress(hLib, "VssFreeSnapshotProperties");
if (!pVssFreeSnapshotProperties) {
-fprintf(stderr, "failed to get proc address from VSSAPI.DLL\n");
+qga_debug("failed to get proc address from VSSAPI.DLL");
return HRESULT_FROM_WIN32(GetLastError());
}
--
2.34.1
[PATCH v2 4/4] QGA VSS: Add log in functions begin/end
Signed-off-by: Konstantin Kostiuk
---
qga/vss-win32/install.cpp | 33 +
qga/vss-win32/provider.cpp | 3 +++
qga/vss-win32/requester.cpp | 34 ++
3 files changed, 70 insertions(+)
diff --git a/qga/vss-win32/install.cpp b/qga/vss-win32/install.cpp
index c84c40106e..0740fb0761 100644
--- a/qga/vss-win32/install.cpp
+++ b/qga/vss-win32/install.cpp
@@ -100,6 +100,8 @@ HRESULT put_Value(ICatalogObject *pObj, LPCWSTR name, T val)
/* Lookup Administrators group name from winmgmt */
static HRESULT GetAdminName(_bstr_t *name)
{
+qga_debug_begin;
+
HRESULT hr;
COMPointer pLoc;
COMPointer pSvc;
@@ -142,6 +144,7 @@ static HRESULT GetAdminName(_bstr_t *name)
}
out:
+qga_debug_end;
return hr;
}
@@ -149,6 +152,8 @@ out:
static HRESULT getNameByStringSID(
const wchar_t *sid, LPWSTR buffer, LPDWORD bufferLen)
{
+qga_debug_begin;
+
HRESULT hr = S_OK;
PSID psid = NULL;
SID_NAME_USE groupType;
@@ -168,6 +173,7 @@ static HRESULT getNameByStringSID(
LocalFree(psid);
out:
+qga_debug_end;
return hr;
}
@@ -175,6 +181,8 @@ out:
static HRESULT QGAProviderFind(
HRESULT (*found)(ICatalogCollection *, int, void *), void *arg)
{
+qga_debug_begin;
+
HRESULT hr;
COMInitializer initializer;
COMPointer pUnknown;
@@ -205,12 +213,15 @@ static HRESULT QGAProviderFind(
chk(pColl->SaveChanges(&n));
out:
+qga_debug_end;
return hr;
}
/* Count QGA VSS provider in COM+ Application Catalog */
static HRESULT QGAProviderCount(ICatalogCollection *coll, int i, void *arg)
{
+qga_debug_begin;
+
(*(int *)arg)++;
return S_OK;
}
@@ -218,28 +229,35 @@ static HRESULT QGAProviderCount(ICatalogCollection *coll,
int i, void *arg)
/* Remove QGA VSS provider from COM+ Application Catalog Collection */
static HRESULT QGAProviderRemove(ICatalogCollection *coll, int i, void *arg)
{
+qga_debug_begin;
HRESULT hr;
qga_debug("Removing COM+ Application: %s", QGA_PROVIDER_NAME);
chk(coll->Remove(i));
out:
+qga_debug_end;
return hr;
}
/* Unregister this module from COM+ Applications Catalog */
STDAPI COMUnregister(void)
{
+qga_debug_begin;
+
HRESULT hr;
DllUnregisterServer();
chk(QGAProviderFind(QGAProviderRemove, NULL));
out:
+qga_debug_end;
return hr;
}
/* Register this module to COM+ Applications Catalog */
STDAPI COMRegister(void)
{
+qga_debug_begin;
+
HRESULT hr;
COMInitializer initializer;
COMPointer pUnknown;
@@ -259,12 +277,14 @@ STDAPI COMRegister(void)
if (!g_hinstDll) {
errmsg(E_FAIL, "Failed to initialize DLL");
+qga_debug_end;
return E_FAIL;
}
chk(QGAProviderFind(QGAProviderCount, (void *)&count));
if (count) {
errmsg(E_ABORT, "QGA VSS Provider is already installed");
+qga_debug_end;
return E_ABORT;
}
@@ -355,6 +375,7 @@ out:
COMUnregister();
}
+qga_debug_end;
return hr;
}
@@ -370,6 +391,8 @@ STDAPI_(void) CALLBACK DLLCOMUnregister(HWND, HINSTANCE,
LPSTR, int)
static BOOL CreateRegistryKey(LPCTSTR key, LPCTSTR value, LPCTSTR data)
{
+qga_debug_begin;
+
HKEY hKey;
LONG ret;
DWORD size;
@@ -390,6 +413,7 @@ static BOOL CreateRegistryKey(LPCTSTR key, LPCTSTR value,
LPCTSTR data)
RegCloseKey(hKey);
out:
+qga_debug_end;
if (ret != ERROR_SUCCESS) {
/* As we cannot printf within DllRegisterServer(), show a dialog. */
errmsg_dialog(ret, "Cannot add registry", key);
@@ -401,6 +425,8 @@ out:
/* Register this dll as a VSS provider */
STDAPI DllRegisterServer(void)
{
+qga_debug_begin;
+
COMInitializer initializer;
COMPointer pVssAdmin;
HRESULT hr = E_FAIL;
@@ -479,12 +505,15 @@ out:
DllUnregisterServer();
}
+qga_debug_end;
return hr;
}
/* Unregister this VSS hardware provider from the system */
STDAPI DllUnregisterServer(void)
{
+qga_debug_begin;
+
TCHAR key[256];
COMInitializer initializer;
COMPointer pVssAdmin;
@@ -502,6 +531,7 @@ STDAPI DllUnregisterServer(void)
SHDeleteKey(HKEY_CLASSES_ROOT, key);
SHDeleteKey(HKEY_CLASSES_ROOT, g_szProgid);
+qga_debug_end;
return S_OK; /* Uninstall should never fail */
}
@@ -528,6 +558,8 @@ namespace _com_util
/* Stop QGA VSS provider service using Winsvc API */
STDAPI StopService(void)
{
+qga_debug_begin;
+
HRESULT hr = S_OK;
SC_HANDLE manager = OpenSCManager(NULL, NULL, SC_MANAGER_ALL_ACCESS);
SC_HANDLE service = NULL;
@@ -552,5 +584,6 @@ STDAPI StopService(void)
out:
CloseServiceHandle(service);
CloseServiceHandle(manager);
+qga_debug_end;
return hr;
}
diff --git a/qga/vss-win32/provider.cpp b/qga/vss-win32/provider.cpp
index 1b885e24ee..cc72e5ef1b 100644
--- a/qga/vss-win32/provider.cpp
+++ b/qga/vss-win32/provider
[PATCH v2 1/4] QGA VSS: Add wrapper to send log to debugger and stderr
Signed-off-by: Konstantin Kostiuk
---
qga/vss-win32/meson.build | 2 +-
qga/vss-win32/vss-debug.cpp | 31 +++
qga/vss-win32/vss-debug.h | 24
3 files changed, 56 insertions(+), 1 deletion(-)
create mode 100644 qga/vss-win32/vss-debug.cpp
create mode 100644 qga/vss-win32/vss-debug.h
diff --git a/qga/vss-win32/meson.build b/qga/vss-win32/meson.build
index 9483ccd3b8..0ac918910b 100644
--- a/qga/vss-win32/meson.build
+++ b/qga/vss-win32/meson.build
@@ -7,7 +7,7 @@ link_args = cc.get_supported_link_arguments([
qga_vss = shared_module(
'qga-vss',
- ['requester.cpp', 'provider.cpp', 'install.cpp', genh],
+ ['requester.cpp', 'provider.cpp', 'install.cpp', 'vss-debug.cpp', genh],
name_prefix: '',
cpp_args: ['-Wno-unknown-pragmas', '-Wno-delete-non-virtual-dtor',
'-Wno-non-virtual-dtor'],
link_args: link_args,
diff --git a/qga/vss-win32/vss-debug.cpp b/qga/vss-win32/vss-debug.cpp
new file mode 100644
index 00..de190a53f4
--- /dev/null
+++ b/qga/vss-win32/vss-debug.cpp
@@ -0,0 +1,31 @@
+/*
+ * QEMU Guest Agent VSS debug declarations
+ *
+ * Copyright (C) 2023 Red Hat Inc
+ *
+ * Authors:
+ * Konstantin Kostiuk
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "vss-common.h"
+
+void G_GNUC_PRINTF(2, 3)
+qga_debug_internal(const char *funcname, const char *fmt, ...) {
+char user_sting[512] = {0};
+char full_string[640] = {0};
+
+va_list args;
+va_start(args, fmt);
+vsnprintf(user_sting, 512, fmt, args);
+va_end(args);
+
+snprintf(full_string, 640, QGA_PROVIDER_NAME "[%lu]: %s %s\n",
+ GetCurrentThreadId(), funcname, user_sting);
+
+OutputDebugString(full_string);
+fprintf(stderr, "%s", full_string);
+}
diff --git a/qga/vss-win32/vss-debug.h b/qga/vss-win32/vss-debug.h
new file mode 100644
index 00..4a15049a62
--- /dev/null
+++ b/qga/vss-win32/vss-debug.h
@@ -0,0 +1,24 @@
+/*
+ * QEMU Guest Agent VSS debug declarations
+ *
+ * Copyright (C) 2023 Red Hat Inc
+ *
+ * Authors:
+ * Konstantin Kostiuk
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include
+
+#ifndef VSS_DEBUG_H
+#define VSS_DEBUG_H
+
+void qga_debug_internal(const char *funcname, const char *fmt, ...);
+
+#define qga_debug(fmt, ...) qga_debug_internal(__func__, fmt, ## __VA_ARGS__)
+#define qga_debug_begin qga_debug("begin")
+#define qga_debug_end qga_debug("end")
+
+#endif
--
2.34.1
[PATCH v2 3/4] QGA VSS: Print error in err_set
Signed-off-by: Konstantin Kostiuk
---
qga/vss-win32/requester.cpp | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/qga/vss-win32/requester.cpp b/qga/vss-win32/requester.cpp
index e85b9bc633..f3eafacfc1 100644
--- a/qga/vss-win32/requester.cpp
+++ b/qga/vss-win32/requester.cpp
@@ -26,9 +26,11 @@
#define DEFAULT_VSS_BACKUP_TYPE VSS_BT_FULL
-#define err_set(e, err, fmt, ...) \
-((e)->error_setg_win32_wrapper((e)->errp, __FILE__, __LINE__, __func__, \
- err, fmt, ## __VA_ARGS__))
+#define err_set(e, err, fmt, ...) { \
+(e)->error_setg_win32_wrapper((e)->errp, __FILE__, __LINE__, __func__, \
+ err, fmt, ## __VA_ARGS__); \
+qga_debug(fmt, ## __VA_ARGS__); \
+}
/* Bad idea, works only when (e)->errp != NULL: */
#define err_is_set(e) ((e)->errp && *(e)->errp)
/* To lift this restriction, error_propagate(), like we do in QEMU code */
--
2.34.1
Re: [PATCH v2 1/4] QGA VSS: Add wrapper to send log to debugger and stderr
On 7/7/23 10:31, Konstantin Kostiuk wrote:
Signed-off-by: Konstantin Kostiuk
---
qga/vss-win32/meson.build | 2 +-
qga/vss-win32/vss-debug.cpp | 31 +++
qga/vss-win32/vss-debug.h | 24
3 files changed, 56 insertions(+), 1 deletion(-)
create mode 100644 qga/vss-win32/vss-debug.cpp
create mode 100644 qga/vss-win32/vss-debug.h
diff --git a/qga/vss-win32/meson.build b/qga/vss-win32/meson.build
index 9483ccd3b8..0ac918910b 100644
--- a/qga/vss-win32/meson.build
+++ b/qga/vss-win32/meson.build
@@ -7,7 +7,7 @@ link_args = cc.get_supported_link_arguments([
qga_vss = shared_module(
'qga-vss',
- ['requester.cpp', 'provider.cpp', 'install.cpp', genh],
+ ['requester.cpp', 'provider.cpp', 'install.cpp', 'vss-debug.cpp', genh],
name_prefix: '',
cpp_args: ['-Wno-unknown-pragmas', '-Wno-delete-non-virtual-dtor',
'-Wno-non-virtual-dtor'],
link_args: link_args,
diff --git a/qga/vss-win32/vss-debug.cpp b/qga/vss-win32/vss-debug.cpp
new file mode 100644
index 00..de190a53f4
--- /dev/null
+++ b/qga/vss-win32/vss-debug.cpp
@@ -0,0 +1,31 @@
+/*
+ * QEMU Guest Agent VSS debug declarations
+ *
+ * Copyright (C) 2023 Red Hat Inc
+ *
+ * Authors:
+ * Konstantin Kostiuk
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "vss-common.h"
+
+void G_GNUC_PRINTF(2, 3)
"G_GNUC_PRINTF(2, 3)" attribute goes with the declaration,
not the definition ...
+qga_debug_internal(const char *funcname, const char *fmt, ...) {
+char user_sting[512] = {0};
+char full_string[640] = {0};
+
+va_list args;
+va_start(args, fmt);
+vsnprintf(user_sting, 512, fmt, args);
+va_end(args);
+
+snprintf(full_string, 640, QGA_PROVIDER_NAME "[%lu]: %s %s\n",
+ GetCurrentThreadId(), funcname, user_sting);
+
+OutputDebugString(full_string);
+fprintf(stderr, "%s", full_string);
+}
diff --git a/qga/vss-win32/vss-debug.h b/qga/vss-win32/vss-debug.h
new file mode 100644
index 00..4a15049a62
--- /dev/null
+++ b/qga/vss-win32/vss-debug.h
@@ -0,0 +1,24 @@
+/*
+ * QEMU Guest Agent VSS debug declarations
+ *
+ * Copyright (C) 2023 Red Hat Inc
+ *
+ * Authors:
+ * Konstantin Kostiuk
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include
+
+#ifndef VSS_DEBUG_H
+#define VSS_DEBUG_H
+
... here: "G_GNUC_PRINTF(2, 3)".
+void qga_debug_internal(const char *funcname, const char *fmt, ...);
+
+#define qga_debug(fmt, ...) qga_debug_internal(__func__, fmt, ## __VA_ARGS__)
+#define qga_debug_begin qga_debug("begin")
+#define qga_debug_end qga_debug("end")
+
+#endif
Otherwise LGTM, thanks for the rework.
Re: [PATCH v2 2/4] QGA VSS: Replace 'fprintf(stderr' with PRINT_DEBUG
On 7/7/23 10:31, Konstantin Kostiuk wrote:
Signed-off-by: Konstantin Kostiuk
---
qga/vss-win32/install.cpp | 13 +++--
qga/vss-win32/requester.cpp | 9 +
2 files changed, 12 insertions(+), 10 deletions(-)
@@ -304,9 +305,9 @@ STDAPI COMRegister(void)
}
strcpy(tlbPath, dllPath);
strcpy(tlbPath+n-3, "tlb");
-fprintf(stderr, "Registering " QGA_PROVIDER_NAME ":\n");
-fprintf(stderr, " %s\n", dllPath);
-fprintf(stderr, " %s\n", tlbPath);
+qga_debug("Registering " QGA_PROVIDER_NAME ":");
+qga_debug(" %s", dllPath);
+qga_debug(" %s", tlbPath);
What about:
qga_debug("Registering " QGA_PROVIDER_NAME ": %s %s",
dllPath, tlbPath);
if (!PathFileExists(tlbPath)) {
hr = HRESULT_FROM_WIN32(ERROR_FILE_NOT_FOUND);
errmsg(hr, "Failed to lookup tlb");
@@ -517,7 +518,7 @@ namespace _com_util
}
if (mbstowcs(bstr, ascii, len) == (size_t)-1) {
-fprintf(stderr, "Failed to convert string '%s' into BSTR", ascii);
+qga_debug("Failed to convert string '%s' into BSTR", ascii);
bstr[0] = 0;
}
return bstr;
Re: [PATCH v2 3/4] QGA VSS: Print error in err_set
On 7/7/23 10:31, Konstantin Kostiuk wrote: Signed-off-by: Konstantin Kostiuk --- qga/vss-win32/requester.cpp | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) Reviewed-by: Philippe Mathieu-Daudé
Re: [PATCH 2/2] tests/tcg/s390x: Test single-stepping SVC
On 11/05/2023 01.02, Ilya Leoshkevich wrote:
Add a small test to prevent regressions.
Signed-off-by: Ilya Leoshkevich
---
...
diff --git a/tests/tcg/s390x/hello-s390x-asm.S
b/tests/tcg/s390x/hello-s390x-asm.S
new file mode 100644
index 000..2e9faa16047
--- /dev/null
+++ b/tests/tcg/s390x/hello-s390x-asm.S
@@ -0,0 +1,20 @@
+/*
+ * Hello, World! in assembly.
+ */
+
+.globl _start
+_start:
+
+/* puts("Hello, World!"); */
+lghi %r2,1
+larl %r3,foo
+lghi %r4,foo_end-foo
Hi Ilya!
While testing your other currently pending s390x TCG patches, I noticed that
this is failing with Clang (v16.0.1):
tests/tcg/s390x/hello-s390x-asm.S:11:10: error: invalid operand for instruction
lghi %r4,foo_end-foo
^
make[1]: *** [Makefile:121: hello-s390x-asm] Error 1
Any ideas how to fix this?
Thomas
Re: [PATCH v5 3/3] ppc: Enable 2nd DAWR support on p10
Hi David, All, I am revisiting/reviving this patch. On 5/5/21 11:20, David Gibson wrote: On Wed, Apr 21, 2021 at 11:50:40AM +0530, Ravi Bangoria wrote: Hi David, On 4/19/21 10:23 AM, David Gibson wrote: On Mon, Apr 12, 2021 at 05:14:33PM +0530, Ravi Bangoria wrote: Since we have released versions with POWER10 support, but no DAWR1, in theory we need a capability so new qemu with old machine types don't gain guest visible features that the same machine types on older qemus had. Except.. there's a loophole we might use to sidestep that. The current POWER10 CPU modelled in qemu is a DD1 - which I strongly suspect will never appear outside of IBM. I'm pretty sure we want to replace that with a DD2. While the modelled CPU is DD1, I think it's pretty reasonable to say our POWER10 support hasn't yet stabilized, and it would therefore be ok to simply add DAWR1 on POWER10 unconditionally, as long as we do it before we switch over to DD2. As POWER10 DD2 switch over has already happened, the need for new/separate capability for dawr1 still holds. So, I am keeping it as is. Posting the next version after rebase. Thanks, Shivaprasad I'm wondering if we're actually just better off setting the pa feature just based on the guest CPU model. TCG will be broken if you try to use it, but then, it already is. AFAIK there's no inherent reason we couldn't implement DAWR support in TCG, it's just never been worth the trouble. Correct. Probably there is no practical usecase for DAWR in TCG mode. Thanks, Ravi
[PATCH v6] ppc: Enable 2nd DAWR support on p10
From: Ravi Bangoria
As per the PAPR, bit 0 of byte 64 in pa-features property
indicates availability of 2nd DAWR registers. i.e. If this bit is set, 2nd
DAWR is present, otherwise not. Use KVM_CAP_PPC_DAWR1 capability to find
whether kvm supports 2nd DAWR or not. If it's supported, allow user to set
the pa-feature bit in guest DT using cap-dawr1 machine capability. Though,
watchpoint on powerpc TCG guest is not supported and thus 2nd DAWR is not
enabled for TCG mode.
Signed-off-by: Ravi Bangoria
Reviewed-by: Greg Kurz
Reviewed-by: Cédric Le Goater
Signed-off-by: Shivaprasad G Bhat
---
Changelog:
v5:
https://lore.kernel.org/all/20210412114433.129702-1-ravi.bango...@linux.ibm.com/
v5->v6:
- The other patches in the original series already merged.
- Rebased to the top of the tree. So, the gen_spr_book3s_310_dbg() is renamed
to register_book3s_310_dbg_sprs() and moved to cpu_init.c accordingly.
- No functional changes.
v4:
https://lore.kernel.org/r/20210406053833.282907-1-ravi.bango...@linux.ibm.com
v3->v4:
- Make error message more proper.
v3: https://lore.kernel.org/r/20210330095350.36309-1-ravi.bango...@linux.ibm.com
v3->v4:
- spapr_dt_pa_features(): POWER10 processor is compatible with 3.0
(PCR_COMPAT_3_00). No need to ppc_check_compat(3_10) for now as
ppc_check_compati(3_00) will also be true. ppc_check_compat(3_10)
can be added while introducing pa_features_310 in future.
- Use error_append_hint() for hints. Also add ERRP_GUARD().
- Add kvmppc_set_cap_dawr1() stub function for CONFIG_KVM=n.
v2:
https://lore.kernel.org/r/20210329041906.213991-1-ravi.bango...@linux.ibm.com
v2->v3:
- Don't introduce pa_features_310[], instead, reuse pa_features_300[]
for 3.1 guests, as there is no difference between initial values of
them atm.
- Call gen_spr_book3s_310_dbg() from init_proc_POWER10() instead of
init_proc_POWER8(). Also, Don't call gen_spr_book3s_207_dbg() from
gen_spr_book3s_310_dbg() as init_proc_POWER10() already calls it.
v1:
https://lore.kernel.org/r/20200723104220.314671-1-ravi.bango...@linux.ibm.com
v1->v2:
- Introduce machine capability cap-dawr1 to enable/disable
the feature. By default, 2nd DAWR is OFF for guests even
when host kvm supports it. User has to manually enable it
with -machine cap-dawr1=on if he wishes to use it.
- Split the header file changes into separate patch. (Sync
headers from v5.12-rc3)
[1] https://git.kernel.org/torvalds/c/bd1de1a0e6eff
hw/ppc/spapr.c |7 ++-
hw/ppc/spapr_caps.c| 32
include/hw/ppc/spapr.h |6 +-
target/ppc/cpu.h |2 ++
target/ppc/cpu_init.c | 15 +++
target/ppc/kvm.c | 12
target/ppc/kvm_ppc.h | 12
7 files changed, 84 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 54dbfd7fe9..1e54e0c719 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -241,7 +241,7 @@ static void spapr_dt_pa_features(SpaprMachineState *spapr,
0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
/* 54: DecFP, 56: DecI, 58: SHA */
0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
-/* 60: NM atomic, 62: RNG */
+/* 60: NM atomic, 62: RNG, 64: DAWR1 (ISA 3.1) */
0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
};
uint8_t *pa_features = NULL;
@@ -282,6 +282,9 @@ static void spapr_dt_pa_features(SpaprMachineState *spapr,
* in pa-features. So hide it from them. */
pa_features[40 + 2] &= ~0x80; /* Radix MMU */
}
+if (spapr_get_cap(spapr, SPAPR_CAP_DAWR1)) {
+pa_features[66] |= 0x80;
+}
_FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
}
@@ -2084,6 +2087,7 @@ static const VMStateDescription vmstate_spapr = {
&vmstate_spapr_cap_fwnmi,
&vmstate_spapr_fwnmi,
&vmstate_spapr_cap_rpt_invalidate,
+&vmstate_spapr_cap_dawr1,
NULL
}
};
@@ -4683,6 +4687,7 @@ static void spapr_machine_class_init(ObjectClass *oc,
void *data)
smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON;
smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON;
smc->default_caps.caps[SPAPR_CAP_RPT_INVALIDATE] = SPAPR_CAP_OFF;
+smc->default_caps.caps[SPAPR_CAP_DAWR1] = SPAPR_CAP_OFF;
/*
* This cap specifies whether the AIL 3 mode for
diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c
index 5a0755d34f..2f2cf4a250 100644
--- a/hw/ppc/spapr_caps.c
+++ b/hw/ppc/spapr_caps.c
@@ -655,6 +655,28 @@ static void cap_ail_mode_3_apply(SpaprMachineState *spapr,
}
}
+static void cap_dawr1_apply(SpaprMachineState *spapr, uint8_t val,
+ Error **errp)
+{
+ERRP_GUARD();
+if (!val) {
+return; /* Disable by default */
+}
+
+if (tcg_enabled()) {
+error_setg(errp, "DAWR1 not supported in TCG.");
+error_append_hint(errp, "Tr
[PULL 04/15] hw/net: i82596: Remove the logic of padding short frames in the receive path
From: Bin Meng
Now that we have implemented unified short frames padding in the
QEMU networking codes, remove the same logic in the NIC codes.
Signed-off-by: Bin Meng
Signed-off-by: Jason Wang
---
hw/net/i82596.c | 18 --
1 file changed, 18 deletions(-)
diff --git a/hw/net/i82596.c b/hw/net/i82596.c
index ec21e26..ab26f8b 100644
--- a/hw/net/i82596.c
+++ b/hw/net/i82596.c
@@ -72,10 +72,6 @@ enum commands {
#define I596_EOF0x8000
#define SIZE_MASK 0x3fff
-#define ETHER_TYPE_LEN 2
-#define VLAN_TCI_LEN 2
-#define VLAN_HLEN (ETHER_TYPE_LEN + VLAN_TCI_LEN)
-
/* various flags in the chip config registers */
#define I596_PREFETCH (s->config[0] & 0x80)
#define I596_PROMISC(s->config[8] & 0x01)
@@ -488,8 +484,6 @@ bool i82596_can_receive(NetClientState *nc)
return true;
}
-#define MIN_BUF_SIZE 60
-
ssize_t i82596_receive(NetClientState *nc, const uint8_t *buf, size_t sz)
{
I82596State *s = qemu_get_nic_opaque(nc);
@@ -500,7 +494,6 @@ ssize_t i82596_receive(NetClientState *nc, const uint8_t
*buf, size_t sz)
size_t bufsz = sz; /* length of data in buf */
uint32_t crc;
uint8_t *crc_ptr;
-uint8_t buf1[MIN_BUF_SIZE + VLAN_HLEN];
static const uint8_t broadcast_macaddr[6] = {
0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
@@ -583,17 +576,6 @@ ssize_t i82596_receive(NetClientState *nc, const uint8_t
*buf, size_t sz)
}
}
-/* if too small buffer, then expand it */
-if (len < MIN_BUF_SIZE + VLAN_HLEN) {
-memcpy(buf1, buf, len);
-memset(buf1 + len, 0, MIN_BUF_SIZE + VLAN_HLEN - len);
-buf = buf1;
-if (len < MIN_BUF_SIZE) {
-len = MIN_BUF_SIZE;
-}
-bufsz = len;
-}
-
/* Calculate the ethernet checksum (4 bytes) */
len += 4;
crc = cpu_to_be32(crc32(~0, buf, sz));
--
2.7.4
[PULL 03/15] hw/net: vmxnet3: Remove the logic of padding short frames in the receive path
From: Bin Meng
Now that we have implemented unified short frames padding in the
QEMU networking codes, remove the same logic in the NIC codes.
This actually reverts commit 40a87c6c9b11ef9c14e0301f76abf0eb2582f08e.
Signed-off-by: Bin Meng
Signed-off-by: Jason Wang
---
hw/net/vmxnet3.c | 10 --
1 file changed, 10 deletions(-)
diff --git a/hw/net/vmxnet3.c b/hw/net/vmxnet3.c
index 18b9edf..5dfacb1 100644
--- a/hw/net/vmxnet3.c
+++ b/hw/net/vmxnet3.c
@@ -40,7 +40,6 @@
#define PCI_DEVICE_ID_VMWARE_VMXNET3_REVISION 0x1
#define VMXNET3_MSIX_BAR_SIZE 0x2000
-#define MIN_BUF_SIZE 60
/* Compatibility flags for migration */
#define VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT 0
@@ -1977,7 +1976,6 @@ vmxnet3_receive(NetClientState *nc, const uint8_t *buf,
size_t size)
{
VMXNET3State *s = qemu_get_nic_opaque(nc);
size_t bytes_indicated;
-uint8_t min_buf[MIN_BUF_SIZE];
if (!vmxnet3_can_receive(nc)) {
VMW_PKPRN("Cannot receive now");
@@ -1990,14 +1988,6 @@ vmxnet3_receive(NetClientState *nc, const uint8_t *buf,
size_t size)
size -= sizeof(struct virtio_net_hdr);
}
-/* Pad to minimum Ethernet frame length */
-if (size < sizeof(min_buf)) {
-memcpy(min_buf, buf, size);
-memset(&min_buf[size], 0, sizeof(min_buf) - size);
-buf = min_buf;
-size = sizeof(min_buf);
-}
-
net_rx_pkt_set_packet_type(s->rx_pkt,
get_eth_packet_type(PKT_GET_ETH_HDR(buf)));
--
2.7.4
[PULL 12/15] net: socket: move fd type checking to its own function
From: Laurent Vivier
Reviewed-by: David Gibson
Signed-off-by: Laurent Vivier
Signed-off-by: Jason Wang
---
net/socket.c | 28
1 file changed, 20 insertions(+), 8 deletions(-)
diff --git a/net/socket.c b/net/socket.c
index 24dcaa5..6b1f0fe 100644
--- a/net/socket.c
+++ b/net/socket.c
@@ -446,16 +446,32 @@ static NetSocketState
*net_socket_fd_init_stream(NetClientState *peer,
return s;
}
+static int net_socket_fd_check(int fd, Error **errp)
+{
+int so_type, optlen = sizeof(so_type);
+
+if (getsockopt(fd, SOL_SOCKET, SO_TYPE, (char *)&so_type,
+(socklen_t *)&optlen) < 0) {
+error_setg(errp, "can't get socket option SO_TYPE");
+return -1;
+}
+if (so_type != SOCK_DGRAM && so_type != SOCK_STREAM) {
+error_setg(errp, "socket type=%d for fd=%d must be either"
+ " SOCK_DGRAM or SOCK_STREAM", so_type, fd);
+return -1;
+}
+return so_type;
+}
+
static NetSocketState *net_socket_fd_init(NetClientState *peer,
const char *model, const char *name,
int fd, int is_connected,
const char *mc, Error **errp)
{
-int so_type = -1, optlen=sizeof(so_type);
+int so_type;
-if(getsockopt(fd, SOL_SOCKET, SO_TYPE, (char *)&so_type,
-(socklen_t *)&optlen)< 0) {
-error_setg(errp, "can't get socket option SO_TYPE");
+so_type = net_socket_fd_check(fd, errp);
+if (so_type < 0) {
close(fd);
return NULL;
}
@@ -465,10 +481,6 @@ static NetSocketState *net_socket_fd_init(NetClientState
*peer,
mc, errp);
case SOCK_STREAM:
return net_socket_fd_init_stream(peer, model, name, fd, is_connected);
-default:
-error_setg(errp, "socket type=%d for fd=%d must be either"
- " SOCK_DGRAM or SOCK_STREAM", so_type, fd);
-close(fd);
}
return NULL;
}
--
2.7.4
[PULL 02/15] hw/net: e1000: Remove the logic of padding short frames in the receive path
From: Bin Meng
Now that we have implemented unified short frames padding in the
QEMU networking codes, remove the same logic in the NIC codes.
This actually reverts commit 78aeb23eded2d0b765bf9145c71f80025b568acd.
Signed-off-by: Bin Meng
Signed-off-by: Jason Wang
---
hw/net/e1000.c | 11 +--
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git a/hw/net/e1000.c b/hw/net/e1000.c
index aae5f0b..093c2d4 100644
--- a/hw/net/e1000.c
+++ b/hw/net/e1000.c
@@ -888,7 +888,6 @@ e1000_receive_iov(NetClientState *nc, const struct iovec
*iov, int iovcnt)
uint16_t vlan_special = 0;
uint8_t vlan_status = 0;
uint8_t min_buf[ETH_ZLEN];
-struct iovec min_iov;
uint8_t *filter_buf = iov->iov_base;
size_t size = iov_size(iov, iovcnt);
size_t iov_ofs = 0;
@@ -905,15 +904,7 @@ e1000_receive_iov(NetClientState *nc, const struct iovec
*iov, int iovcnt)
return 0;
}
-/* Pad to minimum Ethernet frame length */
-if (size < sizeof(min_buf)) {
-iov_to_buf(iov, iovcnt, 0, min_buf, size);
-memset(&min_buf[size], 0, sizeof(min_buf) - size);
-min_iov.iov_base = filter_buf = min_buf;
-min_iov.iov_len = size = sizeof(min_buf);
-iovcnt = 1;
-iov = &min_iov;
-} else if (iov->iov_len < MAXIMUM_ETHERNET_HDR_LEN) {
+if (iov->iov_len < MAXIMUM_ETHERNET_HDR_LEN) {
/* This is very unlikely, but may happen. */
iov_to_buf(iov, iovcnt, 0, min_buf, MAXIMUM_ETHERNET_HDR_LEN);
filter_buf = min_buf;
--
2.7.4
[PULL 06/15] hw/net: pcnet: Remove the logic of padding short frames in the receive path
From: Bin Meng
Now that we have implemented unified short frames padding in the
QEMU networking codes, remove the same logic in the NIC codes.
Signed-off-by: Bin Meng
Signed-off-by: Jason Wang
---
hw/net/pcnet.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/hw/net/pcnet.c b/hw/net/pcnet.c
index d456094..02828ae 100644
--- a/hw/net/pcnet.c
+++ b/hw/net/pcnet.c
@@ -987,7 +987,6 @@ ssize_t pcnet_receive(NetClientState *nc, const uint8_t
*buf, size_t size_)
{
PCNetState *s = qemu_get_nic_opaque(nc);
int is_padr = 0, is_bcast = 0, is_ladr = 0;
-uint8_t buf1[60];
int remaining;
int crc_err = 0;
size_t size = size_;
@@ -1000,14 +999,6 @@ ssize_t pcnet_receive(NetClientState *nc, const uint8_t
*buf, size_t size_)
printf("pcnet_receive size=%zu\n", size);
#endif
-/* if too small buffer, then expand it */
-if (size < MIN_BUF_SIZE) {
-memcpy(buf1, buf, size);
-memset(buf1 + size, 0, MIN_BUF_SIZE - size);
-buf = buf1;
-size = MIN_BUF_SIZE;
-}
-
if (CSR_PROM(s)
|| (is_padr=padr_match(s, buf, size))
|| (is_bcast=padr_bcast(s, buf, size))
--
2.7.4
[PULL 11/15] net: socket: prepare to cleanup net_init_socket()
From: Laurent Vivier
Use directly net_socket_fd_init_stream() and net_socket_fd_init_dgram()
when the socket type is already known.
Reviewed-by: David Gibson
Signed-off-by: Laurent Vivier
Signed-off-by: Jason Wang
---
net/socket.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/net/socket.c b/net/socket.c
index ba6e5b0..24dcaa5 100644
--- a/net/socket.c
+++ b/net/socket.c
@@ -587,7 +587,7 @@ static int net_socket_connect_init(NetClientState *peer,
break;
}
}
-s = net_socket_fd_init(peer, model, name, fd, connected, NULL, errp);
+s = net_socket_fd_init_stream(peer, model, name, fd, connected);
if (!s) {
return -1;
}
@@ -629,7 +629,7 @@ static int net_socket_mcast_init(NetClientState *peer,
return -1;
}
-s = net_socket_fd_init(peer, model, name, fd, 0, NULL, errp);
+s = net_socket_fd_init_dgram(peer, model, name, fd, 0, NULL, errp);
if (!s) {
return -1;
}
@@ -683,7 +683,7 @@ static int net_socket_udp_init(NetClientState *peer,
}
qemu_socket_set_nonblock(fd);
-s = net_socket_fd_init(peer, model, name, fd, 0, NULL, errp);
+s = net_socket_fd_init_dgram(peer, model, name, fd, 0, NULL, errp);
if (!s) {
return -1;
}
--
2.7.4
[PULL 13/15] net: socket: remove net_init_socket()
From: Laurent Vivier
Move the file descriptor type checking before doing anything with it.
If it's not usable, don't close it as it could be in use by another
part of QEMU, only fail and report an error.
Reviewed-by: David Gibson
Signed-off-by: Laurent Vivier
Signed-off-by: Jason Wang
---
net/socket.c | 43 +--
1 file changed, 17 insertions(+), 26 deletions(-)
diff --git a/net/socket.c b/net/socket.c
index 6b1f0fe..8e3702e 100644
--- a/net/socket.c
+++ b/net/socket.c
@@ -463,28 +463,6 @@ static int net_socket_fd_check(int fd, Error **errp)
return so_type;
}
-static NetSocketState *net_socket_fd_init(NetClientState *peer,
- const char *model, const char *name,
- int fd, int is_connected,
- const char *mc, Error **errp)
-{
-int so_type;
-
-so_type = net_socket_fd_check(fd, errp);
-if (so_type < 0) {
-close(fd);
-return NULL;
-}
-switch(so_type) {
-case SOCK_DGRAM:
-return net_socket_fd_init_dgram(peer, model, name, fd, is_connected,
-mc, errp);
-case SOCK_STREAM:
-return net_socket_fd_init_stream(peer, model, name, fd, is_connected);
-}
-return NULL;
-}
-
static void net_socket_accept(void *opaque)
{
NetSocketState *s = opaque;
@@ -728,21 +706,34 @@ int net_init_socket(const Netdev *netdev, const char
*name,
}
if (sock->fd) {
-int fd, ret;
+int fd, ret, so_type;
fd = monitor_fd_param(monitor_cur(), sock->fd, errp);
if (fd == -1) {
return -1;
}
+so_type = net_socket_fd_check(fd, errp);
+if (so_type < 0) {
+return -1;
+}
ret = qemu_socket_try_set_nonblock(fd);
if (ret < 0) {
error_setg_errno(errp, -ret, "%s: Can't use file descriptor %d",
name, fd);
return -1;
}
-if (!net_socket_fd_init(peer, "socket", name, fd, 1, sock->mcast,
-errp)) {
-return -1;
+switch (so_type) {
+case SOCK_DGRAM:
+if (!net_socket_fd_init_dgram(peer, "socket", name, fd, 1,
+ sock->mcast, errp)) {
+return -1;
+}
+break;
+case SOCK_STREAM:
+if (!net_socket_fd_init_stream(peer, "socket", name, fd, 1)) {
+return -1;
+}
+break;
}
return 0;
}
--
2.7.4
[PULL 09/15] hw/net: sunhme: Remove the logic of padding short frames in the receive path
From: Bin Meng
Now that we have implemented unified short frames padding in the
QEMU networking codes, remove the same logic in the NIC codes.
Signed-off-by: Bin Meng
Signed-off-by: Jason Wang
---
hw/net/sunhme.c | 11 ---
1 file changed, 11 deletions(-)
diff --git a/hw/net/sunhme.c b/hw/net/sunhme.c
index 1f3d801..391d26f 100644
--- a/hw/net/sunhme.c
+++ b/hw/net/sunhme.c
@@ -714,8 +714,6 @@ static inline void sunhme_set_rx_ring_nr(SunHMEState *s,
int i)
s->erxregs[HME_ERXI_RING >> 2] = ring;
}
-#define MIN_BUF_SIZE 60
-
static ssize_t sunhme_receive(NetClientState *nc, const uint8_t *buf,
size_t size)
{
@@ -724,7 +722,6 @@ static ssize_t sunhme_receive(NetClientState *nc, const
uint8_t *buf,
dma_addr_t rb, addr;
uint32_t intstatus, status, buffer, buffersize, sum;
uint16_t csum;
-uint8_t buf1[60];
int nr, cr, len, rxoffset, csum_offset;
trace_sunhme_rx_incoming(size);
@@ -775,14 +772,6 @@ static ssize_t sunhme_receive(NetClientState *nc, const
uint8_t *buf,
trace_sunhme_rx_filter_accept();
-/* If too small buffer, then expand it */
-if (size < MIN_BUF_SIZE) {
-memcpy(buf1, buf, size);
-memset(buf1 + size, 0, MIN_BUF_SIZE - size);
-buf = buf1;
-size = MIN_BUF_SIZE;
-}
-
rb = s->erxregs[HME_ERXI_RING >> 2] & HME_ERXI_RING_ADDR;
nr = sunhme_get_rx_ring_count(s);
cr = sunhme_get_rx_ring_nr(s);
--
2.7.4
[PULL 07/15] hw/net: rtl8139: Remove the logic of padding short frames in the receive path
From: Bin Meng
Now that we have implemented unified short frames padding in the
QEMU networking codes, remove the same logic in the NIC codes.
Signed-off-by: Bin Meng
Signed-off-by: Jason Wang
---
hw/net/rtl8139.c | 12
1 file changed, 12 deletions(-)
diff --git a/hw/net/rtl8139.c b/hw/net/rtl8139.c
index 5f1a4d3..b4df75b 100644
--- a/hw/net/rtl8139.c
+++ b/hw/net/rtl8139.c
@@ -826,7 +826,6 @@ static ssize_t rtl8139_do_receive(NetClientState *nc, const
uint8_t *buf, size_t
uint32_t packet_header = 0;
-uint8_t buf1[MIN_BUF_SIZE + VLAN_HLEN];
static const uint8_t broadcast_macaddr[6] =
{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
@@ -938,17 +937,6 @@ static ssize_t rtl8139_do_receive(NetClientState *nc,
const uint8_t *buf, size_t
}
}
-/* if too small buffer, then expand it
- * Include some tailroom in case a vlan tag is later removed. */
-if (size < MIN_BUF_SIZE + VLAN_HLEN) {
-memcpy(buf1, buf, size);
-memset(buf1 + size, 0, MIN_BUF_SIZE + VLAN_HLEN - size);
-buf = buf1;
-if (size < MIN_BUF_SIZE) {
-size = MIN_BUF_SIZE;
-}
-}
-
if (rtl8139_cp_receiver_enabled(s))
{
if (!rtl8139_cp_rx_valid(s)) {
--
2.7.4
[PULL 14/15] e1000e: Add ICR clearing by corresponding IMS bit
From: Akihiko Odaki
The datasheet does not say what happens when interrupt was asserted
(ICR.INT_ASSERT=1) and auto mask is *not* active.
However, section of 13.3.27 the PCIe* GbE Controllers Open Source
Software Developer’s Manual, which were written for older devices,
namely 631xESB/632xESB, 82563EB/82564EB, 82571EB/82572EI &
82573E/82573V/82573L, does say:
> If IMS = 0b, then the ICR register is always clear-on-read. If IMS is
> not 0b, but some ICR bit is set where the corresponding IMS bit is not
> set, then a read does not clear the ICR register. For example, if
> IMS = 10101010b and ICR = 01010101b, then a read to the ICR register
> does not clear it. If IMS = 10101010b and ICR = 0101011b, then a read
> to the ICR register clears it entirely (ICR.INT_ASSERTED = 1b).
Linux does no longer activate auto mask since commit
0a8047ac68e50e4ccbadcfc6b6b070805b976885 and the real hardware clears
ICR even in such a case so we also should do so.
Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=1707441
Signed-off-by: Andrew Melnychenko
Signed-off-by: Akihiko Odaki
Signed-off-by: Jason Wang
---
hw/net/e1000e_core.c | 38 --
hw/net/trace-events | 1 +
2 files changed, 33 insertions(+), 6 deletions(-)
diff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c
index 9f185d0..f8aeafa 100644
--- a/hw/net/e1000e_core.c
+++ b/hw/net/e1000e_core.c
@@ -2604,12 +2604,38 @@ e1000e_mac_icr_read(E1000ECore *core, int index)
e1000e_lower_interrupts(core, ICR, 0x);
}
-if ((core->mac[ICR] & E1000_ICR_ASSERTED) &&
-(core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) {
-trace_e1000e_irq_icr_clear_iame();
-e1000e_lower_interrupts(core, ICR, 0x);
-trace_e1000e_irq_icr_process_iame();
-e1000e_lower_interrupts(core, IMS, core->mac[IAM]);
+if (core->mac[ICR] & E1000_ICR_ASSERTED) {
+if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME) {
+trace_e1000e_irq_icr_clear_iame();
+e1000e_lower_interrupts(core, ICR, 0x);
+trace_e1000e_irq_icr_process_iame();
+e1000e_lower_interrupts(core, IMS, core->mac[IAM]);
+}
+
+/*
+ * The datasheet does not say what happens when interrupt was asserted
+ * (ICR.INT_ASSERT=1) and auto mask is *not* active.
+ * However, section of 13.3.27 the PCIe* GbE Controllers Open Source
+ * Software Developer’s Manual, which were written for older devices,
+ * namely 631xESB/632xESB, 82563EB/82564EB, 82571EB/82572EI &
+ * 82573E/82573V/82573L, does say:
+ * > If IMS = 0b, then the ICR register is always clear-on-read. If IMS
+ * > is not 0b, but some ICR bit is set where the corresponding IMS bit
+ * > is not set, then a read does not clear the ICR register. For
+ * > example, if IMS = 10101010b and ICR = 01010101b, then a read to
the
+ * > ICR register does not clear it. If IMS = 10101010b and
+ * > ICR = 0101011b, then a read to the ICR register clears it entirely
+ * > (ICR.INT_ASSERTED = 1b).
+ *
+ * Linux does no longer activate auto mask since commit
+ * 0a8047ac68e50e4ccbadcfc6b6b070805b976885 and the real hardware
+ * clears ICR even in such a case so we also should do so.
+ */
+if (core->mac[ICR] & core->mac[IMS]) {
+trace_e1000e_irq_icr_clear_icr_bit_ims(core->mac[ICR],
+ core->mac[IMS]);
+e1000e_lower_interrupts(core, ICR, 0x);
+}
}
return ret;
diff --git a/hw/net/trace-events b/hw/net/trace-events
index e4a98b2..3eeacc5 100644
--- a/hw/net/trace-events
+++ b/hw/net/trace-events
@@ -217,6 +217,7 @@ e1000e_irq_read_ims(uint32_t ims) "Current IMS: 0x%x"
e1000e_irq_icr_clear_nonmsix_icr_read(void) "Clearing ICR on read due to non
MSI-X int"
e1000e_irq_icr_clear_zero_ims(void) "Clearing ICR on read due to zero IMS"
e1000e_irq_icr_clear_iame(void) "Clearing ICR on read due to IAME"
+e1000e_irq_icr_clear_icr_bit_ims(uint32_t icr, uint32_t ims) "Clearing ICR on
read due corresponding IMS bit: 0x%x & 0x%x"
e1000e_irq_iam_clear_eiame(uint32_t iam, uint32_t cause) "Clearing IMS due to
EIAME, IAM: 0x%X, cause: 0x%X"
e1000e_irq_icr_clear_eiac(uint32_t icr, uint32_t eiac) "Clearing ICR bits due
to EIAC, ICR: 0x%X, EIAC: 0x%X"
e1000e_irq_ims_clear_set_imc(uint32_t val) "Clearing IMS bits due to IMC write
0x%x"
--
2.7.4
[PULL 10/15] hw/net: ftgmac100: Drop the small packet check in the receive path
From: Bin Meng
Now that we have implemented unified short frames padding in the
QEMU networking codes, the small packet check logic in the receive
path is no longer needed.
Suggested-by: Cédric Le Goater
Reviewed-by: Cédric Le Goater
Signed-off-by: Bin Meng
Signed-off-by: Jason Wang
---
hw/net/ftgmac100.c | 8
1 file changed, 8 deletions(-)
diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c
index d3bf14b..702b001 100644
--- a/hw/net/ftgmac100.c
+++ b/hw/net/ftgmac100.c
@@ -968,14 +968,6 @@ static ssize_t ftgmac100_receive(NetClientState *nc, const
uint8_t *buf,
return -1;
}
-/* TODO : Pad to minimum Ethernet frame length */
-/* handle small packets. */
-if (size < 10) {
-qemu_log_mask(LOG_GUEST_ERROR, "%s: dropped frame of %zd bytes\n",
- __func__, size);
-return size;
-}
-
if (!ftgmac100_filter(s, buf, size)) {
return size;
}
--
2.7.4
[PULL 08/15] hw/net: sungem: Remove the logic of padding short frames in the receive path
From: Bin Meng
Now that we have implemented unified short frames padding in the
QEMU networking codes, remove the same logic in the NIC codes.
Signed-off-by: Bin Meng
Signed-off-by: Jason Wang
---
hw/net/sungem.c | 14 --
1 file changed, 14 deletions(-)
diff --git a/hw/net/sungem.c b/hw/net/sungem.c
index eb01520..103376c 100644
--- a/hw/net/sungem.c
+++ b/hw/net/sungem.c
@@ -550,7 +550,6 @@ static ssize_t sungem_receive(NetClientState *nc, const
uint8_t *buf,
PCIDevice *d = PCI_DEVICE(s);
uint32_t mac_crc, done, kick, max_fsize;
uint32_t fcs_size, ints, rxdma_cfg, rxmac_cfg, csum, coff;
-uint8_t smallbuf[60];
struct gem_rxd desc;
uint64_t dbase, baddr;
unsigned int rx_cond;
@@ -584,19 +583,6 @@ static ssize_t sungem_receive(NetClientState *nc, const
uint8_t *buf,
return size;
}
-/* We don't drop too small frames since we get them in qemu, we pad
- * them instead. We should probably use the min frame size register
- * but I don't want to use a variable size staging buffer and I
- * know both MacOS and Linux use the default 64 anyway. We use 60
- * here to account for the non-existent FCS.
- */
-if (size < 60) {
-memcpy(smallbuf, buf, size);
-memset(&smallbuf[size], 0, 60 - size);
-buf = smallbuf;
-size = 60;
-}
-
/* Get MAC crc */
mac_crc = net_crc32_le(buf, ETH_ALEN);
--
2.7.4
[PULL 01/15] virtio-net: correctly report maximum tx_queue_size value
From: Laurent Vivier
Maximum value for tx_queue_size depends on the backend type.
1024 for vDPA/vhost-user, 256 for all the others.
The value is returned by virtio_net_max_tx_queue_size() to set the
parameter:
n->net_conf.tx_queue_size = MIN(virtio_net_max_tx_queue_size(n),
n->net_conf.tx_queue_size);
But the parameter checking uses VIRTQUEUE_MAX_SIZE (1024).
So the parameter is silently ignored and ethtool reports a different
value than the one provided by the user.
... -netdev tap,... -device virtio-net,tx_queue_size=1024
# ethtool -g enp0s2
Ring parameters for enp0s2:
Pre-set maximums:
RX: 256
RX Mini:n/a
RX Jumbo: n/a
TX: 256
Current hardware settings:
RX: 256
RX Mini:n/a
RX Jumbo: n/a
TX: 256
... -netdev vhost-user,... -device virtio-net,tx_queue_size=2048
Invalid tx_queue_size (= 2048), must be a power of 2 between 256 and 1024
With this patch the correct maximum value is checked and displayed.
For vDPA/vhost-user:
Invalid tx_queue_size (= 2048), must be a power of 2 between 256 and 1024
For all the others:
Invalid tx_queue_size (= 512), must be a power of 2 between 256 and 256
Fixes: 2eef278b9e63 ("virtio-net: fix tx queue size for !vhost-user")
Cc: m...@redhat.com
Cc: qemu-sta...@nongnu.org
Signed-off-by: Laurent Vivier
Signed-off-by: Jason Wang
---
hw/net/virtio-net.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c
index aa421a9..04783f5 100644
--- a/hw/net/virtio-net.c
+++ b/hw/net/virtio-net.c
@@ -3630,12 +3630,12 @@ static void virtio_net_device_realize(DeviceState *dev,
Error **errp)
}
if (n->net_conf.tx_queue_size < VIRTIO_NET_TX_QUEUE_MIN_SIZE ||
-n->net_conf.tx_queue_size > VIRTQUEUE_MAX_SIZE ||
+n->net_conf.tx_queue_size > virtio_net_max_tx_queue_size(n) ||
!is_power_of_2(n->net_conf.tx_queue_size)) {
error_setg(errp, "Invalid tx_queue_size (= %" PRIu16 "), "
"must be a power of 2 between %d and %d",
n->net_conf.tx_queue_size, VIRTIO_NET_TX_QUEUE_MIN_SIZE,
- VIRTQUEUE_MAX_SIZE);
+ virtio_net_max_tx_queue_size(n));
virtio_cleanup(vdev);
return;
}
--
2.7.4
[PULL 05/15] hw/net: ne2000: Remove the logic of padding short frames in the receive path
From: Bin Meng
Now that we have implemented unified short frames padding in the
QEMU networking codes, remove the same logic in the NIC codes.
Signed-off-by: Bin Meng
Signed-off-by: Jason Wang
---
hw/net/ne2000.c | 12
1 file changed, 12 deletions(-)
diff --git a/hw/net/ne2000.c b/hw/net/ne2000.c
index 3f31d04..d79c884 100644
--- a/hw/net/ne2000.c
+++ b/hw/net/ne2000.c
@@ -167,15 +167,12 @@ static int ne2000_buffer_full(NE2000State *s)
return 0;
}
-#define MIN_BUF_SIZE 60
-
ssize_t ne2000_receive(NetClientState *nc, const uint8_t *buf, size_t size_)
{
NE2000State *s = qemu_get_nic_opaque(nc);
size_t size = size_;
uint8_t *p;
unsigned int total_len, next, avail, len, index, mcast_idx;
-uint8_t buf1[60];
static const uint8_t broadcast_macaddr[6] =
{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
@@ -213,15 +210,6 @@ ssize_t ne2000_receive(NetClientState *nc, const uint8_t
*buf, size_t size_)
}
}
-
-/* if too small buffer, then expand it */
-if (size < MIN_BUF_SIZE) {
-memcpy(buf1, buf, size);
-memset(buf1 + size, 0, MIN_BUF_SIZE - size);
-buf = buf1;
-size = MIN_BUF_SIZE;
-}
-
index = s->curpag << 8;
if (index >= NE2000_PMEM_END) {
index = s->start;
--
2.7.4
[PULL 15/15] igb: Remove obsolete workaround for Windows
From: Akihiko Odaki
I confirmed it works with Windows even without this workaround. It is
likely to be a mistake so remove it.
Fixes: 3a977deebe ("Intrdocue igb device emulation")
Signed-off-by: Akihiko Odaki
Signed-off-by: Jason Wang
---
hw/net/igb_core.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/hw/net/igb_core.c b/hw/net/igb_core.c
index d00b1ca..8b6b75c 100644
--- a/hw/net/igb_core.c
+++ b/hw/net/igb_core.c
@@ -2678,12 +2678,7 @@ static uint32_t igb_get_status(IGBCore *core, int index)
res |= E1000_STATUS_IOV_MODE;
}
-/*
- * Windows driver 12.18.9.23 resets if E1000_STATUS_GIO_MASTER_ENABLE is
- * left set after E1000_CTRL_LRST is set.
- */
-if (!(core->mac[CTRL] & E1000_CTRL_GIO_MASTER_DISABLE) &&
-!(core->mac[CTRL] & E1000_CTRL_LRST)) {
+if (!(core->mac[CTRL] & E1000_CTRL_GIO_MASTER_DISABLE)) {
res |= E1000_STATUS_GIO_MASTER_ENABLE;
}
--
2.7.4
[PULL 00/15] Net patches
The following changes since commit 97c81ef4b8e203d9620fd46e7eb77004563e3675: Merge tag 'pull-9p-20230706' of https://github.com/cschoenebeck/qemu into staging (2023-07-06 18:19:42 +0100) are available in the git repository at: https://github.com/jasowang/qemu.git tags/net-pull-request for you to fetch changes up to da9f7f7769e8e65f6423095e978f9a375e33515c: igb: Remove obsolete workaround for Windows (2023-07-07 16:35:12 +0800) Akihiko Odaki (2): e1000e: Add ICR clearing by corresponding IMS bit igb: Remove obsolete workaround for Windows Bin Meng (9): hw/net: e1000: Remove the logic of padding short frames in the receive path hw/net: vmxnet3: Remove the logic of padding short frames in the receive path hw/net: i82596: Remove the logic of padding short frames in the receive path hw/net: ne2000: Remove the logic of padding short frames in the receive path hw/net: pcnet: Remove the logic of padding short frames in the receive path hw/net: rtl8139: Remove the logic of padding short frames in the receive path hw/net: sungem: Remove the logic of padding short frames in the receive path hw/net: sunhme: Remove the logic of padding short frames in the receive path hw/net: ftgmac100: Drop the small packet check in the receive path Laurent Vivier (4): virtio-net: correctly report maximum tx_queue_size value net: socket: prepare to cleanup net_init_socket() net: socket: move fd type checking to its own function net: socket: remove net_init_socket() hw/net/e1000.c | 11 +-- hw/net/e1000e_core.c | 38 +++-- hw/net/ftgmac100.c | 8 hw/net/i82596.c | 18 -- hw/net/igb_core.c| 7 +-- hw/net/ne2000.c | 12 hw/net/pcnet.c | 9 - hw/net/rtl8139.c | 12 hw/net/sungem.c | 14 -- hw/net/sunhme.c | 11 --- hw/net/trace-events | 1 + hw/net/virtio-net.c | 4 ++-- hw/net/vmxnet3.c | 10 -- net/socket.c | 53 +++- 14 files changed, 65 insertions(+), 143 deletions(-)
[PATCH] hw/intc/loongarch_pch: fix edge triggered irq handling
For edge triggered irq, qemu_irq_pulse is used to inject irq. It will
set irq with high level and low level soon to simluate pulse irq.
For edge triggered irq, irq is injected and set as pending at rising
level, do not clear irq at lowering level. LoongArch pch interrupt will
clear irq for lowering level irq, there will be problem. ACPI ged deivce
is edge-triggered irq, it is used for cpu/memory hotplug.
This patch fixes memory hotplug issue on LoongArch virt machine.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_pch_pic.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c
index 9208fc4460..6aa4cadfa4 100644
--- a/hw/intc/loongarch_pch_pic.c
+++ b/hw/intc/loongarch_pch_pic.c
@@ -30,7 +30,11 @@ static void pch_pic_update_irq(LoongArchPCHPIC *s, uint64_t
mask, int level)
qemu_set_irq(s->parent_irq[s->htmsi_vector[irq]], 1);
}
} else {
-val = mask & s->intisr;
+/*
+ * intirr means requested pending irq
+ * do not clear pending irq for edge-triggered on lowering edge
+ */
+val = mask & s->intisr & ~s->intirr;
if (val) {
irq = ctz64(val);
s->intisr &= ~MAKE_64BIT_MASK(irq, 1);
@@ -51,6 +55,7 @@ static void pch_pic_irq_handler(void *opaque, int irq, int
level)
/* Edge triggered */
if (level) {
if ((s->last_intirr & mask) == 0) {
+/* marked pending on a rising edge */
s->intirr |= mask;
}
s->last_intirr |= mask;
--
2.27.0
[PATCH v3 0/4] QGA VSS Logging
Print all VSS error and trace to debugger and stderr. v3 -> v2: Reformat few log lines Move G_GNUC_PRINTF attribute to the declaration v2: https://patchew.org/QEMU/20230707083105.746811-1-kkost...@redhat.com/ v2 -> v1: Rename debug macro Move log code to function v1: https://patchew.org/QEMU/20230705141205.525776-1-kkost...@redhat.com/ Konstantin Kostiuk (4): QGA VSS: Add wrapper to send log to debugger and stderr QGA VSS: Replace 'fprintf(stderr' with PRINT_DEBUG QGA VSS: Print error in err_set QGA VSS: Add log in functions begin/end qga/vss-win32/install.cpp | 45 +++- qga/vss-win32/meson.build | 2 +- qga/vss-win32/provider.cpp | 3 +++ qga/vss-win32/requester.cpp | 51 - qga/vss-win32/vss-debug.cpp | 31 ++ qga/vss-win32/vss-debug.h | 25 ++ 6 files changed, 143 insertions(+), 14 deletions(-) create mode 100644 qga/vss-win32/vss-debug.cpp create mode 100644 qga/vss-win32/vss-debug.h -- 2.34.1
Re: [PATCH 1/7] target/ppc: Fix CPU reservation migration for record-replay
Nick,
On 6/23/23 09:57, Nicholas Piggin wrote:
ppc only migrates reserve_addr, so the destination machine can get a
valid reservation with an incorrect reservation value of 0. Prior to
commit 392d328abe753 ("target/ppc: Ensure stcx size matches larx"),
this could permit a stcx. to incorrectly succeed. That commit
inadvertently fixed that bug because the target machine starts with an
impossible reservation size of 0, so any stcx. will fail.
This behaviour is permitted by the ISA because reservation loss may
have implementation-dependent cause. What's more, with KVM machines it
is impossible save or reasonably restore reservation state. However if
the vmstate is being used for record-replay, the reservation must be
saved and restored exactly in order for execution from snapshot to
match the record.
This patch deprecates the existing incomplete reserve_addr vmstate,
and adds a new vmstate subsection with complete reservation state.
The new vmstate is needed only when record-replay mode is active.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h | 2 ++
target/ppc/machine.c | 26 --
target/ppc/translate.c | 2 ++
3 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 4138a25801..0087ce66e2 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1119,7 +1119,9 @@ struct CPUArchState {
target_ulong reserve_addr; /* Reservation address */
target_ulong reserve_length; /* Reservation larx op size (bytes) */
target_ulong reserve_val;/* Reservation value */
+#if defined(TARGET_PPC64)
target_ulong reserve_val2;
+#endif
^ this ifdef breaks gitlab on a handful of runners with this error:
https://gitlab.com/danielhb/qemu/-/jobs/4612030964
[1637/2985] Compiling C object
libqemu-ppc-linux-user.fa.p/target_ppc_translate.c.o
FAILED: libqemu-ppc-linux-user.fa.p/target_ppc_translate.c.o
cc -m64 -mcx16 -Ilibqemu-ppc-linux-user.fa.p -I. -I.. -Itarget/ppc -I../target/ppc
-I../common-user/host/x86_64 -I../linux-user/include/host/x86_64 -I../linux-user/include
-Ilinux-user -I../linux-user -Ilinux-user/ppc -I../linux-user/ppc -Iqapi -Itrace -Iui/shader
-I/usr/include/capstone -I/usr/include/glib-2.0 -I/usr/lib/x86_64-linux-gnu/glib-2.0/include
-fdiagnostics-color=auto -Wall -Winvalid-pch -Werror -std=gnu11 -O2 -g -fstack-protector-strong
-U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=2 -Wundef -Wwrite-strings -Wmissing-prototypes
-Wstrict-prototypes -Wredundant-decls -Wold-style-declaration -Wold-style-definition -Wtype-limits
-Wformat-security -Wformat-y2k -Winit-self -Wignored-qualifiers -Wempty-body -Wnested-externs
-Wendif-labels -Wexpansion-to-defined -Wimplicit-fallthrough=2 -Wmissing-format-attribute
-Wno-missing-include-dirs -Wno-shift-negative-value -Wno-psabi -isystem
/builds/danielhb/qemu/linux-headers -isystem linux-headers -iquote . -iquote /builds/danielhb/qemu
-iquote /builds/danielhb/qemu/include -iquote /builds/danielhb/qemu/host/include/x86_64 -iquote
/builds/danielhb/qemu/host/include/generic -iquote /builds/danielhb/qemu/tcg/i386 -pthread
-D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -fno-strict-aliasing -fno-common -fwrapv
-fPIE -isystem../linux-headers -isystemlinux-headers -DNEED_CPU_H
'-DCONFIG_TARGET="ppc-linux-user-config-target.h"'
'-DCONFIG_DEVICES="ppc-linux-user-config-devices.h"' -MD -MQ
libqemu-ppc-linux-user.fa.p/target_ppc_translate.c.o -MF
libqemu-ppc-linux-user.fa.p/target_ppc_translate.c.o.d -o
libqemu-ppc-linux-user.fa.p/target_ppc_translate.c.o -c ../target/ppc/translate.c
../target/ppc/translate.c: In function 'ppc_translate_init':
../target/ppc/translate.c:156:5: error: 'cpu_reserve_val2' undeclared (first
use in this function); did you mean 'cpu_reserve_val'?
156 | cpu_reserve_val2 = tcg_global_mem_new(cpu_env,
| ^~~~
| cpu_reserve_val
../target/ppc/translate.c:156:5: note: each undeclared identifier is reported
only once for each function it appears in
In file included from /usr/include/rpc/netdb.h:42,
from /usr/include/netdb.h:32,
from /builds/danielhb/qemu/include/sysemu/os-posix.h:34,
from /builds/danielhb/qemu/include/qemu/osdep.h:151,
from ../target/ppc/translate.c:21:
../target/ppc/translate.c:157:65: error: 'CPUPPCState' {aka 'struct
CPUArchState'} has no member named 'reserve_val2'; did you mean 'reserve_val'?
157 | offsetof(CPUPPCState,
reserve_val2),
|
^~~~
[1638/2985] Compiling C object
libqemu-ppc-linux-user.fa.p/libdecnumber_decNumber.c.o
I'll leave patch 1 and 5 behind for now. Since they're marked as fixes you
can send them during the freeze. Thanks,
Daniel
/* These are used in supervisor mode only */
target_ulong msr; /* machine state register */
diff --git a/target/
[PATCH v3 2/4] QGA VSS: Replace 'fprintf(stderr' with PRINT_DEBUG
Signed-off-by: Konstantin Kostiuk
---
qga/vss-win32/install.cpp | 12 ++--
qga/vss-win32/requester.cpp | 9 +
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/qga/vss-win32/install.cpp b/qga/vss-win32/install.cpp
index ff93b08a9e..9bd2c52b70 100644
--- a/qga/vss-win32/install.cpp
+++ b/qga/vss-win32/install.cpp
@@ -13,6 +13,7 @@
#include "qemu/osdep.h"
#include "vss-common.h"
+#include "vss-debug.h"
#ifdef HAVE_VSS_SDK
#include
#else
@@ -54,7 +55,7 @@ void errmsg(DWORD err, const char *text)
FORMAT_MESSAGE_FROM_SYSTEM | FORMAT_MESSAGE_IGNORE_INSERTS,
NULL, err, MAKELANGID(LANG_NEUTRAL, SUBLANG_DEFAULT),
(char *)&msg, 0, NULL);
-fprintf(stderr, "%.*s. (Error: %lx) %s\n", len, text, err, msg);
+qga_debug("%.*s. (Error: %lx) %s\n", len, text, err, msg);
LocalFree(msg);
}
@@ -219,7 +220,7 @@ static HRESULT QGAProviderRemove(ICatalogCollection *coll,
int i, void *arg)
{
HRESULT hr;
-fprintf(stderr, "Removing COM+ Application: %s\n", QGA_PROVIDER_NAME);
+qga_debug("Removing COM+ Application: %s", QGA_PROVIDER_NAME);
chk(coll->Remove(i));
out:
return hr;
@@ -304,9 +305,8 @@ STDAPI COMRegister(void)
}
strcpy(tlbPath, dllPath);
strcpy(tlbPath+n-3, "tlb");
-fprintf(stderr, "Registering " QGA_PROVIDER_NAME ":\n");
-fprintf(stderr, " %s\n", dllPath);
-fprintf(stderr, " %s\n", tlbPath);
+qga_debug("Registering " QGA_PROVIDER_NAME ": %s %s",
+ dllPath, tlbPath);
if (!PathFileExists(tlbPath)) {
hr = HRESULT_FROM_WIN32(ERROR_FILE_NOT_FOUND);
errmsg(hr, "Failed to lookup tlb");
@@ -517,7 +517,7 @@ namespace _com_util
}
if (mbstowcs(bstr, ascii, len) == (size_t)-1) {
-fprintf(stderr, "Failed to convert string '%s' into BSTR", ascii);
+qga_debug("Failed to convert string '%s' into BSTR", ascii);
bstr[0] = 0;
}
return bstr;
diff --git a/qga/vss-win32/requester.cpp b/qga/vss-win32/requester.cpp
index 3e998af4a8..e85b9bc633 100644
--- a/qga/vss-win32/requester.cpp
+++ b/qga/vss-win32/requester.cpp
@@ -12,6 +12,7 @@
#include "qemu/osdep.h"
#include "vss-common.h"
+#include "vss-debug.h"
#include "requester.h"
#include "install.h"
#include
@@ -59,13 +60,13 @@ STDAPI requester_init(void)
NULL, -1, NULL, NULL, RPC_C_AUTHN_LEVEL_PKT_PRIVACY,
RPC_C_IMP_LEVEL_IDENTIFY, NULL, EOAC_NONE, NULL);
if (FAILED(hr)) {
-fprintf(stderr, "failed to CoInitializeSecurity (error %lx)\n", hr);
+qga_debug("failed to CoInitializeSecurity (error %lx)", hr);
return hr;
}
hLib = LoadLibraryA("VSSAPI.DLL");
if (!hLib) {
-fprintf(stderr, "failed to load VSSAPI.DLL\n");
+qga_debug("failed to load VSSAPI.DLL");
return HRESULT_FROM_WIN32(GetLastError());
}
@@ -78,14 +79,14 @@ STDAPI requester_init(void)
#endif
);
if (!pCreateVssBackupComponents) {
-fprintf(stderr, "failed to get proc address from VSSAPI.DLL\n");
+qga_debug("failed to get proc address from VSSAPI.DLL");
return HRESULT_FROM_WIN32(GetLastError());
}
pVssFreeSnapshotProperties = (t_VssFreeSnapshotProperties)
GetProcAddress(hLib, "VssFreeSnapshotProperties");
if (!pVssFreeSnapshotProperties) {
-fprintf(stderr, "failed to get proc address from VSSAPI.DLL\n");
+qga_debug("failed to get proc address from VSSAPI.DLL");
return HRESULT_FROM_WIN32(GetLastError());
}
--
2.34.1
[PATCH v3 1/4] QGA VSS: Add wrapper to send log to debugger and stderr
Signed-off-by: Konstantin Kostiuk
---
qga/vss-win32/meson.build | 2 +-
qga/vss-win32/vss-debug.cpp | 31 +++
qga/vss-win32/vss-debug.h | 25 +
3 files changed, 57 insertions(+), 1 deletion(-)
create mode 100644 qga/vss-win32/vss-debug.cpp
create mode 100644 qga/vss-win32/vss-debug.h
diff --git a/qga/vss-win32/meson.build b/qga/vss-win32/meson.build
index 9483ccd3b8..0ac918910b 100644
--- a/qga/vss-win32/meson.build
+++ b/qga/vss-win32/meson.build
@@ -7,7 +7,7 @@ link_args = cc.get_supported_link_arguments([
qga_vss = shared_module(
'qga-vss',
- ['requester.cpp', 'provider.cpp', 'install.cpp', genh],
+ ['requester.cpp', 'provider.cpp', 'install.cpp', 'vss-debug.cpp', genh],
name_prefix: '',
cpp_args: ['-Wno-unknown-pragmas', '-Wno-delete-non-virtual-dtor',
'-Wno-non-virtual-dtor'],
link_args: link_args,
diff --git a/qga/vss-win32/vss-debug.cpp b/qga/vss-win32/vss-debug.cpp
new file mode 100644
index 00..5d6f37944b
--- /dev/null
+++ b/qga/vss-win32/vss-debug.cpp
@@ -0,0 +1,31 @@
+/*
+ * QEMU Guest Agent VSS debug declarations
+ *
+ * Copyright (C) 2023 Red Hat Inc
+ *
+ * Authors:
+ * Konstantin Kostiuk
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "vss-debug.h"
+#include "vss-common.h"
+
+void qga_debug_internal(const char *funcname, const char *fmt, ...) {
+char user_sting[512] = {0};
+char full_string[640] = {0};
+
+va_list args;
+va_start(args, fmt);
+vsnprintf(user_sting, 512, fmt, args);
+va_end(args);
+
+snprintf(full_string, 640, QGA_PROVIDER_NAME "[%lu]: %s %s\n",
+ GetCurrentThreadId(), funcname, user_sting);
+
+OutputDebugString(full_string);
+fprintf(stderr, "%s", full_string);
+}
diff --git a/qga/vss-win32/vss-debug.h b/qga/vss-win32/vss-debug.h
new file mode 100644
index 00..7800457392
--- /dev/null
+++ b/qga/vss-win32/vss-debug.h
@@ -0,0 +1,25 @@
+/*
+ * QEMU Guest Agent VSS debug declarations
+ *
+ * Copyright (C) 2023 Red Hat Inc
+ *
+ * Authors:
+ * Konstantin Kostiuk
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include
+
+#ifndef VSS_DEBUG_H
+#define VSS_DEBUG_H
+
+void qga_debug_internal(const char *funcname, const char *fmt, ...)
G_GNUC_PRINTF(2, 3);
+
+#define qga_debug(fmt, ...) qga_debug_internal(__func__, fmt, ## __VA_ARGS__)
+#define qga_debug_begin qga_debug("begin")
+#define qga_debug_end qga_debug("end")
+
+#endif
--
2.34.1
[PATCH v3 4/4] QGA VSS: Add log in functions begin/end
Signed-off-by: Konstantin Kostiuk
---
qga/vss-win32/install.cpp | 33 +
qga/vss-win32/provider.cpp | 3 +++
qga/vss-win32/requester.cpp | 34 ++
3 files changed, 70 insertions(+)
diff --git a/qga/vss-win32/install.cpp b/qga/vss-win32/install.cpp
index 9bd2c52b70..6865c04d8a 100644
--- a/qga/vss-win32/install.cpp
+++ b/qga/vss-win32/install.cpp
@@ -100,6 +100,8 @@ HRESULT put_Value(ICatalogObject *pObj, LPCWSTR name, T val)
/* Lookup Administrators group name from winmgmt */
static HRESULT GetAdminName(_bstr_t *name)
{
+qga_debug_begin;
+
HRESULT hr;
COMPointer pLoc;
COMPointer pSvc;
@@ -142,6 +144,7 @@ static HRESULT GetAdminName(_bstr_t *name)
}
out:
+qga_debug_end;
return hr;
}
@@ -149,6 +152,8 @@ out:
static HRESULT getNameByStringSID(
const wchar_t *sid, LPWSTR buffer, LPDWORD bufferLen)
{
+qga_debug_begin;
+
HRESULT hr = S_OK;
PSID psid = NULL;
SID_NAME_USE groupType;
@@ -168,6 +173,7 @@ static HRESULT getNameByStringSID(
LocalFree(psid);
out:
+qga_debug_end;
return hr;
}
@@ -175,6 +181,8 @@ out:
static HRESULT QGAProviderFind(
HRESULT (*found)(ICatalogCollection *, int, void *), void *arg)
{
+qga_debug_begin;
+
HRESULT hr;
COMInitializer initializer;
COMPointer pUnknown;
@@ -205,12 +213,15 @@ static HRESULT QGAProviderFind(
chk(pColl->SaveChanges(&n));
out:
+qga_debug_end;
return hr;
}
/* Count QGA VSS provider in COM+ Application Catalog */
static HRESULT QGAProviderCount(ICatalogCollection *coll, int i, void *arg)
{
+qga_debug_begin;
+
(*(int *)arg)++;
return S_OK;
}
@@ -218,28 +229,35 @@ static HRESULT QGAProviderCount(ICatalogCollection *coll,
int i, void *arg)
/* Remove QGA VSS provider from COM+ Application Catalog Collection */
static HRESULT QGAProviderRemove(ICatalogCollection *coll, int i, void *arg)
{
+qga_debug_begin;
HRESULT hr;
qga_debug("Removing COM+ Application: %s", QGA_PROVIDER_NAME);
chk(coll->Remove(i));
out:
+qga_debug_end;
return hr;
}
/* Unregister this module from COM+ Applications Catalog */
STDAPI COMUnregister(void)
{
+qga_debug_begin;
+
HRESULT hr;
DllUnregisterServer();
chk(QGAProviderFind(QGAProviderRemove, NULL));
out:
+qga_debug_end;
return hr;
}
/* Register this module to COM+ Applications Catalog */
STDAPI COMRegister(void)
{
+qga_debug_begin;
+
HRESULT hr;
COMInitializer initializer;
COMPointer pUnknown;
@@ -259,12 +277,14 @@ STDAPI COMRegister(void)
if (!g_hinstDll) {
errmsg(E_FAIL, "Failed to initialize DLL");
+qga_debug_end;
return E_FAIL;
}
chk(QGAProviderFind(QGAProviderCount, (void *)&count));
if (count) {
errmsg(E_ABORT, "QGA VSS Provider is already installed");
+qga_debug_end;
return E_ABORT;
}
@@ -354,6 +374,7 @@ out:
COMUnregister();
}
+qga_debug_end;
return hr;
}
@@ -369,6 +390,8 @@ STDAPI_(void) CALLBACK DLLCOMUnregister(HWND, HINSTANCE,
LPSTR, int)
static BOOL CreateRegistryKey(LPCTSTR key, LPCTSTR value, LPCTSTR data)
{
+qga_debug_begin;
+
HKEY hKey;
LONG ret;
DWORD size;
@@ -389,6 +412,7 @@ static BOOL CreateRegistryKey(LPCTSTR key, LPCTSTR value,
LPCTSTR data)
RegCloseKey(hKey);
out:
+qga_debug_end;
if (ret != ERROR_SUCCESS) {
/* As we cannot printf within DllRegisterServer(), show a dialog. */
errmsg_dialog(ret, "Cannot add registry", key);
@@ -400,6 +424,8 @@ out:
/* Register this dll as a VSS provider */
STDAPI DllRegisterServer(void)
{
+qga_debug_begin;
+
COMInitializer initializer;
COMPointer pVssAdmin;
HRESULT hr = E_FAIL;
@@ -478,12 +504,15 @@ out:
DllUnregisterServer();
}
+qga_debug_end;
return hr;
}
/* Unregister this VSS hardware provider from the system */
STDAPI DllUnregisterServer(void)
{
+qga_debug_begin;
+
TCHAR key[256];
COMInitializer initializer;
COMPointer pVssAdmin;
@@ -501,6 +530,7 @@ STDAPI DllUnregisterServer(void)
SHDeleteKey(HKEY_CLASSES_ROOT, key);
SHDeleteKey(HKEY_CLASSES_ROOT, g_szProgid);
+qga_debug_end;
return S_OK; /* Uninstall should never fail */
}
@@ -527,6 +557,8 @@ namespace _com_util
/* Stop QGA VSS provider service using Winsvc API */
STDAPI StopService(void)
{
+qga_debug_begin;
+
HRESULT hr = S_OK;
SC_HANDLE manager = OpenSCManager(NULL, NULL, SC_MANAGER_ALL_ACCESS);
SC_HANDLE service = NULL;
@@ -551,5 +583,6 @@ STDAPI StopService(void)
out:
CloseServiceHandle(service);
CloseServiceHandle(manager);
+qga_debug_end;
return hr;
}
diff --git a/qga/vss-win32/provider.cpp b/qga/vss-win32/provider.cpp
index 1b885e24ee..cc72e5ef1b 100644
--- a/qga/vss-win32/provider.cpp
+++ b/qga/vss-win32/provider
[PATCH v3 3/4] QGA VSS: Print error in err_set
Signed-off-by: Konstantin Kostiuk
Reviewed-by: Philippe Mathieu-Daudé
---
qga/vss-win32/requester.cpp | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/qga/vss-win32/requester.cpp b/qga/vss-win32/requester.cpp
index e85b9bc633..f3eafacfc1 100644
--- a/qga/vss-win32/requester.cpp
+++ b/qga/vss-win32/requester.cpp
@@ -26,9 +26,11 @@
#define DEFAULT_VSS_BACKUP_TYPE VSS_BT_FULL
-#define err_set(e, err, fmt, ...) \
-((e)->error_setg_win32_wrapper((e)->errp, __FILE__, __LINE__, __func__, \
- err, fmt, ## __VA_ARGS__))
+#define err_set(e, err, fmt, ...) { \
+(e)->error_setg_win32_wrapper((e)->errp, __FILE__, __LINE__, __func__, \
+ err, fmt, ## __VA_ARGS__); \
+qga_debug(fmt, ## __VA_ARGS__); \
+}
/* Bad idea, works only when (e)->errp != NULL: */
#define err_is_set(e) ((e)->errp && *(e)->errp)
/* To lift this restriction, error_propagate(), like we do in QEMU code */
--
2.34.1
Re: [PATCH] io: remove io watch if TLS channel is closed during handshake
On Wed, Jul 5, 2023 at 10:20 PM Daniel P. Berrangé
wrote:
> The TLS handshake make take some time to complete, during which time an
> I/O watch might be registered with the main loop. If the owner of the
> I/O channel invokes qio_channel_close() while the handshake is waiting
> to continue the I/O watch must be removed. Failing to remove it will
> later trigger the completion callback which the owner is not expecting
> to receive. In the case of the VNC server, this results in a SEGV as
> vnc_disconnect_start() tries to shutdown a client connection that is
> already gone / NULL.
>
> CVE-2023-3354
> Reported-by: jiangyegen
> Signed-off-by: Daniel P. Berrangé
>
> ---
> include/io/channel-tls.h | 1 +
> io/channel-tls.c | 18 --
> 2 files changed, 13 insertions(+), 6 deletions(-)
>
> diff --git a/include/io/channel-tls.h b/include/io/channel-tls.h
> index 5672479e9e..26c67f17e2 100644
> --- a/include/io/channel-tls.h
> +++ b/include/io/channel-tls.h
> @@ -48,6 +48,7 @@ struct QIOChannelTLS {
> QIOChannel *master;
> QCryptoTLSSession *session;
> QIOChannelShutdown shutdown;
> +guint hs_ioc_tag;
> };
>
> /**
> diff --git a/io/channel-tls.c b/io/channel-tls.c
> index 9805dd0a3f..e327e6a5c2 100644
> --- a/io/channel-tls.c
> +++ b/io/channel-tls.c
> @@ -198,12 +198,13 @@ static void
> qio_channel_tls_handshake_task(QIOChannelTLS *ioc,
> }
>
> trace_qio_channel_tls_handshake_pending(ioc, status);
> -qio_channel_add_watch_full(ioc->master,
> - condition,
> - qio_channel_tls_handshake_io,
> - data,
> - NULL,
> - context);
> +ioc->hs_ioc_tag =
> +qio_channel_add_watch_full(ioc->master,
> + condition,
> + qio_channel_tls_handshake_io,
> + data,
> + NULL,
> + context);
> }
> }
>
> @@ -218,6 +219,7 @@ static gboolean
> qio_channel_tls_handshake_io(QIOChannel *ioc,
> QIOChannelTLS *tioc = QIO_CHANNEL_TLS(
> qio_task_get_source(task));
>
> +tioc->hs_ioc_tag = 0;
> g_free(data);
> qio_channel_tls_handshake_task(tioc, task, context);
>
> @@ -378,6 +380,10 @@ static int qio_channel_tls_close(QIOChannel *ioc,
> {
> QIOChannelTLS *tioc = QIO_CHANNEL_TLS(ioc);
>
> +if (tioc->hs_ioc_tag) {
> +g_source_remove(tioc->hs_ioc_tag);
>
set it to 0 ?
or
g_clear_handle_id(&tios->hs_ioc_tag, g_source_remove);
> +}
> +
> return qio_channel_close(tioc->master, errp);
> }
>
> --
> 2.41.0
>
>
>
--
Marc-André Lureau
Re: [PATCH] io: remove io watch if TLS channel is closed during handshake
On Fri, Jul 07, 2023 at 01:30:16PM +0400, Marc-André Lureau wrote:
> On Wed, Jul 5, 2023 at 10:20 PM Daniel P. Berrangé
> wrote:
>
> > The TLS handshake make take some time to complete, during which time an
> > I/O watch might be registered with the main loop. If the owner of the
> > I/O channel invokes qio_channel_close() while the handshake is waiting
> > to continue the I/O watch must be removed. Failing to remove it will
> > later trigger the completion callback which the owner is not expecting
> > to receive. In the case of the VNC server, this results in a SEGV as
> > vnc_disconnect_start() tries to shutdown a client connection that is
> > already gone / NULL.
> >
> > CVE-2023-3354
> > Reported-by: jiangyegen
> > Signed-off-by: Daniel P. Berrangé
> >
>
>
>
> > ---
> > include/io/channel-tls.h | 1 +
> > io/channel-tls.c | 18 --
> > 2 files changed, 13 insertions(+), 6 deletions(-)
> >
> > diff --git a/include/io/channel-tls.h b/include/io/channel-tls.h
> > index 5672479e9e..26c67f17e2 100644
> > --- a/include/io/channel-tls.h
> > +++ b/include/io/channel-tls.h
> > @@ -48,6 +48,7 @@ struct QIOChannelTLS {
> > QIOChannel *master;
> > QCryptoTLSSession *session;
> > QIOChannelShutdown shutdown;
> > +guint hs_ioc_tag;
> > };
> >
> > /**
> > diff --git a/io/channel-tls.c b/io/channel-tls.c
> > index 9805dd0a3f..e327e6a5c2 100644
> > --- a/io/channel-tls.c
> > +++ b/io/channel-tls.c
> > @@ -198,12 +198,13 @@ static void
> > qio_channel_tls_handshake_task(QIOChannelTLS *ioc,
> > }
> >
> > trace_qio_channel_tls_handshake_pending(ioc, status);
> > -qio_channel_add_watch_full(ioc->master,
> > - condition,
> > - qio_channel_tls_handshake_io,
> > - data,
> > - NULL,
> > - context);
> > +ioc->hs_ioc_tag =
> > +qio_channel_add_watch_full(ioc->master,
> > + condition,
> > + qio_channel_tls_handshake_io,
> > + data,
> > + NULL,
> > + context);
> > }
> > }
> >
> > @@ -218,6 +219,7 @@ static gboolean
> > qio_channel_tls_handshake_io(QIOChannel *ioc,
> > QIOChannelTLS *tioc = QIO_CHANNEL_TLS(
> > qio_task_get_source(task));
> >
> > +tioc->hs_ioc_tag = 0;
> > g_free(data);
> > qio_channel_tls_handshake_task(tioc, task, context);
> >
> > @@ -378,6 +380,10 @@ static int qio_channel_tls_close(QIOChannel *ioc,
> > {
> > QIOChannelTLS *tioc = QIO_CHANNEL_TLS(ioc);
> >
> > +if (tioc->hs_ioc_tag) {
> > +g_source_remove(tioc->hs_ioc_tag);
> >
>
> set it to 0 ?
> or
> g_clear_handle_id(&tios->hs_ioc_tag, g_source_remove);
Yes, close can be called mutliple times, so we must set to zero.
> > +}
> > +
> > return qio_channel_close(tioc->master, errp);
> > }
> >
> > --
> > 2.41.0
> >
> >
> >
>
> --
> Marc-André Lureau
With regards,
Daniel
--
|: https://berrange.com -o-https://www.flickr.com/photos/dberrange :|
|: https://libvirt.org -o-https://fstop138.berrange.com :|
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Re: [RFC PATCH] docs/interop: define STANDALONE protocol feature for vhost-user
On Fri, Jul 07, 2023 at 08:58:00AM +0100, Alex Bennée wrote:
>
> "Michael S. Tsirkin" writes:
>
> > On Tue, Jul 04, 2023 at 01:36:00PM +0100, Alex Bennée wrote:
> >> Currently QEMU has to know some details about the back-end to be able
> >> to setup the guest. While various parts of the setup can be delegated
> >> to the backend (for example config handling) this is a very piecemeal
> >> approach.
> >
> >> This patch suggests a new feature flag (VHOST_USER_PROTOCOL_F_STANDALONE)
> >> which the back-end can advertise which allows a probe message to be
> >> sent to get all the details QEMU needs to know in one message.
> >
> > The reason we do piecemeal is that these existing pieces can be reused
> > as others evolve or fall by wayside.
>
> Sure I have no objection in principle but we then turn code like:
>
> if (dev->protocol_features & (1ULL <<
> VHOST_USER_PROTOCOL_F_STANDALONE)) {
> err = vhost_user_get_backend_specs(dev, errp);
> if (err < 0) {
> error_setg_errno(errp, EPROTO, "vhost_get_backend_specs
> failed");
> return -EPROTO;
> }
> }
>
> to
>
> if (dev->protocol_features & (1ULL << VHOST_USER_PROTOCOL_F_ID) &&
> dev->protocol_features & (1ULL << VHOST_USER_PROTOCOL_F_CFGSZ) &&
> dev->protocol_features & (1ULL << VHOST_USER_PROTOCOL_F_MINVQ) &&
> dev->protocol_features & (1ULL << VHOST_USER_PROTOCOL_F_MAXVQ)
> ) {
> err = vhost_user_get_virtio_id(dev, errp);
> if (err < 0) {
> error_setg_errno(errp, EPROTO, "vhost_get_backend_id failed");
> return -EPROTO;
> }
> err = vhost_user_get_virtio_cfgsz(dev, errp);
> if (err < 0) {
> error_setg_errno(errp, EPROTO, "vhost_get_backend_cfgsz
> failed");
> return -EPROTO;
> }
> err = vhost_user_get_virtio_minvq(dev, errp);
> if (err < 0) {
> error_setg_errno(errp, EPROTO, "vhost_get_backend_minvq
> failed");
> return -EPROTO;
> }
> err = vhost_user_get_virtio_maxvq(dev, errp);
> if (err < 0) {
> error_setg_errno(errp, EPROTO, "vhost_get_backend_maxvq
> failed");
> return -EPROTO;
> }
> dev->specs.valid = true;
> }
>
> for little gain IMHO.
>
> > For example, I can think of instances where you want to connect
> > specifically to e.g. networking backend, and specify it
> > on command line. Reasons could be many, e.g. for debugging,
> > or to prevent connecting to wrong device on wrong channel
> > (kind of like type safety).
>
> I don't quite follow what you are trying to say here.
That some or all of these might be better on qemu command line
not come from backend. Then we'll want to *send* it to backend.
All this at our discretion without protocol changes.
> > What is the reason to have 1 message? startup latency?
> > How about we allow pipelining several messages then?
> > Will be easier.
>
> I'm not overly worried about performance because this is all at
> start-up. I am worried about excessive complexity though. We already
> have quite a lot of interacting protocol messages.
>
> >
> >
> >>
> >> Signed-off-by: Alex Bennée
> >>
> >> ---
> >> Initial RFC for discussion. I intend to prototype this work with QEMU
> >> and one of the rust-vmm vhost-user daemons.
> >> ---
> >> docs/interop/vhost-user.rst | 37 +
> >> hw/virtio/vhost-user.c | 8
> >> 2 files changed, 45 insertions(+)
> >>
> >> diff --git a/docs/interop/vhost-user.rst b/docs/interop/vhost-user.rst
> >> index 5a070adbc1..85b1b1583a 100644
> >> --- a/docs/interop/vhost-user.rst
> >> +++ b/docs/interop/vhost-user.rst
> >> @@ -275,6 +275,21 @@ Inflight description
> >>
> >> :queue size: a 16-bit size of virtqueues
> >>
> >> +Backend specifications
> >> +^^
> >> +
> >> ++---+-+++
> >> +| device id | config size | min_vqs | max_vqs |
> >> ++---+-+++
> >> +
> >> +:device id: a 32-bit value holding the VirtIO device ID
> >> +
> >> +:config size: a 32-bit value holding the config size (see
> >> ``VHOST_USER_GET_CONFIG``)
> >> +
> >> +:min_vqs: a 32-bit value holding the minimum number of vqs supported
> >> +
> >> +:max_vqs: a 32-bit value holding the maximum number of vqs supported,
> >> must be >= min_vqs
> >> +
> >
> > looks like a weird set of info.
>
> It's basically the information you need for -device vhost-user-device to
> start-up (and what is essentially the information set by the stubs as
> they start-up).
>
> > why would we want # of vqs and not their sizes?
>
> I thought the vring's themselves where allocated by the driver. We only
> need to the number of vqs so we can allocate the t
[PATCH qemu v3 1/1] fdt_load_addr is getting assigned as the result of riscv_compute_fdt_addr(), which is an uint64_t.
From: Lakshmi Bai Raja Subramanian fdt_load_addr is declared as uint32_t which is not matching with the return data type of riscv_compute_fdt_addr. Modified fdt_load_addr data type to uint64_t to match the riscv_compute_fdt_addr() return data type. This fix also helps in calculating the right fdt address when DRAM is mapped to higher 64-bit address. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Lakshmi Bai Raja Subramanian --- hw/riscv/virt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 95708d890e..c348529ac0 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1244,7 +1244,7 @@ static void virt_machine_done(Notifier *notifier, void *data) target_ulong start_addr = memmap[VIRT_DRAM].base; target_ulong firmware_end_addr, kernel_start_addr; const char *firmware_name = riscv_default_firmware_name(&s->soc[0]); -uint32_t fdt_load_addr; +uint64_t fdt_load_addr; uint64_t kernel_entry = 0; BlockBackend *pflash_blk0; -- 2.38.5
[PATCH qemu v3 0/1] [Ping] [PATCH qemu v3] fdt_load_addr is getting assigned as the result of riscv_compute_fdt_addr(), which is an uint64_t.
Ping for the patch https://patchew.org/QEMU/168753067876.24231.1158476330586280652...@git.sr.ht/ Lakshmi Bai Raja Subramanian (1): fdt_load_addr is getting assigned as the result of riscv_compute_fdt_addr(), which is an uint64_t. hw/riscv/virt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.38.5
[PATCH] vhost_vdpa: no need to fetch vring base when poweroff
In the poweroff routine, no need to fetch last available index.
This commit also provides a better debug message in the vhost
caller vhost_virtqueue_stop, because if vhost does not fetch
the last avail idx successfully, maybe the device does not
suspend, vhost will sync last avail idx to vring used idx as a
work around, not a failure.
Signed-off-by: Zhu Lingshan
---
hw/virtio/vhost-vdpa.c | 4
hw/virtio/vhost.c | 2 +-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/virtio/vhost-vdpa.c b/hw/virtio/vhost-vdpa.c
index 3c575a9a6e..f62952e1c7 100644
--- a/hw/virtio/vhost-vdpa.c
+++ b/hw/virtio/vhost-vdpa.c
@@ -26,6 +26,7 @@
#include "cpu.h"
#include "trace.h"
#include "qapi/error.h"
+#include "sysemu/runstate.h"
/*
* Return one past the end of the end of section. Be careful with uint64_t
@@ -1391,6 +1392,9 @@ static int vhost_vdpa_get_vring_base(struct vhost_dev
*dev,
struct vhost_vdpa *v = dev->opaque;
int ret;
+if (runstate_check(RUN_STATE_SHUTDOWN))
+return 0;
+
if (v->shadow_vqs_enabled) {
ring->num = virtio_queue_get_last_avail_idx(dev->vdev, ring->index);
return 0;
diff --git a/hw/virtio/vhost.c b/hw/virtio/vhost.c
index 82394331bf..84712743e0 100644
--- a/hw/virtio/vhost.c
+++ b/hw/virtio/vhost.c
@@ -1262,7 +1262,7 @@ void vhost_virtqueue_stop(struct vhost_dev *dev,
r = dev->vhost_ops->vhost_get_vring_base(dev, &state);
if (r < 0) {
-VHOST_OPS_DEBUG(r, "vhost VQ %u ring restore failed: %d", idx, r);
+VHOST_OPS_DEBUG(r, "sync last avail idx to the used idx for vhost VQ
%u", idx);
/* Connection to the backend is broken, so let's sync internal
* last avail idx to the device used idx.
*/
--
2.39.3
Re: [virtio-dev] [RFC PATCH] docs/interop: define STANDALONE protocol feature for vhost-user
On Tue, Jul 04, 2023 at 04:02:42PM +0100, Alex Bennée wrote: Stefano Garzarella writes: On Tue, Jul 04, 2023 at 01:36:00PM +0100, Alex Bennée wrote: Currently QEMU has to know some details about the back-end to be able to setup the guest. While various parts of the setup can be delegated to the backend (for example config handling) this is a very piecemeal approach. This patch suggests a new feature flag (VHOST_USER_PROTOCOL_F_STANDALONE) which the back-end can advertise which allows a probe message to be sent to get all the details QEMU needs to know in one message. Signed-off-by: Alex Bennée --- Initial RFC for discussion. I intend to prototype this work with QEMU and one of the rust-vmm vhost-user daemons. Thanks for starting this discussion! I'm comparing with vhost-vdpa IOCTLs, so my questions may be superficial, but they help me understand the differences. I did have a quick read-through to get a handle on vhost-vdpa but the docs are fairly empty. However I see there is more detail in the linux commit so after looking at that I do wonder: * The kernel commit defines a subset of VIRTIO_F feature flags. Should we do the same for this interface? Sorry, I didn't get this. Do you mean that the kernel is filtering some features? Or are you talking about backend features? * The VDPA GET/SET STATUS and GET/SET CONFIG ioctls are already covered by the equivalent VHOST_USER messages? Yep, I think so. --- docs/interop/vhost-user.rst | 37 + hw/virtio/vhost-user.c | 8 2 files changed, 45 insertions(+) diff --git a/docs/interop/vhost-user.rst b/docs/interop/vhost-user.rst index 5a070adbc1..85b1b1583a 100644 --- a/docs/interop/vhost-user.rst +++ b/docs/interop/vhost-user.rst @@ -275,6 +275,21 @@ Inflight description :queue size: a 16-bit size of virtqueues +Backend specifications +^^ + ++---+-+++ +| device id | config size | min_vqs | max_vqs | ++---+-+++ + +:device id: a 32-bit value holding the VirtIO device ID + +:config size: a 32-bit value holding the config size (see ``VHOST_USER_GET_CONFIG``) + +:min_vqs: a 32-bit value holding the minimum number of vqs supported Why do we need the minimum? We need to know the minimum number because some devices have fixed VQs that must be present. But does QEMU need to know this? Or is it okay that the driver will then fail in the guest if there are not the right number of queues? + +:max_vqs: a 32-bit value holding the maximum number of vqs supported, must be >= min_vqs Is this overlap with VHOST_USER_GET_QUEUE_NUM? Yes it does and I considered implementing a bunch of messages to fill in around what we already have. However that seemed like it would add a bunch of complexity to the interface when we could get all the initial data in one go. Yes I understand, though if we need to add new things to return in the future how do we do it? Do we need to provide features for this structure? + C structure --- @@ -296,6 +311,7 @@ In QEMU the vhost-user message is implemented with the following struct: VhostUserConfig config; VhostUserVringArea area; VhostUserInflight inflight; + VhostUserBackendSpecs specs; }; } QEMU_PACKED VhostUserMsg; @@ -316,6 +332,7 @@ replies. Here is a list of the ones that do: * ``VHOST_USER_GET_VRING_BASE`` * ``VHOST_USER_SET_LOG_BASE`` (if ``VHOST_USER_PROTOCOL_F_LOG_SHMFD``) * ``VHOST_USER_GET_INFLIGHT_FD`` (if ``VHOST_USER_PROTOCOL_F_INFLIGHT_SHMFD``) +* ``VHOST_USER_GET_BACKEND_SPECS`` (if ``VHOST_USER_PROTOCOL_F_STANDALONE``) .. seealso:: @@ -885,6 +902,13 @@ Protocol features #define VHOST_USER_PROTOCOL_F_CONFIGURE_MEM_SLOTS 15 #define VHOST_USER_PROTOCOL_F_STATUS 16 #define VHOST_USER_PROTOCOL_F_XEN_MMAP 17 + #define VHOST_USER_PROTOCOL_F_STANDALONE 18 + +Some features are only valid in the presence of other supporting +features. In the case of ``VHOST_USER_PROTOCOL_F_STANDALONE`` the +backend must also support ``VHOST_USER_PROTOCOL_F_CONFIG`` and +``VHOST_USER_PROTOCOL_F_STATUS``. + What about adding a new section where we will describe what we mean with "standalone" devices? For example that the entire virtio device is emulated in the backend, etc. By the way, I was thinking more about F_FULL_DEVICE, but I'm not good with names, so I'll just throw out an idea :-) Naming things is hard ;-) I know :-) I could add a new section although AIUI there is nothing really in existing daemons which is split between the front-end and back-end. The stubs are basically boilerplate and ensure DT/PCIe hubs make the device appear so once things are discovered QEMU never really gets involved aside from being a dumb relay. For the backend I don't think there is much to say, but for the frontend it changes a lot in my opinion if
[PATCH] tcg: Fix info_in_idx increment in layout_arg_by_ref
Off by one error, failing to take into account that layout_arg_1
already incremeneted info_in_idx for the first piece. We only
need care for the n-1 TCG_CALL_ARG_BY_REF_N pieces here.
Cc: qemu-sta...@nongnu.org
Fixes: 313bdea84d2 ("tcg: Add TCG_CALL_{RET,ARG}_BY_REF")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1751
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index a0628fe424..652e8ea6b9 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1083,7 +1083,7 @@ static void layout_arg_by_ref(TCGCumulativeArgs *cum,
TCGHelperInfo *info)
.ref_slot = cum->ref_slot + i,
};
}
-cum->info_in_idx += n;
+cum->info_in_idx += n - 1; /* i=0 accounted for in layout_arg_1 */
cum->ref_slot += n;
}
--
2.34.1
[PATCH] util/interval-tree: Avoid race conditions without optimization
Read the left and right trees once, so that the gating
tests are meaningful. This was only a problem at -O0,
where the compiler didn't CSE the two reads.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Richard Henderson
---
util/interval-tree.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/util/interval-tree.c b/util/interval-tree.c
index 4c0baf108f..31978c32ac 100644
--- a/util/interval-tree.c
+++ b/util/interval-tree.c
@@ -741,12 +741,15 @@ static IntervalTreeNode
*interval_tree_subtree_search(IntervalTreeNode *node,
uint64_t last)
{
while (true) {
+RBNode *rb_tmp;
+
/*
* Loop invariant: start <= node->subtree_last
* (Cond2 is satisfied by one of the subtree nodes)
*/
-if (node->rb.rb_left) {
-IntervalTreeNode *left = rb_to_itree(node->rb.rb_left);
+rb_tmp = node->rb.rb_left;
+if (rb_tmp) {
+IntervalTreeNode *left = rb_to_itree(rb_tmp);
if (start <= left->subtree_last) {
/*
@@ -765,8 +768,10 @@ static IntervalTreeNode
*interval_tree_subtree_search(IntervalTreeNode *node,
if (start <= node->last) { /* Cond2 */
return node; /* node is leftmost match */
}
-if (node->rb.rb_right) {
-node = rb_to_itree(node->rb.rb_right);
+
+rb_tmp = node->rb.rb_right;
+if (rb_tmp) {
+node = rb_to_itree(rb_tmp);
if (start <= node->subtree_last) {
continue;
}
--
2.34.1
Re: [PATCH v3 1/4] QGA VSS: Add wrapper to send log to debugger and stderr
On 7/7/23 11:22, Konstantin Kostiuk wrote:
Signed-off-by: Konstantin Kostiuk
---
qga/vss-win32/meson.build | 2 +-
qga/vss-win32/vss-debug.cpp | 31 +++
qga/vss-win32/vss-debug.h | 25 +
3 files changed, 57 insertions(+), 1 deletion(-)
create mode 100644 qga/vss-win32/vss-debug.cpp
create mode 100644 qga/vss-win32/vss-debug.h
diff --git a/qga/vss-win32/vss-debug.cpp b/qga/vss-win32/vss-debug.cpp
new file mode 100644
index 00..5d6f37944b
--- /dev/null
+++ b/qga/vss-win32/vss-debug.cpp
@@ -0,0 +1,31 @@
+/*
+ * QEMU Guest Agent VSS debug declarations
+ *
+ * Copyright (C) 2023 Red Hat Inc
+ *
+ * Authors:
+ * Konstantin Kostiuk
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "vss-debug.h"
+#include "vss-common.h"
+
+void qga_debug_internal(const char *funcname, const char *fmt, ...) {
+char user_sting[512] = {0};
"user_string"
+char full_string[640] = {0};
+
+va_list args;
+va_start(args, fmt);
+vsnprintf(user_sting, 512, fmt, args);
ARRAY_SIZE(user_string)
+va_end(args);
+
+snprintf(full_string, 640, QGA_PROVIDER_NAME "[%lu]: %s %s\n",
+ GetCurrentThreadId(), funcname, user_sting);
if (snprintf() <= 0) { return; }
+
+OutputDebugString(full_string);
+fprintf(stderr, "%s", full_string);
Format unused:
fputs(full_string, stderr);
+}
With the changes:
Reviewed-by: Philippe Mathieu-Daudé
Re: [PATCH v3 2/4] QGA VSS: Replace 'fprintf(stderr' with PRINT_DEBUG
On 7/7/23 11:22, Konstantin Kostiuk wrote:
Signed-off-by: Konstantin Kostiuk
---
qga/vss-win32/install.cpp | 12 ++--
qga/vss-win32/requester.cpp | 9 +
2 files changed, 11 insertions(+), 10 deletions(-)
@@ -304,9 +305,8 @@ STDAPI COMRegister(void)
}
strcpy(tlbPath, dllPath);
strcpy(tlbPath+n-3, "tlb");
-fprintf(stderr, "Registering " QGA_PROVIDER_NAME ":\n");
-fprintf(stderr, " %s\n", dllPath);
-fprintf(stderr, " %s\n", tlbPath);
+qga_debug("Registering " QGA_PROVIDER_NAME ": %s %s",
+ dllPath, tlbPath);
Previous has 3 "\n", not necessary? Otherwise:
Reviewed-by: Philippe Mathieu-Daudé
if (!PathFileExists(tlbPath)) {
hr = HRESULT_FROM_WIN32(ERROR_FILE_NOT_FOUND);
errmsg(hr, "Failed to lookup tlb");
[PATCH v2 2/2] accel/tcg: Always lock pages before translation
We had done this for user-mode by invoking page_protect
within the translator loop. Extend this to handle system
mode as well. Move page locking out of tb_link_page.
Reported-by: Liren Wei
Reported-by: Richard W.M. Jones
Signed-off-by: Richard Henderson
Tested-by: Richard W.M. Jones
---
accel/tcg/internal.h | 30 -
accel/tcg/cpu-exec.c | 20
accel/tcg/tb-maint.c | 242 --
accel/tcg/translate-all.c | 43 ++-
accel/tcg/translator.c| 34 --
5 files changed, 236 insertions(+), 133 deletions(-)
diff --git a/accel/tcg/internal.h b/accel/tcg/internal.h
index 650c3ac53f..e8cbbde581 100644
--- a/accel/tcg/internal.h
+++ b/accel/tcg/internal.h
@@ -10,6 +10,7 @@
#define ACCEL_TCG_INTERNAL_H
#include "exec/exec-all.h"
+#include "exec/translate-all.h"
/*
* Access to the various translations structures need to be serialised
@@ -35,6 +36,32 @@ static inline void page_table_config_init(void) { }
void page_table_config_init(void);
#endif
+#ifdef CONFIG_USER_ONLY
+/*
+ * For user-only, page_protect sets the page read-only.
+ * Since most execution is already on read-only pages, and we'd need to
+ * account for other TBs on the same page, defer undoing any page protection
+ * until we receive the write fault.
+ */
+static inline void tb_lock_page0(tb_page_addr_t p0)
+{
+page_protect(p0);
+}
+
+static inline void tb_lock_page1(tb_page_addr_t p0, tb_page_addr_t p1)
+{
+page_protect(p1);
+}
+
+static inline void tb_unlock_page1(tb_page_addr_t p0, tb_page_addr_t p1) { }
+static inline void tb_unlock_pages(TranslationBlock *tb) { }
+#else
+void tb_lock_page0(tb_page_addr_t);
+void tb_lock_page1(tb_page_addr_t, tb_page_addr_t);
+void tb_unlock_page1(tb_page_addr_t, tb_page_addr_t);
+void tb_unlock_pages(TranslationBlock *);
+#endif
+
#ifdef CONFIG_SOFTMMU
void tb_invalidate_phys_range_fast(ram_addr_t ram_addr,
unsigned size,
@@ -48,8 +75,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, vaddr pc,
void page_init(void);
void tb_htable_init(void);
void tb_reset_jump(TranslationBlock *tb, int n);
-TranslationBlock *tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc,
- tb_page_addr_t phys_page2);
+TranslationBlock *tb_link_page(TranslationBlock *tb);
bool tb_invalidate_phys_page_unwind(tb_page_addr_t addr, uintptr_t pc);
void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
uintptr_t host_pc);
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 31aa320513..fdd6d3e0e4 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -536,6 +536,26 @@ static void cpu_exec_longjmp_cleanup(CPUState *cpu)
if (have_mmap_lock()) {
mmap_unlock();
}
+#else
+/*
+ * For softmmu, a tlb_fill fault during translation will land here,
+ * and we need to release any page locks held. In system mode we
+ * have one tcg_ctx per thread, so we know it was this cpu doing
+ * the translation.
+ *
+ * Alternative 1: Install a cleanup to be called via an exception
+ * handling safe longjmp. It seems plausible that all our hosts
+ * support such a thing. We'd have to properly register unwind info
+ * for the JIT for EH, rather that just for GDB.
+ *
+ * Alternative 2: Set and restore cpu->jmp_env in tb_gen_code to
+ * capture the cpu_loop_exit longjmp, perform the cleanup, and
+ * jump again to arrive here.
+ */
+if (tcg_ctx->gen_tb) {
+tb_unlock_pages(tcg_ctx->gen_tb);
+tcg_ctx->gen_tb = NULL;
+}
#endif
if (qemu_mutex_iothread_locked()) {
qemu_mutex_unlock_iothread();
diff --git a/accel/tcg/tb-maint.c b/accel/tcg/tb-maint.c
index 9566224d18..c406b2f7b7 100644
--- a/accel/tcg/tb-maint.c
+++ b/accel/tcg/tb-maint.c
@@ -70,17 +70,7 @@ typedef struct PageDesc PageDesc;
*/
#define assert_page_locked(pd) tcg_debug_assert(have_mmap_lock())
-static inline void page_lock_pair(PageDesc **ret_p1, tb_page_addr_t phys1,
- PageDesc **ret_p2, tb_page_addr_t phys2,
- bool alloc)
-{
-*ret_p1 = NULL;
-*ret_p2 = NULL;
-}
-
-static inline void page_unlock(PageDesc *pd) { }
-static inline void page_lock_tb(const TranslationBlock *tb) { }
-static inline void page_unlock_tb(const TranslationBlock *tb) { }
+static inline void tb_lock_pages(const TranslationBlock *tb) { }
/*
* For user-only, since we are protecting all of memory with a single lock,
@@ -96,7 +86,7 @@ static void tb_remove_all(void)
}
/* Call with mmap_lock held. */
-static void tb_record(TranslationBlock *tb, PageDesc *p1, PageDesc *p2)
+static void tb_record(TranslationBlock *tb)
{
vaddr addr;
int flags;
@@ -391,12 +381,108 @@ static void page_lock(PageDesc *pd)
qemu_spin_lock(&pd->lock);
}
+/* Like qemu_spin_trylock, returns false on success */
+static bool p
[PATCH v2 0/2] accel/tcg: Fix race condition in tb create/invalidate
Changes for v2: Adjust the change to cpu_exec_longjmp_cleanup, which should now survive user-only testing. I'm not really happy with it. I suggested two alternatives in the block comment, but neither of them are trivial. Please re-review, if you gave it a glance before. And if you have any bright suggestions short of "use real exceptions", I'm all ears. r~ Richard Henderson (2): accel/tcg: Split out cpu_exec_longjmp_cleanup accel/tcg: Always lock pages before translation accel/tcg/internal.h | 30 - accel/tcg/cpu-exec.c | 63 ++ accel/tcg/tb-maint.c | 242 -- accel/tcg/translate-all.c | 43 ++- accel/tcg/translator.c| 34 -- 5 files changed, 255 insertions(+), 157 deletions(-) -- 2.34.1
[PATCH v2 1/2] accel/tcg: Split out cpu_exec_longjmp_cleanup
Share the setjmp cleanup between cpu_exec_step_atomic
and cpu_exec_setjmp.
Reviewed-by: Richard W.M. Jones
Signed-off-by: Richard Henderson
---
accel/tcg/cpu-exec.c | 43 +++
1 file changed, 19 insertions(+), 24 deletions(-)
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index ba1890a373..31aa320513 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -526,6 +526,23 @@ static void cpu_exec_exit(CPUState *cpu)
}
}
+static void cpu_exec_longjmp_cleanup(CPUState *cpu)
+{
+/* Non-buggy compilers preserve this; assert the correct value. */
+g_assert(cpu == current_cpu);
+
+#ifdef CONFIG_USER_ONLY
+clear_helper_retaddr();
+if (have_mmap_lock()) {
+mmap_unlock();
+}
+#endif
+if (qemu_mutex_iothread_locked()) {
+qemu_mutex_unlock_iothread();
+}
+assert_no_pages_locked();
+}
+
void cpu_exec_step_atomic(CPUState *cpu)
{
CPUArchState *env = cpu->env_ptr;
@@ -568,16 +585,7 @@ void cpu_exec_step_atomic(CPUState *cpu)
cpu_tb_exec(cpu, tb, &tb_exit);
cpu_exec_exit(cpu);
} else {
-#ifdef CONFIG_USER_ONLY
-clear_helper_retaddr();
-if (have_mmap_lock()) {
-mmap_unlock();
-}
-#endif
-if (qemu_mutex_iothread_locked()) {
-qemu_mutex_unlock_iothread();
-}
-assert_no_pages_locked();
+cpu_exec_longjmp_cleanup(cpu);
}
/*
@@ -1023,20 +1031,7 @@ static int cpu_exec_setjmp(CPUState *cpu, SyncClocks *sc)
{
/* Prepare setjmp context for exception handling. */
if (unlikely(sigsetjmp(cpu->jmp_env, 0) != 0)) {
-/* Non-buggy compilers preserve this; assert the correct value. */
-g_assert(cpu == current_cpu);
-
-#ifdef CONFIG_USER_ONLY
-clear_helper_retaddr();
-if (have_mmap_lock()) {
-mmap_unlock();
-}
-#endif
-if (qemu_mutex_iothread_locked()) {
-qemu_mutex_unlock_iothread();
-}
-
-assert_no_pages_locked();
+cpu_exec_longjmp_cleanup(cpu);
}
return cpu_exec_loop(cpu, sc);
--
2.34.1
Re: [RFC PATCH] docs/interop: define STANDALONE protocol feature for vhost-user
On Thu, Jul 06, 2023 at 05:31:15PM +0100, Alex Bennée wrote: Alex Bennée writes: Currently QEMU has to know some details about the back-end to be able to setup the guest. While various parts of the setup can be delegated to the backend (for example config handling) this is a very piecemeal approach. This patch suggests a new feature flag (VHOST_USER_PROTOCOL_F_STANDALONE) which the back-end can advertise which allows a probe message to be sent to get all the details QEMU needs to know in one message. Signed-off-by: Alex Bennée --- Initial RFC for discussion. I intend to prototype this work with QEMU and one of the rust-vmm vhost-user daemons. --- docs/interop/vhost-user.rst | 37 + hw/virtio/vhost-user.c | 8 2 files changed, 45 insertions(+) diff --git a/docs/interop/vhost-user.rst b/docs/interop/vhost-user.rst index 5a070adbc1..85b1b1583a 100644 --- a/docs/interop/vhost-user.rst +++ b/docs/interop/vhost-user.rst @@ -275,6 +275,21 @@ Inflight description :queue size: a 16-bit size of virtqueues +Backend specifications +^^ + ++---+-+++ +| device id | config size | min_vqs | max_vqs | ++---+-+++ + +:device id: a 32-bit value holding the VirtIO device ID + +:config size: a 32-bit value holding the config size (see ``VHOST_USER_GET_CONFIG``) + +:min_vqs: a 32-bit value holding the minimum number of vqs supported + +:max_vqs: a 32-bit value holding the maximum number of vqs supported, must be >= min_vqs + C structure --- @@ -296,6 +311,7 @@ In QEMU the vhost-user message is implemented with the following struct: VhostUserConfig config; VhostUserVringArea area; VhostUserInflight inflight; + VhostUserBackendSpecs specs; }; } QEMU_PACKED VhostUserMsg; @@ -316,6 +332,7 @@ replies. Here is a list of the ones that do: * ``VHOST_USER_GET_VRING_BASE`` * ``VHOST_USER_SET_LOG_BASE`` (if ``VHOST_USER_PROTOCOL_F_LOG_SHMFD``) * ``VHOST_USER_GET_INFLIGHT_FD`` (if ``VHOST_USER_PROTOCOL_F_INFLIGHT_SHMFD``) +* ``VHOST_USER_GET_BACKEND_SPECS`` (if ``VHOST_USER_PROTOCOL_F_STANDALONE``) .. seealso:: @@ -885,6 +902,13 @@ Protocol features #define VHOST_USER_PROTOCOL_F_CONFIGURE_MEM_SLOTS 15 #define VHOST_USER_PROTOCOL_F_STATUS 16 #define VHOST_USER_PROTOCOL_F_XEN_MMAP 17 + #define VHOST_USER_PROTOCOL_F_STANDALONE 18 + +Some features are only valid in the presence of other supporting +features. In the case of ``VHOST_USER_PROTOCOL_F_STANDALONE`` the +backend must also support ``VHOST_USER_PROTOCOL_F_CONFIG`` and +``VHOST_USER_PROTOCOL_F_STATUS``. + This is too tight a restriction as not all VirtIO backends manage a config space. So I suggest the following: Some features are only valid in the presence of other supporting features. In the case of ``VHOST_USER_PROTOCOL_F_STANDALONE`` the backend must also support ``VHOST_USER_PROTOCOL_F_STATUS`` and optionally ``VHOST_USER_PROTOCOL_F_CONFIG`` (if there is a config space). Right, but could we describe it more as a kind of dependence between features? Something like this: Some features depend on others to be supported: * ``VHOST_USER_PROTOCOL_F_STANDALONE`` depends on: * ``VHOST_USER_PROTOCOL_F_STATUS`` * ``VHOST_USER_PROTOCOL_F_CONFIG`` (if there is a config space) Thanks, Stefano
Re: [PATCH 1/2] accel/tcg: Split out cpu_exec_longjmp_cleanup
On 7/7/23 09:09, Philippe Mathieu-Daudé wrote: On 6/7/23 19:05, Richard Henderson wrote: Share the setjmp cleanup between cpu_exec_step_atomic and cpu_exec_setjmp. Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 43 +++ 1 file changed, 19 insertions(+), 24 deletions(-) Reviewed-by: Philippe Mathieu-Daudé Sorry, Phil, missed applying this this morning before sending v2. I'll update the branch now. r~
Re: [PATCH v2 0/6] Add new CPU model GraniteRapids
Queued, thanks. Paolo
Re: [PATCH] vhost_vdpa: no need to fetch vring base when poweroff
On Fri, Jul 7, 2023 at 12:18 PM Zhu Lingshan wrote:
>
> In the poweroff routine, no need to fetch last available index.
>
> This commit also provides a better debug message in the vhost
> caller vhost_virtqueue_stop, because if vhost does not fetch
> the last avail idx successfully, maybe the device does not
> suspend, vhost will sync last avail idx to vring used idx as a
> work around, not a failure.
>
> Signed-off-by: Zhu Lingshan
CCing MST.
> ---
> hw/virtio/vhost-vdpa.c | 4
> hw/virtio/vhost.c | 2 +-
> 2 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/hw/virtio/vhost-vdpa.c b/hw/virtio/vhost-vdpa.c
> index 3c575a9a6e..f62952e1c7 100644
> --- a/hw/virtio/vhost-vdpa.c
> +++ b/hw/virtio/vhost-vdpa.c
> @@ -26,6 +26,7 @@
> #include "cpu.h"
> #include "trace.h"
> #include "qapi/error.h"
> +#include "sysemu/runstate.h"
>
> /*
> * Return one past the end of the end of section. Be careful with uint64_t
> @@ -1391,6 +1392,9 @@ static int vhost_vdpa_get_vring_base(struct vhost_dev
> *dev,
> struct vhost_vdpa *v = dev->opaque;
> int ret;
>
> +if (runstate_check(RUN_STATE_SHUTDOWN))
> +return 0;
> +
QEMU coding style mandates braces around the "if" body (CODING_STYLE.rst file).
Apart from that I think we should add a comment here. Something in the line of:
Some devices do not support the call properly, and we don't need to
retrieve the indexes if we're not migrating. Skip it in this case.
> if (v->shadow_vqs_enabled) {
> ring->num = virtio_queue_get_last_avail_idx(dev->vdev, ring->index);
> return 0;
> diff --git a/hw/virtio/vhost.c b/hw/virtio/vhost.c
> index 82394331bf..84712743e0 100644
> --- a/hw/virtio/vhost.c
> +++ b/hw/virtio/vhost.c
> @@ -1262,7 +1262,7 @@ void vhost_virtqueue_stop(struct vhost_dev *dev,
>
> r = dev->vhost_ops->vhost_get_vring_base(dev, &state);
> if (r < 0) {
> -VHOST_OPS_DEBUG(r, "vhost VQ %u ring restore failed: %d", idx, r);
> +VHOST_OPS_DEBUG(r, "sync last avail idx to the used idx for vhost VQ
> %u", idx);
Guest's used idx? Also, maybe it is worth splitting this in a separated patch.
Apart from the nitpicking, I think the general line of the patch is
the way to go :).
Thanks!
> /* Connection to the backend is broken, so let's sync internal
> * last avail idx to the device used idx.
> */
> --
> 2.39.3
>
Re: [PATCH v2 16/46] target/loongarch: Implement xvmadd/xvmsub/xvmaddw{ev/od}
On 6/30/23 08:58, Song Gao wrote:
+#define XVMADD_Q(NAME, FN, idx1, idx2)\
+static bool trans_## NAME(DisasContext *ctx, arg_vvv * a) \
+{ \
+TCGv_i64 rh, rl, arg1, arg2, th, tl; \
+int i;\
+ \
+CHECK_VEC;\
+ \
+rh = tcg_temp_new_i64(); \
+rl = tcg_temp_new_i64(); \
+arg1 = tcg_temp_new_i64();\
+arg2 = tcg_temp_new_i64();\
+th = tcg_temp_new_i64(); \
+tl = tcg_temp_new_i64(); \
+ \
+for (i = 0; i < 2; i++) { \
+get_vreg64(arg1, a->vj, idx1 + i * 2);\
+get_vreg64(arg2, a->vk, idx2 + i * 2);\
+get_vreg64(rh, a->vd, 1 + i * 2); \
+get_vreg64(rl, a->vd, 0 + i * 2); \
+ \
+tcg_gen_## FN ##_i64(tl, th, arg1, arg2); \
+tcg_gen_add2_i64(rl, rh, rl, rh, tl, th); \
+ \
+set_vreg64(rh, a->vd, 1 + i * 2); \
+set_vreg64(rl, a->vd, 0 + i * 2); \
+} \
+ \
+return true; \
+}
It's easier to debug if you make this a function, into which you pass parameters, like
tcg_gen_muls2_i64.
+len = (simd_oprsz(v) == 16) ? LSX_LEN : LASX_LEN; \
+for (i = 0; i < len / BIT; i++) { \
More of this.
r~
Re: [PATCH v2 17/46] target/loongarch; Implement xvdiv/xvmod
On 6/30/23 08:58, Song Gao wrote:
+len = (oprsz == 16) ? LSX_LEN : LASX_LEN; \
+for (i = 0; i < len / BIT; i++) { \
Similarly.
r~
Re: [PATCH v2] ppc/pnv: Add QME region for P10
Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks,
Daniel
On 7/7/23 04:12, Joel Stanley wrote:
The Quad Management Engine (QME) manages power related settings for its
quad. The xscom region is separate from the quad xscoms, therefore a new
region is added. The xscoms in a QME select a given core by selecting
the forth nibble.
Implement dummy reads for the stop state history (SSH) and special
wakeup (SPWU) registers. This quietens some sxcom errors when skiboot
boots on p10.
Power9 does not have a QME.
Signed-off-by: Joel Stanley
---
v2:
Clean up extra whitespace
Make realize quad specific so power9 doesn't end up with the qme region
---
include/hw/ppc/pnv_core.h | 4 ++
include/hw/ppc/pnv_xscom.h | 11 ++
hw/ppc/pnv.c | 3 ++
hw/ppc/pnv_core.c | 78 +-
4 files changed, 94 insertions(+), 2 deletions(-)
diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h
index 77ef00f47a72..c829a18aa9c6 100644
--- a/include/hw/ppc/pnv_core.h
+++ b/include/hw/ppc/pnv_core.h
@@ -65,6 +65,9 @@ struct PnvQuadClass {
const MemoryRegionOps *xscom_ops;
uint64_t xscom_size;
+
+const MemoryRegionOps *xscom_qme_ops;
+uint64_t xscom_qme_size;
};
#define TYPE_PNV_QUAD "powernv-cpu-quad"
@@ -79,5 +82,6 @@ struct PnvQuad {
uint32_t quad_id;
MemoryRegion xscom_regs;
+MemoryRegion xscom_qme_regs;
};
#endif /* PPC_PNV_CORE_H */
diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h
index a4c9d95dc5d3..9bc64635471e 100644
--- a/include/hw/ppc/pnv_xscom.h
+++ b/include/hw/ppc/pnv_xscom.h
@@ -127,6 +127,17 @@ struct PnvXScomInterfaceClass {
#define PNV10_XSCOM_EC(proc)\
((0x2 << 16) | ((1 << (3 - (proc))) << 12))
+#define PNV10_XSCOM_QME(chiplet) \
+(PNV10_XSCOM_EQ(chiplet) | (0xE << 16))
+
+/*
+ * Make the region larger by 0x1000 (instead of starting at an offset) so the
+ * modelled addresses start from 0
+ */
+#define PNV10_XSCOM_QME_BASE(core) \
+((uint64_t) PNV10_XSCOM_QME(PNV10_XSCOM_EQ_CHIPLET(core)))
+#define PNV10_XSCOM_QME_SIZE(0x8000 + 0x1000)
+
#define PNV10_XSCOM_EQ_BASE(core) \
((uint64_t) PNV10_XSCOM_EQ(PNV10_XSCOM_EQ_CHIPLET(core)))
#define PNV10_XSCOM_EQ_SIZE0x2
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 23740f9d0733..eb54f93986df 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1685,6 +1685,9 @@ static void pnv_chip_power10_quad_realize(Pnv10Chip
*chip10, Error **errp)
pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id),
&eq->xscom_regs);
+
+pnv_xscom_add_subregion(chip, PNV10_XSCOM_QME_BASE(eq->quad_id),
+&eq->xscom_qme_regs);
}
}
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index 1f244ed181d0..09eb2bf94b9e 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -493,7 +493,67 @@ static const MemoryRegionOps pnv_quad_power10_xscom_ops = {
.endianness = DEVICE_BIG_ENDIAN,
};
-static void pnv_quad_realize(DeviceState *dev, Error **errp)
+#define P10_QME_SPWU_HYP 0x83c
+#define P10_QME_SSH_HYP 0x82c
+
+static uint64_t pnv_qme_power10_xscom_read(void *opaque, hwaddr addr,
+unsigned int width)
+{
+uint32_t offset = addr >> 3;
+uint64_t val = -1;
+
+/*
+ * Forth nibble selects the core within a quad, mask it to process read
+ * for any core.
+ */
+switch (offset & ~0xf000) {
+case P10_QME_SPWU_HYP:
+case P10_QME_SSH_HYP:
+return 0;
+default:
+qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__,
+ offset);
+}
+
+return val;
+}
+
+static void pnv_qme_power10_xscom_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned int width)
+{
+uint32_t offset = addr >> 3;
+
+switch (offset) {
+default:
+qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__,
+ offset);
+}
+}
+
+static const MemoryRegionOps pnv_qme_power10_xscom_ops = {
+.read = pnv_qme_power10_xscom_read,
+.write = pnv_qme_power10_xscom_write,
+.valid.min_access_size = 8,
+.valid.max_access_size = 8,
+.impl.min_access_size = 8,
+.impl.max_access_size = 8,
+.endianness = DEVICE_BIG_ENDIAN,
+};
+
+static void pnv_quad_power9_realize(DeviceState *dev, Error **errp)
+{
+PnvQuad *eq = PNV_QUAD(dev);
+PnvQuadClass *pqc = PNV_QUAD_GET_CLASS(eq);
+char name[32];
+
+snprintf(name, sizeof(name), "xscom-quad.%d", eq->quad_id);
+pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev),
+ pqc->xscom_ops,
+ eq, name,
+ pqc->xscom_size);
+}
+
+static void pnv_quad_power10_realize(DeviceState *dev, Error **errp)
{
PnvQuad *eq = PNV_QUAD(dev);
PnvQ
Re: [PATCH v6] ppc: Enable 2nd DAWR support on p10
This one was a buzzer shot.
Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks,
Daniel
On 7/7/23 05:47, Shivaprasad G Bhat wrote:
From: Ravi Bangoria
As per the PAPR, bit 0 of byte 64 in pa-features property
indicates availability of 2nd DAWR registers. i.e. If this bit is set, 2nd
DAWR is present, otherwise not. Use KVM_CAP_PPC_DAWR1 capability to find
whether kvm supports 2nd DAWR or not. If it's supported, allow user to set
the pa-feature bit in guest DT using cap-dawr1 machine capability. Though,
watchpoint on powerpc TCG guest is not supported and thus 2nd DAWR is not
enabled for TCG mode.
Signed-off-by: Ravi Bangoria
Reviewed-by: Greg Kurz
Reviewed-by: Cédric Le Goater
Signed-off-by: Shivaprasad G Bhat
---
Changelog:
v5:
https://lore.kernel.org/all/20210412114433.129702-1-ravi.bango...@linux.ibm.com/
v5->v6:
- The other patches in the original series already merged.
- Rebased to the top of the tree. So, the gen_spr_book3s_310_dbg() is renamed
to register_book3s_310_dbg_sprs() and moved to cpu_init.c accordingly.
- No functional changes.
v4:
https://lore.kernel.org/r/20210406053833.282907-1-ravi.bango...@linux.ibm.com
v3->v4:
- Make error message more proper.
v3: https://lore.kernel.org/r/20210330095350.36309-1-ravi.bango...@linux.ibm.com
v3->v4:
- spapr_dt_pa_features(): POWER10 processor is compatible with 3.0
(PCR_COMPAT_3_00). No need to ppc_check_compat(3_10) for now as
ppc_check_compati(3_00) will also be true. ppc_check_compat(3_10)
can be added while introducing pa_features_310 in future.
- Use error_append_hint() for hints. Also add ERRP_GUARD().
- Add kvmppc_set_cap_dawr1() stub function for CONFIG_KVM=n.
v2:
https://lore.kernel.org/r/20210329041906.213991-1-ravi.bango...@linux.ibm.com
v2->v3:
- Don't introduce pa_features_310[], instead, reuse pa_features_300[]
for 3.1 guests, as there is no difference between initial values of
them atm.
- Call gen_spr_book3s_310_dbg() from init_proc_POWER10() instead of
init_proc_POWER8(). Also, Don't call gen_spr_book3s_207_dbg() from
gen_spr_book3s_310_dbg() as init_proc_POWER10() already calls it.
v1:
https://lore.kernel.org/r/20200723104220.314671-1-ravi.bango...@linux.ibm.com
v1->v2:
- Introduce machine capability cap-dawr1 to enable/disable
the feature. By default, 2nd DAWR is OFF for guests even
when host kvm supports it. User has to manually enable it
with -machine cap-dawr1=on if he wishes to use it.
- Split the header file changes into separate patch. (Sync
headers from v5.12-rc3)
[1] https://git.kernel.org/torvalds/c/bd1de1a0e6eff
hw/ppc/spapr.c |7 ++-
hw/ppc/spapr_caps.c| 32
include/hw/ppc/spapr.h |6 +-
target/ppc/cpu.h |2 ++
target/ppc/cpu_init.c | 15 +++
target/ppc/kvm.c | 12
target/ppc/kvm_ppc.h | 12
7 files changed, 84 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 54dbfd7fe9..1e54e0c719 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -241,7 +241,7 @@ static void spapr_dt_pa_features(SpaprMachineState *spapr,
0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
/* 54: DecFP, 56: DecI, 58: SHA */
0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
-/* 60: NM atomic, 62: RNG */
+/* 60: NM atomic, 62: RNG, 64: DAWR1 (ISA 3.1) */
0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
};
uint8_t *pa_features = NULL;
@@ -282,6 +282,9 @@ static void spapr_dt_pa_features(SpaprMachineState *spapr,
* in pa-features. So hide it from them. */
pa_features[40 + 2] &= ~0x80; /* Radix MMU */
}
+if (spapr_get_cap(spapr, SPAPR_CAP_DAWR1)) {
+pa_features[66] |= 0x80;
+}
_FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
}
@@ -2084,6 +2087,7 @@ static const VMStateDescription vmstate_spapr = {
&vmstate_spapr_cap_fwnmi,
&vmstate_spapr_fwnmi,
&vmstate_spapr_cap_rpt_invalidate,
+&vmstate_spapr_cap_dawr1,
NULL
}
};
@@ -4683,6 +4687,7 @@ static void spapr_machine_class_init(ObjectClass *oc,
void *data)
smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON;
smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON;
smc->default_caps.caps[SPAPR_CAP_RPT_INVALIDATE] = SPAPR_CAP_OFF;
+smc->default_caps.caps[SPAPR_CAP_DAWR1] = SPAPR_CAP_OFF;
/*
* This cap specifies whether the AIL 3 mode for
diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c
index 5a0755d34f..2f2cf4a250 100644
--- a/hw/ppc/spapr_caps.c
+++ b/hw/ppc/spapr_caps.c
@@ -655,6 +655,28 @@ static void cap_ail_mode_3_apply(SpaprMachineState *spapr,
}
}
+static void cap_dawr1_apply(SpaprMachineState *spapr, uint8_t val,
+ Error **errp)
+{
+ERR
Re: [PATCH v2 18/46] target/loongarch: Implement xvsat
On 6/30/23 08:58, Song Gao wrote:
+len = (simd_oprsz(v) == 16) ? LSX_LEN : LASX_LEN; \
+for (i = 0; i < len / BIT; i++) { \
Similarly.
r~
Re: [PATCH] net: add initial support for AF_XDP network backend
On 7/7/23 03:43, Jason Wang wrote: > On Fri, Jul 7, 2023 at 3:08 AM Stefan Hajnoczi wrote: >> >> On Wed, 5 Jul 2023 at 02:02, Jason Wang wrote: >>> >>> On Mon, Jul 3, 2023 at 5:03 PM Stefan Hajnoczi wrote: On Fri, 30 Jun 2023 at 09:41, Jason Wang wrote: > > On Thu, Jun 29, 2023 at 8:36 PM Stefan Hajnoczi > wrote: >> >> On Thu, 29 Jun 2023 at 07:26, Jason Wang wrote: >>> >>> On Wed, Jun 28, 2023 at 4:25 PM Stefan Hajnoczi >>> wrote: On Wed, 28 Jun 2023 at 10:19, Jason Wang wrote: > > On Wed, Jun 28, 2023 at 4:15 PM Stefan Hajnoczi > wrote: >> >> On Wed, 28 Jun 2023 at 09:59, Jason Wang wrote: >>> >>> On Wed, Jun 28, 2023 at 3:46 PM Stefan Hajnoczi >>> wrote: On Wed, 28 Jun 2023 at 05:28, Jason Wang wrote: > > On Wed, Jun 28, 2023 at 6:45 AM Ilya Maximets > wrote: >> >> On 6/27/23 04:54, Jason Wang wrote: >>> On Mon, Jun 26, 2023 at 9:17 PM Ilya Maximets >>> wrote: On 6/26/23 08:32, Jason Wang wrote: > On Sun, Jun 25, 2023 at 3:06 PM Jason Wang > wrote: >> >> On Fri, Jun 23, 2023 at 5:58 AM Ilya Maximets >> wrote: It is noticeably more performant than a tap with vhost=on in terms of PPS. So, that might be one case. Taking into account that just rcu lock and unlock in virtio-net code takes more time than a packet copy, some batching on QEMU side should improve performance significantly. And it shouldn't be too hard to implement. Performance over virtual interfaces may potentially be improved by creating a kernel thread for async Tx. Similarly to what io_uring allows. Currently Tx on non-zero-copy interfaces is synchronous, and that doesn't allow to scale well. >>> >>> Interestingly, actually, there are a lot of "duplication" >>> between >>> io_uring and AF_XDP: >>> >>> 1) both have similar memory model (user register) >>> 2) both use ring for communication >>> >>> I wonder if we can let io_uring talks directly to AF_XDP. >> >> Well, if we submit poll() in QEMU main loop via io_uring, then >> we can >> avoid cost of the synchronous Tx for non-zero-copy modes, i.e. >> for >> virtual interfaces. io_uring thread in the kernel will be able >> to >> perform transmission for us. > > It would be nice if we can use iothread/vhost other than the main > loop > even if io_uring can use kthreads. We can avoid the memory > translation > cost. The QEMU event loop (AioContext) has io_uring code (utils/fdmon-io_uring.c) but it's disabled at the moment. I'm working on patches to re-enable it and will probably send them in July. The patches also add an API to submit arbitrary io_uring operations so that you can do stuff besides file descriptor monitoring. Both the main loop and IOThreads will be able to use io_uring on Linux hosts. >>> >>> Just to make sure I understand. If we still need a copy from guest >>> to >>> io_uring buffer, we still need to go via memory API for GPA which >>> seems expensive. >>> >>> Vhost seems to be a shortcut for this. >> >> I'm not sure how exactly you're thinking of using io_uring. >> >> Simply using io_uring for the event loop (file descriptor monitoring) >> doesn't involve an extra buffer, but the packet payload still needs >> to >> reside in AF_XDP umem, so there is a copy between guest memory and >> umem. > > So there would be a translation from GPA to HVA (unless io_uring > support 2 stages) which needs to go via qemu memory core. And this > part seems to be very expensive according to my test in the past. Yes, but in the current approach where AF_XDP is implemented as a QEMU netdev, there is already QEMU device emulation (e.g. virtio-net) happening. So the GPA to HVA translation will happen anyway in device emulation. >>> >>> Just to make sure we're on the same page. >>> >>> I meant, AF_XDP can do more than e.g 10
[PULL 16/60] target/ppd: Remove unused define
From: BALATON Zoltan
Commit 7a3fe174b12d removed usage of POWERPC_SYSCALL_VECTORED, drop
the unused define as well.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Nicholas Piggin
Message-ID:
<50adc24f9d408882128e896d8a81a1a059c41836.1686868895.git.bala...@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza
---
target/ppc/translate.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 4766240927..db0ba49bdc 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -4486,7 +4486,6 @@ static void gen_hrfid(DisasContext *ctx)
#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
#else
#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
-#define POWERPC_SYSCALL_VECTORED POWERPC_EXCP_SYSCALL_VECTORED
#endif
static void gen_sc(DisasContext *ctx)
{
--
2.41.0
[PULL 29/60] pnv/xive: Print CPU target in all TIMA traces
From: Frederic Barrat
Add the CPU target in the trace when reading/writing the TIMA
space. It was already done for other TIMA ops (notify, accept, ...),
only missing for those 2. Useful for debug and even more now that we
experiment with SMT.
Signed-off-by: Frederic Barrat
Reviewed-by: Cédric Le Goater
Message-ID: <20230705110039.231148-1-fbar...@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza
---
hw/intc/trace-events | 4 ++--
hw/intc/xive.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index 5c6094c457..36ff71f947 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -265,8 +265,8 @@ xive_source_esb_read(uint64_t addr, uint32_t srcno,
uint64_t value) "@0x%"PRIx64
xive_source_esb_write(uint64_t addr, uint32_t srcno, uint64_t value)
"@0x%"PRIx64" IRQ 0x%x val=0x%"PRIx64
xive_router_end_notify(uint8_t end_blk, uint32_t end_idx, uint32_t end_data)
"END 0x%02x/0x%04x -> enqueue 0x%08x"
xive_router_end_escalate(uint8_t end_blk, uint32_t end_idx, uint8_t esc_blk,
uint32_t esc_idx, uint32_t end_data) "END 0x%02x/0x%04x -> escalate END
0x%02x/0x%04x data 0x%08x"
-xive_tctx_tm_write(uint64_t offset, unsigned int size, uint64_t value)
"@0x%"PRIx64" sz=%d val=0x%" PRIx64
-xive_tctx_tm_read(uint64_t offset, unsigned int size, uint64_t value)
"@0x%"PRIx64" sz=%d val=0x%" PRIx64
+xive_tctx_tm_write(uint32_t index, uint64_t offset, unsigned int size,
uint64_t value) "target=%d @0x%"PRIx64" sz=%d val=0x%" PRIx64
+xive_tctx_tm_read(uint32_t index, uint64_t offset, unsigned int size, uint64_t
value) "target=%d @0x%"PRIx64" sz=%d val=0x%" PRIx64
xive_presenter_notify(uint8_t nvt_blk, uint32_t nvt_idx, uint8_t ring) "found
NVT 0x%x/0x%x ring=0x%x"
xive_end_source_read(uint8_t end_blk, uint32_t end_idx, uint64_t addr) "END
0x%x/0x%x @0x%"PRIx64
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index c014e961a4..56670b2cac 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -566,7 +566,7 @@ void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX
*tctx, hwaddr offset,
{
const XiveTmOp *xto;
-trace_xive_tctx_tm_write(offset, size, value);
+trace_xive_tctx_tm_write(tctx->cs->cpu_index, offset, size, value);
/*
* TODO: check V bit in Q[0-3]W2
@@ -639,7 +639,7 @@ uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX
*tctx, hwaddr offset,
*/
ret = xive_tm_raw_read(tctx, offset, size);
out:
-trace_xive_tctx_tm_read(offset, size, ret);
+trace_xive_tctx_tm_read(tctx->cs->cpu_index, offset, size, ret);
return ret;
}
--
2.41.0
[PULL 05/60] mv64361: Add dummy gigabit ethernet PHY access registers
From: BALATON Zoltan We don't emulate the gigabit ethernet part of the chip but the MorphOS driver accesses these and expects to get some valid looking result otherwise it hangs. Add some minimal dummy implementation to avoid rhis. Signed-off-by: BALATON Zoltan Acked-by: Cédric Le Goater Message-ID: <20230605215145.29458746...@zero.eik.bme.hu> Signed-off-by: Daniel Henrique Barboza --- hw/pci-host/mv64361.c | 6 ++ hw/pci-host/mv643xx.h | 3 +++ 2 files changed, 9 insertions(+) diff --git a/hw/pci-host/mv64361.c b/hw/pci-host/mv64361.c index 19e8031a3f..01bd8c887f 100644 --- a/hw/pci-host/mv64361.c +++ b/hw/pci-host/mv64361.c @@ -541,6 +541,12 @@ static uint64_t mv64361_read(void *opaque, hwaddr addr, unsigned int size) } } break; +case MV64340_ETH_PHY_ADDR: +ret = 0x98; +break; +case MV64340_ETH_SMI: +ret = BIT(27); +break; case MV64340_CUNIT_ARBITER_CONTROL_REG: ret = 0x11ff | (s->gpp_int_level << 10); break; diff --git a/hw/pci-host/mv643xx.h b/hw/pci-host/mv643xx.h index cd26a43f18..f2e1baea88 100644 --- a/hw/pci-host/mv643xx.h +++ b/hw/pci-host/mv643xx.h @@ -656,6 +656,9 @@ /*Ethernet Unit Registers */ // +#define MV64340_ETH_PHY_ADDR0x2000 +#define MV64340_ETH_SMI 0x2004 + /***/ /* CUNIT Registers */ /***/ -- 2.41.0
[PULL 33/60] ppc/pnv: SMT support for powernv
From: Nicholas Piggin
Set the TIR default value with the SMT thread index, and place some
standard limits on SMT configurations. Now powernv is able to boot
skiboot and Linux with a SMT topology, including booting a KVM guest.
There are several SPRs and other features (e.g., broadcast msgsnd)
that are not implemented, but not used by OPAL or Linux and can be
added incrementally.
Reviewed-by: Cédric Le Goater
Tested-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
Message-ID: <20230705120631.27670-4-npig...@gmail.com>
Signed-off-by: Daniel Henrique Barboza
---
docs/system/ppc/powernv.rst | 5 -
hw/ppc/pnv.c| 12
hw/ppc/pnv_core.c | 13 +
3 files changed, 17 insertions(+), 13 deletions(-)
diff --git a/docs/system/ppc/powernv.rst b/docs/system/ppc/powernv.rst
index c8f9762342..09f3965858 100644
--- a/docs/system/ppc/powernv.rst
+++ b/docs/system/ppc/powernv.rst
@@ -195,11 +195,6 @@ Use a MTD drive to add a PNOR to the machine, and get a
NVRAM :
-drive file=./witherspoon.pnor,format=raw,if=mtd
-CAVEATS
-
- * No support for multiple HW threads (SMT=1). Same as pseries.
-
Maintainer contact information
--
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 5f25fe985a..23740f9d07 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -887,6 +887,18 @@ static void pnv_init(MachineState *machine)
pnv->num_chips =
machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads);
+
+if (machine->smp.threads > 8) {
+error_report("Cannot support more than 8 threads/core "
+ "on a powernv machine");
+exit(1);
+}
+if (!is_power_of_2(machine->smp.threads)) {
+error_report("Cannot support %d threads/core on a powernv"
+ "machine because it must be a power of 2",
+ machine->smp.threads);
+exit(1);
+}
/*
* TODO: should we decide on how many chips we can create based
* on #cores and Venice vs. Murano vs. Naples chip type etc...,
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index b7223bb445..8a72171ce0 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -218,12 +218,13 @@ static const MemoryRegionOps pnv_core_power10_xscom_ops =
{
.endianness = DEVICE_BIG_ENDIAN,
};
-static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU *cpu, Error **errp)
+static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU *cpu, Error **errp,
+ int thread_index)
{
CPUPPCState *env = &cpu->env;
int core_pir;
-int thread_index = 0; /* TODO: TCG supports only one thread */
ppc_spr_t *pir = &env->spr_cb[SPR_PIR];
+ppc_spr_t *tir = &env->spr_cb[SPR_TIR];
Error *local_err = NULL;
PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip);
@@ -239,11 +240,7 @@ static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU
*cpu, Error **errp)
core_pir = object_property_get_uint(OBJECT(pc), "pir", &error_abort);
-/*
- * The PIR of a thread is the core PIR + the thread index. We will
- * need to find a way to get the thread index when TCG supports
- * more than 1. We could use the object name ?
- */
+tir->default_value = thread_index;
pir->default_value = core_pir + thread_index;
/* Set time-base frequency to 512 MHz */
@@ -292,7 +289,7 @@ static void pnv_core_realize(DeviceState *dev, Error **errp)
}
for (j = 0; j < cc->nr_threads; j++) {
-pnv_core_cpu_realize(pc, pc->threads[j], &local_err);
+pnv_core_cpu_realize(pc, pc->threads[j], &local_err, j);
if (local_err) {
goto err;
}
--
2.41.0
[PULL 04/60] target/ppc: Only generate decodetree files when TCG is enabled
From: Philippe Mathieu-Daudé
No need to generate TCG-specific decodetree files
when TCG is disabled.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Greg Kurz
Reviewed-by: Richard Henderson
Message-ID: <20230626140100.67941-1-phi...@linaro.org>
Signed-off-by: Daniel Henrique Barboza
---
target/ppc/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/meson.build b/target/ppc/meson.build
index a69f174f41..4c2635039e 100644
--- a/target/ppc/meson.build
+++ b/target/ppc/meson.build
@@ -28,7 +28,7 @@ gen = [
extra_args: ['--static-decode=decode_insn64',
'--insnwidth=64']),
]
-ppc_ss.add(gen)
+ppc_ss.add(when: 'CONFIG_TCG', if_true: gen)
ppc_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false:
files('kvm-stub.c'))
ppc_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user_only_helper.c'))
--
2.41.0
[PULL 15/60] target/ppc: Remove some more local CPUState variables only used once
From: BALATON Zoltan
Some helpers only have a CPUState local to call cpu_interrupt_exittb()
but we can use env_cpu for that and remove the local.
Signed-off-by: BALATON Zoltan
Acked-by: Nicholas Piggin
Message-ID:
Signed-off-by: Daniel Henrique Barboza
---
target/ppc/excp_helper.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index d1d3d089a6..b2cff4e7eb 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -2653,8 +2653,7 @@ void helper_store_msr(CPUPPCState *env, target_ulong val)
uint32_t excp = hreg_store_msr(env, val, 0);
if (excp != 0) {
-CPUState *cs = env_cpu(env);
-cpu_interrupt_exittb(cs);
+cpu_interrupt_exittb(env_cpu(env));
raise_exception(env, excp);
}
}
@@ -2691,8 +2690,6 @@ void helper_pminsn(CPUPPCState *env, uint32_t insn)
static void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr)
{
-CPUState *cs = env_cpu(env);
-
/* MSR:POW cannot be set by any form of rfi */
msr &= ~(1ULL << MSR_POW);
@@ -2716,7 +2713,7 @@ static void do_rfi(CPUPPCState *env, target_ulong nip,
target_ulong msr)
* No need to raise an exception here, as rfi is always the last
* insn of a TB
*/
-cpu_interrupt_exittb(cs);
+cpu_interrupt_exittb(env_cpu(env));
/* Reset the reservation */
env->reserve_addr = -1;
--
2.41.0
[PULL 35/60] ppc440: Change ppc460ex_pcie_init() parameter type
From: BALATON Zoltan
Change parameter of ppc460ex_pcie_init() from env to cpu to allow
further refactoring.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
Message-ID:
<1695d7cc1a9f1070ab498c078916e2389d6e9469.1688586835.git.bala...@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc440.h| 2 +-
hw/ppc/ppc440_uc.c | 7 ---
hw/ppc/sam460ex.c | 2 +-
3 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/hw/ppc/ppc440.h b/hw/ppc/ppc440.h
index 7c24db8504..ae42bcf0c8 100644
--- a/hw/ppc/ppc440.h
+++ b/hw/ppc/ppc440.h
@@ -18,6 +18,6 @@ void ppc4xx_cpr_init(CPUPPCState *env);
void ppc4xx_sdr_init(CPUPPCState *env);
void ppc4xx_ahb_init(CPUPPCState *env);
void ppc4xx_dma_init(CPUPPCState *env, int dcr_base);
-void ppc460ex_pcie_init(CPUPPCState *env);
+void ppc460ex_pcie_init(PowerPCCPU *cpu);
#endif /* PPC440_H */
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index 651263926e..8eb985d714 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -17,6 +17,7 @@
#include "hw/qdev-properties.h"
#include "hw/pci/pci.h"
#include "sysemu/reset.h"
+#include "cpu.h"
#include "ppc440.h"
/*/
@@ -1108,17 +1109,17 @@ static void
ppc460ex_pcie_register_dcrs(PPC460EXPCIEState *s, CPUPPCState *env)
&dcr_read_pcie, &dcr_write_pcie);
}
-void ppc460ex_pcie_init(CPUPPCState *env)
+void ppc460ex_pcie_init(PowerPCCPU *cpu)
{
DeviceState *dev;
dev = qdev_new(TYPE_PPC460EX_PCIE_HOST);
qdev_prop_set_int32(dev, "dcrn-base", DCRN_PCIE0_BASE);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
-ppc460ex_pcie_register_dcrs(PPC460EX_PCIE_HOST(dev), env);
+ppc460ex_pcie_register_dcrs(PPC460EX_PCIE_HOST(dev), &cpu->env);
dev = qdev_new(TYPE_PPC460EX_PCIE_HOST);
qdev_prop_set_int32(dev, "dcrn-base", DCRN_PCIE1_BASE);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
-ppc460ex_pcie_register_dcrs(PPC460EX_PCIE_HOST(dev), env);
+ppc460ex_pcie_register_dcrs(PPC460EX_PCIE_HOST(dev), &cpu->env);
}
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index cf065aae0e..aaa8d2f4a5 100644
--- a/hw/ppc/sam460ex.c
+++ b/hw/ppc/sam460ex.c
@@ -422,7 +422,7 @@ static void sam460ex_init(MachineState *machine)
usb_create_simple(usb_bus_find(-1), "usb-mouse");
/* PCI bus */
-ppc460ex_pcie_init(env);
+ppc460ex_pcie_init(cpu);
/* All PCI irqs are connected to the same UIC pin (cf. UBoot source) */
dev = sysbus_create_simple("ppc440-pcix-host", 0xc0ec0,
qdev_get_gpio_in(uic[1], 0));
--
2.41.0
[PULL 32/60] target/ppc: SMT support for the HID SPR
From: Nicholas Piggin
HID is a per-core shared register, skiboot sets this (e.g., setting
HILE) on one thread and that must affect all threads of the core.
Reviewed-by: Cédric Le Goater
Tested-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
Message-ID: <20230705120631.27670-3-npig...@gmail.com>
Signed-off-by: Daniel Henrique Barboza
---
target/ppc/cpu_init.c| 2 +-
target/ppc/helper.h | 1 +
target/ppc/misc_helper.c | 21 +
target/ppc/spr_common.h | 1 +
target/ppc/translate.c | 16
5 files changed, 40 insertions(+), 1 deletion(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 905a59aea9..720aad9e05 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -5638,7 +5638,7 @@ static void register_power_common_book4_sprs(CPUPPCState
*env)
spr_register_hv(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_core_write_generic,
0x);
spr_register_hv(env, SPR_TSCR, "TSCR",
SPR_NOACCESS, SPR_NOACCESS,
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 828f7844c8..abec6fe341 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -704,6 +704,7 @@ DEF_HELPER_3(store_dcr, void, env, tl, tl)
DEF_HELPER_2(load_dump_spr, void, env, i32)
DEF_HELPER_2(store_dump_spr, void, env, i32)
+DEF_HELPER_3(spr_core_write_generic, void, env, i32, tl)
DEF_HELPER_3(spr_write_CTRL, void, env, i32, tl)
DEF_HELPER_4(fscr_facility_check, void, env, i32, i32, i32)
diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
index 26e546cc9c..692d058665 100644
--- a/target/ppc/misc_helper.c
+++ b/target/ppc/misc_helper.c
@@ -43,6 +43,27 @@ void helper_store_dump_spr(CPUPPCState *env, uint32_t sprn)
env->spr[sprn]);
}
+void helper_spr_core_write_generic(CPUPPCState *env, uint32_t sprn,
+ target_ulong val)
+{
+CPUState *cs = env_cpu(env);
+CPUState *ccs;
+uint32_t nr_threads = cs->nr_threads;
+uint32_t core_id = env->spr[SPR_PIR] & ~(nr_threads - 1);
+
+assert(core_id == env->spr[SPR_PIR] - env->spr[SPR_TIR]);
+
+if (nr_threads == 1) {
+env->spr[sprn] = val;
+return;
+}
+
+THREAD_SIBLING_FOREACH(cs, ccs) {
+CPUPPCState *cenv = &POWERPC_CPU(ccs)->env;
+cenv->spr[sprn] = val;
+}
+}
+
void helper_spr_write_CTRL(CPUPPCState *env, uint32_t sprn,
target_ulong val)
{
diff --git a/target/ppc/spr_common.h b/target/ppc/spr_common.h
index fbf52123b5..5995070eaf 100644
--- a/target/ppc/spr_common.h
+++ b/target/ppc/spr_common.h
@@ -82,6 +82,7 @@ void spr_noaccess(DisasContext *ctx, int gprn, int sprn);
void spr_read_generic(DisasContext *ctx, int gprn, int sprn);
void spr_write_generic(DisasContext *ctx, int sprn, int gprn);
void spr_write_generic32(DisasContext *ctx, int sprn, int gprn);
+void spr_core_write_generic(DisasContext *ctx, int sprn, int gprn);
void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn);
void spr_write_MMCR1(DisasContext *ctx, int sprn, int gprn);
void spr_write_PMC(DisasContext *ctx, int sprn, int gprn);
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 4556297ab5..e6a0709066 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -438,6 +438,22 @@ void spr_write_generic32(DisasContext *ctx, int sprn, int
gprn)
#endif
}
+void spr_core_write_generic(DisasContext *ctx, int sprn, int gprn)
+{
+if (!(ctx->flags & POWERPC_FLAG_SMT)) {
+spr_write_generic(ctx, sprn, gprn);
+return;
+}
+
+if (!gen_serialize(ctx)) {
+return;
+}
+
+gen_helper_spr_core_write_generic(cpu_env, tcg_constant_i32(sprn),
+ cpu_gpr[gprn]);
+spr_store_dump_spr(sprn);
+}
+
static void spr_write_CTRL_ST(DisasContext *ctx, int sprn, int gprn)
{
/* This does not implement >1 thread */
--
2.41.0
[PULL 17/60] target/ppc: Get CPUState in one step
From: BALATON Zoltan
We can get CPUState from env with env_cpu without going through
PowerPCCPU and casting that.
Signed-off-by: BALATON Zoltan
Acked-by: Nicholas Piggin
Message-ID:
<28424220f37f51ce97f24cadc7538a9c0d16cb45.1686868895.git.bala...@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza
---
target/ppc/excp_helper.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index b2cff4e7eb..354392668e 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -1770,8 +1770,8 @@ static int p7_interrupt_powersave(CPUPPCState *env)
static int p7_next_unmasked_interrupt(CPUPPCState *env)
{
-PowerPCCPU *cpu = env_archcpu(env);
-CPUState *cs = CPU(cpu);
+CPUState *cs = env_cpu(env);
+
/* Ignore MSR[EE] when coming out of some power management states */
bool msr_ee = FIELD_EX64(env->msr, MSR, EE) || env->resume_as_sreset;
@@ -1860,8 +1860,8 @@ static int p8_interrupt_powersave(CPUPPCState *env)
static int p8_next_unmasked_interrupt(CPUPPCState *env)
{
-PowerPCCPU *cpu = env_archcpu(env);
-CPUState *cs = CPU(cpu);
+CPUState *cs = env_cpu(env);
+
/* Ignore MSR[EE] when coming out of some power management states */
bool msr_ee = FIELD_EX64(env->msr, MSR, EE) || env->resume_as_sreset;
@@ -1981,8 +1981,8 @@ static int p9_interrupt_powersave(CPUPPCState *env)
static int p9_next_unmasked_interrupt(CPUPPCState *env)
{
-PowerPCCPU *cpu = env_archcpu(env);
-CPUState *cs = CPU(cpu);
+CPUState *cs = env_cpu(env);
+
/* Ignore MSR[EE] when coming out of some power management states */
bool msr_ee = FIELD_EX64(env->msr, MSR, EE) || env->resume_as_sreset;
@@ -2675,9 +2675,8 @@ void helper_scv(CPUPPCState *env, uint32_t lev)
void helper_pminsn(CPUPPCState *env, uint32_t insn)
{
-CPUState *cs;
+CPUState *cs = env_cpu(env);
-cs = env_cpu(env);
cs->halted = 1;
/* Condition for waking up at 0x100 */
--
2.41.0
[PULL 42/60] ppc440: Remove ppc460ex_pcie_init legacy init function
From: BALATON Zoltan
After previous changes we can now remove the legacy init function and
move the device creation to board code.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
Message-ID:
<29aafeea9f1c871c739600a7b093c5456e8a1dc8.1688586835.git.bala...@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc440.h | 1 -
hw/ppc/ppc440_uc.c | 21 -
hw/ppc/sam460ex.c | 17 -
include/hw/ppc/ppc4xx.h | 1 +
4 files changed, 17 insertions(+), 23 deletions(-)
diff --git a/hw/ppc/ppc440.h b/hw/ppc/ppc440.h
index ae42bcf0c8..909373fb38 100644
--- a/hw/ppc/ppc440.h
+++ b/hw/ppc/ppc440.h
@@ -18,6 +18,5 @@ void ppc4xx_cpr_init(CPUPPCState *env);
void ppc4xx_sdr_init(CPUPPCState *env);
void ppc4xx_ahb_init(CPUPPCState *env);
void ppc4xx_dma_init(CPUPPCState *env, int dcr_base);
-void ppc460ex_pcie_init(PowerPCCPU *cpu);
#endif /* PPC440_H */
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index b74b2212fa..4181c843a8 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -770,7 +770,6 @@ void ppc4xx_dma_init(CPUPPCState *env, int dcr_base)
*/
#include "hw/pci/pcie_host.h"
-#define TYPE_PPC460EX_PCIE_HOST "ppc460ex-pcie-host"
OBJECT_DECLARE_SIMPLE_TYPE(PPC460EXPCIEState, PPC460EX_PCIE_HOST)
struct PPC460EXPCIEState {
@@ -799,9 +798,6 @@ struct PPC460EXPCIEState {
uint32_t cfg;
};
-#define DCRN_PCIE0_BASE 0x100
-#define DCRN_PCIE1_BASE 0x120
-
enum {
PEGPL_CFGBAH = 0x0,
PEGPL_CFGBAL,
@@ -1096,20 +1092,3 @@ static void ppc460ex_pcie_register(void)
}
type_init(ppc460ex_pcie_register)
-
-void ppc460ex_pcie_init(PowerPCCPU *cpu)
-{
-DeviceState *dev;
-
-dev = qdev_new(TYPE_PPC460EX_PCIE_HOST);
-qdev_prop_set_int32(dev, "busnum", 0);
-qdev_prop_set_int32(dev, "dcrn-base", DCRN_PCIE0_BASE);
-object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort);
-sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
-
-dev = qdev_new(TYPE_PPC460EX_PCIE_HOST);
-qdev_prop_set_int32(dev, "busnum", 1);
-qdev_prop_set_int32(dev, "dcrn-base", DCRN_PCIE1_BASE);
-object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort);
-sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
-}
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index aaa8d2f4a5..1bb23bb18b 100644
--- a/hw/ppc/sam460ex.c
+++ b/hw/ppc/sam460ex.c
@@ -45,6 +45,9 @@
/* dd bs=1 skip=$(($(stat -c '%s' updater/updater-460) - 0x8)) \
if=updater/updater-460 of=u-boot-sam460-20100605.bin */
+#define PCIE0_DCRN_BASE 0x100
+#define PCIE1_DCRN_BASE 0x120
+
/* from Sam460 U-Boot include/configs/Sam460ex.h */
#define FLASH_BASE 0xfff0
#define FLASH_BASE_H 0x4
@@ -421,8 +424,20 @@ static void sam460ex_init(MachineState *machine)
usb_create_simple(usb_bus_find(-1), "usb-kbd");
usb_create_simple(usb_bus_find(-1), "usb-mouse");
+/* PCIe buses */
+dev = qdev_new(TYPE_PPC460EX_PCIE_HOST);
+qdev_prop_set_int32(dev, "busnum", 0);
+qdev_prop_set_int32(dev, "dcrn-base", PCIE0_DCRN_BASE);
+object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort);
+sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+
+dev = qdev_new(TYPE_PPC460EX_PCIE_HOST);
+qdev_prop_set_int32(dev, "busnum", 1);
+qdev_prop_set_int32(dev, "dcrn-base", PCIE1_DCRN_BASE);
+object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort);
+sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+
/* PCI bus */
-ppc460ex_pcie_init(cpu);
/* All PCI irqs are connected to the same UIC pin (cf. UBoot source) */
dev = sysbus_create_simple("ppc440-pcix-host", 0xc0ec0,
qdev_get_gpio_in(uic[1], 0));
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index f8c86e09ec..39ca602442 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -30,6 +30,7 @@
#include "hw/sysbus.h"
#define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
+#define TYPE_PPC460EX_PCIE_HOST "ppc460ex-pcie-host"
/*
* Generic DCR device
--
2.41.0
[PULL 28/60] ppc/pegasos2: Add support for -initrd command line option
From: BALATON Zoltan
This also changes type of sz local variable to ssize_t because it is
used to store return value of load_elf() and load_image_targphys() that
return ssize_t.
Signed-off-by: BALATON Zoltan
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20230704181920.27b58746...@zero.eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/pegasos2.c | 32 +++-
1 file changed, 31 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c
index af5489de26..9c9944188b 100644
--- a/hw/ppc/pegasos2.c
+++ b/hw/ppc/pegasos2.c
@@ -44,6 +44,8 @@
#define PROM_ADDR 0xfff0
#define PROM_SIZE 0x8
+#define INITRD_MIN_ADDR 0x60
+
#define KVMPPC_HCALL_BASE0xf000
#define KVMPPC_H_RTAS(KVMPPC_HCALL_BASE + 0x0)
#define KVMPPC_H_VOF_CLIENT (KVMPPC_HCALL_BASE + 0x5)
@@ -80,6 +82,8 @@ struct Pegasos2MachineState {
uint64_t kernel_addr;
uint64_t kernel_entry;
uint64_t kernel_size;
+uint64_t initrd_addr;
+uint64_t initrd_size;
};
static void *build_fdt(MachineState *machine, int *fdt_size);
@@ -117,7 +121,8 @@ static void pegasos2_init(MachineState *machine)
I2CBus *i2c_bus;
const char *fwname = machine->firmware ?: PROM_FILENAME;
char *filename;
-int i, sz;
+int i;
+ssize_t sz;
uint8_t *spd_data;
/* init CPU */
@@ -213,6 +218,20 @@ static void pegasos2_init(MachineState *machine)
warn_report("Using Virtual OpenFirmware but no -kernel option.");
}
+if (machine->initrd_filename) {
+pm->initrd_addr = pm->kernel_addr + pm->kernel_size + 64 * KiB;
+pm->initrd_addr = ROUND_UP(pm->initrd_addr, 4);
+pm->initrd_addr = MAX(pm->initrd_addr, INITRD_MIN_ADDR);
+sz = load_image_targphys(machine->initrd_filename, pm->initrd_addr,
+ machine->ram_size - pm->initrd_addr);
+if (sz <= 0) {
+error_report("Could not load initrd '%s'",
+ machine->initrd_filename);
+exit(1);
+}
+pm->initrd_size = sz;
+}
+
if (!pm->vof && machine->kernel_cmdline && machine->kernel_cmdline[0]) {
warn_report("Option -append may be ineffective with -bios.");
}
@@ -335,6 +354,11 @@ static void pegasos2_machine_reset(MachineState *machine,
ShutdownCause reason)
error_report("Memory for kernel is in use");
exit(1);
}
+if (pm->initrd_size &&
+vof_claim(pm->vof, pm->initrd_addr, pm->initrd_size, 0) == -1) {
+error_report("Memory for initrd is in use");
+exit(1);
+}
fdt = build_fdt(machine, &sz);
/* FIXME: VOF assumes entry is same as load address */
d[0] = cpu_to_be64(pm->kernel_entry);
@@ -966,6 +990,12 @@ static void *build_fdt(MachineState *machine, int
*fdt_size)
qemu_fdt_setprop_string(fdt, "/memory@0", "name", "memory");
qemu_fdt_add_subnode(fdt, "/chosen");
+if (pm->initrd_addr && pm->initrd_size) {
+qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
+ pm->initrd_addr + pm->initrd_size);
+qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
+ pm->initrd_addr);
+}
qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
machine->kernel_cmdline ?: "");
qemu_fdt_setprop_string(fdt, "/chosen", "name", "chosen");
--
2.41.0
[PULL 48/60] ppc440_pcix: Rename QOM type define abd move it to common header
From: BALATON Zoltan
Rename TYPE_PPC440_PCIX_HOST_BRIDGE to better match its string value,
move it to common header and use it also in sam460ex to replace hard
coded type name.
Signed-off-by: BALATON Zoltan
Reviewed-by: Daniel Henrique Barboza
Message-ID:
<1a1c3fe4b120f345d1005ad7ceca4500783691f7.1688641673.git.bala...@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc440_pcix.c| 9 -
hw/ppc/sam460ex.c | 2 +-
include/hw/ppc/ppc4xx.h | 1 +
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/ppc/ppc440_pcix.c b/hw/ppc/ppc440_pcix.c
index 9321ca0abd..672090de94 100644
--- a/hw/ppc/ppc440_pcix.c
+++ b/hw/ppc/ppc440_pcix.c
@@ -45,8 +45,7 @@ struct PLBInMap {
MemoryRegion mr;
};
-#define TYPE_PPC440_PCIX_HOST_BRIDGE "ppc440-pcix-host"
-OBJECT_DECLARE_SIMPLE_TYPE(PPC440PCIXState, PPC440_PCIX_HOST_BRIDGE)
+OBJECT_DECLARE_SIMPLE_TYPE(PPC440PCIXState, PPC440_PCIX_HOST)
#define PPC440_PCIX_NR_POMS 3
#define PPC440_PCIX_NR_PIMS 3
@@ -399,7 +398,7 @@ static const MemoryRegionOps pci_reg_ops = {
static void ppc440_pcix_reset(DeviceState *dev)
{
-struct PPC440PCIXState *s = PPC440_PCIX_HOST_BRIDGE(dev);
+struct PPC440PCIXState *s = PPC440_PCIX_HOST(dev);
int i;
for (i = 0; i < PPC440_PCIX_NR_POMS; i++) {
@@ -489,7 +488,7 @@ static void ppc440_pcix_realize(DeviceState *dev, Error
**errp)
PCIHostState *h;
h = PCI_HOST_BRIDGE(dev);
-s = PPC440_PCIX_HOST_BRIDGE(dev);
+s = PPC440_PCIX_HOST(dev);
sysbus_init_irq(sbd, &s->irq);
memory_region_init(&s->busmem, OBJECT(dev), "pci-mem", UINT64_MAX);
@@ -529,7 +528,7 @@ static void ppc440_pcix_class_init(ObjectClass *klass, void
*data)
}
static const TypeInfo ppc440_pcix_info = {
-.name = TYPE_PPC440_PCIX_HOST_BRIDGE,
+.name = TYPE_PPC440_PCIX_HOST,
.parent= TYPE_PCI_HOST_BRIDGE,
.instance_size = sizeof(PPC440PCIXState),
.class_init= ppc440_pcix_class_init,
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index 7da38bd58e..1e615b8d35 100644
--- a/hw/ppc/sam460ex.c
+++ b/hw/ppc/sam460ex.c
@@ -438,7 +438,7 @@ static void sam460ex_init(MachineState *machine)
/* PCI bus */
/* All PCI irqs are connected to the same UIC pin (cf. UBoot source) */
-dev = sysbus_create_simple("ppc440-pcix-host", 0xc0ec0,
+dev = sysbus_create_simple(TYPE_PPC440_PCIX_HOST, 0xc0ec0,
qdev_get_gpio_in(uic[1], 0));
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, 0xc0800);
pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0"));
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index 766d575e86..ea7740239b 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -31,6 +31,7 @@
#define TYPE_PPC4xx_HOST_BRIDGE "ppc4xx-host-bridge"
#define TYPE_PPC4xx_PCI_HOST "ppc4xx-pci-host"
+#define TYPE_PPC440_PCIX_HOST "ppc440-pcix-host"
#define TYPE_PPC460EX_PCIE_HOST "ppc460ex-pcie-host"
/*
--
2.41.0
[PULL 10/60] tests/avocado: record_replay test for ppc powernv machine
From: Nicholas Piggin
The powernv machine can boot Linux to VFS mount with icount enabled.
Add a test case for it.
Signed-off-by: Nicholas Piggin
Reviewed-by: Cédric Le Goater
Message-ID: <20230625103700.8992-2-npig...@gmail.com>
Signed-off-by: Daniel Henrique Barboza
---
tests/avocado/replay_kernel.py | 17 +
1 file changed, 17 insertions(+)
diff --git a/tests/avocado/replay_kernel.py b/tests/avocado/replay_kernel.py
index fe1e901f4b..79c607b0e7 100644
--- a/tests/avocado/replay_kernel.py
+++ b/tests/avocado/replay_kernel.py
@@ -259,6 +259,23 @@ def test_ppc64_pseries(self):
console_pattern = 'Kernel command line: %s' % kernel_command_line
self.run_rr(kernel_path, kernel_command_line, console_pattern)
+def test_ppc64_powernv(self):
+"""
+:avocado: tags=arch:ppc64
+:avocado: tags=machine:powernv
+:avocado: tags=accel:tcg
+"""
+kernel_url = ('https://archives.fedoraproject.org/pub/archive'
+ '/fedora-secondary/releases/29/Everything/ppc64le/os'
+ '/ppc/ppc64/vmlinuz')
+kernel_hash = '3fe04abfc852b66653b8c3c897a59a689270bc77'
+kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
+
+kernel_command_line = self.KERNEL_COMMON_COMMAND_LINE + \
+ 'console=tty0 console=hvc0'
+console_pattern = 'VFS: Cannot open root device'
+self.run_rr(kernel_path, kernel_command_line, console_pattern)
+
def test_m68k_q800(self):
"""
:avocado: tags=arch:m68k
--
2.41.0
[PULL 60/60] ppc: Enable 2nd DAWR support on p10
From: Ravi Bangoria
As per the PAPR, bit 0 of byte 64 in pa-features property
indicates availability of 2nd DAWR registers. i.e. If this bit is set, 2nd
DAWR is present, otherwise not. Use KVM_CAP_PPC_DAWR1 capability to find
whether kvm supports 2nd DAWR or not. If it's supported, allow user to set
the pa-feature bit in guest DT using cap-dawr1 machine capability. Though,
watchpoint on powerpc TCG guest is not supported and thus 2nd DAWR is not
enabled for TCG mode.
Signed-off-by: Ravi Bangoria
Reviewed-by: Greg Kurz
Reviewed-by: Cédric Le Goater
Signed-off-by: Shivaprasad G Bhat
Message-ID: <168871963321.58984.15628382614621248470.stgit@ltcd89-lp2>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/spapr.c | 7 ++-
hw/ppc/spapr_caps.c| 32
include/hw/ppc/spapr.h | 6 +-
target/ppc/cpu.h | 2 ++
target/ppc/cpu_init.c | 15 +++
target/ppc/kvm.c | 12
target/ppc/kvm_ppc.h | 12
7 files changed, 84 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 54dbfd7fe9..1e54e0c719 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -241,7 +241,7 @@ static void spapr_dt_pa_features(SpaprMachineState *spapr,
0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
/* 54: DecFP, 56: DecI, 58: SHA */
0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
-/* 60: NM atomic, 62: RNG */
+/* 60: NM atomic, 62: RNG, 64: DAWR1 (ISA 3.1) */
0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
};
uint8_t *pa_features = NULL;
@@ -282,6 +282,9 @@ static void spapr_dt_pa_features(SpaprMachineState *spapr,
* in pa-features. So hide it from them. */
pa_features[40 + 2] &= ~0x80; /* Radix MMU */
}
+if (spapr_get_cap(spapr, SPAPR_CAP_DAWR1)) {
+pa_features[66] |= 0x80;
+}
_FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
}
@@ -2084,6 +2087,7 @@ static const VMStateDescription vmstate_spapr = {
&vmstate_spapr_cap_fwnmi,
&vmstate_spapr_fwnmi,
&vmstate_spapr_cap_rpt_invalidate,
+&vmstate_spapr_cap_dawr1,
NULL
}
};
@@ -4683,6 +4687,7 @@ static void spapr_machine_class_init(ObjectClass *oc,
void *data)
smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON;
smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON;
smc->default_caps.caps[SPAPR_CAP_RPT_INVALIDATE] = SPAPR_CAP_OFF;
+smc->default_caps.caps[SPAPR_CAP_DAWR1] = SPAPR_CAP_OFF;
/*
* This cap specifies whether the AIL 3 mode for
diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c
index 5a0755d34f..2f2cf4a250 100644
--- a/hw/ppc/spapr_caps.c
+++ b/hw/ppc/spapr_caps.c
@@ -655,6 +655,28 @@ static void cap_ail_mode_3_apply(SpaprMachineState *spapr,
}
}
+static void cap_dawr1_apply(SpaprMachineState *spapr, uint8_t val,
+ Error **errp)
+{
+ERRP_GUARD();
+if (!val) {
+return; /* Disable by default */
+}
+
+if (tcg_enabled()) {
+error_setg(errp, "DAWR1 not supported in TCG.");
+error_append_hint(errp, "Try appending -machine cap-dawr1=off\n");
+} else if (kvm_enabled()) {
+if (!kvmppc_has_cap_dawr1()) {
+error_setg(errp, "DAWR1 not supported by KVM.");
+error_append_hint(errp, "Try appending -machine cap-dawr1=off\n");
+} else if (kvmppc_set_cap_dawr1(val) < 0) {
+error_setg(errp, "Error enabling cap-dawr1 with KVM.");
+error_append_hint(errp, "Try appending -machine cap-dawr1=off\n");
+}
+}
+}
+
SpaprCapabilityInfo capability_table[SPAPR_CAP_NUM] = {
[SPAPR_CAP_HTM] = {
.name = "htm",
@@ -781,6 +803,15 @@ SpaprCapabilityInfo capability_table[SPAPR_CAP_NUM] = {
.type = "bool",
.apply = cap_ail_mode_3_apply,
},
+[SPAPR_CAP_DAWR1] = {
+.name = "dawr1",
+.description = "Allow 2nd Data Address Watchpoint Register (DAWR1)",
+.index = SPAPR_CAP_DAWR1,
+.get = spapr_cap_get_bool,
+.set = spapr_cap_set_bool,
+.type = "bool",
+.apply = cap_dawr1_apply,
+},
};
static SpaprCapabilities default_caps_with_cpu(SpaprMachineState *spapr,
@@ -923,6 +954,7 @@ SPAPR_CAP_MIG_STATE(large_decr,
SPAPR_CAP_LARGE_DECREMENTER);
SPAPR_CAP_MIG_STATE(ccf_assist, SPAPR_CAP_CCF_ASSIST);
SPAPR_CAP_MIG_STATE(fwnmi, SPAPR_CAP_FWNMI);
SPAPR_CAP_MIG_STATE(rpt_invalidate, SPAPR_CAP_RPT_INVALIDATE);
+SPAPR_CAP_MIG_STATE(dawr1, SPAPR_CAP_DAWR1);
void spapr_caps_init(SpaprMachineState *spapr)
{
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 538b2dfb89..47fffb921a 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -80,8 +80,10 @@ typedef enum {
#define SPAPR_CAP_RPT_INVALIDATE0x0B
/* Support for AIL modes */
#define SPAPR_CAP_AIL_MODE_30x0C
+/* DAWR1 */
+#
[PULL 06/60] target/ppc: Tidy POWER book4 SPR registration
From: Nicholas Piggin
POWER book4 (implementation-specific) SPRs are sometimes in their own
functions, but in other cases are mixed with architected SPRs. Do some
spring cleaning on these.
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
Message-ID: <20230625120317.13877-2-npig...@gmail.com>
Signed-off-by: Daniel Henrique Barboza
---
target/ppc/cpu_init.c | 82 +--
1 file changed, 55 insertions(+), 27 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index aeff71d063..dc93581dd3 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -5370,31 +5370,6 @@ static void register_book3s_ids_sprs(CPUPPCState *env)
&spr_read_generic, SPR_NOACCESS,
&spr_read_generic, NULL,
0x);
-spr_register_hv(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x);
-spr_register_hv(env, SPR_TSCR, "TSCR",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic32,
- 0x);
-spr_register_hv(env, SPR_HMER, "HMER",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_hmer,
- 0x);
-spr_register_hv(env, SPR_HMEER, "HMEER",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x);
-spr_register_hv(env, SPR_TFMR, "TFMR",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x);
spr_register_hv(env, SPR_LPIDR, "LPIDR",
SPR_NOACCESS, SPR_NOACCESS,
SPR_NOACCESS, SPR_NOACCESS,
@@ -5656,14 +5631,60 @@ static void register_power8_ic_sprs(CPUPPCState *env)
#endif
}
+/* SPRs specific to IBM POWER CPUs */
+static void register_power_common_book4_sprs(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+spr_register_hv(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x);
+spr_register_hv(env, SPR_TSCR, "TSCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic32,
+ 0x);
+spr_register_hv(env, SPR_HMER, "HMER",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_hmer,
+ 0x);
+spr_register_hv(env, SPR_HMEER, "HMEER",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x);
+spr_register_hv(env, SPR_TFMR, "TFMR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x);
+#endif
+}
+
+static void register_power9_book4_sprs(CPUPPCState *env)
+{
+/* Add a number of P9 book4 registers */
+register_power_common_book4_sprs(env);
+#if !defined(CONFIG_USER_ONLY)
+spr_register_kvm(env, SPR_WORT, "WORT",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_WORT, 0);
+#endif
+}
+
static void register_power8_book4_sprs(CPUPPCState *env)
{
/* Add a number of P8 book4 registers */
+register_power_common_book4_sprs(env);
#if !defined(CONFIG_USER_ONLY)
spr_register_kvm(env, SPR_ACOP, "ACOP",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
KVM_REG_PPC_ACOP, 0);
+/* PID is only in BookE in ISA v2.07 */
spr_register_kvm(env, SPR_BOOKS_PID, "PID",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_pidr,
@@ -5679,10 +5700,12 @@ static void register_power7_book4_sprs(CPUPPCState *env)
{
/* Add a number of P7 book4 registers */
#if !defined(CONFIG_USER_ONLY)
+register_power_common_book4_sprs(env);
spr_register_kvm(env, SPR_ACOP, "ACOP",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
KVM_REG_PPC_ACOP, 0);
+/* PID is only in BookE in ISA v2.06 */
spr_register_kvm(env, SPR_BOOKS_PID, "PID",
SPR_NOACCESS, SPR_NOACCESS,
[PULL 44/60] ppc440_pcix: Don't use iomem for regs
From: BALATON Zoltan
The iomem memory region is better used for the PCI IO space but
currently used for registers. Stop using it for that to allow this to
be cleaned up in the next patch.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
Message-ID:
<3def68f200edd4540393d6b3b03baabe15d649f2.1688586835.git.bala...@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/ppc440_pcix.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/ppc440_pcix.c b/hw/ppc/ppc440_pcix.c
index f10f93c533..899558b055 100644
--- a/hw/ppc/ppc440_pcix.c
+++ b/hw/ppc/ppc440_pcix.c
@@ -64,6 +64,7 @@ struct PPC440PCIXState {
MemoryRegion container;
MemoryRegion iomem;
MemoryRegion busmem;
+MemoryRegion regs;
};
#define PPC440_REG_BASE 0x8
@@ -507,11 +508,11 @@ static void ppc440_pcix_realize(DeviceState *dev, Error
**errp)
h, "pci-conf-idx", 4);
memory_region_init_io(&h->data_mem, OBJECT(s), &pci_host_data_le_ops,
h, "pci-conf-data", 4);
-memory_region_init_io(&s->iomem, OBJECT(s), &pci_reg_ops, s,
- "pci.reg", PPC440_REG_SIZE);
+memory_region_init_io(&s->regs, OBJECT(s), &pci_reg_ops, s, "pci-reg",
+ PPC440_REG_SIZE);
memory_region_add_subregion(&s->container, PCIC0_CFGADDR, &h->conf_mem);
memory_region_add_subregion(&s->container, PCIC0_CFGDATA, &h->data_mem);
-memory_region_add_subregion(&s->container, PPC440_REG_BASE, &s->iomem);
+memory_region_add_subregion(&s->container, PPC440_REG_BASE, &s->regs);
sysbus_init_mmio(sbd, &s->container);
}
--
2.41.0
[PULL 54/60] target/ppc: Reorder #ifdef'ry in kvm_ppc.h
From: Philippe Mathieu-Daudé
Keep a single if/else/endif block checking CONFIG_KVM.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Cédric Le Goater
Message-ID: <20230627115124.19632-3-phi...@linaro.org>
Signed-off-by: Daniel Henrique Barboza
---
target/ppc/kvm_ppc.h | 62
1 file changed, 28 insertions(+), 34 deletions(-)
diff --git a/target/ppc/kvm_ppc.h b/target/ppc/kvm_ppc.h
index 2e395416f0..49954a300b 100644
--- a/target/ppc/kvm_ppc.h
+++ b/target/ppc/kvm_ppc.h
@@ -93,7 +93,34 @@ void kvmppc_set_reg_tb_offset(PowerPCCPU *cpu, int64_t
tb_offset);
int kvm_handle_nmi(PowerPCCPU *cpu, struct kvm_run *run);
-#else
+#define kvmppc_eieio() \
+do { \
+if (kvm_enabled()) { \
+asm volatile("eieio" : : : "memory"); \
+} \
+} while (0)
+
+/* Store data cache blocks back to memory */
+static inline void kvmppc_dcbst_range(PowerPCCPU *cpu, uint8_t *addr, int len)
+{
+uint8_t *p;
+
+for (p = addr; p < addr + len; p += cpu->env.dcache_line_size) {
+asm volatile("dcbst 0,%0" : : "r"(p) : "memory");
+}
+}
+
+/* Invalidate instruction cache blocks */
+static inline void kvmppc_icbi_range(PowerPCCPU *cpu, uint8_t *addr, int len)
+{
+uint8_t *p;
+
+for (p = addr; p < addr + len; p += cpu->env.icache_line_size) {
+asm volatile("icbi 0,%0" : : "r"(p));
+}
+}
+
+#else /* !CONFIG_KVM */
static inline uint32_t kvmppc_get_tbfreq(void)
{
@@ -440,10 +467,6 @@ static inline bool
kvmppc_pvr_workaround_required(PowerPCCPU *cpu)
return false;
}
-#endif
-
-#ifndef CONFIG_KVM
-
#define kvmppc_eieio() do { } while (0)
static inline void kvmppc_dcbst_range(PowerPCCPU *cpu, uint8_t *addr, int len)
@@ -454,35 +477,6 @@ static inline void kvmppc_icbi_range(PowerPCCPU *cpu,
uint8_t *addr, int len)
{
}
-#else /* CONFIG_KVM */
-
-#define kvmppc_eieio() \
-do { \
-if (kvm_enabled()) { \
-asm volatile("eieio" : : : "memory"); \
-} \
-} while (0)
-
-/* Store data cache blocks back to memory */
-static inline void kvmppc_dcbst_range(PowerPCCPU *cpu, uint8_t *addr, int len)
-{
-uint8_t *p;
-
-for (p = addr; p < addr + len; p += cpu->env.dcache_line_size) {
-asm volatile("dcbst 0,%0" : : "r"(p) : "memory");
-}
-}
-
-/* Invalidate instruction cache blocks */
-static inline void kvmppc_icbi_range(PowerPCCPU *cpu, uint8_t *addr, int len)
-{
-uint8_t *p;
-
-for (p = addr; p < addr + len; p += cpu->env.icache_line_size) {
-asm volatile("icbi 0,%0" : : "r"(p));
-}
-}
-
#endif /* CONFIG_KVM */
#endif /* KVM_PPC_H */
--
2.41.0
Re: [PATCH 0/6] qemu-img: rebase: add compression support
On 6/30/23 13:54, Denis V. Lunev wrote: > On 6/1/23 21:28, Andrey Drobyshev wrote: >> This series is adding [-c | --compress] option to "qemu-img rebase" >> command, which might prove useful for saving some disk space when, for >> instance, manipulating chains of backup images. Along the way I had to >> make a couple of minor improvements. >> >> The first 2 patches are a bug fix + corresponding test case. >> Patch 3 merely fixes wrong args used in allocation. >> Patch 4 makes write requests during rebase operation >> cluster_size-aligned, >> which seems to be beneficial for both non-compressed and compressed mode. >> The last 2 patches are the actual feature implementation + tests. >> >> Andrey Drobyshev (6): >> qemu-img: rebase: stop when reaching EOF of old backing file >> qemu-iotests: 024: add rebasing test case for overlay_size > >> backing_size >> qemu-img: rebase: use backing files' BlockBackend for buffer alignment >> qemu-img: rebase: avoid unnecessary COW operations >> qemu-img: add compression option to rebase subcommand >> iotests: add test 314 for "qemu-img rebase" with compression >> >> docs/tools/qemu-img.rst | 6 +- >> qemu-img-cmds.hx | 4 +- >> qemu-img.c | 106 ++-- >> tests/qemu-iotests/024 | 57 + >> tests/qemu-iotests/024.out | 30 +++ >> tests/qemu-iotests/314 | 165 + >> tests/qemu-iotests/314.out | 75 + >> 7 files changed, 415 insertions(+), 28 deletions(-) >> create mode 100755 tests/qemu-iotests/314 >> create mode 100644 tests/qemu-iotests/314.out >> > ping Friendly ping
[PULL 57/60] target/ppc: Restrict 'kvm_ppc.h' to sysemu in cpu_init.c
From: Philippe Mathieu-Daudé User emulation shouldn't need any of the KVM prototypes declared in "kvm_ppc.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater Reviewed-by: Greg Kurz Message-ID: <20230627115124.19632-6-phi...@linaro.org> Signed-off-by: Daniel Henrique Barboza --- target/ppc/cpu_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 6ac1765a8d..02b7aad9b0 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -21,7 +21,6 @@ #include "qemu/osdep.h" #include "disas/dis-asm.h" #include "gdbstub/helpers.h" -#include "kvm_ppc.h" #include "sysemu/cpus.h" #include "sysemu/hw_accel.h" #include "sysemu/tcg.h" @@ -49,6 +48,7 @@ #ifndef CONFIG_USER_ONLY #include "hw/boards.h" #include "hw/intc/intc.h" +#include "kvm_ppc.h" #endif /* #define PPC_DEBUG_SPR */ -- 2.41.0
[PULL 53/60] target/ppc: Have 'kvm_ppc.h' include 'sysemu/kvm.h'
From: Philippe Mathieu-Daudé "kvm_ppc.h" declares: int kvm_handle_nmi(PowerPCCPU *cpu, struct kvm_run *run); 'struct kvm_run' is declared in "sysemu/kvm.h", include it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Greg Kurz Reviewed-by: Cédric Le Goater Message-ID: <20230627115124.19632-2-phi...@linaro.org> Signed-off-by: Daniel Henrique Barboza --- target/ppc/kvm_ppc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/ppc/kvm_ppc.h b/target/ppc/kvm_ppc.h index 611debc3ce..2e395416f0 100644 --- a/target/ppc/kvm_ppc.h +++ b/target/ppc/kvm_ppc.h @@ -9,6 +9,7 @@ #ifndef KVM_PPC_H #define KVM_PPC_H +#include "sysemu/kvm.h" #include "exec/hwaddr.h" #include "cpu.h" -- 2.41.0
[PULL 34/60] tests/avocado: Add powernv machine test script
From: Nicholas Piggin
This copies ppc_pseries.py to start a set of powernv tests, including
a Linux boot test for the newly added SMT mode.
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
Message-ID: <20230705120631.27670-5-npig...@gmail.com>
Signed-off-by: Daniel Henrique Barboza
---
tests/avocado/ppc_powernv.py | 87
1 file changed, 87 insertions(+)
create mode 100644 tests/avocado/ppc_powernv.py
diff --git a/tests/avocado/ppc_powernv.py b/tests/avocado/ppc_powernv.py
new file mode 100644
index 00..d0e5c07bde
--- /dev/null
+++ b/tests/avocado/ppc_powernv.py
@@ -0,0 +1,87 @@
+# Test that Linux kernel boots on ppc powernv machines and check the console
+#
+# Copyright (c) 2018, 2020 Red Hat, Inc.
+#
+# This work is licensed under the terms of the GNU GPL, version 2 or
+# later. See the COPYING file in the top-level directory.
+
+from avocado.utils import archive
+from avocado_qemu import QemuSystemTest
+from avocado_qemu import wait_for_console_pattern
+
+class powernvMachine(QemuSystemTest):
+
+timeout = 90
+KERNEL_COMMON_COMMAND_LINE = 'printk.time=0 '
+panic_message = 'Kernel panic - not syncing'
+good_message = 'VFS: Cannot open root device'
+
+def do_test_linux_boot(self):
+self.require_accelerator("tcg")
+kernel_url = ('https://archives.fedoraproject.org/pub/archive'
+ '/fedora-secondary/releases/29/Everything/ppc64le/os'
+ '/ppc/ppc64/vmlinuz')
+kernel_hash = '3fe04abfc852b66653b8c3c897a59a689270bc77'
+kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash)
+
+self.vm.set_console()
+kernel_command_line = self.KERNEL_COMMON_COMMAND_LINE + 'console=hvc0'
+self.vm.add_args('-kernel', kernel_path,
+ '-append', kernel_command_line)
+self.vm.launch()
+
+def test_linux_boot(self):
+"""
+:avocado: tags=arch:ppc64
+:avocado: tags=machine:powernv
+:avocado: tags=accel:tcg
+"""
+
+self.do_test_linux_boot()
+console_pattern = 'VFS: Cannot open root device'
+wait_for_console_pattern(self, console_pattern, self.panic_message)
+
+def test_linux_smp_boot(self):
+"""
+:avocado: tags=arch:ppc64
+:avocado: tags=machine:powernv
+:avocado: tags=accel:tcg
+"""
+
+self.vm.add_args('-smp', '4')
+self.do_test_linux_boot()
+console_pattern = 'smp: Brought up 1 node, 4 CPUs'
+wait_for_console_pattern(self, console_pattern, self.panic_message)
+wait_for_console_pattern(self, self.good_message, self.panic_message)
+
+def test_linux_smt_boot(self):
+"""
+:avocado: tags=arch:ppc64
+:avocado: tags=machine:powernv
+:avocado: tags=accel:tcg
+"""
+
+self.vm.add_args('-smp', '4,threads=4')
+self.do_test_linux_boot()
+console_pattern = 'CPU maps initialized for 4 threads per core'
+wait_for_console_pattern(self, console_pattern, self.panic_message)
+console_pattern = 'smp: Brought up 1 node, 4 CPUs'
+wait_for_console_pattern(self, console_pattern, self.panic_message)
+wait_for_console_pattern(self, self.good_message, self.panic_message)
+
+def test_linux_big_boot(self):
+"""
+:avocado: tags=arch:ppc64
+:avocado: tags=machine:powernv
+:avocado: tags=accel:tcg
+"""
+
+self.vm.add_args('-smp', '16,threads=4,cores=2,sockets=2')
+
+# powernv does not support NUMA
+self.do_test_linux_boot()
+console_pattern = 'CPU maps initialized for 4 threads per core'
+wait_for_console_pattern(self, console_pattern, self.panic_message)
+console_pattern = 'smp: Brought up 2 nodes, 16 CPUs'
+wait_for_console_pattern(self, console_pattern, self.panic_message)
+wait_for_console_pattern(self, self.good_message, self.panic_message)
--
2.41.0
